**Proof.** This is Theorem VIII in [31].

Since our work involves analytic functions defined on the complex plane, we find it useful to define the domain

$$\mathbb{D} := \mathbb{C} \backslash \mathbb{R}\_0^-,\tag{11}$$

namely the complex plane slit along a branch cut from the origin. This is used as a domain for various complex power functions and other related functions.

Our first main result is a fractional identity between the Mittag–Leffler functions with two and three parameters as defined by Equations (6) and (7). This is motivated by previous work (e.g., [32]), in which gamma functions that appear in infinite power series can be interpreted as arising from fractional differintegrals. After submitting the paper, we realised that this result was previously proved in [33]. However, our original proof is preserved below.

**Proposition 1.** *For any α*, *β*, *ρ* ∈ C *with* Re(*α*), Re(*β*) > 0*, we have:*

$$E\_{a,\beta}^{\rho}(z) = \frac{1}{\Gamma(\rho)} \, ^{RL}\_0 D\_z^{\rho-1} \left[ z^{\rho-1} E\_{a,\beta}(z) \right], \qquad z \in \mathbb{D}. \tag{12}$$

**Proof.** First, Lemma 1 tells us that a quotient of gamma functions can very often be interpreted as arising from a fractional differintegral of a power function. In this case, the expression Γ(*ρ*+*n*) *n*! appearing in the coefficients of the series in Equation (7) gives rise to the following:

$$\begin{split} E\_{a,\beta}^{\rho}(z) &= \sum\_{n=0}^{\infty} \frac{\Gamma(\rho+n)z^{n}}{\Gamma(\rho)\Gamma(n\alpha+\beta)n!} = \sum\_{n=0}^{\infty} \frac{1}{\Gamma(n\alpha+\beta)\Gamma(\rho)} \cdot \frac{\Gamma(\rho+n)}{\Gamma(n+1)} z^{n} \\ &= \sum\_{n=0}^{\infty} \frac{1}{\Gamma(n\alpha+\beta)\Gamma(\rho)} \cdot \,\_0^{RL}D\_{z}^{\rho-1} \left[ z^{n+\rho-1} \right] = \frac{1}{\Gamma(\rho)} \sum\_{n=0}^{\infty} \,\_0^{RL}D\_{z}^{\rho-1} \left[ \frac{z^{n+\rho-1}}{\Gamma(n\alpha+\beta)} \right] .\end{split}$$

Since the series here is uniformly convergent, we can use the result of Lemma 2 to swap the summation with the fractional differintegration. This gives:

$$\begin{split} E\_{a,\beta}^{\rho}(z) &= \frac{1}{\Gamma(\rho)} \sum\_{n=0}^{\infty} \, ^{RL}\_{0}D\_{z}^{\rho-1} \left[ \frac{z^{n+\rho-1}}{\Gamma(n\alpha+\beta)} \right] = \frac{1}{\Gamma(\rho)} \, ^{RL}\_{0}D\_{z}^{\rho-1} \left[ \sum\_{n=0}^{\infty} \frac{z^{n+\rho-1}}{\Gamma(n\alpha+\beta)} \right] \\ &= \frac{1}{\Gamma(\rho)} \, ^{RL}\_{0}D\_{z}^{\rho-1} \left[ z^{\rho-1} \sum\_{n=0}^{\infty} \frac{z^{n}}{\Gamma(n\alpha+\beta)} \right] = \frac{1}{\Gamma(\rho)} \, ^{RL}\_{0}D\_{z}^{\rho-1} \left[ z^{\rho-1} E\_{a,\beta}(z) \right], \end{split}$$

and we have the result desired.

Note that, by setting *ρ* = 1 in Equation (12), we recover the trivial identity *E*1 *α*,*β*(*z*) = *Eα*,*β*(*z*).

**Corollary 1.** *For any α*, *ρ* ∈ C *with* Re(*α*) > 0*, we have:*

$$E\_{a,1}^{\rho}(z) = \frac{1}{\Gamma(\rho)} \, \, ^{RL}\_0 D\_z^{\rho-1} \left[ z^{\rho-1} E\_a(z) \right], \qquad z \in \mathbb{D}. \tag{13}$$

**Proof.** This follows immediately by setting *β* = 1 in Proposition 1.

**Remark 1.** *By exactly the same argument as in Proposition 1, we can show that*

$$E\_{a,\beta}^{\rho}(\gamma z) = \frac{1}{\Gamma(\rho)} \, ^{RL}\_0 D\_z^{\rho - 1} \left[ z^{\rho - 1} E\_{a,\beta}(\gamma z) \right], \qquad z \in \mathbb{D}, \tag{14}$$

*for any α*, *β*, *γ*, *ρ* ∈ C *with* Re(*α*), Re(*β*) > 0*. The proof is as above with an extra factor of γn included in each term of the sum.*

We have now established a relation between the Mittag–Leffler functions of two and three parameters, and hence a relation between the Mittag–Leffler function of one parameter and the function *Eρ α*,1(*z*). However, in order to find a connection with the AB model, we need to consider not the function *Eα*(*x*) but rather the function *Eα* −*α* 1−*α xα* , which appears in the kernel of the definition in Equation (9). To this end, we note the following result, which is seen in (Equation (7.1), [12]) but without reference to fractional calculus.

**Proposition 2.** *For any α*, *β*, *γ* ∈ C *with* Re(*α*), Re(*β*) > 0*, we have:*

$$E\_{\mathfrak{a},\mathfrak{\beta}}\left(\gamma z^{\mathfrak{a}}\right) = z^{1-\mathfrak{\beta}} \, ^{RL}\_{0}D\_{z}^{1-\mathfrak{\beta}}\left[E\_{\mathfrak{a}}\left(\gamma z^{\mathfrak{a}}\right)\right], \qquad z \in \mathbb{D}.\tag{15}$$

.

**Proof.** This time we start from the right-hand side of the desired identity, and use the definition in Equation (5) of the function *Eα*:

$$z^{1-\beta} \, \_0^{RL} D\_z^{1-\beta} \left[ E\_a \left( \gamma z^a \right) \right] = z^{1-\beta} \, \_0^{RL} D\_z^{1-\beta} \left[ \sum\_{n=0}^{\infty} \frac{\gamma^n z^{\alpha n}}{\Gamma(n\alpha + 1)} \right]$$

This series is uniformly convergent, thus, by Lemma 2, we can swap the summation and fractional differintegration provided that (at least in the case 0 < Re(*β*) < 1) the resulting series also converges uniformly. We swap the operations now and justify this assumption at the end.

$$\begin{split} z^{1-\beta} \, ^{RL}\_{0}D\_{z}^{1-\beta} \left[ E\_{\mathfrak{a}} \left( \gamma z^{\mathfrak{a}} \right) \right] &= z^{1-\beta} \sum\_{n=0}^{\infty} \, ^{RL}\_{0}D\_{z}^{1-\beta} \left[ \frac{\gamma^{n} z^{an}}{\Gamma(na+1)} \right] \\ &= z^{1-\beta} \sum\_{n=0}^{\infty} \frac{\Gamma(an+1)}{\Gamma(an+\beta)} \cdot \frac{\gamma^{n} z^{an+\beta-1}}{\Gamma(na+1)} \\ &= \sum\_{n=0}^{\infty} \frac{\gamma^{n} z^{an}}{\Gamma(an+\beta)} . \end{split}$$

This series converges uniformly, being precisely the series expression in Equation (6) for *Eα*,*β* (*γzα*). Thus, our swapping of operations above was justified, and the proof is complete.

The key point here is that the dependence of the Mittag–Leffler function in Equation (7) on the parameters *ρ* and *β* can be encoded by fractional differintegrals. Proposition 1 enables us to interpret the parameter *ρ* as merely the order of a differintegral, and Proposition 2 enables us to do the same with *β*.

By combining the results of Proposition 1 and Proposition 2, it is possible to obtain a composite expression for the three-parameter Mittag–Leffler function in Equation (7) in terms of fractional-type integrals, as described by the following theorem.

**Theorem 1.** *For any α*, *β*, *γ*, *ρ* ∈ C *with* Re(*α*), Re(*β*) > 0 *and* Re(*ρ*) < 1*, we have:*

$$E\_{a,\beta}^{\rho}(\gamma z^a) = \frac{a\sin(\pi\rho)}{\pi} \int\_0^z (z^a - u^a)^{-\rho} u^{a\rho - \beta} \, \_0^{\mathbb{R}I} D\_u^{1-\beta} \left[ \mathcal{E}\_a \left( \gamma u^a \right) \right] \, \mathrm{d}u, \qquad z \in \mathbb{D}.\tag{16}$$

**Proof.** For Re(*ρ*) < 1, the fractional differintegrals appearing in Proposition 1 and Corollary 1 are *integrals* (because Re(*ρ* − 1) < 0), and so Equation (14) can be rewritten as follows:

$$E\_{a,\emptyset}^{\rho}(\gamma z) = \frac{1}{\Gamma(\rho)} \, ^{RL}\_0 I\_z^{1-\rho} \left[ z^{\rho-1} E\_{a,\emptyset}(\gamma z) \right] = \frac{1}{\Gamma(\rho)\Gamma(1-\rho)} \int\_0^z (z-y)^{-\rho} y^{\rho-1} E\_{a,\emptyset}(\gamma y) \, \mathrm{d}y \, \mathrm{d}z$$

Making the change of variables *u* = *y*1/*α*, and using the reflection formula for the gamma function:

$$\begin{split} E\_{a,\beta}^{\rho}(\gamma z) &= \frac{\sin(\pi \rho)}{\pi} \int\_0^{z^{1/a}} (z - \mu^a)^{-\rho} \, \mu^{a(\rho - 1)} E\_{a,\beta}(\gamma \mu^a) a \mu^{a - 1} \, \mathrm{d}\mu \\ &= \frac{a \sin(\pi \rho)}{\pi} \int\_0^{z^{1/a}} (z - \mu^a)^{-\rho} \, \mu^{a\rho - 1} E\_{a,\beta}(\gamma \mu^a) \, \mathrm{d}\mu. \end{split}$$

Now, we can apply the result of Proposition 2 to the two-parameter Mittag–Leffler function appearing in the integrand of this expression:

$$\begin{split} \mathcal{E}\_{a,\beta}^{\rho}(\gamma z) &= \frac{a\sin(\pi\rho)}{\pi} \int\_{0}^{z^{1/a}} (z - u^{a})^{-\rho} \, u^{a\rho - 1} \Big[ u^{1 - \beta^{\ }Rl} \, \_0^{L} D\_{u}^{1 - \beta^{\ }} \left[ E\_{\mathfrak{a}} \left( \gamma u^{a} \right) \right] \, \mathrm{d}u \\ &= \frac{a\sin(\pi\rho)}{\pi} \int\_{0}^{z^{1/a}} (z - u^{a})^{-\rho} \, u^{a\rho - \beta^{\ }Rl} \, \_0^{L} D\_{u}^{1 - \beta^{\ }} \left[ E\_{\mathfrak{a}} \left( \gamma u^{a} \right) \right] \, \mathrm{d}u. \end{split}$$

Substituting *zα* for *z*:

$$E\_{a,\beta}^{\rho}(\gamma z^a) = \frac{a\sin(\pi\rho)}{\pi} \int\_0^z (z^a - u^a)^{-\rho} u^{a\rho - \beta} \, \_0^{RL} D\_u^{1-\beta} \left[ E\_a \left( \gamma u^a \right) \right] \, \mathrm{d}u.$$

Note that this can almost, but not quite, be expressed as a composition of two fractional differintegrals.

**Corollary 2.** *For any α*, *β*, *γ*, *ρ* ∈ C *with* Re(*α*) > 0*,* Re(*β*) > 1*, and* Re(*ρ*) < 1*, we have:*

$$E\_{a,\beta}^{\rho}(\gamma z^a) = \frac{a\sin(\pi\rho)}{\pi\Gamma(\beta - 1)} \int\_0^z (z^a - u^a)^{-\rho} u^{a\rho - \beta} \int\_0^u (u - t)^{\beta - 2} E\_a\left(\gamma t^a\right) \,\mathrm{d}t \,\mathrm{d}u, \qquad z \in \mathbb{D}.\tag{17}$$

**Proof.** In this case, we have Re(1 − *β*) < 0 and so the fractional differintegral which appears in the integrand of Equation (16) is an *integral*. Thus, we can write

$${}^{RL}\_{0}I\_{\mu}^{\mathbb{R}-1} \left[ E\_{\mathfrak{a}} \left( \gamma \mu^{\mathfrak{a}} \right) \right] = \frac{1}{\Gamma(\beta - 1)} \int\_{0}^{\mathfrak{u}} (\mathfrak{u} - t)^{\beta - 2} E\_{\mathfrak{a}} \left( \gamma t^{\mathfrak{a}} \right) \, \mathrm{d}t \,\omega$$

and substitute this into Equation (16) to find:

$$E\_{a,\beta}^{\rho}(\gamma z^a) = \frac{a\sin(\pi\rho)}{\pi} \int\_0^z (z^a - u^a)^{-\rho} u^{a\rho - \beta} \left[ \frac{1}{\Gamma(\beta - 1)} \int\_0^u (u - t)^{\beta - 2} E\_a(\gamma t^a) \,\mathrm{d}t \right] \,\mathrm{d}u \,\rho$$

which rearranges to the required result.

**Theorem 2.** *The three-parameter Mittag–Leffler function in Equation* (7) *can be written as an integral transform of the one-parameter Mittag–Leffler function in Equation* (5) *in the following way:*

$$E\_{a,\beta}^{\rho}(\gamma z^a) = \frac{a \sin(\pi \rho)}{\pi \Gamma(\beta - 1)} \int\_0^z F\_{a,\beta,\rho}(t; z) E\_a \left(\gamma t^a\right) dt \qquad z \in \mathbb{D},\tag{18}$$

*where we assume α*, *β*, *γ*, *ρ* ∈ C *with* Re(*α*) > 0*,* Re(*β*) > 1*, and* Re(*ρ*) < 1*, and where the function F is defined as*

$$F\_{a,\beta,\rho}(t;z) := \int\_{t}^{z} (z^a - u^a)^{-\rho} \, u^{a\rho - \beta} (u - t)^{\beta - 2} \, \mathrm{d}u. \tag{19}$$

**Proof.** By Fubini's theorem, it is possible to swap the order of the integrals in Equation (17). We have 0 ≤ *u* ≤ *z* and 0 ≤ *t* ≤ *u*, which after swapping is equivalent to 0 ≤ *t* ≤ *z* and *t* ≤ *u* ≤ *z*. We have from Equation (17):

$$\begin{split} E\_{a,\beta}^{\rho}(\gamma z^{a}) &= \frac{a\sin(\pi\rho)}{\pi\Gamma(\beta-1)} \int\_{0}^{z} \int\_{0}^{u} (z^{a} - u^{a})^{-\rho} \, u^{a\rho - \beta} (u - t)^{\beta - 2} E\_{a} \left(\gamma t^{a}\right) \, \mathrm{d}t \, \mathrm{d}u \\ &= \frac{a\sin(\pi\rho)}{\pi\Gamma(\beta-1)} \int\_{0}^{z} \int\_{t}^{z} (z^{a} - u^{a})^{-\rho} \, u^{a\rho - \beta} (u - t)^{\beta - 2} E\_{a} \left(\gamma t^{a}\right) \, \mathrm{d}u \, \mathrm{d}t \\ &= \frac{a\sin(\pi\rho)}{\pi\Gamma(\beta-1)} \int\_{0}^{z} E\_{a} \left(\gamma t^{a}\right) \int\_{t}^{z} (z^{a} - u^{a})^{-\rho} \, u^{a\rho - \beta} (u - t)^{\beta - 2} \, \mathrm{d}u \, \mathrm{d}t \\ &= \frac{a\sin(\pi\rho)}{\pi\Gamma(\beta-1)} \int\_{0}^{z} E\_{a} \left(\gamma t^{a}\right) F\_{a,\beta,\rho}(t; z) \, \mathrm{d}t, \end{split}$$

as required.

Thus, using Riemann–Liouville fractional calculus, we have forged new connections between the Mittag–Leffler functions of one, two and three parameters. The connection between those of one and three parameters, in particular, may give rise to new formulae linking AB fractional calculus with Prabhakar fractional calculus, in a way more profound than simply writing one as a special case of the other.


**5. Expression and regulation of β-defensin-2**

HBD2 is expressed mainly in all the epithelia of human body (respiratory, digestive, urogenital, conjunctive epithelium), mucous, peripheral blood and skin. In the respiratory system, HBD2 is expressed in mucous from the mouth to the epithelium of the lungs and is induced by bacteria, fungi and virus infections and by proinflammatory stimuli such as interleukin 1α (IL-1α), interleukin 1β (IL-1β), tumor necrosis factor alpha (TNF-α), interferon gamma (IFN-γ) and interleukin IL-6 (IL-6) [29, 47–51]. Recently, a study showed that the cytokines IL-17 and IL-22 are produced by Th17 cells, which are reportedly known to regulate the expression of HBD2 on mucosal surfaces [32]. HBD2 is produced as a functionally inactive peptide (prepro-defensin), and to achieve its biological activity, it must go through a post-translational modification process and form a mature peptide. Prepro-defensin is composed of a highly hydrophobic pre-peptide signal, a propeptide and the mature peptide. The prepropeptide is cut by proteases in the Golgi apparatus, and once removed, the mature peptide with antimicrobial activity is secreted on the surface of the epithelial cells [3, 52].

The regulation of the expression of the HBD2 in the respiratory epithelium involves multiple signaling pathways; most of these have been studied with bacterial infections. The bacterial proteins induce the expression of HBD2 in the respiratory epithelium through transcription factors (NF-kB) [53], the myeloid ELF-1-like factor (MEF) [54], the nuclear factor interleukin 6 (NF-IL6) [55] or the activated protein 1–3 (AP1–3) [56]. Signaling pathways involve mitogen-activated protein kinase (MAPKs) [49, 57, 58], phosphatidylinositol-3-kinase (PI3K) and protein kinase C (PKC) [59].

Another form to induce HBD2 expression is through cellular receptors, the respiratory epithelium expresses various receptors on its surface. Toll-like receptors (TLRs) 1–6 are expressed on the epithelial surface, and in the intracellular vesicles, the TLR3 and TLR7–9 are expressed in the endosomes or endoplasmic reticulum. These receptors recognize pathogens and have a cytoplasmic domain that is homologous to the IL-1 receptor and is responsible for initiating intracellular signaling pathways. This signaling cascade includes the activation of NF-kB. This transcription factor promotes the gene expression that contributes to the cytokines, chemokines, adhesion molecules, co-stimulatory molecules release as well as the expression of HBD2 [60].

In a study with lung epithelial cells infected with *L. pneumophila*, it was observed that the infection induces the release of HBD2, and its expression is mediated by the receptors TLR2 and TLR5 and activation of MAPKs (p38, JNK) and transcription factors NF-kB and AP-1 [50, 57, 58, 61].

Another way to regulate the expression of HBD2 is through the interaction with receptors; its chemotactic property was initially discovered in different types of cells such as monocytes, T cells and immature dendritic cells. The activity is carried through the CCR6 receptor binding [32].

Other receptors involved in the regulation of the HBD2 expression are the receptors for vitamin D and protease-coupled receptors (PARs) [62–65].

Nowadays, HBD2 is considered a multifunctional molecule; the ability to bind to several ligands suggests that there may be more receptors and signaling pathways still to be discovered and that may have important biological activities in the immune system.


etching; then, depositing the 60 nm Si buffer on the patterned substrate, a 600 nm Ge layer was grown to achieve the {113}-faceted Ge hollow structures, as shown in Figure 31a. Second, the typical two-step GaAs was grown on the {113}-faceted Ge/Si (001) hollow substrate in Figure 31b. Figure 31c shows the magnification of {113}-faceted Ge and the GaAs interface; few APBs were found at the bottom of the Ge {113} sawtooth structure, but APBs are not observed in the top GaAs layer. Similarly, the {113}-faceted Ge structure can annihilate the APBs at the interface with the {111}-faceted Si structure, which can be considered as a miscut substrate. However, the Ge {113} crystal plane has less miscut than the Si {111} crystal plane, which brings out a trapezoidal shape of APB in ten nanometers of the bottom of the Ge {113}. In following, the 7-µm-thick GaAs layer, which is far beyond the typical value of the cracking thickness, can be grown on the {113}-faceted Ge/Si hollow substrate. They characterized the thermal strain issue by a high-resolution XRD reciprocal space mapping (RSM) performed around (004) and (224) reflections, as shown in Figure 31d,e. From the peak position of RSM, the in-plane strain εk of the GaAs and Ge layer were calculated from the extracted calculation of the in-plane lattice constant and out-of-plane lattice constant of the GaAs and Ge. Compared with the lattice constant of bulk GaAs and Ge, the residual thermal strain of Ge is about 89.8% lower than that of the Ge layer on normal Si substrates [140]. The residual thermal strain of GaAs is 29.4% lower than that of the GaAs layer grown on the Ge/Si template [141]. Their results indicated that this hollow structure plays an essential role in thermal strain reduction. With a 400 nm GaAs deposition, a smooth GaAs surface with a RMS of 0.67 nm was acquired, and a low TDD of 5.7 × 106/cm2 was obtained by following InGaAs/GaAs quantum-well DFLs inserting. GaAs was grown on the {113}-faceted Ge/Si (001) hollow substrate in Figure 31b. Figure 31c shows the magnification of {113}-faceted Ge and the GaAs interface; few APBs were found at the bottom of the Ge {113} sawtooth structure, but APBs are not observed in the top GaAs layer. Similarly, the {113}-faceted Ge structure can annihilate the APBs at the interface with the {111}-faceted Si structure, which can be considered as a miscut substrate. However, the Ge {113} crystal plane has less miscut than the Si {111} crystal plane, which brings out a trapezoidal shape of APB in ten nanometers of the bottom of the Ge {113}. In following, the 7-µm-thick GaAs layer, which is far beyond the typical value of the cracking thickness, can be grown on the {113}-faceted Ge/Si hollow substrate. They characterized the thermal strain issue by a high-resolution XRD reciprocal space mapping (RSM) performed around (004) and (224) reflections, as shown in Figure 31d,e. From the peak position of RSM, the in-plane strain ε‖ of the GaAs and Ge layer were calculated from the extracted calculation of the in-plane lattice constant and out-of-plane lattice constant of the GaAs and Ge. Compared with the lattice constant of bulk GaAs and Ge, the residual thermal strain of Ge is about 89.8% lower than that of the Ge layer on normal Si substrates [140]. The residual thermal strain of GaAs is 29.4% lower than that of the GaAs layer grown on the Ge/Si template [141]. Their results indicated that this hollow structure plays an essential role in thermal strain reduction. With a 400 nm GaAs deposition, a smooth GaAs surface with a RMS of 0.67 nm was acquired, and a low TDD of 5.7 × 106 /cm2 was obtained by following InGaAs/GaAs quantum-well DFLs inserting.

Si materials. However, the compositional buffer layer has some drawbacks, such as several microns in thickness, high cost, and large usage of material. In following, a thinner superlattice (SL) buffer was applied as the strain compensated layer to minimize the thermal crack, and the SL layer can not only facilitate strain relaxation by interaction with misfit dislocations, but also compensate the thermal strain energy from the mis-

Recently, the use of a patterned substrate to minimize the thermal crack was widely developed. As for pre-patterned growth, cracks can be avoided by growth on a small area due to strain relaxation near the pattern edge. As seen from Figure 31, the thermal strain of GaAs is released and attributed to this Si hollow structure; approaches using the Ge on the micropillar patterned Si (001) substrates were also proposed. Zhang et al. [139] grew APB-free GaAs film on employed the {113}-faceted Ge/Si (001) hollow substrate by MBE. First, the fabrication of the {113}-faceted Ge/Si (001) hollow substrate is as follows: the U-shape grating pattern was defined on an on-axis Si (001) substrate by using deep ultraviolet lithography and reactive ion etching; then, depositing the 60 nm Si buffer on the patterned substrate, a 600 nm Ge layer was grown to achieve the {113}-faceted Ge hollow structures, as shown in Figure 31a. Second, the typical two-step

*Nanomaterials* **2022**, *12*, x FOR PEER REVIEW 32 of 48

match of III-V to Si [107,116,136].

**Figure 31.** (**a**) The schematic illustration of the GaAs grown on the Ge/Si hollow substrate; (**b**) Cross-sectional TEM image of 600 nm thick Ge layer grown on the hollow patterned (001) Si; (**c**) Zoom-in HADDF image of the interface at the bottom region; high-resolution XRD reciprocal-space mapping around (**d**) (004) and (**e**) (224). Inset of (**c**) Higher resolution (004) map from triple-axis mode. Reprinted from ref. [139]. **Figure 31.** (**a**) The schematic illustration of the GaAs grown on the Ge/Si hollow substrate; (**b**) Crosssectional TEM image of 600 nm thick Ge layer grown on the hollow patterned (001) Si; (**c**) Zoom-in HADDF image of the interface at the bottom region; high-resolution XRD reciprocal-space mapping around (**d**) (004) and (**e**) (224). Inset of (**c**) Higher resolution (004) map from triple-axis mode. Reprinted with permission from ref. [139].

Although the ART technique discussed above can effectively solve the APB prob-

nique also limits the maximum achievable dimension of III-V epitaxial layers, which are more amenable in some device applications [142]. In order to provide a large film plane for the preparation of III−V devices, the ART technique needs to be continuously optimized so that the SEG III−V materials are epitaxial and grown out of closely spaced trenches, and extend laterally above the oxidation strips until the materials from adjacent grooves merge together to form a continuous high quality epitaxial layer. Recently, an alternative ART technique called Lateral aspect ratio trapping (LART) was developed. As schematically illustrated in Figure 32a, micrometer-scale III–V crystals can be directly grown above the buried oxide layer by this LART method [143]. Compared to the conventional "aspect ratio trapping" approach, the LART approach is changing the direction of the groove, enabling the growth front to the lateral direction. The lateral oxide trenches can be created by dry etch terminated on the buried oxide; then, anisotropic wet etching was processed to form "V" shaped Si. This {111}-oriented Si bevel structure not only prohibits the formation of APBs in the initiating lateral growth of InP layers, but also the propagation of TDD was effectively blocked by the wide lateral SiO2 trenches, which reveal a high "aspect ratio" in the lateral direction. Figure 32b,c shows a tilted-view SEM image of the SEG InP layer grown on (001) SOI substrates using the LART method. Figure 33b shows an InP-epi "wing" grown using the lateral ART approach, and Figure 33c displays the two symmetrical InP-epi wings. From the SEM images, we can see the Si pedestal sandwiched between the top oxide spacer, and the buried oxide layer features two {111}-oriented surfaces. Starting from the nucleation sites provided by the {111} Si facets, the InP crystal evolves laterally along the [110] direction into wing-structures with two {111} facets. The angle between the two {111} facets is around 110° which indicates a zincblende crystal structure Then, the InP stripes continue laterally to grow inside the long nano-scale SOI trenches resulting in dislocation-free InP crystals right atop the buried oxide layer. In addition, the dimension of III–V

4.2.2. Epitaxial Lateral Overgrowth (ELO)

### 4.2.2. Epitaxial Lateral Overgrowth (ELO)

Although the ART technique discussed above can effectively solve the APB problem, and block the propagation of crystalline defects using the groove mask, this technique also limits the maximum achievable dimension of III-V epitaxial layers, which are more amenable in some device applications [142]. In order to provide a large film plane for the preparation of III−V devices, the ART technique needs to be continuously optimized so that the SEG III−V materials are epitaxial and grown out of closely spaced trenches, and extend laterally above the oxidation strips until the materials from adjacent grooves merge together to form a continuous high quality epitaxial layer. Recently, an alternative ART technique called Lateral aspect ratio trapping (LART) was developed. As schematically illustrated in Figure 32a, micrometer-scale III-V crystals can be directly grown above the buried oxide layer by this LART method [143]. Compared to the conventional "aspect ratio trapping" approach, the LART approach is changing the direction of the groove, enabling the growth front to the lateral direction. The lateral oxide trenches can be created by dry etch terminated on the buried oxide; then, anisotropic wet etching was processed to form "V" shaped Si. This {111}-oriented Si bevel structure not only prohibits the formation of APBs in the initiating lateral growth of InP layers, but also the propagation of TDD was effectively blocked by the wide lateral SiO2 trenches, which reveal a high "aspect ratio" in the lateral direction. Figure 32b,c shows a tilted-view SEM image of the SEG InP layer grown on (001) SOI substrates using the LART method. Figure 33b shows an InP-epi "wing" grown using the lateral ART approach, and Figure 33c displays the two symmetrical InP-epi wings. From the SEM images, we can see the Si pedestal sandwiched between the top oxide spacer, and the buried oxide layer features two {111}-oriented surfaces. Starting from the nucleation sites provided by the {111} Si facets, the InP crystal evolves laterally along the [110] direction into wing-structures with two {111} facets. The angle between the two {111} facets is around 110◦ which indicates a zincblende crystal structure Then, the InP stripes continue laterally to grow inside the long nano-scale SOI trenches resulting in dislocation-free InP crystals right atop the buried oxide layer. In addition, the dimension of III-V nano-ridges can be controlled by changing the thickness of the Si layer on SOI, which is limited by the size of photolithography in the conventional ART approach. This in-plane and close placement of the III-V layer with the Si device layer also facilitates the integration of III-V light emitters with Si-based photonic components. *Nanomaterials* **2022**, *12*, x FOR PEER REVIEW 34 of 48 limited by the size of photolithography in the conventional ART approach. This in-plane and close placement of the III–V layer with the Si device layer also facilitates the integration of III–V light emitters with Si-based photonic components.

**Figure 32.** (**a**) The scheme of lateral ART. The red dotted lines denote the confinement of the majority of crystalline defects at the InP/Si interface and the trapping of residual TDs by the top and bottom SiO2 layers. (**b**) Tilted view SEM image of one InP sandwiched between the top oxide spacer and the buried oxide layer. (**c**) Cross-sectional SEM images of two symmetrical InPs grown using the lateral ART approach. Reproduced with permission from ref. [143]. Copyright 2019 American Institute of Physics. **Figure 32.** (**a**) The scheme of lateral ART. The red dotted lines denote the confinement of the majority of crystalline defects at the InP/Si interface and the trapping of residual TDs by the top and bottom SiO2 layers. (**b**) Tilted view SEM image of one InP sandwiched between the top oxide spacer and the buried oxide layer. (**c**) Cross-sectional SEM images of two symmetrical InPs grown using the lateral ART approach. Reproduced with permission from ref. [143]. Copyright 2019 American Institute of Physics.

The above ART methods or lateral ART approach often produce sub-micrometer dimensions of APB-III–V layers, but to expand the dimension of the epitaxial III–V further to tens and even hundreds of micrometers, ART technology needs to be improved. Epitaxial lateral overgrowth (ELO) is an innovative technique to provide large regions of device materials. In the ELO process, a III-V buffer layer is first grown on the Si substrate, then polished by CMP. Microsized SiO2 stripe patterns are selectively etched to The above ART methods or lateral ART approach often produce sub-micrometer dimensions of APB-III-V layers, but to expand the dimension of the epitaxial III-V further to tens and even hundreds of micrometers, ART technology needs to be improved. Epitaxial lateral overgrowth (ELO) is an innovative technique to provide large regions of device materials. In the ELO process, a III-V buffer layer is first grown on the Si substrate, then polished by CMP. Microsized SiO2 stripe patterns are selectively etched to expose the III-V buffer layer for regrowth. Then, the III-V epitaxial layer is vertically regrown through the

expose the III-V buffer layer for regrowth. Then, the III-V epitaxial layer is vertically regrown through the opened region of the mask and thereafter can be laterally grown over

small number of TDs around the opened region will propagate upwards, as shown in Figure 33a. Therefore, a high crystalline quality and thicker layer can be made by this ELO. For the GaAs on Si, there are many pioneering works reported [144,145]. Tsaur et al. [146] first obtained the single-crystal GaAs layers by means of ELO seeded within stripe openings in a SiO2 mask over GaAs layers grown on Ge-coated Si substrates. TEM and scanning cathodoluminescence studies indicated that the laterally overgrown GaAs layers have a dislocation density. However, the early reports on ELO for GaAs-on-Si suffered from the limited defect-free region and the mechanical weakness of the laterally grown parts, both of which became severe as the ELO layer was further grown. In 2015, Yunrui et al. [147] demonstrated that the GaAs coalescence layer grew on the patterned 1.8 μm GaAs buffer layer by epitaxial lateral overgrowth using metal-organic chemical vapor deposition. A 410-nm-thick coalesced ELO GaAs layer was obtained with the low root-mean-square surface roughness of 6.29 nm. Figure 33b,c show the SEM images of the growth and evolution of the ELO GaAs layer on the opening trenches. As shown in Figure 33b, the growth front of GaAs is faceted, with (111) B on both sides and (001) on the top. With the deposition time, the overall 410 nm ELO GaAs layer was shown in

Figure 33c.

**(a)**

ELOG III-V layer

Si substrate III-V seed

Mask

opened region of the mask and thereafter can be laterally grown over the mask. Most of TDs in the buffer layer are blocked by the bottom of the mask, but a small number of TDs around the opened region will propagate upwards, as shown in Figure 33a. Therefore, a high crystalline quality and thicker layer can be made by this ELO. For the GaAs on Si, there are many pioneering works reported [144,145]. Tsaur et al. [146] first obtained the single-crystal GaAs layers by means of ELO seeded within stripe openings in a SiO2 mask over GaAs layers grown on Ge-coated Si substrates. TEM and scanning cathodoluminescence studies indicated that the laterally overgrown GaAs layers have a dislocation density. However, the early reports on ELO for GaAs-on-Si suffered from the limited defect-free region and the mechanical weakness of the laterally grown parts, both of which became severe as the ELO layer was further grown. In 2015, Yunrui et al. [147] demonstrated that the GaAs coalescence layer grew on the patterned 1.8 µm GaAs buffer layer by epitaxial lateral overgrowth using metal-organic chemical vapor deposition. A 410-nm-thick coalesced ELO GaAs layer was obtained with the low root-mean-square surface roughness of 6.29 nm. Figure 33b,c show the SEM images of the growth and evolution of the ELO GaAs layer on the opening trenches. As shown in Figure 33b, the growth front of GaAs is faceted, with (111) B on both sides and (001) on the top. With the deposition time, the overall 410 nm ELO GaAs layer was shown in Figure 33c. al. [146] first obtained the single-crystal GaAs layers by means of ELO seeded within stripe openings in a SiO2 mask over GaAs layers grown on Ge-coated Si substrates. TEM and scanning cathodoluminescence studies indicated that the laterally overgrown GaAs layers have a dislocation density. However, the early reports on ELO for GaAs-on-Si suffered from the limited defect-free region and the mechanical weakness of the laterally grown parts, both of which became severe as the ELO layer was further grown. In 2015, Yunrui et al. [147] demonstrated that the GaAs coalescence layer grew on the patterned 1.8 μm GaAs buffer layer by epitaxial lateral overgrowth using metal-organic chemical vapor deposition. A 410-nm-thick coalesced ELO GaAs layer was obtained with the low root-mean-square surface roughness of 6.29 nm. Figure 33b,c show the SEM images of the growth and evolution of the ELO GaAs layer on the opening trenches. As shown in Figure 33b, the growth front of GaAs is faceted, with (111) B on both sides and (001) on the top. With the deposition time, the overall 410 nm ELO GaAs layer was shown in Figure 33c.

*Nanomaterials* **2022**, *12*, x FOR PEER REVIEW 34 of 48

tion of III–V light emitters with Si-based photonic components.

American Institute of Physics.

**Buried oxide**

**Si**

SiO2 **(a)**

limited by the size of photolithography in the conventional ART approach. This in-plane and close placement of the III–V layer with the Si device layer also facilitates the integra-

**(b) (c)**

**Figure 32.** (**a**) The scheme of lateral ART. The red dotted lines denote the confinement of the majority of crystalline defects at the InP/Si interface and the trapping of residual TDs by the top and bottom SiO2 layers. (**b**) Tilted view SEM image of one InP sandwiched between the top oxide spacer and the buried oxide layer. (**c**) Cross-sectional SEM images of two symmetrical InPs grown using the lateral ART approach. Reproduced with permission from ref. [143]. Copyright 2019

The above ART methods or lateral ART approach often produce sub-micrometer

dimensions of APB-III–V layers, but to expand the dimension of the epitaxial III–V further to tens and even hundreds of micrometers, ART technology needs to be improved. Epitaxial lateral overgrowth (ELO) is an innovative technique to provide large regions of device materials. In the ELO process, a III-V buffer layer is first grown on the Si substrate, then polished by CMP. Microsized SiO2 stripe patterns are selectively etched to expose the III-V buffer layer for regrowth. Then, the III-V epitaxial layer is vertically regrown through the opened region of the mask and thereafter can be laterally grown over the mask. Most of TDs in the buffer layer are blocked by the bottom of the mask, but a small number of TDs around the opened region will propagate upwards, as shown in Figure 33a. Therefore, a high crystalline quality and thicker layer can be made by this ELO. For the GaAs on Si, there are many pioneering works reported [144,145]. Tsaur et

**Figure 33.** (**a**). Schematics of lateral epitaxial overgrowth (ELO); (**b**) cross-sectional SEM images of the films after the first selective growth stage; (**c**) cross-sectional SEM images of the ELO GaAs layer. Reprinted with permission from ref. [147]. Copyright 2015 American Institute of Physics. **Figure 33.** (**a**). Schematics of lateral epitaxial overgrowth (ELO); (**b**) cross-sectional SEM images of the films after the first selective growth stage; (**c**) cross-sectional SEM images of the ELO GaAs layer. Reprinted with permission from ref. [147]. Copyright 2015 American Institute of Physics.

Compared with GaAs-on-Si, ELO techniques are more widely employed [148–150] on InP-on-Si growth, because it is very difficult to obtain low TDDs and large-scale via the direct growth of InP on Si. For the optimization of InP ELO on the (001) Si substrate, Metaferia et al. [151] investigated the ELO of InP from mesh and line openings on the masked InP seed layer on the Si (001) wafer. Their results showed that the coalesced region produced the TDD in a range from 6 × 106 cm−2 to 4 × 107 cm−2 depending on the thickness of the ELO layer. In their work, the ELO InP layer was grown on a 1.5-µm-thick InP/Si substrate with a 40-nm-thick SiO2 mask. The mesh and line masks (opening and masking width of 200 nm and 3 µm, respectively), tilted 15°and 30°off the [110] direction, are compared. The quicker coalescence in the mesh opening resulted in better surface roughness at the early growth stage (~10-µm-thick InP layer), but, after an extended growth (~100 µm-thick InP layer), both mesh and line opening cases exhibited a similar Compared with GaAs-on-Si, ELO techniques are more widely employed [148–150] on InP-on-Si growth, because it is very difficult to obtain low TDDs and large-scale via the direct growth of InP on Si. For the optimization of InP ELO on the (001) Si substrate, Metaferia et al. [151] investigated the ELO of InP from mesh and line openings on the masked InP seed layer on the Si (001) wafer. Their results showed that the coalesced region produced the TDD in a range from 6 × 106 cm−2 to 4 × 107 cm−2 depending on the thickness of the ELO layer. In their work, the ELO InP layer was grown on a 1.5-µm-thick InP/Si substrate with a 40-nm-thick SiO2 mask. The mesh and line masks (opening and masking width of 200 nm and 3 µm, respectively), tilted 15◦and 30◦off the [110] direction, are compared. The quicker coalescence in the mesh opening resulted in better surface roughness at the early growth stage (~10-µm-thick InP layer), but, after an extended growth (~100 µm-thick InP layer), both mesh and line opening cases exhibited a similar surface roughness (RMS roughness of 16~25 nm). It was shown that regardless of both angles (15◦ and 30◦ ) and masks (mesh and line opening), the TDDs were measured to

growth of lasers' structures.

surface roughness (RMS roughness of 16~25 nm). It was shown that regardless of both angles (15°and 30°) and masks (mesh and line opening), the TDDs were measured to be a

be 2~4 × 107 cm −2 and 6~7 × 106 cm−2, respectively. Han et al. [152] displayed two improved ELO strategies to achieve large-dimension III–V materials with a close proximity to the Si substrates in Figure 34. The first scheme is called conformal growth; III-V films lateral selective epitaxial growth starts from III-V seeds on silicon. In the conformal growth scheme [153], after the III-V films were deposited on the Si substrate, a thin layer of the growth mask is then patterned to form the III-V seeds. Then, the regrown III-V stripes were laterally selectively grown along the initial III-V seeds to extend the large dimension size. Another scheme is named corrugated epitaxial lateral overgrowth (CE-LO) [154]; short III–V thin film segments were processed as a III-V seeds by bulk III–V film deposition and patterned; then, a thin patterned oxide mask was deposited on III-V seeds for the following homogenous selective regrowth of the InP process. In both strategies, crystalline defects are confined within the seed mesa, while the laterally overgrown III–V is free of any TDs. Figure 34b shows the cross-sectional SEM in [110] view of CELOG InP on Si; defects are confined in the lateral trenches, and no TDS can be found in the CELOG InP layer. These two improved processes can be used for large-dimension III–V layer manufacturing, which could be furthered processed to the subsequent

be a similar value. The TDD of the 10 µm-thick and 100 µm-thick InP layer was measured to be 2~4 × 107 cm −2 and 6~7 × 106 cm−2 , respectively. Han et al. [152] displayed two improved ELO strategies to achieve large-dimension III-V materials with a close proximity to the Si substrates in Figure 34. The first scheme is called conformal growth; III-V films lateral selective epitaxial growth starts from III-V seeds on silicon. In the conformal growth scheme [153], after the III-V films were deposited on the Si substrate, a thin layer of the growth mask is then patterned to form the III-V seeds. Then, the regrown III-V stripes were laterally selectively grown along the initial III-V seeds to extend the large dimension size. Another scheme is named corrugated epitaxial lateral overgrowth (CELO) [154]; short III-V thin film segments were processed as a III-V seeds by bulk III-V film deposition and patterned; then, a thin patterned oxide mask was deposited on III-V seeds for the following homogenous selective regrowth of the InP process. In both strategies, crystalline defects are confined within the seed mesa, while the laterally overgrown III-V is free of any TDs. Figure 34b shows the cross-sectional SEM in [110] view of CELOG InP on Si; defects are confined in the lateral trenches, and no TDS can be found in the CELOG InP layer. These two improved processes can be used for large-dimension III-V layer manufacturing, which could be furthered processed to the subsequent growth of lasers' structures. *Nanomaterials* **2022**, *12*, x FOR PEER REVIEW 36 of 48

lishing.

**Figure 34.** (**a**) Schematic of two improved ELO process; (**b**) cross-sectional SEM in [110] direction view of CELOG InP on Si. Reprinted with permission from ref. [154]. Copyright 2015 IOP Pub-**Figure 34.** (**a**) Schematic of two improved ELO process; **(b**) cross-sectional SEM in [110] direction view of CELOG InP on Si. Reprinted with permission from ref. [154]. Copyright 2015 IOP Publishing.

Following the above results, in 2020, Omanakuttan et al. [155] fabricated and studied the high crystalline quality of InP by the self-aligned corrugated epitaxial lateral overgrowth (CELOG) method. Figure 35a–d display the InP-seed mesa fabrication process flow. A schematic of the InP-seed mesa was patterned on Si processed for CELOG and is shown in Figure 35e. Through a series of processes: mask deposition, photolithography, and etching, then the CELOG of InP/Si can be obtained by a schematic of Figure 35f. The defective InP seed acts as the CELOG InP growth origination; the threading dislocations propagating from the InP seed can be eliminated by creating dislocation loops for increasing the InP layer thickness. Their results displayed that RMS surface roughness of 2.95 nm obtained for the uniform InP CELOG layer. A higher intensity band edge emission in the cathodoluminescence spectra near-BE band at 892 nm Following the above results, in 2020, Omanakuttan et al. [155] fabricated and studied the high crystalline quality of InP by the self-aligned corrugated epitaxial lateral overgrowth (CELOG) method. Figure 35a–d display the InP-seed mesa fabrication process flow. A schematic of the InP-seed mesa was patterned on Si processed for CELOG and is shown in Figure 35e. Through a series of processes: mask deposition, photolithography, and etching, then the CELOG of InP/Si can be obtained by a schematic of Figure 35f. The defective InP seed acts as the CELOG InP growth origination; the threading dislocations propagating from the InP seed can be eliminated by creating dislocation loops for increasing the InP layer thickness. Their results displayed that RMS surface roughness of 2.95 nm obtained for the uniform InP CELOG layer. A higher intensity band edge emission in the cathodoluminescence spectra near-BE band at 892 nm (1.39 eV) and enhanced carrier lifetime (710 ps) of InP are observed above the CELO InP/Si interface compared to the defective seed InP layer on Si, which are attributed to the reduced TDD realized (~3 × 108 cm−2 ) by the CELO

(1.39 eV) and enhanced carrier lifetime (710 ps) of InP are observed above the CELO

reduced TDD realized (~3 × 108 cm−2) by the CELO method. For the application of the photonic integrated circuit (PIC), a large dimension and uniform InP layer with ultralow dislocation on Si are desired. The CELOG can be extended to the formation of other large

dimensions of III-V/Si heterostructures.

method. For the application of the photonic integrated circuit (PIC), a large dimension and uniform InP layer with ultralow dislocation on Si are desired. The CELOG can be extended to the formation of other large dimensions of III-V/Si heterostructures. *Nanomaterials* **2022**, *12*, x FOR PEER REVIEW 37 of 48

**Figure 35.** (**a**–**d**) Process of InP-seed mesa fabrication for CELO; (**e**) Schematic of the InP-seed mesa pattern on Si before CELO. The thickness of InP-seed layer is 2 μm, and the distance between the two adjacent circular rings of diameter 30 μm is 5 μm; (**f**) Schematic of the CELO InP/Si cross-section. Reprinted from ref. [155]. **Figure 35.** (**a**–**d**) Process of InP-seed mesa fabrication for CELO; (**e**) Schematic of the InP-seed mesa pattern on Si before CELO. The thickness of InP-seed layer is 2 µm, and the distance between the two adjacent circular rings of diameter 30 µm is 5 µm; (**f**) Schematic of the CELO InP/Si cross-section. Reprinted with permission from ref. [155].

In the laterally grown parts, propagating defects such as threading dislocations and stacking faults will be blocked by the mask and consequently cannot propagate into the layer above the mask. ELOG was used to grow GaN [156], as well as InGaAs [157] on Si. In the laterally grown parts, propagating defects such as threading dislocations and stacking faults will be blocked by the mask and consequently cannot propagate into the layer above the mask. ELOG was used to grow GaN [156], as well as InGaAs [157] on Si.

The InAs semiconductor material is a very good candidate for ultra-high-speed electronic and optoelectronic devices, due to its narrow band gap, small electron effective mass, and very high electron mobility (~33,000 cm2 /V s at 300 K). However, the large epitaxial strain generated by the high lattice mismatch (11.4%) and the difference in thermal expansion between InAs and Si, leads to a roughness surface and high TDD, which degrade the electrical and optical properties. At present, growth of thin-film InAs is usually difficult, but direct growth of vertical nanowires can usually accommodate a larger lattice mismatch as compared to thin-film growth [158]. Regarding InAs nanowires, various strategies including vertical VLS growth [159], vertical SEG growth [160,161] have been proposed. Among these techniques, vertical VLS growth has an obvious disadvantage: using Au as the catalyst leads to the formation of deep-level traps with silicon and degrades the device performance, which makes it forbidden in the CMOS fabrication process, so vertical SAE growth was widely developed. In the process of InAs NWs' growth, the morphology of NWs is essential to homogeneous optical and electrical properties. Hertenberge et al. [160] obtained very high yields of ~90 percent of vertically (111)-oriented InAs nanowires selectively grown on the patterned Si(111) substrate. Then, Bjork et al. [161] studied (111)Si (axial) and (1-10)Si (radial) growth of InAs NWs by varying growth duration, temperature, group-III molar flows, V/III ratio, mask material, mask opening size, and inter-wire distance. To achieve uniform nucleation and a high vertical yield of wires, an As-terminated surface and an optimized TMIn flow and V/III ratio are required. Below 520 °C and 540 °C, respectively, the <111> and the <1-10> growth is surface kinetically limited. Their results also indicated that by placing wires in large arrays, it is possible to stop the <1-10> growth rate completely in favor of the <111> growth rate. Recently, Grégoire et al. [162] report that the vertical and high aspect ratio InAs NWs with a hexagonal shape were grown on both GaAs (111)B and Si(111) pat-The InAs semiconductor material is a very good candidate for ultra-high-speed electronic and optoelectronic devices, due to its narrow band gap, small electron effective mass, and very high electron mobility (~33,000 cm2/V s at 300 K). However, the large epitaxial strain generated by the high lattice mismatch (11.4%) and the difference in thermal expansion between InAs and Si, leads to a roughness surface and high TDD, which degrade the electrical and optical properties. At present, growth of thin-film InAs is usually difficult, but direct growth of vertical nanowires can usually accommodate a larger lattice mismatch as compared to thin-film growth [158]. Regarding InAs nanowires, various strategies including vertical VLS growth [159], vertical SEG growth [160,161] have been proposed. Among these techniques, vertical VLS growth has an obvious disadvantage: using Au as the catalyst leads to the formation of deep-level traps with silicon and degrades the device performance, which makes it forbidden in the CMOS fabrication process, so vertical SAE growth was widely developed. In the process of InAs NWs' growth, the morphology of NWs is essential to homogeneous optical and electrical properties. Hertenberge et al. [160] obtained very high yields of ~90 percent of vertically (111)-oriented InAs nanowires selectively grown on the patterned Si(111) substrate. Then, Bjork et al. [161] studied (111)Si (axial) and (1-10)Si (radial) growth of InAs NWs by varying growth duration, temperature, group-III molar flows, V/III ratio, mask material, mask opening size, and inter-wire distance. To achieve uniform nucleation and a high vertical yield of wires, an As-terminated surface and an optimized TMIn flow and V/III ratio are required. Below 520 ◦C and 540 ◦C, respectively, the <111> and the <1-10> growth is surface kinetically limited. Their results also indicated that by placing wires in large arrays, it is possible to stop the <1-10> growth rate completely in favor of the <111> growth rate. Recently, Grégoire et al. [162] report that the vertical and high aspect ratio InAs NWs with a hexagonal shape were grown on both GaAs (111)B and Si(111) patterned substrates by selective epitaxial growth (SEG). The

terned substrates by selective epitaxial growth (SEG). The morphology and the quality

GaAs(111)B in Figure 36a, a strong peak at 0.445 eV with a full width at half-maximum

morphology and the quality of InAs NWs' arrays grown on GaAs(111)B and Si(111) were characterized by SEM and photoluminescence measurements in Figure 36a–d, respectively. For NWs grown on GaAs(111)B in Figure 36a, a strong peak at 0.445 eV with a full width at half-maximum (FWMH) of 32meV was observed, while a low peak at 0.413 eV with a FWHM of 34 meV grown on Si was observed, as shown in Figure 36b. A lower PL intensity recorded from InAs NWs grown on Si compared to GaAs is probably due to the lower NW density and diameter. By decreasing the NW diameter, the principal PL peak shifted to a higher energy, confirming the presence of both WZ and ZB phases in InAs NWs grown by SAG-HVPE. These NW arrays exhibited strong PL intensity and optical absorption, which is encouraging for future optical devices. (FWMH) of 32meV was observed, while a low peak at 0.413 eV with a FWHM of 34 meV grown on Si was observed, as shown in Figure 36b. A lower PL intensity recorded from InAs NWs grown on Si compared to GaAs is probably due to the lower NW density and diameter. By decreasing the NW diameter, the principal PL peak shifted to a higher energy, confirming the presence of both WZ and ZB phases in InAs NWs grown by SAG-HVPE. These NW arrays exhibited strong PL intensity and optical absorption, which is encouraging for future optical devices.

*Nanomaterials* **2022**, *12*, x FOR PEER REVIEW 38 of 48

**Figure 36.** PL spectra at 10 K of InAs NWs grown on (**a**) GaAs (111) B and (**b**) Si (111); (**c**,**d**) Corresponding SEM images. The pitches are, respectively, 2 and 2.5 μm. Reprinted from ref. [162]. Cop-**Figure 36.** PL spectra at 10 K of InAs NWs grown on (**a**) GaAs (111) B and (**b**) Si (111); (**c**,**d**) Corresponding SEM images. The pitches are, respectively, 2 and 2.5 µm. Reprinted with permission from ref. [162]. Copyright 2021 American Chemical Society.

yright 2021 American Chemical Society. In the III−V semiconductor, III-antimonide, such as GaSb, has attracted a tremendous amount of research interest. GaSb (0.72 eV) is a direct bandgap material, which can be used as a photodetector of the mid-IR spectrum. Moreover, GaSb exhibited attractive characteristics for p-MOSFETs due to their high bulk hole mobility (over 1000 cm2 Similarly, it has great challenges to grow GaSb on Si substrate, due to the large lattice mismatch and thermal mismatch. Recently, there were reports of a GaSb-on-insulator (-OI) by direct wafer bonding [163] and epitaxial layer transfer [164], but these methods remain costly due to the limited sizes of available III−V substrates. However, a one-dimensional (1D) GaSb nanowire (NW) manufactured by selective epitaxial growth (SEG) provides extra benefits for many advanced utilizations, such as the better stress relaxation, capability of the advanced gate stacking integration, more efficient light adsorption and trapping. For the GaSb NWs' application in electronic devices, a well-controlled nanowire-like morphology with a small diameter (several tens of nanometers) is essential. Yang et al. [165] grew very thin and uniform GaSb NWs with diameters down to 20 nm by the use of a sulfur surfactant. This GaSb NWs were configured into transistors and exhibited impressive electrical properties with the peak hole Si. This results in two distinct orientations of the growth facets as illustrated in Figure **(a) (b)** In the III−V semiconductor, III-antimonide, such as GaSb, has attracted a tremendous amount of research interest. GaSb (0.72 eV) is a direct bandgap material, which can be used as a photodetector of the mid-IR spectrum. Moreover, GaSb exhibited attractive characteristics for p-MOSFETs due to their high bulk hole mobility (over 1000 cm2/Vs). Similarly, it has great challenges to grow GaSb on Si substrate, due to the large lattice mismatch and thermal mismatch. Recently, there were reports of a GaSb-on-insulator (-OI) by direct wafer bonding [163] and epitaxial layer transfer [164], but these methods remain costly due to the limited sizes of available III−V substrates. However, a one-dimensional (1D) GaSb nanowire (NW) manufactured by selective epitaxial growth (SEG) provides extra benefits for many advanced utilizations, such as the better stress relaxation, capability of the advanced gate stacking integration, more efficient light adsorption and trapping. For the GaSb NWs' application in electronic devices, a well-controlled nanowire-like morphology with a small diameter (several tens of nanometers) is essential. Yang et al. [165] grew very thin and uniform GaSb NWs with diameters down to 20 nm by the use of a sulfur surfactant. This GaSb NWs were configured into transistors and exhibited impressive electrical properties with the peak hole mobility of ~200 cm2/Vs, better than any mobility value reported for a GaSb nanowire device. To control the GaSb crystal shape and dimension deeply, an alternative to the SEG technique known as template-assisted selective epitaxy (TASE) was developed [166,167]. Borg et al. [167] investigated a monolithic integration of high-mobility horizontal GaSb NWs on the SOI substrate by TASE. They found that a high degree of morphological control allows for GaSb nanostructures with critical dimensions down to 20 nm. Figure 37a displays a SEM image of an exemplary array of

/Vs, better than any mobility value reported for a GaSb nanowire

SEG technique known as template-assisted selective epitaxy (TASE) was developed [166,167]. Borg et al. [167] investigated a monolithic integration of high-mobility horizontal GaSb NWs on the SOI substrate by TASE. They found that a high degree of morphological control allows for GaSb nanostructures with critical dimensions down to 20 nm. Figure 37a displays a SEM image of an exemplary array of GaSb nanostructures outside the templates. The exposed front GaSb surface, at which the crystal grows, typically forms a large {111} facet often with two smaller and opposing {110} facets (see Figure 37c,d). Because of the polar nature of the GaSb zinc-blende crystal structure, nonequivalent 180° rotations of the crystal lattice can occur upon nucleation on the nonpolar

/Vs).

mobility of ~200 cm2

GaSb nanostructures outside the templates. The exposed front GaSb surface, at which the crystal grows, typically forms a large {111} facet often with two smaller and opposing {110} facets (see Figure 37c,d). Because of the polar nature of the GaSb zinc-blende crystal structure, nonequivalent 180◦ rotations of the crystal lattice can occur upon nucleation on the nonpolar Si. This results in two distinct orientations of the growth facets as illustrated in Figure 37d. Meanwhile, the GaSb growth is governed by excess Sb present on the GaSb surface, leading to a strong growth rate dependence on the V/III ratio and temperature. Hall/van der Pauw measurements are conducted on 20-nm-thick GaSb nanostructures, revealing high hole mobility of 760 cm2/(V s). *Nanomaterials* **2022**, *12*, x FOR PEER REVIEW 39 of 48 37d. Meanwhile, the GaSb growth is governed by excess Sb present on the GaSb surface, leading to a strong growth rate dependence on the V/III ratio and temperature. Hall/van der Pauw measurements are conducted on 20-nm-thick GaSb nanostructures, revealing high hole mobility of 760 cm2 /(V s).

**Figure 37.** (**a**) SEM image of an array of horizontal GaSb nanostructures integrated coplanar with a SOI layer using TASE. The inset shows an illustration of the layer structure. (**b**,**c**) Tilted SEM images of GaSb nanostructures. (**d**) Schematic illustration highlighting the typical faceting observed at the growth front of the GaSb crystals. Reprinted from ref [167]. Copyright 2017 American Chemical Society. **Figure 37.** (**a**) SEM image of an array of horizontal GaSb nanostructures integrated coplanar with a SOI layer using TASE. The inset shows an illustration of the layer structure. (**b**,**c**) Tilted SEM images of GaSb nanostructures. (**d**) Schematic illustration highlighting the typical faceting observed at the growth front of the GaSb crystals. Reprinted from ref. [167]. Copyright 2017 American Chemical Society.

In summary, the APB problem can be solved by a miscut Ge/Si substrate, {113}-faceted Ge/Si (001) hollow substrate in the global epitaxial method, and {111}-oriented V-grooved in the ART method. However, high quality III−V heteroepitaxy with low TDD on Si is crucial to the monolithic integration of III−V devices on Si-based PICs. Table 2 is the summary of the reported TDD and RMS values of GaAs, InP in the growth of the substrate, epitaxy method, buffer materials, process in these years. In terms of material growth quality, the TDD of the GaAs layer as low as 107 cm−2 can be achieved by inserting the superlattice via global epitaxy. Then, the 8-inch GaAS-O-I substrate can be realized in our group soon. However, few research projects report on the preparation of other III−V epitaxy methods on the Si substrate. For selective epitaxial growth (SEG), many III−V semiconductors such as InP, InCaP, InAs, GaSb, etc. can be grown by the ART method. A TDD of 106 cm−2 of the InP layer was obtained in the V-grooves patterned Si substrate. In terms of application, the high-quality and stress-controlled large-size III-V epitaxial layer grown by global epitaxy is more conducive to the preparation of Si-based OEIC. On the contrary, the III–V nanowire arrays fab-In summary, the APB problem can be solved by a miscut Ge/Si substrate, {113}-faceted Ge/Si (001) hollow substrate in the global epitaxial method, and {111}-oriented V-grooved in the ART method. However, high quality III−V heteroepitaxy with low TDD on Si is crucial to the monolithic integration of III−V devices on Si-based PICs. Table 2 is the summary of the reported TDD and RMS values of GaAs, InP in the growth of the substrate, epitaxy method, buffer materials, process in these years. In terms of material growth quality, the TDD of the GaAs layer as low as 107 cm−2 can be achieved by inserting the superlattice via global epitaxy. Then, the 8-inch GaAS-O-I substrate can be realized in our group soon. However, few research projects report on the preparation of other III−V epitaxy methods on the Si substrate. For selective epitaxial growth (SEG), many III−V semiconductors such as InP, InCaP, InAs, GaSb, etc. can be grown by the ART method. A TDD of 106 cm−2 of the InP layer was obtained in the V-grooves patterned Si substrate. In terms of application, the high-quality and stress-controlled large-size III-V epitaxial layer grown by global epitaxy is more conducive to the preparation of Si-based OEIC. On the contrary, the III-V nanowire arrays fabricated by the SEG method can produce the monolithic integration of III-V nanodevices on silicon substrates. Especially for a smaller

ricated by the SEG method can produce the monolithic integration of III–V nanodevices on silicon substrates. Especially for a smaller size of CMOS electronic devices, several

nel-FETs.

size of CMOS electronic devices, several tens of nanometers of III-V NWs are considered optimal for high-performance tunnel-FETs.

### **5. Conclusions and Outlooks**

High-quality III-V heteroepitaxy on the Si substrate is crucial to the Si-based optoelectronic integration circuits (OEICs). In this work, we reviewed the three major challenges of the Si based IIII-V heteroepitaxy: (1) anti-phase boundaries (APB); threading dislocation (TD); (3) stacking faults (SF). Meanwhile, the mechanism and theoretical model of three kinds of defects are also deeply analyzed, which is convenient for readers to understand its development process in detail. In order to solve each issue, a wide variety of strategies is discussed. The bulk and high quality of III-V structure layers are the basis of larger scale optoelectronic devices' fabricating. For global epitaxy, the offcut Si substrates can easily suppress the formation of APBs, but it is incompatible with the integration of CMOS manufacturing. To reduce the TDDs, a lot of methods, including the buffer layer, annealing, multi-step growth, defect filter layers, and so on, were developed. In this, the thick layer and high annealing process can lead the new defects as stacking faults and thermal cracks, resulting in the low TDD of 106 cm−2 for GaAs, and a higher TDD (~107 cm−2 ) of InP-on-Si due to a larger lattice mismatch (~8%) between InP and Si. For selective epitaxial growth (SEG), {111}-oriented V-grooved pockets in SiO2 trenches by the ART approach are effective to restrict the generation of APBs and TDs, but the solution-etched V-groove is not always uniform and easily damages the crystal arrangement of the Si surface, which obviously affects the defects' distribution. In addition, the ART method also limits the maximum achievable dimension of the epitaxial III-V materials. Epitaxial lateral overgrowth (ELO) is an innovative technique to provide large regions of device materials, especially for plane-InP growth on Si. Moreover, other III-V semiconductors, such as InAs, GaSb, which have high mobility but larger mismatches with the Si substrate, can be fabricated in small-size Nanowires (NWs) by the ART method, representing potential applications as the channel material integrated on Si substrates to MOSFETs devices.

Even though major obstacles for III-V-on-Si heteroepitaxy, such as APBs, TD, stacking faults, are resolved now, the quality of III-V layers on on-axis Si is still unsatisfactory for the deployment on the PICs or ICs. Currently, we can obtain the low TDD of 106 cm−2 , but it still challenging to reduce the TDD to native substrates (~104 cm−2 ). Therefore, further effects need to be devoted to improving the quality of the III-V layer on Si to realize the integrated III-V on the Si-based platform fully. The Epitaxial Lateral Overgrowth (CELO) is an innovative process for large-scale high-quality Si-based III-V epitaxial layers; systematic research and process optimization are still needed to improve the materials' quality and device performance further. In addition, the bounding of III-V-O-I can thin the LT lowquality layer, which can fabricate the high-performance optoelectronic devices. Therefore, based on the current research, efforts should continue to be devoted to resolving the TDDs and the compatibility of integration techniques with large-volume CMOS manufacturing.

**Author Contributions:** Conceptualization, Y.D. (Yong Du) and H.H.R.; methodology, Y.D. (Yong Du), B.X., B.L. and Z.K.; data curation, Y.D. (Yong Du) and G.W.; writing—original draft preparation, Y.D. (Yong Du); writing—review and editing, Y.D. (Yong Du), G.W., Y.M., W.W., Y.D. (Yan Dong) and H.H.R.; supervision, H.H.R. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work was supported by the construction of the high-level innovation research institute from the Guangdong Greater Bay Area Institute of Integrated Circuit and System (Grant No. 2019B090909006) and the projects of the construction of new research and development institutions (Grant No. 2019B090904015), in part by the National Key Research and Development Program of China (Grant No. 2016YFA0301701), the Youth Innovation Promotion Association of CAS (Grant No. 2020037), and the National Natural Science Foundation of China (Grant No. 92064002).

**Conflicts of Interest:** The authors declare no conflict of interest.

### **References**


**6. Target volume delineation**

#### **6.1. Conventional radiotherapy**

Any clinical information and findings from bronchoscopy and mediastinoscopy should be gathered and correlated with diagnostic images. For postoperative cases, surgical records and pathology reports should be reviewed. And in case with doubt, discussions with surgeons and pathologists are encouraged to identify sites at risk of recurrence. Clips that are placed intraoperatively at sites with incomplete resection are useful for target identification.

An appropriate window setting should be used to delineate different targets on planning CT. Extent of primary lung tumor and mediastinal disease is best visualized by lung setting (window width 1600 and window level ‐600) and soft tissue setting (window width 400 and window level 20), respectively (**Figure 10**). Diagnostic imaging (e.g., CT or PET) should be coregistered with the planning of CT for contouring. PET images can help delineate area of collapse and atelectasis from tumors, but care should be taken when matching the images due to poor spatial resolution and breathing motion artifact.

**Figure 10.** Soft tissue window setting (a) in planning CT to define the mediastinal lymph node (red arrow), which cannot be easily seen in lung window (b).

Gross tumor volume of primary tumor (GTV‐P) is best contoured on lung window setting to include any visible tumor within lung parenchyma and the speculated border. Any local inva‐ sion to surrounding structures (e.g., chest wall, vertebra) should be included as well based on soft tissue window setting. Areas of collapse or atelectasis were excluded but can be difficult to differentiate. Input from radiologists and PET may be useful. Elective nodal irradiation is not recommended as isolated nodal recurrences are rare. So GTV of lymph node (GTV‐N) will only include any pathologically confirmed lymph nodes (fine needle cytology or core biopsy) and any suspicious lymph nodes based on imaging characteristics (including short axis diameter ≥1 cm, necrotic center or PET uptake). If chemotherapy had been used before radiotherapy, all initial sites of tumor involvement should be contoured unless it exceeds a tolerable radiotherapy portal.

An isotropic margin is then added to GTV‐P to cover microscopic tumor spread to form the clinical target volume (CTV‐P). Usually, a 6 mm margin for adenocarcinoma and an 8 mm margin for squamous cell carcinoma are used as it had been shown to cover around 95% of microscopic tumor extension on pathological specimens [11]. Subsequent CTV‐P is edited according to the presence of natural barriers (e.g., great vessels, bone). For GTV‐N, usually no additional margin is needed for CTV.

A margin from CTV to PTV (planning target volume) depends on tumor motion and daily set‐ up errors (**Figure 11**). Tumor motion can be quite variable from zero in cases using implanted fiducial markers in image‐guided radiotherapy to certain centimeters in cases without any breathing motion control. Set‐up errors are regularly measured in each department and usually within 5 mm in all directions. In common practice with free breathing treatment, a 1 cm isotro‐ pic margin is usually given to form the PTV. But a larger superior‐inferior margin of 1.5 cm may be used for tumors with greater movement as long as the lung dose is within the tolerance limit.

**Figure 11.** Target volume delineation: primary lung tumor (T) is contoured on lung window as gross tumor volume (GTV; red line); an additional 6 mm is added to form clinical target volume (CTV; blue line) to cover microscopic spread; further 1 cm margin is added to form the planning target volume (PTV; green line) to account for tumor motion and set‐up error.

For palliative radiotherapy using AP beams, information about tumor extent from diagnostic imaging can be superimposed on those visible on simulator to form the GTV. And a further 1.5 cm margin from GTV can be used to define the radiotherapy field border.

#### **6.2. Stereotactic body radiotherapy**

**6. Target volume delineation**

Any clinical information and findings from bronchoscopy and mediastinoscopy should be gathered and correlated with diagnostic images. For postoperative cases, surgical records and pathology reports should be reviewed. And in case with doubt, discussions with surgeons and pathologists are encouraged to identify sites at risk of recurrence. Clips that are placed

An appropriate window setting should be used to delineate different targets on planning CT. Extent of primary lung tumor and mediastinal disease is best visualized by lung setting (window width 1600 and window level ‐600) and soft tissue setting (window width 400 and window level 20), respectively (**Figure 10**). Diagnostic imaging (e.g., CT or PET) should be coregistered with the planning of CT for contouring. PET images can help delineate area of collapse and atelectasis from tumors, but care should be taken when matching the images due

Gross tumor volume of primary tumor (GTV‐P) is best contoured on lung window setting to include any visible tumor within lung parenchyma and the speculated border. Any local inva‐ sion to surrounding structures (e.g., chest wall, vertebra) should be included as well based on soft tissue window setting. Areas of collapse or atelectasis were excluded but can be difficult to differentiate. Input from radiologists and PET may be useful. Elective nodal irradiation is not recommended as isolated nodal recurrences are rare. So GTV of lymph node (GTV‐N) will only include any pathologically confirmed lymph nodes (fine needle cytology or core biopsy) and any suspicious lymph nodes based on imaging characteristics (including short axis diameter ≥1 cm, necrotic center or PET uptake). If chemotherapy had been used before radiotherapy, all initial sites of tumor involvement should be contoured unless it exceeds a tolerable radiotherapy portal. An isotropic margin is then added to GTV‐P to cover microscopic tumor spread to form the clinical target volume (CTV‐P). Usually, a 6 mm margin for adenocarcinoma and an 8 mm margin for squamous cell carcinoma are used as it had been shown to cover around 95% of microscopic tumor extension on pathological specimens [11]. Subsequent CTV‐P is edited

**Figure 10.** Soft tissue window setting (a) in planning CT to define the mediastinal lymph node (red arrow), which cannot

intraoperatively at sites with incomplete resection are useful for target identification.

to poor spatial resolution and breathing motion artifact.

**6.1. Conventional radiotherapy**

36 Radiotherapy

be easily seen in lung window (b).

Internal target volume (ITV) takes into account both GTV and internal tumor motion. It can be generated from the 4D CT using the maximum intensity projection (MIP) scan, maximum inspiratory, and expiratory scans, or all 10 phases of respiratory cycles (**Figure 12**). No CTV is needed. The usual CTV to PTV margin is 3–5mm, but it depends on methods of immobiliza‐ tion, tumor motion assessments, and treatment verification.

**Figure 12.** Target delineation on 4D CT: tumor is contoured on MIP images to form the internal target volume (ITV; red line); addition 5 mm margin was used to generate the planning target volume (PTV; green line).