The major purpose of this setup is to investigate parallel converters and their interactions, such as power-sharing accuracy. In a first test case, the two converters are connected to the grid sequentially. Fig. 4.11 shows the output power of both converters with droop-control. Converter 1 is connected to the public grid, mainly injecting active power *P*1 with only minor reactive power *Q*1 since the voltage magnitude is almost at its nominal value. Converter 2 synchronizes to the grid voltage and connects to the grid at approximately *t* = 0*.*5 s. After a transient period of approximately 1 s with some oscillation but no overshoot, both active and reactive power converge to stable operating points and verify high power-sharing accuracy without communication. This test bench is mainly used to validate the design for the droop control and the results for FRT operation for unbalanced faults discussed in chapter 7.

**Figure 4.10:** Converter test bench consisting of two converters with LCL-filters, interface rack, RCP-system, line impedance, power supply, and grid emulator.

**Figure 4.11:** Power-sharing of two parallel converters with grid connection.

**Table 4.2:** Basic system parameters

#### **State-of-the-Art IGBT Converter with Flexible Filter Configuration**

The semiconductor's performance limits the parallel converter test bench to low switching frequencies of *f*sw≤8 kHz. As presented before, this is not a drawback to emulate high power applications due to their typically low switching frequencies. However, e.g., PV-inverters often have lower power ratings and higher switching frequencies caused by efficiency, emission, and volume requirements. Consequently, a two-level converter based on IGBT4 technology was designed and built in cooperation during a supervised diploma thesis [108]. It is based on the structure in Fig. 4.9. The main differences compared to the parallel converters are the IGBT module with gate drivers, filter components, and measurements.

The IGBT module and cooling system are chosen based on a hybrid electrical and thermal simulation in *PLECS* using information provided by the semiconductor and heatsink datasheets. The simulation results for the semiconductor losses were verified with a commercial tool provided by *Semikron* and showed just minor differences smaller than 1 % of the total losses [108]. The results lead to the *MiniSKiiP 35NAB12T4V1* module with blocking voltages of 1.2 kV and 72 A rated dc-current. At *f*sw=20 kHz, the setup can achieve a power rating of approximately 10 kVA.

The gate drivers are based on the driver core *2SC0106T* from *Concept*. These driver cores are mounted on driver PCBs, providing active clamping, desaturation detection, soft shut-down, and low-voltage lockout as safety features. The gate resistors are chosen based on double-pulse switching test results such that the voltage overshoot does not exceed the safe operating range while the switching speed is maximized.

For the *LC*-filter design, the maximum inverter current ripple was limited to 20% of the rated current to determine *L*1f. This limit leads to *L*1f≈ 1*.*2 mH for *f*sw = 16 kHz and *V*dc= 750 V. Then, *C*f is given by the maximum output current harmonics defined in several standards such as IEEE-1547 [109]. However, these standards only limit harmonics up to 2.5 kHz and thus enable a wide range of choosing the capacitance *C*f. On the one hand, a larger *C*f guarantees more stable output voltages **v***C*, which is an advantage for grid-forming control algorithms. On the other hand, large *C*f shift the resonance frequency to low values that may cause critical resonance phenomena with the grid. Since the current harmonics do not provide a sufficient design criterion, the capacitance is calculated based on the reactive power *q*pu = 0*.*05 *pu*, which leads to *C*f≈ 10 *µ*F.

Higher switching frequency and smaller filters lead to faster dynamics of the converter. Hence, the measurements must be enhanced to achieve sufficient control characteristics. The *Allegro ACS-730* current sensor has a bandwidth of 1 Mhz with sufficient immunity to distortions. Galvanically isolated op-amps of type *AMC 1301* realize the voltage measurements that achieve bandwidths of up to 200 kHz.

The converter with all components is presented in Fig. 4.12. The output filter and grid connection components such as fuses, circuit breakers, and grid measurements sensors are built into another rack to achieve more flexibility in the filter configuration, as shown in Fig. 4.12.

**Figure 4.12:** IGBT 4 grid converter with peripherals, dSPACE interface, filter, and grid connection box.

A first test case is presented in Fig. 4.13 and 4.14. The converter is controlled with VOC and connected to the grid emulator. At *t* ≈ 0*.*18 s a phase jump of -45◦ occurs in the grid voltages. After a short transient period, grid currents are controlled to the new stable operating point. During phase jumps, the converter dynamics are predominantly affected by the PLL. This characteristic is thoroughly discussed in chapter 5. The presented setup is capable of testing converter control for converter switching frequencies up to 20 kHz with efficiently adaptable filter configurations.

**Figure 4.13:** Converter voltages during a -45◦ phase angle jump.

**Figure 4.14:** Converter currents during a -45◦ phase angle jump.

#### **SiC-MOSFET Converter for High-Switching Frequencies**

New semiconductor devices based on SiC lead to an exceptional increase of switching frequencies without an increase in switching losses. Due to the commercial availability of devices with blocking voltages of up to 1.7 kV and power ratings of several kVAs, SiC-MOSFETs are gaining importance in grid converter applications. Therefore, the third test bench is based on an SiC module and points at applications that require high switching frequencies, such as harmonic emulation or compensation.

This test bench was designed and built during a supervised master's thesis [110] and a detailed comparison to the IGBT4-converter is presented in [111]. The design process is based on the IGBT4-converter design and contains the *MiniSKiiP 26ACM12V17* module. In this case, the converter has smaller gate driver loops and gate drivers with increased d*v/*d*t* immunity due to the fast switching of the SiC-MOSFETs. For details on the general design process, refer to the preceding section. The SiC-converter achieves switching frequencies up to 100 kHz with a rated power of 10 kVA in grid connection and is shown in Fig. 4.15.

During this thesis, the setup is mainly used for PLL tests that need accurate emulation of high-order voltage harmonics. The standard EN 50160 defines voltage harmonics up to the 25th harmonic. The accurate voltage emulation is presented in Fig. 4.16, which shows only minor differences between the reference voltages **v** ∗ abc and converter output voltages **v***C*. This setup can be used to validate controls for converter setups with switching frequencies up to 100 kHz and to emulate voltage harmonics, as presented in chapter 5.

**Figure 4.15:** SiC-MOSFET based grid converter with peripherals.

**Figure 4.16:** Grid voltage emulation up to the 25th harmonic, according to EN 50160.

#### **4.2.2 Generic Controller Implementation**

The *MicroLabBox* contains a CPU and FPGA that can process measurement data, control algorithms, and control signals. The algorithms can be implemented with *Xilinx System Generator* using two programming layers each for the CPU and FPGA programs. The FPGA directly processes the measurement data from Analog-Digital-Converters (ADCs) or Digital Inputs (DIs) and controls the output of Digital Outputs (DOs). These signals can then be

**Table 4.3:** dSPACE control system parameters [112]

routed to the CPU. In the setups, two classes of ADCs are used. ADCs of class A convert all converter output currents and voltages, while class B ADCs only convert the dc-link voltages [112]. The ADC conversion times are summarized in Table 4.3.

Maximum execution step times of algorithms mainly determine if the CPU or FPGA must execute the program part. The CPU step time varies according to model complexity and is typically in the range of 100 *µ*s. The algorithms are implemented in *MATLAB Simulink*, where compiling is very time-efficient. The FPGA achieves much lower step times of typically 10 ns, but the programming is more complicated due to strict data type definitions and execution timing requirements. Moreover, the compiling process needs significantly more time. Exemplarily, the VOC algorithm for one converter in the CPU compiles in less than 1 minute, whereas a comparable algorithm in the FPGA compiles in approximately 30 minutes. Since the FPGA implementation is more time-consuming, the necessary time step for every single controller part is evaluated to decide if it must be implemented in the FPGA or can be implemented in CPU.

Since control algorithms on RCP systems must run with fixed step time, controllers must be transformed to the discrete domain. The two model layers, i.e., CPU and FPGA, demand different processes to transform continuous controllers into their discrete counterpart since the available functions in *MATLAB Simulink* and *Xilinx*-blockset differ significantly.

#### **CPU Controller Implementation in Simulink**

Controller programming in the CPU model is identical to the implementation of discrete *Simulink* models with fixed step time. Two different processes are convenient to transform continuous controllers into their discrete equivalence. The first possibility is to simply replace all integrators 1*/s* in the continuous block diagram by discrete integrator blocks in *Simulink*. Discrete integrator blocks already contain different discrete representations such as forward Euler, backward Euler, or trapezoidal approximation. The second method utilizes discrete transfer function blocks in *Simulink*. This method requires discrete transfer functions of the continuous controller parts. A simple *Matlab* workflow for the z-transform utilizes the function:

Gdi sc r=c2d ( Gcont , Ts , ' t u s ti n ' ) ,

where *Gdiscr* is the discrete form of the continuous transfer function *Gcont*. *Ts* defines the sampling time of the system and, *tustin* exemplarily describes the integration method. Various integration methods are available and according to extensive studies in [113], [114], applying impulse invariant, pole-zero matched, Tustin with pre-warping, Zero-Order-Hold (ZOH) and First-Order-Hold (FOH) formulations yield the most accurate discrete representations for controllers. In this work, Tustin's method is applied predominantly, whereas in some cases, the FOH is used to prevent algebraic loops.

Besides selecting the integration method, the sampling frequency *f*s should be at least ten times larger than the controller bandwidth to obtain an accurate representation of the continuous controller [115]. The CPU model is used for controller implementation with lower dynamic requirements such as power controllers, PLLs, and voltage controls. In contrast, the current control requires lower step times, and thus must be executed in the FPGA.

#### **FPGA Implementation with Xilinx-Blockset**

FPGA models are implemented in *System Generator* by using the *Xilinx*-blockset, which contains several fundamental operators such as adders or multipliers. To implement discrete transfer functions, they must be transformed to difference equations and recursive formulas. These formulas can be programmed by utilizing registers or delay blocks *z*−1 , respectively. In order to clarify how a controller is realized in the FPGA, the PR-controller is used as an example. First, the ZOH-transform of 3.42 leads to the discrete transfer function of the resonant part of the PR-controller according to:

$$G\_{d, \text{pos}}(z) = k\_i \frac{z \frac{1}{\omega\_1} \sin \left(\omega\_1 T\_s\right) - \frac{1}{\omega\_1} \sin \left(\omega\_1 T\_s\right)}{z^2 - z 2 \cos \left(\omega\_1 T\_s\right) + 1} = k\_i \frac{az - a}{z^2 - bz + 1} = k\_i \frac{a(z^{-1} - z^{-2})}{z^{-2} - bz^{-1} + 1} \quad . \quad (4.17)$$

*T*s is the sampling time and *ω*1 the fundamental frequency, and thus *a* = 1 *ω*1 sin (*ω*1*Ts*) and *b* = 2 cos (*ω*1*Ts*) are constants if *ω*1 is assumed to be constant. Second, the proportional part of the controller is added, and the transfer function is rearranged to derive the recursive formula to obtain:

$$u\_i = \left(bz^{-1} - z^{-2}\right)u\_i + k\_i a \left(z^{-1} - z^{-2}\right)e\_i + k\_p e\_i \quad , \tag{4.18}$$

where *e*i is the controller input and *u*i is the controller output of the i-th execution step. This equation can be programmed in the FPGA by using registers and fundamental math operations (e.g., adders, substracters, multipliers), as presented in Fig. 4.17.

The presented programming framework can be used to efficiently implement controllers with different execution step times. The FPGA can meet even challenging time step requirements in the range of a few ns. In this thesis, various PLLs, grid-following controls, and grid-forming controls were realized with this platform, and no critical limits for the target application

**Figure 4.17:** PR-controller algorithm in *System Generator* with *Xilinx*-blockset.

were identified. This RCP system, together with the presented hardware test benches, provide a potent framework to validate converter models and analyze grid converter controls experimentally.

### 5 Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

Fast and robust grid voltage detection is crucial for the control of grid-following converters. Particularly, VOC needs the phase angle of the positive sequence grid voltage to inject active and reactive power accurately. Contrarily, grid-forming converters do not necessarily need a PLL for power control, but a grid synchronization may provide a smooth transient process during connection of grid-forming converters to the grid [3].

In the vast majority of cases, grid synchronization is provided by PLLs, which use feedback control loops to detect the phase angle based on the measured grid voltage. The feedback control is typically realized with PI-controllers to achieve zero steady-state error. The accuracy of the detected phase angle affects separation of injected power into active and reactive power, i.e., the power factor accuracy. The power factor changes significantly during faults with large phase jumps since the PLL must lock on the new phase angle. PLLs thus dominate converter control dynamics during severe grid disturbances.

The simplest PLL structure is the SRF-PLL, which achieves zero steady-state error under ideal grid conditions [116]. However, real three-phase grid voltages contain distortions such as harmonics, unbalances, and frequency variations [58], [38], [45]. These distortions affect voltage magnitude and phase angle estimation of PLLs. If these distortions are not rejected sufficiently by the PLL algorithms, they will impair the steady-state power injection quality of the VSC. Consequently, an error or distortion in the detected grid voltage phase angle propagates to the converter's power factor. These power factor distortions are critical because the VSC must respect the power factor accuracy to comply with grid codes [13].

Severe grid disturbances such as faults pose the most challenging scenarios for PLLs. Faults lead to the most severe transient processes, resulting in large grid voltage steps and phase angle jumps [45]. The PLL must accurately detect these dynamics with small errors to comply with grid codes that demand a fast step response of the reactive current with maximum settling times of 60 ms to reduce the voltage drop at the PCC [13], [67]. Once the fault is cleared, the reactive current must return to its pre-fault value to avoid converter tripping due to overvoltage [58]. Typically, the current control loop is fast enough to comply with grid codes [117], but the PLL time constant is much larger, making it critical for meeting required settling times.

In summary, the major concern of grid synchronization is to realize a PLL with high control bandwidth, high immunity to distortions, and large stability margin. The PLL performance is based on a trade-off between these properties [118]. Various contributions have proposed advanced PLL schemes to enhance the performance under adverse grid conditions, e.g. advanced filter or decoupling structures improve immunity to distortions while trying to preserve the dynamics [72], [119], [120], [56], [121], [122], [118], [123], [124]. S. Golestan has presented an extensive overview of the most popular three-phase PLLs, e.g., the DSOGI-PLL, Moving Average Filter (MAF)-PLL, DSRF-PLL, and Notch-filter (Nf)-PLL [119].

Filter and decoupling structures add complexity to the control system and introduce additional design parameters that demand more sophisticated methods for design and analysis. The vast majority choose the Symmetrical Optimum (SO) to design PLLs [116], [124], [125], [91], [126]. Even though it was originally invented for SRF-PLLs, this design approach can be adapted for PLLs with prefilters [119], [124]. However, the applicability of the SO for PLLs with prefiltering stage is rarely addressed. This discussion is presented in the following chapter and is combined with a detailed design process for a given grid scenario.

Besides enhancing PLLs with filters or decoupling structures, several publications compare and evaluate PLLs during adverse grid scenarios. Ref. [119], [122], [124] and [127] conducted a comparative study with different test cases considering unbalances, harmonics, and frequency variations. However, why these scenarios are chosen and how this choice affects the PLL design is not analyzed in detail. They also do not address the impact of the PLL on the current and power control. Recent research results that present the analysis of PLLs in combination with the current control mainly focus on small-signal stability under ideal voltages and symmetrical faults. Furthermore, they only consider the SRF-PLL without mandatory filters and do not analyze how the design trade-off between immunity to voltage distortions and control bandwidth affects the VSC power factor and its current control [9], [128], [75], [129].

This chapter is intended to fill these gaps and is organized as follows: At first, the general principle of PLLs and their impact on the converter's output power are motivated for the Synchronous Reference Frame with Low-Pass Filters (LSRF)-PLL. The second part introduces critical grid scenarios and addresses converter requirements defined in several grid standards. Then, SRF-PLLs based on sequence decomposition or prefilters are presented, which can detect the positive sequence voltage under severe grid faults considering harmonics, unbalances, and frequency variations. This part further discusses the model fidelity of the SSMs of these PLLs that are used for the SO design. In the fourth section, a general design framework and the corresponding design process is developed to achieve an optimum trade-off between immunity to distortions and control bandwidth. Then, an experiment is designed and conducted to test PLLs and validate their models in various operational scenarios. The model validation indicates significant problems of the SSMs to predict the stability of PLLs with frequency adaptive filters, i.e., DSRF-PLL. Therefore, the proposed design framework is extended to a multi-fidelity approach that can capture transient stability problems of PLLs. Finally, the optimum design parameters for five different PLLs are derived with the introduced multi-fidelity model-based design, and are evaluated considering immunity to distortions and control bandwidth. This study demonstrates that the design process can determine optimum control parameters for any SRF-based PLL. The design framework contains LSMs that can accurately predict the transient stability boundary even for nonlinear characteristics but fail to provide analytical insight into the mechanisms. Therefore, the last part of this chapter focuses on the transient stability phenomena and how to assess them with nonlinear analysis methods.

The SRF-PLL structure relies on the Clarke and Park transformation presented in section 3.2.3 [130], [119]. The Park transformation contains the unknown phase angle *θ* = *ω*1*t* (see 3.6) that must be detected by the PLL for grid synchronization. Since Clarke's transformation is linear, the following derivation will assume **v***αβ* as measured input voltages in *αβ*-frame. The estimated phase angle *θ* 0 is used for Park's transformation **T**dq. So, **T**PLL*,*dq denotes the transformation with *θ* 0 in the following calculations. Describing the grid voltages **v***αβ* according to 3.12 and assuming *δ* = *θ* − *θ* 0 as error of the estimated phase angle leads to the positive sequence voltage in dq-frame:

$$\begin{aligned} \mathbf{v}\_{\text{PLL,dq}}^{\pm} &= \mathbf{T}\_{\text{PLL,dq}} \mathbf{v}\_{\alpha\beta} = \underbrace{\hat{V}\_{\text{S},1} \begin{bmatrix} \cos(\delta) \\\\ \sin(\delta) \end{bmatrix}}\_{\mathbf{v}\_{\text{PLL,dq}}^{\pm}} \\ &+ \underbrace{\hat{V}\_{\text{S},-1} \begin{bmatrix} \cos\left(-2\omega\_{1}t + \delta + \delta\_{-1}\right) \\\\ \sin\left(-2\omega\_{1}t + \delta + \delta\_{-1}\right) \end{bmatrix}}\_{\mathbf{v}\_{\text{PLL,dq}}^{\text{-}}} + \underbrace{\sum\_{n=-m}^{m} \hat{V}\_{\text{S},n} \begin{bmatrix} \cos\left((n-1)\omega\_{1}t + \delta + \delta\_{n}\right) \\\\ \sin\left((n-1)\omega\_{1}t + \delta + \delta\_{n}\right) \end{bmatrix}}\_{\mathbf{v}\_{\text{PLL,dq}}^{\text{-}}}. \tag{5.1}$$

The harmonics and negative sequence components experience a frequency and angle shift according to *nω*1*t*+*δn*−*θ* 0 = *nω*1*t*+*δn*−*θ*+*δ* = (*n*−1)*ω*1*t*+*δn*+*δ*. If *δ* becomes very small, 5.1 provides an accurate estimation of the phase angle *θ* and the corresponding amplitude *V*ˆ S*,*1. A suitable feedback control with **v** + PLL*,*dq as input could ensure *δ* ≈ 0 rad in steady-state, so that the linearized dq-components of the voltages ∆**v** + PLL*,*dq represent the fundamental grid voltage magnitude and phase angle according to:

$$
\Delta \mathbf{v}\_{\rm PLL,dq}^{+} = \hat{V}\_{\rm S,1} \begin{bmatrix} 1 \\ 1 \\ \delta \end{bmatrix} + \mathbf{v}\_{\rm PLL,dq+}^{-} + \mathbf{v}\_{\rm PLL,dq+}^{n} \quad . \tag{5.2}
$$

Chapter 5. Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

**Figure 5.1:** LSM of the LSRF-PLL.

Since ∆**v** + PLL*,*dq+ are dc-quantities in the steady-state, a PI-controller can be applied for controlling ∆*v* + PLL*,*q = 0 to achieve *θ* 0 ≈ *θ*. Unfortunately, higher-order harmonics, i.e., **v** − PLL*,*dq+ and **v** *n* PLL*,*dq+, overlay the fundamental-frequency component and may disturb the controller output *θ* 0 .

Fig. 5.1 presents the feedback control for ∆*v* + PLL*,*q , considering Park's transformation. This plant is a type 2 control system, i.e., it includes two free integrators, which introduce two poles at the origin to guarantee zero steady-state error in response to frequency steps or phase angle jumps [131], [132]. Additionally, it contains a low-pass filter *G*f with the frequency *ω*f to filter out the voltage harmonics and an Amplitude Normalization Scheme (ANS) to normalize the controller input to the voltage magnitude *V*ˆ S*,*1 [133], [119]. The analysis of this control system is complex due to the trigonometric and algebraic nonlinearities.

The following investigation focuses on the dynamic characteristics of PLLs during grid faults. Consequently, the LSM is crucial for evaluating the large-signal behavior and the dynamic performance during severe transient processes. The disturbance rejection may affect the maximum control bandwidth of PLLs and can be described more efficiently by SSMs, since voltage harmonics are typically small compared to the fundamental frequency voltage component [38]. The LSM and SSM are thus used for the analysis and parameter design.

The LSM describes the data-sampled system with continuous grid voltage waveforms and discrete PLL algorithms. Tustin's transformation discretizes the PLL filters, and the same discretization is applied to the integrator of the angular frequency at the PLLs output. For some PLLs, Euler Forward discretization is used to prevent algebraic loops during execution. This is necessary since Tustin's transformation does not include an intrinsic delay. The sampling time is *T*s = 100 *µ*s and is identical to the execution time *T*s = 100 *µ*s of the *dSPACE MicroLabBox*. This sampling time does not critically affect the PLL performance since typical control bandwidths are in the range of 50-100 rad/s.

The LSRF-PLL can be linearized for the operating point *δ* = 0 rad to obtain the SSM. The SSM simplifies the overall analysis without critically affecting the fidelity for small perturbations around an operating point. The Maclaurin series linearizes the non-linear

**Figure 5.2:** SSM of the LSRF-PLL.

trigonometric functions of the fundamental frequency terms **v** + PLL*,*dq+. The time-dependent harmonics **v** − PLL*,*dq+ and **v** *n* PLL*,*dq+ are summed up to *v*˜PLL*,*q+ and serve as disturbance input of the system. The model neglects the dynamics of the ANS. These assumptions result in the SSM of the LSRF-PLL in Fig. 5.2, where ∆ denotes the linearized input and output variables.

The structure in Fig. 5.2 contains three linear transfer functions to describe the dynamics of the estimated phase angle ∆*θ* 0 . These are the closed-loop transfer function *G*cl(*s*) with the phase angle ∆*θ* as input, the disturbance transfer function *G*d(*s*) with the voltage harmonics and negative sequence voltage *v*˜PLL*,*q+ as input, and the feed-forward transfer function *G*fw(*s*) with the nominal fundamental angular frequency *ω*1 as input.

$$G\_{\rm ol}(s) = G\_{\rm f} \frac{1}{\hat{V}\_{\rm S,1}} G\_{\rm Pl} \frac{\hat{V}\_{\rm S,1}}{s} = \frac{k\_{\rm p} \omega\_{\rm f} \left(s + \frac{k\_{\rm f}}{k\_{\rm p}}\right)}{s^2 \left(s + \omega\_{\rm f}\right)}\tag{5.3}$$

$$G\_{\rm cl}(s) = \frac{\Delta\theta'}{\Delta\theta} = \frac{G\_{\rm ol}}{1 + G\_{\rm ol}} = \frac{k\_{\rm p}\omega\_{\rm l}s + k\_{\rm i}\omega\_{\rm l}}{s^3 + \omega\_{\rm l}s^2 + k\_{\rm p}\omega\_{\rm l}s + k\_{\rm i}\omega\_{\rm l}}\tag{5.4}$$

The control transfer function in 5.4, derived from the open-loop transfer function given in 5.3, describes PLL dynamics during transients, such as phase jumps or frequency steps. The disturbance transfer function *G*d(*s*) describes the disturbance rejection and is derived as follows:

$$G\_{\rm d}(s) = \frac{\Delta \theta'}{\tilde{v}\_{\rm PL, q+}} = \frac{1}{\hat{V}\_{\rm S, 1}} G\_{\rm cl} \ . \tag{5.5}$$

The feed-forward transfer function *G*fw(*s*) can be expressed as:

$$G\_{\rm lw}(s) = \frac{\Delta\theta'}{\omega\_1} = \frac{1}{s + G\_{\rm l}G\_{\rm Pl}}\ . \tag{5.6}$$

Due to the constant feed-forward term, *G*fw(*s*) is not of interest in the dynamic or steady-state analysis.

The step response and steady-state characteristics of the LSRF-PLL during different faults demonstrate the accuracy range of the SSM. During a three-phase fault (type A) with *V*ˆ S*,*1 = 0*.*05 pu, and a large phase jump of −*π/*2, the SSM and LSM differ significantly, as shown in Fig. 5.3. In contrast, these models show similar results for the disturbance

**Figure 5.3:** Comparison of the SSM and LSM results for the LSRF-PLL during a type A fault with *V*ˆ S*,*1 = 0*.*05 pu.

**Figure 5.4:** Comparison of the SSM and LSM results for the LSRF-PLL during a type E fault with maximum negative sequence component and *V UF*≈1.

**Figure 5.5:** Phase jumps applied to *G*cl with different filter cutoff frequencies *ω*f.

**Figure 5.6:** Frequency step applied to *G*cl with different filter cutoff frequencies *ω*f.

**Figure 5.7:** Bode plots of *G*d with different filter cut-off frequencies *ω*f.

rejection in steady-state during an unbalanced type E fault with *V*ˆ S*,*1 = 0*.*05 pu in Fig. 5.4. For this exemplary test, the design parameters are *ω*f = 65 rad/s, *k*i = 279 rad*/*s 2 , and *k*p = 26*.*25 rad*/*s. The corresponding design process is derived in section 5.7.

The LSRF-PLL has three design parameters. One for the low-pass filter: *ω*f, and two for the PI-controller: *k*p and *k*i. All three affect the dynamic and steady-state characteristics. Dynamic behavior mainly includes the phase angle and frequency step responses. Fig. 5.5 and 5.6 show these responses for different filter cutoff frequencies *ω*f. The results demonstrate that the rise time, settling time, and overshoot vary significantly depending on *ω*f. Particularly the settling time decreases for larger *ω*f.

The steady-state characteristic determine the PLL's disturbance rejection. The Bode plot of *G*d(*s*) is presented in Fig. 5.7 for different *ω*f. It indicates a decrease in disturbance rejection for higher *ω*f. This characteristic reveals the fundamental PLL design trade-off: An increase in control bandwidth (i.e, increasing *ω*f) typically deteriorates the disturbance rejection. A suitable design process must identify an optimum design considering this trade-off.

Design processes typically require scenarios and performance indicators to evaluate fulfillment

**Figure 5.8:** Grid voltages during a symmetrical fault (type A) with a −90◦ phase jump.

**Figure 5.9:** Phase angle error *δ* during a symmetrical fault (type A) with a −90◦ phase jump.

**Figure 5.10:** Converter active and reactive output power during a symmetrical fault (type A) with a −90◦ phase jump.

of the design objective. Severe grid faults are suitable worst-case scenarios, and a type A fault with a phase jump of −90◦ serves as an example for such a scenario (see Fig. 5.8). The performance indicators are commonly the step responses of the phase angle *δ*, as shown in Fig. 5.9. However, PLLs critically affect the power output of the converter, as indicated for the exemplary type A fault in Fig. 5.10. These characteristics highlight how important it is to consider the converter's power control to evaluate PLL designs.

The LSRF-PLL is a mature algorithm but has a low immunity to large negative sequence voltages during severe, unbalanced faults. Several approaches focus on advanced filter algorithms and different decoupling strategies to improve the immunity [119], [52], [124], [134], [122], [52], [119]. These strategies are mainly based on the algorithms presented in chapter 3.2.

Based on the presented characteristics, three crucial questions arise that will be discussed throughout this chapter:

The investigations show critical transient instability phenomena occurring during severe faults. These are addressed with a proposed design process and an analytical approach based on Lyapunov's indirect and direct method.

Chapter 5. Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

$$\left. \frac{\mathrm{d}^2 \, \cos(\varphi)}{\mathrm{d}\varphi^2} \right|\_{\varphi\_0} = \left. -\cos(\varphi\_0) \right| \stackrel{!}{=} 0 \,\mathrm{(5.7)}$$

$$
\varphi\_0 \quad = \underbrace{n\frac{\pi}{2}}\_{\cdot} \text{rad} \quad \quad \quad (5.8)
$$

$$n \quad := \quad \{1, 3, 5, \ldots\} \qquad \text{(5.9)}$$

**Figure 5.11:** Power factor description based on phase angle *ϕ* and its dependency on *δ*.

### **5.1 Converter Control Requirements and Worst-Case Grid Scenarios considering Severe Network Disturbances and Converter Fault Current Injection**

Grid codes provide the converter requirements for FRT and normal operation [13, p.15], [67, p.18], [11]. Two requirements are particularly critical for the converter control. First, grid codes define the accuracy of active and reactive power supply defined by the active factor cos(*ϕ*) [12, p.57]. Second, the grid operator requires a maximum settling time for the reactive current during FRT [13, p. 15], [67, p. 18], [11].

The active factor cos(*ϕ*) is equivalent to the power factor *λ*, if the active and reactive power caused by harmonics in the voltages and currents are neglectable. Consequently, *λ* ≈ cos(*ϕ*) is assumed in the following analysis, and *λ* obviously depends on the phase *ϕ* between grid voltages and injected converter currents. The error of the estimated phase angle *δ* changes *λ* since it defines the reference voltage for the converter's current control, as depicted in Fig 5.11. If *δ* is not zero, the phase angle of the grid *ϕ* and the phase angle of the current control *ϕ*PLL will differ and lead to a difference between *λ* and *λ*PLL, which is defined as maximum power factor deviation *λ*˜ = *λ* − *λ*PLL. The subscript PLL denotes the orientation of the converter control based on the estimated phase angle *θ* 0 . A worst-case error estimation defines the operating point *ϕ*0 where *δ* has the largest impact on *λ*˜. This is necessary since *λ*˜ has a nonlinear relation to *δ* and *ϕ*. The second order derivative of *λ* = cos(*ϕ*) defines this worst-case operating point of *ϕ* according to 5.7. For simplicity *n* := 1 is chosen to derive this critical point, which occurs at *ϕ*0 = *π/*2.

**Figure 5.12:** Normalized negative sequence fundamental voltage component *V*ˆPCC*,*−1 for different fault types.

**Figure 5.13:** Maximum unbalance factor *V UF* for different fault types.

The critical operating point *ϕ*0, the characteristics in Fig. 5.11, and the maximum power factor error *λ*˜max lead to the maximum permissible phase angle error *δ*max:

$$
\pm \tilde{\lambda}\_{\text{max}} = \ 0.005 \text{ pu} = \lambda - \lambda\_{\text{PLL}} = \cos(\varphi\_0) - \cos(\varphi\_0 + \delta\_{\text{max}}) = \sin(\delta\_{\text{max}}) \quad (5.10)
$$

$$
\Rightarrow \delta\_{\text{max}} = \pm \text{asin}(\tilde{\lambda}\_{\text{max}}) \approx \pm \tilde{\lambda}\_{\text{max}} \text{ rad} = \pm 0.005 \text{ rad} = \pm 0.286^{\circ} \tag{5.11}
$$

*λ*˜max is set to 0.005 pu according to [12, p.57] and serves as requirement for the maximum permissible error of the estimated phase angle of the PLL.

Harmonics in the grid voltages and large negative sequence components may distort *δ*, and thus affect *λ*˜ in steady-state (Table 3.3 [38], [52, p.35]). The PLL-SSM in Fig. 5.2 indicates that only the q-components of the Park transformed grid voltages *v*˜PLL*,*q+ influence *δ*. Therefore, the limits given in EN 50160 are transformed into the dq-domain. However, the negative and positive sequence of the harmonics may compensate each other in dq-domain, not representing the worst-case spectrum. Therefore, only the negative sequence harmonics are considered to determine *v*˜PLL*,*q+ because they have the largest amplitudes according to Table 3.3. Additionally, large negative sequence voltages of unbalanced grid faults have the same effect on *δ* as the harmonics. Analyzing the fault types shows that type C and D result in the maximum negative sequence voltage, as shown in Fig. 5.12. However, the Amplitude Normalization Scheme (ANS) normalizes the negative sequence components and harmonics with the positive sequence voltage. This normalization corresponds to the definition of the voltage unbalance factor (*V UF*). Fig. 5.13 shows the *V UF* for all fault types and indicates that type C to G yield the same normalized negative sequence component of 1 pu. This high disturbance compared to the harmonics in normal operation requires large attenuation of the negative sequence to limit the maximum distortion of the phase angle.

The worst-case grid voltage spectrum in dq-domain is shown in Fig. 5.14 and contains the voltage harmonics at different frequencies and the maximum negative sequence voltage at 100 Hz. The harmonics and negative sequence voltages will vary in their frequency due

**Figure 5.14:** Worst-case spectrum of the grid voltage for the nominal grid frequency *f*1 = 50 Hz, according to EN 50160 [38].

**Figure 5.15:** Superimposed worst-case spectrum of the grid voltage considering frequency drifts (47*.*5 Hz *< f*1 *<* 51*.*5 Hz) of the fundamental frequency voltage and the corresponding harmonics.

to variations in the fundamental grid frequency in the range of 47*.*5 Hz *< f*1 *<* 51*.*5 Hz. Therefore, they may occur in a frequency band around their nominal operating point. Combining all these possible spectra for different fundamental frequencies leads to the superimposed worst-case spectrum in Fig. 5.15, which serves as operational scenario to assess the immunity to distortions of PLLs.

In contrast to the immunity to distortions, which describes the steady-state characteristics, the dynamic requirements mainly focus on the step response of the converter current during severe grid faults. Typically, the converter has to provide reactive current depending on the positive sequence voltage *V*ˆ PCC*,*1. Hence, two crucial operating point variables change almost simultaneously. First, the grid voltages experience large amplitude steps and phase angle jumps. The PLL must detect these changes quickly to inject active and reactive power accurately, as explained in Fig. 5.11. Second, the converter reference currents change with *V*ˆ PCC*,*1 to support the grid voltages according to the grid codes.

The amplitude steps and phase angle jumps predominantly depend on the fault type and the fault impedance to the source impedance ratio *Z*F/*Z*S . The amplitude steps change with the magnitude of the impedance ratio, whereas the grid phase angle jump mainly depends on the impedance angles (see section 3.3.1). Fig. 5.16 shows the maximum phase jump ∆ˆ*θ* for the different fault and grid types (lv - low-voltage, mv - medium voltage, and hv - high voltage). The grid voltage level defines the *r*S = *XL*S*/R*S-ratio of the source impedance *Z*S according to Table 3.1. The *r*F = *XL*F*/R*F-ratio of the fault impedance *Z*F is varied between 0...10 to derive ∆ˆ*θ* for every fault type and voltage level. Type A faults show the largest phase angle jumps of approximately *π/*2 for *Z*F≈0 pu and *r*F = 10 for the lv-grid or *r*F = 0 for the hv-grid, respectively. The unbalanced fault types E, F, and G produce the largest phase angle jump with ∆ˆ*θ* = 0*.*41 rad for *Z*F≈1 pu.

The positive sequence voltage amplitude also experiences the largest sag for the type A fault, whereas the single-phase fault (type B) shows the lowest sag depth. The unbalanced type E, F, and G faults show the largest sag depth of 0.66 pu for *Z*F≈0 pu. The results for

**Figure 5.16:** Maximum phase jump ∆ˆ*θ* for different fault types.

**Figure 5.17:** Normalized positive sequence fundamental voltage component *V*ˆPCC*,*1 for different fault types.

all fault types are summarized in Fig. 5.17. In summary, type A faults are the most severe disturbances for the converter control and PLLs, since they lead to the largest voltage sags, and phase angle jumps. The most severe unbalanced faults are of type E, F, and G.

The converter must provide reactive current during grid faults depending on the positive sequence voltage [11], i.e., the converter must inject q-current for an accurately locked dq-system with *δ* = 0. In contrast to [135], new grid codes do not mention a deadband for reactive current provision [11]. Nonetheless, normal and abnormal grid conditions are not treated separately by the grid operator who sets the power factor and FRT commands. Since the reactive current steps in response to voltage drops below 10% are very small, these are out of the scope of this investigation, and the following analysis focuses on faults starting at 0.9*V*ˆ S*,*1.

Fig. 5.18 shows the active and reactive or d and q-reference current, respectively, for different positive sequence voltage magnitudes *V*ˆ PCC*,*1, considering a converter current limitation to 1 pu. The magnitude *V*ˆ PCC*,*1 is denoted with *V* + in the figures for better readability. The corresponding power factor characteristics in Fig. 5.19 are identical to the currents in their normalized form.

Grid codes require maximum rise and settling times for the q-currents or reactive current, respectively. The grid codes slightly differ in their requirements, and the most recent VDE-AR-N 4110 demands a maximum rise time of 20 ms and settling time of 60 ms considering a tolerance band of 10% [11]. These timing requirements are crucial for fast grid voltage support. After fault clearing, the reactive current must quickly decrease to its pre-fault value to prevent overvoltages [58].

Table 5.1 summarizes the results for the worst-case scenario and the control requirements of RES converters. The PLLs must ensure the required disturbance rejection for the power factor and quick step response of the reactive current during the worst-case scenarios of type E and type A faults. The type E fault is the worst-case for the immunity to distortions due to the high *V UF*. The type A fault serves as worst-case for the dynamics since it contains Chapter 5. Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

**Figure 5.18:** Active and reactive current references during faults according to VDE [11].

**Figure 5.19:** Power factor references derived with current reference requirements according to [11].

**Table 5.1:** Converter requirements and parameters for the worst-case grid scenarios.

the largest ∆ˆ*θ* jump and *V*ˆ PCC*,*1 sag. The minimum positive sequence voltage *V*ˆ PCC*,*1*,*min is assumed to be 0.05 pu according to [13].

Since the LSRF-PLL cannot sufficiently deal with large unbalances, several PLLs are proposed in the literature to increase the control bandwidth while conserving the immunity to distortions. These can be divided into sequence decomposition-based PLLs and PLLs with prefilter. To assess their performance during the derived worst-case scenarios, their accurate disturbance and control transfer functions are necessary, which are derived in the following section.

### **5.2 Control and Disturbance Characterization of Online Symmetrical Component Decomposition**

The analysis in section 3.2 identified Clarke's and Park's transformation as suitable tools for symmetrical component decomposition. The decomposition in *αβ*-frame needs a 90◦ phaselag operator that is realized with a Second Order Generalized Integrator (SOGI) algorithm containing two integrators. The decomposition in the dq-frame is based on the DSRF, which decouples the positive and negative sequences by applying two different reference frames in the positive and negative sequence. These algorithms are interesting for PLLs since the

decomposition extracts the positive sequence voltage and rejects the negative sequence. This characteristic increases the filter capability of the PLLs, but may introduce additional transfer characteristics and feedback loops that affect dynamic behavior and stability.

#### **5.2.1 Dual Synchronous Reference Frame (DSRF)**

The DSRF is a decoupling method to extract symmetrical components in the dq-frame. The characteristics of Park's transformation for positive and negative sequence components were already derived in section 3.2. Rearranging 3.30 and A.12 leads to the basic idea of the decoupling strategy for the DSRF summarized in 5.12 and 5.13 and shown in Fig. 5.20.

The Park matrices with *θ* 0 and −*θ* 0 for the positive and negative sequence voltage, respectively, transform the grid voltages **v***αβ* into their dq-components. These components still contain harmonics and the negative or positive sequence coupling component denoted by **T**dq−2 **v** + dq or **T**dq+2 **v** − dq, respectively. Then, a low-pass filter extracts the dc-components **v** + dq and **v** − dq. These can be transformed back with **T**dq−2 and **T**dq+2 with −2*θ* 0 and 2*θ* 0 , respectively, to get the decoupling terms to compensate for 2*ω*1 oscillations caused by the opposite sequence component. Finally, the positive and negative sequence voltages in dq-frame, i.e, **v** + dq and **v** + dq, respectively, are obtained according to:

$$\mathbf{v}\_{\rm dq}^{+} = \mathbf{v}\_{\rm dq}^{+} - \mathbf{T}\_{\rm dq + 2} \mathbf{v}\_{\rm dq}^{-} - \sum\_{n = -\infty}^{m} \mathbf{T}\_{\rm dq - (n - 1)} \mathbf{v}\_{\rm dq}^{n} \,, \tag{5.12}$$

$$
\overline{\mathbf{v}}\_{\rm dq}^{-} = \mathbf{v}\_{\rm dq}^{-} - \mathbf{T}\_{\rm dq} \cdot {}^{2} \overline{\mathbf{v}}\_{\rm dq}^{+} - \sum\_{n=-\infty}^{m} \mathbf{T}\_{\rm dq \, - (n+1)} \overline{\mathbf{v}}\_{\rm dq}^{n} \, \, . \tag{5.13}
$$

**v** + dq can be directly used to detect the phase angle with a conventional SRF-PLL. The block diagram containing the DSRF, the 1st-order low-pass filter *G*f*,*DSRF(*s*) (see 5.14), and the SRF-PLL is shown in Fig. 5.20.

$$G\_{\rm t,DSRF}(s) = \frac{\omega\_{\rm I}}{s + \omega\_{\rm I}} \tag{5.14}$$

Compared to the SSM of the LSRF-PLL, the SSM of the DSRF-PLL uses the same assumptions for linearizing the PLL but additionally assumes an ideal phase angle tracking for the decoupling structure, i.e., *δ* = 0 for **T**dq−2 and **T**dq+2 . This is, of course, not valid for severe grid faults but leads to the LTI description and SSM in Fig. 5.21. The linear transfer functions *H*21 and *H*21 were already derived in several publications and are given in 5.15 and 5.16 [52, pp.189-192]. The SSM fidelity of the DSRF for severe grid faults is discussed in section 5.7.

$$H\_{21} = \frac{2\omega\_{\rm I}^2 \omega\_{\rm I} s}{s^4 + 4\omega\_{\rm I} s^3 + 4\left(\omega\_{\rm I}^2 + \omega\_{\rm I}^2\right) s^2 + 8\omega\_{\rm I} \omega\_{\rm I}^2 s + 4\omega\_{\rm I}^2 \omega\_{\rm I}^2} \tag{5.15}$$

$$H\_{22} = \frac{\omega\_{\rm I} \left(s^3 + 2\omega\_{\rm I}s^2 + 4\omega\_{\rm I}^2s + 4\omega\_{\rm I}^2\omega\_{\rm I}^2\right)}{s^4 + 4\omega\_{\rm I}s^3 + 4\left(\omega\_{\rm I}^2 + \omega\_{\rm I}^2\right)s^2 + 8\omega\_{\rm I}\omega\_{\rm I}^2s + 4\omega\_{\rm I}^2\omega\_{\rm I}^2} \tag{5.16}$$

Chapter 5. Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

**Figure 5.20:** LSM of the DSRF.

**Figure 5.21:** SSM of the DSRF.

Based on the SSM, the control transfer function *G*cl*,*DSRF(*s*) is derived to describe the system response to phase angle jumps. According to 5.17, the transfer function is of fourth-order, and depends on the PLL design parameters and the fundamental frequency operating point *ω*1.

$$G\_{\rm cl,DSRF}(s) = \frac{\Delta\theta'}{\Delta\theta} = \frac{H\_{22}(s) \left(k\_{\rm p}s + k\_{\rm i}\right)}{s^2 + H\_{22}(s) \left(k\_{\rm p}s + k\_{\rm i}\right)}\tag{5.17}$$

In contrast to the LSRF-PLL, the DSRF-PLL has two significant disturbance transfer functions. Harmonics in the q-voltage component *v*˜PLL*,*q+ distort the estimated phase angle *θ*0 according to 5.18, and the harmonics in the d-voltage component *v*˜PLL*,*d+ also affect the *θ*0 distortions according to 5.19. However, the two disturbance inputs, i.e., *v*˜PLL*,*q+ and *v*˜PLL*,*d+, can be combined to obtain one disturbance transfer function, which is more convenient for further analysis. The transfer function *H*21 has zero gain for dc-components in *v*+ PLL*,*d and thus the input can be simplified to *v*+ PLL*,*d ≈ *v*˜PLL*,*d+, which only contains oscillatory components. This simplification enables a unified transfer function for both disturbance inputs assuming that *v*˜PLL*,*q+*e*−j *π* 2 ≈ *v*˜PLL*,*d+, i.e., the harmonics in the q-voltage are a 90◦ phase lead version

of the d-voltage harmonics in the steady-state. This leads to the unified complex transfer function *G*d*,*dq*,*DSRF(*s*) given in 5.20 that can be used to calculate the harmonics in *θ* 0 .

$$G\_{\rm d,DSRF}(s) = \left. \frac{\Delta \theta'}{\tilde{v}\_{\rm PL,q+}} \right|\_{v\_{\rm PL,d}^{+}=0} = \frac{1}{\hat{V}\_{\rm S,1}} G\_{\rm cl,DSRF}(s) \tag{5.18}$$

$$G\_{\rm d,2,DSRF}(s) = \left. \frac{\Delta \theta'}{v\_{\rm PL,d}^+} \right|\_{\hat{v}\_{\rm PL,q,+} = 0} = \frac{1}{\hat{V}\_{\rm S,1}} \frac{H\_{21}(s) \left(k\_{\rm p}s + k\_{\rm i}\right)}{s^2 + H\_{22}(s) \left(k\_{\rm p}s + k\_{\rm i}\right)} \tag{5.19}$$

$$G\_{\rm d,dq,DSRF}(s) = \frac{\Delta \theta'}{\tilde{v}\_{\rm PL,q+}} = G\_{\rm d,DSRF}(s) + G\_{\rm d,2,DSRF}(s)e^{-j\frac{\pi}{2}} \tag{5.20}$$

Fig. 5.22 and 5.23 show the SSM and LSM results for a type A and type E fault with |*Z*F|=0.05 pu, *r*F=0 pu, and *r*S=1 pu. The low fault impedance magnitude and large change in the impedance ratio lead to large phase angle jumps and amplitude step. The PLL design parameters are set to *ω*f = 168 rad/s, *k*i = 2402 rad*/*s 2 , and *k*p = 74 rad*/*s according to the design process presented in section 5.7. The SSM predicts a much slower response with a smaller overshoot than the LSM. This characteristic is a first indicator that an analysis based on the SSM may predict a larger stability margin, which is critical since it may lead to wrong design decisions. In contrast, the SSM shows only minor differences to the LSM for the disturbance rejection results presented in Fig. 5.23 and accurately predicts the distortions during a type E fault with large *V UF*. This high SSM accuracy was expected due to the small amplitudes of the harmonics.

**Figure 5.22:** Comparison of SSM and LSM results for the phase angle step response of the DSRF-PLL during a type A fault with *V*ˆ S*,*1 = 0*.*05 pu.

**Figure 5.23:** Comparison of SSM and LSM results for the distortions in *θ* 0 of the DSRF-PLL during a type E fault with maximum negative sequence component and *V UF*=1.

#### **5.2.2 Dual Second Order Generalized Integrator (DSOGI)**

The DSOGI is a sequence decomposition algorithm in *αβ*-frame using two Second Order Generalized Integrators (SOGIs), which are ideal integrators for sinusoidal inputs. They can Chapter 5. Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

**Figure 5.24:** LSM of the DSOGI.

be utilized to generate a 90◦ phase lagged signal from a sinusoidal input, and thus to realize the *q*-operator according to 3.21. The SOGI algorithm contains the two integrators, the gain *k*, and the estimated frequency *ω*0 1. Fig. 5.24 shows the DSOGI with two SOGI blocks and a Positive Sequence Calculator (PSC) containing the matrix given in 3.21, which calculates the positive sequence of the input voltages. The positive sequence voltage **v**+ *αβ* are then used as input for a standard SRF-PLL to estimate the phase angle *θ*0 (comparable to the DSRF-PLL in Fig. 5.20). The estimated frequency of the PLL can be used for *ω*0 1 to make the SOGI frequency adaptive. However, a constant *ω*0 1 tuned to the fundamental grid frequency may also achieve satisfactory results for small frequency deviations.

In *αβ*-frame, the SOGI can be described by the linear transfer functions:

$$\frac{x\_{\alpha}^{\prime}}{x\_{\alpha}} = \frac{x\_{\beta}^{\prime}}{x\_{\beta}} = \frac{k\omega\_{1}^{\prime}s}{s^2 + k\omega\_{1}^{\prime}s + \omega\_{1}^{\prime 2}} \quad , \qquad \frac{qx\_{\alpha}^{\prime}}{x\_{\alpha}} = \frac{qx\_{\beta}^{\prime}}{x\_{\beta}} = \frac{k\omega\_{1}^{\prime 2}}{s^2 + k\omega\_{1}^{\prime}s + \omega\_{1}^{\prime 2}} \quad . \tag{5.21}$$

These expressions assume that the grid frequency *ω*1 is equal to the estimated frequency *ω*0 1. In contrast to the SOGI, the DSOGI-PLL has no direct LTI representation since the SOGI does not have a constant operating point but an operating trajectory in the dq-frame, so that the linearization of the PLL-structure is not straightforward. Two possibilities exist to linearize the system: First, Linear Time-Periodic (LTP) methods can be used to linearize the system based on operating trajectories, but the analysis is rather complex. Second, the equivalence to other decomposition structures, i.e, the DSRF, can be exploited.

Fortunately, the DSRF model sufficiently describes the SSM characteristics of the DSOGI for small deviations from the frequency operating point, enabling equivalent tuning of the design parameters of DSOGI and DSRF [52], [124]. Ref. [124] and [52] prove that the SSMs of DSRF or Multiple Reference Frame (MRF) (proposed in [136]) and DSOGI are identical for 2*ω*f*,*DSRF = *kω*0 1. Of course, frequency and phase angle transients that affect *ω*0 1 lead to differences in the large-signal characteristics.

For verification, the models are tested using the same scenarios as the DSRF-PLL simulations achieving similar results. The PLL parameters are *k* = 0*.*875 rad/s, *k*i = 1484 rad*/*s 2 , and *k*p = 63*.*88 rad*/*s, which are obtained from the design process presented in section 5.7. The transient response for a severe type A fault in Fig. 5.25 shows significant deviations of the SSM and LSM. The LSM predicts a larger overshoot than the SSM. The estimated phase angle distortions show only minor differences between SSM and LSM but reveal larger uncertainties compared to DSRF models (compare Fig. 5.23). These simulation results indicate that the DSRF-SSM approximates the DSOGI characteristics but does not capture all effects, and shows differences beyond simple linearization errors.

**Figure 5.25:** Comparison of SSM and LSM results for the phase angle step responses of the DSOGI-PLL during a type A fault with *V*ˆ S*,*1 = 0*.*05 pu.

**Figure 5.26:** Comparison of SSM and LSM results of the distortions in *θ* 0 of the DSOGI-PLL during a type E fault with maximum negative sequence component and *V UF*=1.

#### **5.3 Control and Disturbance Characterization for PLLs with Prefilters**

The presented decomposition algorithms rely on the sequence calculation in dq-frame and *αβ*-frame. A second possibility exploits the characteristic that the positive and negative sequence components occur at different frequencies in the dq-frame. Several filter approaches realize the desired sequence decomposition by filtering the input signals and attenuating the negative sequence voltage or harmonics.

The sequence extraction needs a high attenuation in a narrow frequency band since positive and negative sequence components are very close to each other in the frequency domain. The Notch-filter (Nf) is the fundamental filter structure to attenuate signals in a narrow frequency band. The Bode plots of the DSRF-PLL (see Fig. 5.41) already show a Nf characteristic for the negative sequence. In general, narrowband filters reject single dominant harmonics without critically affecting the bandwidth, such as low-pass filters, but may deteriorate stability. This thesis focuses on two different filter structures: Notch-filters (Nfs) and Moving Average Filters (MAFs).

#### **5.3.1 Notch-filter (Nf)**

The Nf transfer function given in 5.22 describes its input-output characteristic. The natural frequency *ω*n sets the eigenfrequency of the maximum attenuation, and the damping factor *ζ*f*,*Notch*,n* determines the width of the attenuation peak. The eigenfrequency *ω*n must be tuned to 2*ω*1 to reject the negative sequence component in the dq-frame. Moreover, several dominant grid voltage harmonics can be rejected by using Nfs in a sequence tuned to different *ω*n*,n*, according to:

$$G\_{\rm f,Natch,n}(s) = \prod\_{n=2}^{m} \frac{s^2 + \omega\_{\rm n,n}^2}{s^2 + 2\zeta\_{\rm f,Natch,n}\omega\_{\rm n,n}s + \omega\_{\rm n,n}^2} \quad . \tag{5.22}$$

The Nf can be simply integrated into the LSRF-PLL by replacing the low-pass filter. This results in the Nf-PLL that has the same block diagram as the LSRF-PLL in Fig. 5.2 except for the filter. The transfer functions of the SSM in 5.23 and 5.24 are also similar to the LSRF-PLL and rely on the same assumptions.

$$G\_{\rm cl,Notch}(s) = \frac{\theta'}{\theta} = \frac{G\_{\rm Notch,n}(s) \left(k\_{\rm p}s + k\_{\rm i}\right)}{s^2 + G\_{\rm Notch,n}(s) \left(k\_{\rm p}s + k\_{\rm i}\right)}\tag{5.23}$$

$$G\_{\rm d,Notch}(s) = \frac{\theta'}{\tilde{v}\_{\rm PLL, q+}} = \frac{1}{\hat{V}\_{\rm S, 1}} G\_{\rm cl, Notch}(s) \tag{5.24}$$

Again, the models are tested and verified during a type A and type E fault with |*Z*F|=0.05 pu, *r*F=0 pu, and *r*S=1 pu. The tested Nf-PLL contains three cascaded notch-filters tuned to the angular frequencies 2*ω*1, 3*ω*1, and 6*ω*1. The other design parameters are *ζ*f*,*Notch = 1*.*03, *k*i = 2016 rad*/*s 2 , and *k*p = 78*.*54 rad*/*s. How these parameters are derived based on the grid requirements is shown in section 5.7. In contrast to the DSRF and DSOGI-PLL, the SSM yields similar characteristics as the LSM for the transients and steady-state distortions. The reason may be that the Nf-PLL is not frequency adaptive, which reduces the number of assumptions for deriving the SSM. However, the overshoot is slightly larger in the LSM results than predicted by the SSM.

The Nf is a potent algorithm to reject the negative sequence voltage component in PLL algorithms. It can also sufficiently reject harmonics in the grid voltages. However, the dominant harmonics must be known a priori to tune the natural frequencies of the cascaded Nf. MAFs may provide a more efficient solution to reject all harmonics with frequencies that are multiples of the fundamental grid frequency.

**Figure 5.27:** Comparison of SSM and LSM of the Nf-PLL during a type A fault with *V*ˆ S*,*1 = 0*.*05 pu.

**Figure 5.28:** Comparison of SSM and LSM of the Nf-PLL during a type E fault with maximum negative sequence component and *V UF*=1.

#### **5.3.2 Enhanced Moving Average Filter with Prefiltering Stage (EP-MAF)**

The Enhanced Moving Average Filter with Prefiltering Stage (EPMAF)-PLL is based on Moving Average Filters (MAFs) described by the transfer functions:

$$G\_{\rm MAP}(s) = \frac{1 - e^{-sT\_{\rm MAP}}}{sT\_{\rm MAP}} \Rightarrow \qquad G\_{\rm MAP}(z) = \frac{1}{N} \frac{1 - z^{-N}}{1 - z^{-1}} \ . \tag{5.25}$$

They contain a deadtime term and an integrator tuned with the averaging time constant *T*MAF. This filter shows a Nf characteristic for all frequencies that are integer multiples of 1*/T*MAF, and thus rejects all harmonics with these frequencies. This function is not linear, but the deadtime has an accurate representation in the z-domain, and its discrete transfer function with *NT*s = *T*MAF is given in 5.25 [137],[120].

The MAF serves as a prefilter for the SRF-PLL to reject the negative sequence voltages and voltage harmonics. It is applied to the dq-transformed voltages using an angle *θ* generated with a constant frequency and arbitrarily chosen starting angle. The filtered voltages are processed in the SRF-PLL structure, as shown in Fig. 5.29. As a drawback, the algorithm suffers from steady-state error in the amplitude and frequency detection as presented in [120]. Therefore, the EPMAF-PLL consists of an additional amplitude and phase error correction, which were proposed by Golestan in [120]. Details on the mathematical background are provided in [120] and not repeated here. The additional parameters *kv* and *kϕ* of the EPMAF-PLL result directly from the MAF design parameters as follows:

$$k\_{\varphi} = \frac{1}{2} \left( T\_{\text{MAF}} - T\_{\text{s}} \right) \quad , \qquad k\_{v} = T\_{\text{MAF}}^2 / 24 \quad . \tag{5.26}$$

**Figure 5.29:** LSM of the EPMAF-PLL.

The control transfer function was already derived in [120] and is given in 5.27 for the sake of completeness. The disturbance transfer function in 5.28 is derived based on this control transfer function. These two functions describe the SSM of the EPMAF-PLL.

$$G\_{\rm cl,MAF}(s) = \frac{\theta'}{\theta} = \frac{k\_{\rm p}s + k\_{\rm i}}{s^2 + (k\_{\rm p} - k\_{\rm i}k\_{\varphi})s + k\_{\rm i}} G\_{\rm MAF}(s) \tag{5.27}$$

$$G\_{\rm d,MAF}(s) = \frac{\theta'}{\tilde{v}\_{\rm PLL,q+}} = \frac{1}{\left(\hat{V}\_{\rm S,1} + \hat{V}\_{\rm S,-1}\right)} G\_{\rm c1,MAF}(s) \tag{5.28}$$

**Figure 5.30:** Comparison of SSM and LSM results for the phase angle step response of the EPMAF-PLL during a type A fault with *V*ˆS*,*1 = 0*.*05 pu.

**Figure 5.31:** Comparison of SSM and LSM results for the distortions in *θ*0 of the EPMAF-PLL during a type E fault with maximum negative sequence component and *VUF*=1.

A first test of the SSM for the transient and steady-state characteristics in the same scenario as the Nf-PLL shows just minor differences compared to the LSM. The results for the phase angle step response and disturbance rejection are shown in Fig. 5.30, and Fig. 5.31, respectively. The design parameters are *T*MAF = 20 ms, *kϕ* = 0*.*01 s, *kv* = 16*.*7 *µ*s2, *k*i = 2500 rad*/*s 2 , and *k*p = 108*.*4 rad*/*s. For the detailed design process, refer to section 5.7.

The derived PLL-SSMs accurately describe the disturbance rejection but show significant differences during severe transients compared to the LSMs. However, these characteristics sensitively depend on the scenarios and the chosen design parameters. The worst-case scenarios were already derived in section 5.1, and thus the next section discusses the PLL design based on the derived models, Symmetrical Optimum (SO), and required immunity to distortions as the first design approach.

### **5.4 PLL Control Bandwidth Design based on the Required Distortion Attenuation utilizing SSMs**

The PLL parameter design crucially affects the PLL performance in the steady-state and during transients. The LSRF-PLL is a standard type 2 control plant that can be described by the generic open-loop transfer function:

$$G\_{\rm al}(s) = \frac{k\left(s + \omega\_{\rm s}\right)}{s^2\left(s + \omega\_{\rm p}\right)} = \frac{k\_{\rm p}\omega\_f\left(s + \frac{k\_{\rm f}}{k\_{\rm p}}\right)}{s^2\left(s + \omega\_f\right)}\ \ ,\tag{5.29}$$

where *k* is the open-loop gain, and *ω*z and *ω*p are angular frequencies. The symmetric optimum is an approach to design these control structures [138], [139]. The basic idea is to maximize the phase margin *PM* of the system to achieve a desired stability margin [131], [124]. This approach exploits the symmetry of the open-loop Bode plots regarding the crossover frequency *ω*c with the corner frequencies *ω*z and *ω*p, as shown in Fig. 5.32 and 5.33.

Fig. 5.32 further includes an approximation of the transfer function in 5.29, assuming two corner frequencies *ω*z and *ω*p that have both the same distance to *ω*c. Below or above *ω*z and *ω*p, respectively, the magnitude decreases with -40 dB/dec, and in between with -20 dB/dec. The phase plot in Fig. 5.33 illustrates the phase of the open-loop transfer function *G*ol and indicates symmetry around *ω*c. Notable is the fact that the phase margin *PM* reaches its maximum at the crossover frequency *ω*c. But how can this be achieved?

**Figure 5.32:** Magnitude Bode plot of the openloop transfer function of the LSRF-PLL presenting the parameters of a generic type 2 control structure.

**Figure 5.33:** Phase angle Bode plot of the openloop transfer function of the LSRF-PLL presenting the parameters of a generic type 2 control structure.

Golestan already presents in [124] how the symmetric optimum can be applied to LSRF-PLLs. The derivation is repeated here for the sake of completeness. *PM* depends on the three frequencies *ω*z, *ω*c, and *ω*p. The phase of the transfer function in 5.29 can be calculated and results in *PM* according to 5.30, which depends on *ω*z, *ω*c, and *ω*p.

$$PM = -\left(-\pi - \angle G\_{\text{al}}(j\omega\_{\text{c}})\right) = \pi + \left(-\pi + \underbrace{\tan^{-1}\left(\omega\_{\text{c}}/\omega\_{\text{d}}\right)}\_{\phi\_{\text{b}}} - \underbrace{\tan^{-1}\left(\omega\_{\text{e}}/\omega\_{\text{p}}\right)}\_{\phi\_{\text{p}}}\right) \tag{5.30}$$

Then, the general definition of the cross-over frequency leads to the first design rule:

$$|G\_{\rm al}(j\omega\_c)| = 1 \Rightarrow \qquad \omega\_c = k\_p \frac{\cos\left(\phi\_{\rm p}\right)}{\sin\left(\phi\_{\rm a}\right)} \Rightarrow \qquad \omega\_c = k\_{\rm p} \quad . \tag{5.31}$$

Since the SO basically maximizes *PM* to guarantee a large stability margin, *ω*c can be calculated as follows:

$$
\partial PM/\partial \omega\_c = 0 \Rightarrow \qquad \omega\_c = \sqrt{\omega\_\mathbf{k} \omega\_\mathbf{p}} \quad . \tag{5.32}
$$

Rearranging the expressions by introducing an arbitrary constant *a* 2 = *ω*p *ω*z results in 5.33 and leads to the design rule for *k*i and *ω*f, so that the LSRF-PLL design parameters are entirely described by choosing *ω*c and *a* according to:

$$a^2 = \frac{\omega\_p}{\omega\_x} \Rightarrow \qquad \qquad PM = \tan^{-1}\frac{a^2 - 1}{2a} \tag{5.33}$$

$$
\Rightarrow \qquad \qquad \qquad \qquad \omega\_{\rm f} = a\omega\_{\rm c} \tag{5.34}
$$

$$\Rightarrow \qquad \qquad k\_{\rm i} = \frac{k\_{\rm p} \omega\_{\rm c}}{(2\zeta + 1)} \quad . \tag{5.35}$$

The detailed derivation of equations 5.30-5.33 is given in Appendix A.3. This description simplifies the open-loop and closed-loop transfer functions and indicates that *a* corresponds to the damping ratio *ζ* of the closed-loop poles, as described by:

$$G\_{\rm cl}(s) = \frac{a\omega\_c^2 \left(s + \frac{\omega\_c}{a}\right)}{s^2 \left(s + a\omega\_c\right)} \Rightarrow \qquad G\_{\rm cl}(s) = \frac{\theta'}{\theta} = \frac{(2\zeta + 1)\omega\_c^2 \left(s + \frac{\omega\_c}{\left(2\zeta + 1\right)}\right)}{\left(s + \omega\_c\right)\left(s^2 + 2\zeta\omega\_c s + \omega\_c^2\right)}\ . \tag{5.36}$$

Hence, introducing *a* = 2*ζ* + 1 yields the closed-loop transfer function *G*cl with one real pole at −*ω*c and one pole-pair at −*ω*c with *ζ* as damping factor. The desired control bandwidth *ω*c and damping factor *a* determine the three design parameters of the LSRF-PLL. For most applications, the optimum trade-off between overshoot and settling time is achieved by *ζ* = 1*/* √ 2, which corresponds to *a* = 2*.*41 [124]. This leaves the control bandwidth as degree of freedom for PLL design. It should be designed to comply with the necessary immunity to distortions. With the resulting design parameters, the PLL dynamics can be evaluated.

The necessary attenuation of the PLL results from the grid voltage harmonics and the maximum distortions of the estimated phase angle. The maximum control bandwidth *ω*c can be calculated to achieve the necessary attenuation atten*ω*d of |*G*ol| at an angular frequency *ω*d, according to [140]:

$$\text{atten}\_{\omega\_d} \approx |G\_{\text{cl}}\left(j\omega\_{\text{d}}\right)| \approx -20 \log \frac{\omega\_{\text{d}}}{\omega\_c} - 20 \log \frac{\omega\_{\text{d}}}{\omega\_p} = -20 \log \frac{\omega\_{\text{d}}^2}{\omega\_p \omega\_c} \qquad , \tag{5.37}$$

$$
\text{atten}\_{\omega\_{\text{d}}} = -40 \log \left( \frac{\omega\_{\text{d}}}{\omega\_{\text{c}} \sqrt{a}} \right) \Leftrightarrow \omega\_{\text{c}} = \frac{\omega\_{\text{d}}}{\sqrt{a}} 10^{\left(\frac{\text{att-on}\_{\omega\_{\text{d}}}}{40}\right)} \ . \tag{5.38}$$

This approach is suitable for a single dominant harmonic in the grid voltage but may fail for complex spectra. The disturbance transfer function *G*d given in 5.5 leads to a more accurate description of the distortions of the estimated phase angle. The attenuation for every single voltage harmonic |*G*d (*nω*1)| is calculated and multiplied with the amplitude |*v*˜PLL*,*q+ (*nω*1)|. The voltage harmonics *v*˜PLL*,*q+ occur at frequencies 2*ω*1 and 3*nω*1 due to the frequency shift of +*ω*1 of Park's transformation and the varying sequences of the harmonics according Table 3.3. The resulting amplitudes of the phase angles can be summed up for a worst-case approximation of the harmonic amplitude of ∆*δ*. The worst-case estimate neglects the phase shift between different harmonics to yield an accurate upper boundary of the distortions of ∆*δ* as follows:

$$
\Delta \delta = \left| G\_{\rm d} \left( 2 \omega\_1 \right) \right| \left| \tilde{v}\_{\rm PL, q+} \left( 2 \omega\_1 \right) \right| + \sum\_{n=1}^{8} \left| G\_{\rm d} \left( 3n \omega\_1 \right) \right| \left| \tilde{v}\_{\rm PL, q+} \left( 3n \omega\_1 \right) \right| \quad . \tag{5.39}
$$

The SO is a potent method to reduce the design parameter count of the LSRF-PLL, and guarantees the defined stability margin. It can be applied to sophisticated PLLs, but may not achieve the same accuracy in the control bandwidth, immunity to distortions, and stability margin due to the different transfer characteristics. Therefore, the impact of the SO on the presented PLLs is discussed in the following section.

#### **5.4.1 Is the Symmetrical Optimum Applicable for Prefiltered SRF-PLLs?**

Most PLLs with advanced prefilters contain an additional Nf characteristic compared to the LSRF-PLL. Originally, the SO is not applicable for these characteristics since the derived expressions, particularly for the *PM* in 5.30, are not valid anymore. But how do the Nf characteristic affects the SO design rules in detail?

The SO maximizes the phase margin of the open-loop transfer function of the LSRF-PLL. Typical phase margins for a robust characteristic are in the range of *PM >* 30◦ [124]. This requirement guarantees stability since the LSRF-PLL has an infinite gain margin. However, PLLs with prefilter or decomposition algorithms have a finite gain margin due to the 180 degree phase cross-over caused by the notch characteristic. The gain margin mainly

**Figure 5.34:** Phase margin of LSRF-PLL for different design parameters *ζ* and *ω*c with the hashed robust region of *PM >* 30◦ .

**Figure 5.35:** Phase margin of DSRF-PLL for different design parameters *ζ* and *ω*c with the hashed robust region of *PM >* 30◦ .

depends on the open-loop gain, which is critically affected by the voltage amplitude of the fundamental frequency component *V*ˆ S*,*1, as shown in Fig. 5.2. Hence, a deviation in *V*ˆ S*,*1 will directly change the PLL open-loop gain. The ANS suppresses this effect since it normalizes the PLL input to the instantaneous grid voltage amplitude *V*ˆ S*,*1. Consequently, the gain margin is not directly affected by grid voltage steps anymore, and the *PM* also serves as primary robustness criteria for PLLs with prefilter or sequence decomposition.

The design parameters of the DSRF and DSOGI-PLL are equivalent to the LSRF-PLL. They all contain the low-pass filter and the PI-controller parameters that can be simplified to a damping ratio *ζ* and the control bandwidth *ω*c. However, the impact of the design parameters *ζ* and *ω*c on the phase margin differs significantly. Fig. 5.34 shows the phase margin of the LSRF-PLL for different design parameters and indicates the robust design parameter range with *PM >* 30◦ . As expected, the phase margin only depends on *ζ* for the full parameter range. In contrast, the phase margin of the DSRF-SSM (see Fig. 5.35) also depends on *ω*c, but the difference between the designed and real *PM* is neglectable for control bandwidths below *ω*c *<* 80 rad*/*s. This control bandwidth boundary indicates the range where the SO can be applied without checking the *PM* separately. The results are also valid for the DSOGI-PLL due to the equivalence to the SSM of the DSRF-PLL.

The Nf and EPMAF-PLL have a much more apparent notch characteristic in their control behavior and do not contain an explicit low-pass filter. Nevertheless, their design can also be simplified to two parameters, i.e., the PI-controller parameters are fixed by choosing the desired damping ratio *ζ* and control bandwidth *ω*c. In contrast to the other PLLs, the filter frequency of Nf and EPMAF is set to the dominant harmonics. For the Nf-PLLs, the PI parameter design is equivalent to the LSRF-PLL. The Nf is tuned to reject the first three dominant harmonics: 2*ω*1, 3*ω*1, and 6*ω*1, and the corresponding damping ratios are equal *ζ*Notch = *ζ*f*,*Notch*,*2*ω*1 = *ζ*f*,*Notch*,*3*ω*1 = *ζ*f*,*Notch*,*6*ω*1 .

The phase margin of the Nf-PLL presented in Fig. 5.36 critically depends on the damping ratio and control bandwidth. The damping ratio alters the bandwidth of the notch attenuation peak. A higher damping ratio leads to a larger bandwidth of the attenuation peak, which thus affects the control characteristics in a wider frequency range. This effect is verified for small damping ratios of *ζ <* 0*.*1, where the *PM* does not depend on *ω*c anymore, as shown in Fig. 5.36. However, low damping ratios with a narrow frequency band of the notch attenuation cause the immunity to distortions to deteriorate during frequency variations, which will be discussed in detail in the next section.

EPMAF-PLLs significantly differ in their transfer characteristic to the other PLLs and thus show different dependencies of the PI design parameters. Equ. 5.40 and 5.41 give the design rules derived in [120] and indicate that *k*i and *k*p only depend on the natural frequency *ω*n*,*EPMAF, and the damping *ζ* according to:

$$k\_{\rm i} = \omega\_{\rm n,EPMAF}^2 \quad , \tag{5.40}$$

$$k\_{\rm p} = 2\zeta\_{\rm EPMAF}\omega\_{\rm n,EPMAF} + k\_{\varphi}k\_{\rm i} \quad . \tag{5.41}$$

For a more convenient presentation, the natural frequency *ω*n*,*EPMAF will be denoted with *ω*c*,*EPMAF, even though it does not represent the cross-over frequency. The EPMAF filter design is already presented in section 5.3.2 and does not offer a degree of freedom.

Fig. 5.37 presents the phase margin analysis for the EPMAF-PLL. Surprisingly, two robust design regions appear since it does not matter if the gain margin is positive or negative. A large damping ratio is desirable in the lower frequency range to achieve a robust design. Contrarily, the damping ratio does not critically affect *PM* for higher frequencies.

**Figure 5.36:** Phase margin of Nf-PLL for different design parameters *ζ* and *ω*c with the hashed robust region of *PM >* 30◦ .

**Figure 5.37:** Phase margin of EPMAF-PLL for different design parameters *ζ* and *ω*c with the hashed robust region of *PM >* 30◦ or *PM <* −30◦ .

In summary, the SO can be applied to PLLs with prefilters or sequence decomposition and provides a suitable design scheme to reduce the design parameters. It is evident that the prefilter or decomposition alter the phase margin and additionally introduce a gain margin

**Figure 5.38:** Harmonic spectrum of *v*˜PLL*,*q+ considering fundamental frequency variations in the range of 47.5 Hz to 51.5 Hz.

**Figure 5.39:** Estimated phase angle distortions of the EPMAF-PLL, and the definition of the maximum distortion of the estimated phase angle ˆ*δ* is introduced.

to the control system. The gain margin is not critical due to the ANS, whereas the phase margin must be analyzed thoroughly for any PLL. According to [124], the bandwidth *ω*c of PLLs with prefilters have to be one/fifth of the notch frequency. However, this is not valid in general, as shown in the previous analysis. Hence, the *PM* must be checked for every design parameter set for advanced PLLs to ensure robust control behavior.

#### **5.4.2 SSM-based Design of PLLs utilizing the SO**

The presented *PM* analysis is crucial to guarantee PLL stability that is the mandatory requirement for the design. Moreover, the immunity to distortions is another crucial performance indicator in steady-state and critical concerning grid standards. Once the necessary immunity to distortions reduced the number of feasible design parameters, the evaluation of the step responses must be only applied to the left design parameter space.

The grid voltage harmonics presented in Fig. 5.15 distort the error of the estimated phase angle *δ* and the converter's power factor *λ*. These distortions can be predicted with the disturbance transfer function *G*d applying the harmonic spectrum *v*˜PLL*,*q+ as input. For the analysis, the harmonic spectrum is first transformed into the dq-frame since the PLL disturbance input is defined by *v*˜PLL*,*q+. Possible deviations in the fundamental frequency also change the frequencies of the harmonics leading to a frequency-shift of the voltage spectrum. The superimposed spectra of *v*˜PLL*,*q+ for all fundamental frequencies is shown in Fig. 5.38 and serve as input for the disturbance transfer functions of the PLLs to determine the immunity to voltage distortions.

The maximum deviation in the error of the phase angle is described by ˆ*δ*, see Fig. 5.39. The distortion magnitude ˆ*δ* is a superposition of the voltage harmonics attenuated by *G*d. Fig. 5.40 and Fig. 5.41 show the disturbance spectrum at the LSRF and DSRF-PLL output denoted with ˆ*δn* resulting from |*G*d||*v*˜PLL*,*q+| for all fundamental frequencies. The spectrum ˆ*δn* is a superposition of the spectra of ˆ*δ* for each fundamental frequency, and the spectrum

**Figure 5.40:** Disturbance transfer function *G*d and output distortions ˆ*δn* of the LSRF-PLL considering fundamental frequency variations.

**Figure 5.42:** Disturbance transfer function *G*d and output distortions ˆ*δn* of the Nf-PLL considering fundamental frequency variations.

**Figure 5.43:** Disturbance transfer function *G*d and output distortions ˆ*δn* of the EPMAF-PLL considering fundamental frequency variations.

for one fundamental frequency can be extracted by choosing the respective *ω*1 and taking all components of ˆ*δn* with *nω*1. Note that *G*d for the DSRF-PLL must be calculated separately for each fundamental frequency since the algorithm is frequency adaptive, and the transfer function changes with the fundamental frequency.

The superimposed spectrum ˆ*δn* for the Nf-PLL and EPMAF-PLL are presented in Fig. 5.42 and 5.43, respectively. The results for ˆ*δn* indicate that the varying fundamental frequency critically affects the immunity to distortions, particularly at higher frequencies. Higher-order harmonics experience a larger frequency shift than low-order harmonics due to the relation *nω*1 = *nω*1*,*n ± *n*∆*ω*1. These results demonstrate that the notch bandwidth is crucial for the disturbance rejection since frequency deviations may lead to loss of its attenuation, as shown in Fig. 5.42 for the Nf and Fig. 5.43 for the EPMAF.

Due to the frequency variations, it is complicated to evaluate the maximum estimated phase angle distortion ˆ*δ* based on these spectra. However, an estimate of the worst-case for ˆ*δ* can Chapter 5. Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

be achieved by summing up all harmonic amplitudes for one fundamental frequency value *ω*1 according to:

$$\hat{\delta}\_{m} = \left| G\_{\rm d} \left( 2 \omega\_{1,m} \right) \right| \left| \tilde{v}\_{\rm PL, q+} \left( 2 \omega\_{1,m} \right) \right| + \sum\_{n=1}^{8} \left| G\_{\rm d} \left( 3n \omega\_{1,m} \right) \right| \left| \tilde{v}\_{\rm PL, q+} \left( 3n \omega\_{1,m} \right) \right| \quad. \tag{5.42}$$

Then, the range of *ω*1 can be sampled with a sufficiently low step ∆*ω*1 to capture a subset of all possible *ω*1. The interval 47*.*5 Hz *< ω*1*/*(2*π*) *<* 51*.*5 Hz is sampled with *M* equidistant steps *m* with ∆*ω*1, which leads to ˆ*δ*:

$$
\hat{\boldsymbol{\delta}} = \begin{bmatrix} \hat{\boldsymbol{\delta}}\_1 & \dots & \hat{\boldsymbol{\delta}}\_m & \dots & \hat{\boldsymbol{\delta}}\_M \end{bmatrix} \quad . \tag{5.43}
$$

Finally, the maximum expectable distortion magnitude ˆ*δ*wc for one design parameter combination *ω*c and *ζ* can be derived as follows:

$$
\hat{\delta}\_{\text{we}} = \max \hat{\delta}\left(\omega\_c, \zeta\right) \quad . \tag{5.44}
$$

This estimate neglects the phase of the harmonics, which is difficult to approximate for every single operating condition. However, the chosen assumptions always guarantee the condition ˆ*δ* ≤ ˆ*δ*wc.

The design parameter space is finally reduced, respecting the stability and immunity to distortions. Now, the settling time can be extracted to achieve optimum design parameters. In the range of *ζ* = 0 − 1, the difference between the settling times of frequency response and phase angle response is neglectable (Fig. 13 in [124]). Hence, the settling time of the estimated phase angle error for a phase angle jump serves as an indicator for the dynamic performance. The settling time is defined as the time interval from fault initiation until the error of the estimated phase angle enters a defined tolerance band and stays within its boundaries. The tolerance band is chosen to 5 mrad according to the maximum distortions of the power factor presented in section 5.1. This definition is presented in Fig. 5.44. Note that the tolerance band is larger in the figure for visualization purpose.

The type A fault is the most critical disturbance for PLLs, considering the phase angle jump and voltage magnitude steps. This fault can be simplified to −*π/*2 phase angle jump since the voltage amplitude step does not affect the SSM step response. The optimum design can then be extracted by finding the minimum settling time min *t*set*,δ* respecting mandatory immunity to distortions ˆ*δ*wc *<* 5 mrad. The overall optimization is defined as follows:

$$\min\_{\omega\_c, \zeta\_c} \quad t\_{\text{sat}, \delta} \left(\omega\_c, \zeta\right) \qquad \text{s.t.} \qquad \hat{\delta}\_{\text{we}} \leqslant \delta\_{\text{max}} \quad . \tag{5.45}$$

The overall design process can be summarized as presented in Fig. 5.45. First, the design parameter space *ω*c*, ζ* is chosen and sampled with a predefined resolution that leads to a design parameter matrix with *y* x *z* entries containing all sampled combinations of *ω*c and *ζ*.

**Figure 5.44:** Definition of the settling time *t*set*,δ* for the step response of the phase angle error by using a tolerance band to define the steady-state.

**Figure 5.45:** Design process for PLLs considering the necessary immunity to distortions ˆ*δ*wc *< δ*max and optimizing the settling time *t*set*,δ*.

For every design parameter set *ω*c*,g* and *ζh*, the maximum estimated phase angle distortion ˆ*δ*wc is calculated with *G*d during a type E fault with |*Z*F|=0 pu, |*Z*S|=1 pu, *r*F=0 pu, and *r*S=1 pu. Then, the algorithm checks if ˆ*δ*wc *< δ*max is achieved for these design parameters. If not, the next parameter set is calculated since this parameter combination does not comply with the necessary constraint. If the requirement is fulfilled, the settling time of the estimated phase angle *t*set*,δ* is calculated based on the control transfer function *G*cl. A type A fault serves as a worst-case scenario assuming the grid parameters |*Z*F|=0.05 pu, |*Z*S|=1 pu, *r*F=0 pu, and *r*S=1 pu and *f*1 = 50 Hz. Since the magnitude step does not affect the SSM, the scenario is replaced by an -90 degree phase jump. These steps are repeated for all sampled parameter combinations. Finally, the parameter set *ω*c*,g* and *ζh* with the minimum settling time min *t*set*,δ* is the outcome of this optimization. The final parameters ensure the necessary immunity to distortions while achieving the fastest settling for the designed PLL.

The settling times for the analyzed design parameter space [*ω*c *ζ*] are shown in the following figures. The parameters of the hashed surface ˆ*δ*wc *>* 5 mrad violate the immunity to distortions

**Figure 5.46:** Settling time of the phase angle error *t*set*,δ* of the LSRF-PLL for different design parameter sets *ω*c and *ζ*, and identification of the set for minimum settling time considering the maximum distortion criteria and indicating the robustness.

**Figure 5.47:** Settling time of the phase angle error *t*set*,δ* of the DSRF-PLL for different design parameter sets *ω*c and *ζ*, and identification of the set for minimum settling time considering the maximum distortion criteria and indicating the robustness.

criterion, whereas the robustness region *PM <* 30◦ ∧ *PM >* −30◦ is only a performance indicator for the design. The LSRF-PLL only achieves low *ω*c due to the low disturbance rejection capability of the low-pass filter, as shown in Fig. 5.46. The damping ratio directly adjusts the control robustness and does not depend on *ω*c. Surprisingly, the conventional damping ratio of 1*/* √ 2 does not achieve the minimum settling time, but should be increased to 0.78. Note that the PT2 behavior in combination with an absolute settling tolerance leads to steps in the settling times from one design parameter set to the other.

The DSRF-PLL enables much larger control bandwidth *ω*c due to the enhanced filter capability of the sequence decomposition. This characteristic is highlighted in the settling time results in Fig. 5.47, where the mandatory immunity to distortions does not critically limit the allowed design parameter space. For the DSRF-PLL, the maximum *ω*c is predominantly limited by the stability. However, the minimum settling time is achieved for [*ω*c *ζ*] with enough distance to both boundaries, i.e., to the disturbance rejection and robustness limits. Since these results rely on the SSM, they are also valid for the DSOGI-PLL.

Even though the Nf has a high distortion attenuation, the Nf-PLL bandwidth is strictly limited by the immunity to distortions, as presented in Fig. 5.48. This significant difference to the DSRF results from the missing frequency adaptivity of the Nf. The robustness region is not of interest since the required immunity to distortions already covers it. The settling times of the EPMAF-PLL are presented in Fig. 5.49 and demonstrate that the maximum control bandwidth is also strictly limited by the immunity to distortions. Moreover, the resulting design parameter set for the minimum settling time has a *PM* ≤ 30, indicating a small stability margin.

The proposed design, which considers the optimization of *ζ* by finding *ζ*opt and *ω*c*,*opt, is compared to the conventional approach with *ζ*0*.*7 = 0*.*7 and *ω*c*,*0*.*7. Table 5.2 summarizes the results of the PLL designs. The control bandwidths do not show significant differences except for the Nf-PLL, whereas the damping ratios significantly differ from *ζ*0*.*7. Three of four PLLs

**Figure 5.48:** Settling time of the phase angle error *t*set*,δ* of the Nf-PLL for different design parameter sets *ω*c and *ζ*, and identification of the set for minimum settling time considering the maximum distortion criteria and indicating the robustness.

**Figure 5.49:** Settling time of the phase angle error *t*set*,δ* of the EPMAF-PLL for different design parameter sets *ω*c, and *ζ* and identification of the set for minimum settling time considering the maximum distortion criteria and indicating the robustness.

**Table 5.2:** Design parameter results for the presented optimization process considering the phase angle settling time and the immunity to distortions.

achieve a larger *ζ* indicating better damping compared to the conventional design.

However, the design parameters do not explicitly indicate the steady-state and dynamic PLL performance. Therefore, ˆ*δ*wc, *t*set*,δ*, and *PM* are shown for the proposed and conventional design as indicators for the immunity to distortions, dynamic performance, and robustness. The settling time decreases significantly for each analyzed PLL, and the most significant decrease of 50% is achieved for the Nf-PLL. The maximum output distortion slightly increases for the optimum design but never exceeds the limit of 5 mrad. Moreover, in three of four cases, the *PM* is increased. Only for the Nf the *PM* decreases but does not enter a critical region. These results highlight the effectiveness of the proposed design procedure and show that the damping ratio *ζ*0*.*7 = 0*.*7 is not the optimum case for the minimum settling time considering an absolute tolerance band of 5 mrad.

The presented design process relies on the model fidelity of the SSMs. Moreover, the settling time is only determined for a single worst-case scenario. Two validation steps are presented in the next section to confirm the models and worst-case design results. First, the SSM results are compared to the LSM results for type E and type A faults with various sag depths to capture more operating points and proof model fidelity. Second, an experiment is designed to validate the SSMs and LSMs under realistic operating conditions. The experiment also consists of various fault scenarios, not only focusing on the worst-case.

**Table 5.3:** Performance parameters for the conventional and optimized design considering ˆ*δ*wc, *t*set*,δ*, and *PM*.

### **5.5 PLL Model Validation with RCP-System and SiC Converter Prototype**

A realistic test environment for PLLs consists of an adjustable three-phase voltage source, voltage measurements, and the controller hardware that processes the PLL-algorithms. The voltage source must meet three essential requirements: First, it must be adjustable in a wide range to enable fault voltage emulation with arbitrary voltage magnitudes and angles in the three phases in the range of 0-1.2*V*ˆ S*,*1. Second, the voltage source bandwidth must be high enough to enable accurate emulation of harmonics and fast magnitude steps and angle jumps. As a third point, the instantaneous phase angle *θ*, and the positive and negative sequence voltage magnitudes must be known to compare them to the PLL output. All these requirements are met by the realized SiC-converter prototype that provides the adjustable grid voltage **v***C* at its filter capacitor output.

Three LEM LV-25P voltage sensors measure **v***C*, and transform them into analog signals that are captured by the ADCs of the RCP-system. The algorithms in the RCP-system are processed in the FPGA and the CPU. In the following tests, the CPU calculates the voltage reference **v** ∗ abc and executes the PLL algorithms. The FPGA generates the switching signals for the converter applying SPWM and transmits the measured voltages **v***C* to the CPU. Finally, the PLL output signals are compared to the reference values to calculate the error of the estimated phase angle *δ*. The overall setup is presented in Fig. 5.50, and the parameters are summarized in Table 5.4.

The voltage waveform comparison of the reference voltages **v** ∗ abc generated by the RCP-system and the instantaneous output voltages of the converter **v***C* show just minor differences, as shown in Fig. 5.51. However, two problems are identified in the measured error of the estimated phase angle *δ*. The first problem is that the measured phase angle error contains a dc-offset due to the phase shift between the voltages **v** ∗ abc and **v***C* caused by the *LC*-filter. The offset is almost identical for all PLLs and does not depend on the operational scenario. The

**Figure 5.50:** Test bench consisting of an RCPsystem and SiC-converter prototype to validate PLL models with emulated grid voltages considering the ADCs, measurements, and control unit execution time.

**Table 5.4:** Parameters of the test bench for PLL model validation.

**Figure 5.51:** Comparison of reference voltages **v** ∗ abc given to the SPWM and output voltage of the converter **v***C* during a type E fault (without zerosequence voltage) with |*Z*F|=0.1 pu, *r*F=0 pu, and *r*S=10 pu, and voltage harmonics according to EN 50160 [38].

**Figure 5.52:** Filter for dc-components in the measured grid voltages consisting of a moving average filter and a saturation to limit the impact on the PLL dynamics.

offset is shown in the raw data of the DSRF-PLL steady-state in Fig. 5.54 and is compensated in the following analysis. The second problem is based on a dc-offset in the measured grid voltages and is more complicated to solve.

The measured estimated phase angle error demonstrates that PLLs in the SRF are vulnerable to dc-offsets in the input voltages. These dc-components lead to 50 Hz oscillations in the dq-components that are difficult to filter due to their low frequency. Several approaches are proposed in the literature to overcome this problem [134], [141], [142]. Here, a simple structure containing a low-pass filter with a saturated output is used, see Fig. 5.52. The mean operator is tuned to 50 Hz and the lower and upper limit of the saturation to -0.5 V and 3 V, respectively. The saturation prevents that the compensation deteriorates the PLL dynamics. The tuning was the same for every PLL and not changed during all analyzed scenarios, which shows the low sensitivity of the dc-offset on the operating point.

**Figure 5.53:** Step response results for the DSRF-PLL with and without mean compensation during a type E fault with |*Z*F*,*typeE| = 0*.*01. The minor impact of the dc-component rejection on the dynamics is visible.

**Figure 5.54:** 50 Hz oscillation in the error of the estimated phase angle during a type E fault with |*Z*F*,*typeE| = 0*.*01 due to dc-components in the measured grid voltages that mainly result from sensor offsets, and their successful rejection by the proposed mean filter. The constant error of 30 mrad results from the phase-shift caused by the *LC*-filter.

For validation, the dc-filter is tested for the DSRF-PLL. The 50 Hz component is successfully rejected and the dynamics are not significantly affected, as shown in Fig. 5.53 and Fig. 5.54. From the author's point of view, it is not helpful to derive a general design rule, since the dc-component critically depends on the system under investigation, and the dc-filter should be directly designed for the individual hardware setup.

The presented setup enables validation of the PLL-models under realistic operating conditions. The following sections show the results for the PLL performance indicators, i.e., settling time and distortion of the estimated phase angle, in comparison to the offline-simulation results for different grid scenarios.

#### **5.5.1 Steady-State Distortion Rejection during Type E Faults**

The PLL's immunity to distortions is tested during type E faults with different positive sequence voltages or |*Z*F*,*typeE|, respectively. The fundamental frequency operating point is 47.5 Hz representing the worst-case for most of the PLLs. The maximum distortion ˆ*δ* is measured according to Fig. 5.39. Since the distortions are limited to small values below 5 mrad, the SSM, LSM, and Experiment (EXP) should achieve similar results.

Fig. 5.55 and 5.56 confirm these expectations and show only minor differences. However, the relative error is comparably large for some PLLs and fault cases, e.g., the DSRF has the most significant error with approximately 50%. Nevertheless, absolute tolerance is below 1 mrad, which is a very accurate result for phase angle measurements. These results verify the accuracy of the SSMs regarding the phase angle distortions over a wide range of operating points. The results further show that ˆ*δ* increases with decreasing |*Z*F*,*typeE| since the negative sequence voltage increases, which leads to larger distortions. Only the DSRF shows an almost

**Figure 5.55:** Comparison of SSM, LSM, and experimental results (EXP) for the maximum distortion magnitude ˆ*δ* of the LSRF-PLL and DSRF-PLL during a type E fault with different sag depths or |*Z*F*,*typeE|, respectively.

**Figure 5.56:** Comparison of SSM, LSM, and experimental results (EXP) for the maximum distortion magnitude ˆ*δ* of the Nf-PLL and DSOGI-PLL during a type E fault with different sag depths or |*Z*F*,*typeE|, respectively.

constant ˆ*δ* due to the frequency adaptive filter capability, and thus full attenuation of the negative sequence even for shifts in the fundamental frequency.

#### **5.5.2 Dynamic Response on Type A Faults**

The dynamic characteristics of the PLL models are validated during a type A fault with different fault impedance magnitudes |*Z*F*,*typeA| and a constant fault impedance ratio *r*F=0 pu. These parameters, in combination with a source impedance ratio of *r*S=10 pu, lead to large phase angle jumps. |*Z*F*,*typeA| is varied between 0.1 and 3 that yields a positive sequence magnitude range of 0*.*1 pu *< V*ˆ S*,*1 *<* 0*.*88 pu normalized to the rated voltage of 230 V.

Fig. 5.57 shows the comparison of the experiment and LSM results for the PLL design parameters with optimized bandwidth *ω*c and fixed damping ratio *ζ*0*.*7. The results indicate sufficient model accuracy for most operational scenarios. However, the settling times of the simulation and experiment differ significantly in the range of 20% for some operating points caused by the PT2 behavior of the step responses. Only minor differences in the oscillation magnitudes between the simulation and experiment may lead to large deviations in the settling time. For example, the oscillation magnitude of the simulation results is slightly below the limit of the tolerance band, whereas the oscillation magnitude determined by the experiment is slightly larger than the tolerance band. In this case, the settling time determined in the experiment will be shifted by at least 1*/*2 of the oscillation period in comparison to the simulation results until it may stay within the tolerance band. These characteristics lead to the steps in the settling time results that are shifted with |*Z*F*,*typeA| in the LSM compared to the experiment.

The settling time results for the optimized design are shown in Fig. 5.58 and show less differences between experiment and LSM than the conventional design. Here, the maximum deviation is approximately 3% (except for the DSRF) that highlights the high fidelity of

**Figure 5.57:** Comparison of the LSM and experiment results (EXP) for the settling time *t*set*,δ* of the estimated phase angle of the PLLs during type A faults with different sag depths considering the PLL bandwidth optimization with fixed *ζ* = 0*.*7.

**Figure 5.59:** Comparison of the SSM and LSM results for the estimated phase angle settling time *t*set*,δ* of the LSRF-PLL and DSRF-PLL during type A faults with different sag depths.

**Figure 5.58:** Comparison of the LSM and experiment results (EXP) for the settling time *t*set*,δ* of the estimated phase angle of the PLLs during type A faults with different sag depths considering the PLL bandwidth and damping factor optimization.

**Figure 5.60:** Comparison of the SSM and LSM results for the estimated phase angle settling time *t*set*,δ* of the Nf-PLL and EPMAF-PLL during type A faults with different sag depths.

the LSMs. As already observed in the conventional design, the DSRF is unstable for small |*Z*F*,*typeA| (*t*set*,δ* → ∞), which is accurately predicted by the LSM.

The SSMs yield accurate results for most PLLs even for severe fault scenarios with small |*Z*F*,*typeA|, as shown in Fig. 5.59 and Fig. 5.60. The relative error is smaller than 20% except for the DSRF-PLL, which is a sufficient accuracy considering that the fault scenarios contain large magnitude and phase angle jumps that are typically out of range of SSMs. However, the LSM and experiment reveal an instability mechanism of the DSRF-PLL that the SSM cannot capture. Therefore, the assumptions for deriving the SSM are reviewed in section 5.7 and lead to the proposed multi-fidelity model-based design.

Based on the validated models, both design optimizations can be compared. Fig. 5.61 and 5.62 show a shorter settling time for *ζ*opt for most of the PLLs and operating scenarios. The LSRF-PLL yields a smaller settling time, particularly for larger sag depths and smaller *V*ˆ S*,*1, respectively. In contrast, the DSRF settling times do not differ significantly between both designs. The most significant improvement in the settling times is achieved for the PLLs

**Figure 5.61:** LSM results of the settling time of the estimated phase angle *t*set*,δ* of the LSRF-PLL and DSRF-PLL for the two design approaches *ζ*opt and *ζ*0*.*7 during type A faults with different sag depths.

**Figure 5.62:** LSM results of the settling time of the estimated phase angle *t*set*,δ* of the Nf-PLL and EPMAF-PLL for the two design approaches *ζ*opt and *ζ*0*.*7 during type A faults with different sag depths.

with prefilter, as demonstrated in Fig. 5.62. The settling time of the Nf-PLL can be reduced by 50%-100% and the settling time of the EPMAF by 20%.

These results confirm the effectiveness of the damping factor optimization, particularly, for PLLs with prefilter. Moreover, the individually optimized designs enable a fair comparative study between the PLLs since they all must meet the same disturbance rejection constraint under the same worst-case scenarios. The comparison confirms that the settling times of the PLLs can be significantly decreased with higher filter efforts. The Nf and EPMAF-PLL lead to much shorter settling times than the LSRF-PLL. These results can only be improved by a filter that is frequency adaptive such as the DSRF-PLL. Unfortunately, this structure shows other instability mechanisms that cannot be captured by its SSM, so that design efforts are significantly increased.

The validated models accurately predict the error of the estimated phase angle during different grid scenarios. However, the phase angle error is only an auxiliary quantity and not of direct interest for the converter performance since the grid codes provide requirements for the converter's power factor accuracy and output current settling time. Therefore, the models must be extended to describe the impact of the PLL on the power factor and output current of the converter. These model extensions are presented in the next section.

### **5.6 Impact of the PLL on the Voltage Oriented Control Considering Power Factor and Converter Current**

The PLLs affect the converter's power factor and output current, which is critical due to grid code requirements. Conventional PLL designs do not consider these relations and rely on the Chapter 5. Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

**Figure 5.63:** Norton's equivalent circuit of VOC with PLL considering an averaged converter model with filter inductance.

evaluation of the estimated phase angle error *δ* [124], [140]. However, this is typically only an auxiliary quantity for the converter control. Therefore, this section presents the influence of *δ* on the converter's power factor *λ* and output current **i**dq, and analyses the impact on the PLL design.

Fig. 5.63 shows the VOC structure including the PLL and the averaged converter model with the converter-side filter inductance *L*1f. This structure can be simplified to a Norton equivalent circuit in dq-frame that accurately describes the system dynamics. The Norton equivalent circuit relies on the assumption that the current control closed-loop transfer function can be approximated by a First Order Lag Element (PT1) transfer function *Gi* with the time constant *τi* according to 5.46. This assumption holds for the current control design based on pole-zero cancellation.

$$G\_i(s) = \frac{1}{1 + s\tau\_i} \tag{5.46}$$

The VOC structure in Fig. 5.63 consists of two dq-frames. One corresponds to the real phase angle *θ*, and leads to the converter currents **i**dq. The other dq-frame locks on the estimated phase angle *θ* 0 of the PLL, which results in the converter currents **i**dq*,*PLL. Both currents should be identical in steady-state *δ* = 0. However, these currents differ significantly during grid voltage transients leading to differing active and reactive power injection compared to the references.

Eq. 5.47 gives the relation between **i**dq and **i** ∗ dq*,*PLL, which contains the matrix **T***δ* to transform the currents from the PLL dq-frame into the grid dq-frame. This relation reveals that both components of **i** ∗ dq*,*PLL affect reactive and active grid currents during phase angle transients (*δ* 6= 0). These coupling mechanisms are nonlinear due to the multiplication of **T***δ*(*δ*) with the reference currents, even if the trigonometric terms of **T***δ* are linearized.

$$\mathbf{i}\_{\mathrm{dq}} = \begin{bmatrix} i\_{\mathrm{d}} \ i\_{\mathrm{q}} \end{bmatrix}^{\mathrm{T}} = \underbrace{\begin{bmatrix} \cos(\delta) & \sin(\delta) \\ -\sin(\delta) & \cos(\delta) \end{bmatrix}}\_{\mathbf{T}\_{\delta}} \mathbf{i}\_{\mathrm{dq}, \mathrm{PLL}} = \mathbf{T}\_{\delta} \mathbf{G}\_{i}(s) \mathbf{i}\_{\mathrm{dq}, \mathrm{PLL}}^{\*} \tag{5.47}$$

**Figure 5.64:** Extended PLL-LSM with current control and power factor.

The power factor is based on similar relations like the grid currents and can be described as follows:

$$\begin{aligned} \left[\cos(\varphi) \quad \sin(\varphi)\right]^\mathrm{T} &= \frac{\mathbf{i}\_{\mathsf{dq}}}{\sqrt{\mathbf{i}\_{\mathsf{d}}^{\mathsf{2}} + \mathbf{i}\_{\mathsf{q}}^{\mathsf{2}}}} = \mathbf{T}\_{\mathsf{d}} G\_{i}(s) \frac{\mathbf{i}\_{\mathsf{dq}, \mathsf{PLL}}^{\*}}{\sqrt{\mathbf{i}\_{\mathsf{d}, \mathsf{PLL}}^{\*2} + \mathbf{i}\_{\mathsf{q}, \mathsf{PLL}}^{\*2}}} \\ &= \mathbf{T}\_{\mathsf{d}} G\_{i}(s) \left[\cos\left(\varphi\_{\mathsf{PLL}}^{\*}\right) \sin\left(\varphi\_{\mathsf{PLL}}^{\*}\right)\right]^\mathrm{T} \end{aligned} \tag{5.48}$$

Typically the active and apparent power define the power factor, but the d and q-current component in the grid frame directly represent the active and reactive current, respectively. Hence, the power factor can be calculated with **i**dq according to 5.48, which shows that both components of **i** ∗ dq*,*PLL affect the cos(*ϕ*) during phase angle transients. Moreover, the current references **i** ∗ dq*,*PLL can be substituted with the power factor references [cos (*ϕ* ∗ PLL) sin (*ϕ* ∗ PLL)]T to obtain an identical transfer characteristic like the currents (see 5.47).

The equivalent circuit in Fig. 5.63 is combined with the PLL-LSM according to 5.47 and 5.48, and leads to the block diagram in Fig. 5.64. This model describes the large-signal behavior of the VOC, considering the dynamics of the grid synchronization. Only the ANS is neglected, i.e., the grid voltage magnitude *V*ˆ S*,*1 is accurately tracked and normalizes the PLL input.

The model is verified with time-domain simulations based on the averaged converter model considering the PLL, VOC, and physical circuit components, as shown in Fig. 5.63. A type A fault with *V*ˆ *S,*1 = 0*.*68 pu and a 90◦ phase angle jump is applied to the converter terminals at *t* = 0*.*1 s. The LSRF-PLL parameters are *ω*f = 120 rad/s, *k*i = 1035 rad*/*s 2 , and *k*p = 50 rad*/*s. A time constant *τi* =1 ms is assumed for the current control [117]. The grid currents in the PLL-frame (**i**dq*,*PLL) in Fig. 5.65 do not show any response to the type A fault, since they do not depend on *δ*. In contrast, the grid currents **i**dq in Fig. 5.66 show a disturbance response due to the phase angle jump. These characteristics confirm the model equation given in 5.47, which achieves the same results like the numerical model as presented

**Figure 5.65:** Converter currents in dq-components transformed with the PLL phase angle *θ* 0 during a symmetrical fault (type A) with a 90° phase jump.

**Figure 5.67:** Power factors during a symmetrical fault (type A) with a 90° phase jump simulated with the numerical and analytical model.

**Figure 5.66:** Converter current in dq-components transformed with the grid phase angle *θ* during a symmetrical fault (type A) with a 90° phase jump simulated with the numerical and analytical model.

**Figure 5.68:** Converter output power in different angle reference frames during a symmetrical fault (type A) with a 90° phase jump.

in Fig. 5.66. The power factor shows similar transients like the currents **i**dq as depicted in Fig. 5.67, which confirms the relation given in 5.48.

The test scenario shows differing transient processes for the currents **i**dq and **i**dq*,*PLL in response to the fault. However, the active and reactive power, i.e., *p* and *q*, are identical in both reference frames as shown in Fig. 5.68. This behavior indicates that the voltages in the PLLframe **v**dq*,*PLL*,*S change in response to the phase angle jump, whereas the currents **i**dq*,*PLL are constant (compare Fig. 5.65). In contrast, the currents in the grid-frame show a disturbance response, whereas the voltages **v**dq*,*S are constant (compare Fig. 5.66). Regardless of these differences, the PLL dynamics predominantly affect the injected active and reactive power in both reference frames during faults with large phase jumps.

The presented model accurately describes how the phase angle estimation of PLLs affect the power factor and converter currents. Transient processes in the phase angle change the injected converter power, which is particularly critical during faults since the reactive power must be quickly provided to sufficiently support the grid voltages. The next two sections

present the detailed analysis of how *δ* affects the power factor distortions and the settling time of the reactive current for different fault scenarios.

#### **5.6.1 PLL Impact on the Converter Power Factor**

The PLL's immunity to voltage distortions mainly affects the power factor distortions. SSMs can sufficiently describe these characteristics since harmonics occur typically as small perturbations around an operating point. Eq. 5.48 is linearized to derive the SSM to determine the dynamics of the power factor *λ* during phase jumps. Therefore, *Gi* is neglected and sin(*ϕ* ∗ PLL) is substituted by √ 1 − *λ* ∗2 in 5.48 according to:

$$
\lambda = \cos(\varphi\_{\rm PLL}^\*)\cos(\delta) + \sin(\varphi\_{\rm PLL}^\*)\sin(\delta) = \lambda^\*\cos(\delta) + \sqrt{1-\lambda^{\*2}}\sin(\delta)\ . \tag{5.49}
$$

Then, *λ* ∗ 0 is defined as operating point of the power factor reference, whereas *δ*0 = 0 rad is the constant operating point of the phase angle, which leads to:

$$
\Delta\lambda = \Delta\lambda^\* + \sqrt{1 - \lambda\_0^{\*2}} \Delta\delta = \Delta\lambda^\* + \sin(\varphi\_{\text{PLL},0}^\*) \Delta\delta \ . \tag{5.50}
$$

Accordingly, sin(*ϕ* ∗ PLL*,*0) is the operating point of sin(*ϕ* ∗ PLL). The linear equation for the power factor indicates that the estimated phase angle ∆*δ* only affects the power factor if *λ* ∗ 0 = 1 6 or sin(*ϕ* ∗ PLL) 6= 0, respectively. In contrast, the largest impact of ∆*δ* on *λ* occurs for *λ* ∗ 0 = 0 or sin(*ϕ* ∗ PLL) = 1, respectively. Based on 5.50 and assuming ∆*λ* ∗ = 0 (constant power factor reference), the disturbance transfer function of the power factor with the voltage harmonics *v*˜PLL*,*q+ as input can be expressed as:

$$G\_{\rm d,pf}(s) = \frac{\Delta\lambda}{\tilde{v}\_{\rm PLL,q+}} = \sin\left(\varphi\_{\rm PLL,0}^{\*}\right) \frac{\theta'}{\tilde{v}\_{\rm PLL,q+}} = \sin\left(\varphi\_{\rm PLL,0}^{\*}\right) G\_{\rm d}(s) \quad. \tag{5.51}$$

Substituting ∆*λ* in equation 5.51 by 5.50 and assuming ∆*δ*|*θ*=0 = *θ* 0 reveals the equivalence between *G*d*,*pf(*s*) and the disturbance transfer function of the PLL *G*d, which is only scaled by sin *ϕ* ∗ PLL*,*0 .

The derived power factor model is tested with type E faults. The current references **i** ∗ dq are selected according to the FRT requirements shown in Fig. 5.18. The results for the distortions of the estimated phase angle ˆ*δ* and the respective distortions of the power factor *λ*ˆ are shown in Fig. 5.69 and 5.70. They confirm the theoretical expectations for all four PLLs. For the power factor operating point *λ* ∗ 0 = 1 (sin(*ϕ* ∗ PLL*,*0) = 0) and *V* + *>* 0*.*9 pu, ˆ*δ* does not affect *λ*ˆ. For decreasing voltage sags in the range of 0*.*5 pu *< V* + *<* 0*.*9 pu, *λ*ˆ increases since *λ* ∗ 0 is decreasing (sin(*ϕ* ∗ PLL*,*0) is increasing) due to the FRT requirements. Finally, *λ* ∗ 0 = 0 (sin(*ϕ* ∗ PLL*,*0) = 1) for *V* + *<* 0*.*5 pu, and thus *λ*ˆ=ˆ*δ*. These characteristics are valid for all four analyzed PLLs, which verifies the extracted disturbance model in 5.51 and its general applicability to SRF-based PLLs.

**Figure 5.69:** Power factor distortion amplitude *λ*ˆ and estimated phase angle distortions ˆ*δ* of LSRFand DSRF-PLL during type E faults with different sag depths.

**Figure 5.70:** Power factor distortion amplitude *λ*ˆ and estimated phase angle distortions ˆ*δ* of Nf- and EPMAF-PLL during type E faults with different sag depths.

The power factor distortions depend on the distortions in the estimated phase angle extracted by the PLL. However, the influence significantly changes with the power factor or current references, respectively. In normal operation, the power factor reference of the converter is typically in the range of 0.85-1, where the phase angle distortions do not affect the power factor. In contrast, the power factor reference decreases to zero for severe grid faults, where the estimated phase angle distortions directly distort the power factor. Since *λ*ˆ=ˆ*δ* is the worst-case scenario, the power factor requirement in the grid codes can be directly applied to the distortions of the estimated grid angle as already assumed for the design process in section 5.4.

#### **5.6.2 PLL Impact on the Converter Current Control**

The model presented in Fig. 5.64 sufficiently describes the effect of the error of the estimated phase angle on the grid currents. Fig. 5.66 shows simulation results that emphasize the massive impact of the PLL phase angle on the current control dynamics during grid voltage transients. But how can these relations be interpreted and which current settling times can be expected for different fault scenarios depending on the PLL and its design? These questions are answered using the model derived in 5.47:

$$\mathbf{i}\_{\rm dq} = \mathbf{T}\_{\delta} \mathbf{G}\_{i}(s) \mathbf{i}\_{\rm dq, PLL}^{\*} \quad , \tag{5.52}$$

which is linearized to identify critical relations and scenarios.

The transfer characteristics **x**PLL*,*dq+ = [*x*PLL*,*d+ *x*PLL*,*q+] T to *θ* are derived from the block diagram in Fig. 5.64 by defining *x*PLL*,*d+ = cos(*δ*) and *x*PLL*,*q+ = sin(*δ*). The resulting transfer functions are linearized around the steady-state operating point *θ*0 − *x*PLL*,*q+*,*0*G*ol = *δ* ≈ 0, which yields the linear dependency of ∆**x**PLL*,*dq+ on the linearized phase angle ∆*θ*:

$$
\begin{bmatrix} x\_{\text{PLL},\text{d}+} \\ x\_{\text{PLL},\text{q}+} \end{bmatrix} = \begin{bmatrix} \cos\left(\theta - x\_{\text{PLL},\text{q}+} G\_{\text{ol}}\right) \\ \sin\left(\theta - x\_{\text{PLL},\text{q}+} G\_{\text{ol}}\right) \end{bmatrix} \Rightarrow \begin{bmatrix} \Delta x\_{\text{PLL},\text{d}+} \\ \Delta x\_{\text{PLL},\text{q}+} \end{bmatrix} = \begin{bmatrix} 1 \\ \frac{1}{1+G\_{\text{ol}}} \Delta \theta \end{bmatrix} \tag{5.53}
$$

Then, the definition of **x**PLL*,*dq+ is applied to **T***δ*, and the current transfer characteristic according to 5.47 is linearized around the generic operating point defined by **i**dq*,*PLL*,*0 and **x**dq*,*PLL*,*0:

$$\mathbf{i}\_{\mathrm{dq}} = \begin{bmatrix} x\_{\mathrm{PLL,d}+} & x\_{\mathrm{PLL,q}+} \\ -x\_{\mathrm{PLL,q}+} & x\_{\mathrm{PLL,d}+} \end{bmatrix} G\_{\mathrm{i}} \mathbf{i}\_{\mathrm{dq},\mathrm{PLL}}^{\*} \tag{5.54}$$

$$\Rightarrow \Delta \mathbf{i}\_{\mathrm{dq}} = \begin{bmatrix} x\_{\mathrm{PLL},\mathrm{d}+,0} & x\_{\mathrm{PLL},\mathrm{q}+,0} & i\_{\mathrm{d},\mathrm{PLL},0}^{\*} & i\_{\mathrm{q},\mathrm{PLL},0}^{\*} \\ -x\_{\mathrm{PLL},\mathrm{q}+,0} & x\_{\mathrm{PLL},\mathrm{d}+,0} & i\_{\mathrm{q},\mathrm{PLL},0}^{\*} & -i\_{\mathrm{d},\mathrm{PLL},0}^{\*} \end{bmatrix} G\_{\mathrm{l}} \begin{bmatrix} \Delta \mathbf{i}\_{\mathrm{dq},\mathrm{PLL}}^{\*} \\ \Delta \mathbf{x}\_{\mathrm{PLL},\mathrm{d}q+} \end{bmatrix} \tag{5.55}$$

Substituting [∆*x*PLL*,*d+ ∆*x*PLL*,*q+] T in 5.55 and assuming that *x*PLL*,*d+*,*0 = 1 pu and *x*PLL*,*q+*,*0 = 0 pu, which is valid for the PLLs in the steady-state, leads to the converter current transfer functions:

$$
\Delta \mathbf{i}\_{\mathrm{dq}} = \begin{bmatrix} 1 & 0 & \frac{i\_{\mathrm{q}, \mathrm{PLL},0}^{\*}}{1 + G\_{\mathrm{al}}} \\ 0 & 1 & -\frac{i\_{\mathrm{d}, \mathrm{PLL},0}^{\*}}{1 + G\_{\mathrm{al}}} \end{bmatrix} G\_{\mathrm{i}} \begin{bmatrix} \Delta \mathbf{i}\_{\mathrm{dq}, \mathrm{PLL}}^{\*} \\ \Delta \theta \end{bmatrix} + G\_{\mathrm{i}} \mathbf{i}\_{\mathrm{dq}, \mathrm{PLL},0}^{\*} \,. \tag{5.56}
$$

These linear transfer characteristics include the typical current response to reference steps *G*i**i** ∗ dq*,*PLL*,*0 and additionally describe the step response to phase angle jumps. Eq. 5.56 indicates that the current response to grid voltage disturbances strongly depends on the phase angle, current references, and the PLL open-loop transfer function. This means, that the converter current dynamics may behave like the dynamics of the estimated phase angle error depending on the current references. Considering the definition of the error transfer function of the PLLs *δ/*∆*θ* and substituting ∆*θ* in 5.56, leads to:

$$\frac{\delta}{\Delta\theta} = \frac{1}{1 + G\_{\text{cl}}} \Rightarrow \qquad \Delta \mathbf{i}\_{\text{dq}} = \begin{bmatrix} 1 & 0\\ 0 & 1 \end{bmatrix} G\_{\text{l}} \Delta \mathbf{i}\_{\text{dq}, \text{PLL}}^{\*} + G\_{\text{l}} \mathbf{i}\_{\text{dq}, \text{PLL},0}^{\*} + \begin{bmatrix} i\_{\text{q,PLL,0}}^{\*} \\ -i\_{\text{d,PLL,0}}^{\*} \end{bmatrix} G\_{\text{l}} \delta \tag{5.57}$$

This expression describes the coupling between *i*d and *i* ∗ q*,*PLL or *i*q and *i* ∗ d*,*PLL depending on *δ* during grid voltage transients. In the worst-case, i.e., **i** ∗ dq = [1 1] pu, the converter current to phase angle transfer function is identical to the error transfer function *δ/*∆*θ* of the PLL. Consequently, the step response of the estimated phase angle error is identical to the current step response during grid voltage disturbances (see 5.57). This equivalence is critical since the PLL time constant is typically much larger than the current control time constant.

**Figure 5.71:** Grid currents **i**dq during a phase angle jump of −*π*/2 at 0.1 s with current references step to **i** ∗ dq*,*PLL = [1 1]T pu derived with the SSM and numerical model (Num. LSM).

**Figure 5.72:** Grid currents **i**dq during a phase angle jump of −*π*/2 at 0.1 s with current references step to **i** ∗ dq*,*PLL = [0 1]T pu derived with the SSM and numerical model (Num. LSM).

The SSM is validated with the numerical model during a large phase angle jump of −*π/*2 and different current reference steps using the LSRF-PLL with the *ζ*opt design parameters. Fig. 5.71 shows the results with the initial references of **i** ∗ dq*,*PLL = [1 0]T pu. At *t* = 0*.*1 s the phase angle jump is applied that triggers a reference step to **i** ∗ dq*,*PLL = [1 1]T pu, instantaneously. The SSM yields similar results as the LSM, but the first 40 ms after the step differ significantly since the assumption *δ* ≈ 0 is critically violated there. However, this does not critically affect the error of the current settling time predicted by the SSM, which is in the small range of 2-3%. The models are compared again with the same initial conditions and phase angle jump but using **i** ∗ dq*,*PLL = [0 1]T pu for the current reference step. The comparison of the LSM and SSM shows significant differences in the first 40 ms due to the large *δ*. These differences lead to large variations in the predicted settling time of the q-component in this scenario, i.e., *t*set*,i*q*,*SSM = 27 ms to *t*set*,i*q = 44 ms. Contrarily, the slow response of *i*d is accurately captured by the SSM.

Both test scenarios are also analyzed regarding the critical coupling mechanism between the dq-components of the current references. In the first test, the d and q-current, show an oscillation with a large time constant in the range of the PLL time constant that leads to a settling time *t*set*,***i**dq of 220 ms using a tolerance band of 0.1 pu. The results of the second test indicate that *i*d has similar dynamics as in the previous test with *t*set*,i*d = 185 ms but *i*q shows a much quicker response with *t*set*,i*q = 44 ms. This finding confirms the predicted relation that the coupling of the dq-current references highly deteriorates the converter current settling time during phase angle jumps. These results confirm the predicted, critical coupling mechanism between *i*d and *i* ∗ q*,*PLL or *i*q and *i* ∗ d*,*PLL triggered by *δ*.

The type A fault was already defined as the worst-case for transient processes in the grid. Now, the impact of the settling time of *δ* on the settling of converter's reactive current during different type A faults is analyzed. Fig. 5.73 and Fig. 5.75 present the *δ* settling time for the LSRF- and Nf-PLL, and DSRF- and EPMAF-PLL, respectively. A constant settling tolerance band of 0*.*1 · *π/*2 is assumed. The settling time typically increases with smaller *V* +

**Figure 5.73:** Settling time of the estimated phase angle for the LSRF- and Nf-PLL during type A faults considering a tolerance band of 0*.*1 *π/*2.

**Figure 5.74:** Settling time of the reactive current for the LSRF- and Nf-PLL during type A faults considering a tolerance band of 0*.*1 pu.

since the phase angle jumps are getting larger, indicating the worst-case for the settling at *V* + = 0*.*05 pu. The short settling times for *V* + *>* 0*.*8 pu are due to the small phase angle jumps compared to the absolute tolerance band. The LSMs and SSMs show similar results except for the DSRF PLL, which is getting unstable as indicated by the large settling times for small *V* + (see Fig. 5.75).

The comparison of these findings with the settling times of *i*q in Fig. 5.74 and 5.76 show that the worst-case for the *δ* settling time not necessarily coincides with the *i*q settling time. The changing current references cause this effect. The active current reference is zero for *V* + *<* 0*.*5 pu leading to a significant decrease of the reactive current settling times since the current control and PLL dynamics are almost decoupled. Contrarily, the settling time *t*set*,i*q and *t*set*,δ* are almost identical for 0*.*5 pu *< V* + *<* 0*.*8 pu.

The largest settling time max *t*set*,i*q occurs for all analyzed PLLs for the same fault scenario with *V* + = 0*.*68 pu. According to 5.56, the product of *i* ∗ d*,*PLL and ∆*θ* serves as input for the current transfer function and thus affects the settling time of the converter current. Deriving the fault scenario that leads to max(*i* ∗ d*,*PLL · ∆*θ*) results in *V* + = 0*.*68 pu, which is identical to the numerical results. Accordingly, the worst-case for the fault dynamics occurs not at the most severe type A fault with *V* + = 0*.*05 pu but at the maximum coupling of the current control with the PLL dynamics at *V* + = 0*.*68 pu.

The fault clearing can be more critical for the reactive current dynamics than the fault initiation since the current references are typically **i** ∗ dq*,*PLL = [1 0]T pu after fault clearing, and do not depend on the fault scenario. Hence, the current response is dominated by *δ*(*t*) ∝ *i*q(*t*) for all fault clearing processes, as exemplarily shown in Fig. 5.77. This relation is critical since the slow response of the reactive current leads to over-voltages at the PCC that may trip the converter system.

In contrast to the fault initiation, where the reactive current must meet strict rise and settling time requirements, the grid codes do not provide strict requirements for the active current increase after fault clearing. The VDE code in [11] demands a maximum rise time of one

**Figure 5.75:** Settling time of the estimated phase angle for the DSRF- and EPMAF-PLL during type A faults considering a tolerance band of 0*.*1 *π/*2.

**Figure 5.77:** Grid currents **i**dq of the VOC with LSRF-PLL during fault clearing at 0.1 s with current references step to **i** ∗ dq*,*PLL = [1 0]T derived with the SSM and numerical model (Num. LSM).