The current waveform of the open-circuit fault of phase *a* at 0.3 s is shown in Figure 11. The load torque is 30 N·m, and the phase failure of phase *a* occurs at 0.3 s. The phase *a* current becomes zero after 0.3 s. Among the remaining four-phase currents, phase *b* and phase *c* have the same amplitude and complementary waveforms, and the waveform amplitude and phase of phase *d*, *e* and *f* change to varying degrees.

**Figure 11.** Phase *a* current waveform of open-circuit fault in 0.3 s.

The fault index waveform under these conditions is shown in Figure 12. After 0.3 s, the phase *a* fault index rises to 1 and the fault indexes of other phases do not change.

**Figure 12.** Phase *a* fault indicator waveform when open fault occurs within 0.3 s.

The current waveform of the open-circuit fault of phase *a* and phase *d* at 0.3 s and 0.5 s is shown in Figure 13. The load torque is 30 N·m, the phase failure of phase *a* and phase *d* occurs at 0.3 s and 0.5 s, respectively. The phase *a* current becomes zero after 0.3 s and the phase *d* current also becomes zero after 0.5 s.

**Figure 13.** Current waveforms of phase *a* and phase *d* at 0.3 s and 0.5 s open-circuit fault, respectively.

The fault index waveform under these conditions is shown in Figure 14. After 0.3 s, the phase *a* fault index rises to 1, and the phase *d* fault index rapidly rises to 1 within the second half cycle of 0.5 s, so as to accurately locate the two-phase open-circuit fault.

**Figure 14.** Fault index waveforms of phase *a* and phase *d* at 0.3 s and 0.5 s open-circuit fault, respectively.

The current waveform of the open-circuit fault of phase *a* and phase *f* at 0.3 s and 0.5 s is shown in Figure 15. The load torque is 30 N·m, the phase failure of phase *a* and phase *f* occurs at 0.3 s and 0.5 s, respectively. The phase *a* current becomes zero after 0.3 s and the phase *f* current also becomes zero after 0.5 s. Among the remaining four-phase currents, phase *b* and phase *c* have the same amplitude and opposite phase. Similarly, phase *d* and phase *e* have the same amplitude and opposite phase.

**Figure 15.** Current waveforms of phase *a* and phase *f* at 0.3 s and 0.5 s open-circuit fault, respectively.

The fault index waveform under these conditions is shown in Figure 16. After 0.3 s, the phase *a* fault index rises to 1, and the phase *f* fault index rapidly rises to 1 within the second half cycle of 0.5 s, so as to accurately locate the two-phase open-circuit fault.

**Figure 16.** Fault index waveforms of phase *a* and phase *f* at 0.3 s and 0.5 s open-circuit fault, respectively.

#### *5.2. Switch Fault Simulation*

Figure 17 shows the harmonic plane current trajectories obtained by simulation in the case of 12 single-switch faults. It can be observed that the fault trajectories of the 12 switches of the six-phase VSI inverter are consistent with the theory.

**Figure 17.** *z*1-*z*2 harmonic plane current trace in case of single-switch fault.

Figure 18 illustrates the harmonic plane current trajectories obtained by simulation, in the case of 24 types of two-switch faults. The harmonic plane current trajectories are fan-shaped patterns with different center angles in the case of two-switch faults, that are used as characteristic signals for fault diagnosis.

**Figure 18.** *z*1-*z*2 harmonic plane current trace in case of two-switch fault.

Figure 19 presents the training model of the neural network. The current vector characteristic trajectories of single-switch fault and two-switch fault, are used as samples for training. The hidden layer neuron is 9, the expected error is 0.001, and the maximum number of iterations is 1000. The Newff function is used for training and the Sigmoid function is used as the activation function. The feedback process of the optimization error is performed using the L–M algorithm.

**Figure 19.** Neural network training model.

Figure 20 shows the training error convergence curve of the neural network. The neural network optimized using the L–M algorithm has a high convergence speed. When the training is completed 14 times, the mean square error is 7.6208 × 10−4, which meets the error requirements.

**Figure 20.** Error convergence curve of neural network.

The coincidence degree between the error regression curve and the expected curve shown in Figure 21 is high. This proves that the neural network has good fitting and classification ability for different fault current trajectories.

**Figure 21.** Regression curve of neural network training error.

The diagnosis results of the neural network are shown in Table 2. It can be seen that the trained network can identify the single-switch and two-switch faults. The error between the output value of 12 neurons in the output layer and the coding value of the fault type is very small, which leads to an accurate diagnosis.

**Table 2.** Neural network diagnosis results.

**Table 2.** *Cont.*

**Table 2.** *Cont.*

#### **6. Experimental Verification**

Figure 22 shows the overall block diagram of the six-phase PMSM control system, which provides the required DC bus voltage for the inverter after rectification by a threephase uncontrolled rectifier bridge. The DSP-28335 chip outputs the IGBT driving waveform. The resolver and current hall sensor detect the position and phase current of the motor rotor. The Labview host computer platform can receive the motor running state and fault index waveform in DSP in real time.

,\*%7

**Figure 22.** Overall block diagram of the six-phase PMSM control system.

In order to verify the proposed fault diagnosis algorithm, a six-phase motor experimental platform based on DSP is built. The experimental platform is shown in Figure 23. It is mainly composed of a rectifier, controller, inverter, and motor. The motor parameters are: rated output power P = 10 kW, rated voltage U = 311 V, rated current I = 20 A, rated speed N = 1500 r/min, rated torque T = 60 N·m, pole pair p = 5, quadrature axis and straight axis inductor Ld = Lq = 8.5 mH, and power factor = 0.94.

**Figure 23.** Experimental platform of the six-phase motor control system.

Figure 24 shows the phase current waveform when the motor is running at 500 r/min. The current is observed by collecting the voltage at the two ends of the sampling resistance. The voltage value is 100 mV, which corresponds to a current value of 2 A. The amplitudes of the phase currents are equal with a high sinusoidal degree. The current waveforms of phase *a*, *b*, and *d* under the same conditions are shown in Figure 24a. The phase difference between phase *d* current and phase *a* current is 30 degrees. The waveform of the motor is smooth and sinusoidal during normal operation.

**Figure 24.** Waveform of motor under stable operation at 500 r/min: (**a**) current waveform of phase *a*, *b*, and *c*; (**b**) current waveform of phase *a*, *b*, and *d*.

Figure 25 shows the motor speed and six-phase current waveform under sudden load. When the motor speed increases from 400 r/min to 500 r/min in Figure 25a, the actual motor speed gradually increases in the form of the slope with the given speed; the transition is gentle and the overshoot is small in the process of speed increase. In Figure 25b, the amplitude of the motor phase current gradually increases during loading, and the dynamic adjustment process is smooth and stable.

Figure 26 shows the motor speed and the six-phase current waveform during sudden load reduction. When the motor decelerates from 500 r/min to 400 r/min in Figure 26a, the actual motor speed gradually decreases in the form of the slope with the given speed. The transition is smooth and the overshoot is small during deceleration. In Figure 26b, the

amplitude of the motor phase current gradually decreases during load reduction, and the dynamic regulation process is smooth and stable.

&

**Figure 25.** Waveform of the motor under sudden load: (**a**) speed waveform; (**b**) current waveform of the six-phase motor.

**Figure 26.** Waveform of the motor under sudden load: (**a**) speed waveform; (**b**) current waveform of the six-phase motor.

Figure 27 shows the fault index waveform of the motor during stable operation and sudden load increase and decrease. During stable operation and sudden load increase and decrease in the motor, the values of the six-phase open phase fault index are zero, and there is no change. The fault index has no misdiagnosis under fault-free operation, which proves that it has good robustness.

**Figure 27.** Fault index waveform under stable operation at 500 r/min.

Figure 28 presents the phase current and fault index waveform of motor phase *a* in the case of phase failure. Figure 28a presents the current waveform before and after the fault, in which the blue, black, and green lines respectively represent the current waveform of phase *a*, *b*, and *c* of the motor. After the phase failure of phase *a*, the current value of this phase drops to zero, the current amplitude of phase *b* and *c* becomes almost twice the original one, and the phase positions are complementary. Figure 28b illustrates the waveform of the fault phase current and fault index. After the phase failure of phase *a*, the phase failure index Ea of phase *a* increases to a high level after 32 ms, and the optimized fault index has no obvious burr and peak pulse. Therefore, the fault diagnosis and early warning can be performed in a short time.

**Figure 28.** Phase current and fault index waveform in case of phase failure of phase *a*: (**a**) fault current waveform; (**b**) fault phase current and fault index waveform.

Figure 29 shows the fault index waveform of the six-phase disconnection when the *a* phase disconnection fault occurs. After the fault occurs, only the fault index Ea of phase *a* rises to 1, while the fault indexes of the other phases do not change, and there is no misdiagnosis.

**Figure 29.** Fault index waveform in case of phase failure of phase *a*.

The phase current and fault index waveform of phase *a* and phase *d* of the motor with phase failure, are shown in Figure 30. The blue, black, and green lines shown in Figure 30a represent the current waveforms of motor phases *a*, *b*, and *d*, respectively. After the phase failure of phase *a* and *d*, the corresponding phase current value drops to zero, and the amplitude of the phase *b* current increases. The six-phase failure index waveform of phase *a* and phase *d* is shown in Figure 31. Before the phase failure occurs, the sixphase failure index remains null. After the failure occurs, the failure indexes Ea and Ed of phase *a* and phase *d* rise to 1, while the other four-phase failure indexes remain null without misdiagnosis.

Figure 32 shows the phase current and fault index waveform of phase failure of phase *a* and phase *f*. The blue, black, and green lines shown in Figure 32a represent the current waveforms of motor phases *a*, *b*, and *f*, respectively. A phase failure occurs in phase *a* and phase *f*, and the current value drops to zero. After the failure of phase *a* and phase *f*, their failure indexes Ea and Ef jump to the high level after 22 ms and 24 ms, respectively. These situations show that the proposed open phase fault diagnosis method has a high diagnosis speed, and can accurately locate the fault phase position.

**Figure 30.** Phase current and fault index waveform in case of phase failure of phase *a* and phase *d*: (**a**) fault current waveform; (**b**) fault phase current and fault index waveform.

**Figure 31.** Fault index waveform in case of phase failure of phase *a* and phase *d*.

**Figure 32.** Phase current and fault index waveform in case of phase failure of phase *a* and phase *f*: (**a**) fault current waveform; (**b**) fault phase current and fault index waveform.

The six-phase failure index waveform of phase *a* and phase *f* is shown in Figure 33. During normal operation, the failure indexes of the two phases are 0. After phase *a* and phase *f* fail, their failure indexes Ea and Ef rise to 1, and the failure indexes of the other phases do not change. It can then be deduced that the fault index of each phase can accurately locate the position of the fault phase. In addition, the diagnosis results are accurate, and there will be no false diagnosis. Finally, the experimental results are coherent with the theoretical analysis, which verifies the correctness and efficiency of the proposed diagnosis algorithm.

**Figure 33.** Fault index waveform in case of phase failure of phase *a* and phase *f*.

#### **7. Conclusions**

This paper proposed a fault diagnosis method based on vector space decoupling (VSD). The open phase fault index is derived according to the VSD inverse transformation and the current constraints after the fault. The fault index is optimized in order to prevent misdiagnosis and improve reliability. The diagnosis of a single-phase and double-phase fault can be performed in one fundamental cycle. In addition, by considering the unique harmonic plane current track after VSD transformation as the characteristic signal, a neural network is used to identify different fault current tracks, in order to diagnose the switch fault. The simulation and experimental results show that the proposed scheme has a high detection speed, ability to deal with several fault types, and good robustness. Finally, the proposed approach can accurately locate the winding open-circuit fault and power switch fault, which can be used for inverter open-circuit fault diagnosis and provides a basis for maintenance personnel.

**Author Contributions:** Conceptualization, H.G.; formal analysis, H.G. and J.G.; data curation, Z.H. and J.G.; writing—review and editing, B.Z. and Y.D. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research work was funded by the National Natural Science Foundation of China grant number 51177031.

**Data Availability Statement:** The data presented in this study are available on request from the corresponding author.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

### *Article* **Analysis and Operation of a High DC-AC Gain 3-***φ* **Capacitor Clamped Boost Inverter**

**Dogga Raveendhra 1,\*, Poojitha Rajana 2, Beeramangalla Lakshminarasaiah Narasimharaju 3, Yaramasu Suri Babu 4, Eugen Rusu 5,\* and Hady Habib Fayek 6**

**Abstract:** This article introduces a three-phase capacitor clamped inverter with inherent boost capability by relocating the filter components from the AC side to the configuration's midpoint. This topology has several distinguishing characteristics, including: (a) low component count; (b) high DC-AC gain; (c) decreased capacitor voltage stresses; (d) improved power quality (extremely low voltage and current THDs) without the use of an AC-side filter; and (e) decreased voltage stresses on power semiconductor devices. Simulations were carried out on the MATLAB Simulink platform, and results under steady-state conditions, load and reference change conditions, and phase sequence change conditions, along with THD profiles, are presented. This inverter's performance was compared to that of similar converters with intrinsic gain. A 1200 W experimental prototype was built to demonstrate the system's feasibility and benefits. When compared to existing topologies, simulation and experimental results indicate that the proposed inverter provides superior high gain, smooth control, low stress, and a long life time.

**Keywords:** step up inverter; single stage inverter; capacitor clamped inverter; high-gain converter; DC–AC power converter

#### **1. Introduction**

To overcome the disadvantages of the traditional inverters, such as voltage sources and current source inverters, the ZSI/qZSI [1,2] is widely accepted for various applications. The ZSI/qZSI offers a voltage step-up/down function in single-stage power conversion without requiring additional power processing stage, as shown in Figure 1a, and its application in an electric vehicle is depicted in Figure 1b. Moreover, ZSI/qZSI's reliability is high because shoot-through is an integral part of the operation. The study of these converters has mainly focused on control techniques [3–5], applications [6], and PWM schemes [7,8].

In addition, various power electronics topologies have been proposed in the literature to meet the different objectives, such as reducing the number of switches, reducing the passive component count, and increasing the voltage gain and voltage stresses on the switches/capacitors. The SBI [9] is one such topology that was introduced to decrease the number of passive components (one inductor and one capacitor) in comparison to the ZSI/qZSI by having one additional switch. Although the SBI can perform voltage step-up or step-down in a single stage, its voltage gain is significantly less than that of

**Citation:** Raveendhra, D.; Rajana, P.; Narasimharaju, B.L.; Babu, Y.S.; Rusu, E.; Fayek, H.H. Analysis and Operation of a High DC-AC Gain 3-*φ* Capacitor Clamped Boost Inverter. *Energies* **2022**, *15*, 2955. https:// doi.org/10.3390/en15082955

Academic Editors: Nicu Bizon and Adolfo Dannier

Received: 21 February 2022 Accepted: 13 April 2022 Published: 18 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

impedance source converters such as the ZSI/qZSI (1-D). To enhance the source current profile and voltage gain, a group of qSBIs was reported in [10,11]. These included dc-link and embedded-type qSBIs, in addition to current-fed SBIs. However, the embedded-type qZSI necessitates the use of two distinct DC sources, which is undesirable. The qSBI has similar characteristics to the qZSI, except that the shoot-through mode is used for voltage boosting. A comprehensive comparison of the qSBI and qZSI was described [12]. However, the shootthrough duty cycle in these topologies cannot exceed (1–M), where M is the modulation index, thereby limiting the voltage gain in all of the above-mentioned topologies. To achieve the desired output voltage with a high voltage gain and good power quality, a high-duty cycle must be used, lowering M. The lower the value of M, the lower the overall DC-AC conversion gain and the higher the output harmonics. Either the M or the B.F. can be increased to increase the overall DC-AC gain. Numerous PWM techniques have been proposed for modifying the modulating waves, and it has been demonstrated that PWM schemes can only slightly increase M [7]. Numerous high-gain inverter circuits with and without a galvanic isolation transformer have been proposed [13–25] to increase the boost factor in impedance source converters. Transformer-based ZSIs have been introduced [13,14]. However, the transformer's leakage inductance results in voltage spikes at the DC-bus. To achieve a high voltage gain, transformerless ZSIs with additional passive components, such as inductors, capacitors, and diodes, have been proposed [15–25]. They have been labelled L-ZSI [15], SL-ZSI [16], SL-qZSI [17], EB-ZSI [18], DA-qZSI [19], CA-qZS [20], and EB-qZSI [21], and by incorporating switched-inductor, switched-capacitor, and hybrid switched-capacitor/switched-inductor designs, high boosting factors can be achieved. The addition of passive elements and power electronic components, on contrast, increases the converter's cost, size, volume, losses, and weight [24,25].

**Figure 1.** (**a**) Classical impedance source converters and (**b**) their applications in EV.

For single-phase and three-phase applications, the aforementioned topologies have been proposed. A simple single-phase HB ZSI with reduced capacitor voltage stress was described in [26]. Although this topology is straightforward and compact, it has a low boost factor. In [27], an HB-SBI with discontinuous input current was introduced to increase the gain of the inverter. To address the shortcomings of the HB-SBI, [28] proposed the HB-qSBI. The overall voltage gain is low in all of these half-bridge topologies [26–28]. By comparison, in the SL-ZSI [16], SL-qZSI [17], EB-ZSI [18], DA-qZSI [19], CA-qZSI [20], and EB-qZSI [21] topologies, the voltage stresses on the capacitors are greater, and these topologies employ a greater number of capacitors. The capacitor voltage is typically greater than the input voltage in order to perform the impedance-source stage's voltage boost function. As a result, high-voltage Z capacitors must be used, potentially adding volume and cost to the system. Because of the strong probability of capacitor failure during the field operation of power electronic converters [29], and the stringent reliability restrictions imposed by the

aerospace, automotive, defense, space, and energy industries, stresses and use of capacitors must be reduced to improve inverter reliability [30].

Overall, all of the mentioned topologies have common issues, such as the requirement for capacitors having a high voltage rating (greater than supply), common mode voltages, PWM-natured voltages after the inverter switching leg, and a higher component count when achieving a boosted DC-AC gain in a single stage manner. To address these issues, the capacitor clamped boost inverter with high voltage gain was introduced [31], which disperses the X-shaped passive components of the impedance source inverter rather than concentrating them in one location (between the input and inverter switching network in impedance source inverters). The passive components are distributed evenly between the input and output ports on each leg. However, ref. [31] does not deal with detailed steady-state analysis. Hence, in this study, a detailed analysis in various modes based on the inductor current *iL* bands (upper (*iLmax*) and lower bands (*iLmin*)) was conducted. Based on the upper and lower band values, the operation was divided into three zones in this study. Based on the aforementioned zones, the operation of the converter was further divided into two cases: *case-I* (*zone-1* and *zone-3*) and *case-II* (*zone-2*). In addition, this manuscript includes capacitor voltage profiles and capacitor life time calculations. This paper also discusses the design of a sliding mode controller for the CCBI to track the required voltages and currents to fulfil the specified load characteristics. Also shown are the CCBI's performance under load, reference, and phase sequence change conditions, and its THD profiles. In addition, the performance of this inverter for non-linear loads was also examined. The operating principles, steady-state analysis of various cases, differential modulation technique, capacitor voltage profiles, capacitor life time calculations, and sliding mode controller for the CCBI are presented in Section II. Simulation results and a discussion of the results under steady-state conditions, load and reference change, and phase sequence change conditions, along with THD profiles, are discussed in Section III. A performance investigation of this inverter for non-linear loads is also presented. In the same section, comparative analysis of the proposed inverter with existing similar converters is also presented, along with experimental verification. Section IV presents the conclusions.

#### **2. Operation of the CCBI**

The proposed inverter, depicted in Figure 2a, includes six switches, three small inductors, and three capacitors. Because of the time-varying duty cycle, the intrinsic boost feature of this proposed inverter provides flexibility for grid-connected and stand-alone applications, for a large range of AC output voltages, which are even higher than the DC voltage. This capability is not accessible in standard VSIs, where the DC input voltage is always greater than the AC output voltage [11]. The following offers an analysis of the converter in various modes, a differential modulation scheme, capacitor voltage profiles, a life time analysis, and a sliding mode controller.

#### *2.1. Analysis of Converter*

The operation of the converter shown in Figure 2a is explained with the help of a single-phase equivalent circuit, which is shown in Figure 2b. The equivalent circuit contains one leg (phase-A) along with considerations of the effect of other phases. Boost inverter upper switches are represented with odd numbers, whereas lower switches are represented with even numbers, and these switches operate in a complementary manner. Every inverter leg contains one inductor, one capacitor, and two switches. Analysis of the boost inverter is explained via mathematical modeling.

For one cycle (*0* < *t* < *T*) of load current (*iLoad*), the average value of the inductor current (*iL*) is positive and negative for the periods (0 < *t* < *T*/2) and (*T*/2 < *t* < *T*) respectively, which is shown in Figure 3, where *T* = 1/*f*. It can be observed that *iL* is oscillating at the switching frequency of *fs* between two bands, namely, the upper band (*iLmax*) and the lower band (*iLmin*). During the positive half cycle, the upper band is always positive. However, the lower band current value is negative in *zone-1* (*0* < *t* < *Ta*) and *zone-3* (*T*/2 − *Ta* < *t* < *T/2*),

whereas it is positive in *zone-2* (*Ta* < *t* < *T*/2 − *Ta*). Here, *Ta* is the time when *zone-1* comes to an end.

**Figure 2.** (**a**) Proposed converter; (**b**) single-phase equivalent circuit.

**Figure 3.** (**a**) Gate signals of S1 and S2 and inductor current for positive half cycle; inductor current in one switching cycle of (**b**) *zone-1*, (**c**) *zone-2*, and (**d**) *zone-3*.

Based on the aforementioned zones, the operation of converter is divided into two cases, *case-I* (*zone-1* and *zone-3*) and *case-II* (*zone-2*) as shown in Figure 3. To simplify the analysis further, only one switching sample is considered of N (*=fs*/*f*) samples, and the detailed description of both cases is given below.

*case-I (zone-1 and zone-3):* It is interesting to note that, in this case, all the semiconductor devices sequentially (*D*2, *S*2, *D*1, and *S*1) participate in one switching sample of *G*2, which is shown in Figure 4. Based on the conduction of these switching devices, the operation of the circuit in this case is further classified into four modes, and its equivalent circuit in each mode is shown in Figure 4. The operation of the inverter in various modes for *case-I* is explained below.

**Figure 4.** Equivalent circuit in various modes: (**a**) *Mode-1*; (**b**) *Mode-2*; (**c**) *Mode-3*; (**d**) *Mode-4*;

*Mode-1 (0* < *t* < *t1):* This mode starts when the gate signal is applied to the lower switch *S*2. However, *S*2 cannot be turned on instantly due to the fact that the inductor does not allow the sudden change in current, as it is has a negative value in the previous mode. This leads the diode *D*1 to be turned on and provide a path for a negative inductor current, as shown in Figure 4a.

This *iL* increases linearly in the presence of a positive supply voltage, as shown in Figure 5, and its current equation can be written as:

$$i\_L(t) = \frac{V\_{in}}{L}(t - T\_o) + i\_L(T\_o) \tag{1}$$

**Figure 5.** Waveforms during *case-I*.

This mode ends at *t* = *t*1, where *iL* becomes zero and diode *D*2 turns off. The time duration of this *Mode-1* can be calculated as:

$$t\_1 = L \frac{i\_L(T\_o)}{V\_{in}} + T\_o \tag{2}$$

*Mode-2 (t1* < *t* < *t2):* This mode starts at *t* = *t*1 when S2 comes into conduction. In the presence of a positive supply voltage (*Vin*) across the inductor, its current is increases linearly from 0 to *ILmax*, as shown in Figure 6, and its equation can be written as:

$$
\dot{u}\_L(t) = \frac{V\_{in}}{L}(t - t\_1) \tag{3}
$$

This mode ends at *t* = *t*2, when the switching pulse for *S2* is removed and the time duration of this mode can be evaluated as:

$$t\_2 - t\_1 = DT - t\_1 \tag{4}$$

*Mode-3 (Ton* < *t* < *t3):* This mode starts when the gate signal is given to switch *S1*. From the previous state, it is clear that the initial inductor current is positive (*ILmax*), which brings diode *D*1 to conduction, even in the presence of firing pulses at *G*1, as shown in Figure 6. During this period, a negative voltage (*Vin* − *VAO*) appears across the inductor, which leads to the decrement of the inductor current with a negative slope of (*Vin* − *VAO*)/*L*, which can be expressed as:

$$i\_L(t) = \frac{V\_{in} - V\_{AO}}{L}(t - t\_2) + i\_L(t\_2) \tag{5}$$

**Figure 6.** Waveforms during *case-II*.

This mode ends at *t* = *t*3, when *iL* reaches zero and forces the diode to be turned off. The duration of this mode can be determined as:

$$t\_3 - DT = \frac{L\dot{t}\_L(t\_2)}{V\_{AO} - V\_{in}}\tag{6}$$

*Mode-4 (t3* < *t* < *T):* The zero-initial current of the inductor and the presence of the switching pulse brings *S1* to conduction mode. Now, the inductor discharges in the presence of a negative voltage (*Vin* − *VAO*) and, hence, the inductor current is decreased to a specific negative value (*ILmin*). This negative inductor current is the initial current for *Mode-1*. The expression for the inductor current is given as:

$$i\_L(t) = \frac{V\_{in} - V\_{AO}}{L}(t - t\_3) \tag{7}$$

This mode ends with the removal of the gate pulse of *S1* and the duration of this mode can be calculated as *t*4 − *t*3 = *T* − *t*3.

The same cycle of operation repeats until *t* = *Ta*. The inductor voltage balance equation during *case-I* can be written as:

$$\begin{array}{l}V\_{in}d\_{Ak}T\_s = (V\_{AO} - V\_{in})(1 - d\_{Ak})T\_s\\ \Rightarrow V\_{AO} = \frac{V\_{in}}{1 - d\_{Ak}}\end{array} \tag{8}$$

where *dAk* is the duty cycle at the '*k*th' switching sample of switch S2 of phase A. Waveforms during this case shown in Figure 5. As *dA* is a time-varying value, and when *d* > *da* at *t* = *Ta*, *case-I* ends.

*case-II (Ta* < *t* < *T/2* − *Ta):* This is the special case where *Mode-2* and *Mode-3* operations of *case-I* only take place as there is no negative value of *iLmin* and the remaining two cases are absent. In this case, only two semiconductor switches take active participation in conversion, namely, *S2* and *D1*, whereas the remaining two are in an idle state. Hence, two modes are sufficient to explain the operation; waveforms during this case are shown in Figure 6. It can be observed from the characteristics presented in Figures 5 and 6 that *case-II* is a special case of *case-I*, where only two modes (*Mode-2* and *Mode-3*) are presented during operation. Waveforms of lower switch gate pulses, inductor current, upper and lower diode and switch currents, coupled capacitor current, and input current are presented in Figure 6 respectively. A detailed explanation is presented below.

*Mode-1(Ta* < *t* < *t5):* This mode starts at *t* = *Ta*, at which instant firing pulses (*G*2) are given to *S2*. Due to a positive initial inductor current and the presence of *G*2, switch *S*2 is turned on. In the presence of a positive voltage across the inductor, it is charged to a specific value, which can be expressed as:

$$i\_L(t) = \frac{V\_{in}}{L}(t - T\_p) + i\_L(T\_p) \tag{9}$$

This mode ends at *t* = *t*5 when firing pulses are removed from *G2*.

*Mode-1 (t5* < *t* < *t6):* This mode of operation starts when pulses are given to *S1*. Although pulses are presented at *S*1, it cannot be turned on due to the positive initial current in the inductor. This turns on diode *D*1. Now, the negative voltage across the inductor causes a decrement in the current with the negative slope of (*Vin* − *VAO*)/*L*, which can be expressed as:

$$\dot{\iota}\_L(t) = \frac{V\_{\rm in} - V\_{AO}}{L}(t - T\_{\rm onb}) + \dot{\iota}\_L(T\_{\rm onb}) \tag{10}$$

This mode ends at *t* = *t6* when firing pulses are removed from *S*1. A similar operation (*Mode-1* and *Mode-2*) continues for several switching cycles until *(T*/2 − *Ta*). The voltage balance equation of the inductor obeys Equation (8), as discussed in *case-I*. Furthermore, the similarly boosted inverter operates in a negative half cycle, with the major role of *S1, D2* in *T*/2 to *(T*/2 + *Ta)*, and (*T* − *Ta*) to *T*, in addition to *D*1, *S*1, *D*2, and *S*2 during (*T*/2 + *Ta*) to (*T* − *Ta*).

#### *2.2. Differential Modulation Technique for Three-Phase Boost Inverter*

As shown in (8), once the duty cycle becomes zero, *VAO* = *Vin*; this shows that this converter outputs a dc bias voltage in relation to the negative supply terminal. The primary goal of this study was to generate three-phase sinusoidal voltages across the load terminals of Figure 2a. Based on the gain of this boost inverter, we assume these voltages are modulated with the following duty cycles (*dA*, *dB*, and *dC*) as follows [13]:

$$\begin{array}{l} V\_{AO} = \frac{V\_{dc}}{1 - d\_A} = V\_{in} + A + A \sin \omega t\\ V\_{BO} = \frac{V\_{dc}}{1 - d\_B} = V\_{dc} + A + A \sin(\omega t - 120^{\circ})\\ V\_{CO} = \frac{V\_{dc}}{1 - d\_C} = V\_{dc} + A + A \sin(\omega t - 240^{\circ}) \end{array} \tag{11}$$

where *dA*, *dB*, and *dC* are the duty cycles of the *A*, *B*, and *C* phases, respectively, *Vin* is the bias DC voltage of the boost inverter (i.e., supply voltage), and A is the sinusoidal voltage amplitude. It should be noted that the CCBI one-leg voltage with regard to the negative terminal of a source (*VAO*, *VBO*, *VCO*) always has the same sign as *Vin*; thus, *(VAO*)*DC* must be added to maintain this necessary condition:

$$\begin{Bmatrix} V\_{AO}(t) = (V\_{AO})\_{DC} + (V\_{AO})\_{AC} \sin wt\\ V\_{BO}(t) = (V\_{BO})\_{DC} + (V\_{BO})\_{AC} \sin wt\\ V\_{CO}(t) = (V\_{CO})\_{DC} + (V\_{CO})\_{AC} \sin wt \end{Bmatrix} \tag{12}$$

Here

$$(V\_{dc} + \mathbf{A} = (V\_{AO})\_{DC} = (V\_{BO})\_{DC} = (V\_{CO})\_{DC} \& |V\_{AO}|\_{AC} = |V\_{BO}|\_{AC} = |V\_{CO}|\_{AC} \tag{13}$$

From the 1 − *φ* equivalent model of the 3 − *φ* boost inverter, as shown in Figure 2b, the phase voltage *VAN* applied to *RL* of the 3 − *φ* system can be obtained as [2]:

$$V\_{AN} = \frac{2}{3} \left[ V\_{A0} - \frac{1}{2} (V\_{\text{BO}} + V\_{\text{CO}}) \right] \tag{14}$$

The first term in (14) is the voltage *VAO* produced by the same phase of the boost converter, whereas the second and third terms account for the influence of the other two phases. It can be understood that the phase voltage of the load is a function of all of the three phases' leg voltages (*VAO*, *VBO*, and *VCO*), and for the particular load phase voltage, the other phases' leg voltages' combined effort can be grouped as:

$$V\_{cq} = \frac{1}{2}(V\_{\rm BO} + V\_{\rm CO})\tag{15}$$

The difference in *VANVeq* should also cause the same phase current in the 1 − *φ* model, so an equivalent resistance can be introduced, as mentioned below:

$$R\_{eq} = \frac{3}{2} R\_L \tag{16}$$

From Equations (12) and (14):

$$\begin{array}{ll} V\_{AN} &= \frac{2}{3} \left\{ \left[ \left( V\_{AO} \right)\_{DC} + \left( V\_{AO} \right)\_{DC} \sin \omega t \right] \\ &- \frac{1}{2} \left[ \left( V\_{BO} \right)\_{DC} + \left( V\_{BO} \right)\_{DC} \sin(\omega t - 120) \right. \\ &+ \left( V\_{CO} \right)\_{DC} + \left( V\_{CO} \right)\_{DC} \sin(\omega t - 240) \right] \right\} \\ \Rightarrow & V\_{AN} = \left( V\_{AO} \right)\_{AC} \sin \omega t \end{array} \tag{17}$$

In a similar way, *VBN* and *VCN* have a 120◦ phase shift at the load terminals. Therefore, the phase-to-neutral voltages at the load are:

$$\begin{array}{l} V\_{AN} = \left( V\_{AO} \right)\_{\mathcal{AC}} \sin \omega t\\ V\_{BN} = \left( V\_{AO} \right)\_{\mathcal{AC}} \sin(\omega t - 120^{\circ})\\ V\_{CN} = \left( V\_{AO} \right)\_{\mathcal{AC}} \sin(\omega t - 240^{\circ}) \end{array} \tag{18}$$

These ideal outcomes can be achieved by calculating the three-phase duty cycles using:

$$\begin{cases} D\_A(t) = 1 - \frac{V\_{in}}{(V\_{AO})\_{DC} + (V\_{AO})\_{AC} \sin wt}{V\_{in}}\\ D\_B(t) = 1 - \frac{V\_{in}}{(V\_{BO})\_{DC} + (V\_{IO})\_{AC} \sin (wt - 120^\circ)}{V\_{in}}\\ D\_C(t) = 1 - \frac{V\_{in}}{(V\_{CO})\_{DC} + (V\_{CO})\_{AC} \sin (wt - 240^\circ)} \end{cases} \tag{19}$$

#### *2.3. Capacitor Voltage Profile*

One of the main objectives of this study was to reduce the capacitor peak voltages, which can be calculated for the CCBI as follows:

$$\begin{array}{l} V\_{\text{CA}} = \left( V\_{\text{AO}} \right)\_{\text{DC}} + \left( V\_{\text{AO}} \right)\_{\text{AC}} \sin \omega t - V\_{\text{in}} \\ \Rightarrow V\_{\text{CA}} = \left( V\_{\text{CO}} \right)\_{\text{DC}} + \left( V\_{\text{CO}} \right)\_{\text{AC}} \sin \omega t \end{array} \tag{20}$$

Here (*VCO*) *DC* = (*VAO*) *DC* − *Vin*, and can be calculated as:

$$\begin{aligned} \left(\left(V\_{\text{CO}}\right)\_{\text{DC}} = \left(V\_{\text{AO}}\right)\_{\text{DC}} - V\_{\text{in}}\\ \Rightarrow \left(V\_{\text{CO}}\right)\_{\text{DC}} = \begin{pmatrix} \frac{D}{1 - D} \\ \frac{1 - D}{1 - D} \end{pmatrix} V\_{\text{in}} \end{aligned} \tag{21}$$

Whereas in case of other topologies, the capacitor voltages are higher due to the requirement of a higher dc link voltage for the required DC-AC conversion. Capacitor voltage profiles for the DC-AC conversion of 1 to 1.8 in the proposed case and other similar impedance source inverters are shown in Figure 7, which depicts the reduction in voltage stress on the capacitor.

**Figure 7.** Capacitor voltage profiles.

#### *2.4. Life Time Calculation for Capacitor*

To examine the life time benchmarks of different capacitor solutions and online condition monitoring, life models are used. Generally, the life time of the capacitors is greatly influenced by two factors, namely, voltage stress and temperature. The most extensively accepted empirical model for capacitor life is:

$$\tau = \tau\_0 \times \left(\frac{V}{V\_o}\right)^{-n} \times \exp\left[\left(\frac{E\_a}{K\_B}\right)\left(\frac{1}{\theta} - \frac{1}{\theta\_0}\right)\right] \tag{22}$$

where *τ* is the life time under use conditions, *τo* is the life time under test conditions, *V* is the voltage at use conditions, and *V0* is the voltage at test conditions. *θ* and *θ*0 are the temperature (Kelvin) at use and test conditions, respectively. *Ea* is the activation energy, *KB* is Boltzmann's constant (8.62 × 10−5 eV/K), and n is the voltage stress exponent.

From (22), it is clear that Ea and n are the key parameters to determine the life time; its values were found to be 1.19 and 2.46 for high dielectric constant ceramic, and 1.3–1.5 and 1.5–7 for MLC-Caps.

For Al-Caps and film capacitors, a simplified model from (22) is popularly applied as follows [14]:

$$
\pi = \pi\_o \times \left(\frac{V}{V\_o}\right)^{-n} \times 2^{\frac{\theta\_0 - \theta}{10}} \tag{23}
$$

#### *2.5. Sliding Mode Controller*

When a sliding mode controller is adopted, the system performs effectively in both steady-state and dynamic operations. Although more complicated control approaches, such as THD, can increase system performance, the observed results look satisfactory in many circumstances of practical importance, while the basic controller lowers system cost. An experimental prototype was created, and the experimental findings show that the converter is capable of step-up [2].

The following reasonable assumptions must be considered when designing the sliding mode controller for the proposed converter: power switches that are ideal, converters that operate at high switching frequencies, and power supplies that are free of sinusoidal ripple. Each phase of the proposed converter has two state variables. The sliding surface equation of state space in a three-phase system is expressed as:

$$\begin{array}{l} s\_1(i\_{La}, v\_d) = K\_{a1}\varepsilon\_{a1} + K\_{a2}\varepsilon\_{a2} = 0\\ s\_2(i\_{Lb}, v\_b) = K\_{b1}\varepsilon\_{b1} + K\_{b2}\varepsilon\_{b2} = 0\\ s\_3(i\_{Lc}, v\_c) = K\_{c1}\varepsilon\_{c1} + K\_{c2}\varepsilon\_{c2} = 0 \end{array} \tag{24}$$

where:

$$
\begin{bmatrix} \varepsilon\_{d1} \\ \varepsilon\_{b1} \\ \varepsilon\_{b1} \end{bmatrix} = \begin{bmatrix} i\_{la} \\ i\_{lb} \\ i\_{lc} \end{bmatrix} - \begin{bmatrix} i\_{la\_{ref}} \\ i\_{lb\_{ref}} \\ i\_{lc\_{ref}} \end{bmatrix} \otimes \begin{bmatrix} \varepsilon\_{d2} \\ \varepsilon\_{b2} \\ \varepsilon\_{c2} \end{bmatrix} = \begin{bmatrix} \upsilon\_a \\ \upsilon\_b \\ \upsilon\_c \end{bmatrix} - \begin{bmatrix} \upsilon\_{a\_{ref}} \\ \upsilon\_{b\_{ref}} \\ \upsilon\_{c\_{ref}} \end{bmatrix} \tag{25}
$$

In sliding mode control theory, sensing of all state variables is required to generate the proper control signals and obtain the required AC supply. The generation of the inductor current reference is difficult to assess because it is dependent on several factors, such as supply voltage, load demand, and load voltage. As a result, *iL*-*iLref* can be generated directly from the high frequency component of the inductor current feedback signal, which must be removed due to the control strategy by designing a suitable high pass filter. The addition of a high pass filter increases system order and has the potential to change system dynamics. To overcome this issue, the selected values of the CCBI's switching frequency were higher than the filter cut-off frequency. The trajectory of the sliding surface for this design is shown in Figure 8.

**Figure 8.** Trajectory of the sliding surface.

#### **3. Results and Discussions**

The proposed 3 − *φ* CCBI, as shown in Figure 9, was successfully assessed by means of both simulations and prototype-based hardware results. Simulations were carried out using the MATLAB Simulink environment, and the parameters considered for the simulations are summarized in Table 1, as shown below.

**Figure 9.** Complete system diagram of the hardware setup.

**Table 1.** Electrical parameters of the system.

The following results were acquired at the average switching frequency (*Fs*) equal to 10 kHz. A sliding mode controller was used to achieve good dynamic response, high robustness, and noise-free response while tracking the required 3 − *φ* AC from DC supply. System state variables were continuously monitored and controlled near to a zero error response with the hysteresis band = 0.3, filter constant = 0.01, *K*1 = 0.304, and *K*2 = 0.2. System performance was evaluated in both a steady state and transient states while feeding power to different types of loads (linear and nonlinear) under different test conditions. 3 − *φ* Phase voltages, line voltages, and load currents obtained from this inverter are shown in Figures 10–12, respectively. From these results, it can be clearly seen that the input low-level DC supply was successfully converted to ideal sinusoidal three-phase AC power.

**Figure 10.** Phase voltage of the inverter during steady-state conditions.

**Figure 11.** Line voltages of the inverter during steady-state conditions.

**Figure 12.** Load currents of the inverter during steady-state conditions.

In the boost inverter topology, at least one capacitor is placed in every leg of the respective phase of the converter for the boosting operation. The negative terminals of each of the three capacitors of the three-phase inverter are connected to a common point in this topology, and these are also shown in Figure 13. With reference to this point, the common mode capacitor voltage (*CMMCV*) is defined as the average of all of the three capacitor voltages (*VAO*, *VBO*, and *VCO*) and is shown in Figure 14. In Figure 14, the conventional CMMCV is calculated for the topology proposed by Cecati and compared with the proposed topology. Figure 14 shows that the CMMCV across all of the three capacitors is greatly reduced by the proposed scheme, due to the fact that the individual capacitor voltage is also lower than that of the conventional topology. Figures 15 and 16 were captured for the critical evaluation of the harmonic content contained at the output. These results show the THD waveforms of phase voltage, line voltage, and load current, respectively; from these results, it can be clearly understood that this inverter offers good quality of AC output without any lowest order harmonics (<3% of fundamental) for resistive load. All of the harmonic quantities are lower than 1.5% of the fundamental.

**Figure 13.** Capacitor voltages of the inverter during steady-state conditions.

**Figure 14.** Common mode capacitor voltages.

**Figure 15.** THD waveform of line voltage.

**Figure 16.** THD waveform of load current.

In order to assess the dynamic performance of the converter, sudden changes were incorporated during the operation of the converter at load (increased by 50% and decreased by 50%), and in the reference voltage (decreased by 50% and changed the phase by 180◦), and results were captured in each case for analysis. Figure 17 shows the current drawn by the 100% load (1.2 kW) from (0 to 0.04 s) and 50% load (0.6 kW) from (0.04 to 0.08 s), whereas Figure 18 depicts the opposite case of loading, i.e., 50% loading from (0 to 0.04 s) and 100% load from (0.04 to 0.08 s). Figure 19 was captured when the mode of operation is suddenly changed from active mode to regeneration mode at 0.04 s. Although the mode is changed from the active mode to the regeneration mode, the voltage amplitude remains constant, and its harmonics also remain the same. Figures 20–23 show the phase voltages, line voltages, load currents, and capacitor voltages observed when the reference voltage is suddenly changed from 100% to 50% at 0.04 s. Whenever the reference voltage is changed, the output voltage changes, and the current also changes accordingly for the resistive load. THD waveforms in the case in which the reference voltage is changed were captured after

the disturbance was settled, and are shown in Figures 23–25. These results (Figures 20–23) reveal that the CCBI with a sliding mode offers good dynamic response in stable operation, even for all kinds of disturbances, as discussed earlier.

**Figure 17.** Load current for a linear load with a step change in the load from 100 to 50%.

**Figure 18.** Load current for a linear load and a step change in the load from 100 to 50%.

**Figure 19.** Load current for the inversion mode of the load.

**Figure 20.** Phase voltages for a linear load and a step change in the reference load voltage from 100 to 50%.

**Figure 21.** Line voltages for a linear load and a step change in the reference load voltage from 100 to 50%.

**Figure 22.** Load currents for a linear load and a step change in the reference load voltage from 100 to 50%.

**Figure 23.** Capacitor voltages for a linear load and a step change in the reference load voltage from 100 to 50%.

**Figure 24.** Load voltage and load current for a linear load and a step change in the reference load voltage from 50%.

**Figure 25.** Load voltage and load current for a linear load and a step change in the reference load voltage from 100 to 33%.

For critical evaluation of the converter, the inverter output is fed to a nonlinear load (three-phase diode bridge rectifier with R Load of 255 Ω), and Figures 26–33 show the CCB inverter-fed diode bridge output currents and voltage, the diode bridge input line voltage and currents, the capacitor voltages of CCB and CMMCV, and the harmonic spectra of diode bridge input voltage and currents, respectively. Under steady-state mode, the diode bridge rectifier-fed resistive load absorbs the highly distorted current of 31.39% THD and voltage of 7.25% THD, as shown in Figures 32 and 33, respectively. All of the foregoing data show that the CCB inverter has good behavior, and particularly superior dynamic behavior, which is mostly due to the lower values of the boost capacitances and voltage across the capacitor. This performance is especially notable when compared to that of a current source inverter (CSI); whereas the proposed system employs three independent small inductors, the CSI employs only one large inductor, resulting in much poorer dynamic performance.

**Figure 26.** Non-linear load (diode bridge) output currents.

**Figure 27.** Non-linear load (diode bridge) output voltages.

**Figure 28.** Non-linear load (diode bridge) input voltages.

**Figure 29.** Non-linear load (diode bridge) input currents.

**Figure 30.** Capacitor voltages of the CCBI.

**Figure 31.** Common mode voltages of the CCBI.

**Figure 32.** CCBI voltage THD for the nonlinear (diode bridge) load.

**Figure 33.** CCBI current THD for the nonlinear (diode bridge) load.

*Comparison of the CCBI with ZSI:* For the same source and load, and required gain, ZSI is implemented with the shoot-through duty of 0.4091 and AC-side filter components of inductor Lf = 0.25 mH and capacitor Cf = 44 μH. Its load parameters, z-source capacitor voltages, and CMMV are presented in Figures 34–36.

**Figure 34.** Load voltage and current of ZSI.

**Figure 35.** Z-source capacitor voltages of ZSI.

**Figure 36.** Common mode voltages of ZSI.

From these results (Figures 21 and 34), it can be understood that peak voltages (956 V in the impedance source inverter and 910 V in the CCBI) and settling time to reach the steady state (0.065 s for the impedance source inverter and 0.021 s for the CCBI) are higher in the case of the impedance source inverter. The peak capacitor voltage is 1124 V in the case of the impedance source inverter, whereas it is 1056 V in the case of the CCBI. It can also be seen that CMMV in the case of the impedance source inverter has a PWM nature, as depicted in Figure 36, whereas it has a steady nature in the case of the CCBI, as depicted in Figure 14. Hence, it can be understood that the CCBI offers better performance for the single-stage power conversion.

In addition, in terms of the number of components, voltage and current THDs, capacitor voltage stresses, and boost factors, the performance of this inverter was compared to that of existing inverter topologies. Figures 37–40 provide these comparative characteristics. In comparison to other topologies, the implementation of the CCBI requires fewer components, as seen in Figure 37. As a result, the converter's cost, size, and volume are reduced. THD (both voltage and current) profiles of the proposed inverter, and the studied inverter topologies, were captured for comparative analysis. It is worth noting that, with the exception of the boost and CCBI topologies, AC filters are utilized on the AC side in all other topologies. The CCBI is able to deliver greater performance in terms of THDs even under these conditions, as seen in Figure 38.

**Figure 37.** Bar chart of no. of components used in different topologies.

**Figure 38.** THD values in different topologies.

**Figure 39.** Total capacitor stress in different topologies.

**Figure 40.** Boost factors in different topologies.

The total capacitor stresses in the CCBI are quite low as compared to other topologies, as shown in Figure 39. Because the capacitor is the most vulnerable component in an inverter in terms of reliability, reducing voltage stresses on the capacitor improves its reliability. As shown in Figure 40, the proposed converter is capable of providing superior gain than the existing topologies despite having fewer boosting factors. This function aids in the reduction in stresses on the inverter's capacitors and switches. Overall, the proposed inverters provide higher performance in terms of number of components, voltage and current THDs, capacitor voltage stresses, and boost factors, as evidenced by these comparative data.

*Experimentation Results:* For the experimental verifications, a laboratory-made test bench was developed, as illustrated in Figure 41. It consists mainly of six IRF460 MOSFETs (500 V, 16 A) driven by a TLP25-based optically isolated driver circuit, three EZPE50506MTA capacitors (15 μF), and three inductors (0.6 mH). Inductor currents and capacitor voltages are sensed by a TELCON-25 and AD202JN-based signal measurement and conditioning circuit.

**Figure 41.** Prototype of the boost inverter.

The quantities sensed by these sensor-based resistor networks are then applied to the corresponding multiplexer (HEF4052B) input terminals via filtering, amplifying, and biasing circuits. All of the sensed parameters are sent to the FPGA Spartan-3E kit via a multiplexer circuit. Two 2-channel multiplexers are used in time division multiplexing to independently process inductor currents and capacitor voltages. Inductor currents and capacitor voltages are time division multiplexed and processed on the FPGA kit's on-board ADC (LTC1407A). Internally, these signals are demultiplexed using VHDL code. Using demultiplexed inductor currents and capacitor voltages, a VHDL-programmed sliding mode controller generates gating pulses to the inverter.

This prototype was tested with a 150 V DC supply to demonstrate the proposed inverter's step-up capability, and the results were monitored in a closed-loop manner, with the control logic developed in an FPGA Sparta-3e XC3S500e board. The CCBI converts 150 V DC to three-phase AC with a peak voltage of 282 volts, 163.29 V (peak) phase voltage, and 4.89 A (peak) phase current. These conversion pole voltages are shown in Figure 42. Load currents are depicted in Figure 43. These findings show that the converter's performance is consistent with the simulation results. Simulation and hardware tests confirm that the inverter is performing proper DC-AC conversion.

**Figure 43.** Load current [1 A/div].

#### **4. Conclusions**

This research suggested and successfully validated a unique three-phase, step-up DC-AC converter for distributed power generation using both simulation and experimental data. This converter successfully demonstrated single-stage operation in the same way as any other impedance source converter. Both simulation and experimental results verified that the operating voltages across the capacitors are reduced, resulting in increased capacitor and converter reliability and longevity. In addition to the technology, this inverter offers a lower boosting factor for the necessary DC-AC conversion, thus requiring a lower dc link voltage. When compared to other impedance source converters for the same DC-AC conversion, this feature has a high side gate isolation voltage requirement. In this paper, detailed operations in various modes are presented, along with differential pulse width modulation and a sliding mode controller.

**Future work:** A performance investigation of the CCBI in electrical vehicle loads with different drive cycles, and in distributed power generation with different environmental conditions, can comprise the future scope of work.

**Author Contributions:** Writing—original draft and resources, D.R. and P.R.; conceptualisation, methodology, D.R. and P.R.; investigation, D.R., B.L.N. and Y.S.B.; review and editing, D.R., H.H.F. and E.R. All authors have read and agreed to the published version of the manuscript.

**Funding:** Unitatea Executiva Pentru Finantarea Invatamantului Superior a Cercetarii Dezvoltarii si Inovarii: PN-III-P4-ID-PCE-2020-0008.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Not applicable.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Nomenclature**

#### **References**

**Dong Yan, Lijun Hang \*, Yuanbin He, Zhen He and Pingliang Zeng**

College of Automation, Hangzhou Dianzi University, Hangzhou 310018, China<EMAIL_ADDRESS>(D.Y<EMAIL_ADDRESS>(Y.H<EMAIL_ADDRESS>(Z.H<EMAIL_ADDRESS>(P.Z.)

**\*** Correspondence<EMAIL_ADDRESS>
**Abstract:** The Gallium Nitride high electron mobility transistor (GaN HEMT) has been considered as a potential power semiconductor device for high switching speed and high power density application since its commercialization. Compared with the traditional Si transistors, GaN HEMT has faster switching speed and lower on-off loss. As a result, it is more sensitive to the nonlinear parameters due to the fast switching speed. The subsequent voltage and current overshooting will affect the efficiency and safety of the GaN HEMT and power electronic systems. In this paper, an accurate switching transient analytical model for GaN HEMT is proposed, which considers the effects of parasitic inductances, nonlinear junction capacitances and nonlinear transconductance. The model characteristic of turn-ON process and turn-OFF process is illustrated in detail, and the equivalent circuits are derived for each switching transition. The accuracy of the proposed model can be verified by comparing the predicted switching waveform and switching loss with that of the experimental results based on the double pulse test (DPT) circuit. Compared with the conventional model, the proposed model is more accurate and matches better with the experimental results than the conventional model. Finally, this model can be used for analyzing the influences of gate resistance, nonlinear junction capacitances, and parasitic inductances on switching transient waveform and refining calculation switching loss.

**Keywords:** GaN HEMT; switching transient analytical model; parasitic inductance; nonlinear junction capacitance; nonlinear transconductance; double pulse test

#### **1. Introduction**

GALLIUM NITRIDE (GaN) is a typical representative of the third generation wide band gap semiconductor materials and has a broad application prospect. In recent years, Gallium Nitride high electron mobility transistor (GaN HEMT) has been successfully applied to high frequency and high power density converters [1]. GaN HEMT can not only attain small conduction resistance, but also push the switching frequency to several megahertz when comparing with the state-of-the-art Si MOSFETs. Nevertheless, high frequency switching transient still brings some extra problems, such as voltage and current overshooting, and even instability. As a result, it is more sensitive to the nonlinear parameters because of high dv/dt and di/dt. Meanwhile, the subsequent switching process ringing will affect the efficiency and reliability of the GaN HEMT devices and power electronic systems [2]. In order to fully utilize the GaN HEMT, it is necessary to analyze the parameters' effects upon switching loss and the switching transient characteristic.

Generally, the switching transient of devices can be analyzed by experimental testing [3] or software simulation method [4]. However, these methods cannot give a definitive or analytical explanation of the influence mechanism of the nonlinear parameters in devices. Therefore, an accurate switching transient analytical model for estimating the switching loss and influence of nonlinear parameters is necessary.

The popular switching transient analytical model is the piecewise linear model [5]. However, the nonlinear parameters are not taken into account so that the calculated results

**Citation:** Yan, D.; Hang, L.; He, Y.; He, Z.; Zeng, P. An Accurate Switching Transient Analytical Model for GaN HEMT under the Influence of Nonlinear Parameters. *Energies* **2022**, *15*, 2966. https://doi.org/ 10.3390/en15082966

Academic Editor: Denis N. Sidorov

Received: 2 March 2022 Accepted: 14 April 2022 Published: 18 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

do not agree with the experimental results very well, especially in high frequency applications, since the switching transient and switching loss are not well evaluated. In study [6], a second-order analytical model is proposed. More comprehensive analytical models of Si MOSFETs are presented in [7–9]. These models consider the parasitic inductances and the nonlinear junction capacitances properly. On this basis, the authors of [10] apply the analysis model to develop the SiC MOSFET model, whereas, in some of the derivation, the parameter setting is idealistic. The nonlinear parameters' modeling results in [11] is too complex due to the numerical method or iterative calculations. In studies [12–14], the impact of nonlinear capacitance and nonlinear transconductance in SiC MOSFET is discussed, and a semi-physical semi-behavioral analytical model for switching transient of SiC MOSFET power module is proposed. However, these models are still not suitable for GaN HEMT devices, because GaN HEMT have no reverse recovery characteristics, and have smaller charge capacitance and parasitic inductance in contrast to Si MOSFET and SiC MOSFET [15].

In study [16], a switching loss model for GaN HEMT is proposed. The model considers the nonlinear junction capacitances as piecewise linear structure, so it still cannot precisely represent the nonlinear characteristics. In studies [17–19], the adopted interpolation method is used to fit nonlinear junction capacitances of GaN HEMT. However, this method has no specific mathematical expression and the results are too complex. In study [20], the package and PCB parasitic inductances, as well as the nonlinear capacitances are considered in the GaN HEMT model, but this model only includes the turn-ON process without switching loss calculation and parameter analysis. Some analytical models are proposed for cascode GaN HEMT [21,22]. These models cannot be directly applied to the GaN HEMT because of the different structure. Therefore, a more accurate switching transient analytical model for GaN HEMT is needed to explain the influence of nonlinear parameters and calculate the loss accurately. The main contributions of this paper are:

#### **2. Novel Analytical Model of GaN HEMT Device**

In order to test and evaluate the switching characteristics of GaN HEMT, a double pulse test (DPT) circuit with inductive load can be adopted as illustrated in Figure 1, where *Q* and *Q\_H* represent the lower switch and upper GaN HEMT device of the half bridge. In this paper, the GaN HEMT device of GS61004B produced by GaN systems company will be illustrated as an example. *Cgs*, *Cgd*, and *Cds* represent the capacitors of gate source, gate drain, and drain source, respectively. To simplify the circuit analysis, the parasitic inductance and package stray inductance are accounted into *Ld*, *Ls*, *Lg*. *Lloop* lumps all of the parasitic inductances and package stray inductances along the power loop. The GaN HEMT device does not contain a p-n diode, but the way they conduct in the reverse direction is similar to diodes because this channel is formed by turning on the two-dimensional electron gas (2DEG) in the device.

**Figure 1.** Circuit schematic of double pulse test bench.

In Figure 1, it is very important to determine the parasitic inductances and nonlinear parameters to obtain an accurate switching transient analytical model. Generally, the parasitic inductances can be acquired by Maxwell 3-D software and the nonlinear parameters can be obtained by the modeling method, such as the input capacitance *Ciss* = *Cgs* + *Cgd*, the output capacitance *Coss* = *Cds* + *Cgd*, and the reverse capacitance *Crss* = *Cgd*. *Ciss* and *Crss* can be fitted by simple piecewise linear equation due to their low degree of nonlinearity. However, *Coss* is a parameter that changes dramatically with the variation of *vds* at low voltage level, which is with high degree of nonlinearity, and is more difficult to be accurately modeled by the above methods. A nonlinear function tanh(*x*) will be introduced to represent *Coss* in this paper, as shown in Equation (1). This function can be used to approximate the *Coss* during switching process.

$$\tanh(\mathfrak{x}) = \frac{e^{\mathfrak{x}} - e^{-\mathfrak{x}}}{e^{\mathfrak{x}} + e^{-\mathfrak{x}}} \tag{1}$$

Based on tanh(*x*), a nonlinear function shown in Equation (2) is proposed to fitting the nonlinear characteristic of the *Coss* of GS61004B, which can model different changing rate of *Coss* when *vds* began to change in low voltage.

$$\mathcal{L}\_{\text{ess}} = \mathcal{L}\_{\text{owux}} (1 + \upsilon\_{\text{ds}} (1 + k\_1 (1 + \tanh(k\_2 \cdot \upsilon\_{\text{ds}} + k\_3))))^{k\_4} \tag{2}$$

where *Comax*, *k*1, *k*2, *k*3, and *k*4 are the fitting parameters and are given in Table 1. This method has more accuracy modeling results. The modeling results *Coss* of GaN HEMT is verified in Figure 2a, and it can be concluded that the maximum error between the fitted data and extracted data from the datasheet is less than 3%. Furthermore, this model can also be applied to other different types of devices by adjusting the parameters.

**Figure 2.** Modeling results and datasheet: (**a**) Nonlinear capacitances; (**b**) Transfer characteristic curves.

Transconductance *gfs* describes the dynamic behavioral feature of *ich* when *vgs* changes. Using a single value of transconductance has a large opportunity to cause great errors. In this paper, the slope of the tangent line in the transfer characteristic curve is used to approximate the transconductance at the corresponding operation point. Thus, the equation of *gfs* can be expressed as Equation (3).

$$\begin{cases} \begin{aligned} g\_{fs} &= 0 & v\_{\mathbb{S}^3} &< V\_{th} \\\ g\_{fs} = \frac{di\_{th}}{dv\_{\mathbb{S}^3}} &= k5 \left( v\_{\mathbb{S}^5} - V\_{th} \right)^{k\_6 - 1} & v\_{\mathbb{S}^3} &\ge V\_{th} \end{aligned} \tag{3}$$

where *k*5 and *k*6 are the fitting parameters which are given in Table 1 as well. *Vth* is the threshold voltage of gate to source for the device. Figure 2b shows the curve of *ich* versus *vgs*. It is obvious that the modeling result makes an accurate estimation based on the proposed model.

#### **3. Transient Characteristic Analysis of Turn-On Process Based on the Proposed Model**

A typical waveform during turn-ON process of the GaN HEMT half bridge is shown in Figure 3. There are four stages during the switching process and each stage has different features according to the change of the circuit structure. At each stage, the equations can be obtained from the corresponding equivalent circuit which is illustrated in Figure 4. By solving the equations, we can obtain five variables, namely, the gate current *ig*, the gate source voltage *vgs*, the drain current *id*, the drain source voltage *vds*, and the drain source voltage *vds\_H*. The nonlinear junction capacitance and nonlinear transconductance modeling results proposed in Section 2 will be applied to the turn-ON process in the

following analysis. Thus, the analytical model of each variable during turn-ON process can be derived. Furthermore, the switching loss during the turn-ON process can be obtained.

**Figure 3.** Typical waveforms during turn-ON process.

**Figure 4.** Equivalent circuits for different stages during turn-ON period: (**a**) Stage I; (**b**) Stage II; (**c**) Stage III; (**d**) Stage IV.

#### *3.1. Stage I (t0–t1): Turn-On Delay Period*

As shown in Figure 3, at time *t*0, the gate drive voltage *Vg* is applied. In this stage, the gate current charges the capacitance *Cgs* which causes *vgs* to rise. The equivalent circuit of this stage is shown in Figure 4a. According to the equivalent circuit, the following equations can be obtained:

$$V\_{\mathcal{S}} = (L\_{\mathcal{S}} + L\_{\mathfrak{s}}) \frac{di\_{\mathfrak{s}}}{dt} + R\_{\mathfrak{s}} i\_{\mathfrak{s}} + v\_{\mathfrak{s}^{\mathfrak{s}}} \tag{4}$$

$$d\_{\mathcal{S}} = \mathcal{C}\_{\mathcal{S}^s} \frac{d\upsilon\_{\mathcal{S}^s}}{dt} \tag{5}$$

This stage ends at time *t*1 when *vgs* reaches the threshold voltage *Vth*. During this stage, *Q* is still OFF, the drain source voltage *vds*, and the drain current *id* are constant, so there is no switching loss.

#### *3.2. Stage II (t1–t2): Current Rise Period*

As shown in Figure 3, at time *t*1, *vgs* reaches the threshold voltage *Vth*, and the channel current *ich* begins to rise which can be expressed by Equation (3). At the same time, the capacitances *Coss* begins to discharge through the channel of *Q*. The drain current id is clamped to the sum of the channel current *ich* and the *Coss* discharging current. However, *Q\_H* is still in reverse conduction condition, where *Ron* is the on-state resistance and *Vr* represents the reverse conducting voltage drop of *Q\_H*. There will be a voltage drop Δ*V* between *vds* and its initial voltage *VDC* + *Vr* on the parasitic inductance of the power loop. As shown in the equivalent circuit of Figure 4b, the equations of this stage are as follows:

$$V\_{\mathcal{S}} = v\_{\mathcal{S}^5} + R\_{\mathcal{S}}i\_{\mathcal{S}} + L\_{\mathcal{S}}\frac{di\_{\mathcal{S}}}{dt} + L\_{\mathcal{s}}(\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{6}$$

$$i\_{\mathcal{S}} = \mathbb{C}\_{\mathbb{S}^{\mathfrak{s}}} \frac{dv\_{\mathbb{S}^{\mathfrak{s}}}}{dt} + \mathbb{C}\_{\mathbb{S}^{d}} (\frac{dv\_{\mathbb{S}^{\mathfrak{s}}}}{dt} - \frac{dv\_{\mathbb{S}^{\mathfrak{s}}}}{dt}) \tag{7}$$

$$\dot{u}\_d = \mathcal{g}\_{fs}(\upsilon\_{\mathcal{S}^s} - V\_{th}) + \mathbb{C}\_{ds}\frac{d\upsilon\_{ds}}{dt} - \mathbb{C}\_{\mathbb{g}d}\frac{d(\upsilon\_{\mathcal{S}^s} - \upsilon\_{ds})}{dt} \tag{8}$$

$$V\_{DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} + L\_s \frac{di\_s}{dt} \tag{9}$$

$$
\upsilon\_{ds\\_H} = R\_{on}(I\_L - i\_d) - V\_r \tag{10}
$$

This stage ends when the drain current *id* reaches the load current *IL*. Meanwhile, *vgs* reaches Miller plateau voltage. It should be especially noted that the voltage drop Δ*V* is shown in the following equation:

$$
\Delta V = (L\_d + L\_s) \frac{d\dot{l}\_d}{dt} \tag{11}
$$

In case of *Ld* and *Ls* being larger, Δ*V* will drop faster, so *id* would change even slower than *vds*. The transient will skip the voltage drop stage III into ringing stage IV directly. While for small *Ld* and *Ls* of properly designed PCB and reasonable current rising speed, stage III will occur as expected.

During this stage, the energy loss can be expressed as:

$$E\_{\rm ou} = \int\_{t2}^{t1} v\_{ds} \cdot i\_{\rm ch} dt \tag{12}$$

The power loss in this stage can be determined by:

$$\begin{aligned} P\_{\text{on}} &= f\_{\text{s}} \cdot E\_{\text{on}} \\ &= f\_{\text{s}} \cdot \int\_{t2}^{t1} v\_{ds} \cdot i\_{\text{ch}} dt \end{aligned} \tag{13}$$

where *fs* is the switching frequency. However, only id can be measured experimentally, ich cannot. During the turn-ON process, a part of the energy stored in *Coss* is dissipated through the channel, which is not included in the loss calculated by *id*. Thus, the relationship can be expressed as:

$$P\_{\rm out} = f\_{\rm s} \cdot \int\_{t2}^{t1} v\_{\rm ds} \cdot i\_d dt + P\_{\rm Cons} \tag{14}$$

where *PCoss* represents the energy stored in the output capacitance when the applied voltage is *VDC* + *Vr* and can be expressed as:

$$P\_{\text{Coss}} = f\_s \cdot \int\_0^{V\_{D\subset} + V\_r} v\_{ds} \cdot \mathbb{C}\_{\text{oss}}(v\_{ds}) dv\_{ds} \tag{15}$$

*Coss*(*vds*) can be determined by Equation (2), which is plotted in Figure 2a.

#### *3.3. Stage III (t2–t3): Voltage Decline Period*

As shown in Figure 3, at time *t*2, the upper switch GaN HEMT device *Q\_H* stops conducting, and the channel current *ich* surpasses the load current *IL*. This surpasses current charge of the output capacitance *Coss\_H* of *Q*\_*H*. The upper switch can be equivalent to the output capacitor *Coss\_H*, and *vds\_H* is increased. Correspondingly, *vds* decreases and *Coss* continues to discharge through the channel of *Q*. *id* may have a ringing because of the effect of parasitic *LC* elements on the device. The equivalent circuit of this stage is illustrated in Figure 4c. The circuit equations can be expressed as:

$$\dot{m}\_d = g\_{fs}(\upsilon\_{\mathcal{S}^s} - V\_{th}) + \mathbb{C}\_{ds}\frac{d\upsilon\_{ds}}{dt} - \mathbb{C}\_{\mathcal{g}d}\frac{d(\upsilon\_{\mathcal{S}^s} - \upsilon\_{ds})}{dt} \tag{16}$$

$$V\_{\mathcal{S}} = \upsilon\_{\mathcal{S}^5} + R\_{\mathcal{S}} i\_{\mathcal{S}} + L\_{\mathcal{S}} \frac{di\_{\mathcal{S}}}{dt} + L\_{\mathcal{s}} (\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{17}$$

$$\dot{a}\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^{\mathfrak{s}}} \frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt} + \mathbb{C}\_{\mathfrak{g}d} (\frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt} - \frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt}) \tag{18}$$

$$V\_{DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} + L\_s \frac{di\_s}{dt} \tag{19}$$

$$i\_d = I\_L + C\_{\text{oss\\_}H} \frac{d\upsilon\_{ds\\_ H}}{dt} \tag{20}$$

This period ends when *vds* decreases to zero. A current overshoot is caused by the rapid *dv/dt* action on the output capacitance:

$$
\Delta \dot{t}\_d = \mathbb{C}\_{oss\\_H} \frac{dv\_{ds\\_H}}{dt} - \mathbb{C}\_{oss} \frac{dv\_{ds}}{dt} \tag{21}
$$

In addition, the Miller plateau time on *vgs* for GaN HEMT is less than Si MOSFET because of small transfer capacitance *Cgd*. This characteristic can help us to understand why GaN HEMT can turn-ON at a high speed. The turn-ON switching loss calculation method is the same as that of Equation (15).

#### *3.4. Stage IV (t3–t4): Ringing Period*

As shown in Figure 3, at time *t*3, *Q* will work in the linear region and behave equivalent to a loop resistor, as illustrated in Figure 4d. Usually, the ringing is serious due to small damping resistance with large parasitic inductances. The key equations can be expressed as:

$$V\_{\mathcal{S}} = v\_{\mathcal{S}^s} + R\_{\mathcal{S}}i\_{\mathcal{S}} + L\_{\mathcal{S}}\frac{di\_{\mathcal{S}}}{dt} + L\_{\mathcal{s}}(\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{22}$$

$$i\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^{\rm s}} \frac{dv\_{\mathcal{S}^{\rm s}}}{dt} + \mathbb{C}\_{\mathcal{S}^{\rm d}} (\frac{dv\_{\mathcal{S}^{\rm s}}}{dt} - \frac{dv\_{\mathcal{S}^{\rm s}}}{dt}) \tag{23}$$

$$V\_{DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} + L\_s \frac{di\_s}{dt} \tag{24}$$

$$i\_d = \frac{v\_{ds}}{R\_{on}} + \mathcal{C}\_{ds}\frac{dv\_{ds}}{dt} - \mathcal{C}\_{\text{gd}}\frac{d(v\_{\text{gs}} - v\_{ds})}{dt} \tag{25}$$

$$i\_d = I\_L + \mathcal{C}\_{\text{oss\\_}H} \frac{dv\_{ds\\_H}}{dt} \tag{26}$$

where *Ron* represents the on-state resistance of *Q*. During this stage, the turn-ON switching loss can be expressed as:

$$P\_{on} = f\_s \cdot \int\_{t4}^{t3} (i\_d - I\_L)^2 \cdot R\_{on} dt \tag{27}$$

This period ends when the ringing is fully damped.

#### **4. Transient Characteristic Analysis of Turn-Off Process Based on the Proposed Model**

There are still four stages and the typical waveforms during turn-OFF process. At each stage, the equations can be obtained from each equivalent circuit. Similarly, the nonlinear junction capacitance and nonlinear transconductance modeling results proposed in Section 2 are applied to the turn-OFF process and five state variables can be calculated according to the equations obtained from the equivalent circuit of each stage. Furthermore, the switching loss during the turn-OFF process can be obtained. The calculation of each stage will be discussed as follows.

#### *4.1. Stage I (t5–t6): Turn-Off Delay Period*

As shown in Figure 5, at time *t*5, the gate drive voltage *Vg* declines to 0 V. In this stage, *Cgs* and *Cgd* are discharged, so *vgs* begins to reduce. However, *Q* is still in the turn-ON state, *IL* keeps flowing through the channel of *Q*. The equivalent circuit of this stage is shown in Figure 6a. The following equations can be obtained:

$$0 = (L\_{\mathfrak{g}} + L\_{\mathfrak{s}})\frac{d\dot{l}\_{\mathfrak{g}}}{dt} + R\_{\mathfrak{g}}\dot{l}\_{\mathfrak{g}} + v\_{\mathfrak{g}^{\mathfrak{s}}} \tag{28}$$

$$d\_{\mathfrak{J}} = (\mathbb{C}\_{\mathfrak{J}^{\mathfrak{z}}} + \mathbb{C}\_{\mathfrak{J}^d}) \frac{dv\_{\mathfrak{J}^{\mathfrak{z}}}}{dt} \tag{29}$$

This period ends at time *t*6 when *vgs* reaches the Miller plateau voltage *vmiller*.

$$v\_{miller} = V\_{th} + \frac{I\_L}{\mathcal{S}\_{fs}}\tag{30}$$

*vds* and *id* are constants, so there is no turn-OFF switching loss in this stage.

**Figure 5.** Typical waveforms during turn-OFF process.

**Figure 6.** Equivalent circuits for different stages during turn-OFF process: (**a**) Stage I; (**b**) Stage II; (**c**) Stage III; (**d**) Stage IV.

#### *4.2. Stage II (t6–t7): Voltage Rise Period*

As shown in Figure 5, at time *t*6, the channel of *Q* starts to turn-OFF, so the channel current *ich* decreases and begins to charge the capacitances *Cds* and *Cgd*, then *vds* is rapidly increased. At the same time, *Coss\_H* begins to discharge, resulting in the decline of *vds\_H*. However, *Q*\_*H* is still not reverse conducting because *id* is limited by the power loop parasitic inductances. Therefore, the decrease rate of *id* is smaller than that of *ich*. The equivalent circuit is shown in Figure 6b, and the equations of this stage are as follows:

$$0 = v\_{\mathcal{S}^s} + R\_{\mathcal{S}} i\_{\mathcal{S}} + L\_{\mathcal{S}} \frac{di\_{\mathcal{S}}}{dt} + L\_s (\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{31}$$

$$d\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^s} \frac{dv\_{\mathcal{S}^s}}{dt} + \mathbb{C}\_{\mathcal{S}^d} (\frac{dv\_{\mathcal{S}^s}}{dt} - \frac{dv\_{ds}}{dt}) \tag{32}$$

$$\dot{\mathbf{u}}\_d = \mathcal{g}\_{fs}(\upsilon\_{\mathcal{S}^s} - V\_{th}) + \mathcal{C}\_{ds}\frac{dv\_{ds}}{dt} - \mathcal{C}\_{gd}\frac{d(\upsilon\_{\mathcal{S}^s} - \upsilon\_{ds})}{dt} \tag{33}$$

$$V\_{\rm DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} \tag{34}$$

$$i\_d = I\_L + \mathcal{C}\_{\text{oss\\_}H} \frac{dv\_{ds\\_ H}}{dt} \tag{35}$$

This period ends when *vds\_H* reaches −*Vr*. During this stage, the energy loss can be calculated as:

$$E\_{off} = \int\_{t7}^{t6} v\_{ds} \cdot i\_{ch} dt \tag{36}$$

The power loss in this stage can be determined by:

$$\begin{aligned} P\_{off} &= f\_{\text{s}} \cdot E\_{off} \\ &= f\_{\text{s}} \cdot \int\_{t\mathcal{T}}^{t\mathbf{6}} v\_{ds} \cdot i\_{ch} dt \end{aligned} \tag{37}$$

Usually, the energy stored in *Coss* is quite large due to the high peak *vds*. The power loss is different from turn-ON process because *id* contains the charge current from *Coss*. Thus, the relationship can be modified as:

$$P\_{off} = f\_s \cdot \int\_{t7}^{t6} \upsilon\_{ds} \cdot i\_d dt - P\_{\text{Coss}} \tag{38}$$

where *PCoss* is the energy stored in *Coss* when the applied voltage is *v*Peak and can be calculated as:

$$P\_{\rm CSS} = f\_{\rm s} \cdot \int\_0^{v\_{\rm peak}} v\_{\rm ds} \cdot \mathbb{C}\_{\rm loss}(v\_{\rm ds}) dv\_{\rm ds} \tag{39}$$

*C*oss(*vds*) can be determined by Equation (2) and is plotted in Figure 2a.

#### *4.3. Stage III (t7–t8): Current Decline Period*

As shown in Figure 5, at time *t*7, *Q*\_*H* starts to reverse conduct. During this stage, *id* and *vgs* decreases, *vds* continues to increase, and *Cds* and *Cgd* are charged. The equivalent circuit is shown in Figure 6c, and the circuit equations can be expressed as:

$$0 = v\_{\mathcal{S}^s} + R\_{\mathcal{S}} i\_{\mathcal{S}} + L\_{\mathcal{S}} \frac{di\_{\mathcal{S}}}{dt} + L\_s (\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{40}$$

$$\dot{a}\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^{\mathfrak{s}}} \frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt} + \mathbb{C}\_{\mathfrak{g}d} (\frac{dv\_{\mathcal{S}^{\mathfrak{s}}}}{dt} - \frac{dv\_{\mathrm{ds}}}{dt}) \tag{41}$$

$$i\_d = g\_{fs}(v\_{\mathcal{S}^s} - V\_{th}) + \mathcal{C}\_{ds}\frac{dv\_{ds}}{dt} - \mathcal{C}\_{\mathcal{gd}}\frac{d(v\_{\mathcal{S}^s} - v\_{ds})}{dt} \tag{42}$$

$$V\_{DC} = v\_{ds} + v\_{ds\\_H} + (L\_d + L\_s)\frac{di\_d}{dt} + L\_s \frac{di\_s}{dt} \tag{43}$$

$$
\upsilon\_{ds\\_H} = R\_{on}(I\_L - i\_d) - V\_r \tag{44}
$$

This stage ends when *id* drops to zero. The turn-OFF power loss calculation method is the same as Stage II.

#### *4.4. Stage IV (t8–t9): Ringing Period*

As shown in Figure 5, at time *t*8, when *vgs* drops below *Vth*, the channel of *Q* is totally shut down. Then *vgs* continues to decrease until it reaches zero. During this stage, *vds* and *id* both have a ringing due to the oscillation between the parasitic inductances and *Coss*. The equivalent circuit is shown in Figure 6d, and the circuit equations can be expressed as:

$$0 = v\_{\mathcal{S}^\mathfrak{s}} + R\_{\mathcal{S}} i\_{\mathcal{S}} + L\_{\mathcal{S}} \frac{di\_{\mathcal{S}}}{dt} + L\_{\mathfrak{s}} (\frac{di\_d}{dt} + \frac{di\_{\mathcal{S}}}{dt}) \tag{45}$$

$$i\_{\mathcal{S}} = \mathbb{C}\_{\mathcal{S}^s} \frac{dv\_{\mathcal{S}^s}}{dt} + \mathbb{C}\_{\mathcal{S}^d} (\frac{dv\_{\mathcal{S}^s}}{dt} - \frac{dv\_{\mathcal{S}^s}}{dt}) \tag{46}$$

$$i\_d = \mathcal{C}\_{ds}\frac{dv\_{ds}}{dt} - \mathcal{C}\_{\mathbb{S}^d}\frac{d(v\_{\mathbb{S}^\mathbf{s}} - v\_{ds})}{dt} \tag{47}$$

$$V\_{DC} + V\_r = v\_{ds} + (L\_d + L\_s)\frac{di\_d}{dt} \tag{48}$$

During this stage, the turn-OFF power loss calculation method can be expressed as:

$$P\_{off} = f\_s \cdot \int\_{t9}^{t8} i\_d \cdot v\_{ds} dt \tag{49}$$

This period ends when the ringing is fully damped.

#### **5. Experimental Verifications**

In order to verify the accuracy of the proposed switching transient analytical model, a DPT experiment prototype was built, as shown in Figure 7. The double pulses will be applied to the gate of the bottom GaN HEMT by TMS320F28335. The device under test is the GS61004B 100 V enhanced GaN HEMT and the driver is Si8271. The oscilloscope is MDPO3054 by Tektronix Inc. The switching current is measured with 2000 MHz bandwidth current shunt SSDN-10 by T&M Research Products Inc. The parasitic inductance and package stray inductance can be acquired by Maxwell 3-D. The specifications and the main circuit parameters are shown in Table 2. The comparisons among the switching waveforms provided by the experiment, the proposed model, and the traditional mode in [16] are shown in Figure 8. The calculated results from the models for the variables *vds* and *id* with fitting value from Figure 2 will be used to evaluate the model accuracy. The loss calculation results are shown in Figure 9.

**Figure 7.** Experiment circuit prototype.

**Table 2.** Specifications and main circuit parameters.

It can be concluded that the proposed model matches more accurately with the experimental results than the traditional model according to the slope and spike of *id* and *vds* from Figure 8. The oscillation frequency and amplitude of the waveforms from the experimental results deviate from the traditional model while the proposed model results agree with that accurately. The reason is that the traditional model treats the nonlinear parameters in the device as fixed values.

Subsequently, the energy loss of *Eon* and *Eoff* is calculated by the proposed loss calculation method as shown in Figure 9. The results show that the energy loss increases when

the load current changes from 5 A to 10 A. It is obvious that the loss calculation results of the proposed model in this paper are more precise compared with the traditional model. Experiment results verify the accuracy of the proposed loss calculation method with a maximum relative error of less than 10%. Finally, it can be concluded that the proposed switching transient analytical model is quite accurate and the loss analysis results based on the model is believable.

**Figure 8.** Switching waveforms of the experiment, the proposed model, and the traditional model: (**a**) *VDC* = 40 V, *IL* = 7 A; (**b**) *VDC* = 60 V, *IL* = 7 A; (**c**) *VDC* = 40 V, *IL* = 15 A.

**Figure 9.** Switching loss of the experiment, the proposed model, and the traditional model: (**a**) turn-ON energy loss; (**b**) turn-OFF energy loss.

#### **6. Effect of Parameter Variation on the Analytical Model**

The effectiveness of the proposed switching transient analytical model is verified in the previous section. Moreover, it is important to evaluate how the gate resistance *Rg*, the nonlinear junction capacitances *Cgs*, *Cgd*, *Cds*, and the parasitic inductance *Lloop* affect the switching transient and switching loss, thus the further improvement of packaging and application of the device can be inspired.

Figure 10 shows the effect of different driving resistors *Rg* on the switching transition behavior. The waveforms of *vds* and *id* are plotted. It can be seen that the oscillation of *vds* and *id* can be effectively suppressed by increasing the *Rg*. However, the larger *Rg* limits the gate charging current and reduces the charging speed, thus resulting the switching time increase of the device. In addition, Figure 10 also calculates the influence of different *Rg* on switching loss. With the increase of *Rg*, the turn-ON and turn-OFF switching loss is also increased. However, with the increase of *Rg*, the current overshoot for turn-ON transient and the voltage overshoot for turn-OFF transient decreased. Therefore, considering the impact of switching loss and overshoot in practical application, it is necessary to select an appropriate *Rg* value.

In order to simplify the analysis, *Lloop* lumps all of the parasitic inductances and package stray inductances along the power loop. As the package stray inductances are accounted into *Ld* and *Ls*, so *Lloop* is the sum of *Ld* and *Ls*. The effect of different *Lloop* on the switching transition behavior is shown in Figure 11. During the turn-ON process, the change rate of *id* and *vds* become slower with the increase of *Lloop*. Meanwhile, the current overshoot decreases but the voltage overshoot increases. In addition, the ringing period of *id* and *vds* becomes larger. These factors cause the turn-ON switching loss to become larger due to overlap area increases. During the turn-OFF process, the increase of *Lloop* has an obvious influence on *id* overshoot, which also leads to the increase of loss. It can be concluded that the total loss also increases, therefore, the value of *Lloop* should be minimized as much as possible on the PCB design and optimization process.

For the same type of GaN HEMT, the value of the nonlinear junction capacitances should be the same. However, due to different production processes or different production lines, the capacitance values may change. In order to explore the effect of the nonlinear junction capacitance on the switching transient, we make corresponding changes for each nonlinear junction capacitance value within a reasonable range.

The influence of *Cgs* is shown in Figure 12. Set the variation value of *Cgs* as 200 pF, 400 pF, 600 pF. It is observed that the increasing of *Cgs* caused the charge time to become longer, thus resulting in the turn-ON delay time notably increasing. Meanwhile, the current overshoot and the voltage overshoot during the turn-OFF process can be suppressed by increasing *Cgs*. In general, *Cgs* can effectively reduce the waveform oscillation, but will also lead to an increase in switching loss. Therefore, an extra capacitor paralleled with *Cgs* can

be used to reduce the oscillation when the oscillation is too large. However, the value of the parallel capacitor should be selected properly, otherwise the loss will be too large.

**Figure 10.** Influence of different *Rg* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

**Figure 11.** Influence of different *Lloop* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

**Figure 12.** Influence of different *Cgs* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

The effect of *Cgd* is shown in Figure 13. As stated previously, the increase of *Cgd* has a large effect on the switching loss model. It can be concluded that the magnitude of *Cgd* mainly affects the turn-ON process, i.e., the change rate of *id* and *vds* decreases and the conducting time increases. Although the increase of *Cgd* is only 5 pF–15 pF, it has a great impact on the on-off time and switching loss due to the capacitor which affects the length of Miller platform time. Therefore, *Cgd* should be designed as small as possible in device production. Compared with the Si devices, GaN HEMT is able to achieve much faster switching speeds and lower switching losses due to its smaller *Cgd*.

The influence of *Cds* is shown in Figure 14. As we know, *Coss* is a nonlinear junction capacitance of *vds*. It can be concluded that the increase of *Cds* mainly affects the change rate of *id*. Since *Coss* increases with the increase of *Cds*, according to Equation (17), the energy stored in *Coss* will increase, which will result in an increase in the switching loss. In addition, the switching speed is increased and the ringing period becomes larger. For the convenience of overall consideration, the influencing parameter of switching characteristics and their specific impact analysis are listed in Table 3.

**Figure 13.** Influence of different *Cgd* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

**Figure 14.** Influence of different *Cds* on the switching transient: (**a**) turn-ON process; (**b**) turn-OFF process.

**Table 3.** Analysis of The Influencing Parameter of Switching Characteristics.

#### **7. Conclusions**

In this paper, an accurate switching transient analytical model for GaN HEMT under the influence of nonlinear parameters was proposed. The proposed model covers the process of turn-ON and turn-OFF, which is of great significance in understanding the dynamic characteristics during the switching process. In addition, this model can be applied to evaluate the influence of parameter changes on the switching characteristics of devices, and calculate the switching loss. Finally, the following conclusions can be drawn:

**Author Contributions:** All authors contributed to the writing and revisions; writing—review and editing, L.H.; writing—original draft, D.Y.; review, Y.H.; review, Z.H.; supervision, P.Z. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the National Natural Science Foundation of China, grant numbers 51777049, 51707051.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** Data available on request due to privacy or ethical restrictions.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

### *Article* **Three-Level Active Power Filter Based on Model Predictive Control**

**Hanying Gao 1,\*, Weihao Zhang 1, Mingjie Ren 2 and Xiangnan Liu 1**

**Abstract:** The model predictive control (MPC) algorithm is used in the harmonic compensation of active power filter (APF), which has a fast dynamic response and does not require a PWM modulation model. However, this method has some shortcomings, such as the mass computing and difficult selections of weight factors. To solve these problems, this paper proposes a single objective function improved MPC algorithm based on sector judgment, which only takes the reference current and feedback current as the objective function, omits the weight coefficient setting process, and reduces the number of rolling optimization from 27 to 7, thus reducing the computing time and control complexity. The improved model predictive control is applied to APF. Finally, the simulations and experiments show that the improved MPC algorithm is accurate and efficient.

**Keywords:** model predictive control; objective function; sector judgment; active power filter; small vectors

#### **1. Introduction**

With the advancement of power electronics technology and the development of manufacturing industry, more and more nonlinear devices are put into use. The input of these nonlinear loads brings a huge harmonic interference and a reactive power impact on the power grid. If not treated, it brings a huge pollution to the power grid, and causes major economic losses and safety accidents. The active power filter has excellent dynamic response, real-time performance, and controllability. It is an ideal device for compensating harmonics and improving power quality [1–4]. The three-level APF has the advantages of large capacity, more output levels and small filter inductance. It is widely used in medium and low voltage occasions [5–7]. At present, the studies on the three-level APF mainly focus on the optimization of control algorithm.

The studies on the optimization of the three-level control algorithm mainly focus on the harmonic current tracking strategy. The mature tracking strategies include the proportional integral control, hysteresis control, proportional resonance control, and model predictive control [8–11]. The PI control algorithm is not suitable for ac tracking [12]. More precisely, the response speed of hysteresis controller is affected by the loop width, while the loop width of different systems is difficult to adjust, and it is also difficult to balance the selection between switching frequency and tracking effect, which limits the use of this algorithm [13]. In general, in order to take the computational load and compensation performance into consideration, the proportional resonance control algorithm is only used for tracking specific harmonic frequency segments [14]. As a novel current tracking control algorithm, the model prediction has the advantages of fast dynamic response, flexible control and good stability. It has been widely used in the control of power converters [15,16].

The model predictive control mainly samples the device output current at the current time, and substitutes it into the established system mathematical model in order to predict

**Citation:** Gao, H.; Zhang, W.; Ren, M.; Liu, X. Three-Level Active Power Filter Based on Model Predictive Control. *Electronics* **2022**, *11*, 1291. https://doi.org/10.3390/ electronics11091291

Academic Editor: Maciej Ławry ´nczuk

Received: 3 March 2022 Accepted: 8 April 2022 Published: 19 April 2022

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2022 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

the future device output current information according to the current or past current information [17]. Compared with other control algorithms, the model predictive control has great advantages in nonlinear systems, and can better deal with problems such as multiinput, multi variable, and multi constraint conditions [18]. However, the model prediction includes a rolling optimization process, which requires lot of processing time, thus reducing the dynamic performance of the model predictive control [19]. The weight factor reflects the importance of the objective function. It plays a crucial role in the control effect of the target. Therefore, when controlling the multi-objective function, the desired control effect can be obtained by adjusting the weight factor [20,21]. Although the model prediction can unify multiple constraints by adjusting the weight factor, it is difficult to adjust the weight coefficient in engineering applications. In [22], the model predictive control algorithm is applied to the three-phase four leg APF in order to predict the reference current and compensation current, and therefore perform harmonic compensation. However, this method has many rolling times, and the weight factor should be adjusted, which increases the complexity of the system. The authors in [23] apply model predictive control to the current tracking control of the three-level APF system. Although the values of the required parameters in the system are analyzed, a specific setting method of the parameters does not exist. The authors in [24] first classify different types of the objective function and weight factors, and then adjust the weight factors. This method has an excellent control effect. However, it is complex and it has a large computational load, which limits its use in practical application. Another approach [25] combines the model predictive control algorithm with a neural network algorithm. Compared with the traditional MPC algorithm, this method does not require an accurate mathematical model, and significantly improves the dynamic response ability of the APF system. However, the implementation process of this method is complex, and therefore it is difficult to be used in several application domains. The method in [26] applies the model predictive control algorithm to the T-type three-level neutral point clamped (NPC) inverter. It uses the predictive control for the grid current and capacitor voltage. Although the maximum power output and DC side capacitor voltage are stable, a specific setting method for the weight factor does not exist. The method in [27] introduces the idea of mixed logic dynamic (MLD) modeling into MPC control. Although the accuracy of the prediction model is improved, the modeling of this method is complex and difficult to implement. The authors in [28] select the optimal voltage vector according to the inverter output power and DC side voltage. They then optimize multiple objective functions by a constraint term, omitting the setting process of weighting factors. However, this method has more rolling times and a large computational load.

In this paper, a single objective function improved model predictive control algorithm based on sector judgment is proposed. It only takes the given current and feedback current as the objective function, determines the optimal voltage vector according to the influence of small vector and the change of DC voltage, omits the setting process of weight coefficient, and, finally, reduces the rolling optimization times to 7 times by judging the sector. The complexity of the algorithm is reduced and the dynamic response ability of APF system is improved. Finally, the improved MPC algorithm is applied to NPC three-level APF, and the correctness and feasibility of the algorithm are proved by system simulation and experiments.

#### **2. NPC Topological Structure Analysis**

#### *2.1. NPC Topological Structure and Working Principle*

Figure 1 shows the NPC three-level topology, which is composed of 6 diodes, 2 capacitors, and 12 switches. The midpoint of the 3 pairs of diodes is connected with point O. By controlling the switch, each phase of the topology can output three voltage states. The working process of the topology is analyzed as follows.

**Figure 1.** NPC three-level topology.

Considering point O as the zero potential reference point, in order to maintain the balance of two capacitors, that is, the voltage of each capacitor is +*V*dc/2, three levels can be output by changing the on and off states of the switch according to the modulation strategy: +*V*dc/2, 0, and −*V*dc/2.

For the convenience of analysis, the topological phase voltage output +*V*dc/2 is defined as P state, output −*V*dc/2 is N state and output 0 is O state. The NPC topology line voltage output has five states: +*V*dc, +*V*dc/2, 0, −*V*dc/2, and −*V*dc. Table 1 can be obtained by summarizing the three working states of NPC three-level topology.

**Table 1.** Relationship between switch status and output voltage.

Where: 1 represents the switch on, and 0 represents the switch off.

*2.2. Mathematical Model of Three-Level NPC APF*

According to the analysis, the output level function is given by:

$$\begin{array}{c} \text{1. (P) } S\_{x1}, S\_{x2} \text{ on } S\_{x3}, S\_{x4} \text{ off} \\ \text{2. (O) } S\_{x2}, S\_{x3} \text{ on } S\_{x1}, S\_{x4} \text{ off} \\ \text{ -1(N) } S\_{x3}, S\_{x4} \text{ on } S\_{x1}, S\_{x2} \text{ off} \end{array} \tag{1}$$

where: *Sx* is the output level function, and *x* has the value a, b, or c.

Block diagram of NPC three-level APF, as shown in Figure 2. Assuming that the grid is symmetrical without distortion and only contains the fundamental component, the three-phase load symmetrically ignores the line parasitic inductance and only considers the AC side output filter inductance. It also ignores the system line and device loss, and only considers the inductance internal resistance. Moreover, the three-phase inductance internal resistances are equal (*R* = *R*a = *R*b = *R*c), and the DC side capacitances are all equal to C.

**Figure 2.** Schematic diagram of NPC three-level APF.

According to these assumptions and to the Kirchhoff voltage law (KVL), the mathematical model of the APF system is expressed as:

$$\begin{cases} \left(\mu\_{\rm AO} + \mu\_{\rm ON}\right) = R i\_{\rm CA} + L \frac{d i\_{\rm CA}}{dt} + \mu\_{\rm sa} \\ \left(\mu\_{\rm BO} + \mu\_{\rm ON}\right) = R i\_{\rm CB} + L \frac{d i\_{\rm CB}}{dt} + \mu\_{\rm sb} \\ \left(\mu\_{\rm CO} + \mu\_{\rm ON}\right) = R i\_{\rm CC} + L \frac{d i\_{\rm CC}}{dt} + \mu\_{\rm sc} \end{cases} \tag{2}$$

where: *us*a, *us*b, and *us*c are the three-phase voltage, *i*CA, *i*CB, and *i*CC are the system compensation currents, *u*AO, *u*BO, and *u*CO are the potential voltages between the output point of each phase and the reference point O of the NPC topology, *u*ON is the voltage between the DC side neutral point and grid neutral point. *U*AO, *u*BO, and *u*CO can be expressed as (3).

$$
\mu\_{\text{xo}} = \frac{1}{2} S\_{\text{x}} \mathcal{U}\_{\text{dc}\prime} \ge = \text{a} \text{, b} \text{ c}\prime \tag{3}
$$

and therefore:

$$\begin{cases} \mathfrak{u}\_{\mathsf{sa}} + \mathfrak{u}\_{\mathsf{sb}} + \mathfrak{u}\_{\mathsf{sc}} = 0\\ \dot{\mathfrak{i}}\_{\mathsf{CA}} + \dot{\mathfrak{i}}\_{\mathsf{CB}} + \dot{\mathfrak{i}}\_{\mathsf{CC}} = 0 \end{cases} \tag{4}$$

By combining Equations (2)–(4), the difference between the point O potential and the point N potential is given by:

$$
\mu\_{\rm ON} = \frac{1}{6} (\mathcal{S}\_{\rm a} + \mathcal{S}\_{\rm b} + \mathcal{S}\_{\rm c}) \mathcal{U}\_{\rm dc} \tag{5}
$$

The three-level NPC APF output voltage and switching function then meet the following relationships:

$$\begin{cases} \boldsymbol{\mu\_{\rm AN}} = \boldsymbol{\mu\_{\rm AO}} + \boldsymbol{\mu\_{\rm ON}} = \frac{1}{6} (2\mathbf{S\_{a}} - \mathbf{S\_{b}} - \mathbf{S\_{c}}) \boldsymbol{\mathcal{U}\_{\rm dc}}\\ \boldsymbol{\mu\_{\rm BN}} = \boldsymbol{\mu\_{\rm BO}} + \boldsymbol{\mu\_{\rm ON}} = \frac{1}{6} (-\mathbf{S\_{a}} + 2\mathbf{S\_{b}} - \mathbf{S\_{c}}) \boldsymbol{\mathcal{U}\_{\rm dc}}\\ \boldsymbol{\mu\_{\rm CN}} = \boldsymbol{\mu\_{\rm CO}} + \boldsymbol{\mu\_{\rm ON}} = \frac{1}{6} (-\mathbf{S\_{a}} - \mathbf{S\_{b}} + 2\mathbf{S\_{c}}) \boldsymbol{\mathcal{U}\_{\rm dc}} \end{cases} \tag{6}$$

#### *2.3. Analysis of Neutral Point Potential of NPC APF*

Two main reasons exist for the capacitor voltage fluctuation: the various losses in APF system, including the loss of switch tube and line, as well as the load fluctuation and the power grid fluctuation. The load fluctuation and grid fluctuation belong to the external disturbance and cannot be controlled. Therefore, in order to suppress the capacitor voltage fluctuation, maintain the stability of the APF system and achieve a better tracking effect on the harmonic current, the relationship between the NPC topology output voltage vector and neutral point potential fluctuation is analyzed as follows.

As shown in Figure 3, there are 27 voltage vectors in NPC topology switching state vector, including 6 medium vectors, 6 large vectors, 12 small vectors, and 3 zero vectors. Among them, the medium vectors include: PNO(V1), PON(V3), OPN(V5), NPO(V7), NOP(V9), and ONP(V11). The large vector includes: PNN(V2), PPN(V4), NPN(V6), NPP(V8), NNP(V10), and PNP(V12). The small vectors includes: ONO(V13), POP(V14), ONN(V15), POO(V16), OON(V17), PPO(V18), NON(V19), OPO(V20), NOO(21), OPP(V22), NNO(V23), OOP(V24). Zero vectors include: NNN(V25), OOO(V26), and PPP(V27).

**Figure 3.** Voltage vector diagram of NPC three-level topology.

In order to analyze the influence of vectors on the neutral point potential, the equivalent circuits corresponding to these five vectors are analyzed, (cf. Figure 4).

It can be seen from Figure 4a, that the large vector (PNN) acts on the entire bus voltage and does not constitute a loop with the point O. The same applies for the other five large vectors. Therefore, when the large vector acts, it only affects the entire bus voltage on the DC side. When the output voltage vector is a medium vector, one phase is connected to point O, and the other phases are, respectively, connected to the bus voltage in order to form a loop with point O, and therefore affect its potential. However, this effect is uncontrollable. That is, the point O potential cannot be controlled by the medium vectors. The small vectors include positive and negative small vectors. It can be seen from Figure 4c,d that no matter which small vector acts, an electrical connection with point O which constitutes a circuit exists, so the small vectors will affect the neutral point potential balance. When the output state of the switch is a zero vector, it can be seen from Figure 4e that although the three bridge arms are connected to the point O, they do not form a current loop and do not affect the voltage balance. The other two zero vectors of the bridge arms are not connected to the point O, and will not affect the voltage balance. The influences of these four voltage vectors are summarized in Table 2.

**Table 2.** Influence of voltage vectors on neutral point potential.

**Figure 4.** Equivalent circuit diagram of different vectors: (**a**) large vector (PNN); (**b**) middle vector (PON); (**c**) small vector (ONN); (**d**) small vector (POO); (**e**) zero vector (NNN).

Assuming the neutral current is *io*, the load currents are *i*a, *i*b, and *i*c, the output direction of the inverter is positive direction, the corresponding relations among *i*o, the redundant small vectors, and load currents can be obtained, (cf. Table 3).

**Table 3.** Corresponding relationship between *i*o and redundant small vectors and output currents.

According to Table 3, the mathematical relationship between *i*o and the APF system output compensation current is expressed as:

$$i\_{\rm o} = -(i\_{\rm ca}|S\_{\bf a}| + i\_{\rm cb}|S\_{\bf b}| + i\_{\rm cc}|S\_{\bf c}|) \tag{7}$$

The relationship between *i*o and the DC side capacitance is given by:

$$\frac{\mathbf{d}(V\_{\rm dc1} - V\_{\rm dc2})}{\mathbf{d}t} = \frac{1}{\mathbf{C}} i\_0 \tag{8}$$

where: *V*dc1 and *V*dc2 are the voltage values of capacitors *C*1 and *C*2, respectively.

By setting the voltage deviation to *V*O = *V*dc1 − *V*dc2, according to Equations (7) and (8), the following is obtained:

$$\frac{d\mathbf{V\_{o}}}{dt} = -\frac{1}{\mathbf{C}} \Sigma \dot{\mathbf{n}}\_{\mathbf{x}\mathbf{x}} |\mathbf{S\_{x}}|\tag{9}$$

where: *x* = a, b, c.

In summary, the reason of NPC topology DC side neutral point potential fluctuations is that *i*o is not null. Regardless of the magnitude and direction of *i*o, as long as a current flow exists between the neutral point O and the load circuit, the current will affect the point O voltage. Under the action of different vectors, different currents have different effects on the capacitance voltage. However, only the small vectors really affect the capacitance voltage and can be controlled in the system. Therefore, the small vectors can be used to solve the problem of neutral point fluctuation.

#### **3. Model Predictive Control**

#### *3.1. Fundamental Theory*

Figure 5 presents the overall control structure block diagram of the three-level APF system, including the harmonic current detection unit and model predictive control unit. The harmonic current control unit uses the *i*p-*i*q harmonic current detection method in order to obtain the three-phase harmonic reference current *i* \* fa, *i* \* fb, and *i* \* fc. The model predictive control samples the compensation current, capacitor voltage, and grid voltage, and predicts the compensation current and reference current in the future. It also selects the optimal switching vector output combined with the current capacitor voltage error.

**Figure 5.** Overall control scheme of three-level APF system.

Due to the limited switching state of the main circuit, MPC predicts the output of each switching state using the prediction model. By calculating the function values of all the switching states, the switch state corresponding to the minimum function is selected and applied to the next cycle. The detailed process is as follows. The output prediction model *f*mpc of the system is first developed according to the switching state *S*sta of the APF and the system control variable *x*. The value function *f*val is then established. At time *tk*, the output *x*(*tk*) is calculated using the system prediction model *f*mpc in order to calculate the predicted output *x* mpc *i* (*tk*+1) corresponding to n different switching states. Afterwards, the value function of the n switching states can be calculated using the output value *x*ref(*tk*+1) and predicted output value *x* mpc *i* (*tk*+1). Finally, the optimal switching state *S*sta(*tk*) corresponding to the minimum function value is obtained, and the switching state is output. The diagram of the system is illustrated in Figure 6.

**Figure 6.** APF MPC block diagram.

#### *3.2. Traditional MPC*

Model predictive control (MPC) belongs to optimal control in essence. It can predict the future output information of the system according to the current and past sampling information of the system. The switching states of the converter are limited, for example, there are 27 switching states in NPC three-level topology. Therefore, the traditional model is also called finite control set model prediction.

The model predictive control consists of the predictive model, rolling optimization and feedback correction. The overall control block diagram is shown in Figure 7. Establishing a systematic prediction model is the first step of MPC, that is, building a prediction model of future information according to the previous and current information, and then rolling optimization. Through rolling optimization, the size of the value function corresponding to all the cases can be judged, and the switch state output corresponding to the minimum value function can be selected. In the process of rolling optimization, the initial positioning link of the current information to the optimization process includes a feedback correction. Therefore, an additional feedback correction link does not exist in practical applications.

**Figure 7.** Model predictive control block diagram.

In order to reduce the control complexity and improve the real-time performance, the Clarke transform is performed on the APF mathematical model of the traditional MPC in order to obtain the following:

$$\begin{cases} \boldsymbol{\mu}\_{\boldsymbol{a}} = \, \prescript{\boldsymbol{R}}{}{\mathrm{L}}\dot{\boldsymbol{i}}\_{\boldsymbol{a}} + \, \prescript{\mathrm{div}}{}{\mathrm{d}}\dot{\boldsymbol{i}}\_{\boldsymbol{\mathcal{A}}} + \prescript{\boldsymbol{e}}{}{\mathrm{e}}\_{\boldsymbol{a}} \\\ \boldsymbol{\mu}\_{\boldsymbol{\beta}} = \, \prescript{\mathrm{R}}{}{\mathrm{L}}\dot{\boldsymbol{i}}\_{\boldsymbol{\beta}} + \, \prescript{\mathrm{d}}{}{\mathrm{d}}\frac{\mathrm{d}\boldsymbol{i}\_{\boldsymbol{\beta}}}{\mathrm{d}\boldsymbol{\mathcal{I}}} + \prescript{\boldsymbol{e}}{}{\mathrm{e}}\_{\boldsymbol{\beta}} \end{cases} \tag{10}$$

$$\begin{array}{rcl} \text{where:} \begin{bmatrix} \boldsymbol{u}\_{\boldsymbol{a}} \\ \boldsymbol{u}\_{\boldsymbol{\beta}} \end{bmatrix} & = & \mathbf{C}\_{\text{abc}-a\boldsymbol{\beta}} \begin{bmatrix} \boldsymbol{u}\_{\text{AN}} \\ \boldsymbol{u}\_{\text{BN}} \\ \boldsymbol{u}\_{\text{CN}} \end{bmatrix}, \quad \begin{bmatrix} \boldsymbol{i}\_{\boldsymbol{a}} \\ \boldsymbol{i}\_{\boldsymbol{\beta}} \end{bmatrix} & = & \mathbf{C}\_{\text{abc}-a\boldsymbol{\beta}} \begin{bmatrix} \boldsymbol{i}\_{\text{CA}} \\ \boldsymbol{i}\_{\text{CB}} \end{bmatrix} \\\ \mathbf{C}\_{\text{\\_\text{\textdegree}}} \begin{bmatrix} \boldsymbol{e}\_{\text{R}} \\ \boldsymbol{e}\_{\boldsymbol{\beta}} \end{bmatrix} & = & \mathbf{C}\_{\text{abc}-a\boldsymbol{\beta}} \begin{bmatrix} \boldsymbol{u}\_{\text{S3}} \\ \boldsymbol{u}\_{\text{s}\text{B}} \end{bmatrix}, \quad \mathbf{C}\_{\text{abc}-a\boldsymbol{\beta}} = \frac{2}{3} \begin{bmatrix} 1 & -\frac{1}{2} & -\frac{1}{2} \\ 0 & \frac{\sqrt{3}}{2} & -\frac{\sqrt{3}}{2} \end{bmatrix}. \end{array}$$

By applying the Clarke transformation on the pair of Equation (6), the following is obtained:

$$
\begin{bmatrix} u\_{\mathsf{a}} \\ u\_{\mathsf{\beta}} \end{bmatrix} = \mathsf{C}\_{\mathsf{abc} - \mathsf{a}\mathcal{\beta}} \begin{bmatrix} u\_{\mathsf{AN}} \\ u\_{\mathsf{BN}} \\ u\_{\mathsf{CN}} \end{bmatrix} = \frac{1}{\mathsf{6}} \begin{bmatrix} 2\mathsf{S}\_{\mathsf{a}} - \mathsf{S}\_{\mathsf{b}} - \mathsf{S}\_{\mathsf{c}} \\ \sqrt{3}(\mathsf{S}\_{\mathsf{b}} - \mathsf{S}\_{\mathsf{c}}) \end{bmatrix} \mathsf{u}\_{\mathsf{dc}} \tag{11}
$$

Equation (10) is then discretized to obtain:

$$\frac{\mathrm{d}i\_a}{\mathrm{d}t} \approx \frac{i\_a(k+1) - i\_a(k)}{T\_s} \tag{12}$$

$$\frac{\mathrm{d}i\_{\beta}}{\mathrm{d}t} \approx \frac{i\_{\beta}(k+1) - i\_{\beta}(k)}{T\_{s}} \tag{13}$$

where: *iα*(*k*) and *iβ*(*k*) are the actual compensation currents of APF at time k, *iα*(*k* + 1) and *iβ*(*k* + 1) represents the predicted compensation currents at *k*+1 time, and *T*s represents the sampling period of the system.

Using Equations (10), (12), and (13), the following can be obtained:

$$\begin{cases} \begin{array}{l} i\_a(k+1) = \frac{T\_\theta}{L} \left[ u\_a(k) - e\_a(k) - R i\_a(k) \right] + i\_a(k) \\\ i\_\beta(k+1) = \frac{T\_\theta}{L} \left[ u\_\beta(k) - e\_\beta(k) - R i\_\beta(k) \right] + i\_\beta(k) \end{array} \tag{14}$$

where *uαβ*(*k*) is the APF output voltage at time *k*, and *eαβ*(*k*) is the APF grid voltage at time k. In order to maintain a good current tracking effect and take into account the balance

of medium electric potential, Equation (9) is discretized:

$$\frac{\mathrm{d}V\_0}{\mathrm{d}t} \approx \frac{V\_0(k+1) - V\_0(k)}{T\_s} \tag{15}$$

where: *V*o(*k* + 1) and *V*o(*k*) are the deviation prediction value and deviation sampling value of capacitor *C*1 and capacitor *C*2 at *k* + 1 time and *k* time, respectively.

Equation (16) can be obtained from Equations (9) and (15):

$$V\_o(k+1) = V\_o(k) - \frac{T\_s}{C} \Sigma i\_{\rm cr}(k) |S\_x(k)| / \left(\mathbf{x} = \; a, b, c\right) \tag{16}$$

According to the objective function of the NPC three-level APF system, the square error function is selected as the value function model:

$$g\_1 = \left| i\_a^\*(k+1) - i\_a(k+1) \right|^2 + \left| i\_\beta^\*(k+1) - i\_\beta(k+1) \right|^2 \tag{17}$$

Considering the current tracking effect as the objective function, while taking into account the balance of neutral point potential, the value function can be expressed as:

$$\mathcal{g}\_2 = \left| i\_a^\*(k+1) - i\_a(k+1) \right|^2 + \left| i\_\beta^\*(k+1) - i\_\beta(k+1) \right|^2 + \left| V\_\mathbf{o}(k+1) \right| \tag{18}$$

Considering the weights of *g*1 and *g*2, the final expression of the value function is given by:

$$g = \lambda\_1 |i\_a^\*(k+1) - i\_a(k+1)|^2 + \lambda\_1 \left| i\_\beta^\*(k+1) - i\_\beta(k+1) \right|^2 + \lambda\_2 |V\_0(k+1)| \tag{19}$$

where: *λ*1 and *λ*2 are weight coefficients.

The current prediction value given in Equation (19) can be obtained by Lagrange interpolation:

$$\dot{i}^\*(k+1) = \sum\_{l=0}^n (-1)^{n-1} \frac{(n+1)!}{l!(n+1-l)!} \dot{i}^\*(k+l-n) \tag{20}$$

For the sake of accuracy and computational complexity, *n* = 2 is selected, and then:

$$i\_x^\*(k+1) = \left. \mathfrak{H}\_x^\*(k) - \mathfrak{H}\_x^\*(k-1) + i\_x^\*(k-2) \right. \\ \left. \left. \left( \ge \ = \alpha, \beta \right) \right. \tag{21}$$

*3.3. Improved MPC*

3.3.1. Improved MPC Objective Function

The problem of setting the weight coefficient of the objective function can be solved by outputting the optimal small vector to equalize the DC side voltage, and omitting the DC side capacitor voltage error objective function in the cost function.

The realization of DC sides capacitor voltage stability is the premise of maintaining neutral points potential balances. The diagram of the DC sides capacitor voltage stabilizing control is illustrated in Figure 8. Where *e*a, *e*b, and *e*c are the grid voltage, *i*a, *i*b, and *i*c are the three-phase grid current. Firstly, the active current and reactive current components *i*p and *i*q in p-q coordinate system are obtained by Clarke transformation and Park transformation. Then, the fundamental component in the p-q coordinate system can be obtained by filtering the high-order harmonic component through the low-pass filter LPF. The difference between the DC side total voltage reference value and the DC side total voltage feedback can be processed by the PI controller to obtain the active power reference current Δ*i*p. The active current component Δ*i*p is superimposed with the active fundamental current component in the p-q coordinate system to obtain the final active fundamental current component. The three-phase fundamental current components *i*af, *i*bf, and *i*cf are obtained from the final active fundamental component and reactive fundamental component through the inverse transformation of Clarke and Park. Finally, by subtracting the three-phase fundamental current from the three-phase total current, the three-phase harmonic components *i*ah, *i*bh, and *i*ch can be obtained.

**Figure 8.** Schematic diagram of the overall voltage control.

The improved model predictive control algorithm can control the voltage of two capacitors on the DC side, by outputting a specific small vector. This method can omit the DC side capacitor voltage error value function, so as to solve the problem of setting the weight coefficient of the objective function. The specific form of the improved value function is given by:

$$\mathcal{g} = \left| i\_{a\beta}^\*(k+1) - i\_{a\beta}(k+1) \right| \tag{22}$$

Compared with the traditional model prediction value function, this function only needs to consider an objective function of current tracking error, which reduces the computational load and does not introduce a weight coefficient. Therefore, there is no problem of weight coefficient setting.

3.3.2. Single Objective Function Improved Model Predictive Control Strategy Based on Sector Judgment

Inspired by the three-level SVPWM vector control, the sector judgment is introduced into the model predictive control. Figure 9 presents the three-level NPC voltage vector diagram.

It can be seen that the linear *Vβ* + √3/3 *Vα* = 0,*Vβ* − √3/3 *Vα* = 0 and *β* coordinate axes divide the large hexagon into six regions, quadrilateral areas of I, II, III, IV, V, and VI, while each quadrilateral contains 8 vectors. It is first assumed that the projection of the reference voltage vector *V*ref on the *α* and *β* axes is *Vα* and *Vβ*. The six quadrangles are divided according to three lines and voltage vector *V*ref. Specific regional divisions are shown in Table 4.

**Table 4.** Regional divisions.

The quadrilateral region of the reference voltage vector can be determined by assessing the mathematical relationship of the projection of the reference voltage vector on the *α* and *β* axes. Therefore, the mathematical model of the reference voltage is developed:

$$\begin{cases} \boldsymbol{\mu}\_{a}(k) = \boldsymbol{e}\_{a}(k) + \mathrm{Ri}\_{a}(k) - \frac{\boldsymbol{I}\_{\mathcal{P}}}{\boldsymbol{T}\_{\mathcal{P}}} [\boldsymbol{i}\_{a}(k+1) - \boldsymbol{i}\_{a}(k)] \\\ \boldsymbol{\mu}\_{\beta}(k) = \boldsymbol{e}\_{\beta}(k) + \mathrm{Ri}\_{\beta}(k) - \frac{\boldsymbol{I}\_{\mathcal{P}}}{\boldsymbol{T}\_{\ast}} [\boldsymbol{i}\_{\beta}(k+1) - \boldsymbol{i}\_{\beta}(k)] \end{cases} \tag{23}$$

In order to achieve a better current tracking effect of the system, it is necessary to predict that the output current is equal to the predicted harmonic given current:

$$i\_{a\beta}^{\*}\left(k+1\right) = i\_{a\beta}\left(k+1\right) \tag{24}$$

By simultaneously using Equations (23) and (24), the following can be obtained:

$$\begin{cases} \boldsymbol{\mu}\_{a}(k) = \boldsymbol{\varepsilon}\_{a}(k) + \mathrm{Ri}\_{a}(k) - \mathop{\rm l\!}\_{\Gamma\_{\mathsf{s}}} [i\_{a}^{\ast}(k+1) - i\_{a}(k)]\\ \boldsymbol{\mu}\_{\boldsymbol{\beta}}(k) = \boldsymbol{\varepsilon}\_{\boldsymbol{\beta}}(k) + \mathrm{Ri}\_{\boldsymbol{\beta}}(k) - \mathop{\rm l\!}\_{\Gamma\_{\mathsf{s}}} [i\_{\boldsymbol{\beta}}^{\ast}(k+1) - i\_{\boldsymbol{\beta}}(k)] \end{cases} \tag{25}$$

where: *uα* = *Vα* and *uβ* = *Vβ*.

After this evaluation, the region of the reference voltage vector can be determined. In addition, 8 vectors exist in each region, and there are 2 small vectors among the 8 vectors. Consequently, a redundant vector can be removed. Therefore, the proposed model predictive control algorithm has only 7 rolling optimized vectors, which greatly reduces the rolling times and system calculation, compared with the traditional prediction model.

#### 3.3.3. Flow and Analysis of Improved Model Predictive Control

The control flowchart is shown in Figure 10. Based on the traditional model predictive control, firstly, each parameter is sampled, the system parameters are initialized, *uα* and *uβ* are calculated, the position of the reference voltage vector is then judged according to the size of *uα* and *uβ*, and, finally, its quadrilateral region is determined. Afterwards, the seven voltage vectors in this area are subject to rolling optimization. The compensation current is predicted and the value functions containing only current tracking error, are calculated. After seven rolling optimizations, the switching state corresponding to the value function that minimizes the current tracking error is output. Finally, the output voltage vector is judged. In the case of a small vector, a small vector output that is conducive to the capacitor voltage balance on the DC side is selected. Otherwise, it is directly output. Consequently, the optimal switching state output of single objective function improved model predictive control based on sector judgment is completed.

**Figure 10.** Flow chart of single objective function improved model predictive control based on sector judgment.

#### **4. System Simulation and Result Analysis**

The feasibility and efficiency of the proposed algorithm are verified by developing the simulation model of the NPC three-level APF. The model predictive control is written using the S-function module of MATLAB/Simulink. The two model predictions are simulated and compared. Table 5 presents the system simulation parameters.

**Table 5.** Specific parameters of APF simulation model.

#### *4.1. Simulation and Analysis of Traditional Model Predictive Control*

Figure 11 shows the current waveform of A-phase power grid before compensation. It can be seen that when APF is not working, the current waveform is saddle shaped and the waveform distortion is serious because it contains a large number of high-order harmonics. Figure 12 shows the FFT analysis diagram of A-phase grid current before compensation. It can be seen that THD is 27.08%, which is much higher than the national standard of 5%, which seriously reduces the power quality of the grid.

**Figure 11.** Current waveform of A-phase power grid before compensation.

**Figure 12.** FFT analysis diagram of A-phase current before compensation.

Figures 13 and 14 present the current waveform and THD diagram of A-phase power grid under the traditional model predictive control algorithm after APF system works. Compared with Figure 10, it can be seen that the current waveform after compensation changes from saddle shape to sinusoidal shape, and the sinusoidal degree is high. Its THD is 4.51% and less than 5%, which meets the national standard and realizes harmonic compensation.

**Figure 13.** A-phase current waveform after compensation of traditional model predictive control.

**Figure 14.** A-phase current THD diagram after compensation of traditional model predictive control.

Figure 15 is the reference current tracking effect diagram under traditional model predictive control. Under the traditional model predictive control, the feedback current can better track the reference current, but there are some deviations in the peak and trough. Figure 16 presents the error diagram of reference current and feedback current, the error range fluctuates within ±2.5 A, and the maximum error occurs at the peak and trough positions.

**Figure 15.** Reference current tracking effect diagram of traditional model predictive control.

**Figure 16.** Error diagram of reference current and feedback current of traditional model predictive control.

Figure 17 presents the overall voltage waveform of the capacitor at the DC side, and its voltage amplitude fluctuates around 801 V, which can maintain stable fluctuation. Figure 18 presents the waveform of neutral point potential at DC side, with a fluctuation range of ±1.4 V and stable.

**Figure 17.** Overall voltage waveform of DC side capacitor of traditional model predictive control.

**Figure 18.** DC neutral point potential waveform of traditional model predictive control.

In order to observe the MPC the selection of switching state vector, the switching state flag is set to observe the process of finding the optimal switching vector during rolling optimization. Figure 19 is a value diagram of the switching states flag of the traditional model predictive control algorithm. The value of flag is between 1 and 27, which verifies that the rolling optimization times of the traditional model predictive control algorithm is 27.

**Figure 19.** Switching state flag value diagram of traditional model predictive control.

#### *4.2. Single Objective Function Improved Model Predictive Control Based on Sector Judgment*

On the basis of keeping the previously mentioned simulation parameters unchanged, this section uses the single objective function improved model predictive control algorithm based on sector judgment to simulate the APF system.