**1. Introduction**

208 VLSI Design

This work was partially supported by R.O.C National Science Council under Grant NSC99-

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Boliolo, A.; Benini, L.; de Micheli, G. & Ricco, B.(1997). Gate-level power and current

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simulation of CMOS integrated circuits. *IEEE Trans. Very Large Scale Integr.(VLSI)*

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level with standard library information. *Proceedings of IEEE Intl. Symp. Circuits and*

decoupling capacitors. *IEEE Trans. Very Large Scale Integr.(VLSI) Syst.*, vol. 16, no. 7

analysis with gate level simulator. *Proceedings of IEEE Int. Symp. Quality Electronic*

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**7. Acknowledgment**

1063-8210

59593-999-9

Synopsys

**8. References**

2221-E-008-104. Their support are greatly appreciated.

233-240, ISSN: 1751-858X

The design and analysis of a power distribution network is one of the most important areas in high-speed digital systems. The main function of a power distribution network is to supply power to core logic and I/O circuits in any digital system. With increasing clock speeds accompanied by decreasing signal rise times and supply voltages, the transient currents injected into the power distribution planes can induce voltage fluctuations on the power distribution network (Tummala et al., 1997). This undesired voltage fluctuation on the power/ground planes is commonly known as switching noise or delta-I noise. Power supply noise leads to unwanted effects on the power distribution network (PDN) such as ground bounce, power supply compression, and electromagnetic interference. The digital switching noise propagates through the substrate and power distribution networks to analog circuits, degrading their performance in system-on-chip (SoC) applications (Iogra, 2007). The modern advances in process technology along with tremendous increase in number of on-chip devices make the design of on-chip power distribution network a major design challenge. Increased switching activity of high speed devices therefore causes large current derivatives or current transients. These current transients may cause unwanted potential drops in supply voltage due to parasitic resistance and inductance of power distribution network. Over and above, scaling of the supply voltage may cause a large degradation in the signal-to-noise ratio of high speed CMOS circuits (Bai & Hajj, 2002). When on-chip logic cells switch, either they draw current from supply network or inject current into the ground network. If a lot of logic cells switch simultaneously, then they may cause voltage variations within the supply network due to parasitic associated with the power distribution network. This voltage variation is nothing but core switching noise. It is called the voltage surge if variation is above the nominal voltage and is called the sag if variation is below the nominal supply voltage (Bobba & Hajj, 2002). This variation in supply voltage may cause logic errors thereby adversely affecting the circuit performance (Bai & Hajj, 2002). Excessive drop in power bus voltage or surge in ground bus voltage can cause following problems: decrease in the device drive capability, increase in the logic gate delay, and reduction of the noise margin. Hence, it is important to estimate these voltage variations in the power distribution network (Bai & Hajj, 2002). Simultaneous switching noise is mainly caused by the parasitic inductance associated with the power distribution network at high frequency. The power supply level goes down at different nodes in a PDN because of

devices.

(Sapatnekar, 2009).

nodes:

Switching Noise in 3D Power Distribution Networks: An Overview 211

switching noise is substrate noise which may modulate the threshold voltage of MOS

Three-Dimensional (3D) integration is a key enabling technology in today's high speed digital design. The purpose of 3D integration is either to partition a single chip into multiple strata to reduce on-chip global interconnects length (Joyner, 2004) or stacking of chips together through TSVs. By increasing the number of strata from one to four reduces the length of the longest interconnect by 50% with 75% improvement in latency and 50% improvement in interconnect energy dissipation (Meindl, 2002). Using 3D integration the wire-limited clock frequency can be increased by 3.9x and wire-limited area and power can be reduced by 84% (Miendl, 2003) and 51% (Khan et al., 2011) respectively. The power delivery to a 3D stack of high power chips also presents many challenges and requires careful and appropriate resource allocation at the package level, die level, and interstratal interconnect level (Huang et al., 2007). Three-Dimensional (3D) integration provides the potential for tremendously increased level of integration per unit footprint as compared to its 2D counterpart (Xie et al., 2010). While the third dimension introduced this way is attractive for many applications but puts some stringent requirements and bottlenecks on 3D power delivery. The huge current requirements per package pin for 3D integration lead to significant complications in reliable power delivery. A k-tier 3D chip could use k times as much current as a single 2D chip of the same footprint under similar packaging technology (Xie et al., 2010). Through silicon vias used in 3D integration introduce extra resistance and inductance in the power distribution path. The power distribution network impedance has not been kept up with the scaling of technology node due limited wire resources, increased device density and current demands (Xie et al., 2010) and situation is further worsened by 3D integration. The increased IR and Ldi/dt supply noise in 3D chips may cause a larger variation in operating speed leading to more timing violations (Xie et al., 2010). The supply noise overshoot due to inductive parasitic may aggravate reliability issues such as oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI)

Three-Dimensional (3D) integration increases integration density by increasing number of on-chip devices per unit footprint which has following effects with the scaling of technology

Each power distribution TSV pair has to supply a logic load with decoupling capacitance. In order to increase the switching speed, the time constant RC needs to be reduced which means to reduce TSV resistance which is difficult with the scaling of technology node. Even if the instantaneous voltage fluctuation is very small, the periodic nature of digital circuits can cause resonance (Larsson, 1998). The resonance frequency due to effective TSV

1

*TSV dec*

2 *r eff*

π*L C*

*f*

=

• Increase in inductance per unit foot print at high frequency of the order of GHz. • Consequent rise in switching noise imposed on 3D power distribution network.

• Tremendous increase in current per unit foot print.

inductance and decoupling capacitance is given as follows

• Increase in power per unit foot print.

the inductive voltage drop at high frequency. This is because of the simultaneous switching of on-chip logic load as well as drivers connected to the output pins of a chip. The glitch in voltage caused this way is proportional to the number of circuit components switching at a clock edge, the steepness of the clock edge and effective inductance of the power distribution network at this moment. On-chip core switching noise as well as the noise caused by switching of the external drivers is equally important at high operating frequencies of the order of GHz. Scaling down of the technology node shrinks the minimum feature size which in turn increases average capacitive load offered by on-chip core logic. Therefore average charging and discharging currents for on-chip logic load increase. The increased circuit speed also raises di/dt. Therefore, on-chip currents may fluctuate by large amounts within short interval of times. Hence voltage fluctuations caused by switching of on-chip logic load known as core switching noise is very significant and important under these circumstance.

On-chip power distribution noise has become a determining factor in performance and reliability where the core voltage has dramatically dropped to 0.9V for 40nm technology node (Shishuang et al., 2010) and the trend continuous. At the same time jitter tolerance and timing margins are shrinking due to ever increasing clock frequency (Shishuang et al., 2010). The chip-package PDN should therefore be optimized at early design stages to meet I/O jitter specifications and core logic timing closure (Bai & Hajj, 2002). For the IC designers and the signal integrity engineers, the most important issue is to understand how the on-chip transient current load interacts with the entire PDN system, and how the on-chip PDN noise affects the circuit performance (Shishuang et al., 2010). The experimental results in (Shishuang et al., 2010) show that on-chip PDN noise may be much higher even if PCB level PDN noise is well under control.

On-chip noise margins decrease proportionally with the power supply with the scaling of the technology nodes (Coenen & Roermund, 2010). Generally the voltage fluctuation should be kept within 5-10% of the supply voltage in VLSI design (Dennis et al., 2008). When supply voltage is less than the nominal value in synchronous digital circuits, it causes timing violations in a register during a clock period (Dennis et al., 2008). This timing error caused by power supply noise may become permanent when stored in a register (Dennis et al., 2008). Core switching noise has been neglected in past due to higher package inductance as compared to on-chip inductance of the power distribution network. Therefore, switching noise was considered to be inductive voltage noise caused by fast switching I/O drivers (Bathy, 1996; Kabbani & Al-Khalili, 1999; Senthinathan & Prince, 1991; Vaidyanath, 1994;Yang & Brews, 1996). On the other hand today several folds increase in clock frequency as compared to I/O speed accompanied with higher integration densities and scaling of onchip interconnects has made the core switching noise more critical than ever (Zheng & Tenhunnen, 2001). The supply-noise becomes more problematic when microprocessors share the same substrate as the analogue circuits like PLL (Stark et al., 2008) (Vonkaenel, 2002). Therefore core switching noise may cause jitter in clock frequency thereby reducing the usable cycle time and consequently causing critical path failure in the processor. If core switching noise is extended over several clock cycles, then jitter accumulation will take place thereby causing deviation of each subsequent clock edge more and more from the ideal location (Larsson, 2002). The noise accumulation therefore causes synchronization failure between different clock domains more than the critical path failure. The other side effect of

the inductive voltage drop at high frequency. This is because of the simultaneous switching of on-chip logic load as well as drivers connected to the output pins of a chip. The glitch in voltage caused this way is proportional to the number of circuit components switching at a clock edge, the steepness of the clock edge and effective inductance of the power distribution network at this moment. On-chip core switching noise as well as the noise caused by switching of the external drivers is equally important at high operating frequencies of the order of GHz. Scaling down of the technology node shrinks the minimum feature size which in turn increases average capacitive load offered by on-chip core logic. Therefore average charging and discharging currents for on-chip logic load increase. The increased circuit speed also raises di/dt. Therefore, on-chip currents may fluctuate by large amounts within short interval of times. Hence voltage fluctuations caused by switching of on-chip logic load known as core switching noise is very significant and important under

On-chip power distribution noise has become a determining factor in performance and reliability where the core voltage has dramatically dropped to 0.9V for 40nm technology node (Shishuang et al., 2010) and the trend continuous. At the same time jitter tolerance and timing margins are shrinking due to ever increasing clock frequency (Shishuang et al., 2010). The chip-package PDN should therefore be optimized at early design stages to meet I/O jitter specifications and core logic timing closure (Bai & Hajj, 2002). For the IC designers and the signal integrity engineers, the most important issue is to understand how the on-chip transient current load interacts with the entire PDN system, and how the on-chip PDN noise affects the circuit performance (Shishuang et al., 2010). The experimental results in (Shishuang et al., 2010) show that on-chip PDN noise may be much higher even if PCB level

On-chip noise margins decrease proportionally with the power supply with the scaling of the technology nodes (Coenen & Roermund, 2010). Generally the voltage fluctuation should be kept within 5-10% of the supply voltage in VLSI design (Dennis et al., 2008). When supply voltage is less than the nominal value in synchronous digital circuits, it causes timing violations in a register during a clock period (Dennis et al., 2008). This timing error caused by power supply noise may become permanent when stored in a register (Dennis et al., 2008). Core switching noise has been neglected in past due to higher package inductance as compared to on-chip inductance of the power distribution network. Therefore, switching noise was considered to be inductive voltage noise caused by fast switching I/O drivers (Bathy, 1996; Kabbani & Al-Khalili, 1999; Senthinathan & Prince, 1991; Vaidyanath, 1994;Yang & Brews, 1996). On the other hand today several folds increase in clock frequency as compared to I/O speed accompanied with higher integration densities and scaling of onchip interconnects has made the core switching noise more critical than ever (Zheng & Tenhunnen, 2001). The supply-noise becomes more problematic when microprocessors share the same substrate as the analogue circuits like PLL (Stark et al., 2008) (Vonkaenel, 2002). Therefore core switching noise may cause jitter in clock frequency thereby reducing the usable cycle time and consequently causing critical path failure in the processor. If core switching noise is extended over several clock cycles, then jitter accumulation will take place thereby causing deviation of each subsequent clock edge more and more from the ideal location (Larsson, 2002). The noise accumulation therefore causes synchronization failure between different clock domains more than the critical path failure. The other side effect of

these circumstance.

PDN noise is well under control.

switching noise is substrate noise which may modulate the threshold voltage of MOS devices.

Three-Dimensional (3D) integration is a key enabling technology in today's high speed digital design. The purpose of 3D integration is either to partition a single chip into multiple strata to reduce on-chip global interconnects length (Joyner, 2004) or stacking of chips together through TSVs. By increasing the number of strata from one to four reduces the length of the longest interconnect by 50% with 75% improvement in latency and 50% improvement in interconnect energy dissipation (Meindl, 2002). Using 3D integration the wire-limited clock frequency can be increased by 3.9x and wire-limited area and power can be reduced by 84% (Miendl, 2003) and 51% (Khan et al., 2011) respectively. The power delivery to a 3D stack of high power chips also presents many challenges and requires careful and appropriate resource allocation at the package level, die level, and interstratal interconnect level (Huang et al., 2007). Three-Dimensional (3D) integration provides the potential for tremendously increased level of integration per unit footprint as compared to its 2D counterpart (Xie et al., 2010). While the third dimension introduced this way is attractive for many applications but puts some stringent requirements and bottlenecks on 3D power delivery. The huge current requirements per package pin for 3D integration lead to significant complications in reliable power delivery. A k-tier 3D chip could use k times as much current as a single 2D chip of the same footprint under similar packaging technology (Xie et al., 2010). Through silicon vias used in 3D integration introduce extra resistance and inductance in the power distribution path. The power distribution network impedance has not been kept up with the scaling of technology node due limited wire resources, increased device density and current demands (Xie et al., 2010) and situation is further worsened by 3D integration. The increased IR and Ldi/dt supply noise in 3D chips may cause a larger variation in operating speed leading to more timing violations (Xie et al., 2010). The supply noise overshoot due to inductive parasitic may aggravate reliability issues such as oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI) (Sapatnekar, 2009).

Three-Dimensional (3D) integration increases integration density by increasing number of on-chip devices per unit footprint which has following effects with the scaling of technology nodes:

Each power distribution TSV pair has to supply a logic load with decoupling capacitance. In order to increase the switching speed, the time constant RC needs to be reduced which means to reduce TSV resistance which is difficult with the scaling of technology node. Even if the instantaneous voltage fluctuation is very small, the periodic nature of digital circuits can cause resonance (Larsson, 1998). The resonance frequency due to effective TSV inductance and decoupling capacitance is given as follows

$$f\_r = \frac{1}{2\pi\sqrt{L\_{ISV}^{eff}C\_{dec}}}$$

Switching Noise in 3D Power Distribution Networks: An Overview 213

power distribution network depends on the parasitic inductance of the current path between the driver and the output load, the maximum current demand of the load, and the

Fig. 2. (a) Configuration of three stacked chip-PDN connected by a multi-P/G TSV. (b) Simulated PDN impedances of a single chip-PDN (dotted line) and three stacked chip-PDN (solid and dashed lines) by the proposed separated P/G TSVand chip-PDN models. The

The impedance peaks for the power distribution network of a three-dimensional (3D) stack of chips as compared to a two-dimensional (2D) chip is shown by Figure 2 (Pak et al., 2011). The impedance peaks are in GHz range and are created due to faster switching on the power distribution network. A huge amount of decoupling capacitance is required to suppress these peaks for a three-dimensional (3D) power distribution network (Pak et al., 2011). The impedance peaks are mainly generated due to TSV inductance at high frequency.

• Circuit reliability degradation like decrease in the signal to noise ratio or increase in the

Figure is taken from (Pak et al., 2011).

• Reduction of the voltage margins.

• Failure of the logic.

noise sensitivity.

Simultaneous switching noise causes the following problems:

• Noise coupling to sensitive circuits like RF and analogue circuits.

clock frequency.

In order to prevent oscillations through a TSV pair the resonance frequency should be higher or lower than the system clock frequency. The effective resistance of TSV produces IR-drop, whereas reduces the resonance oscillations by providing damping. If simultaneous switching noise is dominant, the decrease in TSV effective resistance may increase the total noise in a 3D power distribution network.

A three-dimensional (3D) stack of logic dies interconnected through TSVs has to connect the core logic circuits, IO circuits, and rest of the circuits from three-dimensional (3D) stack to the printed circuit board. Therefore, both the simultaneous switching noise and the core switching noise depend on high-speed switching currents through power distribution network in three-dimensional (3D) stack of dies, location and number of power distribution TSV pairs, vias and routing of various serial and parallel signal interfaces on signal layers of the package. The signal distribution TSV pairs share the IO power distribution environment. Three-dimensional (3D) power distribution network parasitic significantly account for core noise, significantly influence the simultaneous switching noise, crosstalk, signal propagation delay and skew between signal distribution TSVs. The transient currents drawn by core logic produce voltage droops across outputs of the core power distribution network thereby degrading the operating frequency performance of the microprocessor. Similar voltage droops are produced across IO power distribution network as a result of total transient current pulled through IO drivers and buffers. These droops weaken the signal driving capability of IO drivers thereby causing signal integrity issues.

#### **2. Simultaneous switching in 3D power distribution network**

On-chip simultaneous switching noise is caused by switching of the output buffers or drivers as shown by Figure 1. These drivers have to drive the off chip load. The noise on

Fig. 1. Simultaneous Switching of Output Drivers

In order to prevent oscillations through a TSV pair the resonance frequency should be higher or lower than the system clock frequency. The effective resistance of TSV produces IR-drop, whereas reduces the resonance oscillations by providing damping. If simultaneous switching noise is dominant, the decrease in TSV effective resistance may increase the total

A three-dimensional (3D) stack of logic dies interconnected through TSVs has to connect the core logic circuits, IO circuits, and rest of the circuits from three-dimensional (3D) stack to the printed circuit board. Therefore, both the simultaneous switching noise and the core switching noise depend on high-speed switching currents through power distribution network in three-dimensional (3D) stack of dies, location and number of power distribution TSV pairs, vias and routing of various serial and parallel signal interfaces on signal layers of the package. The signal distribution TSV pairs share the IO power distribution environment. Three-dimensional (3D) power distribution network parasitic significantly account for core noise, significantly influence the simultaneous switching noise, crosstalk, signal propagation delay and skew between signal distribution TSVs. The transient currents drawn by core logic produce voltage droops across outputs of the core power distribution network thereby degrading the operating frequency performance of the microprocessor. Similar voltage droops are produced across IO power distribution network as a result of total transient current pulled through IO drivers and buffers. These droops weaken the signal driving

On-chip simultaneous switching noise is caused by switching of the output buffers or drivers as shown by Figure 1. These drivers have to drive the off chip load. The noise on

I1 I2 In

Increase of maximum power (current)

Simultaneous Switching of Output Buffers Parasitic Inductance

**1 2 n**

H

L

L

L

V=Vdd + V

I= I1+ I2+....+ In

noise in a 3D power distribution network.

capability of IO drivers thereby causing signal integrity issues.

Fig. 1. Simultaneous Switching of Output Drivers

H

L

Common Power Supply

t

I**V=L**

Common Ground

H

L

**2. Simultaneous switching in 3D power distribution network**

Increase of clock frequency

power distribution network depends on the parasitic inductance of the current path between the driver and the output load, the maximum current demand of the load, and the clock frequency.

Fig. 2. (a) Configuration of three stacked chip-PDN connected by a multi-P/G TSV. (b) Simulated PDN impedances of a single chip-PDN (dotted line) and three stacked chip-PDN (solid and dashed lines) by the proposed separated P/G TSVand chip-PDN models. The Figure is taken from (Pak et al., 2011).

The impedance peaks for the power distribution network of a three-dimensional (3D) stack of chips as compared to a two-dimensional (2D) chip is shown by Figure 2 (Pak et al., 2011). The impedance peaks are in GHz range and are created due to faster switching on the power distribution network. A huge amount of decoupling capacitance is required to suppress these peaks for a three-dimensional (3D) power distribution network (Pak et al., 2011). The impedance peaks are mainly generated due to TSV inductance at high frequency.

Simultaneous switching noise causes the following problems:

Switching Noise in 3D Power Distribution Networks: An Overview 215

noise overshoot due to inductive parasitic may aggravate reliability issues such as oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI) (Sapatnekar, 2009). The power delivery to a three-dimensional (3D) stack of high power chips also presents many challenges and requires careful and appropriate resource allocation at the package level, die level, and interstratal interconnect level (Huang et al., 2007). Any drop in the core supply voltage directly impacts the maximum operating frequency of the processor (Huang et al., 2007). Simultaneous switching noise originated from the internal logic circuitry has become a serious issue with the increase in speed and

The voltage variations due to core switching noise are spread out to the diverse nodes of the power distribution network, thereby causing severe performance degradations in the form of propagation delays (Andarde et al., 2007). The timing violation in a register is produced when value of the supply voltage is less than the nominal value in a synchronous digital circuit. Due to slow variation of the supply voltage as compared to the clock period the value of the supply voltage may remain same for all the gates in a combinational path. Therefore, the value of supply voltage may vary period to period causing severe reliability issues is the logic. The logic cells are prone to more delays with the voltage scaling whereas keeping the threshold voltage relatively constant (Ajami et al., 2003). The propagation delay of the gates increases by 10% with 10% drop in the supply voltage for 180nm (Saleh et al., 2002), by 30% with 10% variation in the supply voltage for 130nm (Pant et al., 2004), and by 4% with 1% change in the supply voltage for 90nm technology node (Tirumuri et al., 2004).

The scaling of the threshold voltage with the scaling of the power supply voltage has reduced the noise margins, thereby making the CMOS circuits more vulnerable to the noise (Bobba & Hajj, 2002). The excessive drop in the power voltage or surge in the ground voltage may drop the noise margins of the circuits. Consequently, a circuit may erroneously latch up to a wrong value or switch at a wrong time if magnitude of the voltage surge/droop is greater than the noise margin of the circuit for a given clock edge (Pant et al., 2000). The problem is expected to grow for a three-dimensional (3D) stack of logic dies

The gates are becoming increasingly sensitive to the switching noise due to limited scaling of the threshold voltage as compared to the supply voltage scaling with each technology node (Junxia et al., 2009). The reduction in supply voltage not only reduces the noise immunity but also produces signal integrity as well as the performance and the reliability issues. The voltage spikes are droops produced in the power distribution network due to core switching because of the parasitic inductance and resistance associated with the power supply network. The excessive drop in power voltage or surge in the ground voltage, therefore, slows down the cell transition capability, thereby seriously compromising the cell driving capabilities. Consequently clock skews are produced as a result of violations in the

interconnected through TSVs, with the addition of each die in the vertical stack.

**3.1.3 Impairing driving capabilities of a gate**

density of the internal circuitry.

**3.1.1 Propagation delay**

**3.1.2 Logic errors**

setup and the hold times.

### **3. Core switching noise in 3D power distribution network**

Logic cells are connected between supply and ground TSVs for a three-dimensional (3D) power distribution network. Each logic cell has an equivalent capacitance as a load to the power distribution TSV pair. On-chip logic cells switch either low to high or high to low at different clock edges in a synchronous logic system. When on-chip logic cells switch, either they draw current from supply network or inject current into the ground network. If a lot of logic cells switch simultaneously, they may produce voltage variations within the supply network due to the parasitic associated with the power distribution network. This voltage variation is nothing but core switching noise. It is called voltage surge if variation is above the nominal voltage and is called the sag if variation is below the nominal supply voltage (Bobba & Hajj, 2002). The core switching noise depends on the on-chip power distribution network parasitic rather than the package parasitic because of the scaling of the interconnect in modern high speed ULSI design. In addition to that the core switching noise has become more on-chip centric as the package inductance is significantly less as compared to the onchip inductance at high frequency because of the introduction of BGAs and TSVs in modern packaging. The core switching noise is a major part of the total simultaneous switching noise as the current drawn by the core logic load is generally much higher than the I/O driver's current (Radhakrishnan et al., 2007). The core switching noise in a threedimensional (3D) stack of logic dies interconnected through TSVs is more significant as compared to 2D ICs due to extra parasitic introduced through vertical TSVs. A large switching noise is introduced in a three-dimensional (3D) power distribution network if various stacked dies switch simultaneously (Huang et al., 2007). The number of power distributions TSVs for a three-dimensional (3D) stack of dies is basically limited by the footprint of the die (Jain et al., 2008) and on top of that the power supply noise is further worsened with the addition of dies in vertical stack due to additional parasitic involved in the power distribution paths through TSVs. The core switching noise can be a critical issue in a system like three-dimensional (3D) multi-processor system-on-chip (3D MOPSoC) (Tao et al., 2010). The core switching noise may introduce common mode noise in mixed analog and digital design as well as increase radiation at resonant frequencies. Overall power consumption in a three-dimensional (3D) stack reduces due to less interconnect, however, power density is increased in parts of three-dimensional (3D) stack due to increase in the number of transistors per unit volume as compared to two-dimensional (2D) counterpart.

#### **3.1 Effects of core switching noise**

While the third dimension is attractive for many applications but puts some stringent requirements and bottlenecks on three-dimensional (3D) power delivery. Huge current requirements per package pin for three-dimensional (3D) integration lead to significant complications in reliable power delivery. A k-tier three-dimensional (3D) chip could use k times as much current as a single two-dimensional (2D) chip of the same footprint under similar packaging technology (Xie et al., 2010). Through-silicon-vias used in threedimensional (3D) integration introduce extra resistance and inductance in the power distribution path. The power distribution network impedance has not been kept up with the scaling of the technology node due to limited wire resources, increased device density and current demands (Xie et al., 2010) and situation is further worsened by 3D integration. The increased IR and Ldi/dt supply noise in three-dimensional (3D) chips may cause a larger variation in operating speed leading to more timing violations (Xie et al., 2010). The supply noise overshoot due to inductive parasitic may aggravate reliability issues such as oxide breakdown, hot carrier injection (HCI), and negative bias temperature instability (NBTI) (Sapatnekar, 2009). The power delivery to a three-dimensional (3D) stack of high power chips also presents many challenges and requires careful and appropriate resource allocation at the package level, die level, and interstratal interconnect level (Huang et al., 2007). Any drop in the core supply voltage directly impacts the maximum operating frequency of the processor (Huang et al., 2007). Simultaneous switching noise originated from the internal logic circuitry has become a serious issue with the increase in speed and density of the internal circuitry.


**3.6 Flaky tail mouse denotes human AD**

12 Atopic Dermatitis – Disease Etiology and Clinical Management

Fig. 6. Amount of FITC in the skin of B6 and *Flgft* mice (left panel) and fluorescence

The skin abnormality associated with AD is well known to be a predisposing factor to sensitive skin (Farage, et al., 2006, Willis, et al., 2001) and allergic contact dermatitis (Clayton, et al., 2006, Mailhol, et al., 2009). However, children with atopic dermatitis had lower PPD induration size compared to healthy donors, but this was not statistically significant (Gruber, et al., 2001, Yilmaz, et al., 2000). In humans, sensitive skin is defined as reduced tolerance to cutaneous stimulation, with symptoms ranging from visible signs of irritation to subjective neurosensory discomfort (Farage, et al., 2006, Willis, et al., 2001). The question of whether human AD patients are more prone to allergic contact dermatitis than

Using phorbol myristate acetate (PMA) as an irritant, *Flgft* mice exhibited an enhanced ear swelling response compared to age-matched B6 mice throughout the experimental period (1 hr to 140 hrs). In addition, *Flgft* mice showed an increased skin-sensitized contact hypersensitivity (CHS) reaction to hapten, a form of classic Th1- and Tc1-mediated delayedtype hypersensitivity to haptens, emphasized by increased IFN-γ production, and terminated by regulatory T cells (Honda, et al., 2010, Mori, et al., 2008, Wang, et al., 2001). CHS is induced by epicutaneous sensitization and challenge. The ear thickness change was more prominent in *Flgft* mice than in B6 mice. In addition, the relative amount of IFN-γ in

To further assess the immune responses of *Flgft* mice, we elicited a delayed-type hypersensitivity (DTH) response through non-epicutaneous sensitization and challenge. Mice were immunized intraperitoneally with OVA, and challenged with a subcutaneous injection of OVA into the footpad. In contrast to the CHS response induced epicutaneously, the resulting footpad swelling in *Flgft* mice tended to be lower than that in wild-type mice. This finding is consistent with the observation on tuberculin tests in human. The levels of IFN-γ in the spleen were comparable between *Flgft* mice and wild-type mice. Thus, Th1/Tc1 immune responses were enhanced in *Flgft* mice only when the stimuli operated via the skin, suggesting that the enhanced immune responses seen in *Flgft* mice depend on skin barrier dysfunction and skin barrier function regulates cutaneous immune conditions, which hints

A reduced threshold in *Flgft* mice for contact dermatitis was also reported. These mice showed enhanced propensity to irritant contact dermatitis via low-dose phorbol ester TPA

intensities of FITC of the skin (right panel) after topical application.

**3.5 Altered immunobiology response in flaky tail mouse**

nonatopic individuals is still controversial (Mailhol, et al., 2009).

the ear of *Flgft* mice was higher than that of B6 mice.

at a possible mechanism involved in human AD.

Clinical studies have provided evidence that a house dust mite allergen plays a causative or exacerbating role in human AD (Kimura, et al., 1998), and that a strong correlation exists between *FLG* mutation patients and house dust mite-specific IgE (Henderson, et al., 2008). *Dermatophagoides pteronyssinus* (Dp) is a common mite aeroallergen, which is frequently involved in inducing human AD. Dp exhibits protease activities, and Der p1, Der p3, and Der p9, derived from Dp, are especially capable of activating the PAR-2 in human KC (Jeong, et al., 2008, Vasilopoulos, et al., 2007). A recent report has shown that activation of PAR-2 through Dp application significantly delays barrier recovery rate in barrier functionperturbed skin or otherwise compromised skin (Jeong, et al., 2008). Therefore, Dp may play a dual role in the onset of AD, both as an allergen and proteolytic signal and as a perturbation factor of the barrier function, leading to the persistence of eczematous skin lesions in AD (Jeong, et al., 2008, Roelandt, et al., 2008). It has also been reported that BALB/c and NC/Nga mice develop an allergic cutaneous immune response to mite antigens when they are applied to the skin after vigorous barrier disruption by means of tape-stripping or sodium dodecyl sulfate treatment (Kang, et al., 2006, Yamamoto, et al., 2007). Intriguingly, the application of Dp ointment to the skin without additional barrier disrupt induced dermatitis in *Flgft* mice, while this treatment did not induce any skin inflammation in control C57BL/6 mice (Fig.7). Petrolatum alone, used instead of Dp ointment as a control, induced no skin manifestation (Fig. 7).

Fig. 7. The mite-induced dermatitis model showed severe eczematous skin lesion after being topically treated with Dp ointment in *Flgft* mice, as well as ear thickness change.

Flaky Tail Mouse as a Novel Animal Model of Atopic Dermatitis:

clarify these relationships.

**5. References**

needs to be clarified in future studies.

25), 1225-1232

20, 4, (Apr), 351-356

*Med,* 206, 5, (May 11), 1135-1147

Possible Roles of Filaggrin in the Development of Atopic Dermatitis 15

Since *Flgft* mice are not a homogenous C57BL/6 background, two papers with spontaneous eczematous skin lesion on *Flgft* mice compared their outcomes with other mouse strains, such as C57BL6 and BALB/c mice as controls (Oyoshi, et al., 2009); these two strains lie on opposite ends of the spectrum of T helper responses. Nevertheless, the skin inflammation and susceptibility to EC sensitization of non-tape stripped skin observed in *Flgft* mice were not observed in other strains. In the second paper, they observed immune responses in mice of other genotypes, such as BALB/c and C3H, as controls, but both of these lines exhibited much less severe CHS responses compared to *Flgft* mice (Moniaga, et al., 2010). These data suggested that the enhanced responses seen in *Flgft* mice were not solely due to their genetic background. In addition, other studies used the *Flgft* mice which were backcrossed four generations to a B6 strain (a background coding sequence showed 99.3% identity between B6 and *Flgft)*, and similar enhanced

Furthermore, unlike human AD patients, most of whom are heterozygous for the *FLG* mutation, the heterozygous mice intercrossed with *Flgft* mice and B6 mice did not develop spontaneous dermatitis (Moniaga, et al., 2010). Similar results were obtained with the OVA-induced AD model, where homozygous, but not heterozygous (crossed with B6 mice) *Flgft* mice, showed enhanced susceptibility to cutaneous exposure to OVA (Fallon, et al., 2009). Not only human studies but also additional mouse studies will be required to

Since *Flgft* mice express a hair phenotype (matted), one cannot eliminate the possibility that some of the observations could have been influenced by the concurrent *ma* mutation (Scharschmidt, et al., 2009). Nevertheless, one study indeed removed the matted hair allele (*ma*) early in the course of backcrossing with B6 mice, and showed enhanced antigen (OVA) ingress in mice with the same *Flg* mutation, but no *ma* mutation in their background (Fallon, et al., 2009). The effect of the *ma* mutation in relation to the *Flg*  mutation in commercially available *Flgft* mice in the development of AD-like skin lesions

(1998). Worldwide variation in prevalence of symptoms of asthma, allergic

Aioi, A., et al. (2001). Impairment of skin barrier function in NC/Nga Tnd mice as a possible

Angelova-Fischer, I., et al. (2011). Distinct barrier integrity phenotypes in filaggrin-related

Ardern-Jones, M. R., et al. (2007). Bacterial superantigen facilitates epithelial presentation of allergen to T helper 2 cells. *Proc Natl Acad Sci U S A,* 104, 13, (Mar 27), 5557-5562

Briot, A., et al. (2009). Kallikrein 5 induces atopic dermatitis-like lesions through PAR2-

model for atopic dermatitis. *Br J Dermatol,* 144, 1, (Jan), 12-18

Bieber, T. (2008). Atopic dermatitis. *N Engl J Med,* 358, 14, (Apr 3), 1483-1494

rhinoconjunctivitis, and atopic eczema: ISAAC. The International Study of Asthma and Allergies in Childhood (ISAAC) Steering Committee. *Lancet,* 351, 9111, (Apr

atopic eczema following sequential tape stripping and lipid profiling. *Exp Dermatol,*

mediated thymic stromal lymphopoietin expression in Netherton syndrome. *J Exp*

responses to OVA-induced AD models were observed (Fallon, et al., 2009).

Histological examination of H&E-stained sections of involved *Flgft* skin after 16 applications showed acanthosis, elongation of rete ridges, and dense lymphocyte and neutrophil infiltration in the dermis, accompanied by an increased number of mast cells in the dermis. Consistently, scratching behavior, TEWL, and Dp-specific IgE levels were significantly higher in *Flgft* mice than in B6 mice (Fig.8) (Moniaga, et al., 2010). Thus the treatment of *Flgft* mice with Dp ointment, even without prior barrier disruption, remarkably enhanced both the clinical manifestations and the laboratory findings that correspond to indicators of human AD.

Fig. 8. TEWL and mite-specific serum IgE levels of *Flgft* mice and control mice after the last application.


*3.1. Membrane Stability*

Many studies have shown that resveratrol interacts with membrane lipids due to its lipophilicity. Resveratrol's localization in membranes or membrane models is a matter of debate.

In this study, we used a classic electrophysiological method to investigate resveratrol's microscopic incorporation at concentrations of 10 and 20 µM, in PLMs of different composition. Channel-like event formation indicates that molecules of a substance are incorporating into the membrane. PLMs of different composition were used to see whether resveratrol is able to incorporate into PLMs and to form conductive units, and under what experimental conditions. With this aim, POPC was used as a zwitterionic membrane, POPC:Ch as a neutral mixed membrane and DOPS:DOPE as a mixed membrane with diluted charges.

First of all, we tested PLM stability by applying a voltage of ±120 mV for 10–15 min under stirring and by monitoring the constant values for PLM conductance and capacitance. Preliminarily, to exclude any non-specific and destabilizing effects of DMSO per se on the PLMs used, we performed experiments by adding 4 or 8 µL of a H2O:DMSO (6:1) mixture to the medium, on the *cis* side of the membrane. In many different experiments and independently of lipid composition, the PLMs were stable even when applying a voltage of ±100 mV for 12 h under stirring and monitoring the constant values for PLM conductance and capacitance.


**4. ABCA1, Glucose Metabolism and Type 2 Diabetes**

β-cell failure and insulin resistance in muscle and liver represent the core pathophysiologic defects in type 2 diabetes [99]. Although ABCA1 and cholesterol homeostasis are critical in β-cell function and play a role in insulin resistance, global loss of ABCA1 function is not enough to cause type 2 diabetes (T2D). Diabetes is not a characteristic feature of Tangier disease and was not a feature reported in global *Abca1*−/<sup>−</sup> mice [100], although some consider diabetes as a complication of Tangier [101]. Moreover, while several patients suffering simultaneously from both diseases have been reported in the medical literature, particularly in the Japanese population [60,102–104], there are no reports on whether the prevalence of T2D is higher in Tangier patients. Still, several lines of evidence including tissue-specific *Abca1* KO models, human gene variation and ABCA1 expression studies point to a strong role of cholesterol homeostasis and ABCA1 in β-cell organization, function, and survival. Additionally, studies in muscle cell, hepatocyte and adipocyte-specific KO models, and some studies in humans, have shown ABCA1 also plays a role in peripheral insulin resistance. Altogether, this suggests that ABCA1 function is one of many factors which, acting in concert, contribute to the etiology of T2D.


**The Impact of Salt Tectonics on the Thermal Evolution and the Petroleum System of Confined Rift Basins: Insights from Basin Modeling of the Nordkapp Basin, Norwegian Barents Sea**

### **Andrés Cedeño \*, Luis Alberto Rojo, Néstor Cardozo, Luis Centeno and Alejandro Escalona**

Department of Energy Resources, University of Stavanger, 4036 Stavanger, Norway<EMAIL_ADDRESS>
Received: 27 May 2019; Accepted: 15 July 2019; Published: 17 July 2019

**Abstract:** Although the thermal e ffect of large salt tongues and allochthonous salt sheets in passive margins is described in the literature, little is known about the thermal e ffect of salt structures in confined rift basins where sub-vertical, closely spaced salt diapirs may a ffect the thermal evolution and petroleum system of the basin. In this study, we combine 2D structural restorations with thermal modeling to investigate the dynamic history of salt movement and its thermal e ffect in the Nordkapp Basin, a confined salt-bearing basin in the Norwegian Barents Sea. Two sections, one across the central sub-basin and another across the eastern sub-basin, are modeled. The central sub-basin shows deeply rooted, narrow and closely spaced diapirs, while the eastern sub-basin contains a shallower rooted, wide, isolated diapir. Variations through time in stratigraphy (source rocks), structures (salt diapirs and minibasins), and thermal boundary conditions (basal heat flow and sediment-water interface temperatures) are considered in the model. Present-day bottom hole temperatures and vitrinite data provide validation of the model. The modeling results in the eastern sub-basin show a strong but laterally limited thermal anomaly associated with the massive diapir, where temperatures in the diapir are 70 ◦C cooler than in the adjacent minibasins. In the central sub-basin, the thermal anomalies of closely-spaced diapirs mutually interfere and induce a combined anomaly that reduces the temperature in the minibasins by up to 50 ◦C with respect to the platform areas. Consequently, source rock maturation in the areas thermally a ffected by the diapirs is retarded, and the hydrocarbon generation window is expanded. Although subject to uncertainties in the model input parameters, these results demonstrate new exploration concepts (e.g., deep hydrocarbon kitchens) that are important for evaluating the prospectivity of the Nordkapp Basin and similar basins around the world.

**Keywords:** salt; thermal modeling; basin modeling; source rock maturation; petroleum system


**1. Introduction**

Gout is a common and treatable form of inflammatory arthritis resulting from the chronic deposition of monosodium urate crystals, which form in the presence ofincreased urate concentrations [1]. Recent studies have reported that incidence and prevalence rates of gout are rapidly increasing in many countries due to various factors, such as change of dietary habits and comorbid conditions [2,3]. Previous studies have also reported that gout is associated with a number of comorbidities, including cardiovascular disease (CVD), type II diabetes, obesity, dyslipidemia, chronic kidney disease (CKD), nonalcoholic fatty liver disease, and metabolic syndrome [4]. These comorbidities play an important role in determining the medication for treatment options in patients with gout.

Early episodes of acute gouty attack resolve spontaneously within several days or weeks, but repeated acute flares can lead to chronic arthritis with the formation of tophi and joint damage, which contribute to disability and decreased quality of life. Therefore, uric acid-lowering therapy (ULT) as well as prophylaxis of acute attack is one of the treatment goals of gout [5]. A recent guideline for gout management has recommended that when initiating ULT, prophylactic treatment with anti-inflammatory drugs for at least 6 months reduces the frequency of gout flares [6].

Colchicine is a systemic anti-inflammatory agent, and has been regarded as a first line prophylactic drug to prevent gout flare. However, it also has many side effects, such as gastrointestinal symptoms (including diarrhea), muscle pain or weakness, drug-to-drug interactions, renal impairment, and abnormal liver function tests [7]. Therefore, before colchicine treatment, it is necessary to consider the underlying diseases and concomitant medications.

A previous study has shown that colchicine is associated with a risk of hepatotoxicity in gout patients prescribed febuxostat [8], which has also been reported to induce acute liver injury [9]. However, there are few studies regarding hepatic safety of colchicine as a prophylactic therapy in gout patients treated with febuxostat. We investigated whether the concomitant use of colchicine and febuxostat increases hepatotoxicity in gout patients, and evaluated the factors associated with hepatotoxicity in gout patients treated with febuxostat.

#### **2. Materials and Methods**

### *2.1. Study Subjects*

A total of 319 patients initially diagnosed with gout at Kangwon National University Hospital from January 2012 to December 2018 were included. Exclusion criteria were as follows: age at the time of diagnosis <18 years, patients who used uric acid-lowering agents in asymptomatic hyperuricemia, and patients whose follow-up period was less than 3 months. Patients who had a history of allopurinol use were also excluded. A total of 178 gout patients treated with febuxostat were included. The study was approved by the Institutional Review Board of Kangwon National University Hospital and conducted in accordance with the Declaration of Helsinki (IRB protocol number: 2019-12-009).


*Article* **DSC Analysis of the Effect of Cold Deformation on the Precipitation Kinetics of a Binary Cu-Sc Alloy**

**Ramona Henle 1,\*, Julia Dölling 2, Ulrich Prahl 3, Gerrit Nandi 1 and Andreas Zilly 2**

**Abstract:** The present study aimed to investigate the effect of cold deformation on the precipitation kinetics of a binary CuSc alloy containing 0.4 wt.% scandium using the experimental analysis method of differential scanning calorimetry (DSC). Non-deformed and 75% cross-section-reduced cold-rolled supersaturated specimens were tested in non-isothermal DSC runs at up to five different heating rates. The DSC results showed that cold rolling significantly accelerated the precipitation process in the binary alloy, leading to a decrease in the initial and peak temperatures of the exothermic reactions. The activation energies calculated with the Kissinger method indicated that the precipitation activation energy decreased with increasing cold deformation. The findings of this study provide worthy implications to further optimize the processing of Cu-Sc alloys with improved mechanical properties.

**Keywords:** copper–scandium CuSc; copper alloy; differential scanning calorimetry DSC; precipitation kinetics; cold-working; cold-rolling; activation energy; Kissinger method


*3.5. Serum Stability of the 225Ac-rHDL System*

The 225Ac-rHDL system (150 µL) was added to 5 mL of diluted human serum (5×). The solutions (*n* = 3) were incubated at 37 ◦C for 10 days. A total of 1 mL of sample was taken at 24, 72, 144, and 240 h to evaluate the stability of the nanosystem. To each sample, 300 µL of TFA was added for protein precipitation. Samples were centrifuged at 1200× *g* for 5 min. The activity (measured in a in a well-type scintillation NaI(Tl) detector) obtained in the sediment corresponded to 225Ac-rHDL, and the activity in the supernatant, to the free fraction of 225Ac3+ leaked from the rHDL nanosystem.


**2.1 Optical schematics of SPIDER**

Our home made SPIDER setup is shown in Fig. 1. Figure 1(a) is the schematic optical path. An input femtosecond laser pulse passes through an aperture A1, and then is reflected by a reflective mirror M1. The reflected pulse is split into two pulses by a beam splitter BS1. One of the split pulse is stretched into a strongly chirped pulse, and anther is fed into a Michelsontype interferometer and then replicate into two replicas. The Michelson-type interferometer consists of two beam splitters BS2, BS3 and two corner mirrors TS2, TS3. A fixed time delay between the replicas is generated by tuning the translation stage TS2. The strongly chirped pulse and the replicas are focused by a paraboloid mirror PM, and then sum-frequency generation occurs in a sum-frequency crystal CR. A translation stage TS1 is used for tuning the relative time delay between the strongly chirped pulse and the two replicas. The two replica pulses interact with different parts of the chirped pulse and are upconverted to two different frequencies. The spectral interferogram of the frequency upconverted pulses is recorded by a fiber spectrometer (HR 4000, Ocean Optics Inc.). The spectral phase of the input pulse can be retrieved from the measured spectral interferogram. Our home-made experimental optical setup is shown in Fig. 1(b), with the optical path superposed.

Fig. 1. Our home-made SPIDER setup and the optical path. (a) Optical schematic, (b) experimental setup.

The spectrum of a pulse can easily be measured with a spectrometer. The pulse would be completely known, if we could, in addition, determine the phase across the spectrum [9]. SPIDER is a technique for measurement spectral phase of femtosecond optical pulses. In SPIDER setup, two replicas of the input pulse to be characterized are generated with a fixed time delay between them. These two replica pulses are then upconverted by sum-frequency mixing with a strongly chirped pulse derived from the same original input pulse. Because the two replica pulses are separated in time domain, they interact with different parts of the chirped pulse and are therefore upconverted to different frequencies. From the interferogram of these spectral shearing pulses, it is possible to extract the amplitude and

Our home made SPIDER setup is shown in Fig. 1. Figure 1(a) is the schematic optical path. An input femtosecond laser pulse passes through an aperture A1, and then is reflected by a reflective mirror M1. The reflected pulse is split into two pulses by a beam splitter BS1. One of the split pulse is stretched into a strongly chirped pulse, and anther is fed into a Michelsontype interferometer and then replicate into two replicas. The Michelson-type interferometer consists of two beam splitters BS2, BS3 and two corner mirrors TS2, TS3. A fixed time delay between the replicas is generated by tuning the translation stage TS2. The strongly chirped pulse and the replicas are focused by a paraboloid mirror PM, and then sum-frequency generation occurs in a sum-frequency crystal CR. A translation stage TS1 is used for tuning the relative time delay between the strongly chirped pulse and the two replicas. The two replica pulses interact with different parts of the chirped pulse and are upconverted to two different frequencies. The spectral interferogram of the frequency upconverted pulses is recorded by a fiber spectrometer (HR 4000, Ocean Optics Inc.). The spectral phase of the input pulse can be retrieved from the measured spectral interferogram. Our home-made experimental optical

**2. Characterization of femtosecond pulses with wavelet-transform for**

phase of the initial pulse by using an algebraic inversion algorithm [2].

setup is shown in Fig. 1(b), with the optical path superposed.

Fig. 1. Our home-made SPIDER setup and the optical path. (a) Optical schematic,

**spectral phase retrieval**

**2.1 Optical schematics of SPIDER**

(b) experimental setup.

### **2.2 Spectral phase retrieval with a wavelet-transfrom**

In the traditional phase retrieval algorithm, spectral phase is extracted from the filtered alternating current component of the Fourier transform [8]. The filter is set by manual selection and adjustment. A problem is that different widths or shapes of the filter produce different spectral phases [10]. Thus the uncertainty of the spectral phase contributes to the uncertainty of the reconstructed pulses.

To reduce the uncertainty component coming from the filter with Fourier transform technique, we introduce a wavelet-transform for spectral phase retrieval of femtosecond optical pulses [11]. The phase is directly extracted from the ridge of wavelet-transform. There are no filters in this procedure so that the uncertainty from the filter is eliminated. In what fallows a demonstration of this procedure will be shown.

We have measured an ultrashort optical pulse train emitted from a Ti:sapphire laser (Micra-5, Coherent Inc.). The average output power of the laser is 360 mW after a pulse compressor. The repeat frequency is 82 MHz, and the central wavelength is 800 nm with a spectral bandwidth (FWHM) of 100 nm. We perform a SPIDER measurement with our home-made SPIDER setup. The measured spectral interferogram is shown in Fig. 2.

Wavelet-transform was applied on the measured spectral interferogram, and the time and frequency distributions are exhibited on a two-dimensional plane. The intensity map and phase map are shown in Figs. 3(a) and 3(b), respectively.

Fig. 2. Measured spectral interferogram.

Fig. 3. Wavelet-transform of spectral interferogram. (a) Intensity topography, (b) phase topography. The ridge of wavelet-transform is indicated with a pink coloured line.

We search for the maximum values from the intensity topography along each frequency column. Connecting the positions of the maximum values at each frequency point constructs the ridge line of the wavelet-transform, which is superposed on Fig. 3(a) with a pink coloured line. Then we project the position of ridge from intensity topography (Fig. 3(a)) on the phase topography, as is shown in Fig. 3(b).

The phase of the spectral interferogram was directly extracted from the phase topography at the position of the ridge. With the extracted interferometry phase, the spectral phase was obtained with a concatenation algorithm [8], as is shown in Fig. 4.

Fig. 4. Measured spectrum and retrieved spectral phase.

Fig. 3. Wavelet-transform of spectral interferogram. (a) Intensity topography, (b) phase topography. The ridge of wavelet-transform is indicated with a pink coloured line.

the phase topography, as is shown in Fig. 3(b).

obtained with a concatenation algorithm [8], as is shown in Fig. 4.

Fig. 4. Measured spectrum and retrieved spectral phase.

We search for the maximum values from the intensity topography along each frequency column. Connecting the positions of the maximum values at each frequency point constructs the ridge line of the wavelet-transform, which is superposed on Fig. 3(a) with a pink coloured line. Then we project the position of ridge from intensity topography (Fig. 3(a)) on

The phase of the spectral interferogram was directly extracted from the phase topography at the position of the ridge. With the extracted interferometry phase, the spectral phase was

#### **2.3 Pulse waveform reconstruction and autocorrelation simulation**

Figure 4 shows the measured spectrum with a spectrometer (HR4000 CG-UV-NIR, Ocean Optics Inc.) and the retrieved spectral phase with wavelet-transform technique. The electric field (Fig. 5(a)) and waveform (Fig. 5(b)) of the femtosecond optical pulse are reconstructed from the spectrum and spectral phase with an inverse Fourier transform technique. The pulse width (FWHM) shown in Fig. 5(b) is 18.2 fs.

Fig. 5. Reconstructed electric field and waveform. (a) Electric field, (b) waveform.

From the reconstructed electric field in Fig. 5(a), we simulated the autocorrelation traces of the pulses. The simulated interferometric autocorrelation and intensity autocorrelation are shown in Fig. 6(a) and 6(b), respectively. The intensity autocorrelation in Fig. 6(b) shows the width of autocorrelation (FWHM) is 26.6 fs. With the reconstructed pulse waveform in Fig. 5(b) and the simulated intensity autocorrelation in Fig. 6(b), we can obtain the ratio of autocorrelation width *c* to the pulse width *p* is *cp* = 1.462.

Fig. 6. Simulated autocorrelation traces with reconstructed pulse electric field. (a) Interferomatric autocorrelation, (b) intensity autocorrelation.

#### **2.4 Pulse waveform reconstruction from different replicas separations**

We have investigated the effects of pulse replicas separation on the spectral phase retrieval of femtosecond optical pulses. By tuning the translation stage TS2, a serious of spectral interferograms with different replicas separations was recorded. Figures 7(a), 7(c), 7(e), 7(g), and 7(i) are five measured spectral interferograms with replicas separations of 0.22 ps, 0.55 ps, 0.83 ps, 1.58 ps, and 1.82 ps respectively. We retrieved the spectral phases from the five measured interferograms with wavelet-transfrom. The extracted spectral phases are shown in Figs. 7(b), 7(d), 7(f), 7(h), and 7(j).

We have investigated the effects of pulse replicas separation on the spectral phase retrieval of femtosecond optical pulses. By tuning the translation stage TS2, a serious of spectral interferograms with different replicas separations was recorded. Figures 7(a), 7(c), 7(e), 7(g), and 7(i) are five measured spectral interferograms with replicas separations of 0.22 ps, 0.55 ps, 0.83 ps, 1.58 ps, and 1.82 ps respectively. We retrieved the spectral phases from the five measured interferograms with wavelet-transfrom. The extracted spectral phases are shown

**2.4 Pulse waveform reconstruction from different replicas separations**

in Figs. 7(b), 7(d), 7(f), 7(h), and 7(j).

Fig. 7. Measured spectral interferograms with different replicas separations and retrived spectral phases from the interferograms. (a), (c), (e), (g), and (i) are measured interferograms with replicas separations of 0.22 ps, 0.55 ps, 0.83 ps, 1.58 ps, and 1.82 ps respectively; (b), (d), (f), (h), and (j) are the retrieved spectral phases from interfrograms in (a), (c), (e), (g), and (i) respectively.

With the retrieved spectral phases and the measured spectrum, the waveform of the pulse can be reconstructed. Figure 8(a) is the five retrieved spectral phases with different replicas separations and the spectrum. Figure 8(b) is the reconstructed pulse profiles from the spectrum and spectral phases with inverse Fourier transform.

Fig. 8. Retrieved spectral phase and reconstructed pulse profile with different replicas separations. (a) Spectrum and retrieved spectral phases, (b) reconstructed pulse profiles.

Figure 8(a) shows that with wavelet transform, spectral phases are retrieved from a large range of replicas separations. With replicas separations from 0.22 ps to 1.82 ps, the relative difference of spectral phase is within 0.5 rad. In Fig. 8(b), the full width at half maximum (FWHM) of the reconstructed pulse profiles from replicas separations of 0.22 ps, 0.55 ps, 0.83 ps, 1.58 ps, and 1.82 ps are 28.50 fs, 27.30 fs, 27.77 fs, 28.75 fs, 28.47 fs, 26.81 fs, 26.65 fs, 27.60 fs, and 28.03 fs, respectively. The maximum relative difference is 2.76%, which demonstrates the accuracy of the spectral phase retrieval with wavelet-transform.