**Miniaturized Silicon Photodetectors New Perspectives and Applications**

Maurizio Casalino Edited by

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## **Miniaturized Silicon Photodetectors**

## **Miniaturized Silicon Photodetectors: New Perspectives and Applications**

Editor

**Maurizio Casalino**

MDPI • Basel • Beijing • Wuhan • Barcelona • Belgrade • Manchester • Tokyo • Cluj • Tianjin

*Editor* Maurizio Casalino Institute of Applied Sciences and Intelligent Systems Italy

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This is a reprint of articles from the Special Issue published online in the open access journal *Micromachines* (ISSN 2072-666X) (available at: https://www.mdpi.com/journal/micromachines/ special issues/Silicon Photodetectors).

For citation purposes, cite each article independently as indicated on the article page online and as indicated below:

LastName, A.A.; LastName, B.B.; LastName, C.C. Article Title. *Journal Name* **Year**, *Volume Number*, Page Range.

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## **Contents**

## **About the Editor**

**Maurizio Casalino** (Dr.) graduated summa cum laude in electronic engineering from the University of Naples "Federico II" and he received his Ph.D. degree in engineering electronic from the University "Mediterranea" of Reggio Calabria in the 2008.

In the 2010, he became a researcher at the Institute of Applied Science and Intelligent Systems "Eduardo Caianiello" of the National Council of Research (ISASI-CNR) in Naples (Italy).

He is the author of more than 90 scientific articles published in peer-reviewed journals, proceedings of congress, book chapters, and review articles. His research interests include the design, fabrication, and characterization of photonic devices. Dr. Casalino has served as a reviewer for many international scientific journals, including *Nanoscale*, *Small*, *ACS Nano*, and *Nature Communications*.

He is a member of the Italian Society of Optics and Photonics (SIOF), member of the Italian Society of Electronics (SIE), and member of the Institute of Electrical and Electronics Engineers (IEEE).

## *Editorial* **Editorial for the Special Issue on Miniaturized Silicon Photodetectors: New Perspectives and Applications**

#### **Maurizio Casalino**

Institute of Applied Science and Intelligent Systems "Eduardo Caianiello" (CNR), Via P. Castellino n. 141, 80131 Naples, Italy<EMAIL_ADDRESS>
Received: 9 November 2020; Accepted: 13 November 2020; Published: 17 November 2020

Silicon (Si) technologies provide an excellent platform for monolithically integrating both photonic [1] and microelectronic [2] functionalities in the same substrate. In the last few years, a variety of passive and active Si photonic and optoelectronic devices have been reported, in particular in the field of photodetection [3–5] where new effects and structures have been proposed. Si photodetectors (PDs) at visible wavelengths are a commercial reality, but, unfortunately, they cannot be employed in the infrared (IR) range due the Si transparence over 1100 nm. Historically, the use of germanium (Ge) grown on Si has allowed for the realization of Si-based PDs up to 1550 nm [6]. In recent years, impressive progresses have been achieved by extending the operation of Si PDs to the infrared regime and, recently, thanks to the investigation of new smart structures and effects, the all-Si approach has demonstrated potentialities leading to performances close to those of the well-established germanium (Ge) technology. Moreover, the possibility to integrate new emerging 3D and 2D materials with Si, together with the capability of manufacturing devices at the nanometric scale, has led to the development of new devices with unexpected performance.

There are eight papers published in this Special Issue, six original works and two review articles. The spectral range covered by these works goes from the ultraviolet (UV) to the infrared (IR) regime. Among the original works, four of them are focused on the investigation of novel Si-based PDs while the remaining two on the characterization of materials that could be employed in Si technology. The four papers proposing original devices are based on Schottky, metal–semiconductor–metal (MSM) and P/N structures. The proposed Schottky photodetectors take advantage of the integration of graphene on both crystalline silicon (c-Si) and polycrystalline silicon (poly-Si) substrates while the MSM PDs are based on germanium–tin (GeSn) layers. Both structures (Schottky and MSM) have shown the capability to detect near infrared (NIR) wavelengths. On the other hand, a complementary metal–oxide–semiconductor (CMOS) single photon avalanche P/N diode has been investigated for detecting light in the visible regime. Concerning the two papers dealing with the material characterization, they investigate layers of 4H-SiC and ZnO to be integrated on Si for detecting UV and visible regime. Finally, two review articles are focused on the development of CMOS-compatible microbolometers and integrated PDs based on group IV and colloidal semiconductors.

In particular, Tsai et al. [7] proposed a graphene/poly-Si PD to monolithically integrate with the electronic circuitry constituting the active pixel of a CMOS image sensor. This work is interesting mainly for two reasons. First, although graphene/crystalline Si PDs have been frequently reported in the literature [8], the investigation of graphene/polycrystalline junctions is much less frequently discussed. Second, the use of polycrystalline silicon as semiconductor, instead of crystalline silicon, makes the photodetector able to be directly integrated on top of the gate oxide of a conventional metal–oxide–semiconductor field effect transistor (MOSFET), enabling the realization of a compact active pixel to be employed in CMOS image sensors. The authors name this new proposed structure as: photodiode–oxide–semiconductor field effect transistor (PDOSFET). If the device described in the work of Tsai et al. should operate in the visible range, M. Casalino theoretically investigates the possibility of employing hybrid graphene/c-Si Schottky diodes to detect NIR wavelengths [9]. In this work, the absorption mechanism is based on the internal photoemission effect: graphene first absorbs the incoming radiation and then it transfers the photoexcited carriers into Si where they are collected. In addition, this work suggests integrating the graphene layer in the middle of a silicon-based Fabry–Pérot microcavity constituted by an amorphous hydrogenated silicon/graphene/crystalline silicon three-layer system surrounded by two high reflectivity mirrors. The author shows that the enhancement of the optical field inside the cavity allows a significant increase in graphene optical absorption and, consequently, in device efficiency. Theoretical results show responsivity of 0.24 A/W, bandwidth in GHz regime, noise equivalent power of 0.6 nW/cm√ Hz. MSM PDs have been proposed by Ghosh et al. taking advantage of GeSn layers integrated on Ge-buffered Si substrates for short-wave infrared (SWIR) applications [10]. Indeed, GeSn shows a significant absorption along the entire telecommunication bands unlike germanium (Ge), whose optical absorption falls drastically beyond 1550 nm. GeSn MSM PDs have been both electrically and electro-optically characterized. The I–V electrical characteristic shows the classical MSM behavior while the spectral responsivity measurements show a broadband optical absorption extending over 1800 nm. The reported responsivity increases by increasing the bias voltage and at 7 V maximum values of about 100, 70 and 10 mA/W at 1200, 1500 and 1800 nm, have been reported, respectively. The paper of Goll et al. investigates the discharge mechanism of single-photon avalanche diodes (SPADs) designed in 0.35 μm CMOS technology [2]. Indeed, after the avalanche has been triggered, the SPAD cathode–anode voltage reaches the breakdown voltage with a time that has been measured by the authors. Based on the cathode capacitance measurements, the avalanche current through each SPAD was evaluated too. Measurements on the cathode voltage transient of SPADs based on a 12 μm-thick p- epi-layer (named type A) with various diameters were investigated. Results show fall times of 3.45 ns for 200 μm diameter SPAD and an excess bias (voltage difference between diode work reverse voltage and the breakdown voltage) of 4.26 V, as well as fall times of 10.2 ns for 50 μm diameter SPAD and an excess bias of 4.2 V. On the other hand, SPADs with different diameters were implemented in the high-volume (HV) line of the same CMOS process (named type B) showing fall times of 2 ns for 98.2 μm diameter SPAD and 5.9 V excess bias, as well as 8 ns for 48.2 μm diameter SPAD and 5.4 V excess bias.

Moving our attention onto the characterization of materials to be employed for the realization of Si-based photodetectors, J. Li et al. investigate how different chemical vapor deposition (CVD) growth conditions impact the defect density of 4H-SiC epilayers and the performance of Nickel(Ni)/4H-SiC Shottky PDs [11]. In this work, particular attention was paid to triangular defects (TDs) and deep level defects, Z1/2, showing that, while the C/Si ratio strongly impacts the formation of TDs, no correlation with the deep level defect, Z1/2, can be confirmed. This work shows that, by adjusting the C/Si ratio, the quality of the 4H-SiC epilayer can be improved and the performance of the Ni/4H-SiC Schottky detector increased. In their work, G. Li et al. evaluate the impact ionization coefficient of electrons in a ZnO layer along the (001) direction [12]. In order to do it, the authors have investigated p-Si/i-ZnO/n-AZO structures illuminated by a 532 nm laser diode where the electron avalanche multiplication is triggered in the i-ZnO layer whose thickness was varied from 250 to 750 nm. These insights could be very useful for the realization of high-performance ultraviolet (UV) avalanche photodiodes).

Finally, this Special Issue includes also two review articles: Dardano and Ferrara have reported recent advances in the field of photodetection based on group IV materials with particular reference to silicon [13]. In recent years, the challenge to make silicon usable at NIR wavelengths has attracted much interest and many absorption mechanisms have been both proposed and investigated. The authors show as the mid-bandgap absorption (MBA), i.e., the infrared absorption obtained by voluntarily introducing defects in the Si bandgap, combined with high Q-factor cavity structures (ring resonators), has emerged as a viable solution for the realization of devices whose performance are comparable with the well-established Ge technology. Then, in their work, the authors reviewed PDs based on different materials, such as graphene, Ge and carbon nanotubes (CNTs). Moreover, an overview on PDs based on colloidal semiconductors, representing the frontier of future research, has been presented too. Finally, Yu et al. have reviewed the CMOS microbolometer technology for long-wave infrared

(LWIR) imaging applications at a low cost [14]. This technology is based on a standard CMOS process combined with a simple post-CMOS micro-electro-mechanical system (MEMS) process. In their work, the authors show that the performance of the reported CMOS-compatible microbolometers has started to compare favorably with the state of the art. This paper reviews not only the recent advances of the CMOS-compatible microbolometers but also the aspects of the pixel structure and of the read-out integrated circuitry.

I would like to take this opportunity to thank all the authors for submitting their papers to this Special Issue. I would also like to thank all the reviewers for dedicating their time and helping to improve the quality of the submitted papers. Finally, I would like to warmly thank Ms. Aria Zeng for her constant support in preparing this Special Issue.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The author declares no conflict of interest.

#### **References**

14. Yu, L.; Guo, Y.; Zhu, H.; Luo, M.; Han, P.; Ji, H. Low-Cost Microbolometer Type Infrared Detectors. *Micromachines* **2020**, *11*, 800. [CrossRef] [PubMed]

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© 2020 by the author. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## *Article* **Avalanche Transients of Thick 0.35** μ**m CMOS Single-Photon Avalanche Diodes**

#### **Bernhard Goll \*, Bernhard Steindl and Horst Zimmermann**

Institute of Electrodynamics, Microwave and Circuit Engineering, TU Wien, Gusshausstrasse 25/E354-02, A-1040 Wien, Austria<EMAIL_ADDRESS>(B.S<EMAIL_ADDRESS>(H.Z.)

**\*** Correspondence<EMAIL_ADDRESS>
Received: 1 September 2020; Accepted: 17 September 2020; Published: 19 September 2020

**Abstract:** Two types of single-photon avalanche diodes (SPADs) with different diameters are investigated regarding their avalanche behavior. SPAD type A was designed in standard 0.35-μm complementary metal-oxide-semiconductor (CMOS) including a 12-μm thick p- epi-layer with diameters of 50, 100, 200, and 400 μm; and type B was implemented in the high-voltage (HV) line of this process with diameters of 48.2 and 98.2 μm. Each SPAD is wire-bonded to a 0.35-μm CMOS clocked gating chip, which controls charge up to a maximum 6.6-V excess bias, active, and quench phase as well as readout during one clock period. Measurements of the cathode voltage after photon hits at SPAD type A resulted in fall times (80 to 20%) of 10.2 ns for the 50-μm diameter SPAD for an excess bias of 4.2 V and 3.45 ns for the 200-μm diameter device for an excess bias of 4.26 V. For type B, fall times of 8 ns for 48.2-μm diameter and 5.4-V excess bias as well as 2 ns for 98.2-μm diameter and 5.9-V excess bias were determined. In measuring the whole capacitance at the cathode of the SPAD with gating chip connected, the avalanche currents through the detector were calculated. This resulted in peak avalanche currents of, e.g., 1.19 mA for the 100-μm SPAD type A and 1.64 mA for the 98.2-μm SPAD type B for an excess bias of 5 and 4.9 V, respectively.

**Keywords:** single-photon avalanche diode (SPAD); gating; avalanche transients; 3.3 V/0.35 μm complementary metal-oxide-semiconductor (CMOS)

#### **1. Introduction**

Avalanche photodiodes (APDs) operated with a reverse voltage larger than the breakdown voltage (Geiger mode) are usually capable of detecting single photons and are termed single-photonavalanche-diodes (SPADs). A photon absorption generates an electron-hole pair, and in combination with the high-electric field in a multiplication zone, a large avalanche with charge carriers might be triggered due to impact ionization. This causes a current, which discharges the SPAD until its cathode-anode voltage reaches the breakdown voltage, where the avalanche is quenched. For a further detection of a photon, the SPAD has to be recharged again.

With reference to [1], the avalanche build-up (time between electron-hole pair generation due to a photon hit and reaching maximum avalanche charge) action of a SPAD consists at first in a local charge multiplication, a local voltage drop to breakdown level and then a spreading to lateral directions. After build-up, final quenching happens. The spreading might take place with the help of charge carriers, which move towards side directions or create additional secondary photons when some avalanche carriers recombine. The simplest equivalent circuit to model an avalanche action is the capacitance of the reverse biased avalanche diode in parallel with a resistor [1,2]. When a photon enters a SPAD, the photon detection probability (PDP) describes the chance that a self-sustaining avalanche is triggered. Even in the absence of photons, dark counts occur in a SPAD, which are uncorrelated avalanches due to thermal-/trap-assisted carrier generation or tunneling. They are characterized by

a mean dark count rate (DCR). Afterpulses, on the other hand, are avalanches, which are correlated to a previous avalanche. There are many reasons for afterpulses, e.g., the release of a carrier by a deep-level trap, which has been filled during a previous current flow, or, e.g., the diffusion of secondary charge carriers into the high-field zone of the SPAD, which were generated by photons originating from recombination during avalanche current flow. The probability for appearance of an afterpulse is described with afterpulsing probability (APP). It becomes lower the more time elapses after a previous avalanche. The voltage difference between how much the diode's reverse-voltage is higher than the breakdown voltage is one of the main parameters in operating a SPAD and is called excess bias. Typically, DCR, APP, and PDP increase when raising the excess bias [3–6]. After an avalanche has happened in a SPAD, it needs a dead time, which is controlled by surrounding circuitry, until it is recharged again and ready for a new photon detection. The APP strongly depends on the dead time. If the dead time is longer, the APP will decrease.

SPADs are important in applications like photon detectors for quantum communications [7,8] and quantum random number generators [9–11]. Recently, many multi-pixel image sensors with SPADs were published [12–17], some for 3D imaging. SPAD arrays have potential for highly sensitive optical data receivers [18–21]. Typically, the bit error rate (BER) of SPAD receivers suffers from DCR and APP. Forward error correction might be a solution to solve this problem [22]. A BER of 2 × 10−3 is sufficient to use a concatenated Reed–Solomon code super-forward-error-correction (FEC) scheme to get a BER better than 10−9 with 6.69% redundancy (ITU-T G.975.1). In [23], a 64 × 64 SPAD array in 130 nm complementary metal-oxide-semiconductor (CMOS) was capable to receive a 500 Mb/s 4-PAM optical signal with −46.1 dBm sensitivity for a bit error rate (BER) of 2 × 10−3 when using equalization. In [24], five subsequent time slots (one period of a 250 MHz clock), where each slot consists of the information of whether one or no photon was detected from a gating circuit in a 3.3-V/0.35-μm CMOS technology with one SPAD are fed into a shift register. Hence it could be decided whether a bit has been received or not with the knowledge of how many detections happened in a row of five time slots. This fully integrated optical receiver achieved a data rate of 50 Mb/s in non-return-to-zero (NRZ) with a sensitivity of −57 dBm (BER = 2 × 10−3).

This paper presents measurement results of the cathode voltage drop of two types of SPADs with different diameters when an avalanche occurs. SPAD type A was fabricated in standard 0.35-μm CMOS with 12-μm thick p- epi-layer with active diameters of 50, 100, 200, and 400 μm and type B was implemented in the high-voltage (HV) line of this process with active diameters of 48.2 and 98.2 μm. With the knowledge of the measured capacitance at the cathode node, the avalanche currents through each SPAD were determined. The voltage transient response with a measurement of its 80 to 20% fall time of SPAD type A with 50 μm diameter was already published in [25]. Each SPAD is wire-bonded to a clocked gating chip, which controls charge up to maximum 6.6-V excess bias, active, and quench phase as well as readout during one clock period. This cascaded gating chip was designed in a standard 3.3-V/0.35-μm CMOS technology.

#### **2. Single-Photon Avalanche Diodes (SPADs)**

In Figure 1, cross sections of SPAD type A (see Figure 1a) and SPAD type B (see Figure 1b) are depicted. Both diodes were fabricated in a 3.3-V/0.35-μm CMOS technology. Type A had a ≈12-μm thick low-doped p- epi layer with a doping concentration of ≈2 × 1013/cm3 and type B had the epitaxial layer of the high-voltage process version, which was doped with ≈1015/cm3 [26]. Each type of SPAD could be integrated together with additional circuitry on one chip each [24] when the electronic part was isolated from the substrate with the help of deep n-wells. SPAD type A used the standard CMOS process line and consisted of a n++ cathode with a p-well below to form a high-field multiplication zone. A thick p- epi layer acted as an absorption zone with a high-enough electric field for a high drift velocity of photo-generated charge carriers. Therefore, the maximum sensitivity of the SPAD was located in the visible red and was very near infrared region of the spectrum of the light. An n-well around the multiplication zone prevented the SPAD from edge breakdown. SPAD type A was fabricated in

diameters of 50, 100, 200, and 400 μm. Typical values for its DCR were, e.g., ≈104 counts per second (CpS) and for APP, e.g., 0.2% for a diameter of 50 μm at 20 ◦C, an excess bias of 3 V and a dead time of 9.5 ns [5]. The value of the PDP amounted to 21.5% for a wavelength of 635 nm [24], where the excess bias typically was near below ≈3 V for best BER. For a diameter of 100 μm, the DCR amounted to 1.89 × 104 CpS and 3.08 × 104 CpS for an excess bias of 3.3 and 6.6 V, respectively, at a temperature of 25 ◦C [27]. The APP was 0.7 and 4.8% for an excess bias of 3.3 and 6.6 V, respectively, and a dead time of 9.5 ns. For an excess bias of 6.6 V and wavelengths of 635 and 850 nm, PDPs of 35.1 and 22%, respectively, were achieved.

**Figure 1.** Cross sections (not to scale) of (**a**) single-photon avalanche diode (SPAD) type A in 0.35 μm standard CMOS with p- epi-layer and (**b**) SPAD type B in 0.35 μm high-voltage (HV) complementary metal-oxide-semiconductor (CMOS) with standard p epi-layer, deep p-well, and deep n- -well for high-voltage applications (FOX = field oxide).

SPAD type B was designed in the high-voltage (HV) line of this 0.35-μm CMOS technology with the option of an oxide opening (opto window) with anti-reflection coating (ARC) above the diode (see Figure 1b), which was a nitride layer, where the thickness was optimized for no reflection at visible red light. The cathode consisted of a highly doped n++ region, which was slightly thicker than the cathode of type A. The high-field multiplication zone was located at the passage between cathode and a deep p-well. To assure that the electric field in the depleted absorption zone, which has the same function as for SPAD type A, was high enough for a high drift velocity of photo-generated charge carriers, a deep n- -well was added. SPAD type B was fabricated in diameters of 49.2 and 98.2 μm. At a temperature of 25 ◦C and for a diameter of 49.2 μm, the best measured DCR amounts to 2.88 × 104 CpS for samples in the middle of the wafer up to 14.04 × 104 CpS for samples from the border for an excess bias of 6.6 V. The APP was determined to be near 80% for samples in the middle and down to 10% for samples from the border of the wafer if a dead time of 5.8 ns was used [28]. The PDP was 37.4, 27.9, and 18.6% for wavelengths of the light of 780, 850, and 900 nm, respectively. For the SPAD type B with a diameter of 98.2 μm, a DCR of ≈ 5.5 × 105 CpS for an excess bias of 3.3 V at a temperature of 25 ◦C was measured [29]. The APP was ≈ 10% for an excess bias of 3.3 V and 6 ns dead time. The measured PDP for an excess bias of 3.2 V was ≈21% for 650 nm wavelength. For a wavelength of 800 nm and 6.6 V excess bias, a PDP of 35% was obtained.

A figure of merit (FoM) to compare the performance of different detectors is the noise-equivalent power (NEP) [28,30]. It is depicted in Equation (1), where *h* is the Planck constant, *c* is the speed of light in vacuum, and λ the wavelength of the used light.

$$NEP \;= \; \frac{hc}{\lambda} \frac{\sqrt{2DCR}}{PDP} \tag{1}$$

For SPAD type A with a diameter of 50 μm, this resulted to *NEP* ≈ 205.8 aW√Hz for 3-V excess bias and 635-nm wavelength. For SPAD type B with a diameter of 49.2 μm, a best *NEP* ≈ 163.4 aW√Hz was calculated for 6.6-V excess bias and 780-nm wavelength. The focus of this paper is the transient measurement of photon-triggered avalanche pulses. More information about PDP, DCR, and APP (also in dependence on excess bias) of SPADs type A and B is published in [5,28,29].

#### **3. Gating Chip**

For controlling the SPADs, a gating chip was designed in 0.35-μm CMOS technology with a nominal supply voltage of 3.3 V. In comparison to a quenching circuit, a gated SPAD has defined, mostly periodic time slots, where it is set to active and ready for photon detection. Once a photon has triggered an avalanche, the SPAD is conducting until the breakdown voltage is reached by the cathode-anode voltage or until the reset phase starts (if the photon was absorbed close to the end of the active phase) and quenches the detector below breakdown voltage. This can be, e.g., done with a clock signal, which defines that in one half of the clock period the SPAD is active and in the other half it is quenched. In the active time window, at most, one avalanche can occur. Therefore, to be able to detect more photons, the clock frequency has to be increased. In the case of a data receiver, this results in a larger clock frequency than the data rate [24].

Figure 2 shows the block diagram of the gating control chip. The cathode of the SPAD was bonded with gold wire with 25-μm diameter and 1-mm length to the node CAT. Hence the gating controller can pull the cathode potential to ≈*VSPAD* = 3.3 V to set the SPAD active for photon detection in Geiger mode or to ≈*VSS* = −3.3 V to quench the SPAD in the reset phase. The resulting cathode-anode voltage is *VSPAD*-*VAn* for detection and *VSS*-*VAn* for reset. For operation, the breakdown level of the SPAD should be located somewhere in between. A detailed schematic of the whole gating control chip including the transients are depicted in Figure 3. On-chip, a clock driver generated digital clocks for the circuit block SPAD control and for the switching transistors out of a sine wave with ≈600 mV amplitude, which was applied to pad CLKIN. With a bond wire, CLKIN was connected to a 50-Ω micro-strip line on the printed circuit board (PCB). Therefore, an on-chip 50-Ω resistor was added for termination without appreciable reflections. The on-chip clock driver generates a digital non-inverted and inverted clock, nodes CLK, and CLK, where the logical voltage levels were ground node GND = 0 V for digital low and *VDDL* = 3.3 V for digital high. Clock signal CLKD corresponded to CLK, but was level shifted down by 3.3 V so that the logical voltage levels result to −3.3 and 0 V.

**Figure 2.** Block diagram of a clocked gating control chip, where a SPAD is connected with a bond wire. A radio frequency (RF) amplifier measures the cathode voltage via a RF probe needle on the pad at node cathode node (CAT).

**Figure 3.** SPAD control in the gating control chip: (**a**) Schematics; (**b**) Simulated transients assuming a fast responding SPAD. A photon hit triggers an avalanche in the SPAD, which discharges node CAT until the cathode-anode voltage reaches its breakdown voltage and the avalanche is quenched.

The anode voltage of the external SPAD was applied via a separated pad, which was wire-bonded to the PCB. To charge up the cathode node (CAT) to ≈*VSPAD* = 3.3 V, transistor P0 was turned on. To discharge node CAT to ≈*VSS* = −3.3 V for quenching an avalanche in the SPAD, or to deactivate it, transistor N0 was switched on. All transistors are specified to work with a supply voltage of 3.3 V. To be able to switch node CAT between ≈*VSS* = −3.3 V and ≈*VSPAD* = 3.3 V, which resulted into a 6.6-V swing, cascode transistors P1 and N1 were added to protect all transistors against overvoltage. N-MOS transistors are typically smaller and faster with less parasitic capacitances than P-MOS transistors. Therefore, it was sufficient to connect the gate of N1 to GND, whereas on the gate of P1, a voltage of *Vcas*c = −1 V was applied to faster charge-up node CAT and to reduce voltage peaks in the drain-source voltage of P0 and P1, which could exceed their critical voltages during switching action. On the other side, transistor N2 helped discharging node PLS due to similar reasons.

A clock period consisted of a reset phase (CLK = CLKD = GND = 0 V and CLK = *VDDL* = 3.3 V), where the cathode-anode voltage of the SPAD was below the breakdown voltage, when node CAT was pulled down to ≈*VSS* = −3.3 V, *PLS* ≈ 0 V, and an active phase where CLK switches to *VDDL* = 3.3 V (CLK = GND = 0 V and CLKD = *VSS* = −3.3 V). In reset of the SPAD, the node voltages in the unit SPAD control were LAT = CH = *VDD* = 3.3 V and *LAT* = 0 V, thus transmission gate P3/N3 was turned

on, P2 was off, and node CHARGE = CLK = *VDDL* = 3.3 V, hence transistor P0 was off. Transistor N0 was turned on.

In the active phase, transistor N0 is off. At first, a small fraction of the time duration in this phase was used to charge up the SPAD in pulling up node CAT and PLS to ≈*VSPAD* = 3.3 V with P0 turned on, because at the beginning, nodes LAT = CH = VDD and *LAT* = 0 V, thus transmission gate P3/N3 was on, P2 off, and CHARGE = CLK = 0 V. Transistor P0 was charging node CAT and PLS until PLS reached a voltage level near *VSPAD*. This charge-up was monitored at node PLS with transistor N5, which is turned on after its gate-source voltage raises above its threshold voltage. As a consequence, node CH is discharged with transistor N4 to ≈ 0 V, which forces the latch to flip to *LAT* = *VDD* and LAT = 0 V, thus transmission gate P3/N3 is turned off and P2 is turned on, which charges up node CHARGE to *VSPAD* to stop charging up node CAT and PLS with transistor P0. Because of parasitic capacitances and delay times of logic elements, the time lag between detection with N5 and turning off P0 was sufficiently long that nodes CAT and PLS can easily reach a voltage level very close to VSPAD. Following this, the cathode-anode voltage was above the breakdown voltage; transistors P0, N0, and N2 were turned off; node CAT was charged up and floating; and the SPAD was ready for photon detection. The excess bias depended on the size of the anode voltage *VAN* of the SPAD. For a distinct breakdown voltage *VBD*, the excess bias *VEB* can be calculated to *VEB* ≈ *VSPAD*−*VAN*−*VBD*, where the breakdown level of the cathode voltage must be located between *VSPAD* and *VSS*, hence *VEB* ≤ *VSPAD*−*VSS*.

There could be the case that during charge up of node CAT, when P0 is turned on, an avalanche might occur in the SPAD, which would result especially for low ohmic diodes in a large current flow. Consequently, transistor N5 would never detect a finished charge up at node PLS and P0 stays turned on until the subsequent reset phase. To avoid such a large current flow during nearly the whole active phase of the SPAD, transistor N6 was added. With voltage *Vsec* at the gate of N5, node CH can be discharged independently from transistor N5 during an adjustable time duration. Thus, with adjusting *Vsec*, transistor N6 can be turned off or a discharging time for node CH can be set.

To read out whether an avalanche occurred or not, transmission gate N4/P4 was turned on during the active phase of the SPAD. The clocked comparator was in reset. In the subsequent reset phase of the SPAD, transmission gate N4/P4 was turned off and the voltage at node PLS was stored dynamically in the parasitic capacitance at the negative input-node of the comparator at the end of the active phase. A voltage drop indicated an avalanche. In the reset phase of the SPAD the comparator compared the stored voltage with a reference voltage *Vref* to generate a digital decision at node OUT dependent on whether an avalanche occurred or not. With *Vref*, the detection threshold for the voltage drop at PLS can be set. Finally, a 50-Ω driver was implemented, which consisted of a chain of inverters capable to drive an off-chip 50 Ω load, i.e., a fast oscilloscope.

Capacitance *CCa*t in Figures 2 and 3a represents the overall node capacitance of node CAT including the cathode of the SPAD. Neglecting the bond wire in between due to its low inductance was justified. When an avalanche occurs during the active phase, transistors N0, P0 and N2 were off and only the current through the SPAD can discharge node CAT. Consequently, the avalanche current can be calculated out of the transient of the avalanche with *CCa*t × *d*VCat/dt when measuring the whole node capacitance *CCat*, which included the capacitance of the SPAD due to its connection with a bond wire.

#### **4. Measurement Setup, Results, and Discussion**

Each SPAD was glued together with one gating chip on a printed circuit board (PCB) consisting of FR4 base material (FR = flame retardant). The cathode of the SPAD was bonded with a gold bond wire to node CAT of the gating chip. The anode of the SPAD was bonded to a DC line on the PCB, which provides the negative anode voltage VAN. The sine wave to generate on-chip a digital clock signal was applied via a microstrip line and an SMA connector on the PCB to the gating chip. All supply and reference voltages were provided to the chip via connectors, block capacitances, and lines on the

PCB as well. The PCB itself was mounted on a copper block with temperature sensor and with a Peltier cooler below, which regulated the temperature on the PCB to 25 ◦C for measurements.

The transients of the cathode voltage at the pad of node CAT (see Figure 1) were measured with a high-speed radio frequency (RF) probe, Picoprobe Model 35 from GGB Industries, which had a frequency response from DC to 26 GHz, an operating range of −6 to 6 V, 10:1 signal attenuation, and 1.25-MΩ and 50-fF load at the input. The Model 35 Picoprobe was connected with a coaxial cable (K-system) to a Keysight MSOV204A Mixed Signal Oscilloscope with 20 GHz bandwidth and at maximum 80-GSa/s sampling rate. Unfortunately, the anode pad of the SPAD was situated nearby the cathode pad. Therefore the needle was placed on the pad of node CAT to avoid an accidental touch to the anode pad with its large negative voltage, and consequently, to damage of the expensive Picoprobe. The length of the bond wire between the cathode of the SPAD and node CAT of the gating chip was ≈2 mm, which corresponds to a series inductivity of ≈2 nH when using 1 nH/mm as a rule of thumb. A comparison of the transient at node CAT with the transient directly at the cathode pad of the SPAD revealed no noteworthy difference.

For measuring the transient signals, the gating chip was clocked with 15 MHz, which results in a duty cycle of 50% for a time duration of the active phase of the SPAD of ≈33.3 ns to be able to observe the whole discharging phase when an avalanche occurs. The minimum dead time corresponded to the time duration of the reset phase of the SPAD, which amounted to ≈33.3 ns. Figure 4 shows typical results of the cathode voltage's transient with and without avalanche events, where several active phases have been overlaid for illustration.

**Figure 4.** Transients of the cathode voltage (node CAT) of a SPAD type A with a diameter of 50 μm for different anode voltages *VAN*. In the illustration, transients of several active phases are overlaid. It can be seen that early avalanches quench (themselves) during the active phase, when the breakdown level is reached. Some avalanches, which occurred later in the active phase are quenched by the following reset phase. The observed breakdown level in this figure depends on the anode voltage *VAN*. It can be calculated with the breakdown voltage as *VAN* + *VBD*.

If an avalanche occurs, e.g., due to a photon hit, node CAT is discharged by the avalanche current of the SPAD. Avalanches, which happen earlier in the active phase have enough time to discharge node CAT until the breakdown level is reached. Later avalanches are quenched by the following reset phase. If no avalanche occurs, the voltage at node CAT remains and will be only switched below breakdown level during the reset phase.

With lots of samples of avalanche transients, which happened approximately in the first quarter of the active phase, an 80 to 20% fall time could be measured for the different SPADs. For this, the SPAD was illuminated with a halogen light so that the photon hits on the SPAD were somewhat equally distributed over the time duration of the active phase when overlaying several cycles with a storage oscilloscope as, e.g., depicted in Figure 5 for a SPAD type B with 48.2-μm diameter for an anode voltage of −66 V. When considering an ideal exponential decay of the excess bias, the time constant τ can be calculated by dividing the 80 to 20% fall time by ln(4).

**Figure 5.** Oscilloscope picture of one avalanche (**top**) and several overlaid avalanches (**bottom**) of the cathode voltage of a SPAD type B with 48.2 μm diameter for an illumination power with a halogen source to achieve somewhat equally distributed photon hits.

Figure 6 shows the results for the different types of SPADs. There is a tendency that SPADs of type B in the HV CMOS technology are somewhat faster than SPADs of type A due to more avalanche current. The reason could be that for SPAD type B in HV CMOS technology deeper wells with a tendency to lower doping are used to meet requirements of high-voltage operation, which increases the breakdown voltage. This may result in a vertical thinner p epi layer (thinner absorption zone) below the SPAD type B, which in combination with the deep n-well increases somewhat the field in the depleted absorption zone. For SPADs with a diameter larger than 98.2 μm, a drop of the fall time was observed (meaning the avalanche build-up is faster) when the excess bias was increased, where the avalanche current got larger.

This was because the size of the SPADs' capacitance dominates over the pad capacitances. For the SPAD type A with 50 μm and SPAD type B with 48-μm diameter, the fall time remained approximately constant, because the pad and parasitic capacitances dominated. Concluding, the measurement shows a tendency to a lower fall time for larger SPADs.

For those avalanche transients, which could reach the breakdown level before the end of the active phase, the breakdown voltage *VBD* was determined from the breakdown level *VBL* from the relationship *VBD* = *VBL*-*VAN*. In Figure 7, the results of the breakdown voltage for several SPADs versus the excess bias are depicted. All breakdown voltages were mostly independent from the excess bias (as expected). The small variation for SPAD type A with 400-μm diameter were originated from the gating chip, which came due to the larger capacitance of the SPAD to its operation limit. The measured breakdown voltages amounted to 28.5, 27.5, 26, and ≈27 V for SPAD type A with 50, 100, 200, and 400 μm, respectively. For SPAD type B breakdown voltages of 65.2 and 64.8 V, they were determined for diameters of 48.2 and 98.2 μm, respectively.

**Figure 6.** 80 to 20% fall time of the cathode voltage of different SPADs when an avalanche occurred.

**Figure 7.** Breakdown voltage vs. excess bias.

The avalanche current transient can be calculated, if the overall node capacitance *CCat* is measured and the cathode voltage is evaluated by *CCat* × *d*VCat/dt. The capacitances *CCat* for each SPAD, which was connected with a gating chip, were measured with an Agilent 4284A precision LCR meter. For SPAD type A, the anode voltage was chosen to be as close as possible below breakdown. Due to

device restrictions, for SPAD type B, the anode voltage was set to −40 V for capacitance measurements. The results for the SPADs type A including pads and node CAT on the gating chip were 0.84, 1.12, 1.2, and 2.2 pF for the SPAD diameters of 50, 100, 200, and 400 μm, respectively. For SPAD type B, the capacitances 0.88 and 1.12 pF were measured for the diameters of 48.2 and 98.2 pF.

Figure 8 shows the resulting avalanche-current transients for SPAD type A with 200-μm diameter, and in Figure 9, the current transients for SPAD type B with 98.2 μm diameter are plotted. In Figures 8 and 9, the anode voltages VAN of the SPADs are varied, which directly alters the excess bias. It can be seen, that at the beginning of the avalanche, the current raised towards a maximum current value, while the cathode of the SPAD was discharged and the excess bias dropped. This decrease operated against a further growing of the avalanche current, because the ionization coefficients for electrons and holes decline for lower field strengths. For every excess bias, which would be held constant, there exists a static avalanche current after breakdown. This avalanche current is smaller for a lower excess bias and vanishes at the breakdown level of the SPAD, where the excess bias amounts to zero. After the point of a peak avalanche-current, the current decreased, because the cathode's voltage dropped towards the breakdown level. The peak avalanche currents for all SPADs are plotted in Figure 10 in dependence on the excess bias.

**Figure 8.** Avalanche-current transients for a SPAD type A with 200 μm diameter for different anode voltages VAN, where the avalanche starts at 0 ns.

In Figure 8, there is a considerable shift of the peak current towards larger time points from 3 ns to almost 5 ns when changing the anode voltage from −29 to −26 V. For −25 V, noise influences the current transient. In Figure 9 the shift of the peak current occurs to a less extent. This can be explained, if the range of the excess bias from 0 to 6.6 V is seen in relation to the breakdown voltage, which was lower for the 200-μm SPAD type A with 26 V than for the 98.2-μm SPAD type B with 64.8 V. Therefore, the same excess bias caused a larger increase of the electric field in the multiplication region of SPAD type A than in SPAD type B.

For SPADs type A and SPADs type B, the peak avalanche current increased with raising excess bias and larger diameter. This can be observed in the same way in Figure 6, because a larger avalanche current caused a faster discharge and hence a lower fall time. For SPAD type A with a diameter of 50 μm and SPAD type B with a diameter of 48.2 μm, the pad capacitances were dominant and therefore the delay times and avalanche currents were nearly the same in the observed range of the excess bias.

**Figure 9.** Avalanche-current transients for a SPAD type B with 98.2 μm diameter for different anode voltages VAN, where the avalanche starts at 0 ns.

**Figure 10.** Peak avalanche-current for SPADs type A and B in dependence on the excess bias.

#### **5. Conclusions**

Knowing the behavior of SPADs helps to develop more detailed models. Especially for fully integrated data receivers, it is important to optimize the circuit to a distinct SPAD.

In this paper, the avalanche actions of two types of single-photon avalanche diodes (SPADs) in 0.35-μm CMOS technology were investigated. SPAD type A with diameters of 50, 100, 200, and 400 μm was designed in standard CMOS technology including a 12-μm thick p- epi-layer. SPAD type B with diameters of 48.2 and 98.2 μm was designed in the high-voltage (HV) line of this technology. Each SPAD was wire-bonded to a clocked gating chip in standard 0.35-μm CMOS technology with a nominal supply voltage of 3.3 V. This chip controls in one clock period the charge up to maximum 6.6 V excess bias in the active phase as well as the quenching and read out in the reset phase. Measurements of the cathode voltage transients after photon hit at SPAD type A resulted in fall times (80 to 20%) of 10.2 ns for 50-μm SPAD diameter and an excess bias of 4.2 V and 3.45 ns for 200-μm SPAD diameter

and an excess bias of 4.26 V. For type B fall times of 8 ns for 48.2-μm SPAD diameter and 5.4 V excess bias as well as 2 ns for 98.2-μm SPAD diameter and 5.9 V excess bias were determined. To calculate the avalanche current transients of the SPADs out of the transients of the cathode voltage in using the relationship *CCat* × *d*VCat/dt, the whole capacitance at the cathode of the SPAD including gating chip connected were measured. This may be an alternative method to determine the current during discharging by the SPAD from a high-ohmic cathode node. It resulted in peak avalanche currents in the transients of, e.g., 1.19 mA for 100-μm SPAD type A and 1.64 mA for 98.2-μm SPAD type B for an excess bias of 5 and 4.9 V, respectively.

The breakdown voltages amounted to 28.5, 27.5, 26, and ≈27 V for SPAD type A with 50, 100, 200, and 400 μm, respectively, and 65.2 and 64.8 V for SPAD type B with diameters of 48.2 and 98.2 μm, respectively. Typically, the avalanche current rises for larger excess bias and larger diameter of the SPAD. Consequently, this has an effect on the fall time of the cathode voltage drop, when an avalanche occurs. The fall time depends on the avalanche current and typically gets smaller when the excess bias or the diameter of the SPAD is increased.

**Author Contributions:** Conceptualization, B.G., B.S., and H.Z.; methodology, B.G. and H.Z.; software, B.G.; validation, B.G. and H.Z.; formal analysis, B.G.; investigation, B.G.; resources, B.G., B.S., and H.Z.; data curation, B.G.; writing—original draft preparation, B.G.; writing—review and editing, B.G and H.Z.; visualization, B.G.; supervision, H.Z.; project administration, H.Z.; funding acquisition, H.Z. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by AUSTRIAN SCIENCE FOUNDATION (FWF), project P28335-N30.

**Acknowledgments:** The authors thank the Austrian Science Foundation (FWF) for financial funding in the project P28335-N30.

**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

#### **References**

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## *Article* **Metal-Semiconductor-Metal GeSn Photodetectors on Silicon for Short-Wave Infrared Applications**

**Soumava Ghosh 1,2,3, Kuan-Chih Lin 2, Cheng-Hsun Tsai 2, Harshvardhan Kumar 1,2, Qimiao Chen 4, Lin Zhang 4, Bongkwon Son 4, Chuan Seng Tan 4, Munho Kim 4, Bratati Mukhopadhyay 3 and Guo-En Chang 1,2,\***

Received: 25 July 2020; Accepted: 19 August 2020; Published: 21 August 2020

**Abstract:** Metal-semiconductor-metal photodetectors (MSM PDs) are effective for monolithic integration with other optical components of the photonic circuits because of the planar fabrication technique. In this article, we present the design, growth, and characterization of GeSn MSM PDs that are suitable for photonic integrated circuits. The introduction of 4% Sn in the GeSn active region also reduces the direct bandgap and shows a redshift in the optical responsivity spectra, which can extend up to 1800 nm wavelength, which means it can cover the entire telecommunication bands. The spectral responsivity increases with an increase in bias voltage caused by the high electric field, which enhances the carrier generation rate and the carrier collection efficiency. Therefore, the GeSn MSM PDs can be a suitable device for a wide range of short-wave infrared (SWIR) applications.

**Keywords:** photodetectors; GeSn alloys; silicon photonics; photonic integrated circuits

#### **1. Introduction**

The monolithic integration of photonic components and devices on a silicon (Si) platform to create electronic–photonic integrated circuits (EPICs) has attracted immense research interest over recent decades [1–5]. The key driving force is the bottleneck in the data transport rate due to the limited data rates of~10 GB/s of the current copper interconnects. Nowadays, optical and photonic interconnects operating in the fiber-optic low-loss windows (1264–1675 nm) of silica fibers have been proposed to replace metal interconnects to increase the data transport rate and reduce thermal problems. Among the various active photonic components, photodetectors (PDs) are a crucial building block. Although III-V semiconductor compounds are mostly used for high-speed photodetection, these compounds are not compatible with the Si complementary metal-oxide-semiconductor (CMOS) IC technology [6].

Alternatively, the compatibility with Si-based CMOS processing technology, monolithic integration on the same Si chip [7], and low fabrication cost make group-IV materials very attractive to develop CMOS-compatible photonic devices. However, the realization of those devices for the most important fiber-optical communication window (1310 and 1550 nm) by Si is not possible due to its bandgap of 1.12 eV [8], resulting in a cutoff wavelength of ~1100 nm. This problem can be partially circumvented by using Ge, as its direct bandgap (0.8 eV) supports 1310 nm at room temperature. However, beyond 1500 nm wavelength, the responsivity of Ge falls drastically [9]. Therefore, the entire telecommunication bands cannot be covered by Ge based photodetectors (PDs).

Over recent decades, the growth of high-quality Ge1-xSnx thin film by chemical vapor deposition (CVD) and molecular beam epitaxy (MBE) [10–12] on Si substrate via a suitable buffer has opened new avenues for group-IV photonics. The incorporation of Sn in Ge not only modifies the electronic band structure by shrinking the direct bandgap and hence red-shifting the absorption edge [13], but also beyond 8% Sn concentration the GeSn alloy acts as a direct bandgap semiconductor [14]. This noteworthy feature of GeSn has encouraged researchers to develop different types of optoelectronic devices such as Light Emitting Diodes (LEDs) [15–17], LASERs [18–20], Transistor LASERs [21,22], *p-i-n* PDs [23–25], quantum well infrared photodetectors (QWIPs) [26–28], metal-semiconductor-metal photodetectors (MSM PDs) [29–31], waveguide PDs [32], and heterojunction bipolar phototransistors (HPTs) [33–40].

MSM PDs are an alternative choice of *p-i-n* PD, consisting of back-to-back Schottky diodes. As MSM PDs do not require any doping, the effect of parasitic capacitance cannot degrade the performance [41]. Only transit-time limited delay presents; therefore, the operation speed is higher than normal *p-i-n* PDs. The simple planar fabrication of MSM PDs is suitable for monolithic integration with other components of photonic circuits [42,43]. Yasar et al. [29] and Mahmodi et al. [30] reported amorphous (8% Sn content) and crystalline GeSn MSM PD on Si substrates, respectively, but they only focused on the measurement of dark and photocurrent. Recently, the responsivity of Ge1-xSnx thin-film based MSM PD on Si has been reported [31]; however, in their work, they only demonstrated up to 1000 nm wavelength which cannot cover the modern telecommunication window (1550 nm).

In this work, we demonstrate the GeSn MSM PD on the Si platform for efficient photodetection in the entire telecommunication bands. We show the material growth and electrical and optical characterization results of the fabricated GeSn MSM PD with 4% Sn content. Furthermore, we also measured the spectral responsivity for different bias voltages and analyzed the strain electronic band structure and absorption to study the enhanced photodetection.

#### **2. Materials and Methods**

#### *2.1. Device Design*

Figure 1a exhibits the 3D schematic diagram of the designed surface-illuminated GeSn MSM PD. The layer structure consisted of a GeSn active layer as the absorption layer grown on the Si substrate via Ge virtual substrate (VS). The presence of GeSn active region helped to enhance the absorption capacity with respect to the pure Ge, due to the smaller direct bandgap and the larger absorption coefficient. The GeSn layer was passivated by the SiO2 layer. Two metal pads were deposited on the top surface of the GeSn active layer. A schematic band diagram is shown in Figure 1b.

**Figure 1.** (**a**) 3D Schematic diagram of our designed surface-illuminated GeSn metal-semiconductor-metal photodetectors (MSM PDs) on Ge buffered Si substrates. (**b**) Schematic band diagram of the GeSn MSM PD.

As light is normally incident on the device and absorbed by the GeSn active layer, electrons and holes could be generated in the GeSn active layer. In the presence of the bias voltage, the potential difference between positive and negative electrical contacts created a band bending. Under the illuminated conditions, the electron-hole pairs were generated in the active region and then swept out to the electrodes in the presence of the induced electric field. The holes and electrons accumulated in the negative and positive metal contacts, respectively, resulting in the flow of the photocurrent. The materials and dimensions of the different regions are listed in Table 1.

**Table 1.** Materials and dimensions of the GeSn metal-semiconductor-metal photodetectors (MSM PDs).

#### *2.2. Material Growth and Characterization*

The GeSn sample was grown on a 150 mm Si (001) substrate in industry compatible reduced pressure-chemical vapor deposition (RP-CVD) chamber from ASM by using Ge2H6 and SnCl4 as the precursors. Prior to the deposition of the GeSn layer, a high-quality Ge VS with a thickness of ~900 nm was deposited on the Si substrate by using Ge2H6 as the precursor at 400 ◦C followed by annealing at 850 ◦C for 30 min. After that, the temperature in the chamber was decreased to 325 ◦C, and a 180 nm thick of GeSn film was deposited on Ge VS as the active layer. The Sn concentration and strain of the GeSn layer were characterized at room temperature by X-ray diffraction reciprocal space mapping (XRDRSM) using a PANalytical X'Pert diffractometer. The microstructure of the GeSn sample was investigated by cross-sectional transmission electron microscopy (XTEM) in dark field mode (FEI Tecnai G2 F20, FEI, Waltham, MA, USA). A Pt layer was deposited on the surface of the GeSn sample to increase the conductivity for XTEM experiments.

#### *2.3. MSM PD Fabrication*

The surface-illuminated GeSn MSM PDs were fabricated using a standard CMOS-compatible process. A square mesa with a width of 1 mm was created by standard optical lithography followed by reactive ion etching (RIE) techniques. Next, a 180 nm thick SiO2 passivation layer was deposited using plasma-enhanced chemical vapor deposition (PECVD), which acts as an electric isolator between positive and negative electrodes and an anti-reflection (AR) layer to enhance the optical responsivity. After that, contact windows were incorporated using optical lithography and wet etching methods with buffered oxide etch (BOE) solution to expose the semiconductor surfaces for making the electrical contacts. Finally, 200/20 nm thick Au/Cr metal pads were deposited using an e-beam evaporator and patterned rectangular-shaped using a lift-off process.

#### *2.4. Electrical and Optical Measurements*

A Keithley 2400 SourceMeter was used to characterize the electrical properties of the fabricated GeSn MSM PDs at room temperature under dark and illuminated conditions. To characterize the spectral property of the GeSn MSM PDs, Fourier-transform infrared spectroscopy (FTIR) was used. The emitted light from the FTIR was incident normally on the devices. A Keithley 2400 SourceMeter and a 50 Ω load resistance in series were used to bias the GeSn MSM PDs. The voltage drop across the load resistance was fed back to the FTIR for the determination of photocurrents. The responsivity of the GeSn MSM PDs was then obtained by calibrating the optical responses using a commercial extended InGaAs PD (Thorlabs DET10D2, Thorlabs, Inc., Newton, NJ, USA) to determine the optical responsivity.

#### **3. Results and Discussion**

#### *3.1. Material Characterization*

Figure 2a shows a cross-sectional XTEM of the grown GeSn sample. Most defects were confined in the region near the Ge/Si interface, and no obvious defects were found near the surface of the Ge VS. The single-crystalline GeSn had a thickness of ~180 nm which was below the critical thickness for plastic relaxation, resulting in a high-quality GeSn layer. As a result, no obvious threading defects were observed in the TEM image of the GeSn layer, as shown in Figure 2a, suggesting the GeSn layer was pseudomorphic to the underlying Ge VS. The threading dislocation density (TDD) of the GeSn layer was estimated to be ~4.7 × 107 cm−2 by etch pit density (EPD) methods. Figure 2b shows a (224) XRDRSM of the grown GeSn sample, from which three peaks were observed, associated with the Si substrate, Ge VS, and GeSn layer. From the peak positions, the concentration and strain could be extracted. In addition, the Ge and GeSn peaks were aligned at the same *Q*x, suggesting that GeSn was pseudomorphically grown on Ge VS. The diagonal line through the Si peak indicates that Ge VS was almost fully relaxed (~0.1% tensile strain due to the annealing process). The Sn concentration and compressive strain of the GeSn layer were determined to be 4% and 0.57%, respectively.

**Figure 2.** (**a**) Cross-sectional transmission electron microscopy (XTEM) image of the grown GeSn/Ge/Si sample. (**b**) (224) X-ray diffraction reciprocal space mapping (XRDRSM) of the GeSn/Ge/Si sample, revealing a pseudomorphic heterostructure.

To confirm the bandgap of the grown GeSn sample, photoluminescence (PL) experiments were performed at room temperature using a 532 nm laser as the light source. The emitted PL signals from the GeSn sample were recorded uisng Fourier Transform infrared spectroscopy (FTIR) with ab LN2-cooled InSb photodetector. Figure 3 shows the measured room-temperature PL spectrum from the grown GeSn sample. Although there was signal distortion in the range of 1700–1900 nm due to the atmospheric absorption, a single emission peak was observed near 1800 nm. In addition, the emission peak was asymmetrical, confirming direct-bandgap light emission. The measured PL spectrum was modeled using the modified Gaussian function to obtain the emission peak position; the results are depicted in Figure 3. From the results, the emission peak was determined to be 1810 nm. The emission peak (*E*max) was related to the direct bandgap energy *E*Γ *g* via

$$E\_{\text{max}} = E\_{\text{g}}^{\Gamma} + \frac{kT}{2} \tag{1}$$

where *k* is the Boltzmann constant and *T* is temperature. Using the *E*max obtained from the room-temperature PL spectrum, we obtained *E*max = 0.672 eV. This value was obviously smaller than that of pure Ge (0.8 eV), showing the reduced direct bandgap of the GeSn materials due to Sn-alloying.

**Figure 3.** Room-temperature photoluminescence spectrum of the grown GeSn/Ge/Si sample. The signal distribution in the range of 1700–1900 nm is attributed to the atmospheric absorption.

#### *3.2. Dark Current, Photogenerated Current, and Gains*

Figure 4a shows the current-voltage (I-V) characteristics under dark and illumination conditions. The symmetric nature of the dark current at forward and reverse bias was observed due to the design of the symmetrical electrodes. In addition, the I-V curves were also seen to be nonlinear, this indicated the presence of the Schottky contact between the metal and GeSn layer. The increase in bias voltage increased the band to band tunneling mechanisms; therefore, the dark current increased. In addition, our fabricated GeSn-based MSM PD exhibited a lower measured value of dark current compared to the fabricated Ge-based MSM PD [44], suggesting good material quality. Under illumination with a 1510 nm laser source and an optical power of 7.7 mW, the enhancement of the current confirmed the photodetection ability of the fabricated device. Figure 4b exhibits the current gain which could be obtained from the ratio of current under illumination (*I*Illumination) and dark current (*I*dark) as a function of bias voltage. The current gain showed a constant nature with applied bias due to the constant enhancement of the current under dark and illumination.

**Figure 4.** (**a**) Measured dark current and photocurrent variation with bias voltage at *T* = 300 K. (**b**) Measured current gain (IIllumination/Idark) variation with bias voltage at *T* = 300 K.

#### *3.3. Spectral Responsivity*

To obtain the maximum spectral responsivity, a SiO2 AR layer was employed to reduce the reflection of incident light for MSM PDs. Figure 5a shows the measured reflectivity for the GeSn MSM PDs. For the GeSn MSM PDs, reflectivity showed low values of 20%–30% in the wavelength of 1400 to 2000 nm. The ripple-like features of reflectivity spectra were observed due to the interference between the layers. Figure 5b shows the measured responsivity spectra of the GeSn MSM PDs with different bias voltages at room temperature and the reflectivity spectrum. It can be seen that the responsivity of the device decreased with an increase in the wavelength. From the responsivity at a bias voltage of 1V, the cutoff-wavelength was estimated to be 1800 nm. This extended photodetection cutoff wavelength compared to 1550 nm of Ge PDs was caused by the incorporation of Sn in the active layer, indicating that the lowest direct bandgap of the GeSn active layer was *E*Γ *g*= 688 meV, which is in reasonable agreement with the PL results. The measured results suggested that the photodetection range of our devices entirely covered the telecommunication O-, E-, S-, C-, L-, and U- bands; thus, it is useful for telecommunication applications. Beyond 1800 nm, the optical responsivity was low because only inefficient indirect-gap interband absorption contributed to the optical absorption. Furthermore, the spectral responsivity of the device increased with increasing bias voltage. The enhancement ratios for GeSn MSM PDs for 1, 3, 5, and 7 V were about 84.5%, 219.6%, and 369.6%, respectively, compared to the referential PD for 1V at 1550 nm. The increase in responsivity with bias voltage could be explained based on the high electric field, which enhanced the carrier generation rate and the carrier collection efficiency. However, a high bias voltage caused more power dissipation in the device; therefore, the low bias voltage was preferred for the operation of the device. The applied voltage could be significantly reduced by shrinking the size of the GeSn MSM, while a high responsivity could be maintained. The designed device showed the peak responsivity of 40 mA/W at 1550 nm, which is much higher than that of conventional SiGe-based MSM PDs [45–47], showing the unique advantages of GeSn MSM PDs for telecommunication applications. The high spectral responsivity of GeSn MSM PD was due to the direct bandgap nature, high absorption coefficient, and high carrier mobility of GeSn alloy in the active region. In addition, it was also observed that the optical responsivity beyond 1800 nm also significantly increased with increasing applied bias voltage. This observation could be attributed to the Joule heating effect that enhanced lattice vibrations (phonons), resulting in enhanced indirect-gap absorption. Further enhancement in optical responsivity is possible by increasing the Sn content to further increase the absorption coefficient and/or optimizing the device structure to increase the carrier collection efficiency to enable more sensitive short-wave infrared (SWIR) photodetection.

**Figure 5.** (**a**) Measured reflectivity spectra for the GeSn MSM PDs. (**b**) Measured responsivity spectra of the GeSn MSM PDs with different bias voltages at T = 300 K.

#### *3.4. Numerical Analysis*

The incorporation of Sn into Ge led to the extension of the absorption edge to the higher wavelength. This was because of the reduction in the direct bandgap of the GeSn alloy with Sn alloying. With an increase in Sn concentration, the Γ-conduction band shifted downward mainly due to the negative bandgap of α − *Sn* and the bowing effect of the direct bandgap. However, the heavy-hole (HH) band light-hole (LH) band in the valence band shifted upwards with an increase in Sn concentration. Therefore, direct-gap interband transitions contributed to the increased absorption spectra with Sn alloying owing to the increased density-of-states (DOS). To obtain a clear visualization of the effect of Sn concentration on the absorption coefficient, we theoretically calculated the strained electronic band structures using the deformation potential theory [42,48]. Then, the direct band absorption coefficient was calculated by using the Fermi's golden rule with consideration of a Lorentzian lineshape function [25,49],

$$a(h\omega) = \frac{\pi h e^2}{n \varepsilon \varepsilon\_0 m\_0^2 h \omega} \sum\_m \int \frac{2d\mathbf{k}}{\left(2\pi\right)^3} \left| \not\mathbf{\dot{\varepsilon}} \cdot p\_{CV} \right|^2 \times \frac{\gamma/(2\pi)}{\left[E\_{C\Gamma}(\mathbf{k}) - E\_m(\mathbf{k}) - h\omega\right]^2 + (\gamma/2)^2} \tag{2}$$

where nr is the refractive index; c is the velocity of light in free space; e is the electronic charge; *h*¯ is the reduced Planck's constant; m0 is the rest mass of an electron; ε0 is the free space permittivity; ω is the angular frequency of incident light; *e*ˆ · *pCV* 2 is the momentum matrix; γ is the full-width-at-half-maximum (FWHM) of the Lorentzian lineshape, whose value 15 meV was used in this study; *E*CΓ (**k**) and *E*m(**k**) are the electron and hole energy in the Γ-valley conduction band (CB) and valance band (VB), respectively, which were calculated using a multi-band k·p method by considering the strain effect [33,42]. The summation over m represents all interband transitions from the VB (HH and LH bands) to the direct CB. For the indirect-band absorption, because the probability of the indirect-gap transition was much smaller than that of the direct-gap transition, we neglected the indirect-band absorption effect in this study. The parameters for GeSn alloys could be evaluated from the linear interpolation of the Ge and Sn, as shown in Table 2. The direct bandgap bowing parameter of GeSn alloy was *b*Γ = 2.42 eV [33].

**Table 2.** Parameters for Ge and Sn at T = 300 K.

Figure 6a shows a schematic band diagram of pseudomorphic Ge0.96Sn0.04 on Ge with respect to wavenumber (k)at T = 300 K. The pseudomorphic growth of GeSn with 4% Sn on Ge VS exerted a compressive strain (~0.57%) which split the degeneracy of the HH and the LH bands. It is clearly shown from Figure 6a that the HH band shifted above the LH band, and their separation energy became larger with increasing Sn concentration due to the larger compressive strain. Therefore, two possible direct interband transitions contributed to the optical absorption: the direct transition from the HH band to the Γ-conduction band (*HH* → Γ*c*) and from the LH band to the Γ-conduction band (*LH* → Γ*c*). The calculated transition energies for the *HH* → Γ*c* and *LH* → Γ*c* transitions were 697 and 749 meV, respectively, which are in good agreement with the experimental results. Figure 6b shows the calculated absorption spectra of pure Ge and pseudomorphic Ge0.96Sn0.04 on Ge at T = 300 K. The overall absorption coefficient was the superposition of the direct interband transitions: *HH* → Γ*c* and *LH* → Γ*c* ; therefore, a cusp-like feature was shown in the calculated absorption spectra. The calculated result shows that the absorption coefficient decreased with an increasing wavelength. The calculated result also shows that the optical cutoff wavelength for GeSn alloy shifted towards the longer wavelength, which considerably increased the photodetection range of the proposed device. The calculated result also shows that the absorption coefficient increased with increasing Sn concentration. For Ge0.96Sn0.04 on Ge, the absorption coefficient increased by ∼3.3 times more than pure Ge at 1550 nm. This behavior can be explained based on the redshift in the absorption edges with increasing Sn concentration due to the shrinkage of the bandgap energies from the Sn alloying. Further increases in the Sn content can redshift the direct-gap absorption edge and thus extend the photodetection range of the GeSn MSM PDs for important short-wave infrared applications.

**Figure 6.** (**a**) Band structure of pseudomorphic GeSn with 4% Sn content on Ge in which heavy-hole (HH) and band light-hole (LH) split due to compressive strain. (**b**) Calculated absorption spectra for pure Ge and GeSn with 4% Sn composition pseudomorphically grown on Ge VS at T = 300 K.

#### **4. Conclusions**

In conclusion, we have demonstrated a GeSn MSM PD monolithically grown on Ge buffered Si substrates. The GeSn active layer was grown on a silicon substrate with good material quality as the optical absorber, which had a lower bandgap than that of pure Ge, extending the photodetection region. The responsivity experiments show enhanced spectral responsivity and low dark current compared to the existing SiGe-based MSM PDs. Furthermore, the responsivity increases with an increase in bias voltage due to the enhanced electric field. With the extended photodetection range, planar structures and CMOS compatibility, Si-based short-wave infrared GeSn PDs are promising for a wide range of applications.

**Author Contributions:** Conceptualization, G.-E.C.; methodology, S.G., K.-C.L., C.-H.T., Q.C, L.Z., and B.S.; formal analysis, S.G., H.K., G.-E.C., B.M., K.-C.L., C.S.T., Q.C, L.Z., M.K., and B.S.; writing—original draft preparation, S.G., Q.C.; writing—review and editing, G.-E.C., H.K., C.S.T., and B.M.; supervision, G.-E.C. All authors have read and agreed to the published version of the manuscript.

**Funding:** This work at CCU was funded by the Ministry of Science and Technology, Taiwan, grant numbers MOST 108-2221-E-194 -055 and MOST 109-2636-E-194 -002, and the Ministry of Education of Taiwan. The work at NTU was supported by the National Research Foundation, Singapore, under its Competitive Research Program (CRP Award NRF-CRP19-2017-01).

**Acknowledgments:** The authors would like to thank Yue-Tong Jheng at CCU for providing assistance in the experiments.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## *Article* **Characterization of Impact Ionization Coe**ffi**cient of ZnO Based on a p-Si**/**i-ZnO**/**n-AZO Avalanche Photodiode**

#### **Gaoming Li 1,2,\*, Xiaolong Zhao 1, Xiangwei Jia 1, Shuangqing Li 1 and Yongning He 1,\***

Received: 9 July 2020; Accepted: 29 July 2020; Published: 30 July 2020

**Abstract:** The avalanche photodiode is a highly sensitive photon detector with wide applications in optical communication and single photon detection. ZnO is a promising wide band gap material to realize a UV avalanche photodiode (APD). However, the lack of p-type doping, the strong self-compensation effect, and the scarcity of data on the ionization coefficients restrain the development and application of ZnO APD. Furthermore, ZnO APD has been seldom reported before. In this work, we employed a p-Si/i-ZnO/n-AZO structure to successfully realize electron avalanche multiplication. Based on this structure, we investigated the band structure, field profile, Current–Voltage (I-V) characteristics, and avalanche gain. To examine the influence of the width of the i-ZnO layer on the performance, we changed the i-ZnO layer thickness to 250, 500, and 750 nm. The measured breakdown voltages agree well with the corresponding threshold electric field strengths that we calculated. The agreement between the experimental data and calculated results supports our analysis. Finally, we provide data on the impact ionization coefficients of electrons for ZnO along the (001) direction, which is of great significance in designing high-performance low excess noise ZnO APD. Our work lays a foundation to realize a high-performance ZnO-based avalanche device.

**Keywords:** p-Si/i-ZnO/n-AZO; avalanche photodiode (APD); impact ionization coefficients

#### **1. Introduction**

The avalanche photodiode (APD) has a wide application in photoelectric conversion [1], especially in the areas of optical communication [2–5], imaging [6–8], and single photon detection [9–11], because it has a large avalanche gain that enables the high sensitivity [12,13]. When the detection spectral range enters the UV region, we need to utilize wide band gap materials as the absorption layer. Therefore, 4H-SiC [14–19], GaN [20–27]-based UV APDs have been demonstrated and investigated in recent years. ZnO is also an attractive wide band gap semiconductor that has a lot of advantages such as high exciton binding energy, direct band gap, low cost, ease of fabrication, and environmental friendliness [28–30]. Based on a simulation work, for ZnO, the ratio of the impact ionization coefficient of holes to that of electrons is rather low [31]. This has a very appealing merit that may be fully exploited to achieve high-performance, low excess noise APD devices.

Recently, some works devoted to studying the impact of ionization multiplication in ZnO/MgO [32–34] and TiO2/AlOx [35] material systems have been reported. These works are mainly based on the metal–insulator–semiconductor–insulator–metal structure. The highest electric field occurred in the insulator layer, and an avalanche gain was observed. However, this structure has two issues in our opinion. Firstly, the high electric field is primarily in the insulator area, and the field in the semiconductor layer is relatively weak, so the separation of photo carriers and the transport of these photo carriers may have a low efficiency. Secondly, the insulator has a very large band gap; then, the threshold energy needed for impact ionization is very large. Moreover, the thickness of several tens of nanometers may be too short to accelerate the initial injected carriers. So, a traditional pin structure without these issues may be more favorable. Considering the big challenge of stable and effective p-type doping for ZnO [36–38], we turned to Si for a p-type material, owing to the compatibility to the highly developed CMOS technology and the availability of a high-quality Si wafer. Although the p-Si/n-ZnO heterostructure may be exhaustively investigated [39–43], few works have been published up to date that demonstrate the impact of ionization multiplication base on this structure. The quality of the ZnO layer and the interface between Si and ZnO are the primary constraints.

In this paper, we fabricated the p-Si/i-ZnO/n-AZO structure and realized electron avalanche multiplication in the poly-crystalline i-ZnO layer. We systematically investigated this structure with an emphasis on the avalanche multiplication process. The band structure, field profile, current voltage characteristics, threshold breakdown electric field, avalanche gain, and impact ionization coefficient were comprehensively discussed. We also investigated the influence of the width of the i-ZnO layer. The major contribution from this work is that we provide the impact ionization coefficient of electrons for ZnO through triggering an electron avalanche multiplication by visible light with a wavelength of 532 nm. Our work indicates that ZnO still holds promise to realize a high-performance APD device, and it may renew the research interest in ZnO for the application of APD.

#### **2. Materials and Methods**

The p-Si/i-ZnO/n-AZO structure was fabricated through the process shown in Figure 1. At first, we cleansed the p+ Si wafer with acetone, ethanol, and deionized water successively; the whole cleansing process was with the help of ultrasonic oscillation. Then, we used Buffered Oxide Etch (BOE) to remove the native oxide layer on the surface of the wafer. Magnetron sputtering was exploited to deposit poly-crystalline ZnO and Al-doped ZnO (AZO) on the Si wafer in turn. The thickness and doping level of each layer are indicated in Figure 1. To investigate the dependence of performance on the width of the multiplication layer, which is the thickness of the i-ZnO layer, we tuned the thickness of the ZnO layer to 250, 500, and 750 nm, respectively. We also fabricated p-Si/n-AZO and p-Si/i-ZnO structures as references and to characterize the doping density based on a simpler pn junction structure. The aluminum electrodes were evaporated on AZO and Si, and the pattern was formed through photolithography. Since the AZO and Si are both heavily doped, Al electrodes can realize Ohmic contact with both layers.

**Figure 1.** Fabrication process and structural details of the p-Si/i-ZnO/n-AZO heterostructure.

We utilized Capacitance–Voltage (C-V) measurement to characterize the density of doping impurities for pn junctions. To eliminate the influence of interface states as much as possible, a high frequency of 1 MHz was chosen. A source measure unit was employed to do Current–Voltage (I-V) analysis for the pin structures. To probe the avalanche gain, we used a laser diode as the light source, which provides a strong illumination with the wavelength of 532 nm. We used an attenuator to reduce the light intensity, because a relatively weak light is enough to inject some charge carriers and initiate an impact ionization multiplication process.

#### **3. Results and Discussion**

#### *3.1. Heterostructure of Si and ZnO*

At the very beginning, we want to verify that the ohmic contacts between Al electrodes and p-Si, as well as those between Al electrodes and n-AZO, were successfully formed. We fabricated two Al electrodes with a size of 10 × 100 μm on 500 nm-thick p-Si and 500 nm-thick n-AZO films, respectively. These p-Si and n-AZO films have an identical doping concentration to those used in the p-Si/i-ZnO/n-AZO structure. The distance between electrodes is 1 cm. The I-V curves for these two setups are shown in Figure 2, from which we can see good linearity for both I-V curves. Therefore, we confirmed that ohmic contacts were formed.

**Figure 2.** The Current–Voltage (I-V) curves for two Al electrodes on p-Si and n-AZO, respectively.

As a result of lacking of durable, stable, and highly effective p-type doping for ZnO, a lot of applications for ZnO based on the pn junction need another p-type material to form a heterostructure. Silicon is a very mature and widely used semiconductor material. Its planar fabrication process, for example CMOS technology, is highly developed. Compatibility with CMOS technology and the availability of high-quality Si wafer are the benefits of choosing Si as the p-type material. Besides, the lattice mismatch between Si and ZnO is tolerable. Based on the hexagonal ZnO (a = 3.252 × 10−10 m) and cubic Si (a = 5.43 × 10−10 m) lattice parameters from the literature, we can calculate the mismatch, which is 40% in this case [28]. To alleviate the strain caused by the lattice mismatch and improve the crystalline quality of ZnO near the interface, annealing at 600 degrees Celsius for 30 min in the Ar ambient was employed after the growth of ZnO film on Si. We successfully fabricated the p-Si/i-ZnO/n-AZO structure to realize the avalanche multiplication of electrons in ZnO.

The band diagram of the p-Si/i-ZnO/n-AZO structure is shown in Figure 3. The band offset, especially for the conduction band, is crucial for analyzing the electron transport. Moreover, the bending degree of the band due to the built-in potential and applied voltage bias is also responsible for the modulation of electron transport. The position of the Fermi level in the band gap is related with the doping density, which is deduced from the C-V measurement. For p-Si substrate, the doping

density NA = 5 × 1017 cm−3, and it can be assumed that the doping impurities are all ionized at room temperature. Therefore, based on the following equation:

$$\delta\_1 = E\_{\rm F,Si} - E\_{\rm v,Si} = kT \ln(N\_{\rm v,Si}/N\_{\rm A}) \tag{1}$$

where *E*F,Si and *E*v,Si are the Fermi level and valence band maximum (VBM) of the Si band, respectively, *k* is the Boltzmann constant, *T* is the temperature, and *N*v,Si is the effective density states in the valence band of Si, which is 1.1 × 1019 cm−3 [44]. Then, we can derive the energy difference between the Fermi level and VBM in Si, which is 80.4 meV.

**Figure 3.** The band diagram of the p-Si/i-ZnO/n-AZO structure.

In a similar manner, we can deduce the energy difference between the Fermi level and conduction band minimum (CBM) in ZnO and AZO based on the following equations:

$$
\delta\_{\rm 2} = E\_{\rm c,ZnO} - E\_{\rm F,ZnO} = kT \ln(N\_{\rm c,ZnO}/N\_{\rm D1}) \tag{2}
$$

$$
\delta\_3 = E\_{\rm c,ZnO} - E\_{\rm F,AZO} = kT \ln(N\_{\rm c,ZnO}/N\_{\rm D2}) \tag{3}
$$

where *E*F,ZnO and *E*c,ZnO, *E*F,AZO and *E*c,AZO are the Fermi level and CBM for the ZnO and AZO band, respectively, *N*c,ZnO is the effective density state in the conduction band of ZnO, which is 3.4 × 1018 cm−3 [44], and *N*D1 and *N*D2 are the density of ionized impurities of ZnO and AZO, respectively. The values we used here were extracted from C-V measurement, which are 4 × 1013 and 2.4 × 1016 cm−3 for ZnO and AZO, respectively. The energy differences in the neutral regions of ZnO (δ2) and AZO (δ3) are 295 and 129 meV, respectively. The impurity density of unintentionally doped intrinsic ZnO is determined by C-V measurement. These impurities in ZnO are native point defects such as oxygen vacancy and interstitial zinc, which serve as donors. These native defects are the origin of the self-compensation effect and the reason why p-type doping for ZnO is very challenging.

The conduction band offset ΔEc is determined by the difference of the electron affinity energy between Si and ZnO, which is defined as the energy measured from the bottom of the conduction band to the vacuum level. Based on the data in the literature [44,45], the electron affinity energy values for Si and ZnO are 4.05 and 4.35 eV, respectively. Therefore,

$$
\Delta E\_{\rm \bf \bf} = \chi\_{\rm Z \rm r} \rm D\_{\rm Si} - \chi\_{\rm Si} = 0.3 \,\text{eV}.\tag{4}
$$

If we consider the influence of interface states, the situation could be rather complicated. Firstly, the Fermi level will be pinned by the interface states, and the bending degree of the energy band near the interface will be changed. To simplify the effect of interface, one could add a correction term to Δ*E*c, which is determined by the density and position in the band gap for the interface states. Here, we did not consider the influence of interface states when calculating the band offset. It is well known that the

band gaps for Si and ZnO are 1.12 and 3.37 eV, respectively. We can calculate the valence band offset Δ*E*v by the equation:

$$
\Delta E\_{\rm v} = E\_{\rm g.ZnO} - E\_{\rm g.Si} + (\chi\_{\rm ZnO} - \chi\_{\rm Si}) = 2.55 \,\text{eV}.\tag{5}
$$

Since the doping density of Si is about 4 orders of magnitude greater than that of ZnO, the width of the depletion layer in ZnO is much greater such that the whole region of ZnO is depleted. We will discuss the width of the depletion layer in ZnO in detail afterwards. Thus, the pin diode we fabricated belongs to the punch-through type, which has a nearly constant high field in the multiplication layer. This field profile is very suitable for avalanche multiplication.

#### *3.2. C-V Measurement and Field Profile*

The C-V measurement is a common method to acquire the doping density and built-in potential in the semiconductor field. For the ideal pn structure, we applied a reverse bias without consideration of interface states, and the capacitance of a pn junction is mainly determined by the variation of charge in the depletion layer with the applied voltage. It is easy to deduce the equation as follows:

$$\left|\frac{d1/\mathcal{C}^2}{dV}\right| = \frac{2(\varepsilon\_1 N\_\Lambda + \varepsilon\_2 N\_\mathcal{D})}{q\varepsilon\_1 \varepsilon\_2 N\_\mathcal{D} N\_\Lambda} \tag{6}$$

where *N*A and *N*D are the doping density of the p-type and n-type layer, respectively, ε1 and ε2 are the relative permittivity of the n-type and p-type materials, respectively, and q is the electron charge. According to Equation (6), if we plot the 1/C2-V curve, we could derive the doping concentration from the slope.

To exclude the influence of interface states, a high-frequency AC field is employed. From Figures 4a and 5a, we can see that the capacitance goes down with increasing frequency, which indicates that the interface states contribute to the capacitance less at higher frequency. The reason is that the charging process through interface states is too slow to catch up with the fast varying AC field. To be more specific, the electrons and holes can be transferred between the interface states and the conduction band and valence band, respectively, depending on the position of the Fermi level. Generally speaking, the interface states that are under the Fermi level are always occupied by electrons. When the applied voltage is changing, the Fermi level will move accordingly. Then, the electric charge will flow into or out of the interface states; thus, in this case, the interfaces states behave similar to a capacitor. This charging or discharging process is usually very slow, so when the frequency of the AC voltage increases, the contribution to total capacitance from interface states gets lower. This interpretation explains the capacitance dependence on frequency well. The capacitance decreases with the increasing reverse voltage due to the increase of the width of the depletion layer. From Figures 4 and 5, based on the slope of curve that we showed using a black straight line, we derived the doping densities of i-ZnO and n-AZO, which are 4 × 1013 and 2.4 × 1016 cm−3, respectively. As we can see either in Figure 4 or Figure 5, the slope of the curve for 1 MHz is not a single value, because the curve is not perfect straight line. Therefore, we took the average for the incline angles corresponding to the slope within the voltage range. The tangent of the average incline angle is the slope we extracted. The C-V measurement results are shown in Figure 6, from which we can deduce that the capacitance of the pin structure is mainly determined by the variation of the width of the depletion layer in AZO with the voltages.

When the doping concentration of each layer is determined, we can calculate the electric field profile based on Poisson's equation as follows:

$$\begin{cases} \frac{dE}{dx} = \frac{qN\_\Lambda}{\varepsilon\_2}, \text{ in depletion layer of Si} \\ \frac{dE}{dx} = \frac{qN\_\mathrm{D(1,2)}}{\varepsilon\_1}, \text{ in depletion layer of ZnO or AZO} \end{cases} \tag{7}$$

**Figure 4.** (**a**) Capacitance–voltage measurement data for the p-Si/i-ZnO junction; (**b**) 1/C2–V curve for p-Si/i-ZnO junction.

**Figure 5.** (**a**) Capacitance–voltage measurement data for p-Si/n-AZO junction; (**b**) 1/C2–V curve for p-Si/n-AZO junction.

**Figure 6.** Capacitance–voltage measurement results measured with 1 MHz AC signal for p-Si/i-ZnO/n-AZO structure.

The calculated electric field profile for the different impurity concentrations of the i-ZnO layer is shown in Figure 7. The relative permittivities for Si (ε2) and ZnO (ε1) that we used in the calculation are 11.9 and 9.0, respectively [44]. The variation of doping density can alter the electric field profile. Before we do the calculation, we need to verify the assumption that the i-ZnO layer is completely depleted. It can be proved by the contradiction. If the i-ZnO layer is not fully depleted, then the width of the depletion layer should be less than the thickness of the i-ZnO layer. We can calculate the width XD in this case by the following equation:

$$X\_{\rm D} = \left[\frac{2\varepsilon\_{\rm Si}\varepsilon\_{\rm ZnO}(N\_{\rm A} + N\_{\rm D1})^2 V\_{\rm D}}{qN\_{\rm D1}N\_{\rm A}(\varepsilon\_{\rm Si}N\_{\rm A} + \varepsilon\_{\rm ZnO}N\_{\rm D1})}\right]^{1/2} \approx \left[\frac{2\varepsilon\_{\rm ZnO}V\_{\rm D}}{qN\_{\rm D1}}\right]^{1/2}, \text{ For } N\_{\rm A} \gg N\_{\rm D1} \tag{8}$$

where *V*D is the built-in potential for the Si/ZnO junction, which is 0.61 eV for our sample. This built-in potential was determined by the energy difference between the Fermi levels of Si and ZnO before they contact to form a heterojunction. The detailed process is outlined in the following description. From the common vacuum level, we determined the position of the CBM for Si and ZnO based on their electron affinity energy, respectively. Then, we can determine the position of the Fermi level with respect to the CBM for both of them by their impurity concentration. Finally, we calculated the difference between the Fermi levels, which is the built-in potential. Compared with the literature, this value is comparable to their results for a similar situation [46]. Based on Equation (8), we derived the width of the depletion layer, which is 1.28 μm. It is much greater than the maximum value of the i-ZnO layer, which is 750 nm. Therefore, we verified the assumption that the i-ZnO layer is fully depleted.

**Figure 7.** Field profile p-Si/i-ZnO/n-AZO structure for different impurity concentrations of i-ZnO layer.

The electric field profile in the depletion layer can be described by the following equations, which are the integration of Equation (7):

$$\begin{cases} E(\mathbf{x}) = \frac{qN\_{\rm A}}{\ell\_{\rm Si}^{\rm Si}} (\mathbf{x} + \mathcal{W}\_{\rm P}), \ -\mathcal{W}\_{\rm P} \le \mathbf{x} \le \mathbf{0} \text{ in } \mathbf{p} - \text{Si} \\\ E(\mathbf{x}) = \frac{qN\_{\rm D1}}{\ell\_{\rm ZnO}} (\mathcal{W}\_{\rm i} - \mathbf{x}) + \mathcal{C}\_{\rm I}, \ 0 \le \mathbf{x} \le \mathcal{W}\_{\rm I} \text{ in } \mathbf{i} - \text{ZnO} \\\ E(\mathbf{x}) = \mathcal{C}\_{\rm I} - \frac{qN\_{\rm D2}}{\ell\_{\rm ZnO}} (\mathbf{x} - \mathcal{W}\_{\rm i}), \ \mathcal{W}\_{\rm i} \le \mathbf{x} \le \mathcal{W}\_{\rm R} \text{ in } \mathbf{n} - \text{AZO} \end{cases} \tag{9}$$

where *W*p, *W*i, and *W*n are the width of the depletion layer for p-Si, i-ZnO, and n-AZO, respectively, and C1 is a constant that can be determined by the boundary conditions. The calculated field profile for different thicknesses of the i-ZnO layer is shown in Figure 8. The greatest field strength occurs at *x* = 0, which is the interface between Si and ZnO; then, the field gradually decreases with the slope, which is proportional to the impurity density of the i-ZnO layer. If the strength of the field in the multiplication layer remains very high—in other words, it decreases very slowly—it is very suitable to realize a large gain. The smaller the impurity density of i-ZnO, the more suitable the electric field profile that we can generate. Given a constant reverse bias, the greater the width of i-ZnO, the smaller the maximum field strength that we can get. Since the doping density of Si and AZO are very high, if compared with the impurity density of ZnO, the depletion layers in Si and AZO under zero voltage bias are quite narrow. From Figures 9 and 10, we can see the variation of the depletion layer width in Si and AZO with reverse voltages. The width of the depletion layer in Si is in the range of several tens of nanometers, although the voltage reaches 40 V. In contrast, the width of the depletion layer in AZO increases faster with voltages; it can be several hundred nanometers, which is comparable to that in ZnO when the voltage goes high. However, the electric field strength in AZO falls much faster than that in ZnO, and the descending rate is determined by the impurity concentration. Therefore, the charge carriers transporting in these regions cannot initiate an impact ionization process, for they cannot gain enough energy from the electric field in such a short accelerating distance. It is apparent that a proper width of the multiplication layer is crucial to the ionization process, because if this value

is too large, the field strength is not strong enough to accelerate the carrier to a critical velocity that can realize the impact ionization. On the contrary, if this value is too small, the accelerating distance would be too short to initiate an ionization multiplication. It is sound that we assume that the multiplication process solely happens in the i-ZnO when we simultaneously consider the electric field strength and acceleration distance.

**Figure 8.** Field profile of the p-Si/i-ZnO/n-AZO structure for different widths of the i-ZnO layer.

**Figure 9.** Width of the depletion layer in p-Si for the p-Si/i-ZnO/n-AZO structure under different voltages.

**Figure 10.** Width of the depletion layer in n-AZO for the p-Si/i-ZnO/n-AZO structure under different voltages.

#### *3.3. Current–Voltage Characteristics and Influence of Width of i-ZnO Layer*

The strong electric field in the depletion layer is highly needed for ionization multiplication, so APD always works under reverse voltage bias. The current–voltage curve of a p-Si/i-ZnO/n-AZO structure is shown in Figure 11. The thickness for the i-ZnO layer is 250 nm. It has typical I-V

characteristics for an avalanche photodiode (APD). The reverse voltage range can be broken into three regions. Within the first region, APD is in a simple diode mode without a gain or with a unit gain. In this region, the current is equal to the reverse saturation current. In the second region, APD works in a linear mode, in which the photocurrent is proportional to the light intensity, and the photocurrent decays rapidly after the light is off. The third region is related to the Geiger mode, in which an avalanche multiplication process is generated violently such that the generation rate of carriers is greater than the collection rate of the electrodes. So, we need a quenching mechanism to cease this multiplication process after the light is off. The boundary between the linear mode and Geiger mode is the critical voltage, which is called the avalanche breakdown voltage.

**Figure 11.** The typical I-V characteristics for our p-Si/i-ZnO/n-AZO avalanche photodiode; the green dashed line indicates the photo current, and the red solid line represents the dark current.

It is easy to deduce that the threshold energy *E*i demanded for impact ionization is highly related to the band structure of the semiconductor, which serves as a multiplication layer. Regardless of whether there are two parabolic bands, three parabolic bands, or non-parabolic bands, *E*i is comparable with the band gap *E*g. As the well-known 3/2-band-gap rule indicates, if the effective mass for electrons and holes are equal, the threshold energy *E*i is equal to 3*E*g/2 [12]. Since the effective mass of the holes in ZnO is lacking, we took the assumption that the effective mass of the holes is equal to that of the electrons. Then, if we make a sound guess for the mean free path of the carrier, which is defined as the distance that the carrier moves between two collisions with phonons, we could roughly derive the threshold electric field strength required for impact ionization multiplication. The mean free path can be expressed as the product of the carrier velocity and the scattering time. The scattering time is the reciprocal of the scattering rate. Based on the aforementioned analysis, the threshold field strength can be described as follows:

$$E\_{\rm BR} = \frac{\left(3m^\*E\_{\rm g}\right)^{1/2} \cdot R\left(3E\_{\rm g}/2\right)}{q} \tag{10}$$

where *m*\* is the effective mass of the charge carrier, which is equal to 0.27 *m*0 for ZnO [44]. *m*0 is the electron rest mass. *q* is the electron charge. R(3*E*g/2) is the scattering rate for the carrier with the energy, which is equal to 3*E*g/2. We substitute the quantities in Equation (10) with realistic values; then, we acquire that *E*BR is equal to 4.2 × 105 V/cm. The R(3*E*g/2) we used is 1.1 × 1013 s−1 from the reference [31].

We calculated the maximum electric field strength at various reverse voltages at the interface between ZnO and Si for different i-ZnO layer thicknesses. The calculated results are shown in Figure 12. As we can see, given the same reverse voltage applied, the thicker the i-ZnO layer, the smaller the maximum electric field we can get. The reverse voltages corresponding to *E*BR are avalanche breakdown voltages; for the i-ZnO layer with different thicknesses, they are 25 V (250 nm), 35 V (500 nm), and 45 V (750 nm), respectively. Compared with the I-V curves for the p-Si/i-ZnO/n-AZO APD, the experimental results are smaller than the calculated results. Possible reasons for this discrepancy could be that the scattering rate we used is greater than that in the realistic situation, and the assumption and approximation may bring some errors.

**Figure 12.** The maximum electric field strength at various reverse voltages.

#### *3.4. Avalanche Gain and Ionization Coe*ffi*cient*

We utilized a laser diode with wavelength of 532 nm as the light source to investigate the photo response and avalanche gain of our p-Si/i-ZnO/n-AZO APD. Although the light firstly shines on the AZO side, which is on the top of the device, photocarriers will be generated in the p-Si, which is the bottom layer of the device. The reason is that the wavelength of 532 nm is much longer than the cutoff wavelength of ZnO and AZO; thus, this green light will pass through the ZnO and AZO layer without much loss. The photocarrier injection happens in the p-Si layer, and the minority carrier electrons will drift to the ZnO layer under the strong built-in electric field. So, these photogenerated electrons are the initial electrons that will be accelerated in a high-field ZnO layer and triggered the impact ionization multiplication. Based on this analysis, we can draw two important conclusions: first, the impact ionization multiplication happens in the i-ZnO layer; second, this avalanche multiplication is an electron-dominant process, and the contribution from holes can be neglected. Moreover, from the calculated results in the literature [31], we know that for ZnO, the ionization coefficient of the electrons (α) is much greater than that of the holes (β). This also supports the conclusion that we can omit the influence of the holes and solely consider the electrons' impact ionization.

The I-V curves of the APD under illumination are shown in Figure 13. The avalanche gain can represent the degree to which the photocurrent is magnified through impact ionization multiplication. The definition is based on the following equation:

$$M = \frac{I\_{\rm MP} - I\_{\rm MD}}{I\_{\rm P} - I\_{\rm D}} \tag{11}$$

where *I*P and *I*D are the photocurrent and dark current without multiplication, respectively, and *I*MP and *I*MD are the photocurrent and dark current with avalanche multiplication. It is apparent that the ionization multiplication is highly dependent on the strength of electric field; thus, the avalanche gain is a function of reverse voltage. We calculated the avalanche gain using Equation (11). The result is shown in Figure 14. When we calculated the gain, we assumed that the gain is a unit at 5 V and used the photocurrent and dark current at 5 V for the denominator of the right part of Equation (11). From the relationship between the avalanche gain and the electric field strength, we can estimate that the breakdown voltage is about 3.3 × 105 V/cm.

**Figure 13.** The I-V characteristics of p-Si/i-ZnO/n-AZO APD in dark and under illumination.

**Figure 14.** The avalanche gain at various reverse voltages.

Ionization coefficients are crucial parameters that mean how many electrons and holes are created when the initial carrier travels along the electric field for a unit distance. They are related with the performance of APD such as the multiplication gain, excess noise, threshold energy, and gain–bandwidth product. When one designs a high-performance APD, the ionization coefficient is an important factor that should always be kept in mind. In a pin structure, the ionization coefficients are independent of position; therefore, the avalanche gain can be expressed using ionization coefficients as the following equation shows:

$$M = \frac{(1 - \beta/\alpha) \exp[a\mathcal{W}\_\mathcal{D}(1 - \beta/\alpha)]}{1 - (\beta/\alpha) \exp[a\mathcal{W}\_\mathcal{D}(1 - \beta/\alpha)]} \approx \exp(a\mathcal{W}\_\mathcal{D}), \text{ if } a \gg \beta \tag{12}$$

where *W*D is the width of the multiplication layer. According to Equation (12), we calculated the ionization coefficient of electron (α) for APD with i-ZnO layers with different thicknesses. The calculation process is as follows. We firstly calculated the avalanche gain under various voltages;

then, based on the relationship between the ionization coefficient and avalanche gain, we derived the ionization coefficient under these voltages. In an ideal situation, the avalanche gain and ionization coefficient should have been independent of the specific structural parameters of the punch-through pin structure. They are mainly determined by what material is utilized as a multiplication layer. However, owing to the nonuniformity of the ZnO layer, the avalanche gain and ionization coefficient under a given electric field extracted from the I-V curves exhibit a little discrepancy for different ZnO layer thicknesses. Therefore, we averaged the ionization coefficients derived from the pin structure with different ZnO layer thicknesses to minimize the extraction error. The results are shown in Figure 15. It should be noted that these ionization coefficients correspond to the case in which the electric field is along the (001) direction of ZnO, because our ZnO sample is highly c-axis oriented and the electric field is along the c-axis, which is the (001) direction. The results represented herein show that p-Si/i-ZnO/n-AZO is a promising structure to realize high-performance APD.

**Figure 15.** The impact ionization coefficients of electrons.

#### **4. Conclusions**

In this paper, we have fabricated a p-Si/i-ZnO/n-AZO structure and realized avalanche multiplication in the poly-crystalline i-ZnO layer based on this structure. The band structure of this p-Si/i-ZnO/n-AZO heterostructure was systematically investigated. Based on C-V measurement, the ionized impurity density of the unintentionally doped ZnO layer is 4 × 1013 cm−3, while the doping density of the AZO layer is 2.4 × 1016 cm−3. This i-layer with rather low impurity density is very important for a suitable field profile and ionization multiplication. We calculated the field profile for our p-Si/i-ZnO/n-AZO structure and investigated how the impurity density of the i-ZnO layer and the width of the i-ZnO layer affect the field profile. We chose three values, which are 250, 500, and 750 nm for the width of the i-ZnO layer. The calculated results show that the p-Si/i-ZnO/n-AZO structure of the parameters mentioned before is a punch-through type pin APD, which holds a very high field in the i layer. According to the field profile and width of the depletion layer in AZO and Si, an avalanche multiplication process only happened in the i-ZnO layer. We proposed an equation that roughly estimates the threshold electric field strength for the avalanche breakdown and breakdown voltage for different i-ZnO layer widths. The threshold electric field strength for avalanche breakdown for our pin structure is 3.3 × 105 V/cm. To initiate the electron dominant avalanche ionization multiplication

process in the i-ZnO layer and derive the ionization coefficient of electrons, we used 532 nm light from a laser diode to illuminate the pin APD. The photocurrent is greatly enhanced when the ionization multiplication is triggered at high voltages. A large avalanche gain was observed, and its variation with the electric field strength was investigated. Then, we derived the impact ionization coefficient of electrons for ZnO along the (001) direction, which is a very significant parameter for APD design and optimization. Our work provides important data for high-performance APD based on an Si/ZnO heterostructure, and it also indicates that the p-Si/i-ZnO/n-AZO structure is a promising option to realize a high-performance avalanche-type device. It may renew the research interest in the realization of APD using ZnO.

**Author Contributions:** Conceptualization, G.L., X.Z.; methodology, X.Z., X.J., S.L.; validation, G.L., X.J. and S.L.; formal analysis, G.L.; investigation, G.L., X.J. and S.L.; resources, Y.H.; data curation, X.J., S.L.; writing—original draft preparation, G.L.; supervision, G.L.; project administration, G.L., Y.H. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by the Youth Program of National Science Foundation of China, grant muber 61804121; General Program of National Natural Science Foundation of China, grant number 61574113; China Postdoctoral Science Foundation, grant number 2018M643650; Research Support Plan for New Teachers of Xi'an Jiaotong University.

**Acknowledgments:** The authors would like to thank Shuwen Guo for her assistance in C-V measurement.

**Conflicts of Interest:** The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.

#### **References**

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

*Article*

## **Theoretical Investigation of Near-Infrared Fabry–Pérot Microcavity Graphene**/**Silicon Schottky Photodetectors Based on Double Silicon on Insulator Substrates**

#### **Maurizio Casalino**

Institute of Applied Science and Intelligent Systems "Eduardo Caianiello" (CNR), Via P. Castellino n. 141, 80131 Naples, Italy<EMAIL_ADDRESS>
Received: 29 June 2020; Accepted: 20 July 2020; Published: 22 July 2020

**Abstract:** In this work a new concept of silicon resonant cavity enhanced photodetector working at 1550 nm has been theoretically investigated. The absorption mechanism is based on the internal photoemission effect through a graphene/silicon Schottky junction incorporated into a silicon-based Fabry–Pérot optical microcavity whose input mirror is constituted by a double silicon-on-insulator substrate. As output mirror we have investigated two options: a distributed Bragg reflector constituted by some periods of silicon nitride/hydrogenated amorphous silicon and a metallic gold reflector. In addition, we have investigated and compared two configurations: one where the current is collected in the transverse direction with respect to the direction of the incident light, the other where it is collected in the longitudinal direction. We show that while the former configuration is characterized by a better responsivity, spectral selectivity and noise equivalent power, the latter configuration is superior in terms of bandwidth and responsivity × bandwidth product. Our results show responsivity of 0.24 A/W, bandwidth in GHz regime, noise equivalent power of 0.6 nW/cm√Hz and full with at half maximum of 8.5 nm. The whole structure has been designed to be compatible with silicon technology.

**Keywords:** resonant cavity; photodetectors; near-infrared; silicon; graphene

#### **1. Introduction**

Silicon (Si) photonics is nowadays an emerging market promising to reach a value of \$560 M at chip level and \$4 B at transceiver level in 2025 as shown in Figure 1. Indeed, both switching and interconnects of the existing data center risk becoming an early bottleneck for the huge increase in internet data traffic driven by social network and video contents.

**Figure 1.** Silicon photonics 2016–2025 market forecast [1].

This is because in the future new technologies must necessarily be introduced for making Si fully compatible for sensors [2,3] and photonic devices in general. Since the 1980s the interest of both scientists and industry in Si photonics has grown exponentially. Nowadays Luxtera together with Intel share the leadership in Si photonics with commercial transceivers able to transmit data at a rate of 100 G. Si is a very mature technology and still plays a key role in the microelectronic industry, for this reason the realization of photonic devices in Si would be the best approach for matching the data center requirements in terms of reliability, low cost, power consumption and integration density.

Photodetectors (PDs) are key devices in photonics making possible the transduction of light into current. Si PDs operating in the visible spectrum are still commercial components, on the other hand Si employment for near-infrared (NIR) detection is hindered by its optical transparence over 1.1 micron.

Currently, Si-based NIR PDs take advantage of the integration of germanium (Ge) [4,5], however, these devices are characterized by high leakage current due to the lattice mismatch of 4.3%. In order to mitigate this drawback a buffer layer, gradually matching the Si to the Ge lattice, can be fabricated [5–7]; even if this approach reduces the leakage current, however it remains quite high. In addition, the fabrication of this buffer layer involves high thermal budget fabrication processes [8] which prevent Ge being monolithically integrated on Si. Finally, the low Ge absorption at 1550 nm (one order of magnitude lower than indium gallium arsenide, InGaAs) hinders the realization of high-speed PIN devices due to the high thickness of the intrinsic region.

Internal photoemission effect (IPE) offers one option to the all-Si approach in the field of the NIR detection. IPE concerns the optical absorption of a metal involved in a Schottky junction and then the emission of the photo-excited carriers into the semiconductor over the Schottky junction [9,10]. Both palladium silicide (Pd2Si) and platinum silicide (PtSi) have been widely employed in infrared charge-coupled device (CCD) image sensors but, unfortunately, they have to work at cryogenic temperature for increasing the signal-to-noise ratio at an acceptable level. Pd2Si/Si Schottky PDs can operate in the spectrum ranging from 1 to 2.4 μm requiring temperatures of 120 K [11,12] (e.g., satellite applications) while PtSi/Si Shottky PDs can work to an extended spectrum ranging from 3 to 5 μm [13,14] but they needs to operate at lower temperatures of only 80 K. Focal plane arrays (FPA) based on 512 × 512 PtSi/Si PDs have been demonstrated [15].

In 2006, for first time, it was theoretically proposed to use IPE for detecting NIR in Si at room temperature. The idea was to work with junctions characterized by higher Schottky barriers for reducing the dark current and, at the same time, to recovery the unavoidable reduced efficiency by incorporating the junction into a Fabry–Peròt optical microcavity [16]. After that, many innovative approaches have been investigated taking advantage of: Si nanoparticles (NPs) [17], surface plasmon polaritons (SPPs) [18,19], antennas [20] and gratings [21]. Despite this, to date responsivities of only 30 mA/W [17] and 5 mA/W [22] were reported for waveguide and free-space PDs, respectively. The low responsivity is mainly due to the low emission probability of the charge carriers excited from the metal to the semiconductor. IPE theory shows that this emission probability can be increased by thinning the metal [23,24]. This is the reason why the idea of replacing metal with graphene was born. Graphene/Si Schottky PDs have shown unexpected efficiency in both the visible [25,26] and NIR [27] spectrum: while in the visible range this enhancement has been ascribed to the gating effect of the graphene/SiO2/Si capacitor in parallel to the graphene/Si junction [25,28], in the NIR range increased IPE has been attributed to the increased charge emission probability due to the mediation of the interface defects [27]. However, in this last case the whole efficiency is hindered by the low graphene absorption (only 2.3%). In order to increase the graphene optical absorption, many strategies have been followed: by realizing plasmonic nanostructures [29], by reducing the graphene size down to nanodisks [30] or quantum dots [31]. On the other hand, PDs based on the increase of thin film optical absorption by the use of an optical microcavity have been already reported in literature with the name of resonant cavity enhanced (RCE) photodetectors [32]. RCE PDs are able to shrink the optical field inside the cavity within the active intrinsic layer of III-V PIN diodes [32] allowing reducing

the size of the absorbing layer, and consequently the carrier transit time, without degradation of the device efficiency.

Taking advantage of this idea, in this work we propose a new concept of Si-based RCE PDs operating at 1550 nm where graphene/Si Schottky junctions have been incorporated into a Fabry–Perot microcavity [33] that could be realized starting from a crystalline-Si (c-Si) based distributed Bragg reflector (DBR) substrate. Indeed, thanks to a double silicon on insulator (SOI) process, DBRs consisting of two periods of c-Si/SiO2 can be realized and optimized for high reflectivity around 1550 nm [34]; they are named double-SOI (DSOI). As second mirror two options have been considered: a distributed Bragg reflector constituted by some periods of silicon nitride (Si3N4)/hydrogenated amorphous silicon (a-Si:H) and a metallic reflector based on a thick layer of gold. In more detail, our proposal is to replace the III-V P-I-N diodes used in classical RCE configuration by a buffer layer added to a graphene/silicon Schottky junction. The buffer layer is useful to accommodate the localized optical field on the thin graphene layers where charge carriers are excited by photons and then emitted into c-Si through the Schottky junction making detection possible in the NIR spectrum. As buffer layer, we have chosen a-Si:H, a material which can be deposited at low temperature by a plasma-enhanced chemical vapor deposition (PECVD) system. Moreover, a-Si:H is characterized by a refractive index very close to that of c-Si at 1550 nm which is mandatory to reduce the Fresnel reflection at the interface and, consequently, to consider the a-Si:H/graphene/c-Si three-layer structure as one unique optical cavity. Finally, we have investigated the possibility to collect the current both longitudinally and transversally to the direction of the incoming light putting in evidence advantages and disadvantages of each configuration.

#### **2. Photodetector Performance and Theoretical Background**

It is well-known that a very important figure of merit for a PD is the internal quantum efficiency (IQE) η*int*, defined as the number of charge carriers collected per absorbed photon. IQE is linked to the external quantum efficiency (EQE) η*ext* (number of charge carriers collected per incident photon) by the following formula: η*ext* = *A* η*int*, where *A* is the optical absorption of the active material. A macroscopic measurable magnitude is the responsivity *R*, i.e., the ratio of the photogenerated current (*Iph*) to the incident optical power (*Pinc*). The responsivity *R* is linked to EQE η*ext* by the following formula:

$$R = \frac{I\_{\rm plr}}{P\_{\rm inc}} = \frac{\lambda (nm)}{1242} \eta\_{\rm cxt} = \frac{\lambda (nm)}{1242} A \ \eta\_{\rm lint} \tag{1}$$

As reported in literature, the internal quantum efficiency of an IPE-based graphene/silicon Schottky photodetectors is given by the following [35]:

$$\eta\_{int} = \frac{1}{2} \frac{\left(h\nu\right)^2 - \left(q\phi\_B\right)^2}{\left(h\nu\right)^2} \tag{2}$$

where *h*ν is the photon energy, *q* = 1.602 × 10−19 C is the charge electron and *q*φ*B* is the Schottky barrier height of the graphene/silicon junction. It is well-known that due to the Fermi level shift in graphene, the Schottky barrier of a graphene/silicon junction lowers by increasing the reverse voltage applied. Of course, the decrease in φ*B* leads to increased responsivity, thus the effects of the reverse voltage *VR* on the responsivity can be investigated. In other words, the Schottky barrier *q*φ*B* can be viewed as the sum of the Schottky barrier at zero-bias *q*φ*B*0 and the Schottky barrier lowering *q*Δφ*B(VR)* due to the increase in reverse voltage: *q*φ*B (VR)* = *q*φ*B*0 + *q*Δφ*B (VR)*. To this aim we take advantage of the work of Tongay et al. [36] where, the Schottky barrier lowering Δφ*B (VR)* due to the Fermi level shift has been calculated by the following formula:

$$
\eta\_I \Delta \phi\_B(V\_R) = -\frac{1}{2} \hbar v\_F \sqrt{\frac{\pi \varepsilon\_{s} \varepsilon\_{l} \mathcal{N}(V\_{bi} + V\_R)}{2qn\_0}} \tag{3}
$$

where *n*0 is the graphene extrinsic doping (a typical value is 5 × 1012 cm−2 [36]), *N* is the semiconductor doping, *vF* = 1.1 × 108 cm/s is the Fermi velocity, - = 6.5 × 10−16 *eVs* is the Plank constant, ε0 = 8.859 × 10−14 C/cmV is the permittivity of vacuum, ε*S* = 11.4 is the relative permittivity of Si and *Vbi* is the built-in potential of the junction.

Device bandwidth is another figure of merit very important for a PD, in particular in telecom and datacom applications. The main factors limiting the time response of a PD integrated into an optical microcavity are [37,38]: (1) the carriers transit time τ*tr* across the charge spatial region, (2) the charge/discharge time τ*RC* linked to both the junction capacitance *Cj* and the load resistance *RL*; (3) the cavity photon lifetime τ*ph* [39]. Thus, the overall time constant of the PD is τ = τ*tr* + τ*RC* + τ*ph*. For the τRC = *RLCj* calculation, we can consider *RL* = 50 Ω (typical value for high-speed applications) and the junction capacitance given by the following formula: *Cj* = *APD*·ε0·ε*s*/W, where *APD* = π*r*2 is the circular graphene area with radius r in contact with Si and W is the charge spatial region width On the other hand, the cavity photon lifetime can be calculated by the following formula τ*ph* = 1/2πδν [39], being δν the spectral width of the absorption peak at half maximum. The transit time τ*tr* can be written as τ*tr* = *t*/*vsat* where *t* is the maximum distance that the electron must travel before being collected (by considering this distance completely depleted) and *vsat* is the carrier saturation velocity in Si. As we will see, this distance t strongly affects the bandwidth of the device.

Finally, the cut-off frequency can be estimated as:

$$f\_{3dB} = \frac{1}{2\pi\tau} = \frac{1}{2\pi \left(\frac{t}{v\_{\text{sat}}} + \frac{\pi c\_0 c\_d R\_L}{W} r^2 + \frac{1}{2\pi \delta v}\right)}\tag{4}$$

Another very important figure of merit is the noise equivalent power (NEP), i.e., the minimum optical power which can be detected by a PD, in an approximated form, which can be written as:

$$NEP = \frac{\sqrt{2qI\_d}}{R} \tag{5}$$

Being *q* the electron charge and *Jd* the dark current density that, for Schottky PD, can be written as:

$$J\_d = A^\* T^2 e^{-\frac{q\phi\_{00}}{kT}}\tag{6}$$

where *A\** is the Richardson constant (32 A/cm2K2 for *p*-Si [37]), *T* the absolute temperature, *k* the Boltzmann constant and *q*Φ*B*0 is the Schottky barrier of the graphene/silicon Schottky junction at zero bias. The unity of measure of NEP is *W*/*cm* √ *Hz*.

#### **3. Photodetector Concept: From the Idea to the Device**

In this section the basic idea of the device will be presented, some details on the numerical simulations will be provided, and the materials selected for a possible fabrication will be discussed.

#### *3.1. Si-Based Resonant Cavity Enhanced (RCE) Photodetectors*

Classical RCE PDs are able to concentrate the enhanced optical field in the absorbing intrinsic region of a PIN diode realized by a III-V semiconductor [32], where the P, I and N are characterized by a slightly different stoichiometry in such a way as to neglect the reflections at the interface and to consider the whole PIN structure as an unique cavity.

In our proposed device, the P-I-N structure has been replaced by a Schottky graphene/c-Si Schottky junction on which is added a buffer layer useful to accommodate the localized optical field on graphene as shown in Figure 2. As buffer layer we have chosen hydrogenated amorphous silicon (a-Si:H) because it can both be deposited at low temperature by a PECVD system and its refractive index at 1550 nm is 3.58 [40], very close to that one of c-Si (3.48) [41]. This latter property together with the

high transparence of the graphene layer allow considering the whole a-Si:H/graphene/c-Si three-layer structure as one unique optical cavity with negligible reflections at the interfaces.

**Figure 2.** Simplified model of the proposed Fabry–Pérot graphene/silicon Schottky photodetector.

It is widely reported in literature that the maximum absorption of RCE PDs occurs when the reflectivity of the output mirror is close to the unity. This is the reason why we consider illumination from the bottom as shown in Figure 2, indeed as will see in Section 3.3 the DSOI DBR is characterized by a limited reflectivity making it not suitable to work as output mirror. It is worth mentioning that an optimized RCE structure is characterized by an output mirror reflectivity *R*2 = 1 and an input mirror reflectivity *R*1 = *R*2 × *e* −α*gdg* , being α*g* and *dg* the absorption coefficient and thickness of the graphene absorbing layer, respectively [35]. All numerical simulations have been carried out by the transfer matrix method (TMM) taking into account the dispersion curve shown in Figure 3a–d.

Figure 3b shows that only graphene and Au are provided of a non-negligible extinction coefficient (absorption coefficient) in the range of wavelength taken into account. Moreover, Figure 3d shows that non-negligible absorption appears when Si is considered heavily doped due to free carrier absorption. In the next, for heavily and lightly doped silicon semiconductor we'll intend doping of 5 × 1019 cm−3 and 1 × 1015 cm−3, respectively.

All dispersion curves shown in Figure 3 have been taken by references [41–43], while the graphene complex refractive index *ng* can be obtained by [44]:

$$m\_{\mathcal{S}} = \sqrt{\epsilon\_{\mathcal{S}}} = \sqrt{2.148 + j \frac{G\lambda}{2d\_{\mathcal{S}}}} \tag{7}$$

where ε*g* is the relative permittivity of graphene, λ is the wavelength, *dg* = 0.335 nm is the graphene thickness and *G* = *q*2 2ε0*hc* = 0.0073 is the fine structure constant [45] (being h = 6.626 × 10−34 Js the Planck constant, and c = 3 × 1010 cm/s the speed of light in vacuum).

Finally, the heavily-doped c-Si complex refractive index has been calculated by applying the theory of the free carrier absorption [46]. The calculation provides the variation of both the real part of the refractive index Δ*nSi* and the absorption coefficient ΔαSi of doped c-Si as a function of the donor and acceptor concentration atoms, *Nd* and *Na*, respectively [46]:

$$
\Delta m\_{Si} = \frac{q^2 \lambda^2}{8\pi^2 c^2 \varepsilon\_0 n\_{Si}^0} \left(\frac{N\_d}{m\_c^\*} + \frac{N\_d}{m\_h^\*}\right) \tag{8}
$$

$$
\Delta \alpha\_{Si} = \frac{q^3 \lambda^2}{4 \pi^2 c^3 \varepsilon\_0 n\_{Si}^0} \left( \frac{N\_d}{\mu\_\epsilon \left( m\_e^\* \right)^2} + \frac{N\_a}{\mu\_h \left( m\_h^\* \right)^2} \right) \tag{9}
$$

where *nSi*0 is the refractive index of unperturbed crystalline Si, *m*∗ *e* and *m*∗ *h* are the conductivity effective mass of electrons and holes, respectively, while μ*e* and μ*h* are the electrons and holes mobility, respectively. It is worth remembering that the extinction coefficient κ*Si* can be derived by the absorption coefficient α*Si* by the following formula: α*Si* = *(4*π/λ*)* κ*Si*.

**Figure 3.** Dispersion curves of all materials used in our numerical simulation: (**a**) real part of refractive index and (**b**) extinction coefficient of a-Si:H, Si3N4, Au, SiO2 and graphene. (**c**) real part of refractive index and (**d**) extinction coefficient of lightly (1 × 1015 cm−3) and heavily doped (5 × 1019 cm−3) c-Si.

#### *3.2. Bu*ff*er Layer*