**Part 3**

**Power Systems Applications**

34 MATLAB/Book4

152 MATLAB for Engineers – Applications in Control, Electrical Engineering, IT and Robotics

processing data represented in different forms such as plane data, 3D (rectangular and

The examples of working codes given in the chapter allow wide range of investigators and, in the first place, PhD and master students, to start quickly the solution of their own original

Joannopoulos, J., Meade, R. & Winn, J. (1995). *Photonic Crystals: Molding the Flow of Light*,

Lourtioz, J.-M., Benisty, H. & Berger, V. (2005). *Photonic Crystals, Towards Nanoscale Photonic*

Sukhoivanov, I. & Guryev, I. (2009). *Photonic crystals – physics and practical modeling*, Optical

Taflove, A. & Hagness, S. (2005). *Computational Electrodynamics: The Finite-Difference*

triangular mesh) data, the data represented by several files.

URL: *http://www.comsol.com*

*Devices*, Springer-Verlag.

URL: *http://www.rsoftdesign.com/*

sciences, 1 edn, Springer, Berlin.

Princeton University Press, Princeton.

URL: *http://www.mathworks.com/help/techdoc/*

URL: *http://ab-initio.mit.edu/wiki/index.php/Meep\_manual*

URL: *http://ab-initio.mit.edu/wiki/index.php/MPB\_manual*

Sakoda, K. (2001). *Optical Properties of Photonic Crystals*, Springer-Verlag.

*Time-Domain Method*, 3 edn, Artech House, Norwood, MA.

problems.

**10. References** *COMSOL* (2011).

*MATLAB manual* (2011).

*MEEP* (2011).

*MPB* (2011).

*RSoft* (2011).

**7**

*Italy*

**MATLAB Co-Simulation Tools for**

Modern electronic devices could be thought as the collection of elementary subsystems, each one requiring a regulated supply voltage in order to perform the desired function. Actually, in a system board you can find as many as ten separate voltage rails, each one rated for a maximum current and current slew-rate. If the available energy source is not suitable for the specific application, a power supply system is required to convert energy from the available input form to the desired output. Since power-up, power-down sequences and recovery from multiple fault conditions are usually offered, monitoring and sequencing the voltage rails is quite complex and a central power management controller is used. The design of the power management system is a key step for a successful conclusion of the overall design. The cost, size and volume of the electronic device are heavily affected by the power supply performances. The proliferation of switching converters throughout the electronic industry is a matter of fact. Unlike linear regulators, switching converters are suitable for both reducing and increasing the unregulated input voltage and efficiency can be as high as 97%. Classification of switching power supplies is mainly based on the available input energy form and the desired output: AC-AC cycle conversion: alternate input, alternate output; AC-DC rectification: alternate input, continuous output; DC-AC inversion: continuous input, alternate output; DC-DC conversion: continuous input, continuous output. Several topologies are well suited to perform the required conversion (Erikson et al., 2001; Pressman et al., 2009). Independently of the specific topology, the architecture of a power supply system can be generalized as shown in Fig.1. A power section and a control section are highlighted. The switching converter is included in the power section while the feedback network and protection circuits for safe operation are collected in the control system. Mainly because of the growing interest in digital controllers, a power supply system can be modelled as a complex system, quite often involving both digital and analog subsystems. If compared to their analog counterparts, digital controllers offer lower power consumption, higher immunity to components aging and higher and higher design flexibility. The control algorithm is often described at a functional level using hardware description language, as VHDL or Verilog. ASICs or FPGA based controllers are usually integrated by the means of sophisticated simulation, synthesis and verification tools. Time to market is heavily reduced by the means of powerful simulation environments and accurate system modelling. Achieving high accuracy models for mixed-mode systems is quite difficult. Specific simulation tools are available on the market, each one oriented to a specific

**1. Introduction**

**Power Supply Systems Design**

Valeria Boscaino and Giuseppe Capponi

*University of Palermo*

### **MATLAB Co-Simulation Tools for Power Supply Systems Design**

Valeria Boscaino and Giuseppe Capponi *University of Palermo Italy*

#### **1. Introduction**

Modern electronic devices could be thought as the collection of elementary subsystems, each one requiring a regulated supply voltage in order to perform the desired function. Actually, in a system board you can find as many as ten separate voltage rails, each one rated for a maximum current and current slew-rate. If the available energy source is not suitable for the specific application, a power supply system is required to convert energy from the available input form to the desired output. Since power-up, power-down sequences and recovery from multiple fault conditions are usually offered, monitoring and sequencing the voltage rails is quite complex and a central power management controller is used. The design of the power management system is a key step for a successful conclusion of the overall design. The cost, size and volume of the electronic device are heavily affected by the power supply performances. The proliferation of switching converters throughout the electronic industry is a matter of fact. Unlike linear regulators, switching converters are suitable for both reducing and increasing the unregulated input voltage and efficiency can be as high as 97%. Classification of switching power supplies is mainly based on the available input energy form and the desired output: AC-AC cycle conversion: alternate input, alternate output; AC-DC rectification: alternate input, continuous output; DC-AC inversion: continuous input, alternate output; DC-DC conversion: continuous input, continuous output. Several topologies are well suited to perform the required conversion (Erikson et al., 2001; Pressman et al., 2009). Independently of the specific topology, the architecture of a power supply system can be generalized as shown in Fig.1. A power section and a control section are highlighted. The switching converter is included in the power section while the feedback network and protection circuits for safe operation are collected in the control system. Mainly because of the growing interest in digital controllers, a power supply system can be modelled as a complex system, quite often involving both digital and analog subsystems. If compared to their analog counterparts, digital controllers offer lower power consumption, higher immunity to components aging and higher and higher design flexibility. The control algorithm is often described at a functional level using hardware description language, as VHDL or Verilog. ASICs or FPGA based controllers are usually integrated by the means of sophisticated simulation, synthesis and verification tools. Time to market is heavily reduced by the means of powerful simulation environments and accurate system modelling. Achieving high accuracy models for mixed-mode systems is quite difficult. Specific simulation tools are available on the market, each one oriented to a specific

MATLAB Co-Simulation Tools for Power Supply Systems Design 157

values, often higher than 100A, are required. VRMs supply highly dynamic loads exhibiting current slew rates as high as 1000A/μs. Today, in distributed power architectures, individual POL converters usually draw power from a 12V intermediate power bus. Lowering the core voltage results in a very narrow duty cycle of the 12V-input converter, worsening the converter efficiency and load transient response. The best topology for VRM applications features tight voltage regulation, very fast transient response, high-current handling capabilities and high efficiency. Modern technology advances constantly prompt electronics researchers to meet all requirements investigating innovative solutions. The evolution from a classical buck topology to multiphase architectures is described to better understand the great

The buck topology and the MOSFET gate drive signal are shown in Fig.2. The gate signal period is always referred to as the converter switching period T. The duty-cycle D is defined as the ratio between the MOSFET on-time and the switching period. Since one terminal of the power MOSFET is tied to the high-side of the input voltage rail, the MOSFET is also called high-side MOSFET. The steady-state analysis is here performed assuming constant

On the rising edge of the gate drive signal, the high-side MOSFET is turned on. The inductor is now series connected between the input and output rails and the diode is reverse biased. During the MOSFET on-time, the inductor current slope is constant and it can be expressed

> ��� = ��� � ���� �

> > ���� = ����� �

On the falling edge of the gate drive signal, the MOSFET is turned off. The inductor opposes the current break trying to maintain the previously established current. The voltage polarity across it immediately reverses. Since the right terminal of the inductor is tied to the output rail, the cathode voltage of the diode D is driven toward negative values. When zero crossing occurs, the diode D is forced into conduction clamping the cathode node to ground. The inductor voltage is now reversed and full inductor current flows through the diode D. The inductor is now connected in parallel to the output voltage rail. During the OFF-time,

(1)

(2)

advantages brought by multiphase architectures.

the input voltage and the output voltage during a switching period.

Fig. 2. The buck converter topology and gate drive signal.

the slope of the inductor current is given by:

as:

abstraction level. Circuit simulation software as *Powersim PSIM* and *Orcad Pspice* are the most common choice for circuit modelling. In (Basso, 2008), the design and simulation of switchmode power supplies is deeply analyzed and simulation tips in several environments are proposed. ASIC simulation and verification tools as Xilinx ISE/Modelsim or Aldec Active-HDL are available to implement the digital controller by the VHDL or VERILOG source code. Since the interaction between subsystems is the most common source of faults, testing separately analog and digital subsystems by the means of different verification tools is a severe mistake. Matlab is a powerful simulation environment for mixed-mode systems modelling and simulation, providing several tools for system co-simulation (Pop, 2010; Kaichun et al., 2010). The Matlab suite offers co-simulation tools for *PSIM*, *Modelsim* and *Active-HDL* simulation environments. Ideally, modelling the power converter by a circuit implementation in PSIM environment and the digital controller by the VHDL code in *Xilinx ISE* or *Active-HDL* environment allows the designer to test the composite system in Matlab environment using co-simulation procedures. Unfortunately, the use of several co-simulation tools in the same Simulink model heavily reduces the processing speed. As an example, in this chapter the Simulink model of a multiphase dc-dc converter for VRMs applications is described. The control system is described by VHDL language and the controller model is implemented in *Active-HDL* environment. For the highest processing speed, an alternative modelling technique for the power section is proposed by the means of elementary library blocks, avoiding *PSIM* co-simulation and not affecting the accuracy of behavioural simulations. As shown by simulation results, the high accuracy relies in the opportunity to match the system behaviour both within the switching event and during long-time events such as load transients and startup. The great potential of the co-simulation procedure for mixed-mode systems is highlighted by the comparison between simulation and experimental results.

Fig. 1. Power supply system architecture.

#### **2. Multiphase dc-dc converters for VRM applications**

The evolution in microprocessor technology poses new challenges for power supply design. The end of 2009 marked the birth of 32nm technology for semiconductor devices, and 22nm is expected to be reached in the 2011-2012 timeframe. The next generation of computer microprocessors will operate at significantly lower voltages and higher currents than today's generation in order to decrease the power consumption and increase the processing speed.  Highquality power is delivered to the microprocessor by a point-of-load (POL) converter, also known as voltage regulator module (VRM), which is located on the motherboard next to the load. Embedded POL converters are designed to supply a tight regulated output voltage in the 0.8 – 1.2V range. Due to integration advances and increasing clock frequencies, high current

abstraction level. Circuit simulation software as *Powersim PSIM* and *Orcad Pspice* are the most common choice for circuit modelling. In (Basso, 2008), the design and simulation of switchmode power supplies is deeply analyzed and simulation tips in several environments are proposed. ASIC simulation and verification tools as Xilinx ISE/Modelsim or Aldec Active-HDL are available to implement the digital controller by the VHDL or VERILOG source code. Since the interaction between subsystems is the most common source of faults, testing separately analog and digital subsystems by the means of different verification tools is a severe mistake. Matlab is a powerful simulation environment for mixed-mode systems modelling and simulation, providing several tools for system co-simulation (Pop, 2010; Kaichun et al., 2010). The Matlab suite offers co-simulation tools for *PSIM*, *Modelsim* and *Active-HDL* simulation environments. Ideally, modelling the power converter by a circuit implementation in PSIM environment and the digital controller by the VHDL code in *Xilinx ISE* or *Active-HDL* environment allows the designer to test the composite system in Matlab environment using co-simulation procedures. Unfortunately, the use of several co-simulation tools in the same Simulink model heavily reduces the processing speed. As an example, in this chapter the Simulink model of a multiphase dc-dc converter for VRMs applications is described. The control system is described by VHDL language and the controller model is implemented in *Active-HDL* environment. For the highest processing speed, an alternative modelling technique for the power section is proposed by the means of elementary library blocks, avoiding *PSIM* co-simulation and not affecting the accuracy of behavioural simulations. As shown by simulation results, the high accuracy relies in the opportunity to match the system behaviour both within the switching event and during long-time events such as load transients and startup. The great potential of the co-simulation procedure for mixed-mode systems is highlighted

by the comparison between simulation and experimental results.

**2. Multiphase dc-dc converters for VRM applications**

The evolution in microprocessor technology poses new challenges for power supply design. The end of 2009 marked the birth of 32nm technology for semiconductor devices, and 22nm is expected to be reached in the 2011-2012 timeframe. The next generation of computer microprocessors will operate at significantly lower voltages and higher currents than today's generation in order to decrease the power consumption and increase the processing speed.  Highquality power is delivered to the microprocessor by a point-of-load (POL) converter, also known as voltage regulator module (VRM), which is located on the motherboard next to the load. Embedded POL converters are designed to supply a tight regulated output voltage in the 0.8 – 1.2V range. Due to integration advances and increasing clock frequencies, high current

Fig. 1. Power supply system architecture.

values, often higher than 100A, are required. VRMs supply highly dynamic loads exhibiting current slew rates as high as 1000A/μs. Today, in distributed power architectures, individual POL converters usually draw power from a 12V intermediate power bus. Lowering the core voltage results in a very narrow duty cycle of the 12V-input converter, worsening the converter efficiency and load transient response. The best topology for VRM applications features tight voltage regulation, very fast transient response, high-current handling capabilities and high efficiency. Modern technology advances constantly prompt electronics researchers to meet all requirements investigating innovative solutions. The evolution from a classical buck topology to multiphase architectures is described to better understand the great advantages brought by multiphase architectures.

The buck topology and the MOSFET gate drive signal are shown in Fig.2. The gate signal period is always referred to as the converter switching period T. The duty-cycle D is defined as the ratio between the MOSFET on-time and the switching period. Since one terminal of the power MOSFET is tied to the high-side of the input voltage rail, the MOSFET is also called high-side MOSFET. The steady-state analysis is here performed assuming constant the input voltage and the output voltage during a switching period.

Fig. 2. The buck converter topology and gate drive signal.

On the rising edge of the gate drive signal, the high-side MOSFET is turned on. The inductor is now series connected between the input and output rails and the diode is reverse biased. During the MOSFET on-time, the inductor current slope is constant and it can be expressed as:

$$s\_{on} = \frac{Vin - Vout}{L} \tag{1}$$

On the falling edge of the gate drive signal, the MOSFET is turned off. The inductor opposes the current break trying to maintain the previously established current. The voltage polarity across it immediately reverses. Since the right terminal of the inductor is tied to the output rail, the cathode voltage of the diode D is driven toward negative values. When zero crossing occurs, the diode D is forced into conduction clamping the cathode node to ground. The inductor voltage is now reversed and full inductor current flows through the diode D. The inductor is now connected in parallel to the output voltage rail. During the OFF-time, the slope of the inductor current is given by:

$$s\_{off} = \frac{-Vout}{L} \tag{2}$$

$$(Vin - Volt) \cdot T\_{on} = -Vout \cdot T\_{off} \tag{3}$$

$$\text{Vout} = \text{Vin} \cdot \frac{T\_{on}}{T\_{on} + T\_{off}} \tag{4}$$

$$
\Delta I\_L = \frac{V \text{in} - V \text{out}}{L} \cdot T\_{on} = \frac{-V \text{out}}{L} \cdot T\_{off} = \frac{V \text{in} (1 - D)D}{L} T \tag{5}
$$

$$\frac{\Delta IL}{2} \ll I\_{out} \tag{6}$$

$$q = \frac{1}{2} \frac{\Delta I\_L}{2} \frac{T}{2} \tag{7}$$

$$
\Delta V = \frac{q}{\mathcal{C}} = \frac{\Delta I\_L T}{8\mathcal{C}} \tag{8}
$$

$$
\Delta V\_{out,max} = \Delta I \cdot \sqrt{\frac{L}{C}} + \text{ }Rc \cdot \Delta I \tag{9}
$$

MATLAB Co-Simulation Tools for Power Supply Systems Design 161

A dead-time is required to avoid the simultaneous conduction of high-side and low-side MOSFETs. During the dead time, neither the low-side nor the high side MOSFET is on. When the high-side MOSFET is turned off, the inductor opposes the current break forcing the low-side MOSFET body-diode into conduction. Over the entire dead time the full inductor current flows through the body diode itself. At the end of the dead time, the lowside MOSFET is turned on, the body diode is bypassed by the active MOSFET channel and the inductor current flows through the low-side MOSFET channel.  It would be advisable a further reduction of both the diode threshold voltage and the dead time in order to limit power losses. A Schottky diode is often integrated in parallel to power MOSFET: the body diode will be bypassed by the Schottky diode over the entire dead time lowering the effective threshold voltage. A minimization of the low-side body-diode conduction time is required to take advantage from synchronous rectification. Sophisticated dead-time control algorithms are usually implemented by synchronous MOSFET drivers. If a single buck converter topology were employed in high-current applications, a large amount of outputfilter and on-board decoupling capacitance would be required to achieve the expected transient response. The size and cost of the voltage regulator would increase as well. Multiphase converters are widely used. Ripple cancellation and improved transient response are only a few advantages of multi-phase architectures. A detailed analysis of multiphase converters is reported in (Miftakhutdinov, 2001). In N-modules architecture, N identical buck converters are connected in parallel to the load resulting in a heavy reduction of the output ripple. Smaller inductances are allowed thus improving the transient response. Note that increasing the number of modules emphasizes the advantages of a multiphase architecture. Gate drive signals are interleaved to take full advantage from the multiphase architecture. Assume that each channel operates at a switching frequency fsw. Under steadystate conditions, the phase shift between gate drive signals of each module depend on the number of interleaved channels. If an N-channels architecture is considered, assume that the control signal sequence is Phase 1, 2,.., N. The interleaved technique requires a 360°/N phase shift between two following channels. The maximum number of channel is limited by

Fig. 7. The synchronous buck topology and MOSFETs gate drive signals.

the relationship:

Fig. 6. The converter waveforms under a large-signal transient.

The optimization of steady-state and dynamic performances leads to a trade-off in the choice of the inductor value. As will be further discussed, the inductor value is usually chosen to meet steady-state requirements and dynamic performances are improved by the control algorithm.

As shown by (4), the buck converter reduces the dc input voltage by the means of switching elements. Power loss due to switches is ideally zero. Yet, switches are not ideal. Further, switching losses cannot be neglected. The inductor current flows through the MOSFET during the on-time and through the diode during the OFF time. Conduction losses are proportional to the forward voltage drop across the active elements. The MOSFET forward voltage drop is lower than the diode threshold voltage. In a buck converter, conduction losses are mainly due to the freewheeling diode.

In high-current low-voltage applications, synchronous rectification is widely used to improve efficiency. As shown in Fig.7, the diode D is replaced by a MOSFET featuring a very low forward voltage drop. The rectification function, typically performed by diodes, is now achieved by the means of a MOSFET which is driven synchronously with the high-side MOSFET. For this reason, the added MOSFET is sometimes referred to as the synchronous rectifier MOSFET. Since the rectifier MOSFET source terminal is tied to the low-side of the input voltage rail, the MOSFET is also called low-side MOSFET. If compared with classical topology, synchronous rectification heavily reduces conduction losses improving efficiency. During the conduction time of the high-side (on time) the low-side is off and vice versa.

Fig. 6. The converter waveforms under a large-signal transient.

losses are mainly due to the freewheeling diode.

control algorithm.

The optimization of steady-state and dynamic performances leads to a trade-off in the choice of the inductor value. As will be further discussed, the inductor value is usually chosen to meet steady-state requirements and dynamic performances are improved by the

As shown by (4), the buck converter reduces the dc input voltage by the means of switching elements. Power loss due to switches is ideally zero. Yet, switches are not ideal. Further, switching losses cannot be neglected. The inductor current flows through the MOSFET during the on-time and through the diode during the OFF time. Conduction losses are proportional to the forward voltage drop across the active elements. The MOSFET forward voltage drop is lower than the diode threshold voltage. In a buck converter, conduction

In high-current low-voltage applications, synchronous rectification is widely used to improve efficiency. As shown in Fig.7, the diode D is replaced by a MOSFET featuring a very low forward voltage drop. The rectification function, typically performed by diodes, is now achieved by the means of a MOSFET which is driven synchronously with the high-side MOSFET. For this reason, the added MOSFET is sometimes referred to as the synchronous rectifier MOSFET. Since the rectifier MOSFET source terminal is tied to the low-side of the input voltage rail, the MOSFET is also called low-side MOSFET. If compared with classical topology, synchronous rectification heavily reduces conduction losses improving efficiency. During the conduction time of the high-side (on time) the low-side is off and vice versa.

Fig. 7. The synchronous buck topology and MOSFETs gate drive signals.

A dead-time is required to avoid the simultaneous conduction of high-side and low-side MOSFETs. During the dead time, neither the low-side nor the high side MOSFET is on. When the high-side MOSFET is turned off, the inductor opposes the current break forcing the low-side MOSFET body-diode into conduction. Over the entire dead time the full inductor current flows through the body diode itself. At the end of the dead time, the lowside MOSFET is turned on, the body diode is bypassed by the active MOSFET channel and the inductor current flows through the low-side MOSFET channel.  It would be advisable a further reduction of both the diode threshold voltage and the dead time in order to limit power losses. A Schottky diode is often integrated in parallel to power MOSFET: the body diode will be bypassed by the Schottky diode over the entire dead time lowering the effective threshold voltage. A minimization of the low-side body-diode conduction time is required to take advantage from synchronous rectification. Sophisticated dead-time control algorithms are usually implemented by synchronous MOSFET drivers. If a single buck converter topology were employed in high-current applications, a large amount of outputfilter and on-board decoupling capacitance would be required to achieve the expected transient response. The size and cost of the voltage regulator would increase as well. Multiphase converters are widely used. Ripple cancellation and improved transient response are only a few advantages of multi-phase architectures. A detailed analysis of multiphase converters is reported in (Miftakhutdinov, 2001). In N-modules architecture, N identical buck converters are connected in parallel to the load resulting in a heavy reduction of the output ripple. Smaller inductances are allowed thus improving the transient response. Note that increasing the number of modules emphasizes the advantages of a multiphase architecture. Gate drive signals are interleaved to take full advantage from the multiphase architecture. Assume that each channel operates at a switching frequency fsw. Under steadystate conditions, the phase shift between gate drive signals of each module depend on the number of interleaved channels. If an N-channels architecture is considered, assume that the control signal sequence is Phase 1, 2,.., N. The interleaved technique requires a 360°/N phase shift between two following channels. The maximum number of channel is limited by the relationship:

$$(1 - D) > N \cdot D \tag{10}$$

MATLAB Co-Simulation Tools for Power Supply Systems Design 163

Fig. 9. High-side MOSFETs gate drive signals.

Fig. 10. Inductor current waveforms under steady-state conditions.

Fig. 11. Equivalent inductor current under steady-state conditions.

������ = ��� − ����

according to the equation:

Within the time interval [0, DTsw/4] the slope of the equivalent current is given by:

� − (�−�)

The equivalent slope is positive during the first subinterval. During the second subinterval [DTsw/4,Tsw/4] all modules are driven OFF. The equivalent current slope is negative

����

� = ���(� − ��) �

(12)

where N is the number of channel and D is the duty-cycle. A key feature of multiphase architecture is now highlighted: the ripple frequency of the output voltage is N-times the switching frequency of each power module. The equivalent switching frequency is higher and higher than the effective switching frequency of each module. The designed multiphase converter features a 4-modules architecture, as shown in Fig.8. Inductors and capacitors are modelled including the parasitic equivalent series resistance. Assume that the control sequence is Phase 1,2,3,4. Interleaved gate drive signals are shown in Fig.9. Fig.10 shows the inductor current waveforms for each buck channel. As shown in Fig.11, the equivalent current is defined as:

$$IL\_{eq} = \Sigma\_{l=1}^{n} IL\_l = IL\_1 + IL\_2 + IL\_3 + IL\_4 \tag{11}$$

Ripple cancellation derives from the interleaving technique. The steady-state analysis is carried on within a fundamental Tsw/4 time interval. Within a Tsw/4 period, only one module could be driven in the ON state, the others are constantly OFF. For example, from 0 to Tsw/4 modules 2, 3 and 4 are constantly OFF while the first module (phase 1) is driven in the ON state during the subinterval [0, DTsw/4]. No matter which phase is active in the ON state, the fundamental period of the output waveforms is Tsw/4 since we have assumed identical modules.

Fig. 8. Multiphase architecture.

where N is the number of channel and D is the duty-cycle. A key feature of multiphase architecture is now highlighted: the ripple frequency of the output voltage is N-times the switching frequency of each power module. The equivalent switching frequency is higher and higher than the effective switching frequency of each module. The designed multiphase converter features a 4-modules architecture, as shown in Fig.8. Inductors and capacitors are modelled including the parasitic equivalent series resistance. Assume that the control sequence is Phase 1,2,3,4. Interleaved gate drive signals are shown in Fig.9. Fig.10 shows the inductor current waveforms for each buck channel. As shown in Fig.11, the equivalent

Ripple cancellation derives from the interleaving technique. The steady-state analysis is carried on within a fundamental Tsw/4 time interval. Within a Tsw/4 period, only one module could be driven in the ON state, the others are constantly OFF. For example, from 0 to Tsw/4 modules 2, 3 and 4 are constantly OFF while the first module (phase 1) is driven in the ON state during the subinterval [0, DTsw/4]. No matter which phase is active in the ON state, the fundamental period of the output waveforms is Tsw/4 since we have assumed

���� = ∑ ��� �

current is defined as:

identical modules.

Fig. 8. Multiphase architecture.

(���) ���� (10)

��� = ��� � ��� � ��� � ��� (11)

Fig. 9. High-side MOSFETs gate drive signals.

Fig. 10. Inductor current waveforms under steady-state conditions.

Fig. 11. Equivalent inductor current under steady-state conditions.

Within the time interval [0, DTsw/4] the slope of the equivalent current is given by:

$$s\_{eq.on} = \frac{Vin - Vout}{L} - (N - 1)\frac{Vout}{L} = \frac{Vin(1 - ND)}{L} \tag{12}$$

The equivalent slope is positive during the first subinterval. During the second subinterval [DTsw/4,Tsw/4] all modules are driven OFF. The equivalent current slope is negative according to the equation:

$$s\_{eq,off} = -N \frac{Vout}{L} \tag{13}$$

MATLAB Co-Simulation Tools for Power Supply Systems Design 165

*COMP\_OUT* is generated by the error amplifier which includes the adder and the *COMP* block. A type-2 compensation action is digitally implemented to ensure system stability. The error signal is then converted to analog and compared to the current sense signal of each

The gate drive interleaved technique is digitally implemented by the *Switching logic* subsystems. The master module is the Phase 1, the others slave. Fig.13 shows the switching logic algorithm for the master power module. A clock signal at the switching frequency is synchronously derived from the system clock. The switch-on of the high-side MOSFET is triggered by the rising-edge of the switching clock Ck1. The high-side MOSFET switch-off is

A digital counter generates a switching clock for each slave module which is synchronous with the master switching clock and phase-shifted according to the interleaved technique. The sense signal Vc2,i reproduces the instantaneous inductor current of the *i-th* power module. RC networks are used to sense the instantaneous inductor current of each power

power module Vc2,i.

Fig. 12. Schematic block diagram of the linear controller.

triggered by the rising-edge of the corresponding PWM signal.

Fig. 13. Switching logic for the master module.

The equivalent current ripple is given by:

$$
\Delta I\_{L,eq} = \frac{V \text{in} (1 - ND) D}{L} T\_{\text{sw}} = \frac{\Delta IL \text{ (1 - ND)}}{(1 - D)} \tag{14}
$$

As (14) states, in a multiphase architecture the current ripple is cancelled. If compared with classical buck converters, the current ripple is reduced by (1-ND)/(1-D). Moreover, the equivalent switching frequency as seen by the power load is N times the operating switching frequency of each power module.

Note that (14) could be expressed as:

$$
\Delta I\_{L,eq} = \frac{V \text{in} (1 - ND) D}{L} T\_{sw} = \frac{V \text{in} (1 - ND) DN \cdot N}{N \cdot N \, L} T\_{sw} = \frac{V \text{in}, eq (1 - Deq) Deq}{Leq} T\_{sw, eq} \tag{15}
$$

where N is the number of modules and ��� = � � �� ���� �� = � � ���, ��� = � � � ���� �� = ��� � .

By comparing (15) and (5), conclusions are drawn: a N-modules architecture is equivalent to a buck converter operating at fsw,eq switching frequency, Deq duty-cycle, supplied by Vin,eq input voltage and featuring Leq inductance. Then, if compared with a buck converter fed by the same input voltage rail and supplying the same voltage bus, the multiphase architecture features higher switching frequency, higher duty-cycle and lower inductance. Both steadystate and dynamic performances of the switching regulator take a great advantage from these interesting properties. With regards to steady-state performances, tight voltage regulation could be achieved thanks to the ripple cancellation effect. Dynamic performances are greatly improved by the reduction of the equivalent inductor under load transients. The steady-state and dynamic performances of multiphase converters are affected by the duty cycle value. A narrow duty cycle results in a poor ripple cancellation. Hence, a larger inductance should be selected to keep tight voltage regulation worsening the transient response. If a wide input-output voltage range is considered, a proper design of passive components is not yet suitable for speeding up the system performances. Multiphase architectures achieving a duty cycle extension by the means of coupled inductors are frequently proposed in literature.

Otherwise, unconventional control algorithms are proposed to speed up the transient response not affecting the passive components design.

#### **3. The control system**

A survey of the control algorithm is given to highlight the system complexity and high accuracy of simulation results. Authors suggest (Boscaino et al., 2009) for further details. A linear-non-linear digital controller oriented to IC implementation, improving both steadystate and transient response is presented. A schematic block diagram of the linear loop is shown in Fig.12.

A Pulse Width Modulation (PWM) current-mode control is implemented. Two 10 bits/2V ADCs and a 12 bits /5V DAC are included in the analog-digital interface. The output voltage is converted to digital and compared to a reference voltage Vref. The error signal

As (14) states, in a multiphase architecture the current ripple is cancelled. If compared with classical buck converters, the current ripple is reduced by (1-ND)/(1-D). Moreover, the equivalent switching frequency as seen by the power load is N times the operating

By comparing (15) and (5), conclusions are drawn: a N-modules architecture is equivalent to a buck converter operating at fsw,eq switching frequency, Deq duty-cycle, supplied by Vin,eq input voltage and featuring Leq inductance. Then, if compared with a buck converter fed by the same input voltage rail and supplying the same voltage bus, the multiphase architecture features higher switching frequency, higher duty-cycle and lower inductance. Both steadystate and dynamic performances of the switching regulator take a great advantage from these interesting properties. With regards to steady-state performances, tight voltage regulation could be achieved thanks to the ripple cancellation effect. Dynamic performances are greatly improved by the reduction of the equivalent inductor under load transients. The steady-state and dynamic performances of multiphase converters are affected by the duty cycle value. A narrow duty cycle results in a poor ripple cancellation. Hence, a larger inductance should be selected to keep tight voltage regulation worsening the transient response. If a wide input-output voltage range is considered, a proper design of passive components is not yet suitable for speeding up the system performances. Multiphase architectures achieving a duty cycle extension by the means of coupled inductors are

Otherwise, unconventional control algorithms are proposed to speed up the transient

A survey of the control algorithm is given to highlight the system complexity and high accuracy of simulation results. Authors suggest (Boscaino et al., 2009) for further details. A linear-non-linear digital controller oriented to IC implementation, improving both steadystate and transient response is presented. A schematic block diagram of the linear loop is

A Pulse Width Modulation (PWM) current-mode control is implemented. Two 10 bits/2V ADCs and a 12 bits /5V DAC are included in the analog-digital interface. The output voltage is converted to digital and compared to a reference voltage Vref. The error signal

���� �

� ��� = ��� (� � ��)

���� ��� = ���� ��(� � ���)���

(13)

(� � �) (14)

��� ������ (15)

� � ���� �� =

������� = ��

������ = ���(� � ��)�

� ��� = ���(� � ��)�� � �

where N is the number of modules and ��� = � � �� ���� �� = � � ���, ��� = �

The equivalent current ripple is given by:

switching frequency of each power module. Note that (14) could be expressed as:

������ = ���(� � ��)�

frequently proposed in literature.

**3. The control system**

shown in Fig.12.

response not affecting the passive components design.

��� � .  *COMP\_OUT* is generated by the error amplifier which includes the adder and the *COMP* block. A type-2 compensation action is digitally implemented to ensure system stability. The error signal is then converted to analog and compared to the current sense signal of each power module Vc2,i.

Fig. 12. Schematic block diagram of the linear controller.

The gate drive interleaved technique is digitally implemented by the *Switching logic* subsystems. The master module is the Phase 1, the others slave. Fig.13 shows the switching logic algorithm for the master power module. A clock signal at the switching frequency is synchronously derived from the system clock. The switch-on of the high-side MOSFET is triggered by the rising-edge of the switching clock Ck1. The high-side MOSFET switch-off is triggered by the rising-edge of the corresponding PWM signal.

Fig. 13. Switching logic for the master module.

A digital counter generates a switching clock for each slave module which is synchronous with the master switching clock and phase-shifted according to the interleaved technique. The sense signal Vc2,i reproduces the instantaneous inductor current of the *i-th* power module. RC networks are used to sense the instantaneous inductor current of each power module. As shown in Fig.14, a RC filter is connected across the low-side MOSFET of each power module. The capacitor voltage Vc2 is the sense signal for current-mode control implementation.

Fig. 14. Current sense network.

The period T=rsCs is fixed according to the equation:

$$D\_{\text{max}}T\_{\text{sw}} \ll T \tag{16}$$

MATLAB Co-Simulation Tools for Power Supply Systems Design 167

Fig. 15. Dynamic response under load transients. At the top the load current step, at the

ref is the variable reference voltage, Vref is a fixed reference voltage, Io is the load

current and Rc is the equivalent series resistor of the output capacitor. The DC set point of the output voltage changes accordingly to the output current, as shown in Fig.16. At steadystate, the output voltage is forced by the AVP technique to the variable reference voltage, instead of a fixed value Vref . Under high-load conditions, the DC set point drops in the lower part of the allowable tolerance window. The maximum tolerance window is now

The technique results in added margin to handle load transients. Since the load current is equal to the average inductor current, the AVP technique is implemented by sensing the

Fig. 16. The dynamic response to a load current step with Adaptive Voltage Positioning.

A non-linear control is introduced to speed-up the transient response not affecting steady-state performances. During transients, the non-linear control modifies a few linear loop parameters, as the reference voltage or the duty-cycle. Since the converter output voltage is the only nonlinear loop input, the proposed technique can be efficiently applied to each power supply

ᇱ ൌ ܸ െ ܫܴܿ) 21 (

οܸ௨௧ǡ௫ ൌ οܫǡ௫ܴܿ (22)

ݒ

bottom, the output voltage waveforms are shown.

average inductor current of the master phase.

where, *v*'

given by:

where Tsw is the switching period and Dmax the maximum operating duty-cycle. The charge and discharge of the capacitor C2 within the switching period reproduces the charge and discharge of the inductor L. The average value of the sense signal is given by:

$$
\overline{V\_{c2}} = Volut + \overline{I\_L} R\_L \tag{17}
$$

where �� is the average inductor current and RL the ESR of the inductor L. The superimposed ripple is given by:

$$
\Delta V\_{c2} = R\_v \Delta I\_L \tag{18}
$$

where ΔIL is the inductor current ripple and Rv the virtual sensing resistor which is given by:

$$R\_v = \frac{L}{r\_s \mathcal{L}\_s} \tag{19}$$

The current-mode control is implemented by the Vc2 sense signal. A detailed analysis of the proposed current-sensing technique, including design guidelines is reported in (Boscaino et al., 2008).

Another RC network featuring a lower cut-off frequency is connected across the switching node of the master phase. The sense capacitor voltage Vc1 reproduces the average inductor current. Vc1 is converted to digital and feeds the *AVP* subsystem which implements the wellknown Adaptive Voltage Positioning (AVP) technique. Fig.15 shows the output voltage and the load current waveforms under a load current step without AVP. The maximum tolerance window on the output voltage is given by:

$$
\Delta V\_{\text{out,max}} = 2 \cdot \Delta I\_{o,max} Rc \tag{20}
$$

With the AVP technique, the reference voltage becomes a function of the load current according to the following equation.

module. As shown in Fig.14, a RC filter is connected across the low-side MOSFET of each power module. The capacitor voltage Vc2 is the sense signal for current-mode control

where Tsw is the switching period and Dmax the maximum operating duty-cycle. The charge and discharge of the capacitor C2 within the switching period reproduces the charge and

where ΔIL is the inductor current ripple and Rv the virtual sensing resistor which is given

The current-mode control is implemented by the Vc2 sense signal. A detailed analysis of the proposed current-sensing technique, including design guidelines is reported in (Boscaino et

Another RC network featuring a lower cut-off frequency is connected across the switching node of the master phase. The sense capacitor voltage Vc1 reproduces the average inductor current. Vc1 is converted to digital and feeds the *AVP* subsystem which implements the wellknown Adaptive Voltage Positioning (AVP) technique. Fig.15 shows the output voltage and the load current waveforms under a load current step without AVP. The maximum

With the AVP technique, the reference voltage becomes a function of the load current

�� = � ����

discharge of the inductor L. The average value of the sense signal is given by:

where �� is the average inductor current and RL the ESR of the inductor L.

������� � � (16)

��� = ���� � ���� (17)

���� = ����� (18)

��������� = � � ��������� (20)

(19)

implementation.

Fig. 14. Current sense network.

The superimposed ripple is given by:

by:

al., 2008).

The period T=rsCs is fixed according to the equation:

tolerance window on the output voltage is given by:

according to the following equation.

Fig. 15. Dynamic response under load transients. At the top the load current step, at the bottom, the output voltage waveforms are shown.

$$
\upsilon\_{ref}' = V\_{ref} - I\_o R \varepsilon \tag{21}
$$

where, *v*' ref is the variable reference voltage, Vref is a fixed reference voltage, Io is the load current and Rc is the equivalent series resistor of the output capacitor. The DC set point of the output voltage changes accordingly to the output current, as shown in Fig.16. At steadystate, the output voltage is forced by the AVP technique to the variable reference voltage, instead of a fixed value Vref . Under high-load conditions, the DC set point drops in the lower part of the allowable tolerance window. The maximum tolerance window is now given by:

$$
\Delta V\_{out,max} = \Delta I\_{o,max} Rc \tag{22}
$$

The technique results in added margin to handle load transients. Since the load current is equal to the average inductor current, the AVP technique is implemented by sensing the average inductor current of the master phase.

A non-linear control is introduced to speed-up the transient response not affecting steady-state performances. During transients, the non-linear control modifies a few linear loop parameters, as the reference voltage or the duty-cycle. Since the converter output voltage is the only nonlinear loop input, the proposed technique can be efficiently applied to each power supply system independently of the specific converter topology and linear loop architecture. Thanks to the AVP technique, load transients are detected by an instantaneous drop of the output voltage, and the increasing or decreasing load current transient is detected by monitoring the output voltage drop in terms of sign and width. Two different non-linear control actions are implemented: under a load current increase (*case a*) or decrease (*case b*). The reference voltage (*case a*) or the duty-cycle (*case b*) is modified by the non-linear control loop. Under increasing load current steps, the non-linear control loop acts on the reference voltage advancing the linear loop action. Two auxiliary signals, VVAR and VLOOP, are defined: VVAR is the output voltage value related to the new steady-state condition while VLOOP is the output voltage ripple during transient referred to VVAR value, as shown in Fig.17.

$$V\_{LOAD} = Volt - V\_{VAR} \tag{23}$$

MATLAB Co-Simulation Tools for Power Supply Systems Design 169

Under a load current decrease, the non-linear control loop modifies the duty-cycle signal, as shown in Fig.18. All modules are simultaneously turned off to allow the inductor current to decrease as fast as possible. Turning off all modules allows the fastest transient response. Unfortunately, the system is driven towards a loop upsetting and thus to an increase, instead of a reduction, of the output voltage over-and-under shoots. Then, a fixed duty-cycle is forced to all modules according to the interleaved technique. Known the VVAR value, the new steady-state duty-cycle is evaluated and forced by the non-linear subsystem to maintain a regulated output voltage during linear loop resettling. The false steady-state

> ��� = ���� + ���� ���

> > �� = ��� ��

��� = ���� + (������� � ����)�� ���

Fig. 18. The output voltage and the forced duty-cycle value under a load current decrease.

The duty-cycle value is evaluated by the non linear controller by the means of fixed parameters and the VVAR value which is obtained by monitoring the output voltage. The difference between the output voltage and VVAR is monitored and compared to the maximum steady-state output voltage ripple VOUT\_STEADY. If the condition (30) is

���� � ���� � ������������ (30)

module, RL the inductor parasitic resistance and Vin the converter input voltage.

continuously verified over a fixed TFSS time, the non-linear control action ends.

Further design guidelines could be found in (Boscaino et al. 2009, 2010).

where Vout is the regulated output voltage, �� is the average inductor current of a single

(27)

(28)

(29)

period is a tunable parameter to achieve high design flexibility.

From (27), defining the KR constant as:

the forced DNL value is obtained:

$$
\sigma'\_{ref} = V\_{ref} - V\_{LOAD} \tag{24}
$$

In order to achieve the fastest transient response, the gain factor KNL is introduced. Hence, *v*'REF is given by:

$$v\_{ref}' = V\_{ref} - K\_{NL}V\_{LOAD} \tag{25}$$

The KNL value is designed by the frequency response analysis to ensure the fastest effective gain under transients avoiding loop instabilities. Under transients, the difference between the output voltage and VVAR is monitored and compared with the maximum steady-state output voltage ripple VOUT\_STEADY. If the condition (26) is continuously verified over TSTEADY time, the non-linear control action ends.

$$\text{Vout} - V\_{VAR} < \Delta V\_{OUT\\_STEADY} \tag{26}$$

Fig. 17. Non linear control signals under a load current increase.

Under a load current decrease, the non-linear control loop modifies the duty-cycle signal, as shown in Fig.18. All modules are simultaneously turned off to allow the inductor current to decrease as fast as possible. Turning off all modules allows the fastest transient response. Unfortunately, the system is driven towards a loop upsetting and thus to an increase, instead of a reduction, of the output voltage over-and-under shoots. Then, a fixed duty-cycle is forced to all modules according to the interleaved technique. Known the VVAR value, the new steady-state duty-cycle is evaluated and forced by the non-linear subsystem to maintain a regulated output voltage during linear loop resettling. The false steady-state period is a tunable parameter to achieve high design flexibility.

$$D\_{NL} = \frac{Vout + \overline{I\_L}R\_L}{Vin} \tag{27}$$

where Vout is the regulated output voltage, �� is the average inductor current of a single module, RL the inductor parasitic resistance and Vin the converter input voltage. From (27), defining the KR constant as:

$$K\_R = \frac{4R\_L}{Rc} \tag{28}$$

the forced DNL value is obtained:

168 MATLAB for Engineers – Applications in Control, Electrical Engineering, IT and Robotics

system independently of the specific converter topology and linear loop architecture. Thanks to the AVP technique, load transients are detected by an instantaneous drop of the output voltage, and the increasing or decreasing load current transient is detected by monitoring the output voltage drop in terms of sign and width. Two different non-linear control actions are implemented: under a load current increase (*case a*) or decrease (*case b*). The reference voltage (*case a*) or the duty-cycle (*case b*) is modified by the non-linear control loop. Under increasing load current steps, the non-linear control loop acts on the reference voltage advancing the linear loop action. Two auxiliary signals, VVAR and VLOOP, are defined: VVAR is the output voltage value related to the new steady-state condition while VLOOP is the output voltage

In order to achieve the fastest transient response, the gain factor KNL is introduced. Hence,

The KNL value is designed by the frequency response analysis to ensure the fastest effective gain under transients avoiding loop instabilities. Under transients, the difference between the output voltage and VVAR is monitored and compared with the maximum steady-state output voltage ripple VOUT\_STEADY. If the condition (26) is continuously verified over TSTEADY

ܸைை ൌ ܸݐݑ െ ܸோ (23)

ᇱ ൌ ܸ െ ܸைை (24)

ᇱ ൌ ܸ െ ܭேܸைை (25)

ܸݐݑ െ ܸோ ൏ οܸை̴்ௌ்ா (26)

ripple during transient referred to VVAR value, as shown in Fig.17.

*v*'REF is given by:

time, the non-linear control action ends.

ݒ

ݒ

Fig. 17. Non linear control signals under a load current increase.

$$D\_{NL} = \frac{V\_{VAR} + (Vout\_{I=0} - V\_{VAR})K\_R}{Vin} \tag{29}$$

The duty-cycle value is evaluated by the non linear controller by the means of fixed parameters and the VVAR value which is obtained by monitoring the output voltage. The difference between the output voltage and VVAR is monitored and compared to the maximum steady-state output voltage ripple VOUT\_STEADY. If the condition (30) is continuously verified over a fixed TFSS time, the non-linear control action ends.

$$Vout - V\_{VAR} < \Delta V\_{OUT\\_STEADY} \tag{30}$$

Further design guidelines could be found in (Boscaino et al. 2009, 2010).

Fig. 18. The output voltage and the forced duty-cycle value under a load current decrease.

MATLAB Co-Simulation Tools for Power Supply Systems Design 171

Fig. 19. Top level model

a state vector as:

Fig. 20. The State-Space block and the parameter box.

A continuous large-signal model of the buck converter is derived and implemented by the state-space block. The Parasitic components of passive elements as the DC resistance of the inductor (DCR) and the capacitor equivalent series resistor (Rc) are included. Assuming identical MOSFETs, the model accounts for the MOSFET equivalent resistance Rds,on. Define

��(�)�����(�)

��(�)� (32)

�(�) � ���(�)

#### **4. Co-simulation set-up**

Active-HDL provides an interface to MATLAB/Simulink simulation environment which allows co-simulation of functional blocks described by using hardware description languages. The digital controller is tested on a FPGA device. A specific co-simulation procedure should be activated in order to make each VHDL design unit available in Simulink libraries. The VHDL code and signal timing are tested as well. High-accuracy simulation results are obtained heavily reducing experimental fault conditions. The cosimulation procedure features automatic data type conversion between Simulink and Active HDL and simulation results could be displayed in both simulation environments. All VHDL entities are collected in an Active HDL workspace. A MATLAB m-file is generated for each VHDL entity. By right clicking on a VHDL entity, select the option "Generate Block Description for Simulink". The procedure is repeated for each VHDL entity of current Workspace. After generating the m-files, the *Active-HDL Blockset* is available in the Simulink library browser. The *Active-HDL Co-Sim* and *HDL Black-Box* elements are used for system cosimulation. The *Active-HDL Co-Sim* element must be included in the Simulink top level model. The block allows the designer to fix co-simulation parameters. In order to simulate a VHDL entity as an integral part of the current model, a *HDL Black-Box* block should be added and associated to the corresponding m-file by the configuration box. When the model is completed, running simulation from Simulink starts the co-simulation. The connection to the Active-HDL server will be opened and all *HDL Black-Boxes* simulated with the Active-HDL simulator. Input and output waveforms can be analyzed both in Simulink and Aldec environment while internal signal waveforms can be analyzed in Aldec environment only.

#### **5. MATLAB/Simulink model**

The top level model is shown in Fig.19. The power section includes the *Multiphase converter* and the *Current-sense* subsystems. In the *A/D converter* subsystem, the Analog-to-Digital interface is modelled by Simulink library elements. The controller is modelled in Aldec Active-HDL environment and each design unit is included in the *Controller* subsystem. The *Active-HDL Co-Sim* block is added to the top level model.

#### **5.1 The power section model**

The power section includes the multiphase converter and current-sense filters. A fourmodule interleaved synchronous buck converter is connected to the power load. The power section is modelled by Simulink library elements in order to achieve the highest processing speed. The use of several co-simulation tools is avoided, keeping at the same time the highest accuracy. In this paragraph, the Simulink model of the multiphase converter based on a continuous-time large-signal model is described. The proposed modelling technique could be efficiently extended to each switching converter.

In Simulink environment, the State-Space block models a system by its own state-space equations:

$$\begin{aligned} \dot{\mathfrak{X}} &= A\mathfrak{x} + Bu \\ \mathfrak{y} &= \mathfrak{C}\mathfrak{x} + Du \end{aligned} \tag{31}$$

where **x** is the state vector, **u** the input vector and **y** the output vector.

According to (31), the block is fed by the input vector *u* and the output vector *y* is generated. As shown in Fig.20, the designer could enter the matrix coefficients in the parameter box.

Fig. 19. Top level model

Active-HDL provides an interface to MATLAB/Simulink simulation environment which allows co-simulation of functional blocks described by using hardware description languages. The digital controller is tested on a FPGA device. A specific co-simulation procedure should be activated in order to make each VHDL design unit available in Simulink libraries. The VHDL code and signal timing are tested as well. High-accuracy simulation results are obtained heavily reducing experimental fault conditions. The cosimulation procedure features automatic data type conversion between Simulink and Active HDL and simulation results could be displayed in both simulation environments. All VHDL entities are collected in an Active HDL workspace. A MATLAB m-file is generated for each VHDL entity. By right clicking on a VHDL entity, select the option "Generate Block Description for Simulink". The procedure is repeated for each VHDL entity of current Workspace. After generating the m-files, the *Active-HDL Blockset* is available in the Simulink library browser. The *Active-HDL Co-Sim* and *HDL Black-Box* elements are used for system cosimulation. The *Active-HDL Co-Sim* element must be included in the Simulink top level model. The block allows the designer to fix co-simulation parameters. In order to simulate a VHDL entity as an integral part of the current model, a *HDL Black-Box* block should be added and associated to the corresponding m-file by the configuration box. When the model is completed, running simulation from Simulink starts the co-simulation. The connection to the Active-HDL server will be opened and all *HDL Black-Boxes* simulated with the Active-HDL simulator. Input and output waveforms can be analyzed both in Simulink and Aldec environment while internal signal waveforms can be analyzed in Aldec environment only.

The top level model is shown in Fig.19. The power section includes the *Multiphase converter* and the *Current-sense* subsystems. In the *A/D converter* subsystem, the Analog-to-Digital interface is modelled by Simulink library elements. The controller is modelled in Aldec Active-HDL environment and each design unit is included in the *Controller* subsystem. The

The power section includes the multiphase converter and current-sense filters. A fourmodule interleaved synchronous buck converter is connected to the power load. The power section is modelled by Simulink library elements in order to achieve the highest processing speed. The use of several co-simulation tools is avoided, keeping at the same time the highest accuracy. In this paragraph, the Simulink model of the multiphase converter based on a continuous-time large-signal model is described. The proposed modelling technique

In Simulink environment, the State-Space block models a system by its own state-space

ൌ ሶ

ൌ

According to (31), the block is fed by the input vector *u* and the output vector *y* is generated. As shown in Fig.20, the designer could enter the matrix coefficients in the parameter box.

(31)

**4. Co-simulation set-up**

**5. MATLAB/Simulink model**

**5.1 The power section model**

equations:

*Active-HDL Co-Sim* block is added to the top level model.

could be efficiently extended to each switching converter.

where **x** is the state vector, **u** the input vector and **y** the output vector.

Fig. 20. The State-Space block and the parameter box.

A continuous large-signal model of the buck converter is derived and implemented by the state-space block. The Parasitic components of passive elements as the DC resistance of the inductor (DCR) and the capacitor equivalent series resistor (Rc) are included. Assuming identical MOSFETs, the model accounts for the MOSFET equivalent resistance Rds,on. Define a state vector as:

$$\mathbf{x}(t) = \begin{vmatrix} \boldsymbol{\varkappa}\_1(t) \\\\ \boldsymbol{\varkappa}\_2(t) \end{vmatrix} = \begin{vmatrix} \boldsymbol{\iota}\_L(t) \\\\ \boldsymbol{\nu}\_c(t) \end{vmatrix} \tag{32}$$

$$\mathbf{y}(t) = \begin{bmatrix} \mathbf{y}\_1(t) \\\\ \mathbf{y}\_2(t) \end{bmatrix} = \begin{bmatrix} i\_L(t) \\\\ v\_{out}(t) \end{bmatrix} \tag{33}$$

$$\begin{cases} L\dot{\boldsymbol{x}}\_{1}(t) + Rc\mathcal{C}\dot{\boldsymbol{x}}\_{2}(t) = -\dot{R}\_{L}\boldsymbol{x}\_{1}(t) - \boldsymbol{x}\_{2}(t) + l\dot{m} \\\\ \left(R\boldsymbol{c} + R\right)\mathcal{C}\dot{\boldsymbol{x}}\_{2}(t) = R\boldsymbol{x}\_{1}(t) - \boldsymbol{x}\_{2}(t) \end{cases} \tag{34}$$

$$
\begin{bmatrix} L & RcC \\ 0 & (Rc + R)C \end{bmatrix} \mathfrak{x}(t) = \begin{bmatrix} R\_L & -1 \\ R & -1 \end{bmatrix} \mathfrak{x}(t) + \begin{bmatrix} 1 \\ 0 \end{bmatrix} Vin \tag{35}
$$

$$\mathbf{x}(t) = \begin{bmatrix} \frac{R\_L R c + R \{R\_L + R c\}}{\{R c + R\} L} & -\frac{R}{\{R c + R\} L} \\ \frac{R}{\{R c + R\} C} & -\frac{1}{\{R c + R\} C} \end{bmatrix} \mathbf{x}(t) + \begin{bmatrix} 1 \\ 0 \\ 0 \end{bmatrix} V \text{in} \tag{36}$$

$$\begin{cases} L\dot{\boldsymbol{x}}\_{1}(t) + Rc\mathcal{C}\dot{\boldsymbol{x}}\_{2}(t) \stackrel{\cdot}{=} -R\_{L}\boldsymbol{x}\_{1}(t) - \boldsymbol{x}\_{2}(t) \\\\ \{R\boldsymbol{c} + R\}\mathcal{C}\dot{\boldsymbol{x}}\_{2}(t) = R\boldsymbol{x}\_{1}(t) - \boldsymbol{x}\_{2}(t) \end{cases} \tag{37}$$

$$
\begin{bmatrix} L & Rc\mathcal{C} \\ 0 & (Rc+R)\mathcal{C} \end{bmatrix} \mathfrak{X}(t) = \begin{bmatrix} R\_L & -1 \\ R & -1 \end{bmatrix} \mathfrak{x}(t) \tag{38}
$$

$$
\dot{\mathbf{x}}(t) = \begin{bmatrix}
\frac{R\_L R c + R (R\_L + R c)}{(R c + R)L} & -\frac{R}{(R c + R)L} \\
R & -\frac{1}{(R c + R)C} \end{bmatrix} \mathbf{x}(t) \tag{39}
$$

$$\begin{cases} \begin{aligned} \boldsymbol{\chi}\_{1}(t) &= \boldsymbol{\chi}\_{1}(t) \\ \boldsymbol{\chi}\_{2}(t) &= \frac{RcR}{R+Rc} \boldsymbol{\chi}\_{1}(t) + \frac{R}{R+Rc} \boldsymbol{\chi}\_{2}(t) \end{aligned} \tag{40}$$

$$\mathbf{y}(t) = \begin{bmatrix} 1 & 0\\ \frac{RRc}{R+Rc} & \frac{R}{R+Rc} \end{bmatrix} \mathbf{x}(t) \tag{41}$$

$$\mathbf{x}(\mathbf{t}) = \mathbf{A\_{on}} \cdot \mathbf{x}(\mathbf{t}) + \mathbf{b\_{on}} \cdot u(\mathbf{t})$$

$$\mathbf{y}(\mathbf{t}) = \mathbf{C\_{on}} \cdot \mathbf{x}(\mathbf{t}) + \mathbf{d\_{on}} \cdot u(\mathbf{t}) \tag{42}$$

$$\mathcal{A}\_{on} = \begin{bmatrix} \frac{R\_L R c + R (R\_L + R c)}{(R c + R)L} & -\frac{R}{(R c + R)L} \\ & R & 1 \\ \hline \overline{(R c + R)C} & -\frac{1}{(R c + R)C} \end{bmatrix} \tag{43}$$

$$\mathbf{b}\_{\text{on}} = \begin{bmatrix} 1 \\ \hline \\ 0 \end{bmatrix} \tag{44}$$

$$\mathbf{C\_{on}} = \begin{bmatrix} 1 & 0 \\ \frac{\text{RRc}}{\text{R} + \text{Rc}} & \frac{\text{R}}{\text{R} + \text{Rc}} \end{bmatrix} \tag{45}$$

$$\mathbf{d}\_{\rm on} = \begin{bmatrix} 0 \\ 0 \end{bmatrix} \tag{46}$$

$$\mathbf{x}(\mathbf{t}) = \mathbf{A}\_{\rm off} \cdot \mathbf{x}(\mathbf{t}) + \mathbf{b}\_{\rm off} \cdot u(\mathbf{t})$$

$$\mathbf{y}(\mathbf{t}) = \mathbf{C}\_{\rm off} \cdot \mathbf{x}(\mathbf{t}) + \mathbf{d}\_{\rm off} \cdot u(\mathbf{t}) \tag{47}$$

$$\mathbf{A}\_{on} = \begin{bmatrix} \frac{R\_L R c + R \{R\_L + R c\}}{\{R c + R\} L} & -\frac{R}{\{R c + R\} L} \\ & \frac{R}{\{R c + R\} C} & -\frac{1}{\{R c + R\} C} \end{bmatrix} \tag{48}$$

$$\mathbf{b}\_{\rm off} = \begin{bmatrix} \mathbf{0} \\ \mathbf{0} \end{bmatrix} \tag{49}$$

$$\mathbf{C\_{off}} = \begin{bmatrix} 1 & 0 \\ \frac{\text{RRc}}{\text{R} + \text{Rc}} & \frac{\text{R}}{\text{R} + \text{Rc}} \end{bmatrix} \tag{50}$$

$$\mathbf{d}\_{\rm off} = \begin{bmatrix} 0 \\ 0 \end{bmatrix} \tag{51}$$

$$\mathbf{A} \mathbf{=} \mathbf{A}\_{\mathrm{ON}} \mathbf{=} \mathbf{A}\_{\mathrm{OFF}}$$

$$\mathbf{C} \mathbf{=} \mathbf{C}\_{\mathrm{ON}} \mathbf{=} \mathbf{C}\_{\mathrm{OFF}}$$

$$\mathbf{b}\_{\mathrm{OFF}} = \mathbf{0}$$

$$\mathbf{d}\_{\rm ON} = \mathbf{d}\_{\rm OFF} = \mathbf{0} \tag{52}$$

$$q(t) = \begin{cases} 1\,\,during\,\,the\,\,\,ON\,\,time\\ 0\,\,during\,\,the\,\,\,OFF\,\,time \end{cases} \tag{53}$$

$$u(t) = q(t) \cdot V \text{in} \tag{54}$$

$$\mathbf{x}(\mathbf{t}) = \mathbf{A} \cdot \mathbf{x}(\mathbf{t}) + \mathbf{b} \cdot Vm \cdot q(\mathbf{t})$$

$$\mathbf{y}(\mathbf{t}) = \mathbf{\dot{C}} \cdot \mathbf{x}(\mathbf{t}) \tag{55}$$

$$\mathbf{x}(t) = \begin{bmatrix} i\_{L1}(t) \\ i\_{L2}(t) \\ i\_{L3}(t) \\ i\_{L4}(t) \\ v\_c(t) \end{bmatrix} \tag{56}$$

The output vector is defined as:

$$\mathbf{y}(t) = \begin{bmatrix} \iota\_{L1}(t) \\ \iota\_{L2}(t) \\ \iota\_{L3}(t) \\ \iota\_{L4}(t) \\ \upsilon\_{out}(t) \end{bmatrix} \tag{57}$$

MATLAB Co-Simulation Tools for Power Supply Systems Design 177

Fig. 25 shows the Simulink model of the multiphase converter. The input voltage and scalar components of the q vector are the model inputs. The *Mux* block multiplexes scalar components into the input vector **u**. The *Demux* block generates the scalar components of

Fig. 25. Simulink model of a four-module buck converter. Inductor currents are the output

State -Space x' = Ax+Bu y = Cx+Du

Demux

Vout 5 Vsw4 4 Vsw3 3 Vsw2 2 Vsw1 1

Demux

Demux

Demux

Vout 5

> ILeq 6

IL 4 4

IL3 3

IL 2 2

IL 1 1

The proposed model could be adapted to the designer requirements. For example, in Fig.26 another implementation is shown. Besides the inductor current signals and the output voltage, the switching node voltages Vsw of each module are also included in the output vector. Further, the equivalent inductor current instead of the inductor currents as well as switching node voltages are available outside the subsystem. The equivalent current is

> State -Space x' = Ax+Bu y = Cx+Du

obtained as the sum of inductor currents by the means of *Adder* blocks.

Mux

Mux

Fig. 26. Simulink model of the multiphase converter.

Mux

Mux

the output vector **y**(t).

Q 4 5

Q 3 4

Q 2 3

Q 1 2 Vdc 1

The state-space model is obtained:

$$\mathbf{x}(\mathbf{t}) = \mathbf{A} \cdot \mathbf{x}(\mathbf{t}) + \mathbf{b} \cdot Vm \cdot \mathbf{q}(t)$$

$$\mathbf{y}(\mathbf{t}) = \mathbf{\dot{C}} \cdot \mathbf{x}(\mathbf{t})\tag{58}$$

where:

1 1 1 1 1 11 2 2 2 2 2 22 3 3 3 3 3 33 () () () () () () () () () () () () () () ( *C C C C C C C C CC C C CC C C C C CC CC C C C CC C C RR RR R R RR RR RR R LR R LR R LR R LR R LR R RR RR RR R R RR RR R LR R LR R LR R LR R LR R RR RR RR RR R R RR R A LR R LR R LR R LR R LR R* + + − − −− + + + ++ + + −− − − − + + + ++ + + = − −− −− + + + ++ 4 4 4 4 4 44 ) () () () () () 1 () () () () () *C C C C C C C C C CC C C C CC RR RR RR RR RR R R R LR R LR R LR R LR R LR R RR R R CR R CR R CR R CR R CR R* + + − − −− − + + + ++ − + + + ++ (59)

$$B = \begin{bmatrix} \frac{1}{L\_1} & 0 & 0 & 0\\ 0 & \frac{1}{L\_2} & 0 & 0\\ 0 & 0 & \frac{1}{L\_3} & 0\\ 0 & 0 & 0 & \frac{1}{L\_4} \end{bmatrix} \tag{60}$$

$$C = \begin{bmatrix} 1 & 0 & 0 & 0 & 0 \\ 0 & 1 & 0 & 0 & 0 \\ 0 & 0 & 1 & 0 & 0 \\ 0 & 0 & 0 & 1 & 0 \\ \frac{RR\_C}{R + R\_C} & \frac{RR\_C}{R + R\_C} & \frac{RR\_C}{R + R\_C} & \frac{RR\_C}{R + R\_C} & \frac{R}{R + R\_C} \end{bmatrix} \tag{61}$$

$$\mathbf{q}(t) = \begin{bmatrix} q\_1(t) \\ q\_2(t) \\ q\_3(t) \\ q\_4(t) \end{bmatrix} \tag{62}$$

� � � � � ���(�) ���(�) ���(�) ���(�) ����(�)� � � � �

�(�)� =���(�) � � � ��� � �(�) �

1 1 1 11

+ + − − −− + + + ++

*RR RR R R RR RR RR R LR R LR R LR R LR R LR R RR RR RR R R RR RR R LR R LR R LR R LR R LR R RR RR RR RR R R RR R*

*C C C C C*

*C C CC C*

*CC C C C CC C C*

*RR R R*

1

*L*

*B*

=

*C*

*C C*

*RR RR*

2

=

*L*

*A LR R LR R LR R LR R LR R*

+ + = − −− −− + + + ++

*C C C C C*

2 2 2 22

+ + −− − − − + + + ++

3 3 3 33

4 4 4 44

() () () () (

+ + − − −− − + + + ++ − + + + ++

3 3

*C C C CC*

*C C C CC*

() () () () ()

() () () () ()

() () () () ()

*RR RR RR RR RR R R R LR R LR R LR R LR R LR R*

*C C C CC*

*C C C CC*

() () () () ()

3

*L*

+++++

� � � � � ��(�) ��(�) ��(�) ��(�) � � � � �

*RR RR*

01000 00100 00010 00001

> *C C*

�(�) =

*RR RR*

*C C*

4

*L*

*CR R CR R CR R CR R CR R*

2 2

�(�) =���(�) � (58)

4 4

*C C*

*RR R*

*C*

*RR RR*

(57)

)

 (59)

(60)

(61)

(62)

*C*

1

�(�) =

The output vector is defined as:

The state-space model is obtained:

1 1

where:

Fig. 25 shows the Simulink model of the multiphase converter. The input voltage and scalar components of the q vector are the model inputs. The *Mux* block multiplexes scalar components into the input vector **u**. The *Demux* block generates the scalar components of the output vector **y**(t).

Fig. 25. Simulink model of a four-module buck converter. Inductor currents are the output vector components.

The proposed model could be adapted to the designer requirements. For example, in Fig.26 another implementation is shown. Besides the inductor current signals and the output voltage, the switching node voltages Vsw of each module are also included in the output vector. Further, the equivalent inductor current instead of the inductor currents as well as switching node voltages are available outside the subsystem. The equivalent current is obtained as the sum of inductor currents by the means of *Adder* blocks.

Fig. 26. Simulink model of the multiphase converter.

MATLAB Co-Simulation Tools for Power Supply Systems Design 179

Fig. 28. The Controller subsystem.

Fig. 29. The non-linear controller.

#### **5.2 The sense network**

Current sense filters are modelled by their own Laplace transfer function using the *Transfer Function* block. In the parameter box the coefficients of the Laplace function are entered. The *low-pass filter* subsystem of the master phase is shown in Fig.27.

Fig. 27. Current-sense filters of the master module.

#### **5.3 The digital controller model**

The digital controller is modelled as the collection of VHDL entities, each one described by the VHDL code in Active-HDL environment. By the co-simulation procedure, each design unit is added to the Simulink model and simulated among the others. The Simulink model of the *Controller* subsystem is shown in Fig.28. Two subsystems are highlighted: the *Non\_linear\_controller* and the *Linear\_Controller.* VHDL entities are collected in the *Controller*  subsystem. The 6.25MHz system clock is derived from the 50MHz clock signal available from the FPGA device by the means of a digital clock divider, described in the *clock\_div* entity. VHDL entities are linked in Simulink environment. Note that modelling the digital controller by multiple entities is a unique choice of the designer. Instead of modelling the controller by a unique VHDL entity, authors suggest a multiple entities approach to monitor internal signal of the FPGA controller in Simulink environment. The co-simulation procedure allows the designer to test the VHDL code, including timing between entities. The digital controller is thus tested as closely as possible to the effective FPGA implementation.

Each VHDL entity accomplishes a specific task of the digital controller: soft-start, protection circuits for safe operation, adaptive voltage positioning and the strictly-named controller implementing the sophisticated control algorithm, as shown in Fig.29. The co-simulation procedure as well as the proposed modelling approach allows the designer to test each available function by behavioural simulations, thus reducing the risk of experimental fault conditions.

In the *Linear Controller*, the error signal is converted to analog by the DAC subsystem and then compared to the analog saw-tooth within the PWM generator. The interleaved technique is digitally implemented. Fig.30 shows the switching logic subsystem of the master phase. The *f1\_sim* VHDL entity is fed by the master phase PWM signal and nonlinear control signals. The unit generates the q-signal for the master module. The digital counter which generates the switching clocks (*SwCk*) of all slave modules is modelled by the *acc\_sint* VHDL unit.

Current sense filters are modelled by their own Laplace transfer function using the *Transfer Function* block. In the parameter box the coefficients of the Laplace function are entered. The *low-pass filter* subsystem of the master phase is shown in Fig.27. Low-pass filter subsystems

The digital controller is modelled as the collection of VHDL entities, each one described by the VHDL code in Active-HDL environment. By the co-simulation procedure, each design unit is added to the Simulink model and simulated among the others. The Simulink model of the *Controller* subsystem is shown in Fig.28. Two subsystems are highlighted: the *Non\_linear\_controller* and the *Linear\_Controller.* VHDL entities are collected in the *Controller*  subsystem. The 6.25MHz system clock is derived from the 50MHz clock signal available from the FPGA device by the means of a digital clock divider, described in the *clock\_div* entity. VHDL entities are linked in Simulink environment. Note that modelling the digital controller by multiple entities is a unique choice of the designer. Instead of modelling the controller by a unique VHDL entity, authors suggest a multiple entities approach to monitor internal signal of the FPGA controller in Simulink environment. The co-simulation procedure allows the designer to test the VHDL code, including timing between entities. The digital controller is thus tested as closely as possible to the effective FPGA

Each VHDL entity accomplishes a specific task of the digital controller: soft-start, protection circuits for safe operation, adaptive voltage positioning and the strictly-named controller implementing the sophisticated control algorithm, as shown in Fig.29. The co-simulation procedure as well as the proposed modelling approach allows the designer to test each available function by behavioural simulations, thus reducing the risk of experimental fault

In the *Linear Controller*, the error signal is converted to analog by the DAC subsystem and then compared to the analog saw-tooth within the PWM generator. The interleaved technique is digitally implemented. Fig.30 shows the switching logic subsystem of the master phase. The *f1\_sim* VHDL entity is fed by the master phase PWM signal and nonlinear control signals. The unit generates the q-signal for the master module. The digital counter which generates the switching clocks (*SwCk*) of all slave modules is modelled by the

are fed by the switching node voltage of the corresponding power module.

Fig. 27. Current-sense filters of the master module.

**5.3 The digital controller model**

implementation.

conditions.

*acc\_sint* VHDL unit.

**5.2 The sense network**

Fig. 28. The Controller subsystem.

Fig. 29. The non-linear controller.

MATLAB Co-Simulation Tools for Power Supply Systems Design 181

The available *Quantizer* block allows the user to set the voltage resolution while the number

The S*aturation* block is thus cascaded to the *Quantizer* in order to set the full scale range. The

where Vres is the voltage resolution and Nlev the number of levels. The discrete output of the *Saturation* block should be coded. In order to simulate the ADC coding, the *Gain* block is cascaded to the saturation block. The output of the ADC model is the equivalent decimal

K = FS

The C*onversion Delay* block accounts for the input-output delay of the modelled A/D

The Simulink model of the digital-to-analog converter is shown in Fig.32. The subsystem is fed by a digital signal and generates a discrete analog signal. The maximum value of the

where Nbit,dac is the converter bit resolution. The maximum value of the output voltage is equal to the DAC full scale voltage. The digital-to-analog converter is modelled by a gain

> K��� = FS��� 2��������

In order to model the full scale range of the converter, a *Saturation* block is cascaded with the

The PWM comparator is fed by the analog error signal and the analog current sense signal. The analog comparator model is shown in Fig.33. An adder block is used as the input stage of the comparator. The *Relay* block models the non-linearity of the comparator. The Relay block allows its output to switch between two specified values. The state of the relay is obtained by comparing the input signal to the specified thresholds, the *Switch-off point and the Switch-on point* parameters. When the relay is on, it remains on until the input drops below the value of the *Switch-off point* parameter. When the relay is off, it remains off until the input exceeds the value of the *Switch-on point* parameter. The parameter box allows the

2���� ∙ (2���� − 1) (64)

2���� (65)

���� = 2�������� − 1 (66)

analog 1

(67)

High = V��� ∙ N��� = FS

where Nbit is the bit resolution and FS the full scale voltage.

number of the binary vector. The conversion gain is given by:

gain block. Saturation levels are equal to the full scale range.

Fig. 32. The Simulink model of a digital-to-analog converter.

DAC Gain Saturation

Conversion Delay digital

of levels is yet unlimited.

converter.

factor Kdac:

input signal is given by:

**5.5 PWM comparator model**

1

high-level saturation limit is given by:

Fig. 30. The Switching Logic model of the master module.

#### **5.4 Analog-digital interface**

Co-simulation features are to be well-understood before implementing a mixed-mode model. ALDEC and Simulink automatically code common signals. In ALDEC environment signals are coded as signed binary vectors. The output of each HDL block is thus a binary vector. Simulink automatically codes binary vectors by the equivalent decimal number. HDL block inputs are Simulink signals thus coded as decimal numbers. ALDEC environment codes decimal numbers as the equivalent signed binary vector. The Simulink model should account for binary-decimal data conversion. Digital to analog converters and analog to digital converters are introduced in the Simulink model.

The A/D converter section includes two A/D converters, each modelled as shown in Fig.31 by the means of elementary blocks of Simulink libraries.

Fig. 31. The A/D converter model

The input signal is sampled at the clock frequency by the *Triggered Zero-Order Hold* block. Since in the Simulink library browser only an ideal symmetrical *Quantizer* block is provided, a non-ideal A/D converter model is achieved by adding the horizontal shift. The horizontal shift constant is given by:

$$\mathcal{C} = \frac{\text{FS}}{\text{Z}^{\text{Nbit} + 1}} \tag{63}$$

Co-simulation features are to be well-understood before implementing a mixed-mode model. ALDEC and Simulink automatically code common signals. In ALDEC environment signals are coded as signed binary vectors. The output of each HDL block is thus a binary vector. Simulink automatically codes binary vectors by the equivalent decimal number. HDL block inputs are Simulink signals thus coded as decimal numbers. ALDEC environment codes decimal numbers as the equivalent signed binary vector. The Simulink model should account for binary-decimal data conversion. Digital to analog converters and

The A/D converter section includes two A/D converters, each modelled as shown in Fig.31

The input signal is sampled at the clock frequency by the *Triggered Zero-Order Hold* block. Since in the Simulink library browser only an ideal symmetrical *Quantizer* block is provided, a non-ideal A/D converter model is achieved by adding the horizontal shift. The horizontal

FS

2������ (63)

C =

Fig. 30. The Switching Logic model of the master module.

analog to digital converters are introduced in the Simulink model.

by the means of elementary blocks of Simulink libraries.

**5.4 Analog-digital interface**

Fig. 31. The A/D converter model

shift constant is given by:

where Nbit is the bit resolution and FS the full scale voltage.

The available *Quantizer* block allows the user to set the voltage resolution while the number of levels is yet unlimited.

The S*aturation* block is thus cascaded to the *Quantizer* in order to set the full scale range. The high-level saturation limit is given by:

$$\text{High} = \text{V}\_{\text{res}} \cdot \text{N}\_{\text{lev}} = \frac{\text{FS}}{\text{2^{Nbit}}} \cdot (\text{2^{Nbit}} - 1) \tag{64}$$

where Vres is the voltage resolution and Nlev the number of levels. The discrete output of the *Saturation* block should be coded. In order to simulate the ADC coding, the *Gain* block is cascaded to the saturation block. The output of the ADC model is the equivalent decimal number of the binary vector. The conversion gain is given by:

$$\mathbf{K} = \frac{\mathbf{F}\mathbf{S}}{2^{\mathbf{N}\text{bit}}} \tag{65}$$

The C*onversion Delay* block accounts for the input-output delay of the modelled A/D converter.

The Simulink model of the digital-to-analog converter is shown in Fig.32. The subsystem is fed by a digital signal and generates a discrete analog signal. The maximum value of the input signal is given by:

$$V \text{max} = 2^{N\_{\text{bit,dac}}} - 1 \tag{66}$$

where Nbit,dac is the converter bit resolution. The maximum value of the output voltage is equal to the DAC full scale voltage. The digital-to-analog converter is modelled by a gain factor Kdac:

$$\mathbf{K\_{dac}} = \frac{\mathbf{F\_{disc}}}{\mathbf{Z^{N\_{bit,dac}}}} \tag{67}$$

In order to model the full scale range of the converter, a *Saturation* block is cascaded with the gain block. Saturation levels are equal to the full scale range.

Fig. 32. The Simulink model of a digital-to-analog converter.

#### **5.5 PWM comparator model**

The PWM comparator is fed by the analog error signal and the analog current sense signal. The analog comparator model is shown in Fig.33. An adder block is used as the input stage of the comparator. The *Relay* block models the non-linearity of the comparator. The Relay block allows its output to switch between two specified values. The state of the relay is obtained by comparing the input signal to the specified thresholds, the *Switch-off point and the Switch-on point* parameters. When the relay is on, it remains on until the input drops below the value of the *Switch-off point* parameter. When the relay is off, it remains off until the input exceeds the value of the *Switch-on point* parameter. The parameter box allows the

MATLAB Co-Simulation Tools for Power Supply Systems Design 183

Fig. 35. Steady-state waveforms under 115A load current. At the top the output voltage, at

Fig. 36. Dynamic response to a 0-120A load current step without the non-linear control. At the top the output voltage, at the bottom the equivalent current waveforms are shown.

Fig. 37. Dynamic response to a 120A-0 load current step without the non-linear control. At the top the output voltage, at the bottom the equivalent current waveforms are shown.

the bottom the equivalent current waveforms are shown.

end user to set a specified value for both on and off conditions. In this model, the output value is equal to "1" in the on-state, "0" in the off-state.

Fig. 33. The Simulink model of the PWM comparator.

#### **6. Simulation results**

A 12V/1V@120A four-module buck converter has been designed and modelled in Simulink-Aldec mixed environment. Each power module operates at 250kHz switching frequency. Simulation results are shown to highlight the high accuracy of the modelling approach. Steady-state waveforms under 1A load are shown in Fig.34. At the top the output voltage waveform, at the bottom the equivalent inductor current is shown. The proposed modelling approach allows the designer to simulate the system behaviour within the switching period achieving high accuracy results. The output voltage ripple and the current ripple are accurately modelled. The DC set point of the output voltage is fixed at the nominal value. The output voltage, at the top, and the equivalent current, at the bottom, under 115A load are shown in Fig.35. The DC set point is fixed at 0.96V at full load due to the implemented AVP technique.

The system is tested under load current transients to evaluate the non-linear control performances. Under a 0-120A load current step, if the non linear controller is disabled the system behaviour shown in Fig.36 is obtained. Under a 120A -0 load current step, if the non linear controller is disabled the system behaviour shown in Fig.37 is obtained. The output voltage, at the top, and the equivalent current, at the bottom, are shown. Note that the proposed design approach accurately models the system behaviour within the switching period as well as under large-signal transients.

Fig. 34. Steady-state waveforms under 1A load current. At the top the output voltage, at the bottom the equivalent current waveforms are shown.

end user to set a specified value for both on and off conditions. In this model, the output

Relay 1

Out 1 1

A 12V/1V@120A four-module buck converter has been designed and modelled in Simulink-Aldec mixed environment. Each power module operates at 250kHz switching frequency. Simulation results are shown to highlight the high accuracy of the modelling approach. Steady-state waveforms under 1A load are shown in Fig.34. At the top the output voltage waveform, at the bottom the equivalent inductor current is shown. The proposed modelling approach allows the designer to simulate the system behaviour within the switching period achieving high accuracy results. The output voltage ripple and the current ripple are accurately modelled. The DC set point of the output voltage is fixed at the nominal value. The output voltage, at the top, and the equivalent current, at the bottom, under 115A load are shown in Fig.35. The DC set point is fixed at 0.96V at full load due to the implemented

The system is tested under load current transients to evaluate the non-linear control performances. Under a 0-120A load current step, if the non linear controller is disabled the system behaviour shown in Fig.36 is obtained. Under a 120A -0 load current step, if the non linear controller is disabled the system behaviour shown in Fig.37 is obtained. The output voltage, at the top, and the equivalent current, at the bottom, are shown. Note that the proposed design approach accurately models the system behaviour within the switching

Fig. 34. Steady-state waveforms under 1A load current. At the top the output voltage, at the

value is equal to "1" in the on-state, "0" in the off-state.

Fig. 33. The Simulink model of the PWM comparator.

+ 1

period as well as under large-signal transients.

bottom the equivalent current waveforms are shown.

**6. Simulation results**

AVP technique.

Fig. 35. Steady-state waveforms under 115A load current. At the top the output voltage, at the bottom the equivalent current waveforms are shown.

Fig. 36. Dynamic response to a 0-120A load current step without the non-linear control. At the top the output voltage, at the bottom the equivalent current waveforms are shown.

Fig. 37. Dynamic response to a 120A-0 load current step without the non-linear control. At the top the output voltage, at the bottom the equivalent current waveforms are shown.

MATLAB Co-Simulation Tools for Power Supply Systems Design 185

(Boscaino et al., 2010). The high accuracy of the proposed design approach is here discussed by the comparison of simulation and experimental results. Experimental waveforms in Fig.40 show the system behaviour under 120A load current square-wave obtained by disabling the non-linear control (a), and by enabling the non-linear control (b). Ch1 shows the output voltage (200mV/div), Ch3 shows the master module inductor current (10A/div)

The great potential of the proposed design approach relies in the performance evaluation of the designed controller. Under load transients, the recovery time as well as the percentage of drop reduction due to the non linear control accurately matches experimental results. The system behaviour is perfectly matched by simulation results. Evaluating system performances by simulation or experimental results leads to the same conclusions. A detail of Fig.40 under the rising edge of the load current square wave is shown in Fig.41: (a) the linear controller response, (b) the non-linear controller response. As shown by experimental results, under the load current rising-edge, the under-shoot of the output voltage is reduced

A detail of Fig.40 under the falling edge of the load current square wave is shown in Fig.42: at the left the linear controller response, at the right the non-linear controller response. By comparing experimental waveforms in Fig.42 the output voltage over-shoot under a load current falling edge is reduced by 28%. Under both transients, the recovery time is reduced by 25%.

(a)

(b)

Fig. 40. System behaviour under a 115A width load current square wave. Ch1 shows the output voltage (200mV/div), Ch3 shows the master module inductor current (10A/div) and Ch4 shows the load current (60A/div). (a) The non-linear control is disabled. (b) The non-

and Ch4 shows the load current (60A/div).

by 29%.

linear controller is enabled.

Fig.38 and 39 show the dynamic response to a 0-120A and 120A-0 load current step, respectively, obtained by enabling the non-linear controller.

Fig. 38. Dynamic response to a 0-120A load current step with the non-linear control. At the top, the output voltage. At the top the output voltage, at the bottom the equivalent current waveforms are shown.

Fig. 39. Dynamic response to a 120A-0 load current step with the non-linear control. At the top the output voltage, at the bottom the equivalent current waveforms are shown.

As shown by simulation results, the non linear controller ensures a reduction of the output voltage over- and-under-shoots during large-signal transients. Under the rising edge of the load current step, the output voltage under-shoot is reduced by 22%. Under the falling edge of the load current step, the output voltage over-shoot is reduced by 26%. The recovery time is reduced by 24%. The instantaneous output voltage change due to the capacitor ESR is included. Note that the instantaneous drop is not affected by the non-linear control.

#### **7. Experimental results**

A laboratory prototype has been realized to test the efficiency of the non-linear control algorithm. Experimental validation of the non linear control algorithm has been proposed in

Fig.38 and 39 show the dynamic response to a 0-120A and 120A-0 load current step,

Fig. 38. Dynamic response to a 0-120A load current step with the non-linear control. At the top, the output voltage. At the top the output voltage, at the bottom the equivalent current

Fig. 39. Dynamic response to a 120A-0 load current step with the non-linear control. At the

As shown by simulation results, the non linear controller ensures a reduction of the output voltage over- and-under-shoots during large-signal transients. Under the rising edge of the load current step, the output voltage under-shoot is reduced by 22%. Under the falling edge of the load current step, the output voltage over-shoot is reduced by 26%. The recovery time is reduced by 24%. The instantaneous output voltage change due to the capacitor ESR is

A laboratory prototype has been realized to test the efficiency of the non-linear control algorithm. Experimental validation of the non linear control algorithm has been proposed in

top the output voltage, at the bottom the equivalent current waveforms are shown.

included. Note that the instantaneous drop is not affected by the non-linear control.

respectively, obtained by enabling the non-linear controller.

waveforms are shown.

**7. Experimental results**

(Boscaino et al., 2010). The high accuracy of the proposed design approach is here discussed by the comparison of simulation and experimental results. Experimental waveforms in Fig.40 show the system behaviour under 120A load current square-wave obtained by disabling the non-linear control (a), and by enabling the non-linear control (b). Ch1 shows the output voltage (200mV/div), Ch3 shows the master module inductor current (10A/div) and Ch4 shows the load current (60A/div).

The great potential of the proposed design approach relies in the performance evaluation of the designed controller. Under load transients, the recovery time as well as the percentage of drop reduction due to the non linear control accurately matches experimental results. The system behaviour is perfectly matched by simulation results. Evaluating system performances by simulation or experimental results leads to the same conclusions. A detail of Fig.40 under the rising edge of the load current square wave is shown in Fig.41: (a) the linear controller response, (b) the non-linear controller response. As shown by experimental results, under the load current rising-edge, the under-shoot of the output voltage is reduced by 29%.

A detail of Fig.40 under the falling edge of the load current square wave is shown in Fig.42: at the left the linear controller response, at the right the non-linear controller response. By comparing experimental waveforms in Fig.42 the output voltage over-shoot under a load current falling edge is reduced by 28%. Under both transients, the recovery time is reduced by 25%.

Fig. 40. System behaviour under a 115A width load current square wave. Ch1 shows the output voltage (200mV/div), Ch3 shows the master module inductor current (10A/div) and Ch4 shows the load current (60A/div). (a) The non-linear control is disabled. (b) The nonlinear controller is enabled.

MATLAB Co-Simulation Tools for Power Supply Systems Design 187

tools. For the highest processing speed, a modelling technique for the power section is proposed. The digital subsystems are described by VHDL source code and verified by Aldec/Simulink co-simulation tool, allowing the test of the VHDL code and timing between separate entities. As an application, the model of a multiphase dc-dc converter for VRM applications is described. Thanks to the available co-simulation tool, all provided functions such as soft-start, protection algorithms for safe operation and adaptive voltage positioning are accurately modelled and verified during behavioural simulations. As shown by simulation results, the proposed model matches the system behaviour both within the switching period and during load transients. The design approach allows the designer to simulate the system behaviour as closely as possible to the effective behaviour, modelling and testing the "effective" controller. The controller performances are evaluated by simulation and experimental results leading to the same conclusions. Authors suggest the co-simulation tool for mixed-mode system and complex architectures. Actually, the IC implementation of the proposed controller in BCD6S technology is carried on. A central unit for signal processing is introduced. Mathematical operations are time-multiplexed in order to speed up the input-output delay in the control loop. The co-simulation tool is already

Authors would like to thank ST Microelectronics for supporting this research activity.

Vol.39, No. 12, (December 2008), pp. 1852-1859, ISSN:0026-2692.

*Motion,* ISBN:<PHONE_NUMBER>87-3, Pisa, Italy, June 2010.

Science, ISBN 0-7923-7270-0, USA.

Basso, C. (2008). *Switch-mode Power Supplies*, McGraw Hill, ISBN 978-0-07-150859-0,

Boscaino, V., Livreri, P., Marino, F. & Minieri, M. (2008). Current-Sensing Technique for

Boscaino, V., Livreri, P., Marino, F. & Minieri, M. (2009). Linear-non-linear digital control for

Erickson, R. & Maksimovic, D. (2001). *Fundamentals of Power Electronics (2nd ed),* Springer

Kaichun, R. et al. (October 2010). Matlab Simulations for Power Factor Correction

Miftakhutdinov, R. (June 2001). Optimal Design of Interleaved Synchronous Buck Converter

*Conference,* ISBN 0-7803-7067-8, Vancouver, BC, Canada, June 2001.

*Energy Systems,* Vol.29, No.1, (March, 2009), pp. 38-47, ISSN: 10783466. Boscaino, V., Gaeta, Capponi, G. & M., Marino, F. (2010). Non-linear digital control

Current-Mode Controlled Voltage Regulator Modules. *Microelectronics Journal*,

dc/dc converters with fast transient response. *International Journal of Power and*

improving transient response: Design and test on a multiphase VRM, *Proceedings of the International Symposium on Power Electronics, Electrical Drives, Automation and*

of Switching Power, In: *Matlab -Modelling, Programming and Simulations*, Emilson Pereira Leite, pp. 151-170, Scyio, ISBN 978-953-307-125-1, Vukovar,

at High Slew-Rate Load Current Transients. IEEE *Power Electronics Specialists*

used to test the efficiency of the implemented solution.

**9. Acknowledgements**

**10. References**

USA.

Croatia.

Fig. 41. System behaviour under the load current rising-edge. Ch1 shows the output voltage (50mV/div, AC coupling), Ch3 shows the master module inductor current (10A/div) and Ch4 shows the load current (60A/div). At the left, the non-linear control is disabled. At the right, the non-linear controller is enabled.

Fig. 42. System behaviour under the load current falling-edge. Ch1 shows the output voltage (50mV/div, AC coupling), Ch3 shows the master module inductor current (10A/div) and Ch4 shows the load current (60A/div). At the left, the non-linear control is disabled. At the right, the non-linear controller is enabled.

#### **8. Conclusion**

In this chapter, a high-accuracy design approach for power supply systems is proposed. Mixed-mode systems are modelled in Simulink environment using powerful co-simulation tools. For the highest processing speed, a modelling technique for the power section is proposed. The digital subsystems are described by VHDL source code and verified by Aldec/Simulink co-simulation tool, allowing the test of the VHDL code and timing between separate entities. As an application, the model of a multiphase dc-dc converter for VRM applications is described. Thanks to the available co-simulation tool, all provided functions such as soft-start, protection algorithms for safe operation and adaptive voltage positioning are accurately modelled and verified during behavioural simulations. As shown by simulation results, the proposed model matches the system behaviour both within the switching period and during load transients. The design approach allows the designer to simulate the system behaviour as closely as possible to the effective behaviour, modelling and testing the "effective" controller. The controller performances are evaluated by simulation and experimental results leading to the same conclusions. Authors suggest the co-simulation tool for mixed-mode system and complex architectures. Actually, the IC implementation of the proposed controller in BCD6S technology is carried on. A central unit for signal processing is introduced. Mathematical operations are time-multiplexed in order to speed up the input-output delay in the control loop. The co-simulation tool is already used to test the efficiency of the implemented solution.

#### **9. Acknowledgements**

Authors would like to thank ST Microelectronics for supporting this research activity.

#### **10. References**

186 MATLAB for Engineers – Applications in Control, Electrical Engineering, IT and Robotics

(a)

(b)

Fig. 41. System behaviour under the load current rising-edge. Ch1 shows the output voltage (50mV/div, AC coupling), Ch3 shows the master module inductor current (10A/div) and Ch4 shows the load current (60A/div). At the left, the non-linear control is disabled. At the

Fig. 42. System behaviour under the load current falling-edge. Ch1 shows the output voltage (50mV/div, AC coupling), Ch3 shows the master module inductor current (10A/div) and Ch4 shows the load current (60A/div). At the left, the non-linear control is disabled. At the

In this chapter, a high-accuracy design approach for power supply systems is proposed. Mixed-mode systems are modelled in Simulink environment using powerful co-simulation

right, the non-linear controller is enabled.

right, the non-linear controller is enabled.

**8. Conclusion**

**8**

*Italy*

**High Accuracy Modelling of**

Valeria Boscaino and Giuseppe Capponi

This chapter proposes a modelling approach based on the PSIM/Simulink co-simulation toolbox for hybrid power supplies, featuring high accuracy. Hybrid source performances are fully tested during behavioural simulations. The importance of high-accuracy modelling is investigated and modelling guidelines for both power sources and load are given for further applications. The Simulink model is analyzed and the efficiency of the proposed approach is

In the last few years, hybrid power supplies are investigated for a wide variety of application areas: two primary sources are coupled to take advantages of both, overcoming their drawbacks. The growing interest in hybrid sources is mainly due to the spread of fuel cells. Fuel cells are renewable energy sources, fed by an external fuel and thus potentially infinite source of energy. The fuel cell supplies power until the fuel is supplied to, thus ensuring potentially infinite life cycle to each power load. Automotive, residential and portable electronics are only a few examples of fuel cells application areas. Powering a portable electronic device by a fuel cell is still a challenge for the scientific world. With the aid of fuel cells, the full portability is achieved: electronics devices could be recharged by simply replacing the fuel cartridge instead of being connected to the power grid. Further, fuel cells ensure the highest energy density allowing higher and higher device run time. Yet, portable devices feature a pulsed power consumption profile which depends on the user-selected function. The required peak power is usually higher and higher than the average power. Since the response of fuel cells to instantaneous power demands is relatively poor, innovative solutions are investigated to take full advantage from the fuel cell use. The goal is to couple the fuel cell with a high power density component. The instantaneous peak power is supplied by the high power density component while the average power is supplied by the fuel cell itself. Specific power management algorithms for active power sharing are required. Life-cycle and transient response are directly controlled thus leading to a close dependence of the power management control algorithms on the related application and power load. In the last few years, authors experienced the importance of accurate modelling of both power source and load to evaluate the system performances since the simulation step. The efficiency of power management algorithms is ensured by the high accuracy of source, power load and power

verified by the comparison between simulation and experimental results.

**1. Introduction**

management system modelling.

**Hybrid Power Supplies**

*University of Palermo*

### **High Accuracy Modelling of Hybrid Power Supplies**

Valeria Boscaino and Giuseppe Capponi *University of Palermo Italy*

#### **1. Introduction**

188 MATLAB for Engineers – Applications in Control, Electrical Engineering, IT and Robotics

Pop, O. & Lungu, S. (October 2010). Modelling of DC-DC Converters, In: *Matlab -Modelling,*

Pressman, A. & Billings, K. (2009). *Switching Power Supply Design* (*3rd ed*.), McGraw Hill,

953-307-125-1, Vukovar, Croatia.

ISBN 978-0-07-148272-1, USA.

*Programming and Simulations*, Emilson Pereira Leite, pp. 125-150, Scyio, ISBN 978-

This chapter proposes a modelling approach based on the PSIM/Simulink co-simulation toolbox for hybrid power supplies, featuring high accuracy. Hybrid source performances are fully tested during behavioural simulations. The importance of high-accuracy modelling is investigated and modelling guidelines for both power sources and load are given for further applications. The Simulink model is analyzed and the efficiency of the proposed approach is verified by the comparison between simulation and experimental results.

In the last few years, hybrid power supplies are investigated for a wide variety of application areas: two primary sources are coupled to take advantages of both, overcoming their drawbacks. The growing interest in hybrid sources is mainly due to the spread of fuel cells.

Fuel cells are renewable energy sources, fed by an external fuel and thus potentially infinite source of energy. The fuel cell supplies power until the fuel is supplied to, thus ensuring potentially infinite life cycle to each power load. Automotive, residential and portable electronics are only a few examples of fuel cells application areas. Powering a portable electronic device by a fuel cell is still a challenge for the scientific world. With the aid of fuel cells, the full portability is achieved: electronics devices could be recharged by simply replacing the fuel cartridge instead of being connected to the power grid. Further, fuel cells ensure the highest energy density allowing higher and higher device run time. Yet, portable devices feature a pulsed power consumption profile which depends on the user-selected function. The required peak power is usually higher and higher than the average power. Since the response of fuel cells to instantaneous power demands is relatively poor, innovative solutions are investigated to take full advantage from the fuel cell use. The goal is to couple the fuel cell with a high power density component. The instantaneous peak power is supplied by the high power density component while the average power is supplied by the fuel cell itself. Specific power management algorithms for active power sharing are required. Life-cycle and transient response are directly controlled thus leading to a close dependence of the power management control algorithms on the related application and power load. In the last few years, authors experienced the importance of accurate modelling of both power source and load to evaluate the system performances since the simulation step. The efficiency of power management algorithms is ensured by the high accuracy of source, power load and power management system modelling.

High Accuracy Modelling of Hybrid Power Supplies 191

Simulink model and linked to the PSIM netlist file by the block parameter box. The *SimCoupler* block now behaviours as a Simulink subsystem showing input and output ports as specified in the corresponding PSIM schematic: the Simulink output nodes are the subsystem input ports and the Simulink input nodes are the subsystem output ports. The PSIM schematic is simulated as an integral part of the active Simulink model. The efficiency of the Simulink-based modelling technique is shown by the comparison between simulation

Hybrid power sources have received a great deal of attention in the last few years and they are considered the most promising source of energy for portable applications. Two basic sources are coupled: a high energy density and a high power density source. The goal is to optimize the power and energy performances of the composite power source. Each basic source supplies the load current under a specific working condition, as steady-state or transient, according to its own stand-alone performances. The high energy density source, i.e. fuel cell, supplies the load current under steady-state. Simultaneously, under a load transient the high power density component, i.e. battery or supercapacitor, supplies the load with the difference between the instantaneous and the steady-state load current. The controller is accurately designed to correctly manage the power flow between primary sources and load. If properly controlled, the hybrid source is neither influenced by the transient response of the high energy density source nor by the running time of the high power density source. If compared with stand-alone basic sources, the hybrid source shows

longer running time, faster transient response, higher power and energy density.

electronics, weapon systems, as well as for industrial applications.

as a battery charger, leading to a decrease in system cost and weight.

In literature, battery-ultracapacitor or fuel cell-battery power supply systems are presented (Gao &Dougal, 2003; Alotto et al., 2008). Coupling a battery and an ultracapacitor yields higher specific power than a battery-alone source and higher specific energy than an ultracapacitor-alone source. In the meantime higher running time is achieved. Research on battery/ultracapacitor hybrids has been actively carried out for electric vehicles, portable

In literature hybrids are classified in active and passive sources. Direct coupling is a passive hybrids feature while in active hybrids a DC-DC converter is interposed between the two basic sources. Several advantages are brought by the DC/DC converter. A detailed comparative analysis of a battery/supercapacitor hybrid in passive and active configuration is reported in (Gao & Dougal, 2003). The active hybrid configuration ensures an increase in power capability, a better regulation of the output voltage, a minimization of the current ripple and a reduction of the system weight and volume. If a capacitor based hybrid is considered, since the voltage of the two basic sources may be different, the capacitor array size could be designed independently of the other primary source. The DC-DC converter plays an important role in regulating the output voltage and making the voltage of the two basic sources independent of each other. The active hybrids ensure higher power capability than passive hybrids since the power sharing is directly controlled by the switching converter. Further, in active hybrids the output voltage is independent of the discharge curve of its stand-alone sources. In battery-based hybrids, the DC/DC converter can also act

Yet, all described hybrid systems are designed and tested with regular pulsed load, featuring a square wave current profile. The frequency and width of the current profile are

and experimental results.

**2. Hybrid power supply architectures**

The choice of a powerful simulation environment is a key step for a successful conclusion of the overall design process. The power consumption profile of the specific load device should be deeply analyzed to ensure proper control algorithms. Load emulators best fit designers' requirements. During behavioural simulations, emulators allow the designer to virtually use the load device reproducing the effective power consumption profile. Hence, no assumptions are made on the load power consumption profile while designing the power management algorithms avoiding the risk of experimental failures.

Fuel cell modelling is a critical step since fuel cells are non linear devices whose performances are heavily affected by temperature, fuel pressure and voltage-current operating conditions. Since electro-chemical, physical and geometrical parameters are not readily available to applications engineers, a black-box approach is usually preferred to an analytical one. Both steady-state and dynamic behaviour should be accurately modelled in order to design an efficient power supply design. In this chapter, an accurate modelling approach is proposed.

As an application, a fuel cell – supercapacitor hybrid power supply for portable applications is designed and tested. The proposed system supplies a Digital Still Camera (DSC). Like any other portable device, the digital still camera behaviours as a pulsed load. Unlike the others, the power consumption profile features three possible standby modes (playback, photography and movie mode), each one requiring a specific average current value. The load power consumption profile is closely dependent on the user-selected function and thus unpredictable. Consequently, the DSC represents the worst-case portable device for hybrid power supply design and optimization. Note that accurate modelling is required for testing purposes only. Useful information about the DSC state is reproduced by sampling the supply voltage. The power load, a Fujifilm S5500 Digital Still Camera is modelled in Simulink environment with the aid of the *Stateflow* toolbox. A user-interactive interface is provided. During behavioural simulations, the designer is able to select a specific DSC function and the corresponding power consumption profile is emulated. The fuel cell is modelled in Simulink environment. The architecture and modelling technique is suitable for each fuel cell type and power level. The proposed fuel cell model has been implemented by authors in several simulation environments like PSIM, Simulink and PSPICE and further implementations are readily available in literature. Yet, authors suggest the Simulink implementation to achieve low-complexity, high accuracy and the highest processing speed. On the basis of the Simulink model, a FPGA-based fuel cell emulator has been realized. With the aid of the fuel cell emulator, preliminary tests could be performed saving hydrogen reserve. A circuit implementation of the analog controller in PSIM environment is proposed. PSIM by Powersim Inc. is a circuit simulation software oriented to power electronics systems. Furthermore, a Matlab/PSIM co-simulation tool allows behavioural simulation in a mixed environment. In the basic package, PSIM consists of two programs: PSIM Schematics, full-featured schematic-entry program and SIMVIEW, advanced waveforms viewer software. As soon as the PSIM schematic is built, the designer is able to start the co-simulation procedure. In PSIM Elements/Control Library, the *SimCoupler Module* is provided for Matlab/Simulink co-simulation. Simulink input and output nodes are available. The Simulink input nodes receive values from Simulink and behaviour as voltage sources while the output nodes send values to Simulink. Input and output nodes can be placed in the PSIM schematics according to co-simulation requirements. After generating the circuit netlist in PSIM environment, the PSIM procedure for system cosimulation is completed. In Simulink, the *SimCoupler* block can be added to the existing

The choice of a powerful simulation environment is a key step for a successful conclusion of the overall design process. The power consumption profile of the specific load device should be deeply analyzed to ensure proper control algorithms. Load emulators best fit designers' requirements. During behavioural simulations, emulators allow the designer to virtually use the load device reproducing the effective power consumption profile. Hence, no assumptions are made on the load power consumption profile while designing the power

Fuel cell modelling is a critical step since fuel cells are non linear devices whose performances are heavily affected by temperature, fuel pressure and voltage-current operating conditions. Since electro-chemical, physical and geometrical parameters are not readily available to applications engineers, a black-box approach is usually preferred to an analytical one. Both steady-state and dynamic behaviour should be accurately modelled in order to design an efficient power supply design. In this chapter, an accurate modelling

As an application, a fuel cell – supercapacitor hybrid power supply for portable applications is designed and tested. The proposed system supplies a Digital Still Camera (DSC). Like any other portable device, the digital still camera behaviours as a pulsed load. Unlike the others, the power consumption profile features three possible standby modes (playback, photography and movie mode), each one requiring a specific average current value. The load power consumption profile is closely dependent on the user-selected function and thus unpredictable. Consequently, the DSC represents the worst-case portable device for hybrid power supply design and optimization. Note that accurate modelling is required for testing purposes only. Useful information about the DSC state is reproduced by sampling the supply voltage. The power load, a Fujifilm S5500 Digital Still Camera is modelled in Simulink environment with the aid of the *Stateflow* toolbox. A user-interactive interface is provided. During behavioural simulations, the designer is able to select a specific DSC function and the corresponding power consumption profile is emulated. The fuel cell is modelled in Simulink environment. The architecture and modelling technique is suitable for each fuel cell type and power level. The proposed fuel cell model has been implemented by authors in several simulation environments like PSIM, Simulink and PSPICE and further implementations are readily available in literature. Yet, authors suggest the Simulink implementation to achieve low-complexity, high accuracy and the highest processing speed. On the basis of the Simulink model, a FPGA-based fuel cell emulator has been realized. With the aid of the fuel cell emulator, preliminary tests could be performed saving hydrogen reserve. A circuit implementation of the analog controller in PSIM environment is proposed. PSIM by Powersim Inc. is a circuit simulation software oriented to power electronics systems. Furthermore, a Matlab/PSIM co-simulation tool allows behavioural simulation in a mixed environment. In the basic package, PSIM consists of two programs: PSIM Schematics, full-featured schematic-entry program and SIMVIEW, advanced waveforms viewer software. As soon as the PSIM schematic is built, the designer is able to start the co-simulation procedure. In PSIM Elements/Control Library, the *SimCoupler Module* is provided for Matlab/Simulink co-simulation. Simulink input and output nodes are available. The Simulink input nodes receive values from Simulink and behaviour as voltage sources while the output nodes send values to Simulink. Input and output nodes can be placed in the PSIM schematics according to co-simulation requirements. After generating the circuit netlist in PSIM environment, the PSIM procedure for system cosimulation is completed. In Simulink, the *SimCoupler* block can be added to the existing

management algorithms avoiding the risk of experimental failures.

approach is proposed.

Simulink model and linked to the PSIM netlist file by the block parameter box. The *SimCoupler* block now behaviours as a Simulink subsystem showing input and output ports as specified in the corresponding PSIM schematic: the Simulink output nodes are the subsystem input ports and the Simulink input nodes are the subsystem output ports. The PSIM schematic is simulated as an integral part of the active Simulink model. The efficiency of the Simulink-based modelling technique is shown by the comparison between simulation and experimental results.

#### **2. Hybrid power supply architectures**

Hybrid power sources have received a great deal of attention in the last few years and they are considered the most promising source of energy for portable applications. Two basic sources are coupled: a high energy density and a high power density source. The goal is to optimize the power and energy performances of the composite power source. Each basic source supplies the load current under a specific working condition, as steady-state or transient, according to its own stand-alone performances. The high energy density source, i.e. fuel cell, supplies the load current under steady-state. Simultaneously, under a load transient the high power density component, i.e. battery or supercapacitor, supplies the load with the difference between the instantaneous and the steady-state load current. The controller is accurately designed to correctly manage the power flow between primary sources and load. If properly controlled, the hybrid source is neither influenced by the transient response of the high energy density source nor by the running time of the high power density source. If compared with stand-alone basic sources, the hybrid source shows longer running time, faster transient response, higher power and energy density.

In literature, battery-ultracapacitor or fuel cell-battery power supply systems are presented (Gao &Dougal, 2003; Alotto et al., 2008). Coupling a battery and an ultracapacitor yields higher specific power than a battery-alone source and higher specific energy than an ultracapacitor-alone source. In the meantime higher running time is achieved. Research on battery/ultracapacitor hybrids has been actively carried out for electric vehicles, portable electronics, weapon systems, as well as for industrial applications.

In literature hybrids are classified in active and passive sources. Direct coupling is a passive hybrids feature while in active hybrids a DC-DC converter is interposed between the two basic sources. Several advantages are brought by the DC/DC converter. A detailed comparative analysis of a battery/supercapacitor hybrid in passive and active configuration is reported in (Gao & Dougal, 2003). The active hybrid configuration ensures an increase in power capability, a better regulation of the output voltage, a minimization of the current ripple and a reduction of the system weight and volume. If a capacitor based hybrid is considered, since the voltage of the two basic sources may be different, the capacitor array size could be designed independently of the other primary source. The DC-DC converter plays an important role in regulating the output voltage and making the voltage of the two basic sources independent of each other. The active hybrids ensure higher power capability than passive hybrids since the power sharing is directly controlled by the switching converter. Further, in active hybrids the output voltage is independent of the discharge curve of its stand-alone sources. In battery-based hybrids, the DC/DC converter can also act as a battery charger, leading to a decrease in system cost and weight.

Yet, all described hybrid systems are designed and tested with regular pulsed load, featuring a square wave current profile. The frequency and width of the current profile are

High Accuracy Modelling of Hybrid Power Supplies 193

closely related to the actual mode: 180mA for playback mode, 330mA for photography mode and 440mA for movie mode. Each available function requires a pulsed current over the entire function run time. The load current profile under turning-on in playback mode is shown at the left in Fig.1. At the end of function transient, the required load current is strictly constant at 180mA. Yet, during the transient, the peak current reaches 486mA and the run time is equal to 1.24s. The load current profile under the zoom function in playback mode is shown at the right in Fig.1. The transient time is equal to 88.4ms and the peak current reaches 351mA. The average current value over the function transient time is equal to 269mA. If compared with turning-on in playback mode, the transient time is quite short and the peak current value is quite similar to the average current value. Hence, the zoom

Fig. 1. At the left, the DSC current profile under turning-on in playback mode (100mA/div) is shown. Time base is set to 200ms/div. At the right, the DSC current profile under zoom

The load current profile under turning-on the DSC in photography mode is shown at the left in Fig.2. At the end of transient the current is constant at 330mA which is the standby current of the photography mode. Yet, under function running, the load current reaches a 611mA peak value and the transient time is equal to 4.6s. The load current profile required for taking picture without flash is shown at the right in Fig.2. The transient time is equal to 2.9s. The peak current value is equal to 716mA and the average current over the transient time is equal to 443mA. The load current under movie mode selection is shown at the left in

(100mA/div) is shown. Time base is set to 500ms/div. At the right, the DSC current profile under taking picture without flash (100mA/div) is shown. Time base is set at 500ms/div.

Fig. 2. At the left, the DSC current profile under turning-on in photography mode

function in playback mode (100mA/div) is shown. Time base is set at 20ms/div.

function is not critical for the hybrid power supply.

usually assumed as design ratings by control algorithms, even if these assumptions are not verified by commercial devices. If tested with commercial devices, these algorithms would lead to an accidental turning-off or alternatively to a weak optimization of the hybrid power source in terms of both running time and power capability. A fuel cell/supercapacitor active hybrid system supplying a digital still camera is presented. A buck converter is interposed between the primary sources. The specific load device affects system ratings and the architecture of the hybrid source but not the control algorithm. Even under stress, an accidental turning-off is avoided. A high-accuracy model is proposed for both power sources and load. The importance of modelling is confirmed by the comparison between simulation and experimental results.

#### **3. The importance of measurements**