**Figure 5.76:** Settling time of the reactive current for the DSRF- and EPMAF-PLL during type A faults considering a tolerance band of 0*.*1 pu.

**Figure 5.78:** Grid currents **i**dq of the VOC with LSRF-PLL during fault clearing at 0.1 s with current references step to **i** ∗ dq*,*PLL = [1 0]T and delayed active current provision derived with the SSM and numerical model (Num. LSM).

second for the active current. This fact can be used to speed up the reactive current response by introducing a delay in the active current increase. In the presented test, the settling time of the reactive current using an LSRF-PLL is reduced from 106 ms without active current delay to 2.4 ms with an active current delay using a low-pass filter with *τ* = 0*.*6 s. This solution highly decreases the probability of overvoltage and converter tripping during fault clearing.

With the proposed solution, the dynamics of the fault clearing are no longer critical for the transient behavior of the converter current, and the PLL design and evaluation can focus on the settling time constraints introduced by the reactive current response during fault initiation. This constraint contains a maximum settling time of 60 ms in accordance with [11] and becomes critical due to the coupling mechanism of the PLL.

The dynamic performance of the analyzed PLLs for both derived design parameter sets (*ζ*0*.*7 and *ζ*opt) can be compared regarding their settling times of the reactive current. The settling times of both PLL designs presented in Fig. 5.79 and 5.80 are derived with the LSMs and show the expected dependency on the fault scenario. All PLLs achieve shorter settling times

**Figure 5.79:** Settling time of the estimated phase angle of the LSRF- and Nf-PLL during type A faults considering a tolerance band of 0.1 pu and the two design parameter sets based on the *ζ*0*.*7 and *ζ*opt optimization.

**Figure 5.80:** Settling time of the estimated phase angle of the DSRF- and EPMAF-PLL during type A faults considering a tolerance band of 0.1 pu and the two design parameter sets based on the *ζ*0*.*7 and *ζ*opt optimization.

for *ζ*opt in comparison to *ζ*0*.*7, particularly, for smaller *V* +. Only the Nf-PLL has significantly shorter settling times for *ζ*0*.*7 during faults with small *V* +. However, in the critical range of 0*.*5 pu *< V* + *<* 0*.*8 pu, the settling is significantly decreased with the optimum design. Using this design, the Nf-PLL based current control achieves conformity with the grid codes, since *t*set*,i*q *<* 60 ms for all fault scenarios. The other three analyzed PLLs are not able to meet this requirement.

This section presents the detailed description and modeling of the coupling mechanism between the converter current control and the PLL during severe faults. Moreover, the impact of the chosen scenarios on the PLL design is analyzed. The results confirm that the maximum power factor distortions can be directly designed by the immunity to voltage distortions of PLLs. However, to evaluate the current dynamics based on the estimated phase angle error is not straightforward since they are dominated by the coupling of dq-components during phase angle jumps. A delay in the active current reference after fault clearing may solve this problem. This solution does not work for the fault initiation, though, due to grid code requirements. Hence, the PLLs must be designed to meet the dynamic requirements on the settling time of the reactive current. In the presented tests, only the Nf-PLL is able to meet the settling time requirement in all fault scenarios. This is achieved by optimizing both design parameters, i.e., *ω*c and *ζ*, since the design with *ζ*0*.*7 also fails.

The presented PLL evaluation is comparable since all PLLs are designed with the same optimization objective and application scenarios. However, in the case of the DSRF-PLL, the SSM does not predict its instability, so that the DSRF performance based on this design cannot be directly compared. This problem is solved by a multi-fidelity model-based design process for PLLs proposed and presented in the next section.

### **5.7 Multi-Fidelity Model-based Design for PLLs under Severe Grid Disturbances**

The proposed SSM-based PLL design is applicable for most of the analyzed PLLs. However, mainly the SSM of the DSRF-PLL fails to predict the estimated phase angle settling time accurately, and even worse cannot capture the transient stability boundary of the design parameter space. A similar problem can be expected with the DSOGI-PLL since it is described with the same SSM, and thus relies on the same assumptions. In order to overcome this problem, other design processes from the literature propose to limit the bandwidth of the PLLs to one/fifth of the notch-characteristic [124]. This rule is only a general guideline and may be too conservative to achieve a fast settling time.

The SSM-based design process was presented in section 5.4 and an overview of the process steps is shown in Fig. 5.45. The immunity to distortions evaluation utilizes the SSMs that show sufficient accuracy for the harmonics in the investigated range. Contrarily, the estimated phase angle settling times show significant differences between the SSM and LSM. These differences are not surprising since the investigated transient scenarios contain substantial voltage sags and phase angle jumps. The SSM completely neglects the ANS, and in the case of the DSRF and DSOGI, the phase angle and frequency feedback to the filters, respectively. So, the LSM should be used for more accurate settling time evaluations. Moreover, the LSM is able to predict transient stability phenomena such as the instability of the DSRF-PLL or DSOGI-PLL.

The presented design process in section 5.4 is modified, so that the settling time of the estimated phase angle is extracted with the LSM during a type A fault with |*Z*F|=0.05 pu, |*Z*S |=1 pu, *r*F=0 pu, and *r*S=1 pu, and *f*1 = 50 Hz. The LSM-based design typically increases the computational burden of the optimization. Consequently, a multi-fidelity approach is chosen to limit this burden. First, the design parameter combinations are reduced to the valid parameter sets that comply with the necessary immunity to distortions. Second, the settling times of *δ* are simulated with the LSM only for the valid parameter sets.

The resulting settling time of phase angle error *t*set*,δ* is presented in Fig. 5.82 for the DSRF-PLL and shows significant differences to the SSM results in Fig. 5.81. A large subset of the design parameter space leads to an unstable step response of the DSRF-PLL. This transient instability region, which cannot be predicted by the SSM, limits the maximum bandwidth. This is critical since the SSM-based design leads to design parameters that are located in the unstable region of the design parameter space. Hence, in the case of the DSRF-PLL, an SSM-based design is prone to instability.

The LSM-based design also enables the design process to optimize the DSOGI-PLL without relying on the equivalence to the DSRF. Although, the optimum design parameters extracted with the SSM lead to an unstable PLL comparable to the DSRF, the results also show significant differences. The stable design parameter space reaches significantly higher control

**Figure 5.81:** Angle error settling time *t*set*,δ* of the DSRF-PLL for different design parameter sets *ω*c and *ζ* extracted with the SSM and identification of the set for minimum settling time considering the maximum distortion criteria.

**Figure 5.82:** Angle error settling time *t*set*,δ* of the DSRF-PLL for different design parameter sets *ω*c and *ζ* extracted with the LSM and identification of the set for minimum settling time considering the maximum distortion criteria.

**Figure 5.83:** Angle error settling time *t*set*,δ* of the DSOGI-PLL for different design parameter sets *ω*c and *ζ* extracted with the LSM and identification of the set for minimum settling time considering the maximum distortion criteria.

bandwidth for the DSOGI, and thus enables faster dynamics. Unfortunately, the stable parameter combinations next to the maximum distortion boundary, which is indicated by ˆ*δ*wc, show a small stability margin and high sensitivity to fault parameters. Therefore, control bandwidths of *ω*c *>* 130 rad*/*s are not considered in the optimization.

The multi-fidelity optimization is applied to all analyzed PLLs and the results are summarized in Table 5.5. The LSRF and EPMAF show only minor differences between the SSM-based and LSM-based designs. The design parameters of the other PLLs change significantly. The control bandwidths of the DSRF is almost halved, and the DSRF bandwidth is decreased by 33%. The Nf-PLL bandwidth increases by 31%, but this change is mainly caused by an extension of the damping ratio range to 0 *< ζ <* 2.

The LSM-based design achieves much faster settling times of the converter current for the DSOGI, DSRF, and Nf-PLL, as shown in Fig. 5.84 and 5.85. The DSOGI and DSRF are Chapter 5. Modeling, Design, and Characterization of Phase-Locked-Loops during Grid Faults

**Table 5.5:** Design parameter results for the LSM-based optimization process. The values in brackets indicate the change in comparison to the SSM-based design.

**Figure 5.84:** Settling time of the estimated phase angle of the DSRF- and DSOGI-PLL during type A faults considering a tolerance band of 0.1 pu.

**Figure 5.85:** Settling time of the estimated phase angle of the Nf- and EPMAF-PLL during type A faults considering a tolerance band of 0.1 pu.

stable until *V* + *<* 0*.*05, which is sufficient for most grid codes. Moreover, they do not exceed the maximum settling time of 60 ms anymore, and the DSOGI achieves a slightly lower settling time in most scenarios. The Nf-PLL could further improve its settling time and is still below the limit of 60 ms for all scenarios. With the multi-fidelity model-based design, the design parameter optimization can be improved due to its more accurate settling time data. But particularly for the DSRF and DSOGI, the LSM-based design is crucial since the instability finally affects the suitable design parameter space. It identifies the transient stability boundary in the design space and reveals the differences between DSRF and DSOGI. Accordingly, the DSOGI-PLL achieves shorter settling times than the DSRF in a broader grid fault operating range.

The presented optimization consists of a robust design framework and process to conduct comparative studies of PLLs with optimized design to comply with grid codes considering the power factor distortion and reactive current settling time. The model-based design identifies PLL properties and possible improvements such as optimization of control bandwidth and damping, identification of critical coupling mechanism of the PLLs with the current control, rejection of overvoltages after fault clearing by active current delay, and identification of the transient stability boundary for the design parameters of the DSRF- and DSOGI-PLL.

The LSM-based design framework can capture the transient stability phenomena of PLLs during faults, because it can accurately describe the input-output characteristics. However, it is not suitable for deriving analytical stability criteria. Therefore, the next section presents the analytical assessment of transient stability for PLLs with prefilter.

#### **5.8 Transient Stability Phenomena caused by the PLL**

The PLLs may show instability phenomena that cannot be explained with Linear Time-Invariant (LTI)-models. These phenomena are closely related to the Loss of Synchronization (LOS) as one of the most critical scenarios for converter-based generation units [143], [8], [144]. The instability mechanism is complex since it is caused by the interaction of the current control with the PLL in weak grids and the trigonometric function sin(*δ*) introduced by Park's transformation. Hence, it is influenced by the interaction of different equilibria that cannot be captured by LTI-models.

The transient stability of PLLs has attracted much attention, particularly, the interaction with the current control for weak grid conditions [145] [143], [146], [147]. These contributions mainly focus on the SRF-PLL without any prefilter, however, as shown, this PLL is typically not able to meet the required immunity to distortions and bandwidth. With this simplified PLL structure, the phase-portrait technique and the Equal Area Criterion (EAC) can be directly applied since the systems are typically of second-order. Sophisticated PLL structures for unbalanced and distorted grids, e.g., LSRF, DSRF, are often higher-order systems that cannot be directly analyzed with these techniques but with Lyapunov's direct method [98], [148]. An overview of the application of Lyapunov's direct method for higher order PLLs is given in [149]. Recently, Guangyu presented the transient stability analysis for a nonlinear PLL with the same method [150]. However, the evaluation of the transient stability of the LSRF-PLL based on Lyapunov's direct method and the relation to its design based on the Symmetrical Optimum (SO) is still an open point, which will be presented in this section. The large-signal structure of the LSRF-PLL is shown in Fig. 5.86 indicating the states of the system *x*1*, x*2, and *x*3. The nonlinear dynamic matrix **A**(**x**) and its linear equivalent can be obtained from this block diagram and leads to:

$$\dot{\mathbf{X}} = \begin{bmatrix} \dot{x}\_1 \\ \dot{x}\_2 \\ \dot{x}\_3 \end{bmatrix} = \begin{bmatrix} x\_2 + x\_3 k\_\mathrm{p} \\ x\_3 k\_\mathrm{i} \\ -\omega\_\mathrm{f} \left( \hat{V}\_{\mathrm{S},1} \sin \left( x\_1 \right) + x\_3 \right) \end{bmatrix} \qquad \dot{\mathbf{X}}\_{\mathrm{lin}} \Big|\_{\delta\_0 = 0} = \begin{bmatrix} 0 & 1 & k\_\mathrm{p} \\ 0 & 0 & k\_\mathrm{i} \\ -\omega \hat{V}\_{\mathrm{S},1} & 0 & -\omega\_\mathrm{f} \end{bmatrix} \Delta \mathbf{x} \, \, . \tag{5.58}$$

This equation describes the large-signal system dynamics and due to the term sin(*δ*), this system has an infinite count of equilibria on the *x*1-axis or *δ*-axis, respectively.

The derived system equations can be directly verified with the numerical large-signal model since they rely on the same model assumptions, and thus, should yield the same results. The trajectories *x*1(*t*), *x*2(*t*), and *x*3(*t*) of both models for a severe transient process, i.e., a phase angle jump of *π/*2, are shown in Fig. 5.87 and Fig. 5.88, and describe precisley the same

**Figure 5.86:** Block diagram of the nonlinear state-space model of LSRF-PLL.

**Figure 5.87:** Trajectory of the states ˙*δ* and *δ* of the LSRF-PLL for a phase angle jump of *π/*2 calculated with the numerical LSM and the nonlinear statespace model.

**Figure 5.88:** Trajectory of the states ¨*δ* and *δ* of the LSRF-PLL for a phase angle jump of *π/*2 calculated with the numerical LSM and the nonlinear statespace model.

transient process. This finding confirms the expected accuracy of the model according to 5.58. Now, the analysis techniques for nonlinear systems can be applied to this model.

The phase-portrait is a suitable technique to visualize the state-space characteristics of nonlinear systems up to the second-order. The LSRF-PLL is of order three, and thus its phase portrait consist of three dimensions, which cannot be sufficiently visualized. Therefore, only the phase-portrait and velocity plot of the SRF-PLL is presented in Fig. 5.89. The velocity vector **X**˙ can be directly drawn based on 5.58 for any point in the state-space and shows the direction and velocity of the trajectory in the state-space moving forward in time. Hence, deriving the equilibria and analyzing the vector field in the neighborhood of them reveals their stability properties. The equilibria of the system can be divided into Stable Equilibrium Points (SEPs) and Unstable Equilibrium Points (UEPs). For the SEPs, the trajectory converges to these points if the initial condition is in its neighborhood, which indicates asymptotic stability. Contrarily, the trajectories next to the UEPs will move away from these points. These conclusions can be drawn by analyzing the velocity vector **X**˙ in the neighborhood of these equilibria. Exemplary, three initial condition are chosen, and their trajectories are plotted. Two of them are unstable, whereas the third one converges into the origin.

Unfortunately, the phase-portrait, which is often used in recent publications ([143], [146]), is not a suitable technique for analyzing the stability of higher-order PLLs since the interpretation is too complex. So, Lyapunov's method should be applied to achieve analytical stability

**Figure 5.89:** Velocity plot with phase portrait of the SRF-PLL highlighting the SEP and UEPs in the plotted range of *δ* and ˙*δ*.

criteria. It is divided into the indirect method and direct method. The indirect method is still based on the linearized state equations given in 5.58. The direct method is more complex but directly derives the stability properties from the nonlinear system equations [148]. Based on Lyapunov's indirect method, the stability of an equilibrium of a nonlinear system can be proved with the stability of the linear representation, if the system has no eigenvalues *λ*ev on the imaginary axis. The characteristic polynomial can be derived from 5.58 and results in:

$$
\lambda\_{\rm av}^3 + \underbrace{\omega\_{\rm I}}\_{a\_2} \lambda\_{\rm av}^2 + \underbrace{\omega\_{\rm I} \hat{V}\_{\rm S,1} k\_{\rm p}}\_{a\_1} \lambda\_{\rm av} + \underbrace{\omega\_{\rm I} \hat{V}\_{\rm S,1} k\_{\rm i}}\_{a\_0} = 0 \quad . \tag{5.59}
$$

Using the Routh-Hurwitz criterium *a*2*a*1 *> a*0 leads to the criterium for asymptotic stability of the LSRF-PLL design parameters:

$$k\frac{k\_{\rm i}}{\omega\_{\rm f}} - k\_{\rm p} < 0 \quad . \tag{5.60}$$

However, this result does not provide sufficient information in which region of the state-space this property is valid. Therefore, Lyapunov's direct method must be applied: First, the positive definite energy function *V* in 5.61 is defined as Lyapunov candidate that fits for a system with trigonometric terms according to [98], [149]. This function should be positive in the whole state-space except for the analyzed equilibrium **x**0, and thus *V* (**x**0) = 0. The integral is positive in the range of −*π < x*1 *< π* since R *x*1 0 sin(*σ*)d*σ* = 1 − cos(*x*1). The second term is positive if *p*11*p*22 *> p*2 12 according to Sylvester's criterion.

$$V = \int\_0^{x\_1} \sin(\sigma) \mathbf{d}\sigma + \mathbf{x}^T P \mathbf{x} = \int\_0^{x\_1} \sin(\sigma) \mathbf{d}\sigma + \frac{1}{2} \begin{bmatrix} x\_2 & x\_3 \end{bmatrix} \begin{bmatrix} p\_{11} & p\_{12} \\ p\_{12} & p\_{22} \end{bmatrix} \begin{bmatrix} x\_2 \\ x\_3 \end{bmatrix} \tag{5.61}$$

Then, *V*˙ according to 5.62 must be negative definite to conclude that *V* is a Lyapunov function, and thus the equilibrium is locally asymptotically stable. Since the parameters of **P** can be chosen to meet this requirement, 5.62 is rearranged to obtain 5.63, and all terms

that do not contain quadratic state dependencies are set to zero (see 5.64). These operations lead to the definition of **P** in 5.64 that only depends on system parameters.

$$\dot{V} = \sin\left(x\_1\right)\dot{x}\_1 + p\_{11}x\_2\dot{x}\_2 + p\_{22}x\_3\dot{x}\_3 + p\_{12}x\_3\dot{x}\_2 + p\_{12}x\_2\dot{x}\_3\tag{5.62}$$

$$\begin{split} \dot{V} &= \left(1 - p\_{12}\omega\_{1}\hat{V}\_{S,1}\right)\sin\left(x\_{1}\right)x\_{2} + \left(k\_{\rm p} - p\_{22}\omega\_{1}\hat{V}\_{S,1}\right)\sin\left(x\_{1}\right)x\_{3} \\ &+ \left(p\_{11}k\_{\rm i} - p\_{12}\omega\_{1}\right)x\_{3}x\_{2} + \left(p\_{12}k\_{\rm i} - p\_{22}\omega\_{1}\right)x\_{3}^{2} \end{split} \tag{5.63}$$

$$\begin{cases} 1 - p\_{12}\omega\hat{V}\_{S,1} = 0\\ k\_{\rm p} - p\_{22}\omega\hat{V}\_{S,1} = 0 \quad \Rightarrow \qquad \mathbf{P} = \begin{bmatrix} \frac{1}{k\_{1}\hat{V}\_{S,1}} & \frac{1}{\omega\_{1}\hat{V}\_{S,1}}\\ \frac{1}{\omega\_{1}\hat{V}\_{S,1}} & \frac{k\_{\rm p}}{\omega\_{1}\hat{V}\_{S,1}} \end{bmatrix} \end{cases} \tag{5.64}$$

This matrix must be positive definite to comply with the requirement that *V >* 0 except for *V* (**x**0) = 0. This can be checked with Sylvester's criterion *p*11*p*22 *> p*2 12 and leads to the same conclusion as the Routh-Hurwitz criterion that *k*i *ω*f − *k*p *<* 0. Substituting these relations in 5.63 yields

$$
\dot{V} = \left(p\_{12}k\_{\text{i}} - p\_{22}\omega\_{\text{I}}\right)x\_3^2 = \left(\frac{k\_{\text{i}}}{\omega\_{\text{I}}\hat{V}\_{S,\text{1}}} - \frac{k\_{\text{p}}}{\hat{V}\_{S,\text{1}}}\right)x\_3^2 \quad , \tag{5.65}
$$

and

$$
\dot{V} \le 0 \Leftrightarrow \frac{k\_{\rm i}}{\omega\_{\rm f}} - k\_{\rm p} \le 0 \ . \tag{5.66}
$$

Unfortunately, *V*˙ is only semi-positive definite since *x*1 and *x*2 are not included in *V*˙ anymore and thus, the equilibrium is only locally stable and not necessarily locally, asymptotically stable. Lasalle's Invariance Principle must be applied to prove that the system is asymptotically stable. The set *M* = {**x**|*V*˙ = 0} should only contain the trajectory of **x**0, which is in this case the vector [0 0 0]. Checking this criterion leads to the conclusion that the equilibrium **x**0 of the LSRF-PLL is locally asymptotically stable for *k*i *ω*f −*k*p *>* 0 in the interval −*π < x*1 *< π*.

This analysis is validated in simulation for two design parameter sets next to the stability boundary, i.e., *k*i *ω*f − *k*p = −0*.*0015 and 0.0166. Fig. 5.90 and 5.91 show the trajectory for a phase angle jump of *π/*2 for a design parameter set with *k*i *ω*f − *k*p = −0*.*0015. According to the stability criterion, the system should be asymptotically stable. The simulation confirms the stability and the constraints of Lyapunov's method that *V >* 0 ∀*t* and *V*˙ ≤ 0 ∀*t*. The other case with *k*i *ω*f − *k*p = 0*.*0166 also confirms the criterion with *V >* 0 ∀*t* and *V*˙ ≥ 0 ∀*t*, as shown in Fig. 5.92 and 5.93.

**Figure 5.90:** Trajectory of the states ˙*δ* and *δ* of the LSRF-PLL with *k*i *ω*f − *k*p = −0*.*0015 for a phase angle jump of *π/*2 calculated with the nonlinear state-space model.

**Figure 5.92:** Trajectory of the states ˙*δ* and *δ* of the LSRF-PLL with *k*i *ω*f − *k*p = 0*.*0166 for a phase angle jump of *π/*2 calculated with the nonlinear state-space model.

**Figure 5.91:** Lyapunov function *V* and its derivative *V*˙ for the LSRF-PLL with *k*i *ω*f − *k*p = −0*.*0015 for a phase angle jump of *π/*2 calculated with the nonlinear state-space model.

**Figure 5.93:** Lyapunov function *V* and its derivative *V*˙ for the LSRF-PLL with *k*i *ω*f − *k*p = 0*.*0166 for a phase angle jump of *π/*2 calculated with the nonlinear state-space model.

The SO design process can be analyzed with the new insights into the stability behavior and the analytical stability criterion. Including the design rules of the SO according to 5.31-5.33 into the stability criterion *k*i *ω*f − *k*p *<* 0 leads to:

$$\frac{\frac{k\_{\rm p\omega\_c}}{(2\zeta+1)}}{(2\zeta+1)} - \omega\_c = \frac{\omega\_c^2}{(2\zeta+1)^2 \omega\_c} - \omega\_c < 0 \Rightarrow \qquad \zeta > 0 \quad . \tag{5.67}$$

Consequently, if the LSRF-PLL is designed with the SO, it is locally asymptotically stable for all *ω*c and *ζ >* 0 in the interval −*π < x*1 *< π*.

The presented transient stability framework is a potent tool to derive parameter constraints for local asymptotic stability of PLLs. This was proved exemplary for the LSRF as the most simple structure of a PLL with prefilter. However, the application to more complex PLLs is not straightforward because deriving of the criteria gets increasingly complicated with larger system-order. Consequently, the use of Lyapunov's direct method for PLLs with advanced prefilters is still an open research point for a better understanding of the presented instability mechanism.

In summary, this chapter comprises the following results:

Based on these findings, the DSOGI-PLL is identified as PLL with the shortest settling time considering stability and distortion immunity constraints. Consequently, the DSOGI-PLL is used for grid synchronization and sequence decomposition in the following analyses of the grid-following and grid-forming controls.

#### Grid-following Converter Control for Unbalanced Fault Ride-Through Operation Considering Grid Strength

Grid-following control comprises control schemes that rely on a grid synchronization unit. VOC is a mature and widely used control structure of the grid-following controls. It basically consists of a PLL and current control. The previous chapter presents the basic scheme of the VOC (see Fig. 5.63) but mainly focuses on the impact of the PLL on the converter control. Consequently, the previous analysis relies on the following simplifications:

6

This chapter aims to fill these gaps by deriving a complete control structure considering the dual sequence current control with voltage limitation and current reference generators with current limitation. This structure utilizes the tuned DSOGI-PLL developed in the previous chapter. The control performance is evaluated using the previously derived worst-case grid scenarios, which are modified to cover weak grid conditions.

Two types of basic dual sequence controllers are the PI-based or PR-based controls. Four PI-controllers operating in two reference frames, i.e., positive sequence dq-frame and negative sequence dq-frame, are necessary to control both sequence currents [76], [52]. In contrast, both

sequences can be directly controlled in the *αβ*-frame using two PR-controllers [77], [52]. The equivalence between PI-controllers and PR-controllers, in theory, is derived in [151] and [52, pp.151-156], but does not consider the sequence decomposition necessary for realizing a dual sequence control in the dq-frame. Therefore, this chapter presents a thorough comparison between both structures considering the sequence extraction algorithm and explaining the critical controller part by utilizing an SSM.

Besides the control structure, the dynamic performance of current controllers mainly depends on their control parameter design and the voltage limitation of the converter. Consequently, the design process for current controllers is summarized, and different limitation algorithms are compared throughout this section. Finally, a combination of Peak Voltage Limitation (PVL) and Vector Voltage Limitation (VVL) is proposed that guarantees the best trade-off between both limitation concepts, i.e., fast dynamic performance and low Total Harmonic Distortion (THD). The control performance is evaluated for reference steps and grid voltage disturbances. Therefore, the power model presented in chapter 5 is extended to the negative sequence, and the LSM and SSM are experimentally validated using the test bench introduced in chapter 4.2.1.

Once the converter accurately controls the positive and negative sequence current during FRT, it may provide unbalanced currents during unbalanced faults. These unbalanced currents might lead to an unbalanced power injection by the converter. The unbalanced power injection causes double-fundamental frequency oscillations in the power that may propagate to the dc-link of the converter yielding voltage oscillations. An accurate model of these oscillations is derived, and a basic design criterion for the dc-link of grid converters is discussed based on the model assumptions. In the following evaluation of current reference generators, the dc-link oscillations serve as a critical indicator for converter utilization.

The converter may accomplish different control objectives during FRT by adjusting the amount of positive and negative sequence currents. Current reference generators calculate the converter current references based on the measured PCC voltages to achieve control objectives like balancing the voltages or mitigating dc-link oscillations. Several current reference generators and grid support schemes are already presented in the literature [52], [16], [26]. However, the voltage support schemes using VOC show critical implementation problems, and the typical current reference generators are not analyzed regarding their voltage support behavior. To fill this gap, the voltage support of the current reference generators is evaluated considering different grid impedance ratios and SCRs. This evaluation reveals a trade-off between limitation of dc-link voltage oscillations, limitation of the maximum phase voltage, and increasing the minimum phase voltage.

The current reference generators significantly change the stability margin depending on the impedance ratio of the lines and SCR of the grid connection. This stability phenomenon is one of three stability related problems of the VOC. The current control causes the second instability phenomenon, which is analyzed by assessing the stability of the VOC based on PR-controllers under different grid impedance ratios and SCRs. The interaction between current control and PLL dominates the third mechanism, an emerging topic that urgently demands analysis methods to capture the nonlinear dynamics. To fill this gap, a stability analysis framework based on a Lyapunov function is proposed that accurately predicts the Region of Attraction (ROA) of the VOC for generic weak grid scenarios.

### **6.1 Dual Sequence Current Control for Severe Unbalanced Grid Faults and Weak Grid Conditions**

VOC may be implemented with PI-controllers or PR-controllers, but which controller achieves a better control performance? Both control structures are presented in Fig. 6.1. They contain a DSOGI-PLL, frame transformations, the controllers, and a voltage feed-forward. Details on the current controller blocks are shown in section 3.4. For evaluating the controllers, the converter is modeled with a PT1-delay *τ*d, representing the sampling delay and SPWM, and a controlled voltage source neglecting switching patterns.

The main difference between the PI and PR based structure is how they use the estimated phase angle of the PLL *θ* 0 . For the PI control, the measured phase currents **i**1 must be transformed into the dq-frame. In contrast, the reference currents **i** ∗ dq*,*PLL for the PR-controller need to be transformed from the dq-frame into the *αβ*-frame. The PI-controller block or PR-controller block's detailed structures are shown in Fig. 3.12 and 3.13, respectively.

In a first approach, only the positive sequence is considered, and the PLL dynamics are neglected to derive the design parameters and compare both controllers. Both control structures may achieve the same control characteristics, which is proven in theory in [151]. However, this equivalence is only valid for PR-controllers with the coupling terms between the *αβ*-components as described by:

$$\mathbf{v}^\*\_{\text{conv},\alpha\beta} = \begin{bmatrix} k\_\text{p} + k\_\text{r} \frac{s}{s^2 + \omega\_\text{r}^2} & -k\_\text{r} \frac{\omega\_\text{r}}{s^2 + \omega\_\text{r}^2} \\\ k\_\text{r} \frac{\omega\_\text{r}}{s^2 + \omega\_\text{r}^2} & k\_\text{p} + k\_\text{r} \frac{s}{s^2 + \omega\_\text{r}^2} \end{bmatrix} \mathbf{e}\_{\alpha\beta} \tag{6.1}$$

where **v** ∗ conv*,αβ* denotes the reference voltage of the converter and **e***αβ* is the control error of the current control. Throughout the following analysis, this controller is denoted as decoupled PRcontroller. In contrast to this controller definition, the PR-controller is typically implemented without the cross-coupling terms between the *α* and *β*-channel. This implementation is

**Figure 6.1:** VOC using a PI or PR-controller with an averaged converter model and output filter.

equivalent to operate two PR-controllers in parallel, each for the positive and negative sequence, i.e., *ω*r = *ω*1 and *ω*r = −*ω*1, respectively, according to:

$$\begin{split} \mathbf{v}\_{\text{conv},\alpha\beta}^{\*} &= \frac{1}{2} \Biggl( \begin{bmatrix} k\_{\text{p}} + \frac{k\_{\text{s}}s}{s^2 + \omega\_1^2} & \frac{-k\_{\text{s}}\omega\_1}{s^2 + \omega\_1^2} \\ \frac{k\_{\text{s}}\omega\_1}{s^2 + \omega\_1^2} & k\_{\text{p}} + \frac{k\_{\text{s}}s}{s^2 + \omega\_1^2} \end{bmatrix} + \begin{bmatrix} k\_{\text{p}} + \frac{k\_{\text{s}}s}{s^2 + \omega\_1^2} & \frac{-k\_{\text{s}}(-\omega\_1)}{s^2 + \omega\_1^2} \\ \frac{k\_{\text{s}}(-\omega\_1)}{s^2 + \omega\_1^2} & k\_{\text{p}} + \frac{k\_{\text{s}}s}{s^2 + \omega\_1^2} \end{bmatrix} \Biggr) \mathbf{e}\_{\alpha\beta} \tag{6.2} \\ &= \begin{bmatrix} k\_{\text{p}} + k\_{\text{i}}\frac{s}{s^2 + \omega\_1^2} & 0 \\ 0 & k\_{\text{p}} + k\_{\text{i}}\frac{s}{s^2 + \omega\_1^2} \end{bmatrix} \mathbf{e}\_{\alpha\beta} \tag{6.3} \end{split}$$

Fig. 6.2 and 6.3 show the comparison between the PI-controller, decoupled PR-controller, and standard PR-controller for different control bandwidths or time constants *τi*, respectively. A simulation model according to Fig. 6.1 is used assuming *RL*1f=0.2 mΩ, *L*1f=1.2 m*H*, and *V*ˆ S=325 V. The PI and decoupled PR-controller show identical results in the step response. In contrast, the PR-controller without the cross-coupling experiences a comparably large oscillation related to the missing coupling terms. However, this oscillation is not critical for the dynamics since its magnitude is smaller than 10%. Moreover, a larger control bandwidth can reduce this oscillation significantly, as shown in Fig. 6.3.

There are several design methods for current controls of grid converters. The technical and

**Figure 6.2:** Reference step response of *i*d to 16 A for the PI, PR, and decoupled PR-controller designed to a time constant of *τ*i = 1 ms.

**Figure 6.3:** Reference step response of *i*d to 16 A for the PI, PR, and decoupled PR-controller designed to a time constant of *τ*i = 62*.*5 *µ*s.

symmetrical optimum are mature methods for the design [130]. The technical optimum relies on pole-zero cancellation with an "optimum" damping factor of 1*/* √ 2. The symmetrical optimum interprets the RL-load as ideal integrator 1*/sL* in the time range of the current control. More sophisticated approaches consider the sampling delay of the converter [152]. For the control modeling, it can be desirable to achieve a PT1 behavior of the closed-loop current control for reference steps, as presented in chapter 5. The control bandwidth of PI-controllers and PR-controllers can be designed with pole-zero cancellation to achieve this behavior [153]. This design procedure relies on the open-loop transfer function assuming an ideal voltage feed-forward according to:

$$G\_{\rm al,PI,i1}(s) \quad = \underbrace{\left(k\_{\rm p} + k\_{\rm i}\frac{1}{s}\right)}\_{G\_{\rm p1}} \cdot \underbrace{\frac{1}{R\_{L\rm ff} + sL\_{\rm ff}}}\_{G\_{RL}(s)} \cdot \underbrace{\frac{1}{\tau\_{\rm d}s + 1}}\_{G\_{\rm d,env}(s)} = \frac{k\_{\rm p}}{L\_{\rm ff}} \cdot s \cdot \frac{\frac{k\_{\rm i}}{k\_{\rm p}} + s}{\frac{R\_{L\rm ff}}{L\_{\rm ff}} + s} \cdot \frac{1}{\tau\_{\rm d}s + 1} \quad (6.4)$$

The converter sampling and modulation delay *τ*d must be considered if it has the same order of magnitude as the desired bandwidth. The line impedance components *RL*1f and *L*1f introduce a PT1 transfer characteristic that should be canceled by the PI-controller by adjusting the parameters *k*p and *k*i as follows:

$$\frac{k\_{\rm i}}{k\_{\rm p}} = \frac{R\_{\rm 1f}}{L\_{\rm 1f}} \quad , \qquad \tau\_{\rm i} = \frac{L\_{\rm 1f}}{k\_{\rm p}} = \frac{R\_{\rm 1f}}{k\_{\rm i}} \; . \tag{6.5}$$

The resulting time constant *τi* serves as a design parameter for the control bandwidth. The converter sampling delay and SPWM delay are modeled as a PT1-element with *τ*d and lead to the closed-loop transfer function:

$$G\_{\rm o,PI,i1}(s) = \frac{1}{\tau\_i} \cdot \frac{1}{\tau\_d s + 1} \Rightarrow \qquad G\_{\rm c,PI,i1}(s) = \frac{1}{\tau\_d \tau\_i} \cdot \frac{1}{s^2 + \frac{1}{\tau\_d} \, s + \frac{1}{\tau\_d \tau\_i}}\tag{6.6}$$

This transfer function is a second-order system that only depends on *τ*d and *τi*. Hence, the natural frequency *ω*c*,i*1 and corresponding damping ratio *ζ*c*,i*1 can be designed with *τi* for a given *τ*d according to:

$$
\omega\_{c,i1} = \frac{1}{\sqrt{\tau\_d \tau\_i}} \Rightarrow \qquad \zeta\_{c,i1} = \frac{1}{2} \sqrt{\frac{\tau\_i}{\tau\_d}} \ . \tag{6.7}
$$

The design is tested for different damping ratios *ζ*c*,i*1 using a simulation model according to Fig. 6.1 with the parameters *RL*1f=0.2 mΩ, *L*1f=1.2 m*H*, and *V*ˆ S=325 V. The sampling delay is defined to *τ*d = 1*/f*sw = 62*.*5 *µ*s. The current reference of *i*d is changed from 0 A to 16 A to derive the step response. The pole-zero cancellation sufficiently cancels the *R*1f*/L*1f-pole and achieves very similar results for the PI-controller and PR-controller, as shown in Fig. 6.4 and 6.5. Moreover, the step responses indicate that a first-order transfer

**Figure 6.4:** Reference step response of *i*d to 16 A for the PI-controller designed to different damping factors *ζ*c*,i*1 assuming a converter and sampling delay of *τ*d = 62*.*5 *µ*s.

**Figure 6.5:** Reference step response of *i*d to 16 A for the PR-controller designed to different damping factors *ζ*c*,i*1 assuming a converter and sampling delay of *τ*d = 62*.*5 *µ*s.

function *Gi* could sufficiently approximate the closed-loop current control for damping ratios *ζ*c*,i*1 *>* 0*.*7 according to:

$$G\_{c, \text{Pl}, i1}(s)|\_{\zeta\_{c, i1} > 0.7} \approx G\_i(s) = \frac{1}{\tau\_i s + 1} \quad . \tag{6.8}$$

The presented controller comparison only considers the positive sequence component. However, converters need a dual sequence controller for the FRT. The PR-controller intrinsically handles the negative sequence. Contrarily, the PI-controller needs a sequence decomposition to control the positive or negative sequence component with zero steady-state error. The structure is presented in Fig. 6.6, where the current **i**1 is fed back to the controller using a DSOGI to extract the positive sequence current **i** + 1*,αβ*. This DSOGI introduces a filter in the feedback that must be considered during the control design and can be approximated by the transfer function *H*22 given in 5.16. The transfer function of the converter current *G*cl*,*PI*,i*1 can be derived by assuming **i**1*,*dq ≈ **i** ∗ 1*,*dq and *i*1*,*q ≈ 0 and is defined as follows:

$$G\_{\rm cl,PI,i1}(s) = \frac{i\_{\rm d}}{i\_{\rm d}^\*} = \frac{G\_{\rm cl,PI,i1}(s)}{1 + H\_{22}(s)G\_{\rm cl,PI,i1}(s)} \ . \tag{6.9}$$

The DSOGI transfer function *H*22 can be replaced by a PT1 element *G*DSOGI with the time-constant *τ*DSOGI = 1*/*4*f*1 = 5 ms, which yields the simplified closed-loop transfer function:

$$G\_{\rm cl,PI,i1}(s) \approx \frac{G\_{\rm cl,PI,i1}(s)}{1 + G\_{\rm DSOCl}(s)G\_{\rm cl,PI,i1}(s)} \qquad \text{with } \; G\_{\rm DSOCl}(s) = \frac{1}{\tau\_{\rm DSOCl}s + 1} \; . \tag{6.10}$$

The design of the PI-parameters must be adjusted considering the delay *τ*DSOGI. The comparison of the step responses presented in Fig. 6.7 confirms that the PR-controller is much faster than the PI-controller. The PR achieves a rise time of 200 *µ*s, whereas the PI needs 17 ms to reach the reference value. This comparison proves that the sequence

**Figure 6.6:** Structure of the positive-sequence PI-controller with DSOGI.

decomposition slows down the dual sequence PI-control, whereas the PR-controller is much faster. The same step responses are simulated with the SSM given in 6.10 and compared to the time-domain simulation. Fig. 6.8 shows that the SSM cannot describe the slow oscillations but accurately captures the slope of the current step response.

**Figure 6.7:** Reference step response of *i*d to 16 A for the dual-sequence PI and PR-controller assuming a converter and sampling delay of *τ*d = 5 ms and *τ*d = 62*.*5 *µ*s, respectively.

**Figure 6.8:** Reference step response of *i*d to 16 A for the dual-sequence PI-controller simulated with the numerical model, transfer function, and PT1 approximation.

The PR-controller is a fast dual-sequence controller without suffering from the delay of sequence decomposition like the PI-controller. The presented analysis has confirmed this characteristic. Consequently, the PR-controller is identified as a suitable controller and is considered for further analysis.

#### **6.1.1 Voltage Limitation Schemes**

The derived current control must be combined with a voltage limitation to achieve a suitable control performance. The voltage limitation typically deteriorates the current control dynamics since it limits the output voltage of the converter, and thus the maximum converter

**Figure 6.9:** Voltage limitation schemes: (a) PVL; (b) VVL; (c) PDVVL.

current slope in the filter inductance *L*1f. Hence, this section aims to describe a proposed voltage limitation with minimum impact on the controller dynamics.

There are two typical approaches for limiting the voltages: the Peak Voltage Limitation (PVL) and Vector Voltage Limitation (VVL), which are already introduced in section 3.4.3. Moreover, recent approaches propose a limitation of the current reference to guarantee the voltage limits [85], [86]. However, all these structures suffer from the following drawbacks: The PVL leads to harmonics if the limitation is active in steady-state operation. The VVL suffers from poor dynamics since a filter algorithm must extract the fundamental sequence component. These slow dynamics are also a drawback of the current reference limitation, which additionally relies on the measured grid voltages to calculate the maximum current reference to respect the limits of the converter voltage. The main goal of this section is to derive a limitation algorithm that does not suffer from the drawbacks mentioned above.

The structures of the PVL and VVL are presented in Fig. 6.9a and 6.9b, respectively. The PVL simply limits the output voltages of the control to *V*dc/2. The VVL calculates the magnitudes of the controller output voltages and determines a scaling factor to keep the converter voltage amplitudes within the limit of *V*dc/2. This VVL conserves the sinusoidal waveform in the steady-state. Both limitation schemes suffer from the previously mentioned drawbacks. Therefore, the Peak and Delayed Vector Voltage Limitation (PDVVL) is proposed, which combines both strategies to achieve the fast dynamic response of the PVL without suffering from the harmonics in steady-state. It limits the output voltage with a saturation block like the PVL and scales the output voltages to the maximum *V*dc/2 with a delayed magnitude calculation. This limitation guarantees that the VVL is not active during transients, where the maximum output voltage is desirable. In contrast, the PVL is no longer active in the steady-state since the delayed VVL properly limits the fundamental frequency voltages before reaching the saturation block.

The algorithms are tested with a large-signal model of the converter with VOC based on PR-controllers, as presented in Fig. 6.1. The model considers the same parameters as in the previous section and a dc-link voltage of 700 V. A current reference step of 16 A is applied to the controller that triggers the voltage limitation during its transient process. The results are

**Figure 6.10:** Reference step response of *i*d for the PR controller with different limitation algorithms. The controller and limitation are designed to *τ*i = 62*.*5 *µ*s, *τ*lim = 6*.*3 ms, and to *v*lim = 350 V.

**Figure 6.12:** Reference step response of *i*d with *i* ∗ d = 180 A using the PR controller with PVL and PDVVL. The controllers and limitation are adjusted to *τ*i = 62*.*5 *µ*s, *τ*lim = 6*.*3 ms, and *v*lim = 350 V.

**Figure 6.11:** Reference step response of *i*d for the PR controller highlighting the impact of the antiwindup. The controllers and limitation are designed to *τ*i = 62*.*5 *µ*s, *τ*lim = 6*.*3 ms, and *v*lim = 350 V.

**Figure 6.13:** Zoomed reference step response of *i*d for the PR controller using PVL and PDVVL. The controllers and limitation are adjusted to *τ*i = 62*.*5 *µ*s, *τ*lim = 6*.*3 ms, and to *v*lim = 350 V.

shown in Fig. 6.10. The current response without voltage limitation is used as a reference and denoted with w/o. The low-pass filter of the PDVVL is tuned to *τ*lim = 6*.*3 ms in this test. The chosen time constant guarantees a settling time of the vector limitation within *T*1 = 20 ms considering a tolerance band of 3%. All analyzed limitations increase the rise time of the current control. However, the PVL and PDVVL achieve the same rise time, whereas the VVL is much slower. The anti-windup presented in chapter 3 only slightly changes the response characteristics, as shown in Fig. 6.11, and is not analyzed further.

In the steady-state test, a very large current reference of *i* ∗ d = 180 A is chosen to operate the converter in steady-state voltage limitation. The results in Fig. 6.12 and 6.13 expose that the PVL causes low-frequency harmonics in the output current by clipping the output voltage peaks but achieves larger currents due to overmodulation. The PDVVL accurately limits the magnitude of the fundamental frequency voltage component without clipping the voltages. Hence, the proposed PDVVL combines the advantages of the PVL and VVL without suffering from their drawbacks. This voltage limitation is used throughout the following analyses.

The overall current control structure with the proposed voltage limitation (PDVVL) is shown

**Figure 6.14:** Dual sequence current control containing PR-controllers, a DSOGI-PLL and PDVVL.

in Fig 6.14. It tracks the positive and negative sequence current references with short settling times and minor steady-state error. The control performance during severe grid faults is analyzed in the following section.

#### **6.1.2 Evaluation and Modeling of the Dual Sequence Current Control during Severe Voltage Sags and Phase Jumps**

The derived dual sequence control (see Fig 6.14) is tested in the worst-case scenarios identified in chapter 5. This previous analysis has identified type A faults as the most critical scenarios. However, the type A fault does not contain negative sequence voltages and thus cannot be a suitable test scenario for the dual sequence control. For the positive and negative sequence, the type E fault with maximum phase jump ∆ˆ*θ* serves as the most critical scenario. This fault characteristic is achieved by choosing the fault parameter *Z*F=1 pu, which leads to ∆ˆ*θ* ≈ 0*.*41 rad.

The main focus of this section is to test the dual sequence control and analyze how it affects the current step response during unbalanced faults. Therefor, the analytical model in section 5.6 is extended to the negative sequence to describe the fault dynamics of the dual sequence control. In order to obtain the analytical model for the negative sequence, the model of the VOC introduced in section 5.6 is adapted by simply replacing *δ* with −*δ* for the negative sequence, as exemplarily shown in Fig. 6.15 for the reactive currents *i*+ q and *i*− q . Note that *δ* describes the deviation between the grid phase angle *θ* and the estimated phase angle of the PLL *θ* 0 .

At first, only positive or negative sequence reference currents according to the VDE-AR-N 4110 are applied in response to the type E fault to test the current control and verify the analytical model. The fault voltages are depicted in Fig. 6.16. The numerical model according to Fig 6.14 and the analytical model achieve similar results for the current step responses, as shown in Fig. 6.17 and Fig. 6.18. Note that the current *i*dq+ describes the simulated grid current **i**1 transformed with Park's transformation using *θ*, whereas the current *i*dq− corresponds to the grid current transformed with −*θ*. The overall findings are threefold: The results of the numerical model verify the accurate reference tracking of the proposed dual sequence control. Second, approximating the current control with *Gi* given in 6.8 causes

**Figure 6.15:** Analytical model of the dual sequence current control considering PLL dynamics.

**Figure 6.16:** Grid voltages during a type E fault with *Z*F=1 pu and ∆ˆ*θ* ≈ 0*.*41 rad.

**Figure 6.17:** Positive sequence current injection during a type E fault with *Z*F=1 pu and ∆ˆ*θ* ≈ 0*.*41 rad.

**Figure 6.18:** Negative sequence current injection during a type E fault with *Z*F=1 pu and ∆ˆ*θ* ≈ 0*.*41 rad.

only minor deviations in the step responses since the PLL dominates the control dynamics. Third, the comparison between the numerical model and analytical model verify the fidelity of the derived analytical model, which accurately describes the behavior of the dual sequence control for grid faults with phase jumps. This proves that the coupling of the PLL with the current control explained in section 5.6 is also valid for the dual sequence control. However, the negative sequence current response to faults is not critically changed by this coupling effect since the operating points typically do not contain an active current component in the negative sequence.

In contrast to the previous analysis, VDE-AR-N 4110 (see Fig. 3.10) typically requires that the converter injects positive and negative sequence currents simultaneously during unbalanced grid faults (see Fig. 3.10) [11]. The step response of current references with positive and negative sequence are difficult to analyze since the coupling of positive and negative sequence currents leads to double fundamental frequency oscillations in the dq-frame. These oscillations make it difficult to determine the settling time of active and reactive currents without decomposing the sequences of the simulated grid currents. The described

**Figure 6.19:** Grid currents **i**dq+ during positive and negative sequence current injection during a type E fault with *Z*F=1 pu and ∆ˆ*θ* ≈ 0*.*41 rad.

**Figure 6.20:** Grid currents **i**dq− during positive and negative sequence current injection during a type E fault with *Z*F=1 pu and ∆ˆ*θ* ≈ 0*.*41 rad.

characteristic is shown in Fig. 6.19 and Fig. 6.20 for the transformed grid currents *i*dq+ and *i*dq−, respectively. A sequence decomposition such as the DSOGI may calculate the sequence components of the simulated grid currents **i**1 to derive the positive and negative sequence of the grid currents (*i* + dq and *i* − dq), which can then be used to extract the settling times. However, the sequence decomposition introduces a delay due to the necessary sequence decomposition. Especially for short settling times, this delay dominates the dynamics and leads to significant errors in the settling time compared to the real settling time.

Another way to extract the instantaneous sequence components *i* + dq and *i* − dq is based on the derived analytical model of the dual-sequence control (see Fig. 6.15) since it only needs the current references and the estimated phase angle error *δ* to calculate the sequence components of the grid currents.

The step responses of *i*dq+ and *i*dq− presented in Fig. 6.19 and Fig. 6.20 are analyzed again using either the decoupling of the positive and negative sequence based on the DSOGI or the calculation of the analytical model. The comparison of the step responses of the calculated positive and negative sequence currents is shown in Fig. 6.21. The results indicate that the step responses derived with the analytical model accurately track the positive and negative sequence currents. In contrast, the calculation based on the DSOGI significantly alters the original step responses due to the delay of the DSOGI. The analytical model achieves much more accurate results for the settling time, particularly for the negative sequence current response. Here, the post-processing delay of the sequence decomposition changes the extracted settling time from *t*set*,i*q− = 0*.*2 ms to *t*set*,i*q− = 10 ms. Consequently, the proposed analytical model is a potent tool to derive the settling times of the positive and negative sequence currents in simulation.

The presented simulation results prove the low settling time and minor steady-state error of the dual sequence control for grid fault events. However, the control must be tested in a realistic test bench to validate its control characteristics and simulation models finally.

**Figure 6.21:** Positive and negative sequence grid currents **i**+ dq (left) and **i**− dq (right) extracted with DSOGI and analytical model during dual sequence current injection during a type E fault with *Z*F=1 pu and ∆ˆ*θ* ≈ 0*.*41 rad.

**Figure 6.22:** Test bench for the VOC with PS, IGBT4 prototype, and grid emulator.

#### **6.1.3 Experimental Validation of Dual Sequence PR-controllers with Voltage Limitation and Anti-Windup**

The control performance of the dual sequence control and the simulation models are validated with the IGBT4 test bench presented in section 4.2.1. The converter is connected to the grid emulator. The detailed circuit configuration is shown in Fig. 6.22, and Table 4.2 lists the basic parameters. The converter's switching frequency is 16 kHz, the dc-link voltage 700 V, and the phase voltage magnitude *V*ˆ S*,*1 = 325 V. Two test cases are considered: First, reference jumps of *i*d and *i*q validate the current controller performance and models. Second, the control is tested during type A and type E faults to validate the overall control structure considering the interaction of the PR-controllers with the DSOGI-PLL. As an example, Fig. 6.22 shows the phase voltages for the type E fault without zero-sequence voltage. The SSM contains the closed-loop transfer function of the current control and converter delay neglecting the voltage limitation. In contrast, the LSM contains the derived control structure used in the previous sections (see Fig 6.14).

**Figure 6.23:** Comparison of SSM, LSM, and experimental (EXP) results for a reference step of *i* ∗ d = 16 A. **Figure 6.24:** Comparison of SSM, LSM, and experimental (EXP) results for a reference step of *i* ∗ q = 16 A.

The step responses of the currents in Fig. 6.23 and 6.24 show only minor differences between the SSM, LSM, and experiment (EXP). However, the LSM shows slightly larger deviations than the SSM, but the error is below 5% for all values. Moreover, the currents are accurately controlled to the reference values for all analyzed models. The step responses derived with the LSM and test bench show a coupling between dq-components, but the effect is negligible. The step response of the negative sequence currents is not shown here since very similar characteristics are expected.

The reference steps only validate the current controller models and performance without the interaction of the PLL. Therefore, the control is tested again with a type A fault with a phase jump of -42 degrees and magnitude step of 0.5 pu. In contrast to the simulation scenarios, the current references are constant before and during the fault. Moreover, the converter power is measured since the grid currents are not available in the dq-frame of the grid. The results are presented in Fig. 6.25 and show that the LSM accurately describes the time constant and oscillation of the converter power, which is dominated by the PLL dynamics. The comparably large deviation at the beginning of the fault is caused by the slope limitation of the voltage step and phase angle jump of the grid emulator. The test is repeated for a type E fault with a phase jump of 24 degrees (0*.*41 rad), which is the same scenario used in the previous sections. The results in Fig. 6.26 demonstrate the equivalence between LSM and experiment and thus validate the high fidelity of the model.

The overall findings of this section are threefold: First, the presented dual sequence control enables fast and accurate positive and negative sequence current injection. Second, the proposed voltage limitation guarantees safe limitation, fast dynamics, and lower harmonics in steady-state. Third, the derived analytical model accurately describes the control performance during reference steps and grid faults, which is validated for different grid scenarios and reference steps. Additionally, the model provides a suitable algorithm to extract the positive and negative sequence currents in the simulation without using a post-processing decomposition.

**Figure 6.25:** Type A fault with |*Z*F|=0.5 pu, *r*F=0 pu, and *r*S=10 pu with converter current references **i** ∗ dq = [16 5] A.

**Figure 6.26:** Type E fault with |*Z*F|=1 pu, *r*F=0 pu, and *r*S=10 pu with converter current references **i** ∗ dq = [16 5] A

The presented control scheme enables the converter to accurately inject the current references into the grid even during severe grid faults. In the next step, the impact of different current references on the converter and grid voltage support must be analyzed.

### **6.2 Impact of Unbalanced Grid Faults on Grid Converters: Model and Analysis of DC-link Oscillations**

Since the positive and negative sequence currents can be sufficiently controlled, the impact of FRT operation on converters can be discussed. Unbalanced grid faults may lead to double-fundamental frequency oscillations in the active power that propagate to the dc-link of the converter. Three models must be derived to sufficiently describe this effect. First, the accurate description of the ac-power based on unbalanced grid voltages and converter currents must be derived. Second, the model must describe the relation of ac-currents and voltages on the dc-link currents and voltages, respectively. Third, the effect of the power- or current-oscillations in the dc-link on the dc-link voltage must be modeled considering the dc-link capacitor design.

Particularly for unbalanced systems, the modified *p* − *q* theory provides a convenient description of the three-phase instantaneous active power and the instantaneous imaginary power according to [19, pp.82-87]. For simplicity, both power terms are simply denoted by active and imaginary power in the following discussion. The theory divides the power into the active power *p*ac that comprises any energy flow per time unit between two nodes of a system, and the imaginary power *q*ac that only propagates between the phases [19, p.80]. The active power is defined as dot product of the phase currents **i** and phase voltages **v** in the time domain:

$$p\_{\mathsf{AC}} = \mathbf{v} \cdot \mathbf{i} \quad . \tag{6.11}$$

Chapter 6. Grid-following Converter Control for Fault Ride-Through

The norm of the cross product of the components describes the total imaginary power as follows:

$$q\_{\mathcal{AC}} = -\left(\mathbf{i} \times \mathbf{v}\right) \cdot \mathbf{1} \; \; \; \; \; \; \; \; \tag{6.12}$$

The description is valid in any reference frame such as abc, *αβ*, or dq. In the following analysis, only the fundamental frequency components, i.e., positive and negative sequence components, are considered, which leads to the power approximation according to:

$$p\_{\rm MC} \approx \underbrace{\mathbf{v}^+ \cdot \mathbf{i}^+ + \mathbf{v}^- \cdot \mathbf{i}^-}\_{\hat{p}\_{ac}} + \underbrace{\mathbf{v}^+ \cdot \mathbf{i}^- + \mathbf{v}^- \cdot \mathbf{i}^+}\_{\text{fac}}\,,\tag{6.13}$$

$$q\_{\rm AC} \approx -\left(-\underbrace{\left(\dot{\mathbf{i}}^{+} \times \mathbf{v}^{+}\right) \cdot \mathbf{1} + \left(\dot{\mathbf{i}}^{-} \times \mathbf{v}^{-}\right) \cdot \mathbf{1}}\_{\dot{Q}\_{\rm AC}} + \underbrace{\left(\dot{\mathbf{i}}^{-} \times \mathbf{v}^{+}\right) \cdot \mathbf{1} + \left(\dot{\mathbf{i}}^{+} \times \mathbf{v}^{-}\right) \cdot \mathbf{1}}\_{\dot{q}\_{\rm AC}}\right) \tag{6.14}$$

In case positive and negative sequence components are apparent, i.e., **i**+ and **i**− or **v** + and **v** −, the power terms contain a dc-component *P*¯ ac or *Q*¯ ac and an ac-component *p*˜ac and *q*˜ac oscillating with double fundamental frequency 2*ω*1. The instantaneous active power of the ac-side propagates to the dc-side of the converter:

$$p\_{\text{dc, inst}}\left(t\right) = p\_{\text{ac, inst}}\left(t\right) \,. \tag{6.15}$$

The dc-side power can be divided into a dc-component and a double-fundamental frequency component as follows:

$$v\_{\rm dc} = V\_{\rm o} + v \quad , \qquad i\_{\rm dc} = I\_{\rm o} + i \quad , \tag{6.16}$$

where *V*o and *I*o denote the dc operating point, and *v* and *i* contain only alternating terms. These definitions lead to the expression for the active power that focuses on the 2*ω*1 oscillations caused by unbalanced currents and voltages:

$$\underbrace{V\_{o}I\_{o}}\_{\tilde{P}\_{\rm dc}} + \underbrace{vI\_{o} + V\_{o}i + vi}\_{\text{p}\_{\rm dc}} = \underbrace{v\_{\alpha}^{+}i\_{\alpha}^{+} + v\_{\alpha}^{-}i\_{\alpha}^{-} + v\_{\beta}^{+}i\_{\beta}^{+} + v\_{\beta}^{-}i\_{\beta}^{-}}\_{\tilde{P}\_{\rm dc}} + \underbrace{v\_{\alpha}^{-}i\_{\alpha}^{+} + v\_{\alpha}^{+}i\_{\alpha}^{-} + v\_{\beta}^{-}i\_{\beta}^{+} + v\_{\beta}^{+}i\_{\beta}^{-}}\_{\tilde{P}\_{\rm dc}}\tag{6.17}$$

The following description neglects all other frequency components and thus assumes:

$$p\_{\text{ac},2\omega1} \gg p\_{\text{ac},\omega1} + \sum\_{k=3}^{\infty} p\_{\text{ac},k\omega1} \quad . \tag{6.18}$$

Finally, the generic expression of the alternating term of the ac-power *pac,*2*ω*1 using the magnitude *P*ac*,*2*ω*1 and the corresponding angle *γp* can be derived:

$$\underbrace{vI\_o + V\_o i + vi}\_{p\_{ac}} = \underbrace{v\_\alpha^- i\_\alpha^+ + v\_\alpha^+ i\_\alpha^- + v\_\beta^- i\_\beta^+ + v\_\beta^+ i\_\beta^-}\_{p\_{ac}} \approx p\_{ac, 2\omega 1} = P\_{ac, 2\omega 1} \cos \left(2\omega\_1 t + \gamma\_p \right) \quad . \tag{6.19}$$

The nonlinear equation in 6.19 has no analytical solution. Therefore, *vi* and *vI*o are set to zero in most publications that focus on the dc-link oscillations during unbalanced faults [17], [18] and assume:

$$
vi \ll vI\_o \ll V\_o i \quad . \tag{6.20}$$

The first term of the inequality is typically valid since the alternating parts *v* and *i* should be at least one magnitude smaller than the dc operating points. However, the second part is not valid for all converter configurations and is particularly critical for low voltage high-power converters. Consequently, *vI*o is not neglected in the following analysis.

The dc-current oscillations are defined as generic oscillations with the frequency 2*ω*1 and the magnitude *I*dc*,*2*ω*1 similar to the active power *pac,*2*ω*1, which leads to:

$$p\_{\rm ac}(t) \approx p\_{\rm ac,2\omega1}(t) = vI\_o + V\_o i = \left(\frac{1}{C\_{\rm dc}} \int I\_{\rm dc,2\omega1} \cos\left(2\omega\_1 t\right) \mathrm{d}t\right) I\_o + V\_o I\_{\rm dc,2\omega1} \cos\left(2\omega\_1 t\right) . \tag{6.21}$$

This equation can be analytically solved by defining *XC,*2*ω*1 = 1*/ω*1*C*dc to obtain *I*dc*,*2*ω*1 according to:

$$I\_{dc,2\omega\_1} = \frac{P\_{ac,2\omega1}}{I\_o X\_{C,2\omega1}} \sqrt{\frac{1}{1+\rho^2}} \frac{\cos\left(2\omega\_1 t + \gamma\_p\right)}{\cos\left(2\omega\_1 t + \tan^{-1}(-\rho)\right)} \quad \text{with} \quad \rho = \frac{V\_o}{I\_o X\_{C,2\omega1}}\ . \tag{6.22}$$

Rearranging the equations above and assuming cos (2*ω*1*t* + *γp*) ≈ cos (2*ω*1*t* + tan−1(−*ρ*)) yields the expressions for the double fundamental frequency component of the dc-link voltage:

$$V\_{\rm dc,2\omega1} = I\_{\rm dc,2\omega1} X\_{C,2\omega1} = X\_{C,2\omega1} P\_{\rm ac,2\omega1} \sqrt{\frac{1}{\left(I\_o X\_{C,2\omega1}\right)^2 + V\_o^2}} = \frac{P\_{\rm ac,2\omega1}}{I\_o} \sqrt{\frac{1}{1+\rho^2}} \quad . \tag{6.23}$$

The expression 1 *ρ* is equivalent to *vI*o *V*o*i* by considering *XC,*2*ω*1 = *v/i*. Setting *ρ* → ∞ corresponds to *vI*o ≈ 0 and leads to the conventional expression for the dc-link voltage oscillations:

$$V\_{\rm dc,2\omega1} \approx \frac{P\_{\rm ac,2\omega1}}{V\_{\rm o}} X\_{C,2\omega1} \quad , \tag{6.24}$$

which verifies the calculations.

The derived model is compared to a numerical model, which considers the current control and a switched converter model, to verify its fidelity. The test scenario is a type G fault with balanced current injection according to Fig. 6.27. The type G fault is chosen because it can

**Figure 6.27:** Phase voltages and currents during a type G fault considering balanced current injection.

**Figure 6.28:** Comparison of dc-link current, voltage and active power oscillations between the switched model and the derived analytical model during a type G fault.

be easily emulated with an auto-transformer, which is necessary for validating the models in the next section. Moreover, it has similar voltage and phase angle characteristics as the type E fault. The results of the model comparison are shown in Fig. 6.28 and indicate a high fidelity of the model. The deviations in the range of 10% are caused by the line impedances that slightly shift the operating points of the switched model in comparison to the analytical model.

The dc-link capacitor design has a strong impact on the effect of power oscillations on the dc-link voltage. The derived model can be used to analyze dc-link oscillations considering typical dc-link capacitor designs. The hold-up time criterion is a standard approach to design dc-link capacitors for grid converters based on the stored energy ∆*W* [154]. The energy is chosen to buffer a required power ∆*P* over the time *T*r assuming that the power input from the generation unit is zero. During this time, the dc-link voltage *V*dc should not violate the maximum voltage deviation ∆*V* . The stored energy in the capacitor is approximated with:

$$
\Delta W = \frac{1}{2} C\_{\rm dc} \left( V\_o^2 - \left( V\_{\rm dc} + \Delta V \right)^2 \right) = C\_{\rm dc} \left( V\_{\rm dc} \Delta V + \frac{1}{2} \Delta V^2 \right) \tag{6.25}
$$

This expression is combined with the generic description of the energy to include the design parameters according to:

$$
\Delta W = \frac{\Delta P T\_{\rm r}}{2} \le C\_{\rm dc} \left( V\_{\rm dc} \Delta V + \frac{1}{2} \Delta V^2 \right) \tag{6.26}
$$

Finally, the criterion for the dc-link capacitor *C*dc is obtained:

$$C\_{\rm dc} \ge \frac{\Delta P T\_{\rm r}}{\Delta V \left(2V\_{\rm dc} + \Delta V\right)} \quad . \tag{6.27}$$

The hold-up time design parameter can be directly used to verify the assumption *vI*o *V*o*i*. Substituting the design rule for *C*dc in 6.23 and considering normalized quantities ∆*p* = ∆*P/*(*V*dc*I*o) and ∆*v* = ∆*V/V*dc yields:

$$vI\_o \ll V\_o i \qquad \Leftrightarrow \left(\frac{2\omega\_1 T\_r}{2\Delta v + \Delta v^2} \Delta p\right)^2 \gg 1 \quad . \tag{6.28}$$

The description links the design rule for the dc-link capacitor with the assumption to simplify the calculation of *V*dc*,*2*ω*1. This makes it possible to decide based on *T*r , ∆*v*, and ∆*p* if the exact relation of *V*dc*,*2*ω*1 (see 6.23) or the simplified relation (see 6.24) should be used for determining *V*dc*,*2*ω*1.

The section presented a model of the dc-link oscillations, which accurately predicts the impact of the fault voltages and converter currents on the dc-link oscillations. Since the current reference generator define the converter currents dependent on the fault voltages, their impact on the power oscillations is discussed in the next section. Additionally, the experimental validation of the dc-link oscillations using different current generators is presented.

### **6.3 Dual Sequence Current Reference Calculation Schemes, Voltage Support Schemes, and the Grid Codes**

The main goal of converter current control is to provide active and reactive power to the grid. Current reference generators calculate the required currents according to given active and reactive power references using the grid voltage measurements. The current reference generation is straightforward for balanced systems. However, unbalanced systems raise new challenges of current reference calculation and introduce more flexibility for the active and reactive power injection since the power may be provided in positive and negative sequence. Grid codes require positive and negative sequence currents depending on the fault voltage but typically neglect power oscillation constraints and resistive parts of the line impedances.

There are four basic algorithms for current reference generators proposed in the literature [52], [155], [156]. The algorithms aim to achieve specific power or current properties, which are briefly summarized here. The Balanced Positive Sequence Control (BPSC) balances the output currents. It is identical to solely positive sequence current generators and thus suffers from large active and reactive power oscillations at the double fundamental frequency. The Instantaneous Active–Reactive Control (IARC) rejects the active and reactive power oscillations at double fundamental frequency but suffers from low order harmonics. The Positive- and Negative-Sequence Control (PNSC) and Average Active–Reactive Control (AARC) reject the active or imaginary power oscillations, respectively, for the power references *P* ∗ = 1 pu and *Q*∗ = 0 pu. Notably, this characteristic changes with the power setpoints. For the setpoint *P* ∗ = 0 pu and *Q*∗ = 1 pu, the PNSC rejects the imaginary power oscillations, whereas the AARC rejects active power oscillations. This high sensitivity to the power setpoints is the major drawback of these algorithms. The Flexible Positive and Negative Sequence Control (FPNSC) provides a generic algorithm that includes all these strategies by introducing two parameters to adjust the power characteristics [52, pp.267-269]. A brief discussion on rejecting active and imaginary power oscillations based on this algorithm is given in [52, p.269], and a specific power reference generator to reject the active power oscillations is presented in [16].

In the literature, the current reference generators mentioned above are not analyzed regarding their grid voltage support. Several current reference generators predominantly support the grid voltages during unbalanced faults by increasing the voltage in the faulty phases as close as possible to the tolerance band of the normal operation. Additionally, they prevent the healthy phases from exceeding the maximum permissible phase voltage [26]. However, these algorithms, which are denoted as Voltage Support Schemes (VSSs), critically depend on the SCR and rely on a line impedance estimation. These implementation problems make them critically sensitive to grid parameter variations.

Converter current limitation may deteriorate the grid voltage support capability because the converter typically injects its maximum current during deep voltage sags. Most current limitation algorithms limit the reference currents to guarantee the maximum converter current [16], [23] [85]. However, this approach critically depends on the current reference generator or VSS and sequence decomposition. Therefore, a straightforward current limitation is proposed that conserves the voltage and current characteristics and thus the characteristics of power oscillations.

The rest of this section is organized as follows: in the first section, two reference generators are derived from the FPNSC that reject the active and reactive power oscillations independent of the power reference setpoint. Then, a dual sequence Vector Current Limitation (VCL) is proposed that conserves the power oscillation properties of the current reference generators. In the third section, the voltage support strategies are presented that guarantee optimum voltage recovery, and the impact of the line impedance estimation on the support characteristics is discussed. Finally, the current reference generators are compared considering maximum power oscillations, voltage support, and stability.

#### **6.3.1 Rejection of Power Oscillations Considering the Current Limitation**

A current reference generator to reject power oscillation is proposed in [16]. However, in the following section, current reference generators based on the Flexible Positive and Negative Sequence Controls (FPNSCs) are derived to reject active or reactive power oscillations. The FPNSC defines two parameters, i.e., *kp* and *kq*, for separation of active and reactive currents in positive and negative sequence [23]. The power references *P* ∗ and *Q*∗ can be provided in positive and negative sequence by adjusting *kp* or *kq* in the range of [0...1]. In the extreme cases *kp* = *kq* = 1 and *kp* = *kq* = 0, the converter provides only positive sequence power or negative sequence power, respectively. The active and reactive current references (**i** ∗ *p,*FPNSC and **i** ∗ *q,*FPNSC) are calculated in the *αβ*-frame with the expressions:

$$\mathbf{i}\_{p, \text{FPNSC}}^{\*} = P^{\*} \left( \frac{k\_p}{|\mathbf{v}^{+}|^2} \mathbf{v}^{+} + \frac{1 - k\_p}{|\mathbf{v}^{-}|^2} \mathbf{v}^{-} \right) \quad , \qquad \mathbf{i}\_{q, \text{FPNSC}}^{\*} = Q^{\*} \left( \frac{k\_q}{|\mathbf{v}^{+}|^2} \mathbf{v}\_{\perp}^{+} + \frac{1 - k\_q}{|\mathbf{v}^{-}|^2} \mathbf{v}\_{\perp}^{-} \right) \tag{6.29}$$

where **v** + and **v** − denote the positive and negative sequence voltage vectors in *αβ*-frame, respectively; and **v** + ⊥ and **v** − ⊥ denote the corresponding orthogonal voltages. These components can be determined by a simple matrix operation according to:

$$\mathbf{v}\_{\perp} = \begin{bmatrix} 0 & -1 \\ 1 & 0 \end{bmatrix} \mathbf{v}\_{\perp}. \tag{6.30}$$

Substituting the expressions in 6.29 in the equations for the instantaneous power in 6.11 and 6.12 results in the power oscillations:

$$P\_{\rm ac,2\omega1} = \sqrt{P^{\ast 2} \left[k\_p VUF + (1 - k\_p) VUF^{-1}\right]^2 + Q^{\ast 2} \left[k\_q VUF - (1 - k\_q) VUF^{-1}\right]^2},\tag{6.31}$$

$$Q\_{\rm ac,2\omega1} = \sqrt{Q^{\ast 2} \left[k\_q VUF + (1 - k\_q) VUF^{-1}\right]^2 + P^{\ast 2} \left[k\_p VUF - (1 - k\_p) VUF^{-1}\right]^2}. \tag{6.32}$$

With the expressions in 6.31, the parameters *kp* and *kq* can be determined to achieve *P*ac*,*2*ω*1 = 0 as follows:

$$k\_p = \frac{\left|\mathbf{v}^+\right|^2}{\left|\mathbf{v}^+\right|^2 - \left|\mathbf{v}^-\right|^2} \quad , \qquad k\_q = \frac{\left|\mathbf{v}^+\right|^2}{\left|\mathbf{v}^+\right|^2 + \left|\mathbf{v}^-\right|^2} \quad . \tag{6.33}$$

By inserting these expressions into 6.29, the current reference generator denoted as Zero Active Power Oscillation Control (ZAPOC) is defined according to:

$$\left[\mathbf{i}\_{p,\text{ZAPOC}}^{\*}\mathbf{i}\_{q,\text{ZAPOC}}^{\*}\right]^{\text{T}} = \left[\frac{P^{\*}}{\left|\mathbf{v}^{+}\right|^{2} - \left|\mathbf{v}^{-}\right|^{2}}\left(\mathbf{v}^{+} - \mathbf{v}^{-}\right) \frac{Q^{\*}}{\left|\mathbf{v}^{+}\right|^{2} + \left|\mathbf{v}^{-}\right|^{2}}\left(\mathbf{v}\_{\perp}^{+} + \mathbf{v}\_{\perp}^{-}\right)\right]^{\text{T}}.\tag{6.34}$$

133

**Figure 6.29:** Active power injected by the converter using the ZAPOC and ZRPOC during a type E fault with |*Z*F|=0.5 pu.

**Figure 6.30:** Imaginary power injected by the converter using the ZAPOC and ZRPOC during a type E fault with |*Z*F|=0.5 pu.

The same process can be repeated to obtain the current reference generator that guarantees *Q*ac*,*2*ω*1 = 0, which is denoted as Zero Reactive Power Oscillation Control (ZRPOC). The current references are calculated with:

$$\left[\mathbf{i}\_{p,\text{ZRPOC}}^{\*}\,\mathbf{i}\_{q,\text{ZRPOC}}^{\*}\right]^{\text{T}} = \left[\frac{P^{\*}}{|\mathbf{v}^{+}|^{2} + |\mathbf{v}^{-}|^{2}}\left(\mathbf{v}^{+} + \mathbf{v}^{-}\right)\frac{Q^{\*}}{|\mathbf{v}^{+}|^{2} - |\mathbf{v}^{-}|^{2}}\left(\mathbf{v}\_{\perp}^{+} - \mathbf{v}\_{\perp}^{-}\right)\right]^{\text{T}}.\tag{6.35}$$

The presented current reference strategies are tested in a simulation with a current source, which directly injects the reference currents into the grid. Fig. 6.29 and Fig. 6.30 show the active and imaginary power for a type E fault with |*Z*F|=0.5 pu. At *t* = 0*.*05 s, the current reference generator is switched from ZAPOC to ZRPOC. For the ZAPOC, the active power oscillations *p*AC are zero, whereas the imaginary power oscillations *q*AC have a large amplitude of 0.6 pu. The ZRPOC leads to the exact opposite behavior. These simulation results confirm the expected characteristics of both derived current reference generators.

As discussed before, the current reference generator cannot be sufficiently analyzed in a realistic scenario without considering the current limitation. Therefore, a suitable limitation algorithm must be derived that conserves the aforementioned current reference characteristics, e.g., current balancing or active power oscillation rejection [157]. Several approaches are introduced in the literature to sufficiently limit the maximum converter current. The simplest method proposes a static limitation with predefined ratios of the active and reactive current [87]. The static limitation cannot achieve optimum converter operation and system support for different grid scenarios. More advanced techniques utilize additional virtual impedances and observers with the drawback of increasing complexity [85], [86], [87], [89].

Suitable algorithms to conserve the power characteristics should guarantee that the ratios of positive to negative sequence are constant and the ratio of active to reactive current in positive and negative sequence. This behavior can be achieved by equal scaling of the reference current components. The idea is explained for the reference currents **i** ∗ by using the active power oscillation definition in 6.17 and combining it with a current limitation factor *ki,*lim as follows:

$$\mathbf{i}\_{\rm lim}^{\*} = k\_{i,\rm lim} \mathbf{i}^{\*} \Rightarrow \qquad \tilde{p}\_{\rm ac,\rm lim} = k\_{i,\rm lim} \left( v\_{\alpha}^{-} i\_{\alpha}^{\*+} + v\_{\alpha}^{+} i\_{\alpha}^{\*-} + v\_{\beta}^{-} i\_{\beta}^{\*+} + v\_{\beta}^{+} i\_{\beta}^{\*-} \right) = k\_{i,\rm lim} \tilde{p}\_{\rm ac} \; . \tag{6.36}$$

This description indicates that the factor *ki,*lim only scales the power component *p*˜ac. The achieved characteristic is very promising because the scaling conserves the power oscillation rejection presented in 6.34 and 6.35 since *p*˜ac*,*lim|*p*˜ac=0 = 0 ∀*ki,*lim and *q*˜ac*,*lim|*q*˜ac=0 = 0 ∀*ki,*lim. The limitation factor *ki,*lim can be calculated as ratio of the actual converter current magnitude |**i** ∗ *αβ*| and the maximum converter current ˆ*I*max. This implementation is similar to the Vector Voltage Limitation (VVL) in section 6.1.1. However, during unbalanced grid faults, the current trajectory may be an ellipse in the *αβ*-frame so that the magnitude |**i** ∗ *αβ*| is not constant. Therefore, the maximum current magnitude can be calculated with max |**i** ∗ *αβ*| = |**i** ∗ *αβ,*lim| = |**i** +∗ *αβ*| + |**i** −∗ *αβ*|. Then, the ellipse can be scaled with

$$k\_{i, \text{lim}} = \frac{\hat{I}\_{\text{max}}}{|\mathbf{i}\_{\alpha\beta}^{+\*}| + |\mathbf{i}\_{\alpha\beta}^{-\*}|}\ \ , \tag{6.37}$$

so that |**i** ∗ *αβ*| never exceeds ˆ*I*max and |**i** ∗ *αβ,*lim| = ˆ*I*max. The final limitation scheme is presented in Fig. 6.31. The structure is identical to the PDVVL (see 6.1.1) but contains the magnitude calculation of |**i** ∗ *αβ*| based on the sequence decomposition of the DSOGI. Note that the DSOGI adds a delay here so that only the peak current limitation is active during transients and the vector limitation is only active in steady-state. The impact of the limitation on the current trajectory **i** ∗ *αβ* in steady-state is depicted in Fig. 6.32a.

**Figure 6.31:** Saturation method for converter currents considering the positive and negative sequence.

The reference calculation can be performed in any reference frame. For PR-controllers, it is convenient to calculate the currents directly in the *αβ*-frame. Unfortunately, the current amplitudes in the *α/β*-frame cannot accurately describe the maximum phase currents for unbalanced systems with phase shift *δ*e between positive and negative sequence. This leads to the characteristic that |**i** +∗ *αβ*| + |**i** −∗ *αβ*| *>* max ˆ*I* ∗ 1 *,* ˆ*I* ∗ 2 *,* ˆ*I* ∗ 3 . This relation indicates that the limitation based on |**i** +∗ *αβ*|+|**i** −∗ *αβ*| *<* ˆ*I*max not exceeds the maximum phase currents but also does not reach the maximum current during unbalanced faults with *δ*e 6= 0. This characteristic is

**Figure 6.32:** a) Proposed limitation with equal scaling of the positive and negative sequence; b) Difference between phase currents in abc-frame and *αβ*-frame considering the ellipse parameters *A*, *B*, and *δ*e.

shown in Fig. 6.32b. This figure also introduces the ellipse parameters *A*, *B*, and *δ*e that are necessary to calculate the maximum phase currents ˆ*Ij* |*j*=[1*,*2*,*3] according to:

$$\left. \hat{I}\_{j}^{\*} \right|\_{j=[a,b,c]} = \sqrt{B^2 \cdot \sin^2 \left( \delta\_c + (j-1) \cdot \frac{4}{3}\pi \right) + A^2 \cdot \cos^2(\delta\_c + (j-1) \cdot \frac{4}{3}\pi)} \quad (6.38)$$

considering the phase angles of the positive and negative sequence:

$$\delta\_{+1} = \operatorname{atan2}\left(\frac{i\_{\beta}^{+\*}}{i\_{\alpha}^{+\*}}\right) \qquad \delta\_{-1} = \operatorname{atan2}\left(\frac{i\_{\beta}^{-\*}}{i\_{\alpha}^{-\*}}\right) \Rightarrow \qquad \delta\_{a} = \frac{\delta\_{+1} + \delta\_{-1}}{2} \tag{6.39}$$

and the diagonals of the ellipse:

$$A = |\mathbf{i}\_{\alpha\beta}^{+\*}| + |\mathbf{i}\_{\alpha\beta}^{-\*}| \qquad B = |\mathbf{i}\_{\alpha\beta}^{+\*}| - |\mathbf{i}\_{\alpha\beta}^{-\*}| \quad . \tag{6.40}$$

With these expressions, the limitation factor *ki,*lim can be directly calculated according to:

$$k\_{i, \text{lim}} = \hat{I}\_{\text{max}} / \max \left( \hat{I}\_a^\* \; \hat{I}\_b^\* \; \hat{I}\_c^\* \right) \; . \tag{6.41}$$

In combination with the current reference generators, the proposed limitation is simulated during different type G faults with varying sag depths or *V UF*, respectively. The power references are set to *P* ∗ = *.*5 pu and *Q*∗ = *.*5 pu, and the maximum current to ˆ*I*max = 1 pu. The simulation results in Fig. 6.33 confirm that the current magnitudes are sufficiently limited. However, the current magnitudes of the limitation scheme in *αβ*-frame significantly differ from the limitation in abc-frame. Particularly, the AARC, PNSC, and ZAPOC show

M

significant deviations in the maximum phase currents between both limitation schemes. In the worst case, the ZAPOC injects 13% less current with the limitation in the *αβ*-frame than in abc-frame. This current deviation is not acceptable for optimum grid support. The ZRPOC and BPSC do not differ since *δ*e = 0 for both strategies. Consequently, the *αβ*-amplitudes correspond to the abc-frame amplitudes.

Once the currents are sufficiently limited, the impact of the current limitation on the active power oscillations can be analyzed. Fig. 6.34 shows the active power oscillations during the same type G faults as before. The results confirm that the current limitation scales *P*ac*,*2*ω*1. The ZAPOC shows identical results with and without limitation and completely rejects the active power oscillation. In contrast, the ZRPOC and PNSC cause the largest active power oscillations. This characteristic verifies the analysis in 6.36.

**Figure 6.33:** Comparison of the current limitation in the abc-frame and *αβ*-frame using different current reference generators during type G faults with different *V UF*. This plot highlights the deviation between the phase current amplitudes and amplitudes in *αβ*-frame.

**Figure 6.34:** Impact of the current limitation on the active power oscillation amplitude *P*ac*,*2*ω*1 using different current reference generators during type G faults with different *V UF*.

The ZAPOC shows promising results for rejecting active power oscillations. The proposed limitation scheme also enables the converter to reject the power oscillations during current limitation. Moreover, the limitation strategy does not deteriorate the dynamics since it does not decompose the sequences like solutions from the literature [16], [23], [85]. The performance of the current generators with limitation and the dc-link models are validated in the following part.

#### **6.3.2 Validation of the Control Characteristics and DC-Link Oscillations**

The current reference generators with limitation are tested with the same experimental setup as the dynamic responses, as shown in Fig. 6.22. Additionally, the setup contains a dc-link current measurement to validate the impact of active power oscillations at 2*ω*1 on the dc-link. Moreover, a step transformer is used to emulate a two-phase fault that corresponds to a type G fault since the zero sequence component does not affect the converter terminal voltages. The sag depth is changed in the range of *V UF*=0-0.7 pu, and the power references are *P* ∗ = 1 pu and *Q*∗ = 0 pu. The active power oscillations, imaginary power oscillations, and dc-link currents are evaluated by performing an FFT and comparing the 2*ω*1 components to LSM simulation results. The LSM contains the derived control structure and an averaged converter model according to Fig. 6.14. The current reference generators are implemented with a *MATLAB* function, which is used in the simulation and RCP system of the test-bench. The results for the power oscillations of the BPSC, AARC, PNSC, ZAPOC, and ZRPOC schemes are shown in Fig. 6.35 and 6.36. The LSM and experimental results differ significantly but the basic power oscillation properties of the current reference generators are confirmed. The ZAPOC leads to zero active power oscillations *P*ac*,*2*ω*1, whereas the ZRPOC rejects imaginary power oscillations *Q*ac*,*2*ω*1. Due to the setpoint of *P* ∗ = 1 pu and *Q*∗ = 0 pu, the power oscillation rejection can also be achieved with the PNSC and AARC. However, for different power setpoints, the oscillations for these reference generators will change. The largest *P*ac*,*2*ω*1 occurs for the AARC and ZRPOC since they reject *Q*ac*,*2*ω*1. Contrarily, the PNSC and ZAPOC yield the largest *Q*ac*,*2*ω*1 and the BPSC leads to active and imaginary power oscillations.

The impact of the power oscillations on the dc-link is validated by analyzing the 2*ω*1 oscillations of the dc-link current *I*dc*,*2*ω*1 with an FFT, as shown in Fig. 6.37-6.39. Fig. 6.37 shows the measured currents of the Power Supply to highlight the large oscillations in the dc-link current due to the active power oscillations. Note that the dc-link current *i*dc is not shown in the time domain due to the large distortions at switching frequency. However, an FFT of *i*dc in Fig. 6.38 confirms that the ZRPOC sufficiently mitigates the oscillations. Moreover, it is proven that dc-link oscillations at 2*ω*1 are fully described by the instantaneous active power oscillations, as predicted by the modified *pq*-theory. Consequently, the ZAPOC can sufficiently reject the dc-link oscillations at 2*ω*1 in any power setpoint. In contrast, the ZRPOC leads to the largest oscillation amplitudes since it rejects the imaginary power oscillations.

The experiment successfully validated the power characteristics of the current reference generators. Moreover, the impact of the power oscillations on the dc-link is proven. The ZAPOC could sufficiently reject the dc-link oscillations during unbalanced faults. However, the limitation of the active power oscillations is only one objective of the converter operation in unbalanced systems. The converter must predominantly support the grid voltage. Hence, the indicators for the converter capability to support the grid voltage are derived in the next section.

**Figure 6.35:** Comparison of simulation and experimental results for the active power oscillation amplitude *P*ac*,*2*ω*1 using different current reference generators during type G faults with different *V UF*.

**Figure 6.36:** Comparison of simulation and experimental results for the imaginary power oscillation amplitude *Q*ac*,*2*ω*1 using different current reference generators during type G faults with different *V UF*.

**Figure 6.37:** Measurement of *i*PS during type G fault with *V UF*=0.4 using ZAPOC and ZRPOC. **Figure 6.38:** FFT of *i*dc during type G fault with *V UF*=0.4 to determine *I*dc*,*2*ω*1. **Figure 6.39:** Comparison of simulation and experimental results for *I*dc*,*2*ω*1 using different current reference generators during type G faults with different *V UF*.

#### **6.3.3 Grid support based on Voltage Support Scheme (VSS) and VDE-AR-N 4110**

The grid support of converters focuses on voltage support during faults. The converter should try to increase the positive sequence voltage and reduce the unbalance by rejecting the negative sequence voltage. The grid code requires a reactive current in the positive and negative sequence dependent on the positive and negative sequence grid voltages, as already shown in Fig. 3.10 [11]. However, this support strategy has two severe drawbacks. First, the voltage support with reactive current is only applicable for inductive grid, i.e., the strategy might fail for distribution grids with typically significant resistive parts in the line impedance. Second, a large increase in the positive sequence voltage may lead to overvoltages in the healthy phases. Several research contributions focus on developing a more sophisticated VSS to overcome these drawbacks [26], [23]. The basic VSS algorithm is based on [26]. It was extended to inductive-resistive grid impedances by [23]. The basic idea of the VSS is presented in [26] and [23] with changes in the notation. For the sake of completeness, it is

repeated here: first, the maximum and minimum phase voltages are extracted according to:

$$\min\left(V\_a, V\_b, V\_c\right) = \sqrt{|\mathbf{v}^+|^2 + |\mathbf{v}^-|^2 + 2\left|\mathbf{v}^+\right|\left|\mathbf{v}^-\right|y} \tag{6.42}$$

$$\max\left(V\_a, V\_b, V\_c\right) = \sqrt{\left|\mathbf{v}^+\right|^2 + \left|\mathbf{v}^-\right|^2 + 2\left|\mathbf{v}^+\right|\left|\mathbf{v}^-\right|x} \tag{6.43}$$

using the angle definitions

$$y = \min\left(\cos(\gamma), \cos\left(\gamma - \frac{2\pi}{3}\right), \cos\left(\gamma + \frac{2\pi}{3}\right)\right) \quad , \tag{6.44}$$

$$x = \max\left(\cos(\gamma), \cos\left(\gamma - \frac{2\pi}{3}\right), \cos\left(\gamma + \frac{2\pi}{3}\right)\right) \text{ with } \gamma = \sin\left(\frac{v\_\alpha^+ v\_\beta^- + v\_\beta^+ v\_\alpha^-}{|\mathbf{v}^+| |\mathbf{v}^-|}\right) \dots \text{ (6.45)}$$

The maximum and minimum reference voltages are then derived according to 6.46, where the desired maximum is slightly changed to sufficiently handle small imbalances, as proved in [26].

$$\max\left\{V\_a^\*, V\_b^\*, V\_c^\*\right\} = \min\left(\overline{\mathcal{V}}, \underline{\mathcal{U}} + \max\left\{V\_a, V\_b, V\_c\right\} - \min\left\{V\_a, V\_b, V\_c\right\}\right) \tag{6.46}$$

$$\min \left\{ V\_a^\*, V\_b^\*, V\_e^\* \right\} = \underline{\mathcal{V}} \tag{6.47}$$

V and V indicate the desired maximum and minimum voltages for all three phases and are typically defined in the normal tolerance band of 0.9-1.1 pu or for FRT according to the voltage boundaries [20]. With these defined boundaries, the reference voltages for the positive and negative sequence can be calculated by solving:

$$\left| \mathbf{v}^{+\*} \right| = \sqrt{\frac{x\underline{\lambda}^2 - y\overline{\nu}^2 + \sqrt{\left(y\overline{\nu}^2 - x\underline{\lambda}^2\right)^2 - \left(\overline{\nu}^2 - \underline{\lambda}^2\right)^2}{2(x - y)}}},\tag{6.48}$$

$$\left|\mathbf{v}^{-\*}\right| = \sqrt{\frac{x\underline{\lambda}^2 - y\overline{\lambda}^2 - \sqrt{\left(y\overline{\lambda}^2 - x\underline{\lambda}^2\right)^2 - \left(\overline{\lambda}^2 - \underline{\lambda}^2\right)^2}{2(x - y)}}\ . \tag{6.49}$$

Finally, the reference currents are obtained using the estimated line and fault impedances *R* and *X*, and the voltage **v**S:

$$\begin{aligned} \left| \mathbf{i}\_{p, \text{VSS}}^{\*} \right| &= \frac{R}{X^2 + R^2} \left( \left| \mathbf{v}^{+\bullet} \right| - \left| \mathbf{v}\_{\text{S}}^{+} \right| + \left| \mathbf{v}^{-\bullet} \right| - \left| \mathbf{v}\_{\text{S}}^{-} \right| \right) \\\\ \left| \mathbf{i}\_{q, \text{VSS}}^{\*} \right| &= \frac{X}{X^2 + R^2} \left( \left| \mathbf{v}^{+\bullet} \right| - \left| \mathbf{v}\_{\text{S}}^{+} \right| - \left| \mathbf{v}^{-\bullet} \right| + \left| \mathbf{v}\_{\text{S}}^{-} \right| \right) \end{aligned} \tag{6.50}$$

The main drawback is the uncertain impedance values that deteriorate the voltage estimation and current references. This problem is not discussed in the literature [26], [28], and [20], but is analyzed in the following. Therefore, the impedance terms of 6.50 can be rearranged by defining the impedance ratio *r*S = *X/R*, which leads to:

$$\frac{R}{X^2 + R^2} = \frac{1}{X} \cdot \frac{r\_{\rm S}}{1 + r\_{\rm S}^2}; \qquad \frac{X}{X^2 + R^2} = \frac{1}{X} \cdot \frac{r\_{\rm S}^2}{1 + r\_{\rm S}^2} \tag{6.51}$$

This derivation indicates that the impedance magnitude, i.e., *X*, scales the current references **i** ∗ *p,*VSS  and **i** ∗ *q,*VSS  given in 6.50. Since the reference current cannot be reached in most applications (the maximum converter current is too small), this scaling is not critical. Hence, the impedance ratio dominates the impact of the line impedance on the VSS. For most grid types, this ratio is well known as summarized in Table 3.1. Consequently, the grid voltage estimation is more critical for the implementation of the VSS than the line impedance estimation. Unfortunately, the algorithm only determines the magnitudes of the reference currents (see 6.50) and thus is an RMS-based algorithm, which typically suffers from slow dynamics. Due to these critical problems, the following evaluation only considers the VSS to assess the grid voltage support capability of the current reference generators.

### **6.4 Evaluation of Dual Sequence Power Reference Schemes during Fault Ride-Through**

The presented current reference generators are often analyzed regarding their maximum current injection and power oscillation characteristics [52], [16], [85]. However, the grid support capability is not part of these contributions. Publications that deal with voltage support mainly focus on the VSS and analyze the voltage characteristics during single-phase faults [26], [23], [20]. In [28], the grid support goal is combined with the mitigation of active power oscillations. This contribution utilizes the VSS that is not applicable due to the drawbacks mentioned in the previous section. Moreover, none of these contributions discusses the stability of the current reference generators. In this section, the different current reference strategies are evaluated regarding their converter utilization and optimum grid support using the VSS as reference. The grid scenarios are type C and type E faults to show the difference between single-phase faults and two-phase faults. The stability margin of the different algorithms based on the minimum SCR is identified for the same fault scenarios to include an indicator for the stability into the evaluation.

The VSS algorithm identifies the optimum control behavior to support the grid voltage. Assuming that the converter cannot reach the current necessary for completely recovering the voltage, the absolute current value is not of interest for the grid support. Based on the VSS in 6.50, the voltage support relies on two important criteria: first, the positive sequence voltage should be increased considering the maximum voltage of the healthy phase. Second, the negative sequence voltage should be reduced to increase the minimum phase voltage without exceeding the voltage limit with the maximum phase voltage.

The active and reactive power serve as inputs for the current reference generators and are thus adjustable according to the grid impedance ratio. Hence, the current reference generators can achieve the same characteristic as the VSS. However, the ratio of the positive and negative sequence current is fixed by the applied algorithm, e.g. ZAPOC, or *kp* and *kq* for the FPNSC. Thus, their overall voltage support characteristics must be evaluated and compared to the VSS.

For the evaluation, the model and control depicted in Fig. 6.14 are extended with the current reference generators and a weak grid scenario with SCR=5 pu. The impedance ratios are chosen according to Table 3.1 with *r*S*,*hv = 10, *r*S*,*mv = 1*.*2, and *r*S*,*lv = 0*.*129. The power references are selected according to this impedance ratio to achieve optimum grid support for every strategy. Only for the strategy defined in the VDE standard, the references are chosen according to Fig. 3.10. The active power oscillations *P*ac*,*2*ω*1 , the maximum phase voltage *V*ˆmax, and minimum phase voltage *V*ˆmin are the indicators for converter utilization and grid voltage support to identify the best strategy for the different fault types and the predefined scenarios. The results for the high-voltage grid, medium-voltage grid, and low-voltage grid during a type C fault are presented in Fig. 6.40 and 6.41, respectively. The BPSC, PNSC, and ZRPOC suffer from large power oscillations and maximum phase voltages above the nominal voltage in high voltage grids. The ZAPOC and AARC achieve very similar results to the VSS, while the ZAPOC guarantees zero active power oscillations. Considering the low-voltage grid, the AARC behaves like the PNSC in the high-voltage grid and vice-versa. The different power references according to the impedance cause this effect. This sensitivity of these current generators makes them vulnerable to variations in the line impedance ratio. The VDE based algorithm suffers from the same sensitivity and achieves a deficient minimum phase voltage, particularly in the low-voltage and medium-voltage grid. Only the ZAPOC achieves very similar results compared to the VSS in all scenarios without relying on the sensitive grid voltage estimation of the VSS. The results for a type E fault are not presented here and confirm these conclusions.

The SCR is a crucial parameter for grid-following converters and critically affects their stability. The stability mainly depends on the SCR, the impedance ratio, and the applied current reference generator. The current reference generators are tested in fault scenarios considering different SCRs to assess their stability. Before the system gets unstable, the THD in the current rises significantly. To detect the stability boundary, a THD*i >* 0*.*05 pu after 200 ms of the fault initiation for a sampling window of 100 ms serves as an indicator for an insufficient stability. The results in Fig. 6.42 and Fig. 6.43 for a type C and type E fault, respectively, indicate that, particularly high-voltage grids are vulnerable to instability due to low SCRs. Moreover, the power reference generators critically affect stability. The ZAPOC and AARC already show an insufficient stability margin at SCR<5 for the high-voltage grid. 6.4. Evaluation of Dual Sequence Power Reference Schemes during Fault Ride-Through

**Figure 6.40:** Comparison of active power oscillations, the maximum phase voltage, and the minimum phase voltage for different current reference generators for a type C fault with |*Z*F|=0.05 pu, SCR=5 pu, and *r*S*,*hv = 10.

**Figure 6.41:** Comparison of active power oscillations, the maximum phase voltage, and the minimum phase voltage for different current reference generators for a type C fault with |*Z*F|=0.05 pu, SCR=5 pu, and *r*S*,*mv = 1*.*2 (left) or *r*S*,*lv = 0*.*129 (right).

**Figure 6.42:** Minimum SCR for stable operation with power quality requirement THD*i <* 0*.*05 during a type C fault with |*Z*F|=0.05 pu.

**Figure 6.43:** Minimum SCR for stable operation with power quality requirement THD*i <* 0*.*05 during a type E fault with |*Z*F|=0.05 pu.

In comparison, the ZRPOC and PNSC are stable down to SCRs larger than 4. The fault type has a small impact on the SCRmin of the current reference generators.

The evaluation of the current reference generators indicates that the ZAPOC is a suitable strategy to reject active power oscillations considering the maximum and minimum phase voltages. Unfortunately, the stability of the ZAPOC must be carefully proved since it seems

to be vulnerable to instability for low SCRs. The VSS is identified as a suitable reference for the evaluation but is not applicable since it is too sensitive on the grid voltage estimation. The VDE compliant strategy suffers from low maximum and minimum phase voltages due to prioritizing the reactive current.

Weak grid conditions enable inverters to participate actively in the voltage recovery during and after faults. However, the interaction of the injected current with the PCC voltage in weak grids makes the converter control prone to instability mechanisms. As presented, the applied current reference generator has a large impact on the minimum SCR for stable operation. Besides the impact of the current reference generator, two major interactions contribute to instability mechanisms. These mechanisms comprise the interaction of the current control with the grid impedance and the interaction of the PLL with the current control and grid impedance. The next section presents the stability assessment for both mechanisms.

### **6.5 Methods for Transient Stability Assessment of Dual Sequence Current Controls in Weak Grids**

Stability in weak grids is critically affected by the current control, PLL, and current reference generator. This section focuses on the first two controller components. The current control could be unstable due to large line impedances because the impedances mainly define the control plant. Additionally, the interaction between PLLs, the current control, and the line impedance cause transient stability mechanisms. At first, the stability of the current control is analyzed using an LTI-model that accurately represents the PR-controller characteristics. Second, a method based on Lyapunov's functions to assess the transient stability of the current control and PLL is derived.

#### **6.5.1 Stability of PR-Current Controllers in Weak Grids**

Linear transfer functions can describe the current control based on PR-controllers if the PLL and current reference generator are neglected. This linear model enables the stability analysis of different weak grid conditions described by the SCR. The basic control structure of the *LCL*-filter is shown in Fig. 6.44. The complete *LCL*-filter is considered in this analysis since resonances and filter dynamics become critical in weak grid conditions. The model additionally considers the delay of the measurements denoted with *τ*d*,*m. Rearranging this block-diagram leads to the transfer functions for the grid current **i**2 to the current reference **i** ∗ 1 and for the grid current **i**2 to the grid voltage **v**S. The detailed derivation is shown in appendix A.5, and the closed-loop transfer functions are presented in 6.52 using the transfer functions defined in A.24. These transfer functions are valid in *αβ*-frame and can be applied to the *α* and *β* component separately.

**Figure 6.44:** Model of the current control for a converter with *LCL*-filter using PR-controllers.

$$G\_{\rm Conv}(\mathbf{v\_S} = 0) \quad = \quad \frac{\mathbf{i\_2}(s)}{\mathbf{i\_1^\*}(s)} = \frac{G\_{\rm IL} G\_{\rm 2f}}{1 - G\_{\rm IL} G\_{\rm 2f} G\_{\rm FB3}} \tag{6.52}$$

$$G\_{\rm S}(\mathbf{i}\_1^\* = 0) \quad = \quad \frac{\mathbf{i}\_2(s)}{\mathbf{v}\_{\rm S}(s)} = \frac{-G\_{2\rm f}}{1 - G\_{\rm IL}G\_{2\rm f}G\_{\rm FB3}}\tag{6.53}$$

The model is verified with time-domain simulations (numerical model) considering an averaged converter model with *LCL*-filter and current control. The parameters are identical to the hardware test bench presented in section 4.2.1. The SCR is varied by changing the impedances *L*2f and *RL*2f for different impedance ratios *r*S according to the low-voltage, medium-voltage, and high-voltage grid definitions presented in Table 3.1. For the analytical model, the transfer functions are applied to the *α* and *β* components simultaneously. The results for the step responses in Fig. 6.45 emphasizes the high fidelity of the analytical LTI-model.

The step responses show that the oscillations and overshoot get larger with decreasing SCR, which indicates a decreasing stability margin. To analyze this effect more accurately, Fig. 6.46 presents the eigenvalues of the transfer function *G*Conv. The findings are twofold: First, the impedance ratio highly affects the stability, and the inductive characteristic of the highvoltage grid makes it more vulnerable to control instability. Second, the SCR deteriorates the stability margin since the critical eigenvalues close to the imaginary axis move towards the right half-plane for decreasing SCR. However, the analyzed system is not unstable even for low SCRs.

The presented LTI-model sufficiently describes the PR-current control since it does not contain critical nonlinear parts. However, the interaction of the current control and PLL cannot be neglected during severe grid faults. Hence, more sophisticated methods are necessary to analyze the stability of this nonlinear system.

**Figure 6.45:** Comparison of the current step response of |**i***αβ*| between the analytical LTI-model and the numerical model considering different SCRs.

**Figure 6.46:** Comparison of eigenvalues of the *G*Conv for different impedance ratios and SCRs.

#### **6.5.2 Method for Transient Stability Assessment based on Lyapunov's Direct Method**

The Loss of Synchronization (LOS) caused by the coupling of the PLL with the current control in weak grids attracts much attention in recent research. Several contributions assess the LOS characteristics of the VOC with SRF-PLL and PI-controllers by nonlinear analysis techniques such as the Equal Area Criterion (EAC) and phase portrait [147], [158], [8]. However, these approaches suffer from several drawbacks. First, the EAC is only applicable for plants without proportional gain [159], which is not valid for the analyzed PLL model with current control. Second, the phase portrait is typically only applicable to second-order systems [97], [148]. Additionally, it is based on the manifold in the state-space and therefore relies on ODE-solvers such as standard numerical models. Hence, analytical methods based on the system equations are still demanded [8]. Lyapunov's direct method is a powerful technique to fill this gap.

The following section presents a Lyapunov function for VOC with SRF-PLL in weak grids considering resistive or inductive line impedances. To the best of the author's knowledge, this function was not derived before. Based on this Lyapunov function, an estimate for the Region of Attraction (ROA) can be extracted, which can be used to derive design criteria for the PLLs or identify critical grid scenarios.

The equivalent circuit of the VOC with an averaged converter model and PLL in the dq-frame is shown in Fig. 6.47. Due to the weak grid connection, the converter current **i** ∗ dq*,*PLL influences the PCC voltages *v*d*,*PCC and *v*q*,*PCC according to:

$$\begin{aligned} v\_{\rm d,PCC} &= -\omega\_1(t) L\_{\rm S} i\_{\rm q,PLL}^\* + R\_{\rm S} i\_{\rm d,PLL}^\* + v\_{\rm d,S} \ & \ , \\\\ v\_{\rm q,PCC} &= \omega\_1(t) L\_{\rm S} i\_{\rm d,PLL}^\* + R\_{\rm S} i\_{\rm q,PLL}^\* + v\_{\rm q,S} \ & \ . \end{aligned} \tag{6.54}$$

The equivalent circuit can be combined with the PLL model, which is also shown in Fig. 6.47.

**Figure 6.47:** Equivalent circuit and model for the interaction of the PLL and current control in weak grids.

**Figure 6.48:** Model for the dynamics of the PLL and current control in weak grids.

The low-pass filter of the PLL is neglected to reduce the system order and simplify applying Lyapunov's method. This structure indicates that the converter reference currents change the input voltage of the PLL *v*q*,*PCC and thus influence the dynamics of the grid synchronization. Since the scope of the analysis are the dynamics and not the steady-state, the inputs *θ* 0 and *ω*1 can be set to zero. Note that *ω*1*L*S should still be considered to include the impact of *L*S on *v*q*,*PCC correctly. These assumptions lead to the dynamic model shown in Fig. 6.48. This model can still describe steps in the grid phase angle *θ* 0 by changing the initial condition of *x*1, which corresponds to *δ*. The derived dynamic model, presented in Fig. 6.48, leads to the nonlinear state-space description:

$$\mathbf{X} = \begin{bmatrix} \dot{x}\_1 \\ \dot{x}\_2 \end{bmatrix} = \frac{1}{1 - k\_\mathrm{p} L\_\mathrm{S} i\_{\mathrm{d,PLL}}^\*} \begin{bmatrix} x\_2 + k\_\mathrm{p} \omega\_1 L\_\mathrm{S} i\_{\mathrm{d,PLL}}^\* + k\_\mathrm{p} R \dot{s}\_{\mathrm{q,PLL}}^\* - k\_\mathrm{p} \hat{V}\_{\mathrm{S},1} \sin \left( x\_1 \right) \\ \left( x\_2 + \omega\_1 \right) k\_\mathrm{i} L\_\mathrm{S} i\_{\mathrm{d,PLL}}^\* + k\_\mathrm{i} R\_\mathrm{S} i\_{\mathrm{q,PLL}}^\* - k\_\mathrm{i} \hat{V}\_{\mathrm{S},1} \sin \left( x\_1 \right) \end{bmatrix} \tag{6.55}$$

With these system equations, the equilibrium points **x**e can be derived by calculating **x**e = **x**|**X**˙ =0, which yields two different equilibria (**x**e1 and **x**e2) in the range of 0 *< x*1 *< π* according to:

$$x\_{1, \text{o1}} = \sin^{-1}\left(\frac{\omega L\_{\text{S}} i\_{\text{d,PLL}}^{\*} + R\_{\text{S}} i\_{\text{q,PLL}}^{\*}}{\hat{V}\_{\text{S},1}}\right), \; x\_{1, \text{o2}} = \pi - \sin^{-1}\left(\frac{\omega L\_{\text{S}} i\_{\text{d,PLL}}^{\*} + R\_{\text{S}} i\_{\text{q,PLL}}^{\*}}{\hat{V}\_{\text{S},1}}\right), \; (6.56) \; \dot{V}\_{\text{S},1} = \pi - \sin^{-1}\left(\frac{\omega L\_{\text{S}} i\_{\text{d,PLL}}^{\*} + R\_{\text{S}} i\_{\text{q,cell}}^{\*}}{\hat{V}\_{\text{S},1}}\right)$$

Chapter 6. Grid-following Converter Control for Fault Ride-Through

and

$$x\_{2,a1} = x\_{2,a2} = 0 \quad . \tag{6.57}$$

These expressions indicate that the equilibria shift with the voltage drop over the grid impedance *Z*S and thus depend on the converter reference currents **i** ∗ dq*,*PLL. The stability properties of these equilibria can be analyzed with the phase portrait, similar to the analysis presented in [146], which is based on the *P* − *δ* diagram of the EAC. For details on this analysis refer to [146]. The equilibrium *x*1*,*e1 is stable since the trajectories will converge to this point even after small perturbations. Consequently, *x*1*,*e1 is a Stable Equilibrium Point (SEP), which is denoted with *x*1*,*SEP. In contrast, *x*1*,*e2 is unstable even for small perturbations and thus is called Unstable Equilibrium Point (UEP) (*x*1*,*UEP). The UEP may serve as a stability boundary, i.e., if *x*1 exceeds this value, the system becomes unstable. Unfortunately, this analysis method cannot describe the dynamics of transient stability phenomena.

The dynamics significantly depend on the PLL design parameters. Tuning this PLL structure is straightforward since a second-order system accurately represents it. Hence, the PIparameters are designed according to the damping *ζ* and the settling time *t*set*,δ* [70, pp.131-136]. The PI parameter *k*p and *k*i can be derived as follows:

$$k\_{\rm p} = \frac{2 \cdot 4.6}{\hat{V}\_{\rm S,1} t\_{\rm sat,\delta}}; \qquad k\_{\rm i} = \frac{\hat{V}\_{\rm S,1} k\_{\rm p}^2}{4\zeta^2} \ . \tag{6.58}$$

Now, the model can be verified with a numerical simulation model using these design rules and the grid scenarios introduced in chapter 5. The numerical simulation model contains an averaged converter model, SRF-PLL, and current control. The converter parameters are again set to *V*ˆ S*,*1 = 325 V and *S* = 10 kVA, and the damping factor *ζ* is varied between 0.5 and 0.7. Fig. 6.49 and 6.50 present the system trajectories in the state-space (*x*1/*x*2-plain) for a resistive or inductive weak grid defined by SCR=1.25 and *r*S = 0*.*129 or *r*S = 10, respectively. As expected, the numerical model and analytical model show identical results. The simulated trajectories indicate that larger damping leads to decreasing overshoot and thus a larger transient stability margin. In the case of the inductive grid, a LOS can be observed for *ζ* = 0*.*5. The results indicate that the resistive grid is more stable than the inductive grid. The previous analysis based on phase portraits provides no significant benefit of the analytical

model compared to the time-domain simulation since the results still depend on ODE-solvers. At this point, Lyapunov's direct method is applied to derive stability criteria based on the system equations. Therefore, the Lyapunov candidate is chosen according to 6.59 since it achieved sufficient results for the PLLs in stiff grids (see section 5.8).

$$V = \int\_0^{x\_1} \sin\left(\sigma\right) d\sigma + \frac{1}{2} p x\_2^2 = 1 - \cos\left(x\_1\right) + \frac{1}{2} p x\_2^2\tag{6.59}$$

**Figure 6.49:** Comparison of the state trajectory for the SRF-PLL between the analytical and numerical model considering a weak resistive grid with SCR=1.25 and *r*S = 0*.*129 during reactive current injection **i**dq = [0 24*.*6 A]. The PLL is tuned to *t*set*,δ* = 0*.*1 s and *ζ* is varied from 0.5 to 0.7.

**Figure 6.50:** Comparison of the state trajectory for the SRF-PLL between the analytical and numerical model considering a weak inductive grid with SCR=1.25 and *r*S = 10 during active current injection **i**dq = [24*.*6 A 0]. The PLL is tuned to *t*set*,δ* = 0*.*1 s and *ζ* is varied from 0.5 to 0.7.

To apply this Lyapunov candidate to the dynamic model, the SEP must be shifted into the origin by adding *x*1*,*SEP in the trigonometric term according to:

$$\dot{\mathbf{X}} = \frac{1}{1 - k\_{\rm p} L\_{\rm S} i\_{\rm d,PLL}^{\*}} \left[ \begin{array}{c} x\_{2} + k\_{\rm p} \omega\_{1} L\_{\rm S} i\_{\rm d,PLL}^{\*} + k\_{\rm p} R\_{\rm S} i\_{\rm q,PLL}^{\*} - k\_{\rm p} \hat{V}\_{\rm S,1} \sin \left( x\_{1} + x\_{1, \rm S \rm EP} \right) \\\ \left( x\_{2} + \omega\_{1} \right) k\_{\rm i} L\_{\rm S} i\_{\rm d,PLL}^{\*} + k\_{\rm i} R\_{\rm S} i\_{\rm q,PLL}^{\*} - k\_{\rm i} \hat{V}\_{\rm S,1} \sin \left( x\_{1} + x\_{1, \rm S \rm EP} \right) \end{array} \right] . \tag{6.60}$$

Substituting the system equations according to 6.60 in the derivative *V*˙ yields:

$$\begin{array}{l}\dot{V} = \frac{\sin(x\_1)}{1 - k\_{\text{p}}L\_{\text{S}}i\_{\text{d,PLL}}^{\*}} \left(x\_2 + k\_{\text{p}}\omega\_1 L\_{\text{S}}i\_{\text{d,PLL}}^{\*} + k\_{\text{p}}R\_{\text{S}}i\_{\text{q,PLL}}^{\*} - k\_{\text{p}}\dot{V}\_{\text{S},1}\sin\left(x\_1 + x\_{1,\text{SEP}}\right)\right) \\ \quad + \frac{px\_2}{1 - k\_{\text{p}}L\_{\text{S}}i\_{\text{d,PLL}}^{\*}} \left(\left(x\_2 + \omega\_1\right)k\_{\text{l}}L\_{\text{S}}i\_{\text{d,PLL}}^{\*} + k\_{\text{l}}R\_{\text{S}}i\_{\text{q,PLL}}^{\*} - k\_{\text{l}}\dot{V}\_{\text{S},1}\sin\left(x\_1 + x\_{1,\text{SEP}}\right)\right) \\ \quad \dots \end{array} \tag{6.61}$$

This complex expression makes it challenging to derive a parameter *p* to guarantee *V <*˙ 0 in the whole state-space. Therefore, LaSalles invariance principle can be applied that limits the requirements for Lyapunov stability to a bounded region Ω1 [98]. Theorem VI and VII in [98, pp.58-59] are used in the following analysis and can be summarized as follows: Let Ω1 be a bounded subset of the state-space that is described by *V* (**x**) *< l*. Let Ω1 contain the origin **x** = 0 and Ω1 fulfills the condition *V*˙ (**x**) *<* 0 for all **x** = 0 6 , "then the origin is asymptotically stable, and above all, every solution in Ω1 tends to the origin as *t* → +∞" [98, pp.58-59]. Choosing *p* according to 6.62 leads to a region that fulfills these requirements. For the details on deriving this expression refer to appendix B.

$$p = \frac{1}{k\_1 \sqrt{\dot{V}\_{S,1}^2 - \left(\omega\_1 L\_s i\_{\rm d,PLL}^\* + R\_s i\_{\rm q,PLL}^\*\right)^2}}\tag{6.62}$$

With the Lyapunov function in 6.59, the contour *V* (**x**) = *l*, Ω1, and the ROA can be extracted. The method is tested for a resistive, weak grid considering different SCRs, i.e., 1.25 and 3.

**Figure 6.51:** Estimated ROA and numerical stability results considering a weak resistive grid with *r*S = 0*.*129 and SCR=1.25 (left) or SCR=3 (right) during reactive current injection **i** ∗ dq = [0 24*.*6] A or **i** ∗ dq = [0 10*.*2] A, respectively. The PLL is tuned to *t*set*,δ* = 0*.*1 s and *ζ* = 0*.*5.

Fig. 6.51 presents the results for the ROA. Moreover, the numerical simulation is performed for various initial conditions **x**0. Varying initial conditions of *x*1 represent phase jumps and different *x*2 correspond to frequency steps. The stability results for the trajectories starting from the initial conditions are plotted in the same figure. The red cross indicates unstable trajectories. A green circle indicates that the trajectory starting at this initial point will converge to the equilibrium.

The results confirm the theoretical expectation that any trajectory which starts within the ROA will converge to the SEP in the origin. Some trajectories outside the ROA may be stable since the extracted ROA is only an estimate of the real one. Extending the estimated ROA to the real one is an optimization problem of finding an optimum Lyapunov function for the analyzed system. However, the presented method accurately predicts a ROA of the system without solving the differential equations. The comparison between the two SCR scenarios shows that the ROA significantly shrinks for smaller SCRs. Moreover, the analysis shows that the proposed stability criterion according to the UEP in 6.56 is insufficient since dynamics in *x*2 tremendously decrease the stable range of *x*1.

Unfortunately, the presented Lyapunov function cannot be applied to inductive grids since *V*˙ has an unbounded non-negative region next to the origin. This problem can be solved by slightly changing the Lyapunov candidate according to [160, pp.202-205]:

$$V = \int\_0^{x\_1} \sin(\sigma)d\sigma + \frac{1}{2}px\_2^2 + \beta x\_2 \sin\left(x\_1\right) \quad , \qquad \beta = -1.7 \cdot pk\_\text{i}L\_\text{S}i\_{\text{d,PLL}}^\ast \text{ .} \tag{6.63}$$

The additional parameter *β* can be chosen to create a negative region of *V*˙ near the origin. However, determining this value is not straightforward and more details on the calculation are given in appendix B. The results presented in Fig. 6.52 indicate a very small ROA for very weak, inductive grids with SCR=1.25, whereas the ROA estimate for the SCR=3 shows a significantly larger stable region. Compared to the resistive grid, the inductive grid is particularly prone to LOS since the stable *x*2 range further decreases due to the coupling of the impedance *X*S with the angular frequency *ω*1.

**Figure 6.52:** Estimated ROA and numerical stability results considering a weak inductive grid with *r*S = 10 and SCR=1.25 (left) or SCR=3 (right) during active current injection **i** ∗ dq = [24*.*6 0] A or **i** ∗ dq = [10*.*2 0] A, respectively. The PLL is tuned to *t*set*,δ* = 0*.*1 s and *ζ* = 0*.*5.

The estimated ROA and stability region in the state-space enable transient stability assessment of two different operational scenarios. First, grid faults with phase jumps may lead to steps of *x*1, which could be outside the stable state-space region or ROA and thus would lead to LOS. For example, if a phase jump of *π/*2 occurs in the scenario for SCR=1.25 shown in Fig. 6.52, the system will be unstable. Contrarily, for SCR=3 the converter is stable even for faults with large phase jumps of 3*π/*4.

The second scenario covers reference steps of the converter currents, which shift the equilibrium on the *x*1-axis according to 6.56. Particularly interesting is the case where the SEP of the current references **i** ∗ dq = [0 0] pu is outside the stable region of the nominal operating point **i** ∗ dq = [1 0] pu. That means the converter control will be unstable for current reference steps from 0 pu to the nominal value.

Based on the estimated ROA for a given short-circuit power of the grid, the maximum nominal current *i* ∗ d*,*max for stable operation can be derived. This is done for the weak, inductive grid assuming different damping ratios *ζ* of the PLL. For better comparability, *i* ∗ d*,*max is normalized with the short circuit current of the grid. The results highlight that *i* ∗ d*,*max can be increased by at least 25% by choosing a larger damping factor for the PLL, as shown in Fig. 6.53. The same analysis is repeated by using a simulation model based on Fig. 6.48 and analyzing the stability of the step response of the currents. The current *i* ∗ d*,*max differs significantly between both models but the increase of the maximum current with the damping factor is in the same range of 25%. These findings confirm that the estimated ROA sufficiently predicts the stability analytically but may lead to conservative results. However, further efforts to improve the estimation of the ROA may increase its accuracy to track the stability boundary.

The presented transient stability framework analytically describes the LOS mechanism using Lyapunov's direct method and Lasalle's invariance principle. The proposed method and Lyapunov function evaluate stability of grid-following converters in weak grids by estimating the ROA. The analysis indicates the insufficient stability prediction of EAC-based approaches Chapter 6. Grid-following Converter Control for Fault Ride-Through

**Figure 6.53:** Maximum converter current *i* ∗ d*,*max for stable operation depending on the damping factor of the PLL considering a weak, inductive grid with *r*S = 10. The time constant of the PLL is tuned to *t*set*,δ* = 0*.*1 s.

and accurately predicts stability considering the dynamics of *x*2. Moreover, the ROA enables transient stability assessment of the PLL parameter design and can calculate the maximum converter current for stable operation analytically.

This chapter highlights that grid-following control might suffer from insufficient stability in weak grid conditions predominantly caused by the interaction of PLL with the current control. The current reference generator may further deteriorate the stability. The grid-forming converter control may enhance the control performance and stability in weak grids, which is proved in the following chapter.

# 7

#### Grid-forming Converter Control for Fault Ride-Through in Weak Grids