Along with the thermal conductivity of the substrate, Thermal Boundary Resistance (TBR) is an important parameter to affect the overall rise in temperature of a device [37]. The thermal effects of the device are boosted by TBR which is resulted from the interface for the growth of dissimilar materials. TBR is a measure of the resistance imposed by the interface to heat flow due to the different dynamics of the phonons and the poor quality of the crystal near the boundary. It is defined as the maximum temperature increase by the maximum power dissipation of the device. The TBR in commercial GaN HEMTs on SiC can reach levels greater than 6 × 10−4 cm2K/W which can increase the maximum temperature of the device by up to 40–50% [38,39]. The increase in TBR causes an offset to the advantages offered by the substrate with high thermal conductivity due to the discontinuity of the temperature gradient in TBR layers located at the GaN substrate interface [40]. Thermal conductivity for GaN and different substrate materials at 300 K and TBR values of GaN/ substrate interface simulated in [41] are listed in Table 1. The lower TBR values of GaN on Si substrate than that of SiC substrate is mainly due to the different thermal expansion coefficient [42], the roughness of the substrate materials as well as the defect related to the growth techniques. The high value of TBR at the interface of high thermal conductivity substrate and GaN could be reduced and has additional advantage if it has a better thermal coupling and fewer interface defects while low thermal conductivity like sapphire has a less significant influence of TBR on transporting heat [43].

**Table 1.** Temperature-dependent thermal conductivity of GaN/different substrate materials, TBR values for GaN/substrate interfaces used in simulations are listed [41,44].

#### *1.3. Evolution of GaN HEMT*

1.3.1. Different Gate Structure Designs

The HEMT structure was based on T. Minura et al. (1975) [45] and M.A. khan et al. (1994) [5]. At the interface of AlGaN and GaN, there exists 2-dimensional electron gas (2DEG) with high electron mobility owing to the difference in spontaneous polarization

and piezoelectric polarization [46]. Hence the device operates as a normally-on device naturally. To deplete the 2DEG channel, a gate electrode on top of the AlGaN layer has a negative gate voltage concerning drain and source electrode applied. This type of device is known as depletion-mode (D-mode) HEMT. Moreover, there are two types of D-mode HEMT, namely with a Schottky gate electrode or with an insulating gate [47]. The first d-mode HEMT introduced had a Schottky gate electrode in which the metal gate electrode is directly deposited on top of AlGaN. Ni–Au or Pt metals were used to form the Schottky barrier [23,48,49]. In insulate gated d-mode HEMT, an insulating layer is placed in between the gate electrode and AlGaN similar to that of MOSFET to block the gate current [50]. Schottky gate and insulated gate d-mode HEMTs are shown in Figure 3.

**Figure 3.** (**a**) Schottky gate D-mode HEMT (**b**) Insulated gate D-mode HEMT.

D-mode HEMT is not preferred in system applications as it requires a negative bias to be applied. On the other hand, there is also a concern in fail-safe operation. Therefore, Enhancement-mode (E-mode, normally-off) device is favored and has become one of current focuses of technology development. To create e-mode devices, there are five popular structures: recessed gate, implanted gate, pGaN gate, direct-drive hybrid, and cascode hybrid [47]. For GaN HEMT in RF applications, the most common fabrication technique used for modifying the threshold voltage is "gate-recess". This process reduces the barrier thickness under the gate metal. The basic structure of gate recess HEMT is shown in Figure 4a.

**Figure 4.** (**a**) Basic structure of Gate-recess HEMT. (**b**) Schematic structure of p-GaN Gate HEMT.

There are also approaches to obtain E-mode devices by heterostructure or gate stack designs. Ohmaki et al. proposed a double-barrier-layer AlGaN/GaN HFET in 2006. The use of double-barrier-layer sustains the device at a BV of 435 V, Ron,sp of 1.9 mΩ cm2 , with a threshold voltage of −0.1 V [51]. Inter University Microelectronics Centre (IMEC) presented another E-mode AlN/GaN/AlGaN HFET structure in 2010 with a double heterostructurebarrier layer. The double structure comprises of a high concentration 2DEG at the surface of the hetero structure and an ultrathin AlN barrier layer grown on silicon substrate; and the structure maintains a BV of 580 V, with an Ron,sp of 1.25 mΩ cm2 , and a threshold voltage of about 0 V [52]. Mizutani et al. in 2007, proposed an E-mode AlGaN/GaN HFET with a thin InGaN cap layer. The proposed structure shifts the threshold voltage towards

the positive direction by rising the conduction band of the AlGaN/GaN via the use of a polarization-induced field in the InGaN cap layer [53]. Ostermaier et al. in 2009, proposed an ultrathin InAlN/AlN barrier HEMT that have high performance under normally off operation. They selectively etched the n++ GaN cap layer structure, which in-turn controls the width of the ultrathin barrier layer [54]. The proposed structure operates with a threshold voltage of 0.7 V, a maximum transconductance of 400 mS/mm and a maximum output current of 800 mA/mm. Hughes Research Laboratories, in collaboration with the Next Generation of Nitrides Electronics Project from the US Defense Advanced Research Projects Agency (DARPA), proposed an E-mode HFET with a double-barrier layer via selective-area molecular beam epitaxy (MBE) [55]. For the integrated E-mode and D-mode AlN/GaN/AlGaN double-heterojunction field-effect transistors (DHFETs) on a single SiC substrate, an E-mode channel was achieved without additional procedures or compromise in the electrical characteristics. The idea of developing a monolithic integrated E-mode and D-mode device can be the groundwork for direct-coupled field-effect transistor (FET) logic circuits. Guowang Li et al. proposed an E-mode AlGaN/AlN/GaN HFET having 70% Al composition comprising of a thick AlGaN layer (17 nm), an AlN layer (0.6 nm) and an Al2O3 (4 nm) layer. They used Ni/Au in the Schottky gate metal instead of Al/Au thereby enhancing the threshold voltage from −1.0 V to −0.13 V [56]. Chiu et al. proposed an E-mode HFET comprising of a composite dielectric layer via N2O plasma oxidation technology. The composite dielectric layer (Al2O3/Ga2O3) after the oxidation in the N2O for the AlGaN barrier layer improves the threshold voltage from −3.6 V to 0.17 V [57]. Based on this structure, Chiu et al. presented an E-mode HFET with a high-*k* composite dielectric layer in 2012. The AlGaN barrier layer was oxidized by nitric oxide (NO) gas prior to the Schottky metal gate deposition. After the oxidized AlGaN barrier layer stack (Al2O3/Ga2O3) is formed, a dielectric film of gadolinium oxide (Gd2O3) was deposited to complete the structure thereby, enhancing the threshold voltage from −3.15 V to 0.6 V [58]. Massachusetts Institute of Technology in collaboration with Harvard university presented one E-mode HFET with a scandium oxide (Sc2O3) high-*k* dielectric. In the study, Wang et al. introduced a Sc2O3 high k-dielectric layer in the HFET to reduce the invert leakage current thereby having the switch-current ratio (*I*ON/*I*OFF) reach 10s [59].

By reducing AlGaN barrier thickness, it can result in a reduction of polarization induced 2DEG and the threshold voltage is shifted positively with the help of the workfunction of the metal gate. A positive threshold voltage can be achieved with a deep enough gate recess etching thus forming an E-mode HEMT [60]. A chloride-based dry inductively coupled plasma reactive ion etching (ICP-RIE) for gate recess etching has been employed by several groups [61–66] which can effectively change the threshold voltage to the positive direction of AlGaN/GaN HEMT. Damage in the subsurface was also reported from ICP dry etching due to low etch selectivity between materials which increases the gate-leakage current [67]. The damages were found to be repaired after post-etching rapid thermal annealing (RTA) at 700 ◦C [65,66]. For the RF HEMT structure, recessed gate enhances the device performance by providing a better gate control capability of the channel carriers. On the other hand, due to the repaired damage with proper recessed gate process, flicker noise characteristics were reduced, which is beneficial for RF circuit applications such as voltage-controlled oscillators (VCOs) and mixers [68,69]. On the other hand, p-GaN gate technology is more popular for the fabricator of e-mode power GaN HEMT device. The schematic structure of p-GaN gate HEMT is shown in Figure 4b. The conduction band of the AlGaN is risen above the Fermi level when compared with a standard Schottky gate normally-on HEMT due to the presence of p-GaN cap and results in the depletion of the 2DEG channel. Uemoto et al. first proposed a p-AlGaN gate normally-off HEMT [70]. The thickness of the AlGaN barrier as well as Al-concentration needs to be defined appropriately to achieve an efficient depletion region in the channel [71–74]. A high doping concentration of Mg, a p-type dopant, (>1018 cm−3 ) is necessary for the efficient depletion at the interface of the metal gate/pgate [75]. However, the hole concentration can be reduced at a high temperature above

500 ◦C due to the formation of Mg-H complexes [76]. Hence, proper care is necessary during device processing like annealing of Ohmic contacts so that Mg concentration does not reduce. Another important feature is the choice of the metal gate as the threshold voltage of the device depends on metal/p-GaN Schottky barrier height. In this aspect, much researches have been done on metal gate work-function influence on p-GaN electrical behavior [77–80]. Schottky metal gates have shown improvement in lowering the leakage and increasing the threshold voltage than Ohmic gate [77,78]. Presently, the TiN gate is one of the good solutions due to its thermal and chemical stability along with the processing compatibility [81–84]. A p-GaN gate HEMT with a "self-aligned" process using Mo-based gate was demonstrated which employed "gate first" process [85]. Mo gate sustained the high-temperature annealing process of source-drain ohmic contact without the barrier degradation. Although p-GaN gate HEMT has reached commercialization, their reliability issues [80] need intensive researches.

#### 1.3.2. N Polar vs. Ga Polar

Typically group III-Nitride devices are fabricated using the Ga-polar (0001) orientation. However, the inverted N-polar polarity possesses a numerous advantage over Ga-polar counterparts. The absence of inversion symmetry in wurtzite group III-Nitride results in opposite polarization of N-polar crystal and Ga-polar crystal. Hence, the polarization induced electric fields of Ga-polar heterostructures is opposite to that of N-polar counterparts which results in formation of 2DEG of N-polar heterostructures above the wide-bandgap barrier layer instead of below [86]. The advantages offered by N-polar GaN HEMTs over Ga-polar HEMTs are as follows: (i) N-polar heterostructures has a strong back-barrier due to its inherent wide-bandgap Al(Ga)N back-barrier for electron confinement which reduces the effects due to short-channel [87], (ii) N-polar HEMTs has low-resistivity Ohmic contact as the channel layer with lower surface barrier to electrons and a narrower bandgap can contact 2DEG of N-polar HEMTs rather than contacting through wide-bandgap Al(Ga)N barrier [88,89] which results in the possibility of lowering the contact resistance by using selective regrowth of ohmic area in N-polar structure, (iii) N-polar heterostructure has improved scalability. The effective gate-channel distance is reduced by the quantum displacement of the 2DEG in N-polar HEMT which is opposite to that of Ga-polar HEMTs owing to the reduction in effective gate-channel capacitance due to quantum capacitance [90]. Such enhancement results in higher N-polar transconductance than that of Ga-polar with same gate-channel thickness. The aspect ratio as well as the charge density under the gate of N-polar HEMTs can be controlled independently where the enhancement of charge depletion due to the scaling of channel thickness are compensated by increasing the thickness and the polarization of charge-inducing back barrier. Whereas, gate aspect ratio in Ga-polar HEMT depends on the barrier thickness and there is a trade-off between the charge density under the gate and the barrier thickness [91]. N-polar heterostructure does not required intentional n-type doping for the formation of 2DEG [89,92,93] due to the presence of high-density unintentional bulk and surface donors [94]. A N-polar GaN HEMTs epitaxy grown by MOCVD on 4◦ off-cut 2-inch diameter sapphire substrate at UCSB for X-band power performance transceiver systems was reported with 2 tone results at 10 GHz [95]. The reported HEMTs structure is similar with that of structure reported by X. Zheng et al. [96]. The reported HEMT device shows very little 3rd order distortion in intermodulation and 65% of single tone high power added efficiency (PAE) with 3 W/mm power density which can be scaled favorably with 15 V drain voltage. A deep recess W-band power N-polar GaN HEMTs utilizing a new atomic layer deposition (ALD) ruthenium (Ru) gate metallization process with PAE of 33.8% and 6.2 W/mm high power density was demonstrated [97]. The demonstrated HEMTs has an outstanding control over the DC-RF dispersion due to presence of deep recess structure in conjunction with SiN thin passivation layer and has a high gain as the narrow 48-nm gate trench was filled by ALD Ru metal.

#### *1.4. CMOS Compatible Process for GaN HEMT*

In wireless communication, to respond to the growing demand for high data rates, there is a push to a higher operating frequency, switching to millimeter-wave from the congested sub 6 GHz band. Beyond operational speed of power amplifiers, output power (Pout) and power added efficiency (PAE) in RF Front End Modules are critical for next-generation portable devices and small cells. As opposed to CMOS, the high-power handling capabilities of GaN are advantageous for mm-wave operations [98] as the more energy-efficient system can be achieved owing to its capability in the high output power with high efficiency at high-frequency. However, the integration of GaN HEMTs remains one of the main concerns. The current limitation of GaN RF technology is due to the use of expensive older generation Au-based processing as well as non-Si substrates [99]. Hence to make GaN devices for RF and MM-wave applications, migrating to 200 nm Si platform and using standardized CMOS fabrication tools for manufacturing the device become a crucial step to improve yield and reduce the cost. Similarly, the CMOS compatible technology can also benefit the development of GaN devices for power electronics. A CMOS-compatible 110 V/650 V e-mode GaN HEMT with excellent power converter switching performance with high robustness was fabricated on 6-inch GaN on a Si wafer [100]. Figure 5 shows an example fabrication process flow of GaN devices. GaN devices with low RF loss, low buffer dispersion as well as good leakage blocking capability have been demonstrated by integrating the device on the Si platform based on the Au-free, Si CMOS compatible process [98,101–103]. To enhance the functionality as well as the performance of the RF modules, various approaches to integrate CMOS and GaN devices have been developed [104,105].

**Figure 5.** Gate-first process flow for the fabrication of GaN devices. Five device splits were realized based on differences in gate processing [98].

#### *1.5. GaN-Based CMOS Technology*

A lot of demonstration has been done on power integrated circuit based on GaN [106–108] which depends on the integration of E-mode and D-mode n- type HEMTs. However, these E/D mode circuits have reduced output voltage swing and also suffers from static power dissipation. Therefore, a CMOS-like circuit technology is required to increase the efficiency of ICs based on GaN as this circuit technology has negligible static power consumption, has higher noise immunity and less circuit complexity [109].

However, the challenges of the monolithic integration of the p-type GaN FETs with n-type GaN FETs along with lack of high-performance of p-type GaN FETs are the major obstacle towards achieving high efficiency GaN-based ICs. A various epitaxial structures of p-type GaN FETs have been demonstrated [110–117]. A GaN complementary inverter circuit comprising of both E-mode n-type GaN FET and p-type GaN FET monolithically integrated on Si Substrate without regrowth technology was also demonstrated [118]. The probe station with thermal chuck were used to characterize the fabricated inverter under high operation temperature. The fabricated circuit shows an outstanding transfer characteristics up to 300 ◦C with maximum recorded voltage gain of about 27 V/V at 0.59 V input voltage with 5 V as VDD supply. A very high density of 2D hole gas (2DHG) induced by the polarization at the interface of GaN/AlN was discovered [119] which led to the development of p-channel heterostructure field effect transistors (HFETs) that reach the linear current density of 100 mA/mm [112]. A p-channel MISFET with a recessed-gate was grown by metalorganic chemical vapor deposition (MOCVD) using p-GaN/AlGaN/GaN hetrostructure on Si substrate [113,118]. The fabricated structure contains both 2-dimensional electron gas (2DEG) and 2-dimensional hole gas (2DHG) without regrowth technology which is suitable for implementing GaN- based complementary circuit. The fabricated long channel p-type device when compared with p-FET GaN/AlGaN on sapphire substrate exhibits state of the art on-off ratio performance. A p-channel 2DHG GaN/AlN transistors which can break the barrier of GHz speed was demonstrated [120]. The fabricated transistor exhibits an on-current density of 428 mA/mm and a cut-off frequency of 20 GHz. A wide-bandgap CMOS platform formed using these fabricated p-channel HFETs along with excellent performance n-channel HFETs [121] was expected to achieve a new domain in the RF and power electronics applications [122].

In the later paragraphs, we will review in more detail the progress and performance of GaN on Si devices. Moreover, the progress in hetero-integration will also be described.

#### **2. GaN HEMT on Si**

#### *2.1. GaN Epitaxial Growth on Silicon*

Silicon substrate is a general and commercial materials in semiconductor technology. Actually, a good epitaxy must be fine-matched in lattice and thermal expansion coefficient between GaN and heterogenous substrate, like Si, Sapphire, SiC . . . etc. The related summary in physical parameters is listed in Table 2 [123].

**Table 2.** The lattice and thermal mismatch of Si, SiC, Sapphire, AlN, and GaN.

Due to the mismatch of lattice constant and thermal expansion coefficient between Si and GaN, it is more difficult to achieve high quality GaN structure growth on Si [124–126]. In general, a lot of defects exist, and the gallium nitride layer may crack when cooling process. In order to solve these problems, gallium nitride epitaxial layers with high uniformity, high quality and no cracks can be grown on silicon substrate by growing buffer layer as shown in Figure 6 [12,127]. The buffer layer can be designed in the following two ways: (1) AlN/GaN superlattice growth through the step gradient AlGaN layer [128], and (2) AlGaN/GaN superlattice [129]. The bending of the wafer will increase with the increase of the thickness. A multilayer-buffer structure reduces the tensile stress caused by the huge difference in thermal expansion coefficient between GaN and Si. It's useful for inducing compressive strain in the growth process, as to counteract tensile strain introduced in the cooling process, prevent cracking and produce a flat wafer.

**Figure 6.** (**a**) Schematic cross-section of the typical epitaxial layer structure used for the manufacture of GaN-on-Si HEMTs. (**b**) TEM image of a GaN/AlN superlattice buffer layer and (**c**) a step graded AlGaN buffer layer, both on Si substrates [12].

Furthermore, the breakdown voltage in GaN HEMT is affected by the quality and resistivity of GaN-based templates. In order to operate an efficient GaN channel, it also needs higher resistivity buffer layer to prevent the DC leakage current and AC coupling. The characteristics of GaN high-frequency power amplifiers will change with the resistance of the underlying buffer layer, which is mainly due to the signal coupling effect. However, several groups have used different methods to improve the buffer layer resistivity, which employed p-type dopant (Mg) to enhance GaN buffer structure (n-type intrinsically). Another method is using Carbon dopant which plays a more attractive role in buffer layer. Compared to Mg case, the storage effect of Carbon-doped method isn't strong. According to doped buffer layer, the carrier concentrations and electrical properties (breakdown voltage) are adjusted by varied epitaxial conditions [130].

On the other hand, the top barrier layer includes AlGaN or InAlN, which results in 2DEG of HEMT through polarization charges in nitride-based materials are critical. While the thin AlGaN layer is grown on GaN channel layer, the Al content and thickness would be limited due to the lattice mismatch of GaN. The interface charge could be adjusted by varied barrier thickness and Al compositions. Compared to AlGaN, InAlN could reduce epitaxial defects as a result of thicker critical thickness. It shows that a good lattice-matched InAlN (18% In) exhibits a stronger spontaneous polarization to generate a higher channel charge density [131].

#### *2.2. Power GaN Performance Si Substrate*

As described in Section 1, the traditional power HEMT structure uses a Schottky metal to modulate the 2DEG in the channel. Generally, the metal stack Ni/Au is used for the HEMT. However, in order to efficiently control the gate leakage current, high-k gate dielectric layer was employed to form metal–insulator–semiconductor (MIS) gate, [132] for commercial power GaN HEMT on Si. The passivation layer provides additional protection and reduces the current loss in the surface state of devices. The breakdown voltage of GaN power components on Si in the low- and medium-power fields are predicted above 900 V, and the GaN shows very high potential in power applications due to the benefits of a low switching loss and lower cost [133].

Furthermore, the power electronics application represents one major market in the developments for GaN power devices like p-GaN HEMTs for enhancement-mode (Emode) operation. The breakdown voltages for p-GaN HEMTs have exceeded 1000 V (Ron,sp of 2 mΩ cm2 ). In power switching applications, a normally-off (enhancement-

mode) GaN HEMT is desirable due to the safe-operation formation and efficient gate control to switch on/off. A variety of e-mode GaN HEMTs are fabricated by using p-GaN gate [74], gate recess [134], or plasma treatment techniques. The p-GaN gate HEMT showed a good performance, reliability, and commercialization. Figure 7 shows the band structures of normally-on AlGaN/GaN HEMTs and normally-off p-GaN/AlGaN/GaN HEMTs. The 2DEG channel is depleted at a zero-bias condition as the conduction band energy of AlGaN is lifted due to the p-GaN region. The electrical characteristics of the p-GaN gate HEMT shows VTH, the VGS limitation, and the gate leakage current (IGSS) depend on the structure of the gate stack by using normally on and off system [135]. In order to deplete the 2DEG channel at VG = 0, the general AlGaN thickness is 10~15 nm, and the thickness of the p-GaN gate is 50~100 nm. A doping Mg concentration of the p-GaN (or p-AlGaN) gate is around 1018~1019 cm−3 .

**Figure 7.** (**a**) Cross-sectional schematic of p-GaN gate HEMT [135] and (**b**) schematic of the operation principle of the normally on HEMT and (**c**) normally off HEMT [74].

#### *2.3. RF GaN Performance Si Substrate*

GaN technology that can offer high output power and efficiency at high frequencies is regarded as the most critical technology to reduce the complexity in designing upcoming mm-wave band communication system for 5G or beyond applications. In particular, GaN on Si technology that can greatly reduce production costs has attracted more attention. However, due to the challenges in obtaining higher-quality epitaxy on Si, RF GaN HEMT was fabricated primarily on SiC for high-frequency applications until 2014 when MACOM announced the mass production of 4" GaN on Si technology. Due to the continuous improvement of epitaxial technology, almost all major semiconductor foundry starts to invest heavily on the development of GaN on Si technologies.

In order to develop RF GaN HEMT with superior high-frequency characteristics, we can refer to the equivalent circuit [136] shown in Figure 8, the small signal model of a GaN HEMT includes gate parasitic capacitance and resistances. According to Eq (1)(2) [137], we must decrease capacitance [138], ohmic contact resistance [139], gate resistance [140] and increase transconductance [141] in order to maximum the fT and fmax.

$$\mathbf{F\_T} = \frac{\mathbf{g\_m}}{2\pi (\mathbf{C\_{GS}} + \mathbf{C\_{GD}}) [1 + (\mathbf{R\_S} + \mathbf{R\_D})\mathbf{G\_{DS}} + \mathbf{g\_m} \times \mathbf{C\_{GD}}(\mathbf{R\_S} + \mathbf{R\_D})]} \tag{1}$$

$$F\_{\rm MAX} = \frac{F\_{\rm T}}{2\sqrt{(R\_{\rm i} + R\_{\rm S} + R\_{\rm G}) \times G\_{\rm DS} + 2\pi F\_{\rm T} R\_{\rm G} C\_{\rm GD}}} \tag{2}$$

**Figure 8.** Small-signal equivalent circuit for the tested MOSFETs.

To operate at high frequency, the gate length must be minimum to reduce gate capacitance, as shown in Figure 9. But, the parasitic resistance will be increased and degrade the high frequency performance [142], the T-shaped gate becomes a key element to reduce the gate parasitic resistance. The height and width of the T-shaped gate should be optimized for both capacitance and resistance values. Keisuke Shinohara et al. [142] demonstrated the most suitable T-gate shape through simulation based on gate capacitance as show in Figures 10 and 11. Benchmark of cut-off frequency versus LG [143–148] illustrates the importance of gate length shrinking to increase fT. Both NTU [149] and Intel [143] demonstrated 40 nm gate length GaN HEMT on Si with fT/fmax higher than 300 GHz, though the current record fT/fmax values of 450 GHz was achieved by HRL [144] with the 20 nm Gate GaN on SiC technology.

**Figure 9.** FT and FMAX versus Lg [142].

**Figure 10.** Simulation for T-gate capacitance [142].

**Figure 11.** Benchmark for frequency versus Lg.

There are many device technologies have been developed based on GaN HEMT on SiC substrates. Most of those technologies can be applied on GaN HEMT on Si as well. We will describe some of the typical examples below. Hiroyuki Ichikawa et al. [150] designed 150 nm gate length InAlN/GaN and AlGaN/GaN HEMT, the AlInN/GaN HEMT showed high GM and exhibited a fT/fmax of 70/150 GHz. Michael L. Schuette et al. [141] demonstrated a peak fT/fmax of 348/340 GHz for 27 nm gate length on InAlN/GaN HEMT with gate recess. Ezgi Dogmus et al. [151] used ultra-thin AlN (4 nm) barrier to replace AlGaN and in-situ SiN demonstrated a fT/fmax of 55/235 GHz. Jeong-Sun Moon et al. [152] designed 50 nm gate length AlGaN/GaN HEMT with graded AlGaN barrier and n++regrowth, and the HEMT exhibited a ft/fmax of 156/308 GHz. Lei Li et al. [153] demonstrated fT/fmax of 250/204 GHz using n++regrowth for InAlN/GaN HEMT on Si substrate. Figure 12 benchmark fT versus fMAX [141,150–155].

**Figure 12.** Comparison of the measured fT and fMAX in GaN-based HEMTs from literature.

GaN HEMT on Si also have high load pull result comparable to SiC substrate [155], nevertheless, GaN HEMT on Si substrate shows high potential. D.C. Dumka et al. [156] demonstrated 13.1 dB linear gain, maximum POUT = 34.5 dBm, output power density 7 W/mm and PAE 65.6% at 10 GHz in X band. Diego Marti et al. [157] showed 6 dB linear gain, output power density 1.35 W/mm, and PAE 12% at 94 GHz in W band.

For used in 5G mm-Wave communications, higher data rates require more complex communication systems such as Multi-input Multi-output (MIMO). MIMO employs complex frequency and phase division. So high linearity devices are required to avoid interaction each complex frequency bands. J. Vidkjær et al. [158] summarized some solution for linearity include geometrical, layout and epitaxial design. Weichuan Xing et al. [159] designed 150\*150 nm nanostrip gate hole structure by BCl3/Cl2 and Al2O3 insulator which have good linearity. Jeong-sun Moon et al. [160] used AlGaN/GaN graded channel which have good PAE and linearity. Bin Hou et al. [161] used barrier layer of sandwich structure and AlGaN back barrier which show good power performance and linearity. Kai Zhang et al. [162] used Fin-FET HEMT that have good linearity compared to the planar HEMT.

#### **3. GaN HEMT on Silicon-on-Insulator (SOI) Substrates**

*3.1. GaN Epitaxial Growth on Silicon-on-Insulator (SOI) Substrates*

In epitaxial issues, the bowing effect always exists on the hetero-interface due to the lattice mismatch and the thermal expansion differences. T. Egawa from Nagoya Institute of Technology has reported a relative function of the wafer bowing and epitaxial thickness of AlGaN/GaN HEMT on Si [163], as shown in Figure 13. A thicker GaN/AlN superlattice structure exhibits higher bowing value in these experiments. It is a wafer bowing reference in HEMT epitaxial developments on Si. However, based on the outstanding electrical isotropic and mechanical features of the SOI substrate, it is expected to be a significant contender as a technological platform for mass production of GaN HEMT in the near future. However, the SOI substrate still suffer from a bowing effect, which may result in broken wafers or difficulties in subsequent fabrication processing steps, as well as a lower temperature tolerance during wafer process. Recently, from our study, we demonstrate the growth of AlGaN/GaN heterostructure on a 150-mm SOI substrate with different boron doping concentration in handle wafer, as shown in Figure 14. By heavily doping Boron in silicon handle wafer of SOI substrate, we can effectively reduce the bowing effect, increase the thickness of the epitaxial layer, and further improve the device performance. Heavily doped handle wafer causes a reduction in wafer bowing by >97%, as shown in

Table 3. Moreover, it can be seen from Figure 15 that the issue of edge cracks for the heavily doped SOI substrate (sample B) are great improved, and there is no peeling phenomenon, which means that the heavily doped SOI substrate have better ability to resist the stress generated during GaN epitaxy. Figure 16 is the comparison of the half-width values of the GaN epitaxial layer (102) measured by X-ray diffraction analyzer. It can be observed that the BOW value is related to the epitaxial quality. That is, the more severe the bowing effect, the worse the epitaxial quality, which has also been demonstrated in GaN on SiC and bulk GaN substrate [164,165].

**Figure 13.** Wafer bowing as a function of total epitaxial layer thickness [163].

**Figure 14.** Schematic cross-section of AlGaN/GaN HEMT on SOI substrate.

**Figure 15.** Top section of OM image (**a**) Sample A. (**b**) Sample B.

**Figure 16.** Asymmetric (102) XRD ω-scan rocking curves of substrate with big BOW value (black) and small BOW value (red) measured from surface.

#### *3.2. Power GaN HEMT on SOI*

In the past several years, enhancement mode (E-mode) AlGaN/GaN HEMTs have been demonstrated to be the potential devices for next generation high efficiency power switches and converters application [2,166]. Currently, SiC [19] and Si [167] are the most popular substrates for GaN HEMT. However, GaN-on-SOI has been considered as a highly potential option which may provide better performance in high frequency and high-power system, owing to its capability in defect reduction of epitaxial layer, as described in Section 3.1.

According to our studies shown in Section 3.1, the BOW value of GaN on SOI substrate is close related to threading dislocation density (TDD) and epitaxial quality. The HEMT devices on SOI substrate with lower BOW value exhibit 1 order smaller off-state leakage and 8.4% smaller specific on resistance, also 68.8% improvement is observed in 3-terminal off-state breakdown voltage (BVGD), shown as Figure 17. Moreover, the dynamic RON degradation can be reduced. This implies that by heavily doping in handle wafer not only reduce the bowing effect, but also improve the quality of substrate and the performance of high-power device.

**Figure 17.** (**a**) IDS-VGS characteristics of HEMTs with big BOW value (Device A, black line) and small BOW value (Device B, red line) (VDS = 10 V). (**b**) Three-terminal off-state characteristic of the E-mode HEMTs at VGS =−5 V.

GaN-on-SOI substrate exhibits a capability to improve the power device performance and also have been proven by many research teams [168–172] including smaller reverse recovery leakage [169], higher breakdown voltage [168,169] and smaller vertical leakage [172]. Kevin J. Chen et al. [169] reported the SOI substrate with a reduced stress in the GaN epilayers (shown as Figure 18a) and an excellent E-mode HEMTs on SOI produced by fluorine plasma implantation method with a high ON/OFF current ratio (108–109 ), large breakdown voltage (1471 V with floating substrate), and also a smaller vertical leakage at reverse bias, as shown in Figure 18b.

**Figure 18.** (**a**) GaN-on-SOI and GaN-on-Si (bulk) wafers under Micro-Raman spectroscopy. The E2 peak on the GaN-on-SOI wafer was mapped (Inset) (**b**) Characteristics of vertical leakage on GaN-on-SOI and GaN-on-Si (bulk) platforms [169].

Moreover, most GaN power switching systems are currently produced using a multichip approach, resulting in significant complexity and expense [173–175]. Monolithic integration of GaN-based power devices has steadily gained interest for GaN high-power systems. The benefits of monolithic integration of GaN power systems on a single chip include minimizing parasitic inductance, reducing die size, and enhancing design flexibility [107,176]. To prevent mutual influence between the devices in monolithic GaN power integrated circuit, it suggests that the low and high side HEMT transistors must be fully isolated for a half bridge, as shown in Figure 19 [172,177]. However, it is challenging to accomplish on GaN-on-Si substrates because those HEMTs share a common conductive Si substrate. Figure 20a shows the transfer characteristics of a GaN monolithic half bridge with a common Si substrate biased from −200 to 200 V at 150 ◦C. Significant variations in threshold voltage (Vth) and drive current are seen when the Si substrate is biased negatively. Nevertheless, using GaN-on-SOI and a trench isolation method, this

issue could be overcome [172,177,178]. The transfer characteristics of GaN-on-SOI HEMT, as shown in Figure 20b, illustrate the benefits of device isolation. When the substrate of a neighboring device is biased between −200 V and 200 V, transfer characteristics vary relatively little, which is in sharp contrast to characteristics on a silicon substrate.

**Figure 19.** Schematic cross-section of the isolated e-mode p-GaN HEMT [177].

**Figure 20.** Transfer characteristics while simultaneously biasing the silicon substrate from −200 V to 200 V (**a**) with a common silicon substrate (**b**) with SOI substrate [177].

#### *3.3. RF GaN HEMT on SOI*

In addition to the power devices, AlGaN/GaN HEMTs have also been demonstrated to be the potential devices for RF applications [179–182]. Moreover, GaN-based MMIC (Microwave Monolithic Integrated Circuit) has steadily gained interest as compared to a system in package or a multi-chip module, since monolithic integration of GaN RF systems allows for smaller, cheaper, and less complicated circuitry [181,182].

SOI substrate is outstanding for its better vertical isolation performance and a lower substrate loss [183]. Besides, when compared to GaN on Si substrate devices, GaN on SOI substrate devices demonstrated better DC, breakdown voltage, and RF properties [170,184,185]. It was demonstrated that GaN-on-SOI substrates perform better in terms of tensile stress relaxation and surface flatness than Si substrates. It can result in a reduction of defect density, which is further supported by pulse and low-frequency noise measurements. The SOI substrate capacitances extracted from the small signal model are lower than the HR-Si substrate, as illustrated in Figure 21, owing to the series connection of device layer, buried oxide layer, and handle wafer of SOI substrate. As a result of the small substrate capacitances of SOI substrate shunt to the CDS, the effective CDS items that dominated the feedback capacitance were decreased. Furthermore, the utilization of SOI substrate can increase the device's bandwidth and linearity was proven at the same time, as shown in Figure 21b [185].

**Figure 21.** (**a**) Cross-sectional structure of MISHEMT on SOI substrate (**b**) high frequency parameters for AlGaN/GaN MISHEMT on SOI substrate(blue) and AlGaN/GaN MISHEMT on HR-Si substrate (red). [185].

#### **4. GaN HEMTs on QST Substrates**

Recently, a new engineered substrate consists of polycrystalline core and single crystalline surface layer, which exhibits a good thermal expansion and crystalline match to GaN, are presented. It provides a good matching in coefficient of thermal expansion (CTE) characteristics with Gallium Nitride (GaN). The template enables growth of thick and high quality GaN semiconductor layers on 8- and even 12-inch wafers and support a lower cost for GaN devices in power supplies and RF transmitters commercial markets. According to Qromis Inc., Qromis Substrate Technology (QST) promises a thicker GaN epitaxy to expands the GaN HEMT's limitation in breakdown voltage roadmaps (up to 1200 V) in power devices in vertical electron paths. Compatible with conventional GaN growth platforms, as the substrates are thermally matched to GaN, it offers low defect density, high crystal quality, and low wafer bow. As previous sections described, the high quality GaN power devices enabled are potential for a higher switching speed, simpler and smaller form, and higher-temperature operation.

The Naval Research Laboratory (NRL), Kyma and Qromis Technology reported some material characterization studies. It's interesting that GaN device layers up to 15µm were demonstrated with a wafer bow of 1 µm for growth on 150-mm-diameter substrates [186]. The development to manufacture 200 mm freestanding GaN from 300 mm QST® [187] also looks promising. According to several reports, the thermal conductivity and CTE relationship for different substrates are depicted in Figure 22. It also shows a high quality AlGaN/GaN buffers grown on substrates with a less mismatch in coefficient of thermal expansion (CTE). Figure 23 shows an illustration of evaluating the vertical buffer leakage currents in both reverse and forward bias mode, and it exhibits a maximum of reverse current of 1 µA/mm at 25 ◦C and 10 µA/mm at 150 ◦C as the reverse voltage exceeds 700 V. The leakage current increases by ~3 orders from 25 to 150 ◦C [188]. According to a MIT group, a GaN vertical power FinFETs on engineered substrate was demonstrated [189]. Figure 24 shows the schematic of the quasi-vertical device architecture, which consists of 132 fins with 100 nm, 700 nm and 21 um widths, spacing and length respectively. It exhibits a current density of JDS=3.8 kA/cm2 at VGS= 1.5 V and VDS= 4 V, and a maximum gm = 2 kS/cm2 at VDS = 4 V. The current density in each fin is higher than 30 kA/cm2 at the same bias condition. They also benchmark vertical and quasi-vertical MOSFETs on non-GaN substrates, as shown in Figure 25.

**Figure 22.** Different substrate for coefficient of thermal expansion (CTE) and thermal conductivity [188].

**Figure 23.** (**a**) The illustration of vertical buffer leakage measurements (**b**) The leakage current density under voltage bias for a 5.6 mm-thick buffer grown on 200 mm GaN-on-QST® substrate [188].

**Figure 24.** A schematic diagram of the vertical GaN FinFET devices and fabrication steps [189].

**Figure 25.** Benchmarking maximum current density in vertical GaN-on-Silicon transistors as a function of equivalent oxide thickness [189].

#### **5. Heterogeneous Integration of GaN HEMT**

The conventional silicon-based RF devices fabricated on 32 nm Si complementary metal-oxide-semiconductor (CMOS) with a cut-off frequency of 445 GHz were exhibited and the cut-off frequency are expected to further scale [190]. However, despite having impressive cut-off frequency, Si CMOS is not well suited with high voltage or high-power density due to lower breakdown voltage whereas GaN devices are more suitable for these types of applications. Hence, co-integrating Si with GaN on a single chip may help in achieving high power and high-performance application. The main motivation for integrating GaN and CMOS is due to the superior GaN performance in fast power switching and the high functionality of CMOS logic, reduction in interconnect distance as well as losses, smaller form factor, reduction in power consumption, lower cost, and lower assembling complexity [191,192]. There are two types of GaN and CMOS integration variants on wafer-level namely Monolithic Integration and Heterogeneous Integration (HI). In the past few years, the key technology development and production is heterogeneous integration. For high-frequency applications in space and defense and the 5G application in the commercial world, heterogeneous integration for RF has become an essential task. Typically, hetero-integration of RF devices is done with different semiconductor materials not only CMOS to address the required specific performance like Diverse Accessible Heterogeneous Integration (DAHI) technology [193]. HI methods can be wafer to wafer (WTW), chip to wafer (CTW), or Chip to Chip (CTC), etc [194]. CTW and CTC are usually used for integrating dissimilar heterogeneous materials as it minimizes coefficient of Thermal Expansion (CTE) as well as wafer warpage issues which enable known good die (KGD) and pretty good die (PGD) that helps in achieving good yield. In WTW integration, CTE issues are challenging, and the yield is compromised. High frequency 3D HI faces challenges such as implementing effective 3D screening method as in some cases chiplets don't have test pads and there is insufficient availability of process design kit (PDK) with RF functionality, co-simulation capability, and 3D parasitic extraction [194]. One heterogeneous integration method that makes the GaN power system compatible with CMOS fabrication using SOI substrate was stated by the IBM research division [195] as shown in Figure 26.

**Figure 26.** (**a**) Heterogeneous integration of SOI substrate with top Si (100) and bottom Si (111) and GaN epitaxial (**b**) SEM cross-section [195].

A DC-DC boost converter was designed using GaN power transistors integrated with bipolar-CMOS-DMOS (BCD) which combines both the advantages of high-voltage low-loss GaN devices and high-integration BCD circuits [196]. The designed GaN2BCD technology is a promising power converter application platform. Deeply scaled E/D-mode GaN HEMTs integrated with monolithically integrable GaN Schottky diodes were able to offer advantages in MMIC applications [142]. GaN-on-Si monolithic microwave integrated circuits (MMICs) were fabricated on 200-mm-diameter using a fully CMOS-compatible fabrication process which enables integration of wafer-level 3D GaN MMICs with Si CMOS circuits for performance and functionality enhancement while the size, weight, power, and cost is reduced [197]. As shown in Figure 27, a team from Raytheon [198] in the United States successfully demonstrated fabricating GaN HEMTs in windows on SOI wafers containing Si CMOS transistors, with DC and RF performance comparable to GaN HEMTs on SiC substrate, as well as a first GaN–Si CMOS heterogeneously integrated MMIC: GaN amplifier with CMOS gate bias control circuitry (a current mirror) and heterogeneous interconnects, as shown in Figure 28.

**Figure 27.** GaN HEMT and Si CMOS are heterogeneously combined on a modified SOI wafer [198].

**Figure 28.** GaN–Si CMOS heterogeneously integrated MMIC [198].

For heterogeneous integration, wafer bonding is one of the most promising integration approach for integrating group III-V materials and CMOS on Si [191]. Monolithic structure can be done by direct wafer bonding [199] or heteroepitaxy [200]. Direct wafer bonding can be used for integrating non-lattice matched semiconductors and also for integrating different crystal structures. Moreover, no additional intermediate layers are required and can also integrate two or more wafers. However, it requires a very flat, smooth, and particle-free surface along with fitting wafer diameter and chip sizes.

A new 3D integrated circuit (3DIC) solution, System on Integrated Chips (SoICTM), was developed by Taiwan Semiconductor Manufacturing Company (TSMC) [201] to integrate active and passive chips into a new integrated SoC system. Comparing the typical 3DIC stacking with SoIC, the latter offers higher I/O density bonding density, lower energy consumption/ bit data, lower electrical parasites, and lower thermal resistance [190] which might help in unleashing the boundary of IC designer on heterogeneous integrations in future 5G, AI, mobile, and HPC applications. IMEC developed NaNO-TSV (Through Silicon Vias) connection for heterogeneous integration as 3D system-on-chip (3D-SoC) integration technology which possess a wafer-to-wafer bonding approach combined with via-last TSV connection [202]. Finally, Wafer-level packaging (WLP) of the heterogeneous integrated devices is required to be protected from the environment [203]. WLP also eliminates assembly equipment, reduces package cost, and minimizes the chip size as well as provides high yield and high reliability.

#### **6. Conclusions**

In the previous GaN HEMTs development roadmap, the heterogeneous epitaxy has been one of the issues affecting devices performance. The wide application of compound semiconductors has attracted wide attention and become matured gradually, including and ranging from RF power amplifiers to electronic systems. The demand tendency for power devices is increasing, especially in electric vehicles and the fast-charging applications. As high-frequency communications keep developing, the GaN HEMT technology will be very critical. Traditional silicon substrates will no longer be only GaN HEMTs template but will be replaced by other smooth and friendly substrate for some applications. These advanced substrate technologies efficiently improve device characteristics, performance, and reliability. It will bring thicker GaN buffer layer, high thermal conductivity, and high resistance substrate in the future high-power high-frequency components. In addition, the heterogeneous integration of GaN HEMTs and CMOS structure have become a new direction. In this article, we provide a brief and comprehensive overview of these important technology developments.

**Author Contributions:** Data curation, Y.-Y.L., C.L., Y.-T.C., Y.-W.H., P.-T.T. and L.-H.H.; project administration, Y.-Y.L., W.-C.L., A.-J.T. and L.-H.H.; supervision, Y.-J.C., C.-H.L., H.-C.K. and E.Y.C.; writing—original draft, Y.-Y.L., C.L., Y.-T.C., P.-T.T. and L.-H.H.; writing—review and editing, L.-H.H. and Y.-Y.L. All authors have read and agreed to the published version of the manuscript.

**Funding:** Ministry of Science and Technology, Taiwan (107-2221-E-009-113-MY3, 108-2221-E-009-113- MY3, 109-2222-E-009-001-MY3, 110-2218-E-182-001-MY3).

**Acknowledgments:** The authors would like to thank Ministry of Science and Technology, Industrial Technology Research Institute, Taiwan Semiconductor Research Institute, and the Semiconductor Research Center, Hon Hai Research Institute, for the helpful discussion.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

## *Article* **Design and Implementation of a SiC-Based VRFB Power Conditioning System**

#### **Chao-Tsung Ma \* and Yi-Hung Tian**

Department of Electrical Engineering, CEECS, National United University, Miaoli 36063, Taiwan<EMAIL_ADDRESS>
**\*** Correspondence<EMAIL_ADDRESS>Tel.: +886-37-382-482; Fax: +886-37-382-488

Received: 21 November 2020; Accepted: 11 December 2020; Published: 12 December 2020

**Abstract:** An energy storage system using secondary batteries combined with advanced power control schemes is considered the key technology for the sustainable development of renewable energy-based power generation and smart micro-grids. The performance of energy storage systems in practical application mainly depends on their power conditioning systems. This paper proposes a silicon carbide-based multifunctional power conditioning system for the vanadium redox flow battery. The proposed system is a two-stage circuit topology, including a three-phase grid-tie inverter that can perform four-quadrant control of active and reactive power and a bi-directional multi-channel direct current converter that is responsible for the fast charging and discharging control of the battery. To achieve the design objectives, i.e., high reliability, high efficiency, and high operational flexibility, silicon carbide-based switching devices, and advanced digital control schemes are used in the construction of a power conditioning system for the vanadium redox flow battery. This paper first describes the proposed system topologies and controller configurations and the design methods of controllers for each converter in detail, and then results from both simulation analyses and experimental tests on a 5 kVA hardware prototype are presented to verify the feasibility and effectiveness of the proposed system and the designed controllers.

**Keywords:** energy storage system; power conditioning system; silicon carbide; vanadium redox flow batteries

#### **1. Introduction**

In recent years, the development of secure, low-carbon, and renewable energy sources and various smart micro-grid systems [1], power converter-based system compensating devices [2,3], advanced power converters using state-of-the-art wide-bandgap (WBG) switching devices, and digital-integrated intelligent control schemes [4,5] have become very popular research topics in the field of electric power and energy engineering. To best facilitate the above-mentioned technologies, various types of power converters are normally required [6–11], whose main components are semiconductor power switches and various system control units. To further enhance and optimize the performance of power converters, advanced semiconductor switches based on WBG materials, also known as third-generation semiconductor materials, such as gallium nitride (GaN) and silicon carbide (SiC), are emerging as very promising solutions [12,13]. It is well known that WBG materials offer superior characteristics over silicon in terms of band gap, electron mobility, electric breakdown field, saturated electron velocity, and thermal conductivity, which make WBG devices much desired for switching applications with high-voltage, -power, -temperature, and -frequency requirements. In particular, SiC devices with high-frequency switching capability and superior thermal conductivity are suitable for high-voltage and -power applications, while GaN has the highest bandgap, electron mobility, electric breakdown field, and saturated electron velocity, normally used in low- to mid-power systems [14]. In [15],

the performance of a digitally controlled 2 kVA three-phase shunt-active power filter using GaN high electron mobility transistors was demonstrated for the first time. In addition, since decarbonization and green energy are two of the modern trends, renewable energy-based distributed power generation and on-line energy management systems have been intensively researched over the past decade. How to improve the performance and optimize the application of grid-level energy storage systems (ESSs) has also become one of the necessary technologies to promote the sustainable development of renewable power generation, active power distribution systems, and micro-grids. At present, practical electric energy storage technologies include pumped hydro system, compressed air energy storage, battery energy storage systems (BESS), flow battery, superconducting magnetic energy storage, flywheel, supercapacitor, etc. [16,17]. Among the above-mentioned grid-level ESSs, the vanadium redox flow battery (VRFB) has the advantages of independent and flexible design of output power and energy storage capacity, high energy conversion efficiency, safety, and low maintenance costs, which make it very suitable for a wide range of applications, such as distributed power generation optimization, energy management and integrated power quality control technology related applications [18,19]. In general, the performance of ESSs in practical application mainly depends on their power conditioning systems (PCS). The PCS topology required by the general grid-connected BESS can be divided into two categories: single-stage [20–23] and two-stage [24–27] according to the circuit architecture. The single-stage system is more suitable for high-voltage, high-capacity battery packs, while the two-stage circuit architecture usually includes a single-phase or three-phase direct current to alternative current (DC/AC) converter and a bi-directional direct current to direct current (DC/DC) power converter for matching with a wider range of battery pack voltage specifications, and enabling the realization of different charging and discharging strategies. In fact, various battery-based ESSs have been developed for a long time; however, most BESSs reported in the literature are based on some specific operation and control functions required by the system concerned and the system operating functions in this kind of BESS are quite limited and cannot be universal leading a very high system cost, long payback period, and serious lack of application flexibility. To improve the above-mentioned shortcomings and to achieve an advanced and versatile ESS, this paper proposes a SiC-based multifunctional PCS for the VRFB.

#### **2. The VRFB System and the Proposed PCS Topology**

The system architecture of a VRFB is shown in Figure 1. The two electrolytes, positive (V4+/V 5+) and negative (V2+/V 3+) electrolytes, in a VRFB are stored in different electrolyte storage tanks. During charging or discharging, the two electrolytes are separated by an isolation membrane, but selected ions are allowed to pass through the membrane forming a current path. The concentration and amount of electrolyte determine the system capacity of VRFB, the design specifications of electrodes determine the rated power of VRFB, and the number of single cells in series in the battery stack determines the maximum working voltage of VRFB. It is important to note that to achieve a cost-effective and high-efficiency design, the number of cells in series cannot be too high. This has resulted in a preferable lower system voltage. Considering this condition, a two-stage circuit topology is proposed for the VRFB PCS in this paper. In operation, both the DC/AC power converter and the interleaved multi-channel DC/DC converter are activated at the same time according to the due operating mode and system conditions. The detailed circuit architecture of the VRFB PCS proposed in this paper is shown in Figure 2, where the main function of the interleaved buck-boost converter, consisting of six SiC power semiconductor switches and inductors *Lb* , is fast charging/discharging current command tracking. *Lb* is used to filter out ripple components in the current caused by the switching of the semiconductor switch. As can be seen in Figure 2, the architecture consists of three parallel synchronous buck-boost converters, where the output switching signal of each converter is 120 degrees apart from another, offsetting each other's ripples and reducing total output ripple. The left side of Figure 2 shows the grid-tied 3-phase inverter, whose main functions are DC bus voltage regulation via active power balancing control and system reactive power compensation via bi-directional reactive power tracking control. To provide a

clear picture of the above-mentioned control functions, Figure 3 shows the possible active and reactive power flows in the proposed VRFB PCS.

**Figure 1.** The system architecture of a vanadium redox flow battery (VRFB) [19].

**Figure 2.** VRFB power conditioning system (PCS) circuit topology.

**Figure 3.** Possible active and reactive power flows in the proposed VRFB PCS.

#### **3. Controller Design of VRFB PCS**

The relevant system parameters and hardware specifications of the proposed VRFB PCS are shown in Table 1. Following in this section, the required mathematical model derivation and controller design will be carried out according to the specifications given in Table 1.

**Table 1.** Specifications of the proposed system.

#### *3.1. Grid-Tie Inverter Modeling and Design of Controllers*

To achieve a reliable control scheme, the grid-tie inverter adopts a dual-loop control architecture, where the inner loop controls inductor currents, and the outer loop controls DC bus voltage and AC-side reactive power. The overall control architecture is shown in Figure 4.

**Figure 4.** Overall control architecture of grid-tie inverter (\* indicates commands).

#### 3.1.1. Design of Inductor Current Controllers

The mathematical model of inverter's inductor current in synchronous reference frame can be derived according to Figure 3: \_ \_ \_ 1 0 0 1 0 0

0 1 0

$$
\begin{bmatrix} L\_{\mathcal{S}} \frac{dI\_{o,d}}{dt} \\ L\_{\mathcal{S}} \frac{dI\_{o,q}}{dt} \\ L\_{\mathcal{S}} \frac{dI\_{o,0}}{dt} \end{bmatrix} = K\_{\text{pwm}} \begin{bmatrix} 1 & 0 & 0 \\ 0 & 1 & 0 \\ 0 & 0 & 1 \end{bmatrix} \begin{bmatrix} v\_{cond} \\ v\_{conq} \\ v\_{con0} \end{bmatrix} - \begin{bmatrix} 1 & 0 & 0 \\ 0 & 1 & 0 \\ 0 & 0 & 1 \end{bmatrix} \begin{bmatrix} V\_{\mathcal{S},d} \\ V\_{\mathcal{S},q} \\ V\_{\mathcal{S},0} \end{bmatrix} - \tag{1}
$$
  $\begin{bmatrix} 0 & \omega L\_{\mathcal{S}} & 0 \\ -\omega L\_{\mathcal{S}} & 0 & 0 \\ 0 & 0 & 0 \end{bmatrix} \begin{bmatrix} I\_{o,d} \\ I\_{o,q} \\ I\_{o,0} \end{bmatrix}$

0 1 0

\_

In this paper, the Type II controller is used to control the inductor currents. Using (1) and the mathematical form of Type II controller, dq-axis inner inductor current control loops can be obtained, as shown in Figure 5.

**Figure 5.** Inner inductor current control loops (\* indicates commands): (**a**) d-axis; (**b**) q-axis.

*ω* The quantification design of the inner loop inductor current controller is as follows: choosing the crossover frequency ω*i* = 41,888 rad/s; zero = 8377.5 rad/s and pole = 136,282.2 rad/s, yielding the required Type II controller as follows:

$$G\_{l}(s) = \frac{3.953 \times 10^{5} (s + 8377.5)}{s(s + 1.363 \times 10^{5})} \tag{2}$$

Figure 6 shows the Bode plot of inner inductor current control loop. The phase margin is 62◦ .

**Figure 6.** Bode plot of inner inductor current control loop.

Frequency (rad/s)

#### 3.1.2. Design of the DC Bus Voltage Controller

*ω*

*ω*

*ω*

Considering the steady-state operating point, the equivalent circuit of the DC bus voltage loop is as shown in Figure 7.

**Figure 7.** Equivalent circuit of direct current (DC) bus voltage loop.

The mathematical model of DC bus voltage can be derived according to Figure 7:

\_

$$\frac{V\_{\text{bus}}}{I\_{o,\emptyset}} = \frac{-k\_{dc}}{s\mathcal{C}\_{dc}}, k\_{dc} = 1.5 \frac{V\_{\mathcal{S},\emptyset}}{V\_{\text{bus}}} \tag{3}$$

In this paper, the Type II controller is used to control the DC bus voltage, and thus outer DC bus voltage control loop can be obtained, as shown in Figure 8.

**Figure 8.** Outer DC bus voltage control loop (\* indicates commands).

The quantification design of the DC bus voltage controller is as follows: choosing the crossover frequency ω*v* = 5235.9877 rad/s; zero = 523.598 rad/s; pole = 68,141.144 rad/s, yielding the required Type II controller as follows: 071.1 (10 .523 3426) 7 7

$$G\_{\upsilon}(s) = \frac{1.071 \times 10^7 (s + 523.3426)}{s(s + 6.814 \times 10^4)}\tag{4}$$

Figure 9 shows the Bode plot of outer DC bus voltage control loop. The phase margin is 80◦ .

**Figure 9.** Bode plot of outer DC bus voltage control loop.

#### 3.1.3. Design of Reactive Power Controller

The derivation of the AC-side reactive power controller in this paper takes the grid-side current flowing into the converter as positive:

$$Q\_{\mathcal{S}} = -1.5 \times V\_{\mathcal{S}\angle\emptyset} \times I\_{o\\_d} \tag{5}$$

In this case, the Type II controller is used to control the reactive power, and thus outer reactive power control loop can be obtained, as shown in Figure 10.

**Figure 10.** Outer reactive power control loop (\* indicates commands).

*ω ω* The quantification design of the reactive power controller is as follows: choosing the crossover frequency ω*q* = 3490.6585 rad/s; zero = 1745.329 rad/s; pole = 6981.317 rad/s, yielding the required Type II controller as follows:

$$G\_v(s) = \frac{8359(s + 1745.4241)}{s(s + 6981)}\tag{6}$$

Figure 11 shows the Bode plot of outer reactive power control loop. The phase margin is 127◦ .

**Figure 11.** Bode plot of outer reactive power control loop.

#### *3.2. Interleaved Buck-Boost Converter Controllers*

The interleaved buck-boost converter adopts a single-loop inductor current controller, and each channel is individually controlled and uses a different phase shift angle. The overall control architecture is shown in Figure 12.

**Figure 12.** Overall control architecture of interleaved buck-boost converter (\* indicates commands).

#### Design of Inductor Current Controller

The proposed interleaved buck-boost converter is composed of multiple buck-boost converters, and its operating principle is the same as that of a single buck-boost converter. Therefore, only the controller design of a single buck-boost converter is illustrated. Taking leg A as an example, the mathematical model of the inductor current is as follows:

$$L\_{b1}\frac{di\_{Lb1}}{dt} = v\_{con1}K\_{pwm} - V\_{b\nu}K\_{pwm} = \frac{V\_{bus}}{v\_{tri}}\tag{7}$$

*ω*

In this control case, the Type II controller is again used to control the inductor current, and thus inductor current control loop can be obtained, as shown in Figure 13.

1

1

1

1

1

1

,

,

**Figure 13.** Buck-boost converter inductor current control loop (\* indicates command).

According to Figure 13, the transfer function of inductor current loop is as follows: 1 )(

1

$$H\_{l1}(s) = K\_{pvm} \times \frac{1}{sL\_b} \times k\_s \tag{8}$$

*ω* The quantification design of the inductor current controller is as follows: choosing the crossover frequency ω*i* = 39,270 rad/s; zero = 5167.1 rad/s; pole = 298,280 rad/s, yielding the required Type II controller as follows: .1 122 10 ( 5167 )1. )( 5 6

$$G\_i(s) = \frac{1.122 \times 10^6 (s + 5167.1)}{s(s + 2.9828 \times 10^5)}\tag{9}$$

Figure 14 shows the Bode plot of the designed inductor current control loop. The phase margin is 75◦ .

Frequency (rad/s) **Figure 14.** Bode plot of buck-boost converter inductor current control loop.

#### **4. Cases Simulation**

#### *4.1. Ramp-Up Procedure*

To verify the correctness of the designed PCS controllers presented in the previous section, a software model of the proposed VRFB PCS is developed with power simulation software as shown in Figure 15. Two typical simulation cases, the ramp-up procedure and charging/discharging with four-quadrant P-Q control of the grid-tie inverter, are carried out in this study. Figure 16 shows the result of simulating ramp-up procedure of the system. This is to verify that the designed PCS can

securely establish the required DC bus voltage of 400 V. As can be seen in Figure 16, after the grid-tie converter confirms the status of synchronization with the grid, the circuit starts to charge the DC bus capacitor slowly, and the rated DC bus voltage of PCS is boosted from 360 V and finally controlled at the target value of 400 V to complete the preparation of the system for various functional operations.

**Figure 15.** The power simulation software model of the proposed VRFB PCS.

**Figure 16.** Waveforms of DC bus voltage (**top**), grid three-phase voltages and a-phase current (**mid**), grid a-phase voltage and three-phase currents (**bottom**).

#### *4.2. Charging*/*Discharging with P-Q Four-Quadrant Control of the Grid-Tie Inverter*

This case verifies simultaneous operation of the charging/discharging of VRFB and the function of reactive power regulation. In this operation mode, the charging/discharging current of the VRFB respectively corresponds to the positive and negative active power of the grid-tied inverter. With the independent control function of positive and negative reactive power regulation, a four-quadrant P-Q control is achieved by the grid-tied inverter. In this simulation case, the battery voltage = 150 V, a charging and discharging current command of ±30 A (equivalent to ±4.5 kW) and a ±2 kVAR reactive power command is arranged. Figure 17 shows the schematic diagram of PCS operating in the 1st and 3rd quadrants. Figures 18–22 show a set of complete simulation results. As shown in Figure 18a, the three interleaved inductor currents are regulated evenly while the DC bus voltage is stably controlled at its rated value of 400 V. It can be clearly seen from Figures 19 and 20, with the proposed direct current control scheme, the cross interference between active and reactive power of the grid-tied inverter is negligible. Figures 21 and 22 show the tracking performance of the designed reactive power, charging and discharging controllers. –

**Figure 17.** The schematic diagram of PCS operating in the 1st and 3rd quadrants.

**Figure 18.** Waveforms of (**a**) interleaved buck-boost converter: DC bus voltage (**top**), interleaved inductor currents (**mid**), battery current (**bottom**) and (**b**) grid-tied inverter: DC bus voltage (**top**), grid three-phase voltages and a-phase current (**mid**), grid a-phase voltage and three-phase currents (**bottom**).

**Figure 19.** The detailed view of Figure 18b: (**a**) near t1; (**b**) near t2.

**Figure 20.** The detailed view of Figure 18b: (**a**) near t5; (**b**) near t6.

**Figure 21.** Waveforms of control commands and feedbacks: (**a**) three interleaved inductor currents; (**b**) reactive power (top), DC bus voltage (bottom).

**Figure 22.** Waveforms of control commands and feedbacks: qd-axis inductor currents.

With the same operating condition as described previously, Figure 23 depicts a schematic diagram of PCS operating in the 2nd and 4th P-Q quadrants. Figures 24–28 show a set of complete simulation results. In this case, with the same charging/discharging command, the current waveforms of interleaved buck-boost converter are identical to those shown in Figure 18a, so they are not shown in this case. As shown in Figure 24, during the charging and discharging operation of the battery the DC bus voltage is stably controlled at its rated value of 400 V with the designed voltage controller. It can be clearly seen from Figures 25 and 26, with the proposed control scheme, the cross interference between active and reactive power of the grid-tied inverter is negligible. Figures 27 and 28 verify the tracking performance of the designed reactive power, charging and discharging controllers working at different operating points. –

**Figure 23.** PCS operating in the 2nd and 4th quadrants.

**Figure 24.** Waveforms of DC bus voltage (**top**), grid three-phase voltages and a-phase current (**mid**), grid a-phase voltage and three-phase currents (**bottom**).

**Figure 25.** The detailed view of Figure 23: (**a**) near t1; (**b**) near t2.

**Figure 26.** The detailed view of Figure 23: (**a**) near t5; (**b**) near t6.

**Figure 27.** Waveforms of control commands and feedbacks: (**a**) three interleaved inductor currents; (**b**) reactive power (**top**), DC bus voltage (**bottom**).

**Figure 28.** Waveforms of control commands and feedbacks: qd-axis inductor currents.

#### **5. Hardware Implementation and Test Results**

To further verify the performance of the proposed VRFB PCS, a 5 kVA hardware experimental platform using SiC MOSFET is built according to the system specifications listed in Table 1 and the operating scenarios of the test cases are identical to that used in the simulated cases presented in the previous section. Figure 29 shows a photo of the constructed SiC-based VRFB PCS hardware system and the experimental platform, including (1) auxiliary power, (2) oscilloscope, (3) SiC-based grid-tie three-phase inverter, (4) SiC-based interleaved DC-DC buck-boost converter, (5) current probe, and (6) voltage probes. Figure 30 shows the test result of ramp-up procedure of the PCS hardware system. Figures 31–34 show a set of experimental results of the proposed PCS operating in the 1st and 3rd quadrants. As can be seen in Figures 31–34, the measured waveforms are very close to those obtained from simulation studies presented in the previous section. This has verified the feasibility and effectiveness of the proposed control schemes.

**Figure 29.** Photo of the constructed VRFB PCS hardware and the experimental platform.

**Figure 30.** Waveforms of DC bus voltage (Vbus), phase-a grid voltage (Vg\_a) and a-phase grid current (ig\_a).

**Figure 31.** Waveforms of (**a**) interleaved buck-boost converter: DC bus voltage, interleaved inductor currents, and battery current, (**b**) DC bus voltage and the grid phase-a voltage and current.

**Figure 32.** Detailed view of Figure 31b: (**a**) near t1; (**b**) near t2; (**c**) near t5; (**d**) near t6.

**Figure 33.** Waveforms of grid phase-a voltage and three-phase currents.

**Figure 34.** Detailed view of Figure 33: (**a**) near t1; (**b**) near t2; (**c**) near t5; (**d**) near t6.

– – To fully verify the performance of the proposed SiC-based hardware system and control scheme, Figure 35 show a second set of experimental results, in which the proposed PCS is operating in the 2nd and 4th quadrants. As can be seen in Figures 35–37, satisfactory performances of the proposed PCS grid-tied inverter and the interleaved buck-boost converter are achieved. –

**Figure 35.** Waveforms of (**a**) DC bus and grid phase-a voltage and current; (**b**) three-phase currents. **Figure 35.** Waveforms of (**a**) DC bus and grid phase-a voltage and current; (**b**) three-phase currents.

**Figure 36.** Detailed view of Figure 35a: (**a**) near t1; (**b**) near t2; (**c**) near t5; (**d**) near t6.

**Figure 37.** Detailed view of Figure 35b: (**a**) near t1; (**b**) near t2; (**c**) near t5; (**d**) near t6.

The efficiency test results of the proposed 5 kVA, SiC-based PCS's grid-connected three-phase inverter and the 5 kW, 3-channel interleaved buck-boost converter are shown in Figure 38a,b respectively. The highest efficiency of the grid-tied three-phase inverter and 3-channel interleaved buck-boost

**Figure 38.** The efficiency analysis of the PCS: (**a**) grid-tied inverter, (**b**) interleaved buck-boost converter.

#### **6. Conclusions**

It has been well accepted that the economic benefits of distributed power generation and micro-grids are multifaceted. For power users, the economic benefits lie in efficient use of energy, environmental protection, and reliable customized electrical energy services, while optimizing resource allocation and providing highly efficient energy management with operational flexibility are the main factors for achieving the economic benefits of micro-grids. However, with the addition of renewable power generations and various types of micro-grids in the power systems the complexity in system control and operation is significantly increased and certain compensating devices, e.g., ESSs integrated with advanced PCSs are urgently needed to be proposed and verified for feasibility. In this regard, this paper has proposed a SiC-based multifunctional PCS for the VRFB. In this study, it has been found that SiC switching devices with their excellent thermal and voltage capability can meet the requirement of a cost-effective design of grid-tied inverter system, in which the pulse width modulation technique can be used to reduce the hardware cost of PCS while improving system reliability. In this paper, the consideration of circuit topology and the detailed design steps of related controllers of the proposed SiC-based VRFB PCS have been fully addressed. The highest efficiency of the constructed SiC-based grid-tied three-phase inverter and 3-channel interleaved buck-boost converter system is measured to be 94.1% and 96.3% respectively. With the proposed PCS control schemes, four-quadrant control of active and reactive power and fast charging and discharging control of the VRFB have been achieved. Both simulation studies and experimental tests on a 5 kVA hardware prototype have verified the feasibility and overall performance of the proposed SiC-based VEFB PCS. It is worth noting that with the decoupled active and reactive power control capability and fast current command tracking feature the proposed VRFB PCS is expected to perform multiple system compensating functions, e.g., real-time support for renewable power generation, voltage and frequency support for micro-grids, and power quality improvement for power distribution systems.

**Author Contributions:** The corresponding author, C.-T.M. conducted the research work, proposed the VRFB PCS concept and design methods, verified the results, wrote the manuscript draft and polished the final manuscript. Y.-H.T. a postgraduate student in the department of EE, CEECS, National United University, Taiwan assisted hardware tests and organized results. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by MOST, Taiwan, with the grant number, MOST 109-3116-F-006-020-CC1.

**Acknowledgments:** The author would like to thank the Ministry of Science and Technology (MOST) of Taiwan for financially support the energy-related research regarding key technologies in micro-grids and the design of advanced power and energy systems.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

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## *Review* **Review on Driving Circuits for Wide-Bandgap Semiconductor Switching Devices for Mid- to High-Power Applications**

**Chao-Tsung Ma \* and Zhen-Huang Gu**

Department of Electrical Engineering, CEECS, National United University, Miaoli 36063, Taiwan<EMAIL_ADDRESS>
**\*** Correspondence<EMAIL_ADDRESS>Tel.: +886-37-382-482; Fax: +886-37-382-488

**Abstract:** Wide-bandgap (WBG) material-based switching devices such as gallium nitride (GaN) high electron mobility transistors (HEMTs) and silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) are considered very promising candidates for replacing conventional silicon (Si) MOSFETs for various advanced power conversion applications, mainly because of their capabilities of higher switching frequencies with less switching and conduction losses. However, to make the most of their advantages, it is crucial to understand the intrinsic differences between WBG- and Si-based switching devices and investigate effective means to safely, efficiently, and reliably utilize the WBG devices. This paper aims to provide engineers in the power engineering field a comprehensive understanding of WBG switching devices' driving requirements, especially for mid- to high-power applications. First, the characteristics and operating principles of WBG switching devices and their commercial products within specific voltage ranges are explored. Next, considerations regarding the design of driving circuits for WBG switching devices are addressed, and commercial drivers designed for WBG switching devices are explored. Lastly, a review on typical papers concerning driving technologies for WBG switching devices in mid- to high-power applications is presented.

**Keywords:** wide-bandgap (WBG); gallium nitride (GaN); silicon carbide (SiC); high electron mobility transistor (HEMT); metal-oxide-semiconductor field effect transistor (MOSFET); driving technology

#### **1. Introduction**

In modern industries, requirements for the performance of various power electronicbased converters are becoming stricter in terms of capacity, voltage level, efficiency, and size (switching frequency related issues). In order to enhance the performance of existing power converters, replacing conventional Si switching devices with wide-bandgap (WBG) switching devices such as gallium nitride (GaN) high electron mobility transistors (HEMTs) and silicon carbide (SiC) metal-oxide-semiconductor field-effect transistors (MOSFETs) is currently a popularly adopted method. WBG semiconductor materials offer superior characteristics to those of Si, as shown in Figure 1. The respective merits of GaN and SiC lead to the advantageous adoption of GaN HEMTs for low (<1 kW) to mid (<10 kW) power applications and SiC MOSFETs for mid (<10 kW) to high (>10 kW) power applications in practical design scenarios. The superiority of GaN HEMTs is yet to be fully utilized because they feature some form of heterogeneous integration with dissimilar substrate. This leads to large thermal boundary resistance between GaN and substrate, causing the self-heat issue [1], which may cause the switching device to overheat. However, GaN HEMTs offer the highest efficiency and switching speed, and SiC MOSFETs provide the highest voltage, current, and temperature capabilities. The main challenge of using the WBG semiconductor switching devices is overcoming potential difficulties introduced from their high slew rates, which could worsen electromagnetic interference (EMI) level and may cause voltage oscillation and instability [2–7].

**Citation:** Ma, C.-T.; Gu, Z.-H. Review on Driving Circuits for Wide-Bandgap Semiconductor Switching Devices for Mid- to High-Power Applications. *Micromachines* **2021**, *12*, 65. https://doi.org/10.3390/mi12010065

Received: 25 December 2020 Accepted: 6 January 2021 Published: 8 January 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

**Figure 1.** Comparison of Si, gallium nitride (GaN), and silicon carbide (SiC).

The GaN HEMT is designed with a unique aluminum gallium nitride (AlGaN)/GaN heterojunction structure where two-dimensional electron gas (2DEG) is formed. The 2DEG allows large bidirectional current and yields extremely low on resistance. GaN HEMTs are currently divided into three types: depletion mode (D-mode), enhancement mode (E-mode), and cascode devices. The D-mode GaN HEMT, as shown in Figure 2, is naturally on because of the 2DEG and can be turned off with negative gate-source voltage. The E-mode GaN HEMT, as shown in Figure 3, is normally off because the 2DEG has been depleted by an additional P-doped layer of GaN or AlGaN on the gate, and it can be turned on with appropriate gate-source voltage. The cascode GaN HEMT, as shown in Figure 4, is also normally off because it consists of a D-mode GaN HEMT and an additional high-speed low-voltage Si MOSFET, and it can be turned on with appropriate gate-source voltage applied on the Si MOSFET. E-mode and cascode GaN HEMTs possess different characteristics mainly because of the additional Si MOSFET in the cascode device: the E-mode device offers lower on resistance, higher operating temperature, and no body diode, while the cascode device offers less strict driving requirements, as shown in Table 1 [4–7].

**Figure 2.** D-mode GaN high electron mobility transistors (HEMT).

**Figure 3.** E-mode GaN HEMT.

**Figure 4.** Cascode GaN HEMT.

**Table 1.** General comparison of normally off GaN high electron mobility transistors (HEMTs).

The SiC MOSFET has a similar structure to that of Si MOSFET, as shown in Figure 5, but the thickness can be made an order smaller because of SiC's higher voltage capability. This leads to much smaller on resistance (although not as small as that of the GaN HEMT). Additionally, the SiC MOSFET offers the highest power capability. The operation of the SiC MOSFET is the same as that of the Si MOSFET: with appropriate gate-source voltage, the device can be turned on, and the body diode is used for reverse conduction during off state [8,9]. A general comparison of Si MOSFET, normally off GaN HEMTs, and SiC MOSFET is shown in Table 2.

**Table 2.** General comparison of Si metal-oxide-semiconductor field-effect transistors (MOSFET), normally off GaN HEMTs, and SiC MOSFET.

**Figure 5.** Schematic diagrams of a SiC MOSFET, (**a**) basic structure, (**b**) the gate-source voltage and current path in on-state, (**c**) the gate-source voltage and current path in off-state.

In recent years, because of the high slew rate of the WBG semiconductor switching devices, the philosophy of replacing conventional Si devices with WBG devices is an ongoing research trend. This paper aims to review issues concerning the driving technologies of WBG semiconductor switching devices. First, a general introduction of the GaN HEMT and the SiC MOSFET is given in the first section. In the second section, a survey of commercial GaN HEMTs above 600 V and SiC MOSFETs between 600 and 1200 V is presented. In the third section, the challenges and solutions of driving GaN HEMTs and SiC MOSFETs are addressed. A survey of commercial drivers designed for WBG switching devices is then provided in the fourth section. The fifth and sixth sections cover the literature review on driving circuits for GaN HEMTs and SiC MOSFETs, respectively. Lastly, this paper is concluded in the seventh section.

#### **2. Commercial Wide-Bandgap (WBG) Switching Devices**

#### *2.1. Discrete Commercial GaN High Electron Mobility Transistors (HEMTs)*

According to two famous electronic device providers, Digi-Key [10] and Mouser [11], GaN HEMT products can be purchased from several manufacturers, including EPC (15~200 V) [12], Infineon Technologies (400 and 600 V) [13], GaN Systems (100 and 650 V) [14], Panasonic (600 and 650 V) [15], Nexperia (650 V) [16], and Transphorm (650 and 900 V) [17]. Currently, the two highest voltage ratings of commercial GaN HEMTs are 900 and 650 V, respectively. The 900 V GaN HEMTs are produced by Transphorm, and 650 V GaN HEMTs are produced by GaN Systems, Panasonic, Nexperia (formerly Standard Products business unit of NXP Semiconductors), and Transphorm. Table 3 presents the device specifications of commercial GaN HEMTs above 600 V, where MFR stands for manufacturer, *Vds* denotes drain-source voltage, *Ids* denotes drain-source current, *VTH* denotes threshold voltage, *Vgs* denotes gate-source voltage, *Rds(on)* denotes on resistance, and *Ciss* denotes input capacitance. Some specifications of the latest large-current devices from GaN Systems are not published. The maximum *Vgs* values of the products from Infineon Technologies and Panasonic are not specified because these devices are current-controlled, which offers good robustness but leads to higher gate losses.

#### **Table 3.** Commercial GaN HEMTs above 600 V.

#### *2.2. Discrete Commercial SiC Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs)*

Since SiC MOSFETs have been developed for a longer time, there is a much larger variety of companies that produce SiC MOSFETs: ON Semiconductor (900 and 1200 V) [18], Littelfuse (600~1700 V) [19], Infineon Technologies (650~1700 V) [13], Cree (650~1700 V) [20], Rohm Semiconductor (650~1700 V) [21], STMicroelectronics (650~1700 V) [22], United Silicon Carbide (650~1700 V) [23], Microchip (700~1700 V) [24], and GeneSiC Semiconductor (1200~3300 V) [25]. Tables 4–12 present the device specifications of commercial SiC MOS-FETs with voltages ratings between 600 and 1200 V. When comparing the listed commercial devices, we can see that it is common for SiC MOSFETs to possess much higher current capabilities than those of GaN HEMTs, which makes SiC devices more suitable for high-power

applications such as high-speed railway, power transmission, industrial drives, smart grid, and wind power generation. On the other hand, GaN devices offer smaller on resistances and input capacitances, which indicates that GaN devices have the potential to yield lower conduction losses and faster switching with such ratings. Therefore, GaN HEMTs are currently applied to improve the efficiencies of mid-voltage and mid-power applications such as switching power supply, solar PV, AC/DC adapter, medical equipment, electric vehicle (EV), and uninterruptible power supply. Figure 6 shows the application fields of Si, SiC, and GaN switching devices [13].

**Table 4.** Commercial 600~1200 V SiC MOSFETs by On Semiconductor.

**Table 5.** Commercial 600~1200 V SiC MOSFETs by Littelfuse.

**Table 6.** Commercial 600~1200 V SiC MOSFETs by Infineon Technologies.

#### **Table 7.** Commercial600~1200 V SiC MOSFETs by Cree.

#### **Table 7.** *Cont.*

**Table 8.** Commercial 600~1200 V SiC MOSFETs by Rohm Semiconductor.

**Table 9.** Commercial 600~1200 V SiC MOSFETs by STMicroelectronics.

**Table 9.** *Cont.*

**Table 10.** Commercial 600~1200 V SiC MOSFETs by United Silicon Carbide.

**Table 11.** Commercial 600~1200 V SiC MOSFETs by Microchip.

**Table 12.** Commercial 600~1200 V SiC MOSFETs by GeneSiC.

**Figure 6.** Applications fields of Si, SiC, and GaN switching devices [13].

#### *2.3. Modular WBG Switching Devices*

Some commercial switching modules based on GaN HEMTs can also be found from EPC [12], as numerated in Table 13, where HB stands for half bridge. EPC produces up to 3 kW modules. Consequently, these products are not yet matured for high-power applications.

**Table 13.** Commercial GaN HEMT modules by EPC.

Unlike GaN modules, there are several manufacturers with commercial SiC modules available for purchase: Infineon Technologies [13], Cree [20], Rohm Semiconductor [21], Microchip [24], Powerex [26], and SemiQ [27], as listed in Tables 14–19, where FB stands for full bridge. As can be imagined, the voltage and current ratings of SiC modules easily exceed those of GaN modules. Among SiC modules manufactured by the abovementioned companies, HB is the most common configuration. Particularly, the configuration of DF23MR12W1M1P\_B11, DF23MR12W1M1\_B11, DF11MR12W1M1P\_B11, and DF11MR12W1M1\_B11 by Infineon Technologies is presented in Figure 7. The suitable applications of them are specified as solar applications.

**Table 14.** Commercial SiC MOSFET modules by Infineon Technologies.

#### **Table 15.** Commercial SiC MOSFET modules by Cree.

**Table 16.** Commercial SiC MOSFET modules by Rohm Semiconductor.

#### **Table 17.** Commercial SiC MOSFET modules by Microchip.

#### **Table 18.** Commercial SiC MOSFET modules by Powerex.

**Table 19.** Commercial SiC MOSFET modules by SemiQ.

**Figure 7.** Configurations of Infineon Technologies SiC switching modules DF23MR12W1M1P\_B11, DF23MR12W1M1\_B11, DF11MR12W1M1P\_B11, and DF11MR12W1M1\_B11 [13].

#### **3. Considerations for the Design of Driving Circuits for WBG Switching Devices**

It has been well accepted that the key factor of realizing WBG switching devices' full potential is their driving circuits. The main difference in the driving characteristics of WBG and Si switching devices is due to WBG devices' much faster transient. The fast switching and high switching frequency require shorter driver rise and fall times and propagation delay. Additionally, the slew rate of the WBG devices can reach up to 100 times that of conventional Si devices, which can severely worsen EMI-related problems such as gate ringing and measurement. In order to deal with the fast transient, the driving circuit design and printed circuit board (PCB) layout must be optimized [28,29].

In general, the fundamental rules of driving high-power GaN HEMTs and SiC MOS-FETs are to apply high drive strength, provide enough isolation between driving and power circuits, prevent voltage oscillation, limit gate voltage spikes, and optimize dead time. Isolation can be provided by various types of isolators or isolated drivers suitable for WBG switching devices. In general, it is also possible to use high-speed MOSFET and IGBT drivers (similar to Figure 8) to drive WBG devices, but the complexity of the driving circuits and cost may be increased. However, another special characteristic of WBG switching devices is that they do not always use symmetrical driving voltages (such as ±18 and ±20 V), so there is often a need for asymmetric driving voltage design. Next, it is recommended to minimize the parasitic inductance and capacitance by minimizing the length of the driving loop and the overlapping between circuits and using devices with short or no wire bond [30–32]. In particular, GaN HEMTs (especially E-mode) have faster transients and more narrow driving voltage ranges, and SiC MOSFETs have higher power ratings. Consequently, the EMI issues are more dominant when driving GaN HEMTs, and higher driving strength is required when driving high-power SiC MOSFETs.

**Figure 8.** Conventional totem-pole gate driver.

For the turn-on period, the sum of external resistance and driver's output resistance should be designed to be much larger than the internal resistance of the power switching device in order to reduce the influence of internal resistance on the switching speed and damp voltage overshoot. If there is a need to damp gate ringing of certain frequencies, ferrite beads can be used as gate impedance as well. However, a low-impedance turn-off path is also required to ensure fast turn-offs and thus prevent shoot-through. As a result, it is usually recommended to design separate turn-on and turn-off paths, where drivers with separate high and low outputs can provide more flexibility, as shown in Figure 9. Moreover, active Miller clamps can be used to directly limit gate-source voltage range; negative turn-off voltage can increase the turn-off speed even more; and Kelvin source connection can separate the driving loop and power loop, so that the influence of parasitic inductance on the driving loop can be minimized, as shown in Figure 10 [31–33]. Particularly, active gate drive can be used to control the slew rate directly [34,35].

**Figure 9.** Gate driver with separate high and low outputs [31].

**Figure 10.** Driving loop with active Miller clamp, Kelvin source connection, and negative turn-off voltage [31].

#### **4. Commercial Drivers for WBG Switching Devices**

#### *4.1. GaN HEMT Drivers*

According to Digi-Key [10] and Mouser [11], commercial GaN HEMT drivers are currently available from several companies: Infineon Technologies [13], On Semiconductor [21], Maxim Integrated [36], pSemi [37], Silicon Laboratories [38], and Texas Instruments [39], as given in Tables 20–25. It is desirable to use drivers integrated with multiple functions such as digital control and signal detection in order to reduce the number of external devices required. Some companies also produce GaN power modules that integrate GaN

HEMTs with designed drivers: EPC [12], Texas Instruments [39], and Navitas Semiconductor [40], as presented in Tables 26–28.

**Table 22.** Commercial GaN HEMT drivers by Maxim Integrated.

**Table 23.** Commercial GaN HEMT drivers by pSemi.

**Table 24.** Commercial GaN HEMT drivers by Silicon Laboratories.

**Table 25.** Commercial GaN HEMT drivers by Texas Instruments.

**Table 26.** Commercial switch-driver-integrated module by EPC.

**Table 27.** Commercial switch-driver-integrated module by Texas Instruments.

**Table 28.** Commercial switch-driver-integrated module by Navitas Semiconductor.

#### *4.2. SiC MOSFET Drivers*

Since SiC devices have been developed for a longer time, a larger variety of SiC MOSFET drivers than that of GaN HEMT drivers have been developed by many manufacturers, including Infineon Technologies [13], On Semiconductor [21], Microchip [24],

Maxim Integrated [36], Silicon Laboratories [38], Texas Instruments [39], Analog Devices [41], Tamura [42], Rohm Semiconductor [21], Littelfuse [19], Diodes Incorporated [43], NXP Semiconductors [44], and Power Integrations [45], as listed in Tables 29–37. Because SiC MOSFETs are suitable for and often used in high-power applications, the peak output current ratings of SiC MOSFET drivers are generally larger than those of GaN HEMT drivers. Particularly, Tamura's drivers offer as large as 43 A peak driving current.

**Table 29.** Commercial SiC MOSFET drivers by Infineon Technologies.

**Table 30.** Commercial SiC MOSFET drivers by On Semiconductor.

**Table 31.** Commercial SiC MOSFET drivers by Microchip.

**Table 32.** Commercial SiC MOSFET drivers by Maxim Integrated.

**Table 33.** Commercial SiC MOSFET drivers by Silicon Laboratories.

#### **Table 34.** Commercial SiC MOSFET drivers by Texas Instruments.

**Table 35.** Commercial SiC MOSFET drivers by Analog Devices.

**Table 36.** Commercial SiC MOSFET drivers by Tamura.

**Table 37.** Commercial SiC MOSFET drivers by Rohm Semiconductor, Littelfuse, Diodes Incorporated, NXP Semiconductors, and Power Integrations.

#### **5. Review on GaN HEMT Driving Circuits**

*5.1. Single-Channel GaN HEMT Driving Circuits*

To provide readers with direct design references, typical papers presenting the design of GaN HEMT driving circuits are reviewed in this subsection with examples of singlechannel drive. Gurpinar and Castellazzi [46] conducted a benchmark of Si-, SiC-, and GaNbased switching devices at a 600 V class in 3.5 kW, 700 V/230 V, 16~160 kHz single-phase T-type inverter. Evaluated items included gate driver requirements, switching performance, inverter efficiency performance, heat sink volume, output filter volume, and dead-time effect for each technology. A Broadcom gate drive optocoupler ACPL-P346 was selected as the isolated driver for Panasonic PGA26A10DS, and an XP Power isolated DC/DC converter IH0512S-H was used to provide +12 V supply. The design offered small footprint, but the drive strength was limited at 3 A. The series capacitor Cs in the proposed driving circuit was designed at 2.82 nF in order to provide −4.5 V during turn-off and speed up turn-on transient. In [47], a low-inductance switching power cell was designed for a three-level ANPC inverter based on GaN System GS66508T. Texas Instruments UCC27511 provided separate turn-on and turn-off outputs. PWM signal was generated using a fiber optic link, and an inverting Schmitt trigger were used to transfer the PWM signal and avoid any false turn-on or turn-off. The signal was then isolated using Silicon Laboratories Si861x. A 7 V power supply was provided using an isolated DC/DC converter and a lowdropout (LDO) regulator. A Schottky diode was used for voltage clamp. The four-layer PCB and surface-mount components significantly reduced the loop inductance using flux cancellation, where the layout was required to eliminate common-mode current circulation. In [48], a 1.5 kW HB bidirectional DC/DC converter was proposed based on GaN System GS66508T driven by Silicon Laboratories Si8271 and −3~6 V driving voltage. A CUI isolated DC/DC converter PES1-S5-S9-M-TR was used to provide power supply. Fourlayer PCB layout was adopted in this paper, where flux cancellation was adopted in order to

minimize the loop inductance. Advanced Thermal Solutions heat sink ATS-FPX060060013- 112-C2-R1 was chosen to match the small thermal pad of GS66508T, and a copper bar was placed between the switching device and the heat sink for enhanced thermal performance.

A 3 kW bidirectional GaN-HEMT DC/DC converter was proposed in [49]. The selfdesigned driving circuit was designed with an additional NPN bipolar transistor that acted as a voltage clamp and showed no impact on the switching speed. Zero voltage turn-on and negative turn-off voltage were utilized to reach >99% efficiency. A fast GaN HEMT driving circuit was designed for Panasonic PGA26E19BA with a voltage clamped to achieve optimized switching performance, freewheeling conduction, and short-circuit robustness [50]. The manufacturer-recommended driving circuit design was modified by adding a diode-resistor network that helped the capacitor on the driving path quickly discharge as well as provided more flexibility in gate resistor design.

#### *5.2. Dual-Channel GaN HEMT Driving Circuits*

Dual-channel GaN HEMT driving circuits are generally more complex than singlechannel driving circuits. However, there are some commercial dual-channel GaN HEMT drivers ICs that greatly reduce the design complexity. Zhao et al. [51] designed a 2 kVA GaN-based single-phase inverter. The driving circuit for GaN System GS66508T consisted of Analog Devices ADuM7223 and separate turn-on and turn-off paths. The driver IC selection was limited in the writing of this paper (2016), so the selected driver failed to meet the common-mode transient immunity (CMTI) requirement of over 150 V/ns, but no failure occurred during testing. In [52], a 2 kW inductive power transfer system was designed based on a 600 V GaN gate injection transistor (GIT). The slew rate was lowered so that the Analog Devices ADuM3223, which had state of the art CMTI capability of 50 V/ns back in 2016, was compatible. In [53], a high-power density single-phase FB inverter was designed based on GaN Systems GS66502B. Silicon Laboratories Si8274 was used to drive the GaN HEMTs. Ways to minimize parasitic inductance and optimize heat dissipation were discussed, including Kelvin source connection, short and wide PCB trails (preferably copper), minimized overlap between driving loop and power loop, flux cancellation, sufficient area and thickness of copper, small thermal vias but large in number, direct copper and thermal via placement, increased number of layers, and reduced thickness of PCBs.

A totem-pole bridgeless power factor correction (PFC) converter based on GaN Systems GS66508B was proposed in [54]. The Silicon Laboratories Si8273 was used to drive the GaN HEMTs, and Kelvin source connection, voltage clamp, discharging resistor, and separate turn-on and turn-off paths were utilized. Elrajoubi et al. [55] designed an AC/DC converter for battery charging application based on GaN Systems GS66504B. The Silicon Laboratories Si8273 was used to drive the switches, and the Texas Instruments TMS320F28335 was used to generate PWM signals. Kelvin source connection, four-layer PCB, optimized layout, and voltage clamp were taken into consideration.

In [56], a bidirectional buck–boost converter for EV charging application was designed based on 1.3 kV series-stacked GS66508T switching modules. The modules were each designed with two GaN devices, proper gate impedances, and voltage clamps and required only one driving signal to function. The design yielded almost equally shared DC bus voltage.

#### *5.3. Brief Summary of Reviewed GaN HEMT Driving Circuits*

Table 38 categorizes the reviewed papers according to whether they adopted commercial drivers or self-designed drivers and whether the designed circuits are single-channel or dual-channel circuits, and adopted deriver ICs (if used) are also listed. Sun et al. [57] compared resonant gate drivers for both Si MOSFETs and GaN HEMTs applications. It was concluded that the resonant driver reduced switching losses because of fast charging/discharging capability.

**Table 38.** Reviewed GaN HEMT driving circuits.

#### *5.4. GaN HEMT Power Stages with Integrated Driving Circuits*

Switching module design is also a research focus in the field of GaN HEMT driving. A high-power density, high-efficiency half-bridge module based on insulated metal substrate was proposed in [58] for >3 kW applications. In both high side and low side, two GaN System GS66508Bs were paralleled. The 6-layer module consists of four high-side and four low-side switches. The most crucial work was to minimize and balance parasitic inductances of the GaN switching devices. Brothers and Beechner [59] proposed a threephase 100 V/270 A (per phase) GaN module consisting of six GaN System GS61008Ts. The module layout was then designed based on references from commercial modules and modules in literature. The proposed module successfully hard switched up to 375A.

#### **6. Review on SiC MOSFET Driving Circuits**

*6.1. Single-Channel SiC MOSFET Driving Circuits*

Since the SiC MOSFET has been developed longer than the GaN HEMT, a lot more papers regarding its driving circuit can be found in open literature. Pirc et al. [60] improved the performance of a nanosecond pulse electroporator by adopting Cree C2M0025120D. RECOM DC/DC converters RP-0512D and RP-0505S were used to provide −5 and 24 V isolated power supply, the Broadcom optocoupler HCPL-0723 was used for signal isolation, and the Littelfuse ultrafast MOSFET driver IXDD609SI was used to drive the SiC MOSFETs. In [61], an isolated smart self-driving multilevel SiC MOSFET driver for fast switching and crosstalk suppression was proposed using variable gate voltage generated with an auxiliary circuit that acted differently during turn-on and turn-off periods. The Isolated Analog Devices single-channel driver ADuM4135 was used to drive Cree C2M0040120D. The designed driving circuit adopted a two-state turn-off scheme. At first, the turn off was ensured using negative voltage, and the voltage was then switched to zero to avoid negative voltage breakdown. The circuit was simple, suitable for integration, highly efficient, compact, and cost-effective. A SiC-based 4MHz 10 kW single-phase zero-voltage-switching inverter for high-density plasma generators was proposed in [62]. The Littelfuse singlechannel driver IXRFD630 was used to drive two parallel-connected Cree C2M0080120Ds. The required negative voltage was generated with an auxiliary circuit consisting of a resistor, a capacitor, and a zener diode.

Kim et al. [63] proposed a MHz SiC MOSFET driving circuit using parallel connected FBs based on EPC E-mode device EPC2016. The Broadcom ACPL-346 was used to drive the GaN FBs. The more FBs connected in parallel, the higher the output frequency of pulse width modulation (PWM) could be. The circuit was successfully tested at 2 MHz SiC MOSFET switching frequency using two FBs for a 600 W DC–DC converter. The switching

frequency of 5 MHz was also verified achievable using two FBs (2.5 MHz \* 2). In [64], a highspeed gate driver was designed focusing on high-temperature capability (180 ◦C) with low cost, and the circuit was integrated with overcurrent and undervoltage lockout protection. High-temperature transistors (from On Semiconductor), diodes, zener diodes, and pulse transformer were used to realize the design. Even higher operating temperature could be further realized by using polyimide- and hydrocarbon-based PCBs. The cost was successfully reduced from United States dollar (USD) 2250 to 100 compared with using Cissoid EVK-HADES1210. The tested SiC MOSFET was Fuji Electric MT5F31003. Qi et al. [65] developed a 30 kVA three-phase inverter based on Cree SiC HB power module CAS300M12BM2 in order to investigate how to achieve cost-effective outstanding hightemperature performance (targeted at 180 ◦C ambient temperature). The designed driving circuit was based on Central Semiconductor high-temperature transistors in metal can packages (rated at 200 ◦C) and consisted of signal isolation, gate drive, saturation detection, undervoltage detection, and protection logic circuits. It achieved 90% cost reduction compared with driving circuits using commercial silicon-on-insulator (SOI) ICs (from USD 2250 to 50 for active components).

A low-cost analog active driver was proposed in [34] for a higher parasitic environment. The designed driver consisted of a current amplifier stage and turn-on and turn-off switching controllers and outputted continuous analog current. Cree C2M0080120D was used to verify that the designed driver reduced losses compared with a hard switched gate driver and that good dynamic was achieved with much larger parasitic inductance and capacitance. In [66], a driving circuit with minimum propagation delay was designed to drive Rohm SCH2080KE for high-temperature applications. The design consisted of signal isolation and level shifting circuits and a two-level isolated auxiliary power supply. The isolation circuit achieved very small propagation delay by using non-delay RC differential circuits and a set-rest flip-flop. The auxiliary power supply was compatible with wide input voltage and operating temperature ranges because of the exclusion of low-temperature linear optocouplers. Li et al. [67] focused on crosstalk elimination. High off-state gate impedance was employed to eliminate the voltage drop on the common-source inductance, while the potential fault turn-on was prevented by utilizing the pre-charged voltage in the gate-source capacitance. Cree C2M0025120D was used to verify the driving circuit, and the design was compatible with most of the commercial SiC MOSFETs. Zhao et al. [68] proposed an intelligent and versatile active gate driver with three turn-on speeds and two turn-off speeds using an adjustable voltage regulator, a voltage selector, and a current sinking circuit. Cree C2M0080120D was used to verify the design.

#### *6.2. Dual-Channel SiC MOSFET Driving Circuits*

A 1 kW interleaved high-conversion ratio bidirectional DC-DC converter based on four Rohm SiC MOSFET SCTMU001F and four Si MOSFETs was proposed in [69] for distributed energy storage systems. Each driving circuit drove one SiC MOSFET and one Si MOSFET and consisted of Texas Instruments UCC27531, a transformer with two secondary windings, and a voltage clamp. In [70], two series-connected Cree C2M0160120Ds were driven by a low-cost, simple, and reliable driving circuit based on the Broadcom ACPL-344JT, coupling circuits, dv/dt limiting circuit, and a voltage limit circuit. Good voltage balancing and reliable switching were obtained. Lower switching frequency and smaller DC bus voltage were also compatible for the designed circuit. Wang et al. [71] proposed an enhanced gate driver consisting of the STMicroelectronics galvanically isolated MOS-FET/IGBT driver STGAP1AS, a bipolar junction transistor-based multi-cell current booster, a high-bandwidth and high-accuracy nonintrusive Rogowski switch-current sensor, and a noise-free isolation architecture. The designed driver was verified with Cree HB module CAS300M17BM2 and compatible with almost all the SiC MOSFET modules. Yang et al. [72] proposed a driving circuit with dynamic voltage balancing for series-connected SiC MOS-FETs. Only one external driving IC was required to drive both switches. An overdrive control method helped adapt to DC-bus voltage variation. Switched capacitors could be

utilized to further widen the control range. The Cree C2M1000170D was used to verify the design, which was suitable for various high-voltage applications.

A single gate driver was designed to drive four cascaded series-connected SiC MOS-FETs for medium voltage applications [73]. This was realized using an auxiliary circuits consisting of diodes, zener diodes, resistors, and capacitors. A 2400 V 10 kHz synchronous boost converter was demonstrated using the designed driving circuit.

#### *6.3. Brief Summary of Reviewed SiC MOSFET Driving Circuits*

As can be imagined, many similarities related to safety and loss reduction can be observed in GaN HEMT and SiC MOSFET driving circuit designs. A difference is that SiC MOSFETs require higher driving strength and high temperature capability when used in high-power applications. Table 39 categorizes the reviewed papers according to whether they adopted commercial drivers or self-designed drivers and whether the designed circuits are single-channel or multichannel driving circuits, and adopted deriver ICs are also listed. Sakib et al. [74] compared various gate drivers for SiC MOSFETs (2017). Covered aspects included passively triggered gate drive, negative spike mitigation, crosstalk prevention, and resonance and clamping. Another review was conducted on SiC MOSFET devices and individual SiC MOSFET gate drivers (2018) [75]. Covered items included the adjustment of switching speed, voltage, and power level and other special functions. In [76], the status and applications of SiC-based power converters, challenges regarding highswitching frequency gate driver design, and problems related to commercial drivers were reviewed (2018). It was pointed out that the commercial drivers back then were far from universal, which was due to very specific driving requirements of various SiC switching devices. Liu and Yang [77] reviewed the characteristics of SiC MOSFETs and different driving circuits (2019). It was suggested that, for >150 ◦C applications, discrete components or Si-on-insulator-based gate drivers should be used rather than conventional Si MOS-FET drivers. In terms of crosstalk suppressing, it was recommended that a combination of additional capacitors, variable voltage/resistance driver, and auxiliary discharging path could be used. In [78], slew rate control methods for SiC MOSFET active gate drivers were reviewed (2020). Reviewed aspects included the principle of slew rate control, factors that influenced slew rate, and issues induced by high slew rate. Slew rate control methods included variable gate resistance, input capacitance, gate current, and gate voltage. Control strategies included open-loop, measurement-based, estimation-based, and timingbased controls. The advantages and disadvantages of each control strategy were also listed. Next, the conventional and emerging applications of active gate drive were also reviewed, including EMI noise mitigation, dead-time adaption, motor drive, reliability enhancement of SiC MOSFET, and parallel SiC MOSFET connection.

**Table 39.** Reviewed SiC MOSFET driving circuits.

**Table 39.** *Cont.*

#### *6.4. SiC MOSFET Power Stages with Integrated Driving Circuits*

Some examples of modular SiC MOSFET power stages can be found in [79–81]. Jørgensen et al. [79] proposed a 10 kV single-switch module adopting −5~20 V hard-switched Littlefuse IXRFD630, Kelvin connection, no external gate resistance for the fastest switching speed possible, and low inductance design for better heat dissipation. In [80], a 1200 V/120 A HB module was designed based on a direct bonding copper-stacked hybrid packaging structure for minimized thermal resistance and commutation power loop inductance. The designed module was tested as a 5.5 kW single-phase inverter, yielding 97.7% efficiency, and the power loss was 28.3% less than Cree HB module CAS120M12BM2. A module with adjustable drive strength based on hybrid combination of logics and high temperature capability was proposed in [81]. The Cree bare die SiC MOSFET CPM3-0900-0065B was successfully switched with less than 75 ns rise/fall time from room temperature to over 500 ◦C. Overshoot and dv/dt were successfully and dynamically controlled.

#### **7. Conclusions**

The desire of replacing conventional Si-based switching devices with WBG materialbased switching devices for higher switching frequency and efficiency has led to intensive research on the driving technologies of GaN HEMT and SiC MOSFET. This paper has addressed the characteristics and operating principles of GaN HEMT and SiC MOSFET. Commercially available products of WBG switching devices with Vds ranging from 600V to 1200 V were explored. GaN HEMTs are currently suitable for low- to mid-power and high-frequency applications because of their ultrafast switching speed and ultralow conduction losses, and SiC MOSFETs are especially suitable for high-power applications because of their high thermal capability. In this paper, the driving requirements of WBG switching devices have been explained, where overcoming high slew rate is the biggest challenge. Commercial drivers designed for WBG switching devices were surveyed. It has been observed that drivers for GaN HEMTs and SiC MOSFETs are normally designed based on their specific system requirements. Finally, typical papers discussing the driving circuits of GaN HEMT and SiC MOSFET, previously published review papers, and some papers focusing on modular design of WBG switching devices integrated with driving circuits have been reviewed with brief discussions.

**Author Contributions:** The corresponding author, C.-T.M. conducted the review work, verified the content of technical issues, and polished the final manuscript. Z.-H.G., a postgraduate student in the department of EE, CEECS, National United University, Taiwan, assisted in paper searching and organized results. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research was funded by MOST, Taiwan, with grant numbers MOST 109-2221-E-239-007.

**Institutional Review Board Statement:** Not applicable.

**Informed Consent Statement:** Not applicable.

**Data Availability Statement:** No new data were created or analyzed in this study. Data sharing is not applicable to this article.

**Acknowledgments:** The author would like to thank the Ministry of Science and Technology (MOST) of Taiwan for financially support the energy-related research regarding key technologies in microgrids and the design of advanced power and energy systems.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

**Chao-Tsung Ma 1, \*, Zhen-Yu Tsai 1 , Hung-Hsien Ku 2 and Chin-Lung Hsieh 2**

**Abstract:** In order to efficiently facilitate various research works related to power converter design and testing for solar photovoltaic (PV) generation systems, it is a great merit to use advanced powerconverter-based and digitally controlled PV emulators in place of actual PV modules to reduce the space, cost, and time to obtain the required scenarios of solar irradiances for various functional tests. This paper presents a flexible PV emulator based on gallium nitride (GaN), a wide-bandgap (WBG) semiconductor, and a based synchronous buck converter and controlled with a digital signal processor (DSP). With the help of GaN-based switching devices, the proposed emulator can accurately mimic the dynamic voltage-current characteristics of any PV module under normal irradiance and partial shading conditions. With the proposed PV emulator, it is possible to closely emulate any PV module characteristic both theoretically, based on manufacturer's datasheets, and experimentally, based on measured data from practical PV modules. A curve fitting algorithm is used to handle the real-time generation of control signals for the digital controller. Both simulation with computer software and implementation on 1 kW GaN-based experimental hardware using Texas Instruments DSP as the controller have been carried out. Results show that the proposed emulator achieves efficiency as high as 99.05% and exhibits multifaceted application features in tracking various PV voltage and current parameters, demonstrating the feasibility and excellent performance of the proposed PV emulator.

**Keywords:** wide bandgap semiconductor; gallium nitride; photovoltaic module; digital signal processor; synchronous buck converter

#### **1. Introduction**

It has been predicted that the world's energy consumption will increase by roughly 28% between 2015 and 2040, with residential and commercial buildings' electricity usage being the major contributor to the growth [1]. Conventional electricity generation technologies tend to produce carbon dioxide emission, which is believed to be associated with global warming and some other environmental issues. This has led to an urgent need to increase the penetration of renewable energy (RE)-based distributed power generation (DG). In the past decade, the penetration of typical RE-based DG technologies, such as wind power generation and solar photovoltaic (PV) generation, has grown drastically worldwide [2]. Because of the inherently unpredictable and nonlinear characteristics of these RE-based DG technologies, improvement in energy harvesting and conversion technologies is much desired. Among currently used RE sources, solar PV offers many advantages: it is inexhaustible and pollution-free, and it exhibits the highest energy density, with an average of 170 W/m2 . In addition, solar PV generation systems require relatively low maintenance costs. Increasing the usage of distributed PV systems to a certain level can substantially reduce transmission losses, thus increasing energy utilization. Based on the data reported in [3], until 2017, the total share of global RE-based generation was only roughly 4%, but it

**Citation:** Ma, C.-T.; Tsai, Z.-Y.; Ku, H.-H.; Hsieh, C.-L. Design and Implementation of a Flexible Photovoltaic Emulator Using a GaN-Based Synchronous Buck Converter. *Micromachines* **2021**, *12*, 1587. https://doi.org/10.3390/ mi12121587

Academic Editor: Giovanni Verzellesi

Received: 5 November 2021 Accepted: 17 December 2021 Published: 20 December 2021

**Publisher's Note:** MDPI stays neutral with regard to jurisdictional claims in published maps and institutional affiliations.

**Copyright:** © 2021 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (https:// creativecommons.org/licenses/by/ 4.0/).

has been expected that the solar PV generation level will catch up in the share of future RE-based generation.

The PV cells in a PV module produce DC electricity out of sunlight. As a result, a proper power converter interface is required for a grid-connected or standalone solar PV generation system when supplying electricity to AC loads. When power converters are tested for practical PV generation applications, environmental conditions such as solar irradiance and ambience temperature have to be considered. Testing the converters under actual and various environmental conditions is a valid yet time-consuming method, and the associated cost may be very high. Moreover, it is also challenging to obtain the current and voltage (I-V) characteristics of a PV module in a laboratory with limited space. A better approach is to design PV emulators using power converters, which require much less space and are easily programmable. In the literature, many PV emulation systems have been reported. In [4], a buck converter-based PV emulator was controlled using a fast-convergence resistance-feedback strategy that required a current-resistance model of a PV module. A dynamic field programmable analog array (FPAA)-based PV emulator was presented in [5] with the following advantages: (1) it did not require numerical interpolation or large amount of data in memory; (2) it was easily characterized, compared with a field programmable gate array (FPGA)- or digital signal processor (DSP)-based implementations. In [6], a portable, inexpensive and light-weight plug-and-play PV emulator was developed using a DC/DC converter. Great promise for PV module emulation with a minimum amount of output error was shown. In [7], S. M. Azharuddin et al. proposed a nearaccurate PV emulator using a simple power converter and a dSPACE controller for realtime control. The proposed device enabled fast converter response with a high bandwidth current regulator. A low-cost, portable, embedded design for implementing a real-time, high-accuracy PV emulator using new processors was proposed in [8].

For industrial applications, a PV emulator with a higher power rating is required. In [9], a dynamic 10-kVA PV emulator based on high-power inverters and an active LCL filter was developed and implemented. The maximum power point tracking (MPPT) algorithms of a real PV module were tested using the proposed hardware. The minimized harmonic current content and fast adjustment for power factor (PF) were achieved with the selected power stage. A. Koran et al. [10] proposed a high-efficiency PV source simulator with the advantages of using analog and digital-based controllers. A three-phase AC-DC dual boost rectifier cascaded with a three-phase DC-DC interleaved buck converter was used in this system. A low-cost PV module emulation system developed using LabVIEW software was proposed in [11]. Several analytical models of PV cells and the estimation of power and current curves for a given irradiance and temperature were studied. D. Pelin et al. [12] described a PV emulator using DC programmable sources and conducted a 6-day emulation. In [13], a real-time emulator for control and diagnosis purposes of solar PV generation was developed in a Matlab/Simulink environment. I-V characteristics of generator model were emulated with a programmable DC/AC power source. A PV emulator with quasi-sliding mode controller to realize PV characteristics under rapidly varying environmental conditions was proposed in [14]. In their design case, a userfriendly graphical user interface (GUI) was developed. In [15], a PV emulator using dSPACE controller with simple control was designed to achieve fast response. Current mode controller and a modified look-up table were combined for the control mechanism.

In most of the papers reviewed above, the theoretical models using V-I curves of the given PV modules and the conventional silicon (Si)-based switching devices were commonly used for designing converter-based PV emulators. In the literature, a conference paper [16] presented a hardware design case of the PV module emulator, in which GaN MOSFETs were used; however, the details of controller design issues were not discussed. Comprehensive analysis and comparison of performance between Si- and GaN-based DC-DC converters can be found in [17]. In this paper, a gallium nitride (GaN)-based and DSP-controlled DC-DC converter is presented to achieve a flexible and highly efficient PV emulator with the capability to closely simulate any V-I characteristic of a PV module using

parameters either from manufacture's datasheets or measured data, including normal operating conditions and shading conditions. Flexible emulation features have been implemented with the proposed digital control scheme and verified with a 1 kW hardware prototype. This paper is organized into four sections. In the next section, the PV model is firstly derived, from the cell level to the module level. Then, the modeling of the DC/DC converter and controllers, along with the implementation methodology, are explained. Section 3 presents results from the simulation and implementation of the proposed emulator with an electronic load to demonstrate the performance of the proposed PV emulator. The test of the system efficiencies of the proposed PV emulator using GaN-based synchronous buck converter operated at different switching frequencies is presented in Section 4. Finally, a summary of the paper is given in the last section.

#### **2. PV Module Modeling and Design of Synchronous Buck Converter**

#### *2.1. PV Module Modeling*

A PV module consists of a number of PV cells in series and parallel. Each PV cell is made of a P-N junction semiconductor diode. As the equivalent circuit shown in Figure 1, *Iph* represents equivalent current source (A); *Dj* represents the P-N junction diode; *Rsh* represents equivalent parallel resistance of the material (Ω); *Rs* represents equivalent series resistance of the material (Ω), and *Vp* and *Ip* represent output voltage (V) and current (A), respectively.

**Figure 1.** Equivalent circuit of a PV cell.

From Figure 1, the relationship between output voltage and current can be derived as follows:

$$I\_p = I\_{\rm ph} - I\_{\rm rs} \cdot \left\{ \exp\left[\frac{q(V\_p + R\_s I\_p)}{AkT}\right] - 1 \right\} - \frac{V\_p + R\_s I\_p}{R\_{\rm sh}},\tag{1}$$

where *Irs* represents equivalent reverse saturated current of *Dj* (A); *q* represents elementary charge (1.60 × 10 −19 C); *A* represents ideal factor (ranging from 1 to 5); *k* represents Boltzmann constant (1.38 × 10 −23 J/K), and *T* represents surface temperature (K).

Because the voltage, current, and power generated by a single PV cell are low, many PV cells are usually connected in series and parallel to form a PV module in order to boost the output, as the equivalent circuit shown in Figure 2, where *np* represents the number of paralleled diode paths, and *ns* represents the number of series-connected diodes in each path.

**Figure 2.** Equivalent circuit of a PV module.

Under normal conditions, *Rsh* is large, and *Rs* is small. Ignoring these two parameters, we can simplify (1) to obtain (2).

$$I\_p = I\_{ph} - I\_{rs} \cdot [\exp\left(\frac{qV\_p}{AkT}\right) - 1] \tag{2}$$

where

$$I\_{rs} = I\_{rr} \cdot \left(\frac{T}{T\_r}\right)^3 \cdot \exp[\frac{qE\_g}{kA}(\frac{1}{T\_r} - \frac{1}{T})],\tag{3}$$

*Irr* represents reverse saturated current (A) at reference temperature (*Tr*), and

$$E\_{\mathcal{S}} = 1.16 - (7.02 \times 10^{-4}) \cdot \frac{T^2}{T - 1108^{\prime}} \tag{4}$$

Also,

$$I\_{ph} = \left[I\_{scr} + \frac{\alpha}{1000}(T - T\_r)\right] \cdot \text{S}\_{\prime} \tag{5}$$

where *Iscr* represents short-circuit current (A) at reference temperature and irradiance; *α* represents short-circuit temperature coefficient of a PV cell (mA/ ◦C), and *S* represents solar irradiance (kW/m2 ). The output power of a PV cell can then be expressed as follows:

$$P\_p = V\_p I\_p = I\_{ph} V\_p - I\_{rs} V\_p \cdot [\exp(\frac{qV\_p}{AkT}) - 1]. \tag{6}$$

In Figure 2, *Rsh* and *Rs* can be ignored so that the relationship between output voltage and current can be expressed as follows: