**Figure 9a** is the XPS graph for C1s peak in GO and GOZNs samples. The C1s graph of GO contains sp2 and C─O─C peaks, whereas for the GOZNs sample, the C─O─C peak has disap‐ peared having only sp2 peak in the spectra. The XPS study showed the reduction in oxygen content with the disappeared C─O─C peak for the GO matrix having ZNs, which dem‐ onstrates that GO has become comparatively less resistive having sp2 character dominant. However, ZNs are well known for chemisorption of oxygen at its periphery and it can be evi‐ denced by the fitted O2 peak for O1s spectra in **Figure 9b**. Also, the peak positions for these O1 and O2 in GOZNs sample were found to be little shifted towards lower energy. Furthermore, a noticeable increment in the intensity of O2 peak was also observed in GOZNs in comparison to ZNs. The O1s peak was also found to be shifted to lower binding energy due to the addi‐ tional oxygen absorbed by ZNs as shown in **Figure 9b** [67]. Further, the presence of excess oxygen can also be clearly observed in **Figure 9c** which shows the shift in the Zn 2p peak towards lower energy in GOZNs sample in comparison to ZNs sample [67]. The performance of flexible electronic devices can be tested through flexibility and mechanical endurance mea‐ surements. The flexibility measurements were done on the Al/GOZNs/ITOPET devices and the value of resistance was plotted as a function of bending radii as shown in **Figure 10a**. The resistance was measured up to the maximum bending radius of 4 mm and amazingly found that the LRS and HRS were widely separated and can be well distinguished. The mechanical

**Figure 9.** (a) Comparative XPS spectra of GO and GOZNs for C1S peak. (b) XPS spectra of ZNs and GOZns showing O1S peak resolved into two components O1 and O2. (c) Zn2p spectra of ZNs and GOZNs samples [63].

reliability test was also performed by constantly flexing the device many times to the bending radius of 6 mm and the resistance was plotted against number of bending cycles as shown in **Figure 10b**. The HRS and LRS resistances show no noticeable degradation even up to 1000 times of repeated bending. The measurements performed on the Al/GOZNs/ITOPET device show excellent flexibility and mechanical endurance results and provide the data which show that the devices are capable for flexible memory applications. This study shows that the devices based on ZNs embedded in GO are potential candidate for future flexible non‐volatile memory applications.

in rupture of the conducting channel during the RESET process. But with the incorporation of ZNs into the GO matrix, significant reduction in the switching voltages was observed and this is due to the desorption/adsorption of oxygen at the interface of GO and ZNs, which stimulates the formation/rupture of conducting paths on the application of suitable polarity voltages. This mechanism based on oxygen vacancies is well supported by the X‐ray photo‐

**Figure 8.** Typical I‐V switching characteristics in Al/GOZNs/ITOPET devices. Inset shows the I‐V characteristics for Al/

**Figure 9a** is the XPS graph for C1s peak in GO and GOZNs samples. The C1s graph of GO

content with the disappeared C─O─C peak for the GO matrix having ZNs, which dem‐

However, ZNs are well known for chemisorption of oxygen at its periphery and it can be evi‐ denced by the fitted O2 peak for O1s spectra in **Figure 9b**. Also, the peak positions for these O1 and O2 in GOZNs sample were found to be little shifted towards lower energy. Furthermore, a noticeable increment in the intensity of O2 peak was also observed in GOZNs in comparison to ZNs. The O1s peak was also found to be shifted to lower binding energy due to the addi‐ tional oxygen absorbed by ZNs as shown in **Figure 9b** [67]. Further, the presence of excess oxygen can also be clearly observed in **Figure 9c** which shows the shift in the Zn 2p peak towards lower energy in GOZNs sample in comparison to ZNs sample [67]. The performance of flexible electronic devices can be tested through flexibility and mechanical endurance mea‐ surements. The flexibility measurements were done on the Al/GOZNs/ITOPET devices and the value of resistance was plotted as a function of bending radii as shown in **Figure 10a**. The resistance was measured up to the maximum bending radius of 4 mm and amazingly found that the LRS and HRS were widely separated and can be well distinguished. The mechanical

and C─O─C peaks, whereas for the GOZNs sample, the C─O─C peak has disap‐

peak in the spectra. The XPS study showed the reduction in oxygen

character dominant.

emission spectroscopy (XPS) measurements of these samples shown in **Figure 9**.

onstrates that GO has become comparatively less resistive having sp2

contains sp2

peared having only sp2

GO/ITOPET device [63].

28 Memristor and Memristive Neural Networks

**Figure 10.** (a) Flexibility test for various bending radius on Al/GOZNs/ITOPET RRAM device. (b) Mechanical bending endurance of device at bending radius of 6 mm on Al/GOZNs/ITOPET RRAM device [63].

#### **2.4. Nanoparticles embedded graphene oxide RRAM devices for low operating voltages and high on/off ratio**

were deposited by thermal evaporation method through a shadow mask having diameter of 200 μm. Thus, the device structure formed was Al/GOAu/ITO/glass. Another sample was also fabricated using GOAu solution by spin coating on ITO/glass substrate for XPS study. To know the chemical composition of as‐grown GOAu films by electrophoresis, XPS study was performed as shown in **Figure 12**. These XPS measurements were done to illustrate the amount of oxygen functional groups present in electrodeposited GOAu films (**Figure 12a**) and spin coated GOAu films (**Figure 12b**) (XPS for spin coating films was performed to compare the amount of oxy groups). The peaks corresponding to C1s spectra as depicted in **Figure 12** are C─C, C─O and C═O which are at respective binding energies of 284.6, 286.5 and 288.4 eV. In electrodeposited film, the C─O peak has low intensity in comparison to the C─C peak which shows that the oxygen content is less in the film. The lower oxygen content or presence of oxygen vacancies is favourable for as‐deposited films to be in low‐resistance and hence eliminating the need of forming voltages. Inset of **Figure 12a** shows the presence of Au 4f7/2and

To demonstrate the effect of Au Nps in GO devices, another film of GO having no Au Nps on ITO/glass by electrophoresis keeping same deposition parameters having Al top electrodes (Al/GO/ITO) was fabricated and measured its switching characteristics. **Figure 13a** shows typical I‐V switching characteristics of Al/GO/ITO (inset) and Al/GOAu/ITO devices, respec‐

Ω without Au Nps. Therefore, the initial resistance of the device incorporated with Au Nps was found to be 100 times lower than that of the pristine GO device. The on/off ratio between LRS and HRS in pristine GO devices is very low and that too at high voltages. GOAu devices have enhanced on/off ratio at very low switching voltages as compared to pristine GO devices which is due to the presence of Au Nps, which are working as charge trapping centres.

**Figure 12.** (a) XPS spectra for C1s peak of GOAu film grown by electrophoresis. Inset shows Au peaks for the GOAu film.

(b) C1s peak of spin‐coated GOAu film [71].

Ω with Au Nps and 1.3 × 106

Graphene Oxide-Based Memristor

31

http://dx.doi.org/10.5772/intechopen.69752

Au 4f5/2 peaks at their respective binding energies of 84 and 87.5 eV.

tively. The initial resistance of the devices was found 3.5 × 104

RRAM devices based on oxide have good switching characteristics, but still there are two major downsides with these memories: first one is the need of an initial forming voltage [68–70] to ini‐ tiate the switching mechanism, which is detrimental to device performance, however, this issue can be resolved by manipulating the deposition and growth process and the other problem is the uncontrolled position of conductive channels formation during repetitive applied bias. To address the problem of initial forming in graphene oxide (GO)‐based devices, we adopted the method of electrophoresis to deposit the device structure [71]. Reports have shown that the graphene oxide films grown by electrophoresis are conducted or reduced in nature [72, 73].As the oxygen functional groups attached to its basal plane get removed, the graphene oxide films become semiconducting having localized π‐π electrons network. These functional groups can be eliminated by passing the current during electrophoresis deposition process, resulting GO to be reduced or semiconducting in nature. In this study, the films were deposited by electropho‐ resis and as deposited films were found to be in low‐resistance state; therefore, no high forming voltages were required to initiate the switching process. To resolve the problem of confined conducting channels, we have to understand that there is random formation of conductive fila‐ ments at nanoscale with applied bias in un‐doped films, and it is hard to confine their position precisely. The reports for RRAM devices based on transition metal oxides infused with metal‐ lic nanoparticles have shown enhancement in switching properties with the addition of metal nanoparticles [61, 74]. The present study is focused on improved switching characteristics of graphene oxide films embedded with gold nanoparticles (Au Nps), which helps to confine the conducting filaments during numerous sweep cycles. A colloidal suspension of GO with Au Nps was obtained by sonication. The films were deposited by electrophoresis process using the sonicated GO with Au Nps (GOAu) solution [71]. Electrophoresis was performed using a home‐ built assembly with a pair of ITO/glass as electrodes and a Keithley current source. GOAu films were deposited at room temperature by varying the current value ranging from 0.1 to 1.0 mA for 1–10 minutes having 1.5 cm distance between the electrodes as shown in **Figure 11**.

The thickness of deposited GOAu film was measured to be ∼85 nm. The GO layers were in the size range of 3–5 μm and Au Nps were found in the range of 10–15 nm. The switch‐ ing matrix constitutes the stack of GO layers with Au Nps. Aluminium (Al) top electrodes

**Figure 11.** GO films grown by electrophoresis process.

were deposited by thermal evaporation method through a shadow mask having diameter of 200 μm. Thus, the device structure formed was Al/GOAu/ITO/glass. Another sample was also fabricated using GOAu solution by spin coating on ITO/glass substrate for XPS study. To know the chemical composition of as‐grown GOAu films by electrophoresis, XPS study was performed as shown in **Figure 12**. These XPS measurements were done to illustrate the amount of oxygen functional groups present in electrodeposited GOAu films (**Figure 12a**) and spin coated GOAu films (**Figure 12b**) (XPS for spin coating films was performed to compare the amount of oxy groups). The peaks corresponding to C1s spectra as depicted in **Figure 12** are C─C, C─O and C═O which are at respective binding energies of 284.6, 286.5 and 288.4 eV. In electrodeposited film, the C─O peak has low intensity in comparison to the C─C peak which shows that the oxygen content is less in the film. The lower oxygen content or presence of oxygen vacancies is favourable for as‐deposited films to be in low‐resistance and hence eliminating the need of forming voltages. Inset of **Figure 12a** shows the presence of Au 4f7/2and Au 4f5/2 peaks at their respective binding energies of 84 and 87.5 eV.

**2.4. Nanoparticles embedded graphene oxide RRAM devices for low operating voltages**

RRAM devices based on oxide have good switching characteristics, but still there are two major downsides with these memories: first one is the need of an initial forming voltage [68–70] to ini‐ tiate the switching mechanism, which is detrimental to device performance, however, this issue can be resolved by manipulating the deposition and growth process and the other problem is the uncontrolled position of conductive channels formation during repetitive applied bias. To address the problem of initial forming in graphene oxide (GO)‐based devices, we adopted the method of electrophoresis to deposit the device structure [71]. Reports have shown that the graphene oxide films grown by electrophoresis are conducted or reduced in nature [72, 73].As the oxygen functional groups attached to its basal plane get removed, the graphene oxide films become semiconducting having localized π‐π electrons network. These functional groups can be eliminated by passing the current during electrophoresis deposition process, resulting GO to be reduced or semiconducting in nature. In this study, the films were deposited by electropho‐ resis and as deposited films were found to be in low‐resistance state; therefore, no high forming voltages were required to initiate the switching process. To resolve the problem of confined conducting channels, we have to understand that there is random formation of conductive fila‐ ments at nanoscale with applied bias in un‐doped films, and it is hard to confine their position precisely. The reports for RRAM devices based on transition metal oxides infused with metal‐ lic nanoparticles have shown enhancement in switching properties with the addition of metal nanoparticles [61, 74]. The present study is focused on improved switching characteristics of graphene oxide films embedded with gold nanoparticles (Au Nps), which helps to confine the conducting filaments during numerous sweep cycles. A colloidal suspension of GO with Au Nps was obtained by sonication. The films were deposited by electrophoresis process using the sonicated GO with Au Nps (GOAu) solution [71]. Electrophoresis was performed using a home‐ built assembly with a pair of ITO/glass as electrodes and a Keithley current source. GOAu films were deposited at room temperature by varying the current value ranging from 0.1 to 1.0 mA

for 1–10 minutes having 1.5 cm distance between the electrodes as shown in **Figure 11**.

**Figure 11.** GO films grown by electrophoresis process.

The thickness of deposited GOAu film was measured to be ∼85 nm. The GO layers were in the size range of 3–5 μm and Au Nps were found in the range of 10–15 nm. The switch‐ ing matrix constitutes the stack of GO layers with Au Nps. Aluminium (Al) top electrodes

**and high on/off ratio**

30 Memristor and Memristive Neural Networks

To demonstrate the effect of Au Nps in GO devices, another film of GO having no Au Nps on ITO/glass by electrophoresis keeping same deposition parameters having Al top electrodes (Al/GO/ITO) was fabricated and measured its switching characteristics. **Figure 13a** shows typical I‐V switching characteristics of Al/GO/ITO (inset) and Al/GOAu/ITO devices, respec‐ tively. The initial resistance of the devices was found 3.5 × 104 Ω with Au Nps and 1.3 × 106 Ω without Au Nps. Therefore, the initial resistance of the device incorporated with Au Nps was found to be 100 times lower than that of the pristine GO device. The on/off ratio between LRS and HRS in pristine GO devices is very low and that too at high voltages. GOAu devices have enhanced on/off ratio at very low switching voltages as compared to pristine GO devices which is due to the presence of Au Nps, which are working as charge trapping centres.

**Figure 12.** (a) XPS spectra for C1s peak of GOAu film grown by electrophoresis. Inset shows Au peaks for the GOAu film. (b) C1s peak of spin‐coated GOAu film [71].

**Figure 13.** (a) Typical I‐V characteristics of the Al/GOAu/ITO device in semi‐log scale; inset shows I‐V characteristics for the Al/GO/ITO device. (b) log‐log I‐V plot for the GOAu device [71].

Followed by an initial random charging, the charge carriers around a single Au Np may increase due to trapping process, which results in increasing the capacitive coupling and finally increases the coulomb repulsion.  An additional barrier will be created by these metal‐island capacitors which prevent the movement of electrons in the matrix and the charge transfer through these small metal‐islands, below a particular threshold voltage gets blocked (charges get trapped) leading to an increase in resistance as well. Therefore, in GOAu devices, achieving such a huge resis‐ tance in HRS can be attributed to the coulomb blockade effect imparted by the Au Nps which

**Figure 14.** (a) Retention, (b) endurance properties and (c) statistical distribution over different cells of GOAu device in

Graphene Oxide-Based Memristor

33

http://dx.doi.org/10.5772/intechopen.69752

is associated to the quantum effect of metal nanoparticles [79, 80].

**Figure 15.** C‐V curves of (a) GO and (b) GOAu devices in LRS and HRS [71].

LRS and HRS [71].

The slope of the I‐V curve in LRS was found to be ∼1 as shown in **Figure 13b**; however, this linear current‐voltage relationship need not be ohmic: It can be Schottky‐limited conduction in the Simmons' limit of short electron mean free paths [75],while in the high voltage regime of HRS, the slope was found to be ∼4.4, which reveals that a strong space charge limited cur‐ rent (SCLC) mechanism also known as trapped charge limited current (TCLC) mechanism is prevailing in the device [76]. The TCLC behaviour of the films is in agreement with the pres‐ ence of Au Nps in the films, which are working as charge trapping centres. Hence the charges get trapped in one voltage polarity transiting the device to HRS and detrapped in the opposite polarity rendering back the device to LRS again.  GO sheets have different types of defects, such as oxygen vacancies, dislocations etc. [77, 78]. The defects and trapping nodes present in GO sheets play a significant role in switching behaviour. Initially, the device was in LRS due to the presence of large number of oxygen vacancies and the Au Nps. The device performed well in both states showing retention, endurance and statistical distribution over different cells as shown in **Figure 14a**–**c**.

As discussed above, Au Nps dispersed in GO layers trap the charge, resulting in capacitive behaviour of the devices. In order to test this scenario, capacitance‐voltage (C‐V) measure‐ ments were carried out. **Figure 15a** and **b** shows the C‐V curves of the Al/GO/ITO and Al/ GOAu/ITO devices. The measured capacitance was found to be ∼3.4 pF in LRS and ∼11.2 pF in HRS in GO device, whereas it was ∼9 pF in LRS and ∼350 pF in HRS in the GOAu device. It was observed that in both the resistance states, capacitance values were increased by a factor of ∼10 in HRS/LRS in GOAu devices in comparison to GO devices, which is mainly due to the charge trapping process by Au Nps. In GO matrix having Au Nps, this can be explained as follows: the array of Au Nps induces the coupling capacitance and the trapping energy levels are set by the work function of Au Nps.

**Figure 14.** (a) Retention, (b) endurance properties and (c) statistical distribution over different cells of GOAu device in LRS and HRS [71].

Followed by an initial random charging, the charge carriers around a single Au Np may increase due to trapping process, which results in increasing the capacitive coupling and finally increases the coulomb repulsion.  An additional barrier will be created by these metal‐island capacitors which prevent the movement of electrons in the matrix and the charge transfer through these small metal‐islands, below a particular threshold voltage gets blocked (charges get trapped) leading to an increase in resistance as well. Therefore, in GOAu devices, achieving such a huge resis‐ tance in HRS can be attributed to the coulomb blockade effect imparted by the Au Nps which is associated to the quantum effect of metal nanoparticles [79, 80].

**Figure 15.** C‐V curves of (a) GO and (b) GOAu devices in LRS and HRS [71].

The slope of the I‐V curve in LRS was found to be ∼1 as shown in **Figure 13b**; however, this linear current‐voltage relationship need not be ohmic: It can be Schottky‐limited conduction in the Simmons' limit of short electron mean free paths [75],while in the high voltage regime of HRS, the slope was found to be ∼4.4, which reveals that a strong space charge limited cur‐ rent (SCLC) mechanism also known as trapped charge limited current (TCLC) mechanism is prevailing in the device [76]. The TCLC behaviour of the films is in agreement with the pres‐ ence of Au Nps in the films, which are working as charge trapping centres. Hence the charges get trapped in one voltage polarity transiting the device to HRS and detrapped in the opposite polarity rendering back the device to LRS again.  GO sheets have different types of defects, such as oxygen vacancies, dislocations etc. [77, 78]. The defects and trapping nodes present in GO sheets play a significant role in switching behaviour. Initially, the device was in LRS due to the presence of large number of oxygen vacancies and the Au Nps. The device performed well in both states showing retention, endurance and statistical distribution over

**Figure 13.** (a) Typical I‐V characteristics of the Al/GOAu/ITO device in semi‐log scale; inset shows I‐V characteristics for

As discussed above, Au Nps dispersed in GO layers trap the charge, resulting in capacitive behaviour of the devices. In order to test this scenario, capacitance‐voltage (C‐V) measure‐ ments were carried out. **Figure 15a** and **b** shows the C‐V curves of the Al/GO/ITO and Al/ GOAu/ITO devices. The measured capacitance was found to be ∼3.4 pF in LRS and ∼11.2 pF in HRS in GO device, whereas it was ∼9 pF in LRS and ∼350 pF in HRS in the GOAu device. It was observed that in both the resistance states, capacitance values were increased by a factor of ∼10 in HRS/LRS in GOAu devices in comparison to GO devices, which is mainly due to the charge trapping process by Au Nps. In GO matrix having Au Nps, this can be explained as follows: the array of Au Nps induces the coupling capacitance and the trapping energy levels

different cells as shown in **Figure 14a**–**c**.

the Al/GO/ITO device. (b) log‐log I‐V plot for the GOAu device [71].

32 Memristor and Memristive Neural Networks

are set by the work function of Au Nps.

## **3. Conclusions**

In summary, graphene oxide is a promising material for RRAM devices due to its high scalability and unique physical‐chemical properties. Fabrication of GO and its films, composites and het‐ erostructures are very cost effective and opens up the direction for commercialization. Showing forming‐free behaviour is an excellent property of GO devices over other oxide‐based devices that require initial high voltages to start the switching process. Multi‐level switching in GO‐ based heterostructures has the potential of high‐density data storage, which is the need of future non‐volatile memories. Flexibility and mechanical endurance observed in GO‐based composite RRAM devices have prospects in portable and flexible devices which is advantageous over the rigid silicon technology. Gold nanoparticles embedded in GO have shown enhanced switching properties with very high on/off resistance ratio and very low switching voltages, which are suit‐ able for low power resistive memory devices. The mechanism underlying the graphene oxide‐ based memories is the formation of conductive filaments due to the roles played by oxygen ions and vacancies. Therefore, GO‐based RRAM devices have enough potential to become one of the important non‐volatile memories due to their encouraging properties of forming free, multi‐bit data storage and low power flexible devices. However, further research is still needed towards scaling of these devices below 10 nm node and that too having fast switching speeds to establish graphene oxide‐based non‐volatile resistive devices achieve a niche in memory industry.

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## **Acknowledgements**

The authors acknowledge the financial support from DOD Grant (AFOSR‐FA9550‐16‐1‐0295) and IFN‐NSF Grant (EPS‐01002410) for travel support.

## **Author details**

Geetika Khurana1 \*, Nitu Kumar1 , James F. Scott2,3 and Ram S. Katiyar1

\*Address all correspondence to<EMAIL_ADDRESS>

## **References**

[1] Chua LO. Memristor – The missing circuit element. IEEE Transactions Circuit Theory CT‐18. 1971;**18**:507‐519

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**3. Conclusions**

34 Memristor and Memristive Neural Networks

**Acknowledgements**

**Author details**

Geetika Khurana1

**References**

CT‐18. 1971;**18**:507‐519

and IFN‐NSF Grant (EPS‐01002410) for travel support.

\*, Nitu Kumar1

1 University of Puerto Rico, San Juan, Puerto Rico

\*Address all correspondence to<EMAIL_ADDRESS>
2 Department of Chemistry, University of St Andrews, St Andrews, UK

3 Department of Physics, University of St Andrews, St Andrews, UK

In summary, graphene oxide is a promising material for RRAM devices due to its high scalability and unique physical‐chemical properties. Fabrication of GO and its films, composites and het‐ erostructures are very cost effective and opens up the direction for commercialization. Showing forming‐free behaviour is an excellent property of GO devices over other oxide‐based devices that require initial high voltages to start the switching process. Multi‐level switching in GO‐ based heterostructures has the potential of high‐density data storage, which is the need of future non‐volatile memories. Flexibility and mechanical endurance observed in GO‐based composite RRAM devices have prospects in portable and flexible devices which is advantageous over the rigid silicon technology. Gold nanoparticles embedded in GO have shown enhanced switching properties with very high on/off resistance ratio and very low switching voltages, which are suit‐ able for low power resistive memory devices. The mechanism underlying the graphene oxide‐ based memories is the formation of conductive filaments due to the roles played by oxygen ions and vacancies. Therefore, GO‐based RRAM devices have enough potential to become one of the important non‐volatile memories due to their encouraging properties of forming free, multi‐bit data storage and low power flexible devices. However, further research is still needed towards scaling of these devices below 10 nm node and that too having fast switching speeds to establish graphene oxide‐based non‐volatile resistive devices achieve a niche in memory industry.

The authors acknowledge the financial support from DOD Grant (AFOSR‐FA9550‐16‐1‐0295)

, James F. Scott2,3 and Ram S. Katiyar1

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**Chapter 3**

**Provisional chapter**

**Emulator Circuits and Resistive Switching Parameters**

Chua predicted the existence of the fundamental circuit element, which provides the linkage of flux (*ϕ*) and charge (*q*). The new circuit element that is called memristor (memory + resistor) was demonstrated by Hewlett Packard (HP) researchers in 2008. Researchers focused on memristor fabrication, modeling, and its application with other circuit elements. Researchers could not find the commercially memristor devices in the market because of some fabrication difficulties. For this reason, researchers focused on the memristor modeling to analyze its characteristics with other circuit elements. This chapter presents a review of the general information of memristor and its device parameters. The chapter is continued with the details of memristor mathematical and SPICE

**Keywords:** memristor, memristor models, SPICE, memristor emulator, active circuit

Both active circuit elements and passive circuit elements are used in circuit design, and the first circuit elements that come to mind are passive circuit elements: resistor, capacitor, and inductor. Resistor, capacitor, and inductor define the relationship between the voltage and current, voltage and charge, and current and flux, respectively. Leon Chua from the University of California (Berkeley) showed the missing relationship as shown in **Figure 1** between flux and

At the same time, Chua called the missing circuit element as a memristor (memory + resistor) and presented the mathematical equations of the new circuit element. But the seminal paper

models and memristor emulators based on the other circuit elements.

**Emulator Circuits and Resistive Switching Parameters**

DOI: 10.5772/intechopen.71903

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

**of Memristor**

**Abstract**

**1. Introduction**

current in 1971 and 1976 [1, 2].

**of Memristor**

Abdullah Yesil, Fatih Gül and Yunus Babacan

Additional information is available at the end of the chapter

Abdullah Yesil, Fatih Gül and Yunus Babacan

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.71903

element-based memristors

**Provisional chapter**

## **Emulator Circuits and Resistive Switching Parameters of Memristor of Memristor**

**Emulator Circuits and Resistive Switching Parameters**

DOI: 10.5772/intechopen.71903

Abdullah Yesil, Fatih Gül and Yunus Babacan

[77] Khurana G, Kumar N, Kotnala RK, Nautiyal T, Katiyar RS. Temperature tuned defect induced magnetism in reduced graphene oxide. Nanoscale. 2013;**5**:3346‐3351

[78] Rozada R, Paredes JI, Villar‐Rodil S, Martínez‐Alonso A, Tascón JMD. Towards full repair of defects in reduced graphene oxide films by two‐step graphitization. Nano

[79] Lu J, Moon KS, Xu J, Wong CP. Synthesis and dielectric properties of novel high‐K poly‐ mer composites containing in‐situ formed silver nanoparticles for embedded capacitor

[80] Feng Q, Dang Z, Li N, Cao X. Preparation and dielectric property of Ag‐PVA nano‐com‐

applications. Journal of Materials Chemistry. 2006;**16**:1543‐1548

posite. Materials Science and Engineering: B. 2003;**99**:325‐328

Research. 2013;**6**:216‐233

40 Memristor and Memristive Neural Networks

Abdullah Yesil, Fatih Gül and Yunus Babacan Additional information is available at the end of the chapter

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.71903

#### **Abstract**

Chua predicted the existence of the fundamental circuit element, which provides the linkage of flux (*ϕ*) and charge (*q*). The new circuit element that is called memristor (memory + resistor) was demonstrated by Hewlett Packard (HP) researchers in 2008. Researchers focused on memristor fabrication, modeling, and its application with other circuit elements. Researchers could not find the commercially memristor devices in the market because of some fabrication difficulties. For this reason, researchers focused on the memristor modeling to analyze its characteristics with other circuit elements. This chapter presents a review of the general information of memristor and its device parameters. The chapter is continued with the details of memristor mathematical and SPICE models and memristor emulators based on the other circuit elements.

**Keywords:** memristor, memristor models, SPICE, memristor emulator, active circuit element-based memristors

#### **1. Introduction**

Both active circuit elements and passive circuit elements are used in circuit design, and the first circuit elements that come to mind are passive circuit elements: resistor, capacitor, and inductor. Resistor, capacitor, and inductor define the relationship between the voltage and current, voltage and charge, and current and flux, respectively. Leon Chua from the University of California (Berkeley) showed the missing relationship as shown in **Figure 1** between flux and current in 1971 and 1976 [1, 2].

At the same time, Chua called the missing circuit element as a memristor (memory + resistor) and presented the mathematical equations of the new circuit element. But the seminal paper

main structures which are named doped and undoped region as shown in **Figure 3**, and the

Memristor acts as a conductor if the thickness of the doped region becomes wide as shown in **Figure 3b**. Undoped region becomes wide as shown in **Figure 3c**, and memristor behaves as a

*dt* = *μv R* \_\_\_\_\_*ON*

*dt* = *μv R* \_\_\_\_\_*ON*

 **(a) (b)**

**D**

**(c)**

**Figure 3.** Memristor (a) initial state, (b) low-resistance state, and (c) high-resistance state.

Undoped Region

Doped Region,w

The first function which is called window function is presented by HP research team [3] as

 is the electron mobility, and *w* and *D* denote the doped area of memristor and thickness of the memristor, respectively. The resistances of the high and low dopant concentrations are symbolized with *RON* and *ROFF*, respectively. Researchers added a function to the memristor mathematical model to take into account the nonlinear dopant effect [3, 5–7]. Equation (3) is

], (*x* = \_\_*w*

*D*) (2)

*D*2 *i*(*t*) (3)

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43

*D*2 *i*(*t*)*f*(*x*) (4)

*D* (5)

Undoped Region

Doped Region

**D**

**w**

memristance changes the ratios of the doped region and device thickness.

*M*(*x*) = [*RON x* + *ROFF*(1 − *x*)

Memristance is as below:

rearranged as follows:

shown below:

The *μv*

The change of the *x* value is depicted:

\_\_\_ *dx*

\_\_\_ *dx*

Doped Region

**w**

*f*(*x*) = \_\_\_\_\_ *x*(1 − *x*)

**D**

Undoped Region

high-resistance element when the input signal applied in an opposite direction.

**Figure 1.** The fundamental two-terminal passive circuit elements.

**Figure 2.** The scanning tunneling microscope image of the memristor [4].

of Chua could not find attentions among the researchers because of the technical fabrication difficulties of the memristor. Therefore, researchers did not focus on the memristor and its application until its first fabrication of memristor by HP researchers in 2008 [3]. The first memristor is made from TiO2 thin film and has crossbar structure as shown in **Figure 2**.

The HP research team also presented the mathematical model of TiO2 memristor, and currentvoltage relationship is defined by

$$V = \begin{bmatrix} M(\mathbf{x}\_{1'}, \mathbf{x}\_{2'}, \dots, \mathbf{x}\_n) \end{bmatrix} I \tag{1}$$

where *V* is the voltage and *I* is the current. Here, *M* is the resistance of memristor and memristance and depends on *xi* state variables. Memristance which performs nonlinear characteristics depends on frequency and applied input signal. The TiO2 memristor consists of two main structures which are named doped and undoped region as shown in **Figure 3**, and the memristance changes the ratios of the doped region and device thickness.

Memristor acts as a conductor if the thickness of the doped region becomes wide as shown in **Figure 3b**. Undoped region becomes wide as shown in **Figure 3c**, and memristor behaves as a high-resistance element when the input signal applied in an opposite direction.

Memristance is as below:

of Chua could not find attentions among the researchers because of the technical fabrication difficulties of the memristor. Therefore, researchers did not focus on the memristor and its application until its first fabrication of memristor by HP researchers in 2008 [3]. The first

, *x*2

where *V* is the voltage and *I* is the current. Here, *M* is the resistance of memristor and mem-

The HP research team also presented the mathematical model of TiO2

**Figure 2.** The scanning tunneling microscope image of the memristor [4].

teristics depends on frequency and applied input signal. The TiO2

thin film and has crossbar structure as shown in **Figure 2**.

state variables. Memristance which performs nonlinear charac-

memristor, and current-

memristor consists of two

, …*xn*)]*I* (1)

memristor is made from TiO2

ristance and depends on *xi*

voltage relationship is defined by

*V* = [*M*(*x*1

**Figure 1.** The fundamental two-terminal passive circuit elements.

42 Memristor and Memristive Neural Networks

$$M(\mathbf{x}) = \begin{bmatrix} \mathbb{R}\_{\text{cov}} \mathbf{x} + \mathbb{R}\_{\text{cov}} (1 - \mathbf{x}) \end{bmatrix}\_{\prime} \begin{pmatrix} \mathbf{x} = \frac{w}{D} \end{pmatrix} \tag{2}$$

The change of the *x* value is depicted:

*f*(*x*) = \_\_\_\_\_ *x*(1 − *x*)

$$\frac{d\mathbf{x}}{dt} = \frac{\mu\_v R\_{\text{ON}}}{D^2} \mathbf{i}(t) \tag{3}$$

The *μv* is the electron mobility, and *w* and *D* denote the doped area of memristor and thickness of the memristor, respectively. The resistances of the high and low dopant concentrations are symbolized with *RON* and *ROFF*, respectively. Researchers added a function to the memristor mathematical model to take into account the nonlinear dopant effect [3, 5–7]. Equation (3) is rearranged as follows:

$$\frac{d\mathbf{x}}{dt} = \frac{\mu\_\nu R\_{\rm ON}}{D^2} \mathbf{i}(\mathbf{t}) \mathbf{f}(\mathbf{x}) \tag{4}$$

*D* (5)

The first function which is called window function is presented by HP research team [3] as shown below:

**Figure 3.** Memristor (a) initial state, (b) low-resistance state, and (c) high-resistance state.

**Figure 4.** Window function presented by Wolf and Joglekar [5].

The HP model is linear and very simple; so Wolf and Joglekar [5] depicted the new window function as shown below:

$$f(\mathbf{x}) = \mathbf{1} - (2\mathbf{x} - \mathbf{1})^{2p} \tag{6}$$

Model function of Prodromakis et al. becomes higher than the value of 1 unlike previous win-

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45

Researchers suggested various mathematical memristor models such as nonlinear ion-drift model [8], Simmons' tunnel barrier model [9], and ThrEshold Adaptive Memristor (TEAM) model [10] different from the linear HP model. The chapter is continued with memristor

The pinched hysteresis loops serve as a fingerprint in the characterization of memristors [11] as shown in **Figure 7**. It is to say that, if any two-terminal device is showing pinched hysteresis loop, a memristor regardless of the device material is accepted. Resistive switching (or memristive behavior) in metal-oxide semiconductor was first observed by Hickmott in 1962, but it was interpreted as the current anomaly [12]. As in resistive switching devices, a typical pinched hysteresis loop is seen at the first and third quadrants of the current-voltage (I-V) curves [13]. Put differently, all memristors can be accepted as resistive switching devices

**a) b)**

**Figure 7.** (a) Schematic representation of a memristor device and (b) typical pinched hysteresis current-voltage loop of

dow functions. The function depends on the various *p*-values shown in **Figure 6**.

**2. Memristor switching device parameters**

Boom Electrode

Top Electrodes

Acve Layer or Layers

memristor devices.

**Figure 6.** Window function presented by Prodromakis et al. [7].

regardless of the operating mechanisms and the device material [14].

device.

The function is starting to similar the rectangular shape when *p*-value becomes higher, namely, dopant drift is decreasing as shown in **Figure 4**.

Biolek et al. [6] modified the model of Wolf and Joglekar:

$$f(\mathbf{x}) = \mathbf{1} - (\mathbf{x} - \text{stp}(-i))^{2\rho} \tag{7a}$$

$$stp(\mathbf{j}) = \begin{cases} 1, i \ge 0 \\ 0, i < 0 \end{cases} \tag{7b}$$

The window function which is presented by Biolek is shown in **Figure 5**.

Prodromakis et al. [7] depict the versatile model as the following:

$$f(\mathbf{x}) = j(1 - [(\mathbf{x} - 0.5)^2 + 0.75]^\circ) \tag{8}$$

**Figure 5.** Window function presented by Biolek et al. [6].

**Figure 6.** Window function presented by Prodromakis et al. [7].

The HP model is linear and very simple; so Wolf and Joglekar [5] depicted the new window

*f*(*x*) = 1 − (2*x* − 1)2*p* (6)

The function is starting to similar the rectangular shape when *p*-value becomes higher,

*f*(*x*) = 1 − (*x* − *stp*(−*i*))2*p* (7a)

*f*(*x*) = *j*(1 − [(*x* − 0.5)2 + 0.75]*p*) (8)

The window function which is presented by Biolek is shown in **Figure 5**.

Prodromakis et al. [7] depict the versatile model as the following:

1, *i* ≥ 0

0, *i* < 0 (7b)

function as shown below:

44 Memristor and Memristive Neural Networks

namely, dopant drift is decreasing as shown in **Figure 4**. Biolek et al. [6] modified the model of Wolf and Joglekar:

**Figure 4.** Window function presented by Wolf and Joglekar [5].

*stp*(*i*) = {

**Figure 5.** Window function presented by Biolek et al. [6].

Model function of Prodromakis et al. becomes higher than the value of 1 unlike previous window functions. The function depends on the various *p*-values shown in **Figure 6**.

Researchers suggested various mathematical memristor models such as nonlinear ion-drift model [8], Simmons' tunnel barrier model [9], and ThrEshold Adaptive Memristor (TEAM) model [10] different from the linear HP model. The chapter is continued with memristor device.

#### **2. Memristor switching device parameters**

The pinched hysteresis loops serve as a fingerprint in the characterization of memristors [11] as shown in **Figure 7**. It is to say that, if any two-terminal device is showing pinched hysteresis loop, a memristor regardless of the device material is accepted. Resistive switching (or memristive behavior) in metal-oxide semiconductor was first observed by Hickmott in 1962, but it was interpreted as the current anomaly [12]. As in resistive switching devices, a typical pinched hysteresis loop is seen at the first and third quadrants of the current-voltage (I-V) curves [13]. Put differently, all memristors can be accepted as resistive switching devices regardless of the operating mechanisms and the device material [14].

**Figure 7.** (a) Schematic representation of a memristor device and (b) typical pinched hysteresis current-voltage loop of memristor devices.

#### **2.1. Active layer material and top/bottom electrode**

The semiconductor-based memristor devices usually consist of an active layer sandwiched between a top and a bottom electrode (TE/BE) depicted in **Figure 7**. The first physical implementation of the memristor was achieved by HP labs using TiO2 metal-oxide active layer [3]. After that, several physical memristor devices suggested the use of different materials and production methods. Most metal-oxide semiconductors exhibit memristor characteristics, including TiO2 , ZnO, HfO2 , VO2 , TaOx , and so on [13, 15, 16]. There are two types of contact in semiconductor: one is of Schottky (rectifying), and the other one is ohmic. Several electrode materials can be used as TE or BE including Pt, Au, Ag, Al, etc. In one diode-one resistor (1D1R) type memory cell memristor device, one of the electrodes must be a Schottky contact [17].

in the active layer. Both types of mechanisms can be observed in the memristor devices as

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47

It is well known that reversible switching between a low-resistance state (LRS) or ON (SET) and a high-resistance state (HRS) or OFF (RESET) can be achieved by applying a certain voltage [18]. Operation voltage is also an important value for CMOS or other device integrations for memristor devices. Another criterion for the memristor devices is the power consumption related to the operation current. With the aim of escape permanent damage from over current, the compliance or limit current (CC) must be set in both unipolar and bipolar operations [13]. The compliance current is also related to power consumption of a memristor device [19].

The memristor has two states when used as a switching device: the high-resistance state (HRS) or OFF (RESET) state and the low-resistance state (LRS) or ON (SET) state [13]. The ON/OFF ratio defined as the proportion between resistances in HRS and LRS is some of the

The time to hold ON/OFF state is an important criterion when memristor device used a resistive switching memory or ReRAM element [20]. It is expected that the memristor device's distribution of the HRS or LRS state which is shown in **Figure 10** has acceptable values besides its ON/OFF ratio [19]. Since the memory unit needs to be repeatedly read or written by the other control units, cycling endurance is one of the main importance of memristor-based memory

Some of recent memristor devices which are composed of various materials are compared according to the some important parameters as shown in **Table 1** [19, 22–24]. The chapter is

**Figure 9.** Typical current-voltage curves of memristor devices: (a) filamentary and (b) homogenous transitions on

most important parameters when memristors are used as switching device [18].

continued with memristor emulators based on the active circuit elements.

shown in **Figure 9** and depend on the material and fabrication methods [18].

**2.4. Operation current-voltage**

**2.6. Retention time and endurance**

**2.5. ON/OFF ratio**

devices [18].

bipolar operation [19].

#### **2.2. Unipolar or bipolar operation**

The unipolar and bipolar operation of memristor devices which are shown in **Figure 8** can be categorized in according with current-voltage characteristics. In unipolar operation characteristics depend only on the amplitude of the applied voltage, whereas bipolar operations are resolved by polarity and amplitude of the applied voltage [13]. Unipolar operation is more striking than bipolar operation in memristor switching devices, since it needs simple circuits. But then, bipolar operation has generally high uniformity and more endurance compared to unipolar operation [18].

#### **2.3. Physical mechanism**

There are two types of physical working mechanisms in the explanation of the time-dependent current-voltage characteristics, based on molecular or ionic models: the homogeneous interface type and the filamentary (conduction path) type [13, 16]. In the homogeneous type, the migration of oxygen vacancies as the majority carriers causes change of resistance. The filament-type mechanism is associated with the formation and rupture of conductive filaments

**Figure 8.** Typical current-voltage curves of memristor devices (a) unipolar and (b) bipolar.

in the active layer. Both types of mechanisms can be observed in the memristor devices as shown in **Figure 9** and depend on the material and fabrication methods [18].

#### **2.4. Operation current-voltage**

It is well known that reversible switching between a low-resistance state (LRS) or ON (SET) and a high-resistance state (HRS) or OFF (RESET) can be achieved by applying a certain voltage [18]. Operation voltage is also an important value for CMOS or other device integrations for memristor devices. Another criterion for the memristor devices is the power consumption related to the operation current. With the aim of escape permanent damage from over current, the compliance or limit current (CC) must be set in both unipolar and bipolar operations [13]. The compliance current is also related to power consumption of a memristor device [19].

#### **2.5. ON/OFF ratio**

**2.1. Active layer material and top/bottom electrode**

, ZnO, HfO2

**2.2. Unipolar or bipolar operation**

46 Memristor and Memristive Neural Networks

unipolar operation [18].

**2.3. Physical mechanism**

including TiO2

mentation of the memristor was achieved by HP labs using TiO2

, TaOx

**Figure 8.** Typical current-voltage curves of memristor devices (a) unipolar and (b) bipolar.

, VO2

The semiconductor-based memristor devices usually consist of an active layer sandwiched between a top and a bottom electrode (TE/BE) depicted in **Figure 7**. The first physical imple-

After that, several physical memristor devices suggested the use of different materials and production methods. Most metal-oxide semiconductors exhibit memristor characteristics,

in semiconductor: one is of Schottky (rectifying), and the other one is ohmic. Several electrode materials can be used as TE or BE including Pt, Au, Ag, Al, etc. In one diode-one resistor (1D1R) type memory cell memristor device, one of the electrodes must be a Schottky contact [17].

The unipolar and bipolar operation of memristor devices which are shown in **Figure 8** can be categorized in according with current-voltage characteristics. In unipolar operation characteristics depend only on the amplitude of the applied voltage, whereas bipolar operations are resolved by polarity and amplitude of the applied voltage [13]. Unipolar operation is more striking than bipolar operation in memristor switching devices, since it needs simple circuits. But then, bipolar operation has generally high uniformity and more endurance compared to

There are two types of physical working mechanisms in the explanation of the time-dependent current-voltage characteristics, based on molecular or ionic models: the homogeneous interface type and the filamentary (conduction path) type [13, 16]. In the homogeneous type, the migration of oxygen vacancies as the majority carriers causes change of resistance. The filament-type mechanism is associated with the formation and rupture of conductive filaments

metal-oxide active layer [3].

, and so on [13, 15, 16]. There are two types of contact

The memristor has two states when used as a switching device: the high-resistance state (HRS) or OFF (RESET) state and the low-resistance state (LRS) or ON (SET) state [13]. The ON/OFF ratio defined as the proportion between resistances in HRS and LRS is some of the most important parameters when memristors are used as switching device [18].

#### **2.6. Retention time and endurance**

The time to hold ON/OFF state is an important criterion when memristor device used a resistive switching memory or ReRAM element [20]. It is expected that the memristor device's distribution of the HRS or LRS state which is shown in **Figure 10** has acceptable values besides its ON/OFF ratio [19]. Since the memory unit needs to be repeatedly read or written by the other control units, cycling endurance is one of the main importance of memristor-based memory devices [18].

Some of recent memristor devices which are composed of various materials are compared according to the some important parameters as shown in **Table 1** [19, 22–24]. The chapter is continued with memristor emulators based on the active circuit elements.

**Figure 9.** Typical current-voltage curves of memristor devices: (a) filamentary and (b) homogenous transitions on bipolar operation [19].

**Figure 10.** Typical endurance test of a memristor device @0.1 V for 100 cycles [21].

**Table 1.** Comparison table of some recent memristor devices.

#### **3. Memristor models and emulators**

Many SPICE models and emulators are presented by researchers [6, 25–47]. The first and applicable memristor model has been presented by Biolek and co-workers [6]. This model takes into account the boundary conditions using window function, and the feedback-controlled integrator is used to implement memory effect of the memristor. The block diagram of memristor and its SPICE model is shown in **Figure 11**. All simulation results which are shown in **Figure 12** are completed using SPICE codes as shown below. Each curve is compatible with TiO2 memristor, and boundary effects are taken into account (**Table 2**).

Another active circuit element-based grounded memristor emulator [36] has been implemented by using current backward transconductance amplifier (CBTA). This emulator consists of two different circuits such as decremental and incremental type given in **Figure 14**. Each memristor emulator is composed of a single CBTA, two resistors, one grounded capacitor, and single analog multiplier. In order to validate the feasibility of the presented memris-

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**Figure 12.** Charge-flux, current-voltage, current-voltage-time, and x-time curves for memristor model [6].

The generalized mutator structure based on adder and subtractor has been proposed by Minaei et al. [37]. As far as connection ports are concerned, the generalized structure employs memristor, meminductor, and memcapacitor without using analog multiplier. By selecting an inductor to port 3, a capacitor to port 4, and a nonlinear resistor such as a diode to port 1, the generalized structure given in **Figure 15** is utilized as memristor. Nonetheless, so as to verify

the workableness of the presented structure, the SPICE simulation results are given.

tor, only SPICE simulation results have been given.

**Figure 11.** (a) Block diagram and (b) SPICE model of the memristor [6].

Researchers are not able to reach the memristor devices in the market because of some production problems of the memristor. For this reason, researchers focused on the designing of memristor emulators to use with other circuit elements. Yener and Kuntman reported full active device-based memristor emulator which is consisting of differential difference current conveyor (DDCC) [35]. The proposed grounded memristor emulator consists of four circuit blocks based on DDCC as shown in **Figure 13**. Furthermore, there are no experimental results; however, its SPICE simulation results are given.

Emulator Circuits and Resistive Switching Parameters of Memristor http://dx.doi.org/10.5772/intechopen.71903 49

**Figure 11.** (a) Block diagram and (b) SPICE model of the memristor [6].

**3. Memristor models and emulators**

**Table 1.** Comparison table of some recent memristor devices.

**TE/BE Operation mode**

48 Memristor and Memristive Neural Networks

**Figure 10.** Typical endurance test of a memristor device @0.1 V for 100 cycles [21].

**Operation mechanism**

however, its SPICE simulation results are given.

TiO2

**Active layer material**

Many SPICE models and emulators are presented by researchers [6, 25–47]. The first and applicable memristor model has been presented by Biolek and co-workers [6]. This model takes into account the boundary conditions using window function, and the feedback-controlled integrator is used to implement memory effect of the memristor. The block diagram of memristor and its SPICE model is shown in **Figure 11**. All simulation results which are shown in **Figure 12** are completed using SPICE codes as shown below. Each curve is compatible with

**Operation voltage**

ZnO Al/Al Bipolar Homogenous −1.5 V/+1.5 V 5 × 101 N/A 100 [19] TiO2 Al/Al Bipolar Filamentary −3 V/+1.5 V 8 × 102 N/A 1012 [22] HfO2 Pt/Ti Bipolar Filamentary −3.5 V/+2 V 103 104 1000 [23] TaOx Pt/Pt Unipolar Filamentary −1.5 V/+1 V 101 N/A 1000 [24]

**ON/OFF ratio**

**Retention time**

**Endurance Ref.**

Researchers are not able to reach the memristor devices in the market because of some production problems of the memristor. For this reason, researchers focused on the designing of memristor emulators to use with other circuit elements. Yener and Kuntman reported full active device-based memristor emulator which is consisting of differential difference current conveyor (DDCC) [35]. The proposed grounded memristor emulator consists of four circuit blocks based on DDCC as shown in **Figure 13**. Furthermore, there are no experimental results;

memristor, and boundary effects are taken into account (**Table 2**).

**Figure 12.** Charge-flux, current-voltage, current-voltage-time, and x-time curves for memristor model [6].

Another active circuit element-based grounded memristor emulator [36] has been implemented by using current backward transconductance amplifier (CBTA). This emulator consists of two different circuits such as decremental and incremental type given in **Figure 14**. Each memristor emulator is composed of a single CBTA, two resistors, one grounded capacitor, and single analog multiplier. In order to validate the feasibility of the presented memristor, only SPICE simulation results have been given.

The generalized mutator structure based on adder and subtractor has been proposed by Minaei et al. [37]. As far as connection ports are concerned, the generalized structure employs memristor, meminductor, and memcapacitor without using analog multiplier. By selecting an inductor to port 3, a capacitor to port 4, and a nonlinear resistor such as a diode to port 1, the generalized structure given in **Figure 15** is utilized as memristor. Nonetheless, so as to verify the workableness of the presented structure, the SPICE simulation results are given.

**Table 2.** SPICE codes of modeled memristor [6].

Kim and co-workers presented the active circuit element-based memristor emulator [38]. This circuit is also implemented on the bread board using discrete circuit elements that are ADL1116PAL for NMOS transistors, ADL1117PAL for PMOS transistors, TL082 for OPAMP, and AD633 for analog multiplier and passive elements. There are three important tasks to implement memristor emulator: memory effect, frequency-/voltage-dependent characteristics, and nonlinearity. Memory effect and frequency/voltage dependency characteristics are implemented by using a capacitor like many other previous emulator circuits. Nonlinear characteristic of the memristor is obtained using multiplier circuit block. But each used block gives rise to extra power dissipation and more complex circuit (**Figure 16**).

Another active circuit-based memristor emulators which are shown in **Figure 17** have been presented by Abuelma'atti and Khalifa [39]. Each emulator which is based on current-feedback operational amplifier (CFOA) enjoys operating two different types like decremental and incremental memristor emulators. This situation is a disadvantage of the emulator besides its grounded structure. Each circuit comprises three CFOAs, four resistors, two capacitors, and germanium diode without using an analog multiplier. Nonlinear characteristic is provided by germanium diode. CFOA which is an active element is modeled by AD844 commercially

**Figure 14.** CBTA-based memristor emulator (a) decremental structure and (b) incremental structure [36].

V1 **(+)**

I1

**(-)**

**Subtractor**

V3

I3

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**Adder**

**(+)**

**(-)**

I4 V4

available active devices, and experimental results have been investigated.

V2

**Figure 15.** Generalized mutator structure based on adder and subtractor [37].

I2

**Figure 13.** DDCC-based memristor emulator which is presented by Yener and Kuntman [35].

Emulator Circuits and Resistive Switching Parameters of Memristor http://dx.doi.org/10.5772/intechopen.71903 51

**Figure 14.** CBTA-based memristor emulator (a) decremental structure and (b) incremental structure [36].

**Figure 15.** Generalized mutator structure based on adder and subtractor [37].

Kim and co-workers presented the active circuit element-based memristor emulator [38]. This circuit is also implemented on the bread board using discrete circuit elements that are ADL1116PAL for NMOS transistors, ADL1117PAL for PMOS transistors, TL082 for OPAMP, and AD633 for analog multiplier and passive elements. There are three important tasks to implement memristor emulator: memory effect, frequency-/voltage-dependent characteristics, and nonlinearity. Memory effect and frequency/voltage dependency characteristics are implemented by using a capacitor like many other previous emulator circuits. Nonlinear characteristic of the memristor is obtained using multiplier circuit block. But each used block

**DDCC**

**Multiplier**

**DDCC Summer**

**DDCC**

**Multiplier**

**Memristor**

\* RESISTIVE PORT OF THE MEMRISTOR \*

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* Eflux flux 0 value = {SDT(V(plus,minus))} \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* Echarge charge 0 value = {SDT(I(Emem))} \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\* FOR NONLINEAR DRIFT MODELING \* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \*window function, according to Joglekar

Emem plus aux value = {−I(Emem)\*V(x)\*(Roff-Ron)}

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

Roff aux minus {Roff}

\*Flux computation\*

\*Charge computation\*

\* WINDOW FUNCTIONS

.func f(x,p) = {1-(2\*x-1)^(2\*p)} \*proposed window function ;.func f(x,i,p) = {1-(x-stp(−i))^(2\*p)}

.ENDS memristor

gives rise to extra power dissipation and more complex circuit (**Figure 16**).

Im(t)

Vm(t)

\* HP Memristor SPICE Model \* For Transient Analysis only \* created by Zdenek and Dalibor Biolek

\* Ron, Roff - Resistance in ON/OFF States

50 Memristor and Memristive Neural Networks

\* p - Parameter of the WINDOW-function \* for modeling nonlinear boundary conditions \* x - W/D Ratio, W is the actual width \* of the doped area (from 0 to D)

.SUBCKT memristor Plus Minus PARAMS:

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* \* DIFFERENTIAL EQUATION MODELING \* \*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\* Gx 0 x value = {I(Emem)\*uv\*Ron/D^2\*f(V(x),p)} Cx x 0 1 IC = {(Roff-Rinit)/(Roff-Ron)}

**Table 2.** SPICE codes of modeled memristor [6].

+ Ron = 1 K Roff = 100 K Rinit = 80 K D = 10 N uv = 10F p = 1

\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*\*

\*

Raux x 0 1T

\* Rinit - Resistance at T = 0 \* D - Width of the thin film \* uv - Migration coefficient

**DDCC**

**α**

**Integrator**

**Figure 13.** DDCC-based memristor emulator which is presented by Yener and Kuntman [35].

Another active circuit-based memristor emulators which are shown in **Figure 17** have been presented by Abuelma'atti and Khalifa [39]. Each emulator which is based on current-feedback operational amplifier (CFOA) enjoys operating two different types like decremental and incremental memristor emulators. This situation is a disadvantage of the emulator besides its grounded structure. Each circuit comprises three CFOAs, four resistors, two capacitors, and germanium diode without using an analog multiplier. Nonlinear characteristic is provided by germanium diode. CFOA which is an active element is modeled by AD844 commercially available active devices, and experimental results have been investigated.

**Figure 16.** Voltage-controlled memristor emulator which is presented by Kim and co-workers [38].

Sánchez-López and Aguila-Cuapio proposed the charge-controlled memristor emulator circuit [40]. This circuit which is shown in **Figure 18** is grounded; hence, application areas of the presented memristor emulator are limited in circuit designs. Moreover, it is implemented with discrete circuit element such as AD844 and AD633 besides its disadvantages.

can be adjusted by biasing current of the OTA. The change of the memristance value can be controlled by changing resistor (R) value. Average memristance value can be controlled using OTA-gm value because of the fact that OTA is used as controllable resistor by connecting the negative output terminal to the positive input terminal. In order to demonstrate the performance of OTA-based memristor emulator, both SPICE simulation results and experimental results have been performed. For experimental results, the memristor emulator is built using passive elements and commercially available active devices such as OPA860 for MO-OTA and

+Vdd +Vdd

Z X2

W X1

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Y3

Emulator Circuits and Resistive Switching Parameters of Memristor

Y4

Yesil and co-workers suggested only one DDCC-based memristor emulator which can be operated in high-frequency regions [42]. It is observed from **Figure 20** that the capacitor provides the memory effect and the multiplication of both capacitor and resistor voltages is connected to the Y terminal of the active device. The resistance of memristor emulator circuit decreases when the Z terminal of the DDCC device is chosen as positive terminal (ZP). Consequently, the circuit shows decremental memristor characteristics. For another state, an

R C

VR

P

VP

ZP ZN

ZP,N ZP

**MO-OTA**

**Figure 19.** OT-based memristor emulator which is presented by Babacan and co-workers [41].

VC VN

N

AD633 for the analog multiplier.

IIN VIN

Vm(t)

**Figure 18.** Memristor emulator based on AD844 [40].

Y

Z

W

Ca C1 R1 Rx Rz Rb

X

Babacan and co-workers presented new memristor emulator based on multi-output operational transconductance amplifier (OTA) [41]. This emulator shown in **Figure 19** is a derivative of the DDCC-based memristor emulator [42], but memristance value of this emulator

**Figure 17.** CFOA-based memristor emulator with (a) decremental and (b) incremental characteristic [39].

**Figure 18.** Memristor emulator based on AD844 [40].

Sánchez-López and Aguila-Cuapio proposed the charge-controlled memristor emulator circuit [40]. This circuit which is shown in **Figure 18** is grounded; hence, application areas of the presented memristor emulator are limited in circuit designs. Moreover, it is implemented

Babacan and co-workers presented new memristor emulator based on multi-output operational transconductance amplifier (OTA) [41]. This emulator shown in **Figure 19** is a derivative of the DDCC-based memristor emulator [42], but memristance value of this emulator

with discrete circuit element such as AD844 and AD633 besides its disadvantages.

**Figure 16.** Voltage-controlled memristor emulator which is presented by Kim and co-workers [38].

w

x z y

**(a)**

CFOA2 CFOA3

**(b)**

**Figure 17.** CFOA-based memristor emulator with (a) decremental and (b) incremental characteristic [39].

x z w y

CFOA2 CFOA3

w x z

w x z

y

52 Memristor and Memristive Neural Networks

y

w x z y

Vm

CFOA1

w x z y

Vm

CFOA1

can be adjusted by biasing current of the OTA. The change of the memristance value can be controlled by changing resistor (R) value. Average memristance value can be controlled using OTA-gm value because of the fact that OTA is used as controllable resistor by connecting the negative output terminal to the positive input terminal. In order to demonstrate the performance of OTA-based memristor emulator, both SPICE simulation results and experimental results have been performed. For experimental results, the memristor emulator is built using passive elements and commercially available active devices such as OPA860 for MO-OTA and AD633 for the analog multiplier.

Yesil and co-workers suggested only one DDCC-based memristor emulator which can be operated in high-frequency regions [42]. It is observed from **Figure 20** that the capacitor provides the memory effect and the multiplication of both capacitor and resistor voltages is connected to the Y terminal of the active device. The resistance of memristor emulator circuit decreases when the Z terminal of the DDCC device is chosen as positive terminal (ZP). Consequently, the circuit shows decremental memristor characteristics. For another state, an

**Figure 19.** OT-based memristor emulator which is presented by Babacan and co-workers [41].

**Figure 20.** DDCC-based memristor emulator which is presented by Yesil and co-workers [42].

incremental memristor can be obtained when the Z terminal of DDCC is chosen as negative terminal (ZN). This emulator consists of the third terminal (Vsum) to provide the floating characteristic. Serial connected memristors split applied voltage such as resistor if these memristors carry out a voltage; accordingly, the third terminal is connected to the output terminal. Just as DDCC-based [35], CBTA-based [36], and adder-and-subtractor [37]-based memristor, the performance of [42] is confirmed by SPICE simulations results.

Babacan and Kacar suggested new memristor emulator which does not need any multiplication block as shown in **Figure 23** [45]. This emulator is also fully floating, namely, has two terminals, and input signal can be applied in both terminals. The nonlinearity is provided by transistors which are operated in the subthreshold region. The presented memristor emulator includes single-ended OTA, one grounded capacitor, and two PMOS transistors. Note that the bulk terminals of PMOS transistors are connected to drain terminals of relevant

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The first memristor model which accounts for spike-timing-dependent plasticity (STDP) mechanism is proposed by Li and co-workers [46]. The model which is shown in **Figure 24** consists of five circuit models, and each model depends on the previous model so this model

Babacan and Kacar suggested real-time fully floating memristor emulator which is accounted for synaptic activity [47]. Both memristive and STDP characteristics are obtained from the

is complex and does not have any circuit implementation.

**Figure 23.** Fully floating memristor emulator based on OTA [45].

**Figure 22.** Floating flux-controlled memristor emulator based on CCII [44].

transistors.

Sozen and Cam proposed new floating memristor emulator based on OTA and CCII as shown in **Figure 21** [43]. This emulator is made up of three OTAs, four CCIIs, and seven passive elements. Both SPICE simulation results and experimental results of the presented memristor emulator have been given to confirm its workableness and feasibility. Commercially available active devices CA3080 and AD844 have been utilized instead of OTA and CCII, respectively.

Sánchez-López et al. proposed second-generation current conveyor (CCII)-based flux-controlled memristor emulator which is shown in **Figure 22** [44]. The presented emulator comprises of four CCIIs, a multiplier circuit, five resistors, and single grounded capacitor. AD844 and AD633 are used instead of CCII and analog multiplier in the flux-controlled memristor emulator, respectively. So as to indicate the performance of flux-controlled memristor emulator, both SPICE simulation results and experimental results have been exhibited.

**Figure 21.** OTA- and CCII-based memristor emulator [43].

Emulator Circuits and Resistive Switching Parameters of Memristor http://dx.doi.org/10.5772/intechopen.71903 55

**Figure 22.** Floating flux-controlled memristor emulator based on CCII [44].

incremental memristor can be obtained when the Z terminal of DDCC is chosen as negative terminal (ZN). This emulator consists of the third terminal (Vsum) to provide the floating characteristic. Serial connected memristors split applied voltage such as resistor if these memristors carry out a voltage; accordingly, the third terminal is connected to the output terminal. Just as DDCC-based [35], CBTA-based [36], and adder-and-subtractor [37]-based memristor,

**VR**

**OUTPUT**

**CT RT**

**VC**

Sozen and Cam proposed new floating memristor emulator based on OTA and CCII as shown in **Figure 21** [43]. This emulator is made up of three OTAs, four CCIIs, and seven passive elements. Both SPICE simulation results and experimental results of the presented memristor emulator have been given to confirm its workableness and feasibility. Commercially available active devices CA3080 and AD844 have been utilized instead of OTA and CCII, respectively. Sánchez-López et al. proposed second-generation current conveyor (CCII)-based flux-controlled memristor emulator which is shown in **Figure 22** [44]. The presented emulator comprises of four CCIIs, a multiplier circuit, five resistors, and single grounded capacitor. AD844 and AD633 are used instead of CCII and analog multiplier in the flux-controlled memristor emulator, respectively. So as to indicate the performance of flux-controlled memristor emula-

tor, both SPICE simulation results and experimental results have been exhibited.

the performance of [42] is confirmed by SPICE simulations results.

**VINPUT**

**Figure 21.** OTA- and CCII-based memristor emulator [43].

**Vsum**

54 Memristor and Memristive Neural Networks

**INPUT**

**RS IINPUT**

**X**

**Figure 20.** DDCC-based memristor emulator which is presented by Yesil and co-workers [42].

**Y3 Y2**

**ZN1 ZP,N**

**DDCC**

**Y ZN2 1**

Babacan and Kacar suggested new memristor emulator which does not need any multiplication block as shown in **Figure 23** [45]. This emulator is also fully floating, namely, has two terminals, and input signal can be applied in both terminals. The nonlinearity is provided by transistors which are operated in the subthreshold region. The presented memristor emulator includes single-ended OTA, one grounded capacitor, and two PMOS transistors. Note that the bulk terminals of PMOS transistors are connected to drain terminals of relevant transistors.

The first memristor model which accounts for spike-timing-dependent plasticity (STDP) mechanism is proposed by Li and co-workers [46]. The model which is shown in **Figure 24** consists of five circuit models, and each model depends on the previous model so this model is complex and does not have any circuit implementation.

Babacan and Kacar suggested real-time fully floating memristor emulator which is accounted for synaptic activity [47]. Both memristive and STDP characteristics are obtained from the

**Figure 23.** Fully floating memristor emulator based on OTA [45].

**Figure 24.** Memristor model which is accounted for STDP mechanism [46].

circuit which is shown in **Figure 25**. It is observed from **Figure 25** that fully floating memristor emulator consists of a few numbers of MOS transistors and capacitors without using analog multiplier. Furthermore, STDP is experimentally demonstrated in memristive devices [48–50].

In summary, the comparison of the memristor emulator circuits is according to some important design parameters such as used circuit elements, electronically controllability, power supply value, etc. Each emulator has superior properties among the other emulators. Researchers can prefer appropriate emulator circuit for their memristor-based circuit designs (**Table 3**).

**4.  Comparison of memristor emulator circuits.

[41] *— 1 MO-OTA, 1*

transistors

subtractor

multiplier, 10 transistors

multiplier (AD633)

multiplier (AD633)

*multiplier*

**No. of active comp No. of**

**grounded passive elements**

[36] 1 R 1 CBTA, 1 multiplier 1 R, 1 C Sim. No Grounded ±0.9 V

[39] 2 R, 1 D 3 CFOAs (AD844) 2 R, 2 C Exp. No Grounded NA

[42] 1 R 1 DDCC, 1 multiplier 1 R, 1 C Sim. No Floating ±1.5 [43] 3 R 3 OTAs, 4 CCIIs 3 R, 1 C Both *Yes* Floating ±15

[45] — 1 OTA, 2 transistors 1 C Sim. No Floating ±1 V [47] — 10 transistors 3 C Sim. No Floating —

**Sim./exp Electronically controllable**

4 R, 1 C Sim. No Grounded ±1.25 V

1 D Sim. No Grounded ±1.25 V

1 C Both No Grounded ±10 V

3 R, 1 C Both No Floating ±10 V

*1 R, 1 C* Both *Yes* Grounded *±1.25 V/±5 V*

1 R, 1 C Both No Grounded/

**Floating/ grounded memristor emulator**

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Emulator Circuits and Resistive Switching Parameters of Memristor

floating

**Power supply**

57

±5 V

ing-dependent plasticity mechanism.

In this chapter, memristor devices, models, and emulators have been referred. Memristors have nonlinear characteristics; therefore, high-order mathematical equations should be used to create a mathematical model of the memristor. Active circuit elements are essential to build memristor emulators because of the fact that active elements are versatile and suitable for nonlinear circuit element designs. Nowadays, memristors can exhibit different characteristics when they are fabricated using various materials. Important characteristics such as switching mechanism, synaptic behavior, and operating frequency region are directly depending on the memristor structure. Hence, there is an essential to implement various models and circuits to emulate real memristors. Some emulator circuits exhibit hard-switching characteristics, other emulators exhibit smooth-switching characteristics, or some emulators account for spike-tim-

As a result, researchers are not able to reach real memristor easily so all emulator models and circuits are important to exhibit real memristors. Memristors are ultradense devices

**Figure 25.** Memristor circuit which is accounted for STDP mechanism [47].

**Table 3.** Comparison of memristor emulator circuits.

## **4. Conclusion**

circuit which is shown in **Figure 25**. It is observed from **Figure 25** that fully floating memristor emulator consists of a few numbers of MOS transistors and capacitors without using analog multiplier. Furthermore, STDP is experimentally demonstrated in memristive

**Figure 24.** Memristor model which is accounted for STDP mechanism [46].

**VA1**

T1

T2

**Vtau Cpot**

T3

**Cdep Vtau**

**Figure 25.** Memristor circuit which is accounted for STDP mechanism [47].

T6

**VA2**

T4

T5

In summary, the comparison of the memristor emulator circuits is according to some important design parameters such as used circuit elements, electronically controllability, power supply value, etc. Each emulator has superior properties among the other emulators. Researchers can prefer appropriate emulator circuit for their memristor-based circuit designs (**Table 3**).

T7

**VDD**

TA

TB

**CA**

T8

devices [48–50].

56 Memristor and Memristive Neural Networks

In this chapter, memristor devices, models, and emulators have been referred. Memristors have nonlinear characteristics; therefore, high-order mathematical equations should be used to create a mathematical model of the memristor. Active circuit elements are essential to build memristor emulators because of the fact that active elements are versatile and suitable for nonlinear circuit element designs. Nowadays, memristors can exhibit different characteristics when they are fabricated using various materials. Important characteristics such as switching mechanism, synaptic behavior, and operating frequency region are directly depending on the memristor structure. Hence, there is an essential to implement various models and circuits to emulate real memristors.

As a result, researchers are not able to reach real memristor easily so all emulator models and circuits are important to exhibit real memristors. Memristors are ultradense devices and consume very low energy; that is why it is not only important to emulate real emulator. Researchers need also emulator circuits which have minimum energy consumption and simple structure.

[10] Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. TEAM: Threshold adaptive memristor model. IEEE Transactions on Circuits and Systems I: Regular Papers. 2013;**60**:211-

Emulator Circuits and Resistive Switching Parameters of Memristor

http://dx.doi.org/10.5772/intechopen.71903

59

[11] Adhikari SP, Sah MP, Kim H, Chua LO. Three fingerprints of memristor. IEEE Tran sactions on Circuits and Systems I: Regular Papers. 2013;**60**:3008-3021. DOI: 10.1109/

[12] Hickmott TW. Low-frequency negative resistance in thin anodic oxide films. Journal of

[13] Sawa A. Resistive switching in transition metal oxides. Materials Today. 2008;**11**:28-36.

[14] Chua L. Resistance switching memories are memristors. Applied Physics A: Materials

[15] Lim EW, Ismail R. Conduction mechanism of valence change resistive switching mem-

[16] Strukov DB, Kohlstedt H. Resistive switching phenomena in thin films: Materials, devices, and applications. MRS Bulletin. 2012;**37**:108-114. DOI: 10.1557/mrs.2012.2 [17] Huang CH, Huang JS, Lin SM, Chang WY, He JH, Chueh YL. ZnO1–x nanorod arrays/ ZnO thin film bilayer structure: From homojunction diode and high-performance mem-

ristor to complementary 1D1R application. ACS Nano. 2012 Sep 6;**6**(9):8407-8414

[18] Ielmini D. Resistive switching memories based on metal oxides: Mechanisms, reliability and scaling. Semiconductor Science and Technology. May 2016;**31**(6):063002

[19] Gul F, Efeoglu H. ZnO and ZnO1−x based thin film memristors: The effects of oxygen deficiency and thickness in resistive switching behavior. Ceramics International.

[20] Akinaga H, Shima H. Resistive random access memory (ReRAM) based on metal oxides.

[21] Gul F, Efeoglu H. Bipolar resistive switching and conduction mechanism of an Al/ZnO/ Al-based memristor. Superlattices and Microstructures. 2017 Jan 31;**101**:172-179

[22] Boratto MH, Ramos RA, Congiu M, Graeff CF, Scalvi LV. Memristive behavior of the

[23] He W, Sun H, Zhou Y, Lu K, Xue K, Miao X. Customized binary and multi-level HfO2−xbased memristors tuned by oxidation conditions. Scientific Reports. 2017;**7**:10070

[24] Lian X, Wang M, Rao M, Yan P, Yang JJ, Miao F. Characteristics and transport mechanisms of triple switching regimes of TaOx memristor. Applied Physics Letters. 2017 Apr 24;

interface deposited by sol–gel. Applied Surface Science. 2017 Jul 15;**410**:278-281

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SnO2

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## **Author details**

Abdullah Yesil1 , Fatih Gül2 and Yunus Babacan3 \*

\*Address all correspondence to<EMAIL_ADDRESS>
1 Department of Naval Architecture and Marine Engineering, Bandirma Onyedi Eylul University, Balikesir, Turkey

2 Department of Software Engineering, Gumushane University, Gumushane, Turkey

3 Department of Electrical and Electronic Engineering, Erzincan University, Erzincan, Turkey

## **References**

[10] Kvatinsky S, Friedman EG, Kolodny A, Weiser UC. TEAM: Threshold adaptive memristor model. IEEE Transactions on Circuits and Systems I: Regular Papers. 2013;**60**:211- 221. DOI: 10.1109/TCSI.2012.2215714

and consume very low energy; that is why it is not only important to emulate real emulator. Researchers need also emulator circuits which have minimum energy consumption and sim-

\*

[1] Chua LO. Memristor-the missing circuit element. IEEE Transactions on Circuit Theory.

[2] Chua LO, Kang SM. Memristive devices and systems. Proceedings of the IEEE. 1976;

[3] Strukov DB, Snider GS, Stewart DR, Williams RS. The missing memristor found. Nature.

[4] William RS. How we found the missing Memristor. IEEE Spectrum. 2008;**45**:29-35. DOI:

[5] Wolf SJ, Joglekar YN. The elusive memristor: Properties of basic electrical circuits.

[6] Biolek Z, Biolek D, Biolkova V. Spice model of memristor with nonlinear dopant drift.

[7] Prodromakis T, Peh BP, Papavassiliou C, Toumazou C. A versatile memristor model with nonlinear dopant kinetics. IEEE Transactions on Electron Devices. 2011;**58**:3099-3105.

[8] Lehtonen E, Laiho M. CNN using memristors for neighborhood connections. In: 12th International Workshop on Cellular Nanoscale Networks and Their Applications (CNNA).

[9] Pickett D. Switching dynamics in titanium dioxide memristive devices. Applied Physics.

European Journal of Physics. 2009;**30**:1-24. DOI: 10.1088/0143-0807/30/4/001

1 Department of Naval Architecture and Marine Engineering, Bandirma Onyedi Eylul

2 Department of Software Engineering, Gumushane University, Gumushane, Turkey 3 Department of Electrical and Electronic Engineering, Erzincan University, Erzincan,

and Yunus Babacan3

\*Address all correspondence to<EMAIL_ADDRESS>
1971;**18**:507-519. DOI: 10.1109/TCT.1971.1083337

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ple structure.

**Author details**

Abdullah Yesil1

Turkey

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58 Memristor and Memristive Neural Networks

, Fatih Gül2

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[42] Yesil A, Babacan Y, Kacar F.A new DDCC based memristor emulator circuit and its applications. Microelectronics Journal. 2014;**45**(3):282-287. DOI: 10.1016/j.mejo.2014.01.011 [43] Sözen H, Çam U. Electronically tunable memristor emulator circuit. Analog Integrated Circuits and Signal Processing. 2016;**89**:655-663. DOI: 10.1007/s10470-016-0785-2

[44] Sánchez-López C, Mendoza-López J, Aguila-Cuapio MA, Muñiz-Montero C. A floating analog memristor emulator circuit. IEEE Transactions on Circuits and Systems II:

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[46] Li Q, Serb A, Prodromakis T, Xu H. Memristor SPICE model accounting for synaptic activity dependence. PLoS One. 2015;**10**(3):1-12. DOI: 10.1371/journal.pone.0120506 [47] Babacan Y, Kacar F. Memristor emulator with spike-timing-dependent-plasticity. AEU-International Journal of Electronics and Communications. 2017;**73**:16-22. DOI: 10.1016/j.

[48] Jo SH, Chang T, Ebong I, Bhadviya BB, Mazumder P, et al. Nanoscale memristor device as synapse in neuromorphic systems. Nano Letters. 2010;**10**:1297-1301. DOI: 10.1021/

[49] Berdan R, Xu HY, Li XH, Yu H, Liu YC, et al. Synaptic learning and memory functions achieved using oxygen ion migration/diffusion in an amorphous InGaZnO memristor. Advanced Functional Materials. 2012;**22**:2759-2765. DOI: 10.1002/adfm.201103148 [50] Li Y, Zhong Y, Xu L, Zhang J, Xu X, et al. Ultrafast synaptic events in a chalcogenide

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**Chapter 4**

**Provisional chapter**

**Nanoscale Switching and Degradation of Resistive**

**Random Access Memory Studied by** *In Situ* **Electron**

**Nanoscale Switching and Degradation of Resistive**

DOI: 10.5772/intechopen.69024

**Random Access Memory Studied by** *In Situ* **Electron**

The metal-filament-type resistive random access memories (ReRAMs) with copper were investigated from the point of view of dynamical microstructure evolution in the repetitive switching operations using *in situ* transmission electron microscopy (*in situ* TEM). Through a series of experiments for uncovered solid electrolyte films, stacked devices, and nanofabricated cells, formation and erasure of the copper filaments and deposits were confirmed. The behavior of the filament and deposit depended on the switching condition and history. Based on these *in situ* TEM results, the switching schematics and

**Keywords:** *in situ* transmission electron microscopy, resistive random access memory, ReRAM, conductive bridge random access memory, CBRAM, memristor, conductive

The resistive random access memory (ReRAM) has great potential as a candidate of the nextgeneration nonvolatile memory because of the high-speed operation, the wide memory window, and the high-density storage per cost [1]. In addition, its capability of the multilevel or analogue memory control and its hysteretic nonlinear current-to-voltage (*I–V*) characteristics are suitable for the operation of the artificial neural network hardware using memristors, and this research field is very active especially in these years [2–5]. Because of these advantageous properties, vast numbers of works on ReRAMs have been reported as described in numerous review

> © 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution,

© 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

and reproduction in any medium, provided the original work is properly cited.

Masashi Arita, Atsushi Tsurumaki-Fukuchi and

Masashi Arita, Atsushi Tsurumaki-Fukuchi

Additional information is available at the end of the chapter

the degradation process were discussed.

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69024

**Microscopy**

**Microscopy**

Yasuo Takahashi

**Abstract**

filament

**1. Introduction**

and Yasuo Takahashi

**Provisional chapter**

## **Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by** *In Situ* **Electron Microscopy Random Access Memory Studied by** *In Situ* **Electron Microscopy**

**Nanoscale Switching and Degradation of Resistive**

DOI: 10.5772/intechopen.69024

Masashi Arita, Atsushi Tsurumaki-Fukuchi and Yasuo Takahashi and Yasuo Takahashi Additional information is available at the end of the chapter

Masashi Arita, Atsushi Tsurumaki-Fukuchi

Additional information is available at the end of the chapter

http://dx.doi.org/10.5772/intechopen.69024

#### **Abstract**

The metal-filament-type resistive random access memories (ReRAMs) with copper were investigated from the point of view of dynamical microstructure evolution in the repetitive switching operations using *in situ* transmission electron microscopy (*in situ* TEM). Through a series of experiments for uncovered solid electrolyte films, stacked devices, and nanofabricated cells, formation and erasure of the copper filaments and deposits were confirmed. The behavior of the filament and deposit depended on the switching condition and history. Based on these *in situ* TEM results, the switching schematics and the degradation process were discussed.

**Keywords:** *in situ* transmission electron microscopy, resistive random access memory, ReRAM, conductive bridge random access memory, CBRAM, memristor, conductive filament

## **1. Introduction**

The resistive random access memory (ReRAM) has great potential as a candidate of the nextgeneration nonvolatile memory because of the high-speed operation, the wide memory window, and the high-density storage per cost [1]. In addition, its capability of the multilevel or analogue memory control and its hysteretic nonlinear current-to-voltage (*I–V*) characteristics are suitable for the operation of the artificial neural network hardware using memristors, and this research field is very active especially in these years [2–5]. Because of these advantageous properties, vast numbers of works on ReRAMs have been reported as described in numerous review

© 2016 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. © 2018 The Author(s). Licensee InTech. This chapter is distributed under the terms of the Creative Commons Attribution License (http://creativecommons.org/licenses/by/3.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

articles [6–14]. In these years, highly integrated memory chips have been reported [15–17], and a 16 Gbits chip with 180 MB/s write and 900 MB/s read performance fabricated at the 27 nm node has already been demonstrated using the Cu-based ReRAM [18]. Commercialized or nearly commercialized ReRAM chips have also been reported [19–21]. However, there are still ambiguous issues of the switching and device degradation mechanisms, while basic principles of the ReRAM operations have been discussed using the electrochemistry of solid materials.

To overcome this problem, *in situ* transmission electron microscopy (*in situ* TEM) has been applied on a variety of ReRAMs [12, 14, 23, 24] including CBRAMs [25–29] and other families [30–37], which enable real space observations during ReRAM switching. In some examples, formation and erasure of a Cu or Ag filament were confirmed at quick switching of CBRAM [25, 27]. In another report, the filament growth scheme was categorized in terms of its dependence on the cation mobility and the reduction rate [38]. Comprehension of the filament formation has been much advanced with the sake of *in situ* TEM. On the other hand, *in situ* TEM works on RESET and the multiple operations are still rare, although they are quite important

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*...

http://dx.doi.org/10.5772/intechopen.69024

65

For filling the lack of this knowledge, we have performed *in situ* TEM of SET/RESET and/or multiple switching cycles for an uncovered solid electrolyte, stacked CBRAMs, and nanofabricated CBRAM cells. In this contribution, we will review our work in these years [25, 29, 39–44] and discuss the role of the filament at SET/RESET, the filament growth/erasure mode influenced by the switching history, the CBRAM degradation, and the localization of the fila-

A schematic diagram of the *in situ* TEM system is shown in **Figure 2(a)**. The TEM (10−5 Pa) was equipped with a home-made TEM piezoholder, a piezocontrol system, a current measurement unit, and a CCD camera system (30 frames/s) [45]. The Pt-Ir electrode set in the TEM holder is movable to select the location of the fixed ReRAM sample to be measured (**Figure 2(b)**). The TEM experiments were performed with the beam current density much

The *I–V* measurements were carried out using a source measure unit (SMU). The sweeping rate was typically between 0.3 and 1.6 V/s. The pulse switching operation (pulse width of

**Figure 2.** Schematics of (a) the *in situ* TEM system and (b) the geometry of the sample and the probe.

(typical current density for our high-resolution TEM observations).

for development of reliable ReRAM devices.

**2. Experimental procedure of** *in situ* **TEM**

ment to achieve stable switching.

less than the 170 fA/nm2

The ReRAM operation is performed by simply applying voltage to the device having a capacitor structure with a switching layer between the top and bottom electrodes (TE and BE) as shown in **Figure 1(a)**. The initial state of the device is typically the high-resistance state (HRS). It converts into the low-resistance state (LRS) by applying voltage (SET or "Forming" for the first SET). Subsequent voltage returns the resistance to HRS (RESET) as shown in **Figure 1(b)**. The *I–V* curves are hysteretic with the resistance ratio HRS/LRS typically 102 or larger (**Figure 1(c)**). The operation is called "bipolar" when the voltage polarity for SET and RESET should be reversed, while it is "unipolar" without polarity change. The ReRAM families energetically investigated have been the valence change memory (VCM) composed of a thin oxide layer between two noble electrodes, and the conductive bridging RAM (CBRAM; there are also other naming) composed of a solid electrolyte with an electrochemically active electrode (Cu or Ag) and an inactive electrode (Pt or TiN). In this report, we study some CBRAMs showing the bipolar switching as shown in **Figure 1(b)**.

The CBRAM operation has been explained based on electrical measurements and electronic and electrochemical discussions [8, 10, 14, 22]. Assuming that the TE is Cu, positive voltage to the TE generates Cu cations through oxidation of the electrode at the interface with the solid electrolyte. These cations move along the electric field and are metallized after receiving electrons at the BE interface. A Cu filament is formed there and grows toward the TE. When this filament connects two electrodes, SET switching is completed. Voltage reversal induces the opposite reaction, and the filament is ruptured (RESET). This simple model based on the results of the electrical measurements is plausible, which is an analogical model of electroplating. However, the switching details like filament evolution at SET/RESET and the behavior of the filament during device degradation are hard to be accomplished only with electrical measurements, which are important for usage of ReRAM with guaranteed reliability as the actual electronic device in the circuit.

**Figure 1.** (a) Schematic structure of ReRAM, and typical experimental data of (b) an *I–V* switching curve and (c) a cyclic endurance graph of Cu/WOx /TiN CBRAM cells.

To overcome this problem, *in situ* transmission electron microscopy (*in situ* TEM) has been applied on a variety of ReRAMs [12, 14, 23, 24] including CBRAMs [25–29] and other families [30–37], which enable real space observations during ReRAM switching. In some examples, formation and erasure of a Cu or Ag filament were confirmed at quick switching of CBRAM [25, 27]. In another report, the filament growth scheme was categorized in terms of its dependence on the cation mobility and the reduction rate [38]. Comprehension of the filament formation has been much advanced with the sake of *in situ* TEM. On the other hand, *in situ* TEM works on RESET and the multiple operations are still rare, although they are quite important for development of reliable ReRAM devices.

For filling the lack of this knowledge, we have performed *in situ* TEM of SET/RESET and/or multiple switching cycles for an uncovered solid electrolyte, stacked CBRAMs, and nanofabricated CBRAM cells. In this contribution, we will review our work in these years [25, 29, 39–44] and discuss the role of the filament at SET/RESET, the filament growth/erasure mode influenced by the switching history, the CBRAM degradation, and the localization of the filament to achieve stable switching.

## **2. Experimental procedure of** *in situ* **TEM**

articles [6–14]. In these years, highly integrated memory chips have been reported [15–17], and a 16 Gbits chip with 180 MB/s write and 900 MB/s read performance fabricated at the 27 nm node has already been demonstrated using the Cu-based ReRAM [18]. Commercialized or nearly commercialized ReRAM chips have also been reported [19–21]. However, there are still ambiguous issues of the switching and device degradation mechanisms, while basic principles of the

The ReRAM operation is performed by simply applying voltage to the device having a capacitor structure with a switching layer between the top and bottom electrodes (TE and BE) as shown in **Figure 1(a)**. The initial state of the device is typically the high-resistance state (HRS). It converts into the low-resistance state (LRS) by applying voltage (SET or "Forming" for the first SET). Subsequent voltage returns the resistance to HRS (RESET) as shown in **Figure 1(b)**.

(**Figure 1(c)**). The operation is called "bipolar" when the voltage polarity for SET and RESET should be reversed, while it is "unipolar" without polarity change. The ReRAM families energetically investigated have been the valence change memory (VCM) composed of a thin oxide layer between two noble electrodes, and the conductive bridging RAM (CBRAM; there are also other naming) composed of a solid electrolyte with an electrochemically active electrode (Cu or Ag) and an inactive electrode (Pt or TiN). In this report, we study some CBRAMs show-

The CBRAM operation has been explained based on electrical measurements and electronic and electrochemical discussions [8, 10, 14, 22]. Assuming that the TE is Cu, positive voltage to the TE generates Cu cations through oxidation of the electrode at the interface with the solid electrolyte. These cations move along the electric field and are metallized after receiving electrons at the BE interface. A Cu filament is formed there and grows toward the TE. When this filament connects two electrodes, SET switching is completed. Voltage reversal induces the opposite reaction, and the filament is ruptured (RESET). This simple model based on the results of the electrical measurements is plausible, which is an analogical model of electroplating. However, the switching details like filament evolution at SET/RESET and the behavior of the filament during device degradation are hard to be accomplished only with electrical measurements, which are important for usage of ReRAM with guaranteed reliability as the

**Figure 1.** (a) Schematic structure of ReRAM, and typical experimental data of (b) an *I–V* switching curve and (c) a cyclic

/TiN CBRAM cells.

or larger

ReRAM operations have been discussed using the electrochemistry of solid materials.

The *I–V* curves are hysteretic with the resistance ratio HRS/LRS typically 102

ing the bipolar switching as shown in **Figure 1(b)**.

64 Memristor and Memristive Neural Networks

actual electronic device in the circuit.

endurance graph of Cu/WOx

A schematic diagram of the *in situ* TEM system is shown in **Figure 2(a)**. The TEM (10−5 Pa) was equipped with a home-made TEM piezoholder, a piezocontrol system, a current measurement unit, and a CCD camera system (30 frames/s) [45]. The Pt-Ir electrode set in the TEM holder is movable to select the location of the fixed ReRAM sample to be measured (**Figure 2(b)**). The TEM experiments were performed with the beam current density much less than the 170 fA/nm2 (typical current density for our high-resolution TEM observations).

The *I–V* measurements were carried out using a source measure unit (SMU). The sweeping rate was typically between 0.3 and 1.6 V/s. The pulse switching operation (pulse width of

**Figure 2.** Schematics of (a) the *in situ* TEM system and (b) the geometry of the sample and the probe.

100–500 μs) was occasionally performed. The measurements were done with current compliance of SMU to prevent sample destruction. However, this current compliance was occasionally insufficient because of the parasitic capacitance of the system. In some cases, a MOSFET was installed in the piezoholder to control the compliance current (*I* comp) strictly. To investigate the microstructural change, the TEM images were recorded simultaneously with the current measurements by using a charge coupled device (CCD) video camera. The video contrast was occasionally enhanced nonlinearly to enable a clear identification of the faint contrast. Frame averaging was also used to reduce the noise.

## **3. Filament formation and erasure in chalcogenide containing Cu**

Filament formation and erasure will be demonstrated using GeS containing copper (Cu:GeS) [25, 39]. Though the switching speed and the retention property were not good enough for actual devices, this material is good for easy investigation of the filament evolution. The Cu:GeS thin film was sputter deposited at room temperature (RT) on a wedge-shaped Pt-Ir substrate that acted as the electrode. The film was 8–60 nm thick and was amorphous including Ge nanocrystals. A sharp Pt-Ir probe (the counterelectrode) contacted the Cu:GeS layer, and the *I–V* measurements were performed. The probe was grounded, and the substrate was biased. In this sample, the Cu ion source was Cu:GeS itself. The atomic composition estimated using EDX was Cu:Ge:S = 4:4:2. Though the PtIr/Cu:GeS/PtIr structure was electrochemically symmetric, it showed the asymmetric ReRAM switching (i.e., bipolar switching) because of the shape difference between the substrate and the probe.

properties of the electrodes but to the asymmetry of the electric field caused by the shape difference of the electrodes. Because of the concentrated electric field, Cu ions accumulate at the probe when the substrate is positive. On the other hand, electric flux disperses toward the substrate when the polarity is reversed. Even though Cu is thought to accumulate at the substrate-

**Figure 3.** The switching curve (left panel) and TEM images extracted from a video (right panel) of a Cu:GeS film. The

Nanoscale Switching and Degradation of Resistive Random Access Memory Studied by *In Situ*...

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67

Selected area diffractometry (SAD) and energy dispersive X-ray spectroscopy (EDX) were performed in real time during the operation (but other area than **Figure 3**). In this subsection, the results are briefly summarized. Detailed experimental data are seen in Refs.

The crystal structure of the filament was studied using *in situ* SAD. When a deposit was formed, sharp spots appeared in the patterns. They twinkled like stars. This indicates that nanocrystals were formed, and their orientation frequently changed during the voltage scan. The 1152 frames of the SAD video (35 s) were summed, and Debye rings were identified. The estimated *d*-values were those of Cu reflections. For the elemental analysis, the EDX of the filament was performed with voltage application (+1 V). The Cu peak was greatly enhanced relative to the initial state. The composition estimated using the thin foil approximation was Cu:Ge:S = 7:2:1, while the region containing no filaments showed 4:4:2. The filament was an agglomeration of nanocrystals with a relatively large amount of Cu; probably metallic Cu or

film interface, its density is low for filament formation.

images (a)–(i) correspond to the states marked in the switching curve.

**3.2. SAD and EDX of the conductive filament**

its alloy with either Ge and/or S.

[25, 39].

#### **3.1.** *In situ* **SET and RESET operation**

The *I–V* curve is plotted in the left panel of **Figure 3**, where the current compliance was *I*comp = 500 nA. Clear hysteretic curve was seen as investigated in other studies of solid electrolytes [6, 10, 46, 47]. TEM video images are presented in the right panel of **Figure 3** where each image corresponds to the states (a)–(i) marked in the *I–V* graph. There was no special contrast just before the voltage sweep started (**Figure 3(a)**). The current gradually increased until about 2.5 V, and a deposit-like dark contrast grew from the probe (cathode with this voltage polarity) (**Figure 3(b)–(c)**). Afterward, the current quickly reached *I*comp. This is SET giving LRS. Correspondingly, the deposit was enlarged (**Figure 3(d)–(e)**) and contacted the substrate. In RESET with negative biasing of the substrate, there were sudden jumps at −0.5 and −2 V, which are abnormal with the usual bipolar switching. This is special for the sample without the Cu electrode (thus, amount of Cu is limited) and was neither conventional SET nor RESET [8, 10, 14, 22]. In **Figure 3(f)–(g)**, the deposit was contracted with negative voltage from the substrate (cathode) to the probe (anode). The deposit detached from the substrate in **Figure 3(h)**, and the resistance returned to HRS. This was the RESET switching. At the end of this cycle, the image reverted almost to that of the original (**Figure 3(i)**).

The deposit size and the current corresponded; therefore, this deposit is expected to act as the conductive filament. The polarity dependence may be attributed not to the electrochemical