**Filter Design Solutions for RF systems**

Editors

**Leonardo Pantoli Vincenzo Stornelli**

MDPI • Basel • Beijing • Wuhan • Barcelona • Belgrade • Manchester • Tokyo • Cluj • Tianjin

*Editors* Leonardo Pantoli Universit`a degli Studi dell'Aquila Italy

Vincenzo Stornelli Universit`a degli Studi dell'Aquila Italy

*Editorial Office* MDPI St. Alban-Anlage 66 4052 Basel, Switzerland

This is a reprint of articles from the Special Issue published online in the open access journal *Electronics* (ISSN 2079-9292) (available at: https://www.mdpi.com/journal/electronics/special issues/filter design).

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## **Contents**

#### **Johann Cassar, Andrew Sammut, Nicholas Sammut, Marco Calvi, Sasa Dimitrijevic and Radivoje S. Popovic**

Design and Development of a Reduced Form-Factor High Accuracy Three-Axis Teslameter Reprinted from: *Electronics* **2019**, *8*, 368, doi:10.3390/electronics8030368 ............... **153**

## **About the Editors**

**Leonardo Pantoli** is a Tenure-Track Researcher and Professor with the University of L'Aquila (IT) and Vice-President and founder member of the spin-off SENSing s.r.l. He received a Degree (cum laude and mention) in Electronic Engineering and a Ph.D. in Electrical and Information Engineering from the University of L'Aquila, L'Aquila, Italy, in 2006 and 2010, respectively. In 2007 and 2008, he spent several months with the "Dpto. Ingenieria de Comunicationes—ETS de Ingenieros Industriales y de Telecomunicacion" of the University of Cantabria, Spain, and the "C2S2 Department" of the ´ XLIM Research Institute, Brive La Gaillarde, France. From 2013 to 2017 he was Research Assistant with the University of L'Aquila. From 2017 to 2019 he was Researcher (Law n. 240, 30 December 2010, Art. 24, letter a) with the same University, and in 2017 he obtained a National Scientific Qualification (Law n. 240, 30 December 2010, Art. 16, paragraph 1) to serve as Associate Professor in Italian Universities in the sector 09/E3—Electronics. Since 2019 he has been Tenure-Track Researcher (Law n. 240, 30 December 2010, Art. 24, letter b) with the same University of L'Aquila. His research activities include the development of methods and algorithms for the design of RF, microwave and millimeter wave nonlinear circuits, the stability analysis of circuits in both linear and large-signal regimes, active filter design, and MMIC design for aerospace, wireless communication and imaging applications. He has good experience with GaAs, Si and SiGe technologies.

**Vincenzo Stornelli** was born in Avezzano, Italy. He received the "Laurea" degree (cum laude) in electronic engineering in 2004. In October 2004, he joined the Department of Electronic Engineering, University of L'Aquila, L'Aquila, Italy, where he is involved as an Associate Professor. His research interests include several topics in computational electromagnetics, including microwave antenna analysis for outdoor ultrawideband applications. He serves as a reviewer for several international journals and as an Editor of the Journal of Circuits, Computers and Systems.

## **Preface to "Filter Design Solutions for RF systems"**

Nowadays, technology developments and system integration capabilities are leading to the definition of innovative architectures and modules that require the re-design of many electronic components. Among them, one of the more critical at the system level is filters. In practice, these are difficult to integrate, and in many cases they perform poorly due to the technological limitations of passive elements. Tunability and calibration are often difficult to achieve as well. Different solutions are currently available on the market, and these have already been presented in the literature, depending on the operational frequencies and applications. For instance, modern communication systems have strict performance requirements from electronic devices and components, and these requirements lead to the choice of the technology solutions and component topology to adopt.

Filters can be designed at the electrical, mechanical or electromechanical level; they can be conceived as discrete or distributed components, and among the electrical ones, they can be realized with passive or active circuits. Furthermore, tunability is often a desired characteristic, especially in modern re-configurable systems, but it is usually difficult to achieve. It can be obtained in mechanical filters with screws driven by micro-motors, and in electrical ones by means of voltage-controlled variable components. In any case, it is not trivial to obtain a good tunability and to preserve the same shape factor in the full tuning bandwidth. A further criticism relates to the calibration of these filters, mainly at the industrial level, since the complete characterization of these components is usually obtained with a trial-and-error approach, but this is dependent on the expertise of the technicians. In this regard, automatic test systems optimized for the calibration of the device under test might be very fruitful.

This Special Issue, named "Filter Design Solutions for RF systems" (https://www.mdpi.com/journal/electronics/special issues/filter design) will focus on the state-of-the-art results in the definition and design of filters for low- and high-frequency applications and systems. Aspects related to both the theoretical and experimental research in filter design, CAD modeling and novel technologies and applications, as well as filter fabrication, characterization and testing, are covered.

#### **Leonardo Pantoli , Vincenzo Stornelli**

*Editors*

## *Article* **Low-Current Design of GaAs Active Inductor for Active Filters Applications**

#### **Leonardo Pantoli 1, Vincenzo Stornelli 1,\*, Giorgio Leuzzi 1, Hongjun Li 2 and Zhifu Hu 2**

Received: 30 May 2020; Accepted: 23 July 2020; Published: 31 July 2020

**Abstract:** Active inductors are suitable for MMIC integration, especially for filters applications, and the definition of strategies for an efficient design of these circuits is becoming mandatory. In this work we present design considerations for the reduction of DC current in the case of an active filter design based on the use of active inductors and for high-power handling. As an example of applications, the approach is demonstrated on a two-cell, integrated active filter realized with p-HEMT technology. The filter design is based on high-Q active inductors, whose equivalent inductance and resistance can be tuned by means of varactors. The prototype was realized and tested. It operates between 1800 and 2100 MHz with a 3 dB bandwidth of 30 MHz and a rejection ratio of 30 dB at 30 MHz from the center frequency. This solution allows to obtain a P1 dB compression point of about −8 dBm and a dynamic range of 75 dB considering a bias current of 15 mA per stage.

**Keywords:** active filters; active inductor; MMIC; tunable filters

#### **1. Introduction**

On-chip passive filters are affected by the limited Q-factor of inductors and capacitors, due to ohmic and substrate losses, even on low-loss substrates as Gallium Arsenide. Tunable passive filters are also affected by the limited Q of varactors, normally used for tunability. Moreover, the bandpass of the filter is affected by the combination of constant passive inductance and variable capacitance in the tuning range. Active filters can be realized with several approaches [1–3]; many of them are usually based on active inductors (AIs), that can achieve very low or even negative equivalent resistance, and therefore a high filter Q. The AI can be tuned both in terms of equivalent inductance and of equivalent resistance, yielding constant bandpass with limited losses or positive gain.

In general, active filters usually have limited power handling capabilities also due to the nonlinearities of the active elements, and they are prone to instability due to the negative resistance required for the compensation of the losses of the passive elements in the circuit.

In order to increase the dynamic range, usually a high bias current is required for the active devices. This can lead to higher power consumption that is often unacceptable for integrated circuits and also not allowed at system level. A possible means to reduce the bias current is provided by Class-AB bias, which has already been demonstrated [4]. However, this approach is not always possible or, at least, it experiences some drawbacks depending on the characteristics of the technology process (e.g., the availability of complementary transistors, highly linear active devices).

In this paper, we present a design approach of integrated active inductor and its applications in filters realized in GaAs technology that allows the minimization of bias current, still maintaining Class-A operations that usually ensure high-power handling capability. Concerning the filter AI base design, the proposed approach is based on AIs coupled with shunt capacitors in order to realize an equivalent high-order filter with good performances in terms of shape factor and dynamic range [5–8]. The topology of the AI is such that only a fraction of the bias current is effectively drawn by the active device and it is useful to provide the required negative resistance. In addition, each cell makes use of a single transistor, reducing power consumption and minimizing possible instability concerns.

An example of application is proposed in MMIC technology, potentially tunable in the frequency range between 1.8 to 2.1 GHz, with a tuning bandwidth of about 15%. The −3 dB bandwidth is almost constant and equal to 30 MHz, while the out-of-band rejection is significant thanks to the high shape factor equal to 2.5 for a 30 dB/3 dB bandwidth ratio. The chip has been designed with a standard process provided by HSRI Foundry that implements 0.13 μm GaAs pHEMT devices. Both simulations and on-chip measurement results are presented with a good agreement between them.

Currently; however, no varactor diodes are available in this technology. Therefore, a fixed-capacitor version was implemented, with different values of the capacitors. In fact, our aim is to provide a feasibility proof demonstrating the tunability capability of the filter by replacing the unavailable varactors with fixed capacitors. A version with the varactors will be implemented and fabricated as soon as the technology is available. However, good performances with varactors have already been demonstrated in a hybrid implementation [5], that indicate the possibility of a successful implementation with varactors also in monolithic technology.

Noise figure has not been considered in this design since noise performance requirements were not so strict in the proposed application (as later discussed); therefore, it is quite high. However, noise reduction techniques have been developed and patented [7] that yield a relatively low noise figure. They will be dealt with in a future publication.

In the following, the topology and principle of operation of the active inductor is briefly summarized in Section 2. Section 2 illustrates also the proposed low-current design approach on an active filter, while in Section 3 the MMIC design and measurement results are shown. Finally, the conclusions are drawn (Section 4).

#### **2. The Active Inductor Architecture**

Active filters can be realized by one or more cells, each including an AI-based shunt resonator (Figure 1). Both the shunt capacitor and the AI are tuned in order to maintain both insertion loss and bandpass almost constant across the tuning range. Thus, it is straightforward to notice that the AI is the centerpiece of the filter, as it is also able to control the losses of the cell and; therefore, the overall quality factor of the filter.

**Figure 1.** Topology of a single cell for bandpass active filters.

The traditional structure of the AI is shown in Figure 2a. The input voltage is sampled by a non-inverting transconductance amplifier, that drives a current into the capacitor. The voltage generated in the capacitor is sampled by the inverting transconductance amplifier, that draws an inductive current from the input of the active inductance. The relations between voltages and currents in the active inductor can be better understood in the complex phasor plane (Figure 3). Phases are referred to that of the input voltage *Vin*. The capacitor voltage *VC* has a 90 degrees delay (capacitive delay) with respect to the input voltage and the inverting transconductance introduces a further 180◦ phase shift, so generating an inductive current *Iind* with respect to the input voltage *Vin*. An overall excess phase of the output current with respect to the purely inductive 90◦ phase shift gives an equivalent negative resistance in addition to the equivalent inductance, while an insufficient phase shift gives a positive equivalent resistance. The amplitude of the inductive current with respect to the input voltage determines the value of the equivalent inductance. This amplitude can be changed, for instance, by tuning the value of the transconductance(s).

(**a**)

**Figure 2.** Active inductor architecture: (**a**) Traditional topology, (**b**) improved topology.

**Figure 3.** Phasors of voltages and currents in the AI of Figure 2 in the complex phasor plane. Vin is the input voltage, VC the current across the capacitor (Figure 2a) or at the output of the phase shifting network (Figure 2b), and Iind the current drawn from the inverting transconductance amplifier.3. Low-current design of GaAs active filters based on the proposed AI.

An improved topology of the AI is shown in Figure 2b [5]. The input voltage is sampled at the input of a phase-shifting passive network, then transferred to the input of the inverting transconductance amplifier, that in turn draws the current from the input port. The relations between voltages and currents are approximately the same as in Figure 3; however, some phase shift is also introduced by the inverting transconductance amplifier, given the high operation frequencies. In this improved topology, the amplifier is a fixed-bias, class-A linear amplifier, stable and with fixed gain. The tuning of the phase and amplitude is; therefore, performed by the phase-shifting passive network that includes varactors. This approach allows one to obtain stable and easily tuned AI, and consequently filters with a relatively high gain compression point.

For relatively high-power handling, the current in an AI, conceived with a class-A polarization, may become relatively high. With class-A operation, this requires a high bias current in the active device, where the whole output current flows. A possible means of reducing the DC current is the use of a class-B or class-AB amplifier in the AI [4]. This is certainly a feasible approach that significantly reduces the DC power requirements of the filter, even if it may cause some concerns on intermodulation. However, this approach is not always possible, depending on the characteristics of the active device. For instance, a very sharp pinch-off of the transistor makes the class-B or AB impractical; therefore, a different approach is here proposed and successfully applied to the design of an active filter.

In order to have a high-Q filter, the current at the input of the active inductor must be purely inductive, or nearly so, that is, with a 90 degree phase relation with respect to the voltage across it. The current through a passive inductor has less than 90 degrees with respect to the applied voltage, due to losses. This current can be seen as the vectorial sum of a purely inductive current, and of a purely resistive current in phase with the applied voltage, much smaller in amplitude, due to the losses in the inductor. The compensation of the losses can be obtained by summing another current, opposite in phase with respect to the resistive current and; therefore, equivalent to the current of a negative resistance. This negative resistance current will be therefore much smaller than the total current in the inductor.

A possible topology that implements this approach is shown in Figure 4. The current from the input of the AI flows through a passive inductor (*IL* in Figure 4), because the capacitive current that enters the gate of the active device is relatively small and can be neglected. Then, the main part of this current (*Ipassive* in Figure 4) flows through a relatively large capacitor *Cg*, that has a smaller impedance compared to the passive inductor. Therefore, this current is mainly inductive with respect to the input voltage, but also has a resistive component, due to the losses in the capacitor and in the inductor. From the plot in Figure 5 its resistive nature is apparent from its phase relation to the input voltage.

**Figure 4.** Improved topology of the AI for class-A low bias current.

**Figure 5.** Phasors of voltages and currents in the AI of Figure 3 in the complex plane. *Vin* is the input voltage, *IL* the current through the inductor *L*. *Ipassive* is the current through the capacitor *Cg* and *Iactive* the current drawn from the transistor through the phase-shifting network. Their vectorial sum gives the current through the inductance *IL*.

A smaller part of the current through the passive inductor flows through the phase-shifting network (*Iactive* in Figure 4). This current can have a negative resistance component with respect to the input voltage, because it ultimately comes from the active device. The size of the active device, and the delay introduced by the phase-shifting network must be designed in such a way, that the negative-resistance component of the *Iactive* current compensates the resistive component of the *Ipassive* current through the capacitor. In this way its amplitude is kept to a low value compared to the total current flowing into the AI. Therefore, the current through the active device is minimized, compared to the standard design, where all the current flowing into the AI comes from the active device. As a consequence, bias current and overall power consumption in minimized.

The value of the equivalent inductance is easily tuned by varying the value of the capacitance *Cg*, that can be implemented with a varactor; given the relatively high value of the capacitor, the series *L-Cg* is inductive, because the operating frequency is higher than the resonant frequency of the *LC* series. By changing the value of the capacitor, also the equivalent inductance of the *LC* series is varied. Another varactor can be used also to implement the resonating capacitance *Cres* of the single cell (Figure 1). The simultaneous tuning of the resonating capacitance and of the equivalent inductance

yields a constant bandpass across the tuning frequency range, while the low losses or possibly small negative equivalent resistance of the AI allow to enhance the Q-factor of the filter.

The proposed design approach has some similarities with the negative impedance converter (NIC) approach [9,10]. However, the negative resistance is not designed as a one-port, additive network, but is obtained by suitable phasing of the active inductor loop. Moreover, the very simple AI topology here addressed, based on a single transistor per cell, greatly reduces the current requirements, and makes stability enforcement quite straightforward, ensuring at the same time also high-power handling together with low-power consumption.

When properly implemented, the proposed approach does not cause any reduction in the tuning range or increase in losses with respect to the traditional approach. The main result is the reduction of the current required from the active device, with consequent increase of power handling with the same active device.

It is also important to notice that the proposed design approach is not based on equations but on the optimization of network parameters (currents, voltages, equivalent impedances) at both small and large signals. It suggests a suitable architecture for the realization of active filters based on active inductors. An analytical approach is hard to realize since the filter makes use of AIs that are implemented as closed loop circuits. In addition, it is not useful from a practical point of view also considering that at these frequencies circuits usually make use of distributed elements that are difficult to analytically describe. So the description is strictly related to the network configuration and cannot be generalized.

#### **3. MMIC Design and Test**

Following the above proposed design strategy and making use of the new architecture shown in Figure 4 for the AI, a two-cells example filter has been designed, considering for each cell the same architecture shown in Figure 1. However, the core of the proposed work is the AI design and the filter performance are strictly dependent on the active inductor characteristics. The AI should be applied also to different filter families (e.g., Butterworth, Chebyshev, etc.) [11] that make use of grounded inductors. In this example, the filter has been fabricated on a GaAs technology provided by HSRI, realized and tested for demonstration. The standard PDK from HSRI includes 0.13 μm pHEMT devices that exhibit low noise figure, high gain and high-power density (0.7 W/mm). Varactor diodes are not currently available in this technology; the design will be updated with inclusion of varactors as soon as they are available in the future. The proposed design method can be applied with any technology process and into the millimeter-wave band. It is also important to note that the performances of the example filter have been designed for the replacement of an existing passive filter used as post selector in base station unit for mobile communications, and so could be improved further.

The filter acts exactly as a resonator. Its ease of realization represents its effectiveness. More in detail, *Cres* and *Lres* in Figure 1 define the resonant frequency, that is the center frequency of the filter. The quality factor of the filter depends mainly on the quality factors of the components used in the resonator. *Cdc* and *Ldc* realize series resonators that have decoupling effects and are helpful to tighten the filter bandwidth. The same architecture has been widely described in [11–13]. The filter has been realized replying twice the same cell. Each single cell includes an active inductor that realizes *Lres*. The embedded AI in each cell has been realized with a transistor, whose dimensions are 6 × 25 um, in common source configuration. A self-gate bias architecture has also been implemented in order to limit the number of the bias pads and to reduce the temperature dependence of the filter characteristics. The bias current per transistor is 15 mA, while the total power consumption is 120 mW with a DC voltage supply of 4 V. It is straightforward to notice that the DC power consumption is not very low; but in this example this design choice was not critical. In general, it depends on the desired linearity and dynamic range of the filter, in addition to the available technology. Considering the HAMLA13B Model Handbook from HSRI, in particular the recommended bias voltages and the IV-curves of the active devices, a drain voltage of 4 V and a bias current per transistor of 15 mA are suitable choices,

considering the required power handling and the connected voltage and current swings. Obviously, by using different technology processes and considering different design specs power consumption should be different, but still in the same order of magnitude if you use the same transistor topology. In addition, it may be reduced also changing the number of cells, so allowing to have a lower shape factor of the filter.

In Figure 6, the complete schematic of the single cell is reported, while in Figure 7, the simulated results of the proposed IC design are shown for a fixed tuning state. The insertion loss is about 6 dB, while the 3 dB bandwidth is 30 MHz. It is worth noting that given the active nature of the filter there is no problem in principle to obtain very low attenuation, close to zero, but this was not the aim of this work since the proposed circuit has been designed for the one-to-one replacement of an existing passive post-selector filter, and therefore it had to have the same performances. In that application the insertion loss is not a critical parameter, and has not been improved. However, active filters may reduce the attenuation to zero or even have amplification, at the expense of stability. Typically, an insertion loss of 0.5 dB can be reached with still a good stability margin. The insertion loss is defined properly balancing the negative resistance introduced by the active inductor and losses of passive components of filtering network. So, it is of primary importance the definition of a suitable shape for the input impedance of the AI that allows to provide low losses, out-of-band rejection and tunability versus an external control voltage. As shown in Figure 7, the shape factor achievable with the proposed solution is typical of higher-order passive solutions [11], and the quality factor is approximately equal to 90. It is important to remark that the circuit is stable, as evident from the behavior of the stability factor K and Delta parameter in the same figure [14]. The stability has been checked not only between the external RF I/O pads, but also at transistor level in each stage with the approach proposed in [8]. This is necessary due to the presence of feedback networks (Figure 4) that may generate inner instability problems. In particular, the amplifier in each active inductor is unconditionally stable at all frequencies. Additionally, each cell is unconditionally stable at all frequencies, because the small negative resistance of the active inductor is compensated by the losses of the resonating capacitor and of the connecting lines. Therefore, no oscillations can take place due to reflections between cells. In Figure 8, the simulated output power and attenuation vs. input power are shown for the circuit tuned at 1800 MHz, for a −7 dBm compression point. In Figure 9, the simulated dynamic load lines of the transistor for the same tuning frequency are also shown for several input power levels, demonstrating class-A operations.

**Figure 6.** Schematic of the single cell.

**Figure 7.** Simulated S-parameters and stability parameters of the two-cell filter for a single frequency.

**Figure 8.** Simulated compression of the filter tuned at 1800 MHz.

**Figure 9.** Dynamic load line of the transistor of the filter tuned at 1800 MHz, for different input power levels up to −9 dBm.

At the considered frequencies, better performance can be achieved by using, for instance, SAW devices. However, SAW filters [15] have a limited integration capability and cannot be used at very high frequencies. Additionally, an active chip filter has potential tunability, and smaller size and cost compared to a SAW filter.

A photograph of the fabricated chip is shown in Figure 10a. The chip size is 3 × 1.5 mm, and obviously may be further reduced in next redesign. The two cells are coupled by LC-series elements. The single cell is magnified in Figure 10b, where also some voltages and currents components are reported to better illustrate the proposed approach.

**Figure 10.** The fabricated active filter: (**a**) Photograph of the chip, (**b**) a single cell where the currents of Figure 4 are indicated.

The behavior of the same electrical parameters is shown in the follows in order to prove the design consideration introduced in the previous Section. The main inductance *L* in Figure 4 in this example is replaced by a length of line in each cell. Since standard PDK from HSRI does not include varactors, it has not been possible to use variable capacitors, so in this first run they have been replaced by fixed capacitances, for a first assessment of the design approach and in order to avoid further uncertainties that may be introduced by the nonlinear models of the devices. In fact, our aim is to provide a feasibility proof demonstrating the tunability capability of the filter by replacing the unavailable varactors with fixed capacitors. So, three different chips with different capacitance values of the capacitor *Cg* in Figure 10b have been fabricated, each tuned to a different center frequency. However, the values of the fixed capacitances have been designed with a capacitance ratio of 3:1 for the full tuning bandwidth, making them suitable to be replaced by real varactors. Obviously, there are minor adjustments to be made when the fixed capacitors are replaced by varactors, mainly in term of losses. But we have already verified in different discrete prototypes that the replacement is still possible and does not significantly affect the overall performance of the filter. This is possible thanks to the active nature of the inductors, that can be slightly tuned to compensate the additional losses introduced by varactors.

In Figure 11, comparison between simulated and measured S-parameters for a fixes tuning state is reported demonstrated a good agreement; while measured results of the S-parameters of the three chips, centered at the center frequency and at the two extreme frequencies in the tuning range, are reported in Figure 12. As shown, bandwidth and quality factor are approximately constant at all frequencies. The currents in the active inductor and the corresponding voltages, as indicated in Figure 10b, are plotted in Figures 13–15 vs. time. All quantities refer to the cell tuned at 1800 MHz and at compression level. More in details, in Figure 13 the voltage (*Vcell*) and current (*Icell*) at the input of the cell are shown. It is apparent that the cell has resistive behavior, but very low losses, as indicated by the very low current. In Figure 14 the currents (*Ires*) in the resonating capacitance and in the active inductance (*IL*) are shown, together with the voltage at that node (*Vres*). The sum of the two currents (*Ires* and *IL*) is almost zero since they are in anti-phase, indicating their almost total cancellation. In Figure 15, the inductor current *IL*, the current *Ipassive* through the capacitor *Cg* and the current *Iactive* from the transistor are shown, together with the voltage at the corresponding node. As stated in the previous section, it is apparent that also in this example the main contribution of the inductor current flows through the capacitor *Cg* to ground, and that it is a passive current, as indicated by the phase relation between voltage and current.

**Figure 11.** Comparison between simulated and measured S-parameters at center frequency.

**Figure 12.** Measured S-parameters of the two-cell filter at three frequencies in the tuning range.

**Figure 13.** Simulated voltage and current at the input of the resonating cell (see Figure 10b).

**Figure 14.** Simulated currents *IRES* in the resonating capacitance *CRES* and in the active inductor *IL*, together with the voltage *VRES* at the corresponding node (see Figure 10b).

**Figure 15.** Simulated voltage and current at the input of the resonating cell (see Figure 10b).

A minor contribution comes from the transistor, and it is an active current. Their combination is a slightly active current, corresponding to a negative equivalent resistance, that compensates for the losses in the resonator capacitance (*Cres*). Thus, these real waveforms illustrate and confirm the design approach represented in Figures 4 and 5, that minimizes the RF current in the transistor and; therefore, the bias current requirement for the transistor itself.

The noise figure of the filter has not been measured, since it was not optimized in this design. Simulations give a noise figure in the order of 12 dB. However, reduction techniques [6] should reduce it to approximately 8 dB, approaching the noise figure of a filter with similar losses. Noise reduction techniques will be specifically addressed in a successive design.

It is also important to notice that in the proposed design example of Figure 6, passive components are optimized for the considered frequency and they change accordingly to the operational bandwidth. In any case, as showed in the layout photograph of Figure 10 the area waste due to both the number of components and their values is minimal; in addition some passive components can be also replaced by distributed elements moving at higher frequencies, so further reducing the chip area. In general, the same networks definition may change moving the design to different frequencies, since it strictly depend also on the technology and specs, but still preserving around the same area occupation and realizing the same design principle illustrated in Figure 4. The proposed design is also robust towards tolerances and spread effects. It has been verified also measuring different chips and all of them show similar performance. So the design choices allow to obtain a good reliability making the filter a good candidate to be used in practical applications.

Finally, for completeness, in Table 1 a summary of measurement results is also presented. Both linear and nonlinear characteristics are in good agreement with simulations, showing the feasibility and reliability of the proposed *IC* design. Table 2 shows also a comparison with different literary solutions. From Table 2 it is evident that this work has the highest power consumption, but it is important to notice that the power consumption mainly depends on the selected technology. In the same table, almost all the cited works are realized with CMOS technologies; while just one work makes use of a p-HEMT technology. Obviously, the power consumption of MOS technologies is significantly lower; but on the opposite this kind of technologies cannot provide proficient results at higher frequencies, mainly in term of power handling capability and tunability. The power consumption of the reference makes use of p-HEMT technology around one half (so on the same order of magnitude) of that shown by our work, but it has also a P−1 dB compression point significantly lower. A higher power consumption is usually necessary to obtain better power handling capability. Our work is not strictly focused on performance, but it should be considered as a proof-of-concept and demonstrates the reliability of the proposed design approach. By using HEMT devices, the same design scheme should be successfully applied at also tens of GHz, ensuring good tunability and high 1 dB power compression point.

**Table 1.** Summary of measured results.

#### **4. Conclusions**

We presented an innovative design approach for the minimization of the bias current in the AI-based active filters. The design strategy here proposed allows to obtain a significant reduction of the required DC power, without significantly affecting the power handling capability. The core of the solution here addressed for the first time is the active inductor design. Both the circuitry architecture and the components values were optimized to this purpose and the design choices were described in detail. We also showed how the equivalent inductance and resistance can be tuned by means of variable capacitances. An example of application was also provided: An integrated active filter, centered at three different frequencies, was realized with pHMET technology provided by HSRI Foundry. The filter was optimized between 1800 and 2100 MHz with a narrow and almost constant 3 dB bandwidth of about 30 MHz and a high shape factor, typical of higher order passive filters. This solution allows one to obtain a dynamic range of about 75 dB, minimizing the power consumption. All these characteristics, as well as measured results, makes the proposed solution a good candidate to be used in practical applications and many RF TX/RX systems.

**Author Contributions:** Conceptualization, G.L., V.S. and L.P.; investigation, L.P. and V.S.; data curation, H.L. and Z.H.; supervision, G.L.; validation, H.L.; writing and editing, L.P., G.L. and V.S. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **References**

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## *Article* **Sinusoidal Oscillators Operating at Frequencies Exceeding Unity-Gain Bandwidth of Operational Amplifiers**

#### **Vladimir Ulansky 1,\* and Ahmed Raza 2**

Received: 26 April 2020; Accepted: 17 May 2020; Published: 20 May 2020

**Abstract:** This paper proposes a novel operational amplifier (OPA) voltage-controlled oscillator (VCO) circuits on the basis of impedance converters. The VCO can operate over a frequency range exceeding unity-gain bandwidth due to the location of the tank circuit, not at the output of the OPA, but at the noninverting input. The paper presents the mathematical modeling of oscillated amplitude and start-up conditions. The simulation results confirm the theoretical achievements. The designed and simulated VCO uses an ultra-low noise wideband OPA LMH6629MF, covers a frequency band between 0.830 GHz and 1.429 GHz, and exhibits a maximum in-band total harmonic distortion (THD) of 1.7%. It has a maximum in-band phase noise of −139.3 dBc/Hz at 100 kHz offset frequency and has an outstanding value of a standard figure of merit (FoM) of −198.6 dBc/Hz. The zero-peak amplitude of output voltage is from 3.2 V to 4 V for all generated frequencies at a supply voltage of ±5 V. The fabricated prototype-oscillator based on OPA LMH6624 operates at a frequency of 583.1 MHz with a power level of 0 dBm.

**Keywords:** operational amplifier; voltage-controlled oscillator; unity-gain bandwidth; varactor; total harmonic distortion; phase noise

#### **1. Introduction**

Sinusoidal oscillators are used in almost all systems of receiving and transmitting information, as well as in measuring instruments and systems. One of the most rapidly developing class of sinusoidal oscillators is the class of the voltage-controlled oscillator (VCO). Voltage-controlled oscillators are commonly used in digital frequency synthesizers, which are one of the main subsystems of modern communications systems. The rapid development of modern communications and instrumentation systems has created a high demand for low noise VCOs [1–3]. Modern microwaves sinusoidal oscillators use bipolar junction transistors (BJT), heterojunction bipolar transistors (HBT), a low-noise high-electron-mobility-transistors (HEMT) and pseudomorphic HEMT (pHEMT) as active devices for achieving low phase-noise performance [4–6]. The appearance on the market of a ultra-low-noise, high-speed, broadband operational amplifier (OPA) creates the possibility of their use in the sinusoidal oscillators in the ultra-high frequency range. For example, the LMH6629MF (Texas Instruments) OPA has an input noise voltage of 0.69 nV/ √Hz at the corner frequency of 4 kHz, a slew rate of 1600 V/μs and small-signal −3 dB bandwidth of 900 MHz [7]. Low-noise, high-speed OPA oscillators can offer a practical alternative to transistor oscillators, the performance of which to some extent depends on the variability of the transistor small-signal parameters. The use of a low-noise, high-speed OPA as an active device in the oscillator circuits has some advantages [8,9]. An operational amplifier is an

amplifier with very high input impedance and very low output impedance; it is easy to introduce required positive feedback around the OPA; the oscillator design is simple due to the lack of the bias circuit; the oscillator circuit does not require any adjustment during fabrication.

As is well known [8,10,11], oscillators based on the Colpitts and Hartley topology require a relatively high voltage gain to start-up oscillation. High voltage gains reduce the maximum frequency of oscillation because of the limited gain-bandwidth product of OPA. Besides, the maximum frequency of generated sinusoidal oscillations at the output of the OPA in the Colpitts and Hartley topologies is limited by the ratio of the slew rate to the amplitude of voltage oscillations multiplied by two pi [12]. Thus, with the required voltage amplitude of, say, three volts, and the use of the LMH6629 OPA, the maximum achievable frequency will be less than 85 MHz, which is very far from the microwave frequency range. By simple calculations, we can estimate what should be the slew rate of an OPA to achieve a frequency of 1 GHz with a 3 V amplitude of oscillations. It should be about 19,000 V/μs. Currently, such a slew rate in OPA is unattainable.

The VCO topology proposed in [13] uses the OPA circuit with negative input inductance observed at the noninverting input of the OPA. The disadvantage of this circuit is the use of two resistors, one of which presents the positive feedback circuit, and the second connects the inverting input of the OPA to the ground. These resistors are the source of thermal noise.

In this study, we propose several new VCO topologies that use the idea of a negative impedance converter. However, unlike the well-known studies [14–17], the converter circuit does not include resistors. In contrary to the Colpitts and Hartley oscillators requiring a sufficiently high voltage gain for self-excitation, the proposed oscillator circuits operate with a voltage gain of less than unity; this feature significantly increases the operating frequency, which can exceed the unity-gain bandwidth of the OPA. This particularity of the proposed VCO circuits is due to the location of the tank circuit not at the output of the OPA, but at the noninverting input. Mathematical modeling, simulation, and prototype implementation of the proposed oscillators are given.

#### **2. Architecture of Oscillators**

Figure 1 shows the general VCO electronic diagram. The circuit inside the dashed rectangular is the negative impedance converter. The input impedance observed at the noninverting terminal of the OPA is as follows [16]:

$$Z\_{\rm in} = -Z\_2 \frac{Z\_1}{Z\_0} \tag{1}$$

where *Zin* is the input impedance seen by the noninverting terminal of the OPA, *Z*0 is the impedance between the inverting input and output of the OPA, *Z*1 is the impedance between the noninverting input and output of the OPA, and *Z*2 is the impedance between the inverting terminal of the OPA and ground. The step-by-step derivation of Equation (1) is given in [18] (pp. 349–350).

**Figure 1.** General electronic diagram of voltage-controlled oscillator on the basis of an impedance converter.

In Reference [15–17], one of the impedances *Z*0, *Z*1, or *Z*2 is capacitive, and the other two are resistive.

The presence of significant resistances in the circuit of any oscillator leads to an increase in thermal noise [19]; therefore, in this study, the impedances *Z*0, *Z*1, and *Z*2 are capacitive or inductive.

In the circuit of Figure 1, inductor *L* and two contrary connected varactors *VR*1 and *VR*2 present the tank circuit of the VCO. Resistor *Rdc* isolates the dc control voltage line from the VCO tank.

As can be seen in Figure 1, the tank circuit is connected to the noninverting input of the OPA rather than its output. This feature of the proposed VCO allows extending operation frequency range beyond the unity-gain bandwidth of OPA.

Figure 2 shows VCO circuits based on impedance converters with two inductors and one capacitor. The circuits in Figure 2a,b introduce positive feedback through inductor *L*1 and capacitor *C*1, respectively.

Figure 3 presents VCO circuits on the base of impedance converters with three inductors (a) and two capacitors and one inductor (b).

The oscillator circuits based on impedance converters in which a capacitor is used between the inverting input of the OPA and ground are not considered.

Further, in the article, we will analyze in detail the VCO circuit presented in Figure 2a, and where necessary, we will refer to other VCO configurations.

**Figure 2.** VCO circuits based on impedance converters with two inductors and one capacitor; (**a**) with inductive positive feedback and (**b**) with capacitive positive feedback.

**Figure 3.** Voltage-controlled oscillator (VCO) circuits based on the impedance converter with three inductors (**a**) and one inductor and two capacitors (**b**).

#### **3. Converter Analysis**

Before analyzing the VCO circuit of Figure 2a, let's examine the operation of the converter at frequencies exceeding the OPA bandwidth. Figure 4a shows the test circuit. We assume that the OPA unity-gain bandwidth is 900 MHz, the slew rate is 1600 V/μs, the open-loop gain is 1000 V/V, and the test signal is a sinusoidal voltage with a frequency of 1 GHz and peak amplitude of 2 V.

**Figure 4.** (**a**) Impedance converter testing scheme; (**b**) Input (curve 2) and output (curve 1) voltages of the test circuit.

Figure 4b shows the voltage waveforms at the noninverting input (curve 2) and the output of the OPA (curve 1). As we can see in Figure 4b, the slew rate of the OPA is not sufficient to ensure the shape of the OPA output voltage as that at the noninverting input. Therefore, we observe a triangular voltage waveform at the OPA output (node 1). Moreover, Figure 4b shows that the OPA output voltage lags the input voltage by 90◦. From a comparison of the circuits in Figures 2a and 4a, we can see that instead of the test generator in Figure 4a, a parallel resonant circuit is used in Figure 2a. We will show further that the shape of the voltage curves in the circuit of Figure 2a will be the same as in Figure 4b; however, curve 2 will correspond to the voltage at the output of the VCO.

#### **4. VCO Analysis**

The electronic part of the VCO introduces an alternating current (ac) source *iOPA*(*t*) into the tank circuit, as shown in Figure 5, where *CVCO* and *LVCO* are, respectively, the VCO total capacitance and inductance, and *Rpar* is the equivalent parallel resistance of the tank circuit at the fundamental frequency. Essentially the current *iOPA* (*t*) is the feedback current flowing through inductor *L*1.

**Figure 5.** AC equivalent circuit of the VCO.

The VCO total capacitance includes the capacitance of the contrary connected varactors *VR*1 and *VR*2, the input capacitance of the OPA, and the parasitic capacitance of the printed circuit board (PCB). Therefore,

$$\mathbb{C}\_{VCO}(V\_{dc}) = \frac{\mathbb{C}\_{VR1}(V\_{dc})\mathbb{C}\_{VR2}(V\_{dc})}{\mathbb{C}\_{VR1}(V\_{dc}) + \mathbb{C}\_{VR2}(V\_{dc})} + \mathbb{C}\_{PCB} + \mathbb{C}\_{OPA} \tag{2}$$

As we can see in Equation (2), the VCO capacitance is a function of voltage *Vdc* because the varactor capacitance depends on this voltage. Onwards, inductor *L*1 provides positive shunt–shunt feedback.

By applying the *y*-parameter analysis to the positive feedback network, we find that *y*11 parameter incorporates into the tank circuit. Since *y*11 = 1/*j*ω*funL*1, inductance *L*1 appears in parallel with tank inductance *L*, where ω*fun* is the fundamental angular frequency of oscillation.

Therefore, the total VCO tank circuit inductance is given by

$$L\_{VCO} = L\_1 \| L \tag{3}$$

The current *iOPA*(*t*) flows through the tank circuit. However, only the first harmonic of the current flow creates a significant voltage drop across the tank. The second, third, and subsequent current harmonics create insignificant voltage drops that can be neglected.

We should also note that the tank circuit is connected to the noninverting input of the OPA, where the input impedance is extremely high. Therefore, the OPA does not practically short-out the tank circuit.

This property of the proposed VCO allows obtaining high voltage amplitude of the generated voltage *vout*(*t*), which is not limited by the OPA output. Indeed, we can describe the VCO output voltage by the following equation:

$$w\_{\rm out}(t) = \left| l\_{\rm OPA,1}(V\_{\rm dc}) \right| \mathcal{R}\_{\rm par}(V\_{\rm dc}) \sin \left| \omega\_{\rm fun}(V\_{\rm dc})t + q\_1(V\_{\rm dc}) \right| \tag{4}$$

where |*IOPA*,1(*Vdc*)|, ω*fun*(*Vdc*), and ϕ1(*Vdc*) are, respectively, the amplitude, frequency and initial phase of the first harmonic of current *iOPA*(*t*). Therefore, we can see from (4) that the amplitude of the generated sinusoidal voltage is proportional to |*IOPA*,1| and *Rpar*. In a virtual case of lossless tank circuit, i.e., when *Rpar* → ∞, the amplitude of the output voltage would tend to infinity.

This is a unique property of the proposed OPA oscillator because, for the Colpitts and Hartley OPA oscillators [8], the output amplitude satisfies the following inequality:

$$V\_m \le \frac{4V\_{sat}R\_{par}}{\pi(R\_C + R\_{par})} \tag{5}$$

where *Vsat* is the OPA saturation voltage, and *RC* is the resistance of the load resistor connected between the OPA output and tank circuit.

Since the OPA saturation voltage in (5) is less than the power supply voltage *Vcc*, the oscillation amplitude is also less. Figure 6a illustrates the behavior of the OPA output voltage (curve 1) and the oscillator output voltage (curve 2) for the Colpitts oscillator operating at frequency of 53 MHz with *Vcc* = ±5 V and voltage peak amplitude of 3.7 V. We can also observe in Figure 6a that the shape of the voltage at the output of the OPA, in this particular case, is trapezoidal, which means the slew rate of the OPA is not high enough to ensure a rectangular shape.

**Figure 6.** (**a**) OPA output voltage (curve 1) and oscillator output voltage (curve 2) for the Colpitts VCO; (**b**) OPA output voltage (curve 1) and oscillator output voltage (curve 2) for the proposed VCO.

With a further increase in the frequency of the generated oscillations in the Colpitts oscillator, the voltage shape at the output of the OPA becomes triangular with the amplitude less than *Vsat*. In this case, also, the amplitude of sinusoidal oscillations in the Colpitts oscillator will always be less than the magnitude of triangular oscillations.

A completely different relationship exists between the amplitudes of the voltages at the output of the OPA (node 1) and the oscillator (node 2) in the circuit in Figure 2a. Figure 6b illustrates the behavior of the OPA output voltage (curve 1) at node 1 and the oscillator output voltage (curve 2) at node 2 for the proposed oscillator operating at frequency of 667 MHz with the same OPA, power supply voltages and output peak amplitude of 4 V. As can be seen in Figure 6b, the amplitude of the sinusoidal voltage can be much larger than the voltage amplitude at the output of the OPA (node 1).

Therefore, the proposed VCO can operate at frequencies significantly exceeding the unity-gain bandwidth of OPA.

It should also be noted that by choosing a low-noise OPA, the phase noise of the VCO will be determined mainly by the noise of the tank circuit.

#### **5. Amplitude of Oscillations**

Let us determine the amplitude of the sinusoidal voltage at the output of the VCO (node 2). Assume the voltage at node 1 be triangular, as shown in Figure 6b (curve 1). For the triangle wave, we can describe the voltage at node 1 by the complex exponential Fourier series as follows:

$$v\_{OPA}(t) = 0.5 \sum\_{\mu=-\infty}^{\infty} V\_{\mu} \mathbf{e}^{j\mu\alpha\_{f\mu\alpha}t} \tag{6}$$

where *V*μ is the complex amplitude of the harmonic number μ of voltage *vOPA*(*t*).

The complex amplitude *V*μ can be represented as

$$\mathcal{V}\_{\mu} = |V\_{\mu}| \mathbf{e}^{\mathbf{j}\vartheta\_{\mu}} \tag{7}$$

where |*V*μ| and θμ are the amplitude and phase of the voltage harmonic number μ, respectively. As is well known [20], the amplitude of the voltage harmonic μ for the triangle wave is

$$\left|V\_{\mu}\right| = \frac{8V\_{triangle}}{\pi^2 \mu^2} \sin\frac{\mu\pi}{2} \tag{8}$$

where *Vtriangle* is the amplitude of the triangular voltage at the OPA output.

The feedback current *iOPA*(*t*), which flows from node 1 into the tank circuit, we also present by the complex exponential Fourier series

$$i\_{OPA}(t) = 0.5 \sum\_{\mu=-\infty}^{\infty} I\_{OPA,\mu} \mathbf{e}^{j\mu\omega\_{f\mu\alpha}t} \tag{9}$$

where *IOPA,*μ is the complex amplitude of the current harmonic number μ.

The complex amplitude *IOPA,*μ we write in polar form as follows:

$$I\_{\rm OPA,\mu} = \left| I\_{\rm OPA,\mu} \right| \mathbf{e}^{j\varphi\_{\mu}} \tag{10}$$

where |*IOPA,*μ| and ϕμ are the amplitude and phase of the current harmonic number μ, respectively.

In the ac equivalent circuit of the VCO shown in Figure 5, the feedback inductor *L*1 is in parallel with tank inductor *L*. The feedback current *iOPA*(*t*) flows through inductor *L*1 and tank circuit due to the applied voltage *vOPA*(*t*). Considering the forward transfer admittance of the feedback network *y*12 = −1/*j*ω*funL*1 and parallel connection of inductors *L*1 and *L* in the equivalent circuit of Figure 5, by Ohm's law, we have

$$I\_{\rm OPA, \mu} = -V\_{\mu} / \left( j\omega\_{fum} L\_1 \|L\| \right) = jV\_{\mu} / \left( \omega\_{fum} L\_1 \|L\| \right) \tag{11}$$

By substitution of (7) and (8) into (11), we get

$$I\_{\rm OPA, \mu} = \frac{8V\_{\rm triangle}}{\omega\_{\rm fun}L\_1 || L\pi^2 \mu^2} \sin\frac{\mu\pi}{2} \exp\left[j\left(\theta\_{\mu} + \frac{\pi}{2}\right)\right] \tag{12}$$

The first harmonic of current *iOPA*(*t*) is of interest because for the higher harmonics, the equivalent resistance of the tank circuit is negligible, and they do not create a significant voltage drop. By substitution μ = 1 into (12) gives

$$I\_{\rm OPA,1} = \frac{8V\_{\rm triangle}}{\alpha\_{\rm fun}L\_1 \| L\pi^2} \exp\left[j\left(\theta\_1 + \frac{\pi}{2}\right)\right] \tag{13}$$

We determine the first harmonic of the voltage across the tank by multiplying the complex amplitude *IOPA*,1 and the equivalent resistance of the tank at resonance *Rpar* as follows:

$$V\_{out,1} = \frac{8V\_{triangle}R\_{par}}{\alpha\_{fun}L\_1||L\pi^2} \exp\left[j\left(\theta\_1 + \frac{\pi}{2}\right)\right] \tag{14}$$

By comparing (7) when μ = 1 and (14), we can state that the first harmonic of voltage across the tank leads the first harmonic of triangular voltage at the OPA output by 90◦, which is confirmed by Figure 6b.

From (14) it follows that the amplitude of the voltage across the tank is

$$\left|V\_{out,1}\right| = \frac{8V\_{triangle}R\_{par}}{\omega\_{fun}L\_1 \|L\pi^2} \tag{15}$$

Analyzing (15), we can observe that the amplitude of the VCO output voltage |*Vout*,1| is directly proportional to resistance *Rpar* and inversely proportional to inductance *L*1*L*. As already indicated in the analysis of Equation (4), when using a tank circuit with low losses, the voltage amplitude at the output of the VCO can be significant.

Let us simplify (15) by considering the case when *L*1 >> *L*. In this case, *L*1*L* ≈ *L* and we can write Equation (15) in the following form:

$$\left|V\_{out,1}\right| = \frac{8V\_{triangle}R\_{par}}{\omega\_{fun}L\pi^2} \tag{16}$$

At resonance we have

$$
\omega\_{fum}L = \sqrt{\frac{L}{\mathbb{C}\_{VCO}}} = \rho\tag{17}
$$

where ρ is the tank circuit characteristic impedance.

As is well known [21] (p. 909), the equivalent resistance of the parallel tank at resonance is

$$R\_{\text{par}} = \frac{\rho^2}{r\_s} \tag{18}$$

where *rs* is the series loss resistance of the tank circuit.

Substituting (17) and (18) into (16) gives

$$\left|V\_{out,1}\right| = \frac{8V\_{triangle}
\rho}{r\_s\pi^2} \tag{19}$$

Since the ratio of ρ to *rs* in (19) is equal to the quality factor of the parallel tank circuit (*Q*), then we write (19) in the following form:

$$\left|V\_{out,1}\right| = \frac{8V\_{triangle}Q}{\pi^2} \tag{20}$$

We derived Equation (20) under the condition of an ideal OPA with infinite input resistance, which does not load the tank circuit. However, in the real OPA, the input resistance is not infinite; therefore, in (20), we should use the loaded quality factor. Therefore,

$$\left|V\_{out,1}\right| = \frac{8V\_{triangle}Q\_L}{\pi^2} \tag{21}$$

where *QL* is the quality factor of the loaded VCO tank circuit.

For the VCO shown in Figure 2b, following the same analysis as for the circuit of Figure 2a, we obtain that the amplitude of oscillations is

$$\left|V\_{\rm out,1}\right| = \frac{8V\_{\rm triangle}\omega\nu\_f\mathcal{C}\_{V\rm CO}\|\mathcal{C}\_1\mathcal{R}\_{\rm par}}{\pi^2} = \frac{8V\_{\rm triangle}\omega\nu\_f(\mathcal{C}\_{V\rm CO} + \mathcal{C}\_1)\mathcal{R}\_{\rm par}}{\pi^2} \tag{22}$$

From the analysis of Equation (22), it follows that the capacitance of the positive feedback capacitor *C*1 should be much less than the capacitance *CVCO*; in this case, the capacitance *C*1 will not affect the frequency of generated oscillations.

Given that at the resonant frequency

$$
\omega\_f(\mathbb{C}\_{V\text{CO}} + \mathbb{C}\_1) = \frac{1}{\rho} \tag{23}
$$

We transform Equation (22) as follows:

$$\left|V\_{out,1}\right| = \frac{8V\_{triangle}R\_{par}}{\pi^2 \rho} \tag{24}$$

Considering that *Rpar*/ρ = *Q* in (24), we obtain again Equation (20), which transforms to (21) due to the loaded tank circuit.

The amplitude of the generated sinusoidal voltages in the VCO circuits in Figure 3a,b is also calculated by Equation (21).

#### **6. VCO Start-Up Conditions**

According to the Barkhausen criteria [22], to provide the sustained oscillations, the following conditions must have a place:

$$|A| \| \beta \| = 1 \tag{25}$$

$$
\varphi\_A + \varphi\_\beta = 0 \tag{26}
$$

where |*A*| and |β|, and ϕ*A* and ϕβ are, respectively, the gains and initial phases of impedance converter and feedback network.

As shown in Figure 4b, the voltage gain of the impedance converter is less than unity. We determine the feedback network ratio as follows:

$$\left| \beta \right| = \frac{\left| V\_{out,1} \right|}{\left| V\_1 \right|} \tag{27}$$

where |*V*1| is the voltage amplitude of the first harmonic of triangular voltage at the output of the OPA (node 1).

Substituting (8) at μ = 1 and (21) into (27) gives

$$\left|\beta\right| = Q\_L \tag{28}$$

We can conclude from (25) and (28) that at the steady-state the gain of the impedance converter is

$$|A| = \frac{1}{|\beta|} = \frac{1}{Q\_L} \tag{29}$$

To start the oscillations, the product of |*A*| and |β| is made higher than unity, and when the amplitude reaches a constant value |*Vout,*1|, this product becomes equal to unity.

From relations (28) and (29), it follows that in the proposed oscillators, the feedback network coefficient |β| is more than unity, and the gain of the active network |*A*| is less than unity; this is a unique property because in the Colpitts and Hartley oscillators the opposite is true, i.e., |*A*| > 1 and |β| < 1. Due to this property, the proposed VCO can operate at frequencies significantly exceeding the unity-gain bandwidth of an OPA with sufficiently large oscillation amplitudes.

#### **7. Simulation and Discussion**

The circuit of Figure 2a was simulated with the help of Multisim (ed. 14.1) using SPICE models of a real OPA, varactors, and RF coil to confirm the operation efficiency of the proposed VCO topology. We selected ultra-low noise, high-speed OPA LMH6629MF with −3 dB bandwidth of 900 MHz, slew rate of 1600 V/μs, input voltage noise of 0.69 nV/ √Hz, and power supply voltage ±5 V. We also selected UHF varactors BB215 and a 3.3 nH RF coil. The other component values are as follows: *L*1 = *L*2 = 1 μH, *C* = 100 nF, and *Rdc* = 1 kΩ.

Figure 7 shows the simulated VCO schematic with chosen component values.

**Figure 7.** Simulated VCO schematic with indicated component values.

Figure 8 shows the VCO start-up voltage in the interval 0–720 ns at *V*dc = 1 V (a) and *Vdc* = 11 V (b). As we can see in Figure 8, the oscillations reach the steady-state condition within 500 ns at *Vdc* = 1 V and 50 ns at *Vdc* = 11 V. Thus, the starting time of VCO is speedy.

Figure 9 shows the steady-state voltage waveforms at nodes 1 and 2 when *Vdc* = 1 V (a) and *Vdc* = 11 V (b). As can be seen in Figure 9, the amplitude of the triangular voltage at the output of OPA (node 1) is much less than the amplitude of the sinusoidal voltage at the VCO output (node 2).

From the simulation results shown in Figure 9, it is observed that the THD is 1.5% at *Vdc* = 1 V and 1.7% at *Vdc* = 11 V, which corresponds to −36.5 dB and −35.4 dB, respectively.

Since in the microwave frequency range, the THD value of −30 dB is considered quite well [23] (p. 291), [24], we can argue that the designed VCO is a low-distortion oscillator.

Let us check Equation (21). From Figure 9a it can be observed that *Vtriangle* = 0.37 V and |*Vout,*1| = 3.19 V. To find the loaded quality factor *QL*, we use the property of the parallel tank circuit that the current circulating in the tank circuit *Itank* in *QL* times higher than the current in the general circuit *Ires* [21] (p. 911).

Figure 10a illustrates the location of currents *Itank* and *Ires* in the VCO tank circuit.

**Figure 8.** VCO start-up voltage (**a**) when *Vdc* = 1 V; (**b**) when *Vdc* = 11 V.

**Figure 9.** Steady-state voltages at nodes 1 and 2; (**a**) when *Vdc* = 1 V, (**b**) when *Vdc* = 11 V.

Therefore, the loaded quality factor can be calculated by the following equation:

$$Q\_L = I\_{\text{tank}} / I\_{\text{res}} \tag{30}$$

By simulation, we find that *Itank* = 127 mA and *Ires* = 15 mA. Substituting the currents into (30) gives that *QL* = 8.5. Further, by substitution of *Vtriangle* and *QL* into Equation (21), we calculate that |*Vout,*1| = 2.76 V. So, the relative error of amplitude calculation by Equation (21) is only 13.5%.

Figure 10b shows the VCO tuning characteristics. As we can see in Figure 10b, the VCO operates from 830 MHz to 1.429 GHz, i.e., the tunable band is 599 MHz. Thus, the designed circuit is a wideband VCO, which operates in the frequency range, significantly exceeding the bandwidth of the OPA. Indeed, the bandwidth of the LMH6629MF is 900 MHz, but the highest VCO frequency is 1.429 GHz. Using the equation for maximum signal frequency [12], we can find that with the OPA LMH6629MF in the Colpitts or Hartley VCO, the 4 V amplitude of the sinusoidal voltage corresponds to a frequency that is less than 64 MHz.

**Figure 10.** (**a**) Illustration of external and contour currents at resonance in the VCO tank circuit; (**b**) VCO tuning characteristics.

Thus, by using the proposed VCO topology, we can increase the maximum operating frequency by more than 22 times. Figure 11 shows the simulated power spectrum of the designed VCO at the lowest frequency (a) and the highest frequency (b). As we can see in Figure 11a, only the second and third harmonics contribute to the THD because the fourth and subsequent harmonics attenuated for at least 90 dB compared to the first harmonic. By analyzing Figure 11b, we find that the second and upper harmonics decrease slowly. However, the second and other harmonics attenuated by at least 36 dB.

**Figure 11.** Output power spectrum (**a**) when *Vdc* = 1 V; (**b**) when *Vdc* = 11 V.

One of the essential characteristics of an oscillator operating at microwave frequencies is phase noise. To calculate the phase noise of the simulated VCO, we use the improved Leeson's formula [25] (p. 128)

$$PN(f\_m) = 10\log\left\{\frac{FkT}{2P\_{out}} \left[\frac{f\_{f\_{mu}}^2 f\_c}{f\_m^3 4Q\_L^2} + \left(\frac{f\_{f\_{mu}}}{2Q\_L f\_m}\right)^2 + \left(1 + \frac{f\_c}{f\_m}\right)\right] \right\} \tag{31}$$

where *PN* is the phase noise (dBc/Hz), *F* is the noise figure of the oscillator active device (dB), *k* ≈ 1.38 × 10−23 is the Boltzmann constant (J/K), *T* is the temperature in Kelvin, *Pout* is the oscillator output power, *ffun* is the frequency of oscillations (Hz), *fc* is the 1/*f* corner frequency of active device (Hz), and *fm* is the offset frequency (Hz).

According to Reference [7], the noise figure of OPA LMH6629MF is 8 dB. Figure 11a,b shows that *Pout* = 9 dBm when *Vdc* = 1 V and *Pout* = 11 dBm when *Vdc* = 11 V. Figure 10b indicates that the minimum frequency of oscillations is 830 MHz, and the maximum is 1429 MHz. From Reference [7] (p.15, Figure 28) we find that *fc* = 4 kHz. The loaded quality factor, *QL*, is 8.5 and 2.6 for *Vdc* = 1 V and 11 V, respectively.

Figure 12 shows the dependence of the phase noise versus offset frequency for the VCO shown in Figure 7. As can be seen in Figure 12, the VCO phase noise changes from −153.4 dBc/Hz to −139.3 dBc/Hz at 100 kHz offset frequency when the control voltage varies from 1 V to 11 V. Thus, the maximum in-band phase noise is −139.3 dBc/Hz at *fm* = 100 kHz.

Let us compare the characteristics of the simulated VCO with the best VCO designs operating in the microwave frequency range. The commonly used FoM includes phase noise (*PN*), the ratio of *ffun* to *fm*, and the power consumption (*Pc*) [26].

$$FoM(f\_m) = PN(f\_m)\_{dBc} - 20\log\left(f\_{f\_{um}}/f\_m\right) + 10\log\left(P\_c/1\text{mW}\right) \tag{32}$$

In Equation (32), the second term allows one to compare the phase noise of the oscillators determined at different frequencies and various frequency offsets. The third term in (32) has a positive sign if *Pc* > 1 mW and negative if *Pc* < 1 mW. Thus, the smaller the value of FoM, the higher efficiency of the oscillator.

Table 1 shows a comparison of the designed VCO with microwave oscillators that have been reported in journals and conference proceedings.

**Figure 12.** Phase noise versus offset frequency when *Vdc* = 1 V (curve 1) and *Vdc* = 11 V (curve 2).

**Table 1.** Comparison of designed VCO to other published microwave oscillators.

We can see in Table 1 that the designed VCO has the best FoM among oscillators fabricated in GaN HEMT, SiGe, HEMT, GaAs pHEMT, and SiGe BJT technologies where, in general, power consumption is high enough. Moreover, as shown in Table 1, the designed VCO can even compete with the latest achievements in CMOS VCOs; this is due to low phase noise and in spite of higher power dissipation.

#### **8. Experimental Results**

We fabricated a prototype of oscillator circuit shown in Figure 2b. Figure 13 shows a PCB assembly of the oscillator. We selected OPA LMH6624 (Texas Instruments) with a slew rate of 350 V/μs, gain bandwidth of 1.5 GHz, supply voltage ±5 V, and the following passive components: *L*0 = 200 nH (2 × ELJRFR10), *L* = 8.2 nH (high-quality coil ELJQF8N2), and *C*1 = 2.2 pF (ceramic capacitor C0603C0G1E2R2C030BA). We removed varactors *VR*1 and *VR*2, and inductor *L*2 from the oscillator circuit for simplicity, i.e., *CVR*1 = *CVR*2 = 0, and *L*2 = ∞.

**Figure 13.** Printed circuit board assembly of fabricated oscillator.

A spectrum analyzer USB-SA44B (Keysight Technologies) was used to measure the output power spectrum. We used RF probes P-20A (Auburn Technology) to connect the oscillator output through a capacitive divider to the spectrum analyzer. Figure 14 shows the block diagram of the measurement experiment.

Figure 15 shows the connection between the core elements of the measurement block diagram. The 2-channel power supply HMC8042-G (Rohde and Schwarz) is not shown in Figure 15.

Figure 16 shows the measured power spectrum. As we can see in Figure 16, the frequency of oscillations is 583.1 MHz. The measured power is −43.9 dBm. However, in estimating the real output power, we should consider 21 dB probes attenuation, 10 dB "Attenuation" setting in the spectrum analyzer, and 13 dB insertion loss of the capacitive divider. Thus, the actual power at the output of the fabricated oscillator was around 0 dBm.

**Figure 14.** Block diagram of the measurement experiment.

**Figure 15.** Photograph of the test set-up except for the 2-channel power supply.

**Figure 16.** Measured output power spectrum over 10 MHz span and RBW = 50 kHz.

#### **9. Conclusions**

This article has proposed a new type of VCO based on resistorless negative impedance converter circuits. A distinctive feature of each proposed VCO circuit is that its output is located at the noninverting input of the OPA; this allows us to significantly increase the frequency and amplitude of the generated oscillations. Mathematical modeling of the amplitude of the oscillations and the start-up conditions were carried out. We have shown that, unlike existing oscillators of the Colpitts and Hartley topology, in the proposed VCO, the gain is less than unity, and the feedback coefficient is greater than unity. Therefore, the proposed oscillators can operate at frequencies exceeding the unity-gain bandwidth. The advantage of the proposed VCO circuit is also the fact that the amplitude of the generated sinusoidal oscillations can be dozens of times higher than the magnitude of the nonsinusoidal oscillations at the output of the OPA. The designed and simulated VCO uses ±5 V supply voltage and operates in a wide frequency range from 830 MHz to 1429 MHz showing a maximum in-band THD of 1.7% while the OPA bandwidth is only 900 MHz; the amplitude of oscillations varies from 3.2 V to 4 V. It has a maximum in-band phase noise of −139.3 dBc/Hz at 100 kHz offset frequency and has an outstanding value of FoM of −198.6 dBc/Hz. The conducted comparison of the designed VCO with VCOs in previously published studies concerning standard FoM has shown that the proposed oscillator is about 8–15 dB more efficient than the GaN HEMT, GaN pHEMT, HEMT, and SiGe VCOs and close to the best CMOS VCOs. We have shown that for the same OPA, the operating frequency of the proposed VCO is 22 times higher than that of the Colpitts and Hartley oscillators. The fabricated prototype-oscillator based on OPA LMH6624 operates at a frequency of 583.1 MHz with a power level of 0 dBm.

The proposed OPA VCO circuits are easy to design. They do not require settings during the manufacturing process. These oscillators can be used from high-frequency to the microwave frequency range. Since the power consumption in the proposed VCO is higher than in the CMOS oscillators, the field of application extends to communications, navigation, and radar equipment with an uninterruptible power supply line. As the proposed schemes do not require tuning, they can be useful in conducting laboratory works in the departments of electronics at universities.

Our future work will include mathematical modeling of phase noise in the proposed oscillators using the method of impulse sensitivity functions.

**Author Contributions:** This article presents the collective work of two authors. The authors (A.R. and V.U.) jointly participated in the conceptualization of the problem, development of oscillator circuits and mathematical modeling, numerical calculations, and writing the article. V.U. participated in prototype oscillator design and fabrication. A.R. conducted project administration. All authors have read and agreed to the published version of the manuscript.

**Funding:** This research received no external funding.

**Acknowledgments:** The authors express thanks to engineer A. Kolesnik for technical support.

**Conflicts of Interest:** The authors declare no conflict of interest.

#### **Nomenclature**

#### **Abbreviations**

The following abbreviations exist in the manuscript:

#### **References**

© 2020 by the authors. Licensee MDPI, Basel, Switzerland. This article is an open access article distributed under the terms and conditions of the Creative Commons Attribution (CC BY) license (http://creativecommons.org/licenses/by/4.0/).

## *Article* **Open-Loop Switched-Capacitor Integrator for Low Voltage Applications**

#### **Stefano D'Amico 1,\*, Stefano Marinaci 1, Peter Pridnig 2 and Marco Bresciani 2**

Received: 13 March 2020; Accepted: 28 April 2020; Published: 6 May 2020

**Abstract:** An architecture of a switched-capacitor integrator that includes a charge buffer operating in an open-loop is hereby proposed. As for the switched-capacitor filters, the gain of the proposed integrator, which is given by the input/output capacitor ratio, ensures desensitization to process, voltage, and temperature variations. The proposed circuit is suitable for low voltage supplies. It enables a significant power saving compared to a traditional switched-capacitor integrator. This was demonstrated through an analytical comparison between the proposed integrator and a traditional switched-capacitor integrator. The mathematical results were supported and verified by simulations performed on a circuit prototype designed in 16 nm finFET technology with 0.95 V supply. The proposed switched-capacitor integrator consumes 76 μW, resulting in more than twice the efficiency for the traditional closed-loop switched-capacitor filter as an input voltage equal to 31.25 mV at 7 ns clock period is considered. The comparison of architectures was led among the proposed integrator and the state-of-the-art technology in terms of the figure of merit.

**Keywords:** switched-capacitor filters; low-voltage; finFET

#### **1. Introduction**

Switched-capacitor filters are used in a variety of applications like sensors interfaces [1], audio applications [2], RF front-ends [3], analog-to-digital converters [4], etc. The high accuracy, comparable to the capacitors mismatch and the ease of reprogramming, makes this topology preferable. Such filters require high-performance operational transconductance amplifiers (OTAs). Using modern IC technologies helps to reach high-frequency operation. However, obtaining high DC-gain becomes more challenging for two main reasons: the low supply voltage of the modern IC technologies that limit the number of stackable devices, generally used to obtain high DC-gain OTAs; the reduced length of the transistors that reduces the output resistances and limits the transistor intrinsic gain. On the other hand, the required high-DC gain is obtainable, increasing the number of gain stages of the OTA at the cost of higher power consumption.

In this paper, an open-loop switched-capacitor filter as a building block for the design of a higher-order switched-capacitor filter is presented. Despite its open-loop architecture, the integrator gain depends on the capacitor ratio whose accuracy is related to the capacitor mismatch as it is usually done in closed-loop switched-capacitor integrators. Furthermore, the proposed switched-capacitor integrator enables low voltage operation and relaxes the power requirement compared to the closed-loop counterpart. The paper is organized as follows: Section 2 starts with the analysis from the conventional switched-capacitor integrator used as a benchmark. Section 3 extends the analysis to the proposed open-loop integrator. Section 4 reports the simulation results and Section 5 concludes the paper.

#### **2. The Closed Loop Switched-Capacitor Integrator**

Figure 1 shows the conventional architecture of a switched capacitor integrator.

**Figure 1.** Conventional architecture of a closed-loop switched-capacitor integrator.

The switching scheme of this architecture is defined by two complementary clock phases, φ1 and φ2. During φ1 phase, the input signal, *vs*, is sampled with the input capacitor, *C*1. During φ2 phase the charge collected by *C*1 is transferred to the feedback capacitor *C*2, assuming an ideal virtual ground at the input of the OTA. The overall transfer function in Z-domain is the following

$$\frac{w\_0}{w\_s}(z) = -\frac{C\_1}{C\_2} \cdot \frac{z^{-1}}{1 - z^{-1}}\tag{1}$$

As in many other electronic systems, the feedback in this circuit serves two main functions:

The cost of these desirable features is an excessive OTA requirement.

#### *2.1. Analysis of the Requirements of the Single Stage OTA*

To evaluate the OTA requirements, a single-stage architecture was considered. The linear model of the OTA includes a transconductance *gm* and an output resistance *ro*. Figure 2 reports the linear model of the integrator including the model of the OTA.

**Figure 2.** Equivalent small-signal circuit of the closed-loop switched-capacitor integrator with a single-stage operational transconductance amplifier (OTA).

In a switched-capacitor integrator, the input signal, *vs*, changes suddenly at each clock hit. Therefore, *vs* can be assimilated to a step signal whose a maximum amplitude is equal to *Vi*:

$$w\_s(t) = V\_{\bar{i}} u(t) \tag{2}$$

where *u*(*t*) is the unitary step signal.

The approach followed for this analysis is the following:

The transfer function, *vo vs* , is calculated as follows:

$$\frac{\upsilon\_{0}}{\upsilon\_{s}} = -\frac{C\_{1}}{C\_{2}\left(1 + \frac{1 + \frac{C\_{1}}{C\_{2}}}{\frac{1}{\mathfrak{K}\_{m}\tau\_{0}}}\right)} \cdot \frac{1 - \frac{s\cdot C\_{2}}{\mathfrak{K}\_{m}}}{1 + \frac{s\cdot C\_{1}}{\mathfrak{K}\_{m}\left(1 + \frac{1 + \frac{C\_{1}}{\mathfrak{K}\_{m}\tau\_{0}}}{\mathfrak{K}\_{m}\tau\_{0}}\right)}} = -\frac{C\_{1}}{C\_{2}\left(1 + \frac{1 + \frac{C\_{1}}{C\_{2}}}{\mathfrak{K}\_{m}}\right)} \cdot \frac{1 - \frac{s\cdot C\_{2}}{\mathfrak{K}\_{m}}}{1 + \frac{s\cdot C\_{1}}{\mathfrak{K}\_{m}\left(1 + \frac{1 + \frac{C\_{1}}{C\_{2}}}{\mathfrak{K}\_{m}}\right)}}\tag{3}$$

where *A*0 (=*gm*·*ro*) is the OTA DC-gain. Assuming that both *ro* and *gm* tend to infinite, *vo vs* can be approximate to the ideal value *vo vs* - - - *ideal*:

$$\left. \frac{\upsilon\_o}{\upsilon\_s} \right|\_{\text{ideal}} = \left. \frac{\upsilon\_o}{\upsilon\_s} \right|\_{\text{r}\_o \to \infty} = -\frac{\mathsf{C}\_1}{\mathsf{C}\_2} \tag{4}$$

The function *vs*(*t*) reported in Equation (2) is transformed in s domain and combined with Equation (3), and then the inverse Laplace Transform is evaluated as follows:

$$w\_o(t) = -\frac{C\_1}{C\_2 \left(1 + \frac{1 + \frac{C\_1}{C\_2}}{A\_o}\right)} \cdot V\_i \cdot \left(1 - \frac{\tau\_z + \tau\_p}{\tau\_p} \cdot e^{-\frac{t}{\tau\_p}}\right) \tag{5}$$

where τ*p* and τ*z* are time constants calculated as reciprocal of pole and zero of the transfer function, i.e.,

$$\tau\_p = \frac{C\_1}{g\_m \left(1 + \frac{1 + \frac{C\_1}{C\_2}}{A\_o}\right)} \text{ and } \tau\_z = \frac{C\_2}{g\_m} \tag{6}$$

Assuming *A*0 1 + *C*1 *C*2 , τ*p* can be approximated as follows:

$$
\pi\_p \cong \frac{C\_1}{\mathcal{g}\_m} \tag{7}
$$

The output voltage *vo*(0) at *t* = 0, is defined as:

$$w\_o(0) = -\frac{C\_1}{C\_2 \left(1 + \frac{1 + \frac{C\_1}{C\_2}}{A\_o}\right)} \cdot V\_i \cdot \left(1 - \frac{\tau\_z + \tau\_p}{\tau\_p}\right) \cong V\_i \tag{8}$$

The discontinuity is due to the zero in the transfer function.

#### *2.2. Requirements of the Single Stage OTA*

A finite gain of the OTA, *A*0, and the non-null time is required for settling introduced errors on the output voltage. The OTA finite gain determines an error in a steady state. This error is called static error, ε*stat*:

$$\varepsilon\_{\text{stat}} = \left| \frac{\upsilon\_o}{\upsilon\_s} \right|\_{\text{ideal}} V\_i - \upsilon\_o (t \to \infty) \right| \tag{9}$$

On the base of Equations (4) and (5), the static error, ε*stat*, is calculated as follows:

$$\varepsilon\_{\text{stat}} = \left(\frac{\mathbf{C}\_1}{\mathbf{C}\_2} - \frac{\mathbf{C}\_1}{\mathbf{C}\_2 \left(1 + \frac{\mathbf{1} + \frac{\mathbf{C}\_1}{\mathbf{C}\_2}}{A\_o}\right)}\right) \cdot V\_i = \frac{\frac{\mathbf{C}\_1}{\mathbf{C}\_2} \cdot \frac{1 + \frac{\mathbf{C}\_1}{\mathbf{C}\_2}}{A\_o}}{1 + \frac{1 + \frac{\mathbf{C}\_1}{\mathbf{C}\_2}}{A\_o}} \cdot V\_i \cong \frac{\mathbf{C}\_1}{\mathbf{C}\_2} \cdot \frac{1 + \frac{\mathbf{C}\_1}{\mathbf{C}\_2}}{A\_o} \cdot V\_i \tag{10}$$

where the last approximation is valid as *A*0 1 + *C*1 *C*2 .

The charging process of the feedback capacitance, *C*1, has a finite duration. In the following calculations, it is assumed that the duration of the charging phase is half of the clock period, *TCLK*. Furthermore, an incomplete settling of the output voltage produces an error, which is called dynamic error, ε*dyn*, which is defined as follows:

$$\varepsilon\_{dyn} = \left| v\_o(t \to \infty) - v\_o(\frac{T\_{CLK}}{2}) \right| \tag{11}$$

By using the expression of *vo*(*t*), reported in Equation (5), the dynamic error, ε*dyn*, is calculated as follows:

$$\varepsilon\_{dyn} = \frac{\mathcal{C}\_1}{\mathcal{C}\_2} \cdot V\_i \cdot \frac{1}{1 + \frac{1 + \frac{\mathcal{C}\_1}{\mathcal{C}\_2}}{\mathcal{A}\_\nu}} \cdot \frac{\tau\_z + \tau\_p}{\tau\_p} \cdot e^{-\frac{\mathcal{T}\_{\text{CL}, \text{K}}}{2\tau\_p}} \tag{12}$$

which can be simplified combining Equation (12) with Equations (6) and (7) that:

$$\varepsilon\_{dyn} = \left(1 + \frac{C\_1}{C\_2}\right) \cdot V\_i \cdot \frac{1}{1 + \frac{1 + \frac{C\_1}{C\_2}}{A\_o}} e^{-\frac{T\_{CLK}}{2\sigma\_p}} \tag{13}$$

Figure 3 shows the qualitative behavior of the output voltage. Both static and dynamic errors are highlighted.

**Figure 3.** Output voltage behavior of the closed-loop switched-capacitor integrator in the linear regime.

The overall error, ε*tot*, evalueated on the output voltage, is defined as the difference between the ideal output voltage, *C*2/*C*1·*Vi*, and the output voltage measured at *TCLK*/2:

$$\varepsilon\_{tot} = \left| \frac{\mathbf{C}\_2}{\mathbf{C}\_1} \cdot V\_i - v\_o \left( \frac{T\_{CLK}}{2} \right) \right| = \varepsilon\_{stat} + \varepsilon\_{dyn} \tag{14}$$

As Equation (14) shows, ε*tot* is calculated as the sum of ε*stat* and ε*dyn*.

#### 2.2.1. DC-Gain Requirement of the Single-Stage OTA

The overall error must be less than the required accuracy, ξ, which is a parameter related to the application. According to the definition, both ε*stat* and ε*dyn* must be positive and smaller than the required accuracy, ξ.

To fulfill the DC-gain requirement, the accuracy of the static error, ε*stat*, needs to be addressed as follows:

$$
\varepsilon\_{stat} \prec \xi \tag{15}
$$

Combining Equations (10) and (15), the following is obtained:

$$\frac{C\_1}{C\_2} \cdot \frac{1 + \frac{C\_1}{C\_2}}{A\_o} \cdot V\_i < \xi \tag{16}$$

Then, the following constraint on the DC-gain, *Ao*, is derived:

$$A\_o > \frac{C\_1^2}{C\_2^2} \cdot \frac{V\_i}{\xi} - 1 \cong \frac{C\_1^2}{C\_2^2} \cdot \frac{V\_i}{\xi} \tag{17}$$

Since the DC-gain, *Ao*, undergoes process, voltage and temperature variations, the sensitivity of *Ao*, *S vo*( *TCLK* 2 ) *A*0 , of the output voltage at *t* = *TCLK* 2 , *vo TCLK* 2 , is evaluated from Equation (5) as follows:

$$S\_{A\_0}^{v\_o \left(\frac{T\_{CLK}}{2}\right)} = \frac{A\_0}{v\_o \left(\frac{T\_{CLK}}{2}\right)} \cdot \frac{\partial v\_o \left(\frac{T\_{CLK}}{2}\right)}{\partial A\_0} = A\_0 \cdot \frac{1 + \frac{C\_1}{C\_2}}{\left(A\_0 + \frac{C\_1}{C\_2} + 1\right)^2} \cong \frac{1 + \frac{C\_1}{C\_2}}{A\_0} \tag{18}$$

where last approximation is valid as *A*0 1 + *C*1 *C*2 .

#### 2.2.2. Transconductance Requirement of the Single Stage OTA

A transconductance constrain is determined through the relation between the accuracy specification and the dynamic error, ε*dyn*, i.e.:

$$
\varepsilon\_{dyn} < \xi \tag{19}
$$

Combining Equations (13) and (19), it is obtained:

$$\left(1+\frac{\mathcal{C}\_1}{\mathcal{C}\_2}\right) \cdot V\_{\bar{I}} \frac{1}{1+\frac{\mathcal{C}\_1}{1+\frac{\mathcal{C}\_2}{\mathcal{C}\_2}}} \cdot e^{-\frac{\mathcal{T}\_{\rm CLK}}{2\tau\_p}} \cong \left(1+\frac{\mathcal{C}\_1}{\mathcal{C}\_2}\right) \cdot V\_{\bar{I}} \cdot e^{-\frac{\mathcal{T}\_{\rm CLK}}{2\tau\_p}} < \xi \tag{20}$$

The approximation contained in Equation (20) is justified as it is assumed that *A*0 1 + *C*1 *C*2 . Combining Equations (7) and (20) the following constraint on *gm* is set:

$$\log g\_m > \frac{2 \cdot \mathbb{C}\_1}{T\_{CLK}} \cdot \ln \left( \frac{V\_i}{\xi} \cdot \left( 1 + \frac{\mathbb{C}\_1}{\mathbb{C}\_2} \right) \right) \tag{21}$$

As for the DC-gain, *Ao*, the sensitivity of the output voltage, *S vo*( *TCLK* 2 ) *gm* , at *TCLK* 2 , *vo TCLK* 2 , with respect to *gm* is derived from Equation (5) as follows:

$$S\_{\mathcal{G}\_{m}}^{v\_{0}\left(\frac{T\_{\mathcal{L}\mathcal{L}}}{2}\right)} = \frac{\mathcal{G}\_{m}}{v\_{0}\left(\frac{T\_{\mathcal{L}\mathcal{L}}}{2}\right)} \cdot \frac{\partial v\_{0}\left(\frac{T\_{\mathcal{L}\mathcal{L}}}{2}\right)}{\partial g\_{m}} = \frac{T\_{\mathcal{L}\mathcal{L}K}}{2\cdot\tau\_{p}} \cdot \frac{\left(1 + \frac{2\tau\_{z}}{T\_{\mathcal{L}\mathcal{L}}K} + \frac{C\_{2}}{C\_{1}}\right)e^{-\frac{T\_{\mathcal{L}\mathcal{L}K}}{2\tau\_{p}}}}{1 - \left(1 + \frac{C\_{2}}{C\_{1}}\right)e^{\frac{-T\_{\mathcal{L}\mathcal{L}K}}{2\tau\_{p}}}} \cong \frac{T\_{\mathcal{L}\mathcal{L}K}}{2\cdot\tau\_{p}} \cdot \left(1 + \frac{C\_{2}}{C\_{1}}\right)e^{\frac{-T\_{\mathcal{L}\mathcal{L}K}}{2\tau\_{p}}}\tag{22}$$

where the last approximation is valid as 1 + *C*2 *C*1 ·*e* −*TCLK* 2τ*p* 1 and τ*z TCLK* 2 .

#### *2.3. Circuit Implementation of the Single Stage OTA*

A common circuit solution for the OTA is represented by the telescopic Cascode OTA, shown in Figure 4 [5,6]. As the DC-gain requirement is satisfied and the output signal swing is sufficient, the telescopic Cascode OTA reported in Figure 2 remains the most efficient and simplest OTA solution. Therefore, it was used as a benchmark in this paper.

**Figure 4.** Telescopic Cascode OTA.

The overdrive voltage of *M*1-*M*2 input transistors is limited by the available supply voltage, *Vdd*, and the NMOS transistor threshold, *VTHN*. Assuming a common mode, *Vcm*, equal to *Vdd*/2, by applying Kirchoff's voltage law we obtain:

$$V\_{cm} = \frac{V\_{dd}}{2} = V\_{GS1} + V\_{DS0} \tag{23}$$

where *VGS*1 is the gate-source voltage of *M*1-*M*2 input transistors, and *VDS*0 is the drain-source voltage of the *M*0 bias transistor.

The common mode, *Vcm*, must assure that *M*1-*M*2 and the *M*0 transistors work in the saturation region. Therefore, assuming that all the overdrives of *M*1-*M*2 and *M*0 transistors are equal to *Vov*, from Equation (23) we derive:

$$\frac{V\_{dd}}{2} > V\_{THN} + 2 \cdot V\_{\text{av}} \tag{24}$$

Thus:

$$V\_{\rm UV} < \frac{\frac{V\_{\rm dd}}{2} - V\_{\rm THIN}}{2} \tag{25}$$

As seen in Equation (25), there is a strict limitation to the design of the overdrive of the input transistors at low supply voltage, which is typical of the modern CMOS IC technologies. For example, in finFET 16 nm technology, *Vdd* is 0.95 V, and *VTHN* is 0.275 V, therefore *Vov* must be less than 100 mV.

#### *2.4. Small Signal Analysis of the Single-Stage OTA*

The transconductance *gm* of the linear model of Figure 2 corresponds to the transconductance *gm*1 of *M*1-*M*2 input transistors. The bias current, *IB*, of the OTA is defined by the settling requirements, which mainly depends on *M*1-*M*2 input transistors.

The output resistance *ro* of the linear model of Figure 2 is calculated as follows:

$$r\_o = g\_{m3} \cdot r\_{o3} \cdot r\_{o1} || g\_{m5} \cdot r\_{o5} \cdot r\_{o7} \cong \frac{1}{2} g\_{m3} \cdot r\_{o3} \cdot r\_{o1} \tag{26}$$

where *gm*3 and *gm*5 are the transconductances of *M*3 and *M*5 transistors, respectively, and *ro*1, *ro*3, and *ro*5 are the output resistances of *M*1, *M*2, and *M*3 transistors, respectively. The last approximation in Equation (24) is valid assuming *gm*3 *gm*5, *ro*3 *ro*5, and *ro*1 *ro*7. In practice, the output resistance of *M*1-*M*2 transistors, *ro*1, is boosted by the intrinsic gain of transistor *M*3, *gm*3·*ro*3.

The voltage gain, *A*0, can be calculated as follows:

$$A\_0 = \mathcal{g}\_{m1} \cdot r\_o \cong \frac{1}{2} \mathcal{g}\_{m1} \cdot \mathcal{g}\_{m3} \cdot r\_{o3} \cdot r\_{o1} \tag{27}$$

Rearranging Equation (27), we obtain:

$$A\_0 \cong 2 \cdot \frac{V\_{A3} \cdot V\_{A1}}{V\_{\text{ov3}} \cdot V\_{\text{ov1}}} \tag{28}$$

where *VA*3, *VA*1, *Vov*3, and *Vov*1 are the early and the overdrive voltages of *M*3 and *M*1 transistors, respectively. As derived in Equation (28), the margins to increase the voltage gain *Ao* are limited. A possibility to increment the voltage gain consists of reducing *Vov*3 and *Vov*1. *M*3 and *M*1 transistors are then pushed to work in the subthreshold region, where the transconductance depends only on the bias current, while the transistor overdrives approach their inferior limit of about 50 mV [7]. Therefore, *Vov*1 and *Vov*3 have a strict range of variability between 50 mV and 100 mV. *VA*3 and *VA*1 can be increased by augmenting the length of *M*3 and *M*1. This solution degrades the frequency performance of the OTA since larger transistors introduce bigger parasitic capacitances. Moreover, every IC fabrication process has an intrinsic limit to the maximum allowable transistor length, which is lower and lower as the technology is scaled. For example, in FinFET 16 nm, the maximum allowable transistor length is 240 nm.

If the DC-gain requirement is not reachable by the telescopic Cascode OTA, it is necessary to modify the OTA architecture. An increment of *ro* and, consequently, *Ao* is obtained by using a regulated Cascode OTA [8] or adding an output stage [9]. Both previous solutions imply a significant increase in power consumption. It is also possible to increase the gain by augmenting the number of stacked transistors. At low voltage supply, the last solution is not practicable because of the further reduction of the output signal swing.

#### *2.5. Slew-Rate (SR) Analysis of the Single-Stage OTA*

Due to the finite bias current, *IB*, the OTA goes into a slew-rate regime at the beginning of the charging process.

According to Equation (5), the maximum rate of variation of the output voltage is obtained at *t* = 0 s. -

$$\left|\frac{dv\_o(t)}{dt}\right|\_{\text{max}} = \frac{C\_1}{C\_2\left(1 + \frac{1 + \frac{C\_1}{C\_2}}{A\_o}\right)} \cdot V\_{SRi,\text{max}} \cdot \frac{\tau\_z + \tau\_p}{\tau\_p^2} = \frac{V\_{SRo,\text{max}}}{\tau\_p} \tag{29}$$

*Electronics* **2020**, *9*, 762

where *VSRi,max* is the maximum amplitude of the input voltage step that keeps the OTA in the linear region. The corresponding output voltage in steady state is given by *VSRo,max*, which is calculated as follows:

$$V\_{SRo,max} = \frac{C\_1}{C\_2 \left(1 + \frac{\frac{C\_1}{C\_2}}{A\_o}\right)} \cdot \left(1 + \frac{C\_2}{C\_1}\right) \cdot V\_{SRi,max} \triangleq \left(1 + \frac{C\_1}{C\_2}\right) \cdot V\_{SRi,max} \tag{30}$$

where the last approximation is valid as *A*0 >> 1 + *C*1/*C*2. In a single-stage OTA, the slew-rate depends on the bias current *IB* and the feedback capacitance *C*2, i.e.:

$$SR = \frac{I\_B}{\mathcal{C}\_2} = \frac{I\_B \cdot \mathcal{g}\_{m1}}{\mathcal{C}\_2 \cdot \mathcal{g}\_{m1}} = \frac{V\_{ov1}}{\tau\_z} \tag{31}$$

where *gm*1 and *Vov*1 are the transconductance and the overdrive of the *M*1-*M*2 input transistors, respectively. Matching the *SR* formula in Equation (31) to the maximum rate of variation of the output voltage reported in Equation (29), the *VSRo,max* calculation is obtained:

$$V\_{SRo,max} = V\_{ov1} \cdot \frac{\tau\_p}{\tau\_z} \cong V\_{ov1} \cdot \frac{C\_1}{C\_2} \tag{32}$$

Due to its differential structure, the OTA starts slewing as the input differential voltage step, *Vi*, overcomes 2·*VSRi,max*. The value of *VSRi,max* is calculated by combining Equations (30) and (32):

$$V\_{SRi, \max} \approx \frac{1}{\left(1 + \frac{C\_1}{C\_2}\right)} \cdot V\_{SRo, \max} = \frac{V\_{\text{ov1}}}{\left(1 + \frac{C\_2}{C\_1}\right)}\tag{33}$$

The OTA slews until the output voltage reaches the value −*C*1 *C*2 *Vi* + 2*VSRo*,*max*:

$$V\_i - \frac{2 \cdot V\_{SRo, \text{max}}}{\tau\_p} t|\_{t=\tau\_s} = -\frac{C\_1}{C\_2} V\_i + 2 \cdot V\_{SRo, \text{max}} \tag{34}$$

where the starting value of *Vi* depends on the fact that, at *t* = 0 s, the capacitances of the integrator behave like short circuits, transferring the input voltage directly to the output.

From the previous equation, it is possible to calculate the slewing time of the OTA, τ*s*:

$$\tau\_{\rm s} = \tau\_p \cdot \left( \left( 1 + \frac{C\_1}{C\_2} \right) \cdot \frac{V\_i}{2 \cdot V\_{SRo,\max}} - 1 \right) = \tau\_p \cdot \left( \frac{V\_i}{2 \cdot V\_{SRi,\max}} - 1 \right) \tag{35}$$

During τ*s*, the OTA output voltage evolves according to the linear law. Considering the slew-rate, the equation of the differential output voltage, *vod*(*t*), is then calculated as follows:

$$\begin{cases} \begin{aligned} v\_{ad}(t) &= V\_i - \frac{2 \cdot V\_{SR,\max}}{\tau\_p} \cdot t \qquad \text{for } 0 < t < \tau\_s\\ v\_{ad}(t) &= -\frac{C\_1}{C\_2 \left(1 + \frac{C\_1}{A\_\psi}\right)} V\_i + 2 \cdot V\_{SRo,\max} \cdot t^{-\frac{l-\tau\_d}{\tau\_p}} \triangleq -\frac{C\_1}{C\_2} \cdot V\_i + 2 \cdot V\_{SRo,\max} \varepsilon^{-\frac{l-\tau\_d}{\tau\_p}} \end{aligned} & \begin{aligned} \varepsilon \gets \tau\_s\\ v\_{ad}(t) &= -\frac{C\_1}{C\_2} \left(1 + \frac{C\_1}{A\_\psi}\right) \end{aligned} \tag{36}$$

Figure 5 shows the step response of the closed loop switched capacitor integrator including the slewing period.

**Figure 5.** Output voltage behavior of the closed-loop switched-capacitor integrator including the slewing period.

#### *2.6. Signal to Noise (SNR) Calculations of the Closed-Loop Switched-Capacitor Integrator*

The telescopic Cascode OTA suffers from a reduced output swing. Indeed, both single-ended output voltages must guarantee that the Cascode transistors (*M*3-*M*4 and *M*5-*M*6) work in a saturation region even under the signal swing. The main limitation is the negative output swing since three transistors are stacked between the ground and the output nodes, while only two transistors are stacked between *Vdd* and the output nodes. Focusing the analysis on a single branch, *Vo*+ must satisfy the following inequation to guarantee that *M*3 transistors operate in saturation region:

$$V\_{o+} > V\_{DS,sat3} + V\_{S3} = V\_{ov} + V\_{S3} \tag{37}$$

where *VS*3 and *VDS*,*sat*3 are the source and the saturation voltages of *M*3 transistor, respectively. It is assumed that *Vds*,*sat*3 is equal to *Vov*. The bias voltage *Vb*1 is chosen to make *M*1 transistor operating in saturation, i.e.:

$$V\_{DS1} = V\_{S3} - V\_{S1} > V\_{DS,sat1} = V\_{ov} \tag{38}$$

where *VDS*1, *VS*1, and *VDS,sat*1 are the drain-source, the source, and the saturation voltages of *M*1 transistor, respectively. In this case, it is assumed that *Vds,sat*1 is equal to *Vov*. *VS*1 is derived from the input transistor common mode, *Vcm*, by dropping the gate-drain voltage of the *M*1 transistors, *VGS*1, i.e.:

$$V\_{S1} = V\_{cm} - V\_{GS1} = V\_{cm} - V\_{TH} - V\_{ov} \tag{39}$$

Combining Equations (38) and (39) we obtain the minimum source voltage of *M*3 transistor, *VS*3,min:

$$V\_{S3} > V\_{S1} + V\_{ov} = V\_{S3\,\mu\text{in}} \tag{40}$$

By replacing *VS*3 in Equation (37) with the value of *VS*3,*min* calculated in Equation (40), the minimum value of *Vo*+, *Vo*+*,min*, is obtained:

$$V\_{o+} > V\_{\text{av}} + V\_{S3} = V\_{\text{cW}} - V\_{\text{THR}} = V\_{o+,\text{min}}\tag{41}$$

As the output voltage starts swinging from the common-mode voltage, *Vcm*, down to *Vo*+*,min*, it is possible to calculate the maximum output voltage swing, *Vswing*:

$$V\_{s\text{wing}} = 2 \cdot (V\_{cm} - V\_{o + \,\mu\text{in}}) = 2 \cdot V\_{T\text{Hill}} \tag{42}$$

where the 2 factor is due to the differential architecture.

*Electronics* **2020**, *9*, 762

The thermal noise due to the switches around *C*1 is calculated as 2· *K*·*T C*1 , where the coefficient 2 takes into account both the sampling (φ1) and the integration phase (φ2). Assuming that the thermal noise 2· *K*·*T C*1 is dominant, from Equation (42), the signal to noise ratio of the overall closed-loop switched-capacitor integrator, *SNRCL*, is calculated as follows:

$$\text{SNR}\_{\text{CL}} = \frac{1}{2} \cdot \frac{V\_{\text{swing}}^2}{\overline{\upsilon\_{o,n}^2}} = \frac{1}{2} \cdot \frac{4 \cdot V\_{THN}^2}{2 \cdot \frac{K \cdot T}{C\_1} \cdot \left(\frac{C\_1}{C\_2}\right)^2} = \frac{V\_{THN}^2 \cdot C\_2^2}{K \cdot T \cdot C\_1} \tag{43}$$

where *v*2 *n*,*o* is the total output noise, as a result of the thermal noise contribution due to the *C*1 switched-capacitor multiplied by the square of the integrator gain *C*1 *C*2 2 , furthermore, the 1 2 factor takes into account that the input signal is a sinusoid.

#### *2.7. Power Consumption Requirements*

Regarding the telescopic Cascode shown in Figure 4, the power consumption is given by the product of the supply voltage, *Vdd*, and the bias current *IB*:

$$P\_{w,tot} = V\_{dd} \cdot I\_B \tag{44}$$

Assuming dominant the thermal noise of *C*1, the power consumption of the switched-capacitor integrator is determined by the settling time requirement. In fact, as the input transistor overdrive, *Vov1,* is bonded to considerations on the DC-point at low voltage supply, the constraint on the input transistor transconductance, *gm*1, expressed by in Equation (21), determines the minimum required bias current *IB,min*:

$$I\_{\rm B,min} = \frac{2 \cdot C\_1}{T\_{CLK}} \cdot V\_{ov1} \cdot \ln\left(\frac{V\_i}{\xi} \cdot \left(1 + \frac{C\_1}{C\_2}\right)\right) \tag{45}$$

Therefore, the minimum power consumption, *Pw,min*, is obtained as follows:

$$P\_{w\rho,\min} = V\_{dd} \cdot I\_{B\rho,\min} = V\_{dd} \cdot \frac{2 \cdot \mathbb{C}\_1}{T\_{CLK}} \cdot V\_{w1} \cdot \ln\left(\frac{V\_i}{\xi} \cdot \left(1 + \frac{\mathbb{C}\_1}{\mathbb{C}\_2}\right)\right) \tag{46}$$

As the OTA starts slewing, the minimum bias current, *IB,min*, is determined by taking into account a different calculation for the dynamic error, ε*dyn*. Indeed, considering Equation (36) that assumes the slewing of the OTA, the differential output voltage at *t* = *TCLK* 2 is calculated as follows:

$$w\_{od}\left(\frac{T\_{CLK}}{2}\right) \cong -\frac{C\_1}{C\_2} \cdot V\_i + 2 \cdot V\_{SRo,max} \cdot e^{-\frac{\frac{T\_{CLK}}{2} - \tau\_s}{\tau p}}\tag{47}$$

The dynamic error, ε*dyn*, is, then, calculated as follows:

$$\varepsilon\_{dyn} = \left| \upsilon\_{od}(t \to \infty) - \upsilon\_o(\frac{T\_{CLK}}{2}) \right| = 2 \cdot V\_{SRo,max} e^{-\frac{\frac{T\_{CLK}}{2} - \upsilon\_o}{\tau\_p}} \tag{48}$$

Since ε*dyn* must be less than the required accuracy, ξ, as reported in Equation (19), we obtain:

$$
\tau\_p < \frac{\frac{T\_{CLK}}{2} - \tau\_s}{\ln\left(\frac{2V\_{SRo,\text{max}}}{\xi}\right)}\tag{49}
$$

Moreover, the minimum bias current *IB,min* is evaluated considering τ*p* reported in Equation (7), the transconductance of the input transistors, *gm*1, determined as *IB*,*min Vov*1 , the formula of the slewing

time, τ*s*, in Equation (35), and the previous equation. As a result the minimum bias current *IB,min*, is calculated as follows:

$$I\_{B,\min} = \frac{2 \cdot V\_{ov1} \cdot C\_1}{T\_{CLK}} \cdot \left( \ln \left( \frac{2 \cdot V\_{SRo,\max}}{\xi} \right) + \frac{V\_i}{2 \cdot V\_{SRi,\max}} - 1 \right) \tag{50}$$

The minimum power consumption, *Pw,min*, is derived from the last equation as follows:

$$P\_{w,min} = V\_{dd'} I\_{B,min} = \frac{2 \cdot V\_{ov1} \cdot V\_{dd'} \cdot C\_1}{T\_{CLK}} \cdot \left( \ln \left( \frac{2 \cdot V\_{SRo,max}}{\xi} \right) + \frac{V\_i}{2 \cdot V\_{SRi,max}} - 1 \right) \tag{51}$$

#### **3. Proposed Open-Loop Integrator**

As an alternative solution, an open-loop switched-capacitor integrator is presented (Figure 6).

**Figure 6.** Schematic of the proposed open-loop switched-capacitor integrator.

The active element is an OTA, with a low input impedance, which is called charge buffer. Once the input capacitance, *C*1, is connected to the charge buffer input, it is discharged and its charge is transferred to the output capacitance *C*2. The proposed open-loop switched-capacitor integrator does not include two input nodes with high and low impedances, unlike the switched-capacitor integrator based on a current conveyor [10,11], but only low impedance input nodes. Therefore, the voltage buffer used at the input in the conveyor integrators is eliminated. These simplifications help to get a more efficient circuit implementation.

According to the operation mode aforementioned, *C*1 is connected to the inverting input terminal, it is possible to write:

$$Q\_1(n-1) = -Q\_2(n)\tag{52}$$

where *Q*1(*n*−1) and *Q*2(*n*) are the charges stored in *C*1 and *C*2 capacitances, at *n* − 1 and *n* time steps, respectively. From Equation (52), it is obtained:

$$\mathbf{C}\_1 \cdot \mathbf{v}\_s(n-1) = -\mathbf{C}\_2 \cdot \mathbf{v}\_o(n) \tag{53}$$

where *vo* and *vs* are the output and the input voltages. Therefore, it is possible to calculate the integrator gain in the Z domain, *vo vs* (*z*):

$$\frac{v\_o}{v\_s}(z) = -\frac{\mathcal{C}\_1}{\mathcal{C}\_2} \frac{z^{-1}}{1 - z^{-1}}\tag{54}$$

By using the proposed approach, we obtain a gain expression, which is identical to the traditional closed-loop integrator reported in Equation (1). In both cases, the desensitization of the gain concerning the OTA parameters is reached as the gain depends only on the *C*1 and *C*2 capacitor ratio, in the ideal case.

#### *3.1. Small Signal Analysis of the Proposed Charge Bu*ff*er*

To evaluate the impact of the non-null input resistance and the finite output resistance of the charge buffer, the linear model of the integrator reported in Figure 7 was considered.

**Figure 7.** The linear model of the open-loop switched-capacitor integrator.

In practice, the *C*1 capacitance is discharged on input resistance *ri*, producing the input current *ii*. This current is amplified with a current gain *Ai* by the current amplifier that feds the output load made by the output resistance *ro* and the output capacitance *C*2.

First of all, the transfer function, *vo vs* (*s*), is calculated as previously done for the traditional closed-loop switched-capacitor integrator:

$$\frac{v\_o}{v\_s}(s) = -A\_l \cdot \frac{s \cdot \mathbb{C}\_1}{1 + s \cdot r\_l \cdot \mathbb{C}\_1} \cdot \frac{r\_o}{1 + s \cdot r\_o \cdot \mathbb{C}\_2} \tag{55}$$

Compared to the transfer function of the closed-loop switched-capacitor integrator shown in Equation (3), the transfer function of the open-loop switched-capacitor integrator already is calculated, has an additional pole due to the finite output resistance *ro*.

#### *3.2. Transient Analysis of the Proposed Charge Bu*ff*er*

Assuming a step signal at the input as reported in Equation (2), the output voltage becomes:

$$\begin{split} v\_o(t) &= -\frac{\mathbb{C}\_1}{\mathbb{C}\_2} \cdot A\_{i^\*} V\_{i^\*} \frac{1}{1 - \frac{r\_i}{r\_0} \cdot \frac{\mathbb{C}\_1}{\mathbb{C}\_2}} \left( e^{-\frac{t}{\tau\_{p2}}} - e^{-\frac{t}{\tau\_{p1}}} \right) \\ &= -\frac{\mathbb{C}\_1}{\mathbb{C}\_2} \cdot A\_{i^\*} V\_{i^\*} \frac{1}{1 - \frac{\mathbb{C}\_1}{\mathbb{A}\_2 \times \mathbb{C}\_2}} \left( e^{-\frac{t}{\tau\_{p2}}} - e^{-\frac{t}{\tau\_{p1}}} \right) \end{split} \tag{56}$$

where:

$$
\pi\_{p1} = r\_i \cdot \mathbb{C}\_1 \quad \pi\_{p2} = r\_o \cdot \mathbb{C}\_2 \qquad A\_{\overline{v}} = \frac{r\_o}{r\_i} \tag{57}
$$

*Av* is the voltage gain. The error on the current gain, *Ai*, of the current mirror, directly affects the accuracy of the output voltage. This error mainly depends on the transistor mismatch, which can be minimized thanks to the appropriate design of the overdrive of the transistors forming the current mirror [12].

The output resistance *ro*, partially drags the charge stored in *C*2. Considering a first-order Taylor's expansion for the *e*−*t*/τ*p2* term, and assuming a unitary current gain, the output voltage, *vo*(*t*), at *t* = *TCLK*/2, is calculated as follows from Equation (56):

$$v\_o(\frac{T\_{CLK}}{2}) \cong -\frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_v \cdot C\_2}} \cdot V\_i \cdot \left(1 - \frac{T\_{CLK}}{2 \cdot \tau\_{p2}} - e^{-\frac{T\_{CLK}}{2 \cdot \tau\_{p1}}}\right) \tag{58}$$

Three sources of error on the output voltage at *t* = *TCLK* 2 , *vo TCLK* 2 , remain. They are due to:

The impact of each source of error is evaluated considering the remaining ones disabled.

To evaluate the error, ε*r*, due to the finite voltage gain, *Av*, it is assumed that τ*p*1 tends to zero and τ*p*2 tends to infinite. In these conditions, the output voltage can be approximated as follows:

$$\left.v\_o \left(\frac{T\_{CLK}}{2}\right)\right|\_{\tau\_{p1}} \tau\_{p1} \to 0 \quad \text{\t = } -\frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_v \cdot C\_2}} \cdot V\_i \tag{59}$$

The corresponding error, ε*r*, is calculated as the difference between the ideal voltage obtained using the ideal gain value shown in Equation (54), and the value of the voltage expressed in Equation (59), i.e.,

$$\varepsilon\_{r} = \left| -\frac{\mathbb{C}\_{1}}{\mathbb{C}\_{2}} \cdot V\_{i} - \upsilon\_{o} \left( \frac{T\_{CLK}}{2} \right) \right|\_{\begin{array}{c} \tau\_{p1} \to 0 \\ \tau\_{p2} \to \infty \end{array}} \right| = \frac{\mathbb{C}\_{1}}{\mathbb{C}\_{2}} \cdot \frac{\frac{\mathbb{C}\_{1}}{A\_{v} \cdot \mathbb{C}\_{2}}}{1 - \frac{\mathbb{C}\_{1}}{A\_{v} \cdot \mathbb{C}\_{2}}} \cdot V\_{i} \tag{60}$$

To evaluate the error due to τ*p*1, it is assumed that τ*p*2 tends to infinite. In these conditions, the output voltage can be approximated as follows:

$$\left.v\_o \left(\frac{T\_{CLK}}{2}\right)\right|\_{\tau\_{p2}\to\infty} = -\frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_2 \cdot C\_2}} \cdot V\_i \cdot \left(e^{-\frac{T\_{CLK}}{2\tau\_{p1}}} + 1\right) \tag{61}$$

The error due to τ*p*1, ετ*p*1, is calculated as the difference between the output voltages expressed in Equations (50) and (52), i.e.:

$$\varepsilon\_{\tau p1} = \left| v\_o \left( \frac{T\_{CLK}}{2} \right) \right|\_{\tau\_{p1} \to 0} - v\_o \left( \frac{T\_{CLK}}{2} \right) \Big|\_{\tau\_{p2} \to \infty} \right| = \frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_v C\_2}} \cdot V\_i \cdot e^{\frac{-T\_{CLK}}{2\tau\_{p1}}} \tag{62}$$

The error due to τ*p*2, ετ*p*2, is calculated as the difference between the output voltages expressed in Equations (58) and (61), i.e.:

$$\varepsilon\_{\tau p2} = \left| \upsilon\_o \left( \frac{T\_{CLK}}{2} \right) - \upsilon\_o \left( \frac{T\_{CLK}}{2} \right) \right|\_{\tau\_{p2} \to \infty} \right| = \frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_2 \cdot \overline{C\_2}}} \cdot V\_i \cdot \frac{T\_{CLK}}{2 \cdot \tau\_{p2}} \tag{63}$$

Figure 8 shows the output voltage behavior.

**Figure 8.** Output voltage behavior of the open-loop switched-capacitor integrator in the linear regime.

The sum of the three error ε*r*, ετ*p*1, and ετ*p*2, gives the total error ε*tot*, which must be less than the required accuracy, ξ:

$$
\varepsilon\_{\text{tot}} = \varepsilon\_r + \varepsilon\_{\text{tp1}} + \varepsilon\_{\text{tp2}} < \xi \tag{64}
$$

Since the error terms ε*r*, ετ*p*1, and ετ*p*2 are positive, each of them must be less than ξ.

#### *3.3. Voltage Gain Requirement of the Proposed Charge Bu*ff*er*

As calculated in Equation (60), ε*r* is less than the ξ, therefore, we obtain

$$A\_{\upsilon} > \frac{C\_1}{C\_2} \cdot \left( 1 + \frac{V\_i}{\xi} \cdot \frac{C\_1}{C\_2} \right) \cong \frac{V\_i}{\xi} \cdot \frac{C\_1^2}{C\_2^2} \tag{65}$$

In Equation (65) is very similar to Equation (17), which defines the requirement of the OTA for the closed-loop switched-capacitor integrator. It can be concluded that the charge buffer of the proposed open-loop switched-capacitor integrator requires the same gain of the OTA in the traditional closed-loop solution.

From Equation (58), the sensitivity, *S vo*( *TCLK* 2 ) *Av* , of the output voltage at *TCLK* 2 , *vo TCLK* 2 , and *Av* is evaluated as follows:

$$S\_{A\_{\upsilon}}^{\upsilon\_{\mathbb{P}}\left(\frac{T\_{CLK}}{2}\right)} = \frac{A\_{\upsilon}}{v\_o \left(\frac{T\_{CLK}}{2}\right)} \cdot \frac{\partial v\_o \left(\frac{T\_{CLK}}{2}\right)}{\partial A\_{\upsilon}} = \frac{A\_{\upsilon} \cdot \frac{C\_1}{C\_2}}{\left(A\_{\upsilon} - \frac{C\_1}{C\_2}\right)^2} \cong \frac{A\_{\upsilon} \cdot \frac{C\_1}{C\_2}}{\left(A\_{\upsilon} - \frac{C\_1}{C\_2}\right)^2} \tag{66}$$

where the last approximation is valid as *Av C*1 *C*2 . The previous result is very similar to the one obtained for the Cascode OTA in the closed-loop switched-capacitor integrator in Equation (18).

*3.4. Input and Output Resistances Requirements of the Proposed Charge Bu*ff*er*

Assuming ετ*p*1, calculated in Equation (62), less than ξ we obtain

$$\pi\_{p1} < \frac{T\_{CLK}}{2 \cdot \ln\left(\frac{V\_i}{\xi \cdot \left(1 - \frac{C\_1}{\lambda\_V C\_2}\right) \cdot \frac{C\_2}{C\_1}}\right)} \cong \frac{T\_{CLK}}{2 \cdot \ln\left(\frac{V\_i}{\xi} \cdot \frac{C\_1}{C\_2}\right)}\tag{67}$$

Last approximation in Equation (67) is valid as *Av C*1 *C*2 . *Electronics* **2020**, *9*, 762

Taking into account the expression of τ*p*1 in Equation (57), the following constraint on the input resistance, *ri*, is obtained:

$$r\_i < \frac{T\_{CLK}}{2 \cdot \mathbb{C}\_1 \cdot \ln\left(\frac{V\_i}{\xi} \cdot \frac{C\_1}{C\_2}\right)}\tag{68}$$

Assuming ετ*p*2, calculated in Equation (63), less than ξ we obtain

$$
\pi\_{p2} > \frac{T\_{CLK}}{2} \cdot \frac{V\_i}{\xi \cdot \left(1 - \frac{C\_1}{A\_{V} \cdot C\_2}\right)} \cdot \frac{C\_1}{C\_2} \simeq \frac{T\_{CLK}}{2} \cdot \frac{V\_i}{\xi} \cdot \frac{C\_1}{C\_2} \tag{69}
$$

In this case, last approximation is valid as *Av C*1 *C*2 .

Considering τ*p*2 in Equation (57), from Equation (69) it is derived the following constraint on the output resistance, *ro*:

$$r\_o > \frac{T\_{CLK}}{2} \cdot \frac{V\_i}{\xi} \cdot \frac{C\_1}{C\_2^2} \tag{70}$$

As already done for the voltage gain, *Av*, from Equation (58) the sensitivity, *S vo*( *TCLK* 2 ) *ri* , of the output voltage at *TCLK* 2 , *vo TCLK* 2 , and *ri* is evaluated as follows:

$$S\_{r\_i}^{v\_p(\frac{T\_{CLK}}{2})} = \frac{r\_i}{v\_o(\frac{T\_{CLK}}{2})} \cdot \frac{\partial v\_o(\frac{T\_{CLK}}{2})}{\partial r\_i} = \frac{T\_{CLK}}{2 \cdot \tau\_{p1}} \cdot \frac{e^{\frac{-T\_{CLK}}{2\tau\_{p1}}}}{1 - \frac{T\_{CLK}}{2 \cdot \tau\_{p2}} - e^{\frac{-T\_{CLK}}{2\tau\_{p1}}}} \cong \frac{T\_{CLK}}{2 \cdot \tau\_{p1}} e^{\frac{-T\_{CLK}}{2\tau\_{p1}}}\tag{71}$$

where last approximation is valid as *TCLK* 2·τ*p*2 − *e* −*TCLK* 2·τ*p*1 1. This inequation is verified as the condition imposed by Equations (67) and (69) are satisfied, since, generally, *Vi* ξ and *C*1 *C*2 ≥ 1. It can be seen that the result of the calculation of the sensitivity of the output voltage compared to *ri* is very similar to the one obtained for the calculation of the output voltage sensitivity for *gm* of the Cascode OTA in the closed-loop switched-capacitor integrator in Equation (22).

Regarding the sensitivity, it can be concluded that the proposed switched-capacitor integrator, despite working in an open-loop configuration, has a robustness to PVT variations similar to the closed-loop switched-capacitor integrator.

However, since the performance of the proposed open-loop switched-capacitor integrator depends on the output resistance of the charge buffer, *ro*, the sensitivity, *S vo*( *TCLK* 2 ) *ro* , of the output voltage at *TCLK* 2 , *vo TCLK* 2 , and *ro* is calculated as:

$$S\_{r\_g}^{v\_o(\frac{T\_{CLK}}{2})} = \frac{r\_i}{v\_o(\frac{T\_{CLK}}{2})} \cdot \frac{\partial v\_o(\frac{T\_{CLK}}{2})}{\partial r\_i} = \frac{T\_{CLK}}{2 \cdot \tau\_{p2}} \cdot \frac{1}{1 - \frac{T\_{CLK}}{2 \cdot \tau\_{p2}}e^{-\frac{T\_{CLK}}{2 \cdot \tau\_{p2}}}} \cong \frac{T\_{CLK}}{2 \cdot \tau\_{p2}}\tag{72}$$

According to Equation (69) and considering that *Vi* ξ 1 and *C*1 *C*2 ≥ 1, it can be assumed that *S vo*( *TCLK* 2 ) *ro* is quite less than 1. Therefore, the impact of the *ro* variation on the integrator performance is limited.

#### *3.5. Circuit Implementation of the Proposed Charge Bu*ff*er*

Figure 9 shows a possible circuit implementation of the charge buffer. The switched capacitors network at the output nodes is used to set the output common-mode voltage at *Vcm*. Reference *Vb*1 is designed to set the input common-mode voltage at *Vcm*. To keep *M*2 and *M8* transistors in the saturation region, their source-drain voltage must be more than their saturation voltage, i.e.:

$$V\_{SD2} = V\_{dd} - V\_{cm} > V\_{SD2,sat} \tag{73}$$

It is supposed that *Vcm* is equal to half supply voltage and the saturation voltages correspond to the transistor overdrive, *Vov*2, from Equation (73) we derive

$$V\_{\rm av2} < \frac{V\_{dd}}{2} \tag{74}$$

To bias the *M*1 transistor in the saturation region, it must be guaranteed that its source-drain voltage, *VSD*1, overcomes its saturation voltage, corresponding to the transistor overdrive, *Vov*1, i.e.:

$$V\_{SD1} > V\_{ov1} \tag{75}$$

From the last equation, we obtain

$$|V\_{SD1} = V\_{cm} - V\_{dd} + |V\_{THP}| + V\_{ov2} > V\_{ov1} \tag{76}$$

Assuming *Vcm* = *Vdd*/2, the last equation can be rearranged to obtain a constraint on the difference between the *M*1 and *M*2 transistors overdrives, Δ*Vov2*−1, i.e.:

$$
\Delta V\_{\text{ov2}-1} = V\_{\text{ov2}} - V\_{\text{ov1}} > \frac{V\_{\text{dd}}}{2} - |V\_{\text{THP}}| \tag{77}
$$

Using the finFET 16 nm we obtain the result *Vdd* = 0.95 V, *VTHP* = 0.4 V. Consequently, Δ*Vov2*−1 must be higher than 75 mV.

According to Equations (74) and (77), using a charge buffer in open-loop configuration gives more flexibility to the design since larger overdrives can be defined for the transistors, to employing an OTA in a closed-loop fashion. This is extremely important at low voltage supply.

**Figure 9.** Circuit implementation of the charge buffer.

The input and the output resistances, *ri* and *ro*, are calculated as follows:

$$r\_i \cong \frac{1}{\mathcal{G}\_{m1} \cdot \mathcal{G}\_{m2} \cdot r\_{ds3}} = \frac{V\_{ov1} \cdot V\_{ov2}}{4 \cdot V\_{A3} \cdot I\_B}; \qquad r\_o \cong r\_{ds6} = \frac{V\_{A6}}{I\_B} \tag{78}$$

where *gm*1 and *gm*2 are the transconductance of *M*1 and *M*2 transistors, respectively, while *rds3* and *rds6* are the output resistance of *M*3 and *M*6 transistors, respectively.

The voltage gain, *Av*, is calculated as follows:

$$A\_{\upsilon} = \frac{r\_o}{r\_i} = \frac{4 \cdot V\_{A3} \cdot V\_{A6}}{V\_{\upsilon \upsilon 1} \cdot V\_{\upsilon 2}} \tag{79}$$

The telescopic Cascode OTA reported in Figure 4 implements the boost of the output resistance, *ro*. On the other end, the proposed charge buffer circuit enables the boosting of the transconductance of the input transistors, *gm*1, by a *gm*2·*rds3* factor, lowering the input resistance, *ri*. The impact on the final voltage gain is similar as demonstrated by the similitude of the voltage gain expressions reported in Equations (79) and (27), even if the voltage gain, *Av*, of the proposed charge buffer results the double with respect to the telescopic Cascode OTA.

In both cases, the power consumption is determined by the settling requirements, i.e., both the time constants τ*p* and τ*p*1 for the closed-loop and the proposed open-loop switched-capacitor integrator, respectively. The time constant, τ*p*, depends on 1/*gm*1. In this case, the only possibility to increase *gm*1 is to increase the bias current *IB* of the telescopic Cascode OTA, since the input transistor overdrive is bound to bias constraints. For the proposed integrator, the time constant τ*p*1 is proportional to *ri*. However, in the last case, as the boost on the input transistor transconductance lowers the input resistance, *ri*, a significant power saving is obtained.

#### *3.6. Slew-Rate Analysis of the Proposed Charge Bu*ff*er*

According to Equation (56), the maximum rate of variation of the output voltage, i.e., the slew-rate, is obtained at the initial instant, *t* = 0 s:

$$SR = \frac{dv\_0(t)}{dt}\bigg|\_{\text{max}} = \frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_{\text{r}} \cdot C\_2}} \cdot V\_{SRi,\text{max}} \left(\frac{1}{\tau\_{p1}} - \frac{1}{\tau\_{p2}}\right) \approx \frac{V\_{SRo,\text{max}}}{\tau\_{p1}}\tag{80}$$

where:

$$V\_{SRo,max} = \frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_2 C\_2}} \cdot V\_{SRi,max} \cong \frac{C\_1}{C\_2} \cdot V\_{SRi,max} \tag{81}$$

The last approximation in Equation (81) is valid assuming τ*p*1 τ*p*2.

The slew-rate depends on the bias current *IB* and the output capacitance *C*2, i.e.:

$$SR = \frac{I\_B}{C\_2} \tag{82}$$

where *IB* is the bias current of each branches composing the charge buffer drawn in Figure 9.

Combining Equations (80) and (82) and considering the expression of τ*p*1 and *ri* reported in Equations (57) and (78), respectively, we derive:

$$V\_{SRo,max} = \frac{I\_B}{C\_2} \cdot \tau\_{p1} = \frac{C\_1}{C\_2} \cdot \frac{V\_{ov1} \cdot V\_{ov2}}{4 \cdot V\_{A3}} \tag{83}$$

where *Vov*1 and *Vov*2 are the overdrive voltage of *M*1 and *M*2 transistors, respectively, and *VA3* is the early voltage of *M*3 transistor.

Combining Equations (81) and (84), the value of *VSRi,max* is obtained:

$$V\_{SRi,max} = \frac{V\_{ov1} \cdot V\_{ov2}}{4 \cdot V\_{A3}} \frac{1}{1 - \frac{C\_1}{A\_{\text{v}} \cdot C\_2}} \cong \frac{V\_{ov1} \cdot V\_{ov2}}{4 \cdot V\_{A3}} \tag{84}$$

*Electronics* **2020**, *9*, 762

The output voltage range where the charge buffer operates in the linear regime, *VSRo,max*, has been reduced by a factor equal to 4·*VA*3 *Vov*2 concerning the traditional closed-loop switched-capacitor integrator with the OTA.

Due to its differential structure, the charge buffer starts slewing as *Vi* > *2*·*VSRi,max*. If a slewing period is considered, the differential output voltage, *vod*(*t*), can be calculated as follows:

$$\begin{cases} \begin{aligned} v\_{od}(t) &= -2 \cdot \frac{V\_{SR,\text{max}}}{\tau\_{p1}} \cdot t \quad \text{for } 0 < t < \tau\_s\\ v\_{od}(t) &= \left( -\frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_0 \cdot C\_2}} \cdot V\_i + 2 \cdot V\_{SR,\text{max}} \right) \left( 1 - \frac{t - \tau\_s}{\tau\_{p2}} \right) - 2 \cdot V\_{SR,\text{max}} \left( 1 - \frac{t - \tau\_s}{\tau\_{p2}} - e^{-\frac{t - \tau\_s}{\tau\_{p1}}} \right) \end{aligned} \end{cases} \tag{85}$$

where τ*s* is the duration of the slewing period. The charge buffer slews until the output differential voltage, *vod*(*t*), is less than 2·*VSRo,max* concerning the final value in steady-state, neglecting the losses due to the output resistance (i.e., τ*p*2→∞):

$$-2\cdot \frac{V\_{SRo,\max}}{\tau\_{p1}} \cdot \tau\_s = -\frac{C\_1}{C\_2} \cdot \frac{1}{1 - \frac{C\_1}{A\_v C\_2}} \cdot V\_i + 2\cdot V\_{SRo,\max} \approx -\frac{C\_1}{C\_2} \cdot V\_i + 2\cdot V\_{SRo,\max} \tag{86}$$

From the combination of the last equation and Equation (83), the expression of τ*s* is derived:

$$\tau\_{\sf s} = \tau\_{p1} \cdot \left( \frac{\mathbb{C}\_1}{\mathbb{C}\_2} \cdot \frac{V\_i}{2 \cdot V\_{SRo,max}} - 1 \right) = \tau\_{p1} \cdot \left( \frac{V\_i}{2 \cdot V\_{SRi,max}} - 1 \right) \tag{87}$$

#### *3.7. SNR Analysis of the Proposed Open-Loop Switched-Capacitor Integrator*

By focusing the analysis on a single branch, *Vo*+ must satisfy the following inequation to guarantee that *M*4 transistors operate in saturation region:

$$V\_{o+} \, \ast \, V\_{DS,sat4} + V\_{S4} = V\_{ov} + V\_{S4} \tag{88}$$

where *VS*4 and *VDS*,*sat*4 are the source and the saturation voltages of *M*4 transistor, respectively. It is assumed that *Vds*,*sat*4 is equal to *Vov*. The bias voltage *Vb*5 was chosen to make *M*5 transistor operating in saturation, i.e.,

$$V\_{ds5} = V\_{S4} \times V\_{DS, \text{sat5}} = V\_{\text{av}} \tag{89}$$

where *VDS*5, and *VDS*,*sat*5 are the drain-source, and the saturation voltages of *M*4 transistor, respectively. In this case, it is assumed that *Vds,sat*1 is equal to *Vov*. *VS*1 is derived from the *Vb*5 bias voltage, by dropping the gate-drain voltage of the *M*4 transistors, *VGS*4, i.e.:

$$V\_{\rm S4} = V\_{b1} - V\_{\rm GS4} = V\_{b1} - V\_{TH} - V\_{\rm av} \tag{90}$$

*Vb*1 can be designed to make *VS*4, and, hence, *VDS*5 equal to *VDS5,sat*, i.e., *Vov*. If so, from Equation (88) we derive the minimum output voltage, *Vo*+*,min*:

$$V\_{o+} > V\_{\text{av}} + V\_{\text{DS5}, \text{sat}} = 2 \cdot V\_{\text{av}} = V\_{o+, \text{min}} \tag{91}$$

As the output voltage starts swinging from the common-mode voltage, *Vcm*, down to *Vo,min*, it is possible to calculate the maximum output voltage swing, *Vswing*:

$$V\_{swing} = 2 \cdot (V\_{cm} - V\_{o+,min}) = 2 \cdot \left(\frac{V\_{dd}}{2} - 2 \cdot V\_{ov}\right) = V\_{dd} - 4 \cdot V\_{ov} \tag{92}$$

where the 2 factor is due to the differential architecture. It is assumed that *Vcm* is equal to half *Vdd*.

Assuming that the thermal noise due to the switches around *C*1, 2· *KT C*1 is dominant, from Equation (92), the signal to noise ratio of the overall open loop switched capacitor integrator, *SNROL*, is calculated as follows:

$$\text{SNR}\_{\text{OL}} = \frac{1}{2} \cdot \frac{V\_{\text{suning}}^2}{\overline{\upsilon\_{n,o}^2}} = \frac{1}{2} \cdot \frac{(V\_{dd} - 4 \cdot V\_{ov})^2}{2 \cdot \frac{K \cdot T}{C\_1} \cdot \left(\frac{C\_1}{C\_2}\right)^2} = \frac{\left(V\_{dd} - 4 \cdot V\_{ov}\right)^2 \cdot C\_2^2}{4 \cdot K \cdot T \cdot C\_1} \tag{93}$$

where *v*2 *n*,*o* is the total output noise, which is given by the thermal noise contribution due to the *C*1 switched-capacitor multiplied by the square of the integrator gain *C*1 *C*2 2 , and the 1 2 factor takes into account that the input signal is a sinusoid.

The resulting *SNROL* is slightly higher than the *SNRCL* calculated by Equation (43). The output noise is about the same since the noise contribution of *C*1 is assumed dominant. However, assuming *VTH* = 0.275 V and *Vdd* = 0.95 V as for the finFET technology and *Vov* = 0.1 V, due to bias constraint as defined by Equation (43), the output voltage swing for the proposed switched-capacitor integrator is higher.

#### *3.8. Power Consumption Requirement of the Proposed Charge Bu*ff*er*

The minimum power consumption, *Pw,min*, is given by the product of the supply voltage *Vdd*, by the minimum total bias current *IBTOT.min*:

$$P\_{w,\text{min}} = V\_{dd} \cdot I\_{BTOT,\text{min}} \cdot 4 \cdot \left(1 + \frac{H}{2}\right) \cdot V\_{dd} \cdot I\_{B,\text{min}} \tag{94}$$

where *IB,min* is the minimum *IB* bias current. The power requirement is calculated according to the settling time requirement. In practice, the minimum bias current *IB,min* is derived assuming that the ετ*p*1 error must be less than the required accuracy ξ, i.e.:

$$
\varepsilon\_{\tau p1} < \xi \tag{95}
$$

As *Vi* < *2*·*VSRi,max*, the charge buffer is in the linear regime, where the expression of *IB,min* is derived from Equation (62):

$$I\_{B,\text{min}} = \frac{2 \cdot C\_1 \cdot V\_{SRi,\text{max}}}{T\_{CLK}} \cdot \ln\left(\frac{C\_1}{C\_2} \cdot \frac{V\_i}{\xi}\right) \tag{96}$$

Combining Equations (94) and (96), the minimum required power consumption, *Pw,min*, is calculated as follows:

$$P\_{\rm uv,min} = \frac{8 \cdot V\_{dd} \cdot \left(1 + \frac{Ll}{2}\right) \cdot C\_1 \cdot V\_{SRi,max}}{T\_{CLK}} \cdot \ln\left(\frac{C\_1}{C\_2} \cdot \frac{V\_i}{\xi}\right) \tag{97}$$

As *Vi* > *2*·*VSRi,max*, the charge buffer starts slewing. Considering the expression of the differential output voltage *vod*(*t*), including the slewing period reported in Equation (85), the calculation of the error due to τ*p*1, ετ*p*1, is updated as follows:

$$\varepsilon\_{\tau p1} = \left| \upsilon\_o \left( \frac{T\_{CLK}}{2} \right) \right|\_{\tau\_{p1} \to 0} - \left. \upsilon\_o \left( \frac{T\_{CLK}}{2} \right) \right|\_{\tau\_{p2} \to \infty} \right| = 2 \cdot V\_{SRo, num} \cdot \mathcal{C} \xrightarrow{\frac{T\_{CLK}}{2} - \varepsilon\_1} \tag{98}$$

Considering ετ*p*1 as reported in the previous equation, the constraint on τ*p*1 is derived from Equation (95):