*Edited by Dhanasekaran Vikraman and Hyun-Seok Kim*

In recent years, research on microelectronics has been specifically focused on the proposition of efficient alternative methodologies and materials to fabricate feasible integrated circuits. This book provides a general background of thin film transistors and their simulations and constructions. The contents of the book are broadly classified into two topics: design and simulation of FETs and construction of FETs. All the authors anticipate that the provided chapters will act as a single source of reference for the design, simulation and construction of FETs. This edited book will help microelectronics researchers with their endeavors and would be a great addition to the realm of semiconductor physics.

ISBN 978-1-78923-416-9

Design, Simulation and Construction of Field Effect Transistors

Published in London, UK © 2018 IntechOpen © kefkenadasi / iStock


**Abstract**

Precision manufacturing techniques are required for the fabrication of small and large optical components in various fields. To prepare molding dies with highly precise geometric shapes and surface roughness that are used in certain molding processes, polishing techniques have been investigated for many materials. In this research, the polishing techniques used for a SUS310S stainless steel molding die for the glass forming technology "slumping method" were investigated. The surface roughness of the polished SUS310S molding die surface was below *Rz* = 120 nm (P–V), *Ra* = 20 nm after 35 h of polishing with 0.5% alumina polishing liquid under a pressure of 1.7 kPa. In addition, the centerless polishing machine was designed and manufactured to polish cylindrical molding die surfaces with same polishing conditions. As the result of using cylindrical molding dies that made by this centerless polishing machine, the surface roughness of the glass plate formed using the slumping method with the polished molding die was below *Ra* = 20 nm.