Finally, the properties of the Pt-Ru catalysts were affected by support materials. Pt-Ru/CBs showed 68mA/mg, Pt-Ru/polyaniline showed 121mA/mg, and Pt-Ru/CNTs showed 202mA/mg for values of methanol oxidation specific current. The electroplating method and the physic-chemical feature of support materials affected the deposited particle size of Pt-Ru catalysts and tendency of aggregation.

#### **5. Acknowledgment**

This research was supported by the Converging Research Center Program through the Ministry of Education, Science and Technology (Grant No.: 2011K000643), the Ministry of Knowledge and Economy (Material source Technology Project Grant No. 10037238.2011), and Basic Science Research Program through the National Research Foundation of Korea (NRF) funded by the Ministry of Education, Science and Technology (Grant No.: 2011- 0009007).

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### **Fabrication of InGaN-Based Vertical Light Emitting Diodes Using Electroplating**

Jae-Hoon Lee1 and Jung-Hee Lee2

*1GaN Power Research Group, R&D Institute, Samsung LED Company Ltd., Suwon, 2Electronic Engineering & Computer Science, Kyungpook National University, Daegu, Korea*

#### **1. Introduction**

54 Electroplating

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Giallombardo, J.R. & Castro, De E.S. Investigation of enhanced CO tolerance in proton exchange membrane fuel cells by carbon supported PtMo alloy catalyst.

a micro tubular DMFC cathode. *J. Power Sources*. Vol.139, No.1-2, (January 2005),

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Cell Cathodes with Sulfur and Nitrogen-Based Carbon Functionality. *J. Electrochem.*

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surface science investigation of the PtRu bulk alloy surface*. J. Electroanal. Chem.*,

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Group III–nitride semiconductors and their ternary solid solutions are very promising as the candidates for both short wavelength optoelectronics and power electronic devices (Nakamura et al. 1997; Nakamura et al. 1995; Lee, et al. 2010; Youn, et al. 2004). The AlGaN/GaN heterostructure field effect transistors (HFETs) have a great potential for future high-frequency and high-power applications because of the intrinsic advantages of materials such as wide bandgap, high breakdown voltage, and high electron peak velocity (Smorchkova et al. 2000). Major developments in wide-gap III-nitride semiconductors have led to commercial production of high-brightness light emitting diodes (LEDs). The InGaN-based LEDs have already been extensively used in full-color displays, traffic displays, and other various applications such as projectors, automobile headlights, and general lightings. In particular, white LEDs based on InGaN/GaN quantum well heterostructure are regarded as the most promising solid-state lighting devices to replace conventional incandescent or fluorescent light. It is required, however, to reduce the high dislocation density due to large lattice mismatch between GaN epitaxial layer and sapphire substrate and to increase the light extraction efficiency for fabricating high-performance LEDs. Epitaxial lateral overgrowth (ELOG) or pendeo epitaxy (PE) has been used to partially overcome the problems (Sakai et al. 1997; Zheleva et al. 1997). Although the ELOG and PE process can dramatically decrease dislocation density, the related growth process is complicated and time consuming. Recently, it has been reported that one can not only reduce the threading dislocation density in GaN films, but also enhance the light extraction efficiency by using patterned sapphire substrate (PSS) (Yamada, et al. 2002; Tadatomo, et al. 2001; Wuu, et al. 2006). The PSS technique has attracted much attention for its high production yield due to the single growth process without any interruption. Future demands for these and more advanced applications will require higher light output with lower power consumption. The refractive index of nitride films (n = 2.4) is higher than that of air (n = 1) and sapphire substrate (n = 1.78). The critical angle of the escape cone is about 23°, which indicates that about only 4% of the total light can be extracted from the surface (Huh, et al. 2003). Most of the generated lights in the active layer is absorbed by the electrode at each reflection and gradually disappear due to total internal reflection. In order to improve the light extraction efficiency, it is very important to find the escape cone which the photons generated from LEDs experience multiple opportunities. Several previous works have reported that one can increase the light extraction efficiency of nitride-based LEDs by roughening the sample surface. However, the surface texturing is difficult in conventional LED because the p-GaN top layer being too thin for texturing and the sensitivity of p-GaN to plasma damage and electrical deterioration. It is also well known that poor heat dissipation has been the main problem in the development of high-power In-GaN/sapphire LEDs. For a conventional nitride-based LED, the generated heat is dissipated through the path from sapphire to silver paste and then to heat sink. The poor thermal conductivities of sapphire (∼35 W/mK) and silver paste (2-25W/mK) limit heat flow and dissipation, resulting in increased junction temperature of the device due to Joule heating at the p-n junction. Recently, high efficiency GaN based LEDs was fabricated using the laser liftoff (LLO) technique (Fujii, et al. 2004; Wang, et al. 2005; Wang, et al. 2006). The LLO process can enhance the light output power, the operating current and the heat sink of fabricated vertical type LED (VT-LED). The other advantage of VT-LED is room for roughening top surface compared to conventional lateral LED. It has been reported to produce a roughened VT-LED surface with conlike feature and microns arrays using photoelectrochamical etching and plasma etch process, respectively. However, since these approaches involve difficult and complicated fabrication process, improvement is still required for higher device performance. In this work, we have proposed a new method utilizing surface texture of vertical type LEDs by using cone-shape patterned sapphire substrate (CSPSS) for the purpose of increasing extraction efficiency (Lee, et al. 2006; Lee, et al. 2008; Lee, et al. 2009) Compared to conventional roughening process, the proposed method is simple and highly reproducible due to forming patterns neatly designed on sapphire before GaN growth. In this chapter, firstly the history and important properties of the group III-nitrides is briefly reviewed, then the fabrication of the InGaN-based VT-LED was presented, finally a conclusion is drawn.

#### **2. Evolution of III-nitride materials**

GaN was first created in 1932 by Johnson at the University of Chicago by reacting ammonia gas with solid gallium at temperature of 900-1000℃ (Johnson et al. 1932). The GaN synthesis technique was also used to study the crystal structure and lattice constant by Juza in 1938 and to study the photoluminescence spectra by Grimmeiss in 1959 (Juza, et al. 1938; Grimmeiss, et al. 1959). Maruska and Tietjen deposited the first large area GaN layers on sapphire in 1969 using vapor-phase transport in chlorine (Maruskam, et al. 1969). This earliest research on GaN was directed at understanding the properties of the material and learning how to design the material for specific uses. All the early GaN was very conductive as grown, and it was realized that these crystals were n-type with high carrier concentration owing to the highly defective nature of the crystal (Pankove, 1997). Because the work on GaN had early been focused on its potential for optical sources, p-type GaN was required in order to make p-n junction emitters, so much effort was focused in this area. Pankove et al. were successful in fabricating the first blue GaN LED (Pankove, et al. 1972). It was as metal/insulating GaN:Zn/n-GaN (MIS) diode. The n-GaN layers contained different concentration of Zn. The wavelength of the emitted light depended on the Zn concentration. Until the late 1970s the quality of GaN was not very good. The results of optical and electrical measurements were not reproducible. Yoshida et al. deposited an AlN buffer layer to overcome the nucleation problems of GaN grown directly on a sapphire substrate in 1983 (Yoshida, et al. 1983). This buffer layer technique was very effective in improving the overall material quality on sapphire. The two-step method was investigated and perfected by Akasaki, Amano and co-worker in 1988/1989 (Amano, et al. 1986). In the first step a thin buffer layer of AlN is grown on the sapphire substrate at a low temperature of ~ 500℃. The GaN layer is grown on the buffer layer. This importance accomplishment allowed GaN to be grown with much higher crystal quality than was previously available. The world wide attention on the research of group III-Nitrides were stimulated by the success in the material quality improvement with low temperature GaN nucleation layer by Nakamura in the early 1990's and later by the success in blue LEDs and LDs by Nakamura, leading toward the fundamental understanding of group III-Nitride material system (Nakamura, 1991; Nakamura, et al. 1996). The GaN-based FETs were also fabricated about the same time, i.e., in 1993 (Khan, et al. 1993). Fabrication of a heterostructure bipolar transistor using p-type 6H SiC as the based and n-type GaN as the emitter was reported in 1994 (Pankove, et al. 1994). Metalorganic chemical vapor deposition (MOCVD) has been the most popular growth technique for nitride growth and has been the choice for several electronic and optoelectronic devices such as HEMTs, HBTs, LEDs, and LDs.

#### **2.1 Important properties of III-nitride materials**

56 Electroplating

nitride-based LEDs by roughening the sample surface. However, the surface texturing is difficult in conventional LED because the p-GaN top layer being too thin for texturing and the sensitivity of p-GaN to plasma damage and electrical deterioration. It is also well known that poor heat dissipation has been the main problem in the development of high-power In-GaN/sapphire LEDs. For a conventional nitride-based LED, the generated heat is dissipated through the path from sapphire to silver paste and then to heat sink. The poor thermal conductivities of sapphire (∼35 W/mK) and silver paste (2-25W/mK) limit heat flow and dissipation, resulting in increased junction temperature of the device due to Joule heating at the p-n junction. Recently, high efficiency GaN based LEDs was fabricated using the laser liftoff (LLO) technique (Fujii, et al. 2004; Wang, et al. 2005; Wang, et al. 2006). The LLO process can enhance the light output power, the operating current and the heat sink of fabricated vertical type LED (VT-LED). The other advantage of VT-LED is room for roughening top surface compared to conventional lateral LED. It has been reported to produce a roughened VT-LED surface with conlike feature and microns arrays using photoelectrochamical etching and plasma etch process, respectively. However, since these approaches involve difficult and complicated fabrication process, improvement is still required for higher device performance. In this work, we have proposed a new method utilizing surface texture of vertical type LEDs by using cone-shape patterned sapphire substrate (CSPSS) for the purpose of increasing extraction efficiency (Lee, et al. 2006; Lee, et al. 2008; Lee, et al. 2009) Compared to conventional roughening process, the proposed method is simple and highly reproducible due to forming patterns neatly designed on sapphire before GaN growth. In this chapter, firstly the history and important properties of the group III-nitrides is briefly reviewed, then the

fabrication of the InGaN-based VT-LED was presented, finally a conclusion is drawn.

GaN was first created in 1932 by Johnson at the University of Chicago by reacting ammonia gas with solid gallium at temperature of 900-1000℃ (Johnson et al. 1932). The GaN synthesis technique was also used to study the crystal structure and lattice constant by Juza in 1938 and to study the photoluminescence spectra by Grimmeiss in 1959 (Juza, et al. 1938; Grimmeiss, et al. 1959). Maruska and Tietjen deposited the first large area GaN layers on sapphire in 1969 using vapor-phase transport in chlorine (Maruskam, et al. 1969). This earliest research on GaN was directed at understanding the properties of the material and learning how to design the material for specific uses. All the early GaN was very conductive as grown, and it was realized that these crystals were n-type with high carrier concentration owing to the highly defective nature of the crystal (Pankove, 1997). Because the work on GaN had early been focused on its potential for optical sources, p-type GaN was required in order to make p-n junction emitters, so much effort was focused in this area. Pankove et al. were successful in fabricating the first blue GaN LED (Pankove, et al. 1972). It was as metal/insulating GaN:Zn/n-GaN (MIS) diode. The n-GaN layers contained different concentration of Zn. The wavelength of the emitted light depended on the Zn concentration. Until the late 1970s the quality of GaN was not very good. The results of optical and electrical measurements were not reproducible. Yoshida et al. deposited an AlN buffer layer to overcome the nucleation problems of GaN grown directly on a sapphire substrate in 1983 (Yoshida, et al. 1983). This buffer layer technique was very effective in improving the overall material quality on sapphire. The two-step method was investigated and perfected by Akasaki, Amano and co-worker in 1988/1989 (Amano, et al. 1986). In the first step a thin

**2. Evolution of III-nitride materials**

The III-nitride group of materials includes GaN, AlN, InN, and their alloys. The bandgap of the nitride group of materials is direct and have different band gaps ranging from 6.2 eV for AlN down to 0.7 eV for InN. This gives a tremendous optical range for III-nitride materials, from yellow to ultraviolet. The large bandgap and strong termodynamical stability of the IIInitride material system point to promising high power and high-temperature electronic device applications. Nitride materials are also extremely resilient to harsh chemical environments, giving the possibility for use in environments where the more traditional III-V materials are unable to perform. The most thermodynmically stable form of the nitride materials is the wurtzite or hexagonal form. This result in the familiar hexagonal close pack (HCP) model of alternating planes of Ga and N atoms stacked in an ABABAB sequence. The crystal planes in the wurtzite system are given using the Miller-Bravis index system of [ijkl] with k = - (i + j). Further detail on HCP and hexagonal crystal notation can be found in the classic textbook "Introduction to Solid State Physics" by Charles Kittel (Kittel, 1995). Nitrides can also be forced to grow in a zincblend form by using cubic substrates such as (001) Si and GaAs. The stacking sequence in this case is ABCABC. However, although the electrical properties of cubic III-nitrides are in theory expected to be better than for hexagonal GaN, in practice cubic III-nitrides are generally not as high quality as the wurtzite form and often contain a mixture of both cubic and wurtzite phases (mixed phase). The structural properties of the cubic nitrides can be found in Ref (Gil, 1998).

The most common substrate for GaN epitaxial growth is sapphire. It was the substrate used during the first attempts at GaN epitaxy during the late 1960's and has remained as the leading choice to this day. The attraction to sapphire for GaN epitaxy stems from its high melting point, chemical stability, availability of large wafer sizes, very high quality crystals, and low wafer cost. However, sapphire has a large lattice and thermal mismatch with GaN, leading to high defect density (~109/cm2) in the GaN film and limiting the maximum layer thickness to less than 10 μm. In addition, the low thermal conductivity of sapphire limits heat dissipation through the substrate, imposing severe limits for power devices on this substrate. Despite these difficulties, sapphire remains as leading candidate for basic of IIInitride epitaxy due to wide availability and low cost. In the case of growth on c-plane sapphire, a 30° rotation around the c axis occurs for GaN Epitaxy, resulting in an effective lattice constant that is 1/√3 less than a sapphire. The resulting lattice mismatch is ~ 13%. In addition, on c-plane sapphire, the thermal expansion mismatch is -25.5 %.

Table 1 lists some of the common electronic properties of the III-nitride group of materials (for comparison, properties of Si, GaAs, and SiC are also included) (Levinshtein, et al. 2001). As can be seen, both SiC and the nitride group have larger bandgap energy than either Si or GaAs. The larger bandgap and high breakdown field of these materials allow SiC and Nitride based electronic devices to operate at higher temperatures and higher powers than Si or GaAs based devices. In addition, while SiC has a badgap near that of GaN, the IIInitrides group has three distinct advantages over SiC devices. First, the nitride groups of materials have direct transition bandgap, allowing for use in optical devices such as lasers and LEDs. Secondly, the nitride group has the availability of ternary (AlGaN, InGaN) and quaternary (AlInGaN) compounds leading to a more versatile bandgap range (0.7~6.2) than SiC alone and allowing for bandgap engineering in both optical and electronic application. Finally, the nitride ternary and quaternary compounds can be used for heterojunction

Table 1. Crystal and electrical properties of III-nitrides, SiC, Si and GaAs (Kittel, 1995; Gil, 1998; Levinshtein, et al. 2001).

lattice constant that is 1/√3 less than a sapphire. The resulting lattice mismatch is ~ 13%. In

Table 1 lists some of the common electronic properties of the III-nitride group of materials (for comparison, properties of Si, GaAs, and SiC are also included) (Levinshtein, et al. 2001). As can be seen, both SiC and the nitride group have larger bandgap energy than either Si or GaAs. The larger bandgap and high breakdown field of these materials allow SiC and Nitride based electronic devices to operate at higher temperatures and higher powers than Si or GaAs based devices. In addition, while SiC has a badgap near that of GaN, the IIInitrides group has three distinct advantages over SiC devices. First, the nitride groups of materials have direct transition bandgap, allowing for use in optical devices such as lasers and LEDs. Secondly, the nitride group has the availability of ternary (AlGaN, InGaN) and quaternary (AlInGaN) compounds leading to a more versatile bandgap range (0.7~6.2) than SiC alone and allowing for bandgap engineering in both optical and electronic application. Finally, the nitride ternary and quaternary compounds can be used for heterojunction

> **Lattice mismatch with GaN(%)**

c=4.982 2.48 2.0 4.2

c=5.1855 0 1.3 5.59

c=5.7034 -10.12 0.8 5.7

c=15.117 3.51 4.9 4.2

c=12.982 13.9 0.3 7.5

Si 1.12 a=5.431 -16.96 1.3 3.9 GaAs 1.42 a=5.653 -20.22 0.5 6.7

AlN 135 14 1.4 4-12 3124

InN 1000-1900 - 2.5 5.0 1873 6H SiC 400 50 2.0 3-5 >2000 Al2O3 - - - - 2015 Si 1500 450 1.0 0.3 1412 GaAs 8500 400 1.0 0.4 1240 Table 1. Crystal and electrical properties of III-nitrides, SiC, Si and GaAs (Kittel, 1995; Gil,

**Saturated drift velocity (107cm/s)**

**Thermal Conductivity at 300K (W/cmK)**

**Breakdown field (MV/cm)**

2.0 (exp) 5.0 2518

**Thermal expansion coeff. (10-6 /K)**

5.3

3.17

3.7

4.68

8.5

**Melting Point(**℃**)**

addition, on c-plane sapphire, the thermal expansion mismatch is -25.5 %.

**Lattice constant (Å)**

**Hole mobility (cm2/Vs)**

GaN 300-1000 <200 2.5 (calc)

**Material Bandgap**

**Material Electron**

**(eV)**

AlN 6.2 a=3.112

GaN 3.44 a=3.1891

InN 0.7 a=3.548

6H SiC 3.03 a=3.081

Al2O3 9.0 a=5.431

**mobility (cm2/Vs)**

1998; Levinshtein, et al. 2001).

relegating use of SiC to native oxide based devices (MOSFETs). As seen in Table 1, the undoped electron and hole mobility of the III-nitrides and SiC are relatively low compared to Si and GaAs. The electron mobility for unintentionally doped (UID) single GaN layers on either sapphire or SiC average about 300~400 cm2/Vs. Undoped mobility in these materials are normally limited by defect related scattering of defect hoping (Ng, et al. 1998). The highest reported mobility for MOCVD grown GaN was ~ 900 cm2/Vs (Nakamura, et al. 1997). The maximum calculated phonon-limited mobility in GaN is ~1350 cm2/Vs for electrons and ~200 cm2/Vs for holes (Look, et al. 2001). Light n type doping of GaN (~1 1017/cm3) results in improved mobility due to screening of dislocations and decreased defect-related conductivity. Further doping of the material leads to mobility degradation due to ionized impurity scattering. It should be noted that much higher mobility is possible (1500~2000 cm2/Vs) in GaN heterostructures by forming a high mobility two dimensional electron gas (2DEG) channel. Another important property for high frequency operation is the saturation electron drift velocity. This parameter gives the average electron velocity at high electric fields. The high saturated drift velocity of III-nitrides leads to applications at high frequencies than can be achieved from Si. As seen in Table 1, the calculated value of GaN electron velocity is 2.5 107 cm/s, although experimental evidence is closer to 2.0 107 cm/s (Wraback, et al. 2000) in bulk GaN and near 1.0 107 cm/s for sub-micron HFET devices (Ridley, et al. 2004). The discrepancy between theory and experimental velocity saturation was accounted for in bulk GaN as due to high defect density not accounted for in theory and in case of HFET devices as due to hot carrier effects. In addition, the wide bandgap and high breakdown field give the possibility or nitride application at both highfrequency and much higher power levels than Si or traditional III-V materials.

### **3. Fabrication of InGaN-based vertical type light emitting diodes**

The epitaxial layers were grown both on CSPSS and conventional sapphire substrate (CSS) by using a metal organic chemical vapour deposition (MOCVD). Figure 1 shows a schematic layer structure and procedure of fabricated VT-LEDs employing selective Ni electroplating and LLO techniques. The LED structure consists of an undoped GaN layer, a Si-doped n-GaN layer, five layers of InGaN/GaN multiple quantum well (MQW), and an Mg-doped p-GaN layer. The grown sample was patterned with 230 640 m2 size by a standard photolithographic process. The full mesas were defined by ICP-RIE from p-GaN to sapphire bottom to prevent GaN film from breaking due to different stress between sapphire and GaN film for LLO process. A metal scheme of Ni/Ag/Pt was deposited onto the p-GaN top surface to serve as p-ohmic contact and reflector metal. A TiW and Ti/Au layers were subsequently deposited as a barrier layer and an adhesive layer for the nickel electroplating. To sustain the remaining thin LED structure after the removal of sapphire substrate, the thickness of a nickel layer is around 80 m. To remove the sapphire substrate, a 248 nm KrF excimer laser with pulse width of 25 ns was used for LLO process. Finally, n-contact pad region was defined by ICP-RIE to expose the n-GaN layer and Cr/Au layer was then deposited on n-GaN without additional semitransparent contact layer. For the characterization of the surface morphology of the grown layers, we used a scanning electron microscope (SEM). The crystal quality of the grown films was investigated by both X-ray diffraction (XRD) and transmission electron-microscopy (TEM). The output power of the fabricated VT-LEDs was measured under DC bias at room temperature.

Fig. 1. Schematic layer structure (a) and procedure of fabricated VT-LEDs employing selective Ni electroplating and LLO techniques. (b) p-GaN ohmic contact/mirror layer and Ni electroplating processing, (c) Samples at the LLO processing stage. (b) Samples at the n-GaN ohmic contact processing.

#### **3.1 GaN film on patterned sapphire substrate**

Figure 2 shows a scanning electron microscope (SEM) image of the fabricated CSPSS process. The preparation of the CSPSS is as follows [Lee, et al. 2008]. After a photoresist (PR) with 3.5-μm thickness had been coated on a c-plane (0001) sapphire substrate, the PR was patterned first to be a rectangular shape [Fig. 2(a)] with different interval and reflowed during a hard-baking process at 140 ℃ to make a cone shape as shown in Fig. 2(b). The

*n-GaN*

*MQW P-GaN Adhesive/mirror layer*

**(b)** *Ni electroplating layer*

*CSPSS substrate*

*n-GaN*

*MQW P-GaN Adhesive/mirror layer*

*n-metal* **(d)**

*Ni electroplating layer*

Fig. 1. Schematic layer structure (a) and procedure of fabricated VT-LEDs employing selective Ni electroplating and LLO techniques. (b) p-GaN ohmic contact/mirror layer and Ni electroplating processing, (c) Samples at the LLO processing stage. (b) Samples at the n-

Figure 2 shows a scanning electron microscope (SEM) image of the fabricated CSPSS process. The preparation of the CSPSS is as follows [Lee, et al. 2008]. After a photoresist (PR) with 3.5-μm thickness had been coated on a c-plane (0001) sapphire substrate, the PR was patterned first to be a rectangular shape [Fig. 2(a)] with different interval and reflowed during a hard-baking process at 140 ℃ to make a cone shape as shown in Fig. 2(b). The

GaN ohmic contact processing.

*CSPSS*

**(c)**

**3.1 GaN film on patterned sapphire substrate**

*n-GaN*

*MQW*

**(a)** *P-GaN*

*CSPSS substrate*

*n-GaN*

*substrate*

*MQW P-GaN Adhesive/mirror layer*

*Ni electroplating layer*

sapphire substrate was then etched by using inductively coupled plasma reactive ion etching employing reactive Cl2 gas. The diameter and interval of each cone-shaped pattern were 3 and 1 μm, respectively. The height of the cone shape was about 1.5 μm. The epitaxial layers were grown both on CSPSS and conventional sapphire substrate (CSS) by MOCVD. In the initial stage of the growth on CSPSS, the GaN layer starts to grow only on the etched flat basal sapphire surface, quite differently from the growth mode on the conventional PSS, because there is no preferential growth plane on the cone-shape-patterned region. Similarly to the ELOG, this selective growth on CSPSS prevents the dislocation generated during the initial stage of the growth from propagating further into the patterned area when the growth proceeds laterally toward the cone region, decreases the dislocation density, and hence improves the crystal quality of the grown film.

Fig. 2. SEM images of the fabricated CSPSS process. (a) PR patterning, (b) reflow process, (c) fabricated CSPSS.

The time evolution of interference micrographs for a GaN surface grown on a CSPSS is shown in Fig. 3, i.e., after the growth of the initial buffer layer at low temperature [Fig. 3(a)], after temperature ramping (annealing the buffer layer) [Fig. 3(b)], and after 10- and 30-min growth of the epitaxial layer [Fig. 3(c) and (d)]. In general, the III-nitride layer preferentially grows on the (0001) crystallographic c-plane of a sapphire substrate. Although there is no growth plane in the cone-shape-patterned region, the low-temperature GaN amorphous buffer layer is well formed on the plane and patterned sapphire region as shown in Fig. 3(a).

Fig. 3. Time evolution of interference micrographs for a GaN surface grown on a CSPSS. (a) buffer, (b) annealing, (c) 10 min., (d) 30 min.

When the temperature increases from low temperature (550 ℃) to high temperature (1020 ℃) in the ramping stage of the growth, the random recrystallized GaN islands are formed on the etched flat basal sapphire surface, which is similar to a typical growth mode on the CSS. In the cone-shape-patterned region, however, the larger regular GaN islands are formed on the six corners of a hexagon-shaped cone as shown in Fig. 3(b), which explains that Ga species tend to migrate from the top region of the cone surface to the bottom region of the cone as increasing temperature (Simeonov, et al. 2006; Sugiura, et al, 1997; Sumiya, et al. 2003). In the initial stage of the high-temperature growth on the CSPSS, therefore, the coalescence starts on the etched flat basal sapphire surface, indicating that the growth mode on the CSPSS is considerably different from that on the conventional PSS such as stripe, hexagonal, or rectangular geometry. As expected, the growth of GaN on the CSPSS was only initiated from the etched basal surface with the (0001) crystallographic plane because there was no growth plane in the cone-shape patterned region as shown in Fig. 3(c). As the growth proceeds, the growth also laterally propagates toward the peak of the cone as shown in Fig. 3(d). This lateral growth greatly decreases the dislocation density in the grown film, similarly to the ELOG mode. This also enables reducing the time required in obtaining a smooth growth surface over the patterned region, compared to that for those grown on a conventional PSS, where the growth starts both on the etched and nonetched regions at the same time as shown in Fig. 4. Figure 5 (a) shows the cross-sectional TEM images under g = 0002 two-beam condition of the interface region between the CSPSS and a GaN layer grown on it, demonstrating that the ELOG-like mode on the CSPSS effectively suppresses the

Fig. 3. Time evolution of interference micrographs for a GaN surface grown on a CSPSS. (a)

When the temperature increases from low temperature (550 ℃) to high temperature (1020 ℃) in the ramping stage of the growth, the random recrystallized GaN islands are formed on the etched flat basal sapphire surface, which is similar to a typical growth mode on the CSS. In the cone-shape-patterned region, however, the larger regular GaN islands are formed on the six corners of a hexagon-shaped cone as shown in Fig. 3(b), which explains that Ga species tend to migrate from the top region of the cone surface to the bottom region of the cone as increasing temperature (Simeonov, et al. 2006; Sugiura, et al, 1997; Sumiya, et al. 2003). In the initial stage of the high-temperature growth on the CSPSS, therefore, the coalescence starts on the etched flat basal sapphire surface, indicating that the growth mode on the CSPSS is considerably different from that on the conventional PSS such as stripe, hexagonal, or rectangular geometry. As expected, the growth of GaN on the CSPSS was only initiated from the etched basal surface with the (0001) crystallographic plane because there was no growth plane in the cone-shape patterned region as shown in Fig. 3(c). As the growth proceeds, the growth also laterally propagates toward the peak of the cone as shown in Fig. 3(d). This lateral growth greatly decreases the dislocation density in the grown film, similarly to the ELOG mode. This also enables reducing the time required in obtaining a smooth growth surface over the patterned region, compared to that for those grown on a conventional PSS, where the growth starts both on the etched and nonetched regions at the same time as shown in Fig. 4. Figure 5 (a) shows the cross-sectional TEM images under g = 0002 two-beam condition of the interface region between the CSPSS and a GaN layer grown on it, demonstrating that the ELOG-like mode on the CSPSS effectively suppresses the

buffer, (b) annealing, (c) 10 min., (d) 30 min.

propagation of dislocation into the cone region, even though many dislocations were observed in the film grown on the basal plane of the sapphire. This reduction of dislocation was also confirmed by performing a cathodoluminescence (CL) measurement at room temperature as shown in Fig. 5(b, c). In bright regions, a radiative process dominates over a nonradiative process because of the lower density of structural defects. The dark spot density in the film grown on a CSS is roughly estimated to about 7 × 108 cm−2. Apparently, the dark spot density in the film grown on a CSPSS was decreased to about 2 × 108 cm−2 in number.

Fig. 4. Schematic view of the planarization of GaN grown on the conventional PSS and on the proposed CSPSS.

Fig. 5. TEM image (a) of a film grown on a CSPSS and CL image of (b) film grown on a CSS and (c) film grown on a CSPSS.

#### **3.2 Characteristics of GaN films on CSPSS**

Room temperature photoluminescence (PL) spectra for both InGaN/GaN samples grown on CSS and CSPSS are shown in Fig. 6. The band-edge emission intensity of the sample grown CSPSS was about four times higher in magnitude than that of the sample grown on CSS. The full width half maximum (FWHM) values of samples gown on CSS and CSPSS are 19 and 17

Fig. 6. PL measurements of InGaN/GaN films grown on a CSS and a CSPSS.

Fig. 7. Wafer bowing of films grown on CSS and CSPSS.

nm, respectively. In conjunction with a considerable enhancement in emission intensity and FWHM in PL, it is clear that the crystal quality of the film grown on CSPSS is improved. The typical corresponding spectral PL peak wavelength from the InGaN/GaN MQWs was shifted from 448 nm for film grown on CSS to 451 nm for film grown on CSPSS. In our previous work (Lee, et al. 2008), we reported that the surface geometry of CSPSS may be adequate for the easy relaxation of compressive strain during the growth on sapphire. The lattice constant c of films grown on CSPSS is very close to lattice constant of the bulk GaN of 5.185 Å, while the lattice constant of the GaN film grown on CSS exhibits a relatively large lattice constant. The slight red shift in PL for the film grown on CSPSS is due to the reduced band-gap energy which is caused by the decreased lattice constant c. The reduction of compressive stress in the films grown on CSPSS was also confirmed by thin film stress measurement using FLX-2320S as shown in Fig. 7. The bowing and stress of the 5.12 mthickness film grown on CSS were 34 m and -437 Mpa with sapphire Young's modulus of 4.08 MPa. On the other hand, the values were reduced to 28 m and -364 Mpa for the film with thickness of 5.48 m grown on CSPSS. Consequently, the ELOG-like mode for the GaN layer grown on CSPSS results in less lattice mismatch and incoherency between the GaN layer and the sapphire substrate.

#### **3.3 Role of electroplating**

64 Electroplating

**600 560 520 480 440 400 360**

**- CSS - CSPSS**

Fig. 6. PL measurements of InGaN/GaN films grown on a CSS and a CSPSS.

**2.2 2.4 2.6 2.8 3.0 3.2 3.4**

**1200 g/mm, 300 nm blaze**

**325-nm He-Cd laser (10 mW)**

**Photon energy (eV)**

**0 10 20 30 40 50**

**Distance (mm)**

**PMT Volt. 850 V Int. time: 200 ms slit: 20 um**

Fig. 7. Wafer bowing of films grown on CSS and CSPSS.

 CSS CSPSS

**10-4**

**0**

**5**

**10**

**15**

**Wafer bowing (um)**

**20**

**25**

**30**

**35**

**10-3**

**10-2**

**PL intensity (arb. units)**

**10-1**

**100**

**101**

**300 K**

High power GaN-based LEDs are essential for next-generation lighting applications. Essentially, maintain the effective power conversion efficiency (λ=Po/Pe, i.e., the ration of the light output power Po to the electrical power Pe) at a high injection current density is the key to boost their development. However, it is inevitable that the excessive Joule heating from the inherent parasitic resistance and current crowding due to the insulating sapphire substrate in the operation region would eventually decrease radiative recombination efficiency and in turn decrease light output power conversion efficiency. To resolve this situation, the use of a metallic substrate with laser lift-off technology to realize VT-LEDs has been proposed and has attracted much attention (Fujii, et al. 2004; Wang, et al. 2005; Wang, et al. 2006).

#### **3.4 Patterned Ni electroplating**

The electroplating process was conducted under a current of around 1.65A with the plating solution kept at about 55 ℃, which contains nickel sulphate, nickel chloride, boric acid, water, and some additives to improve surface roughness. The growth rate of nickel layer is about 1000 nm/min. Our experimental results reveal that a nickel layer with a thickness of about 60-80 μm is mechanically strong enough to sustain stress after the removal of sapphire substrate. Figure 8 shows the bowing of film after normal Ni electroplating. The curvature of the bowing increases as thickness of Ni electroplating is increases. This is because the residual compressive stress in the GaN layer, caused by different thermal expansion coefficients between the GaN film and the Ni electroplating substrate. Therefore, the appropriate condition of electroplating is required to prevent the bowing of film. To obtain a flat surface, a patterned Ni electroplating was proposed. Figure 9 shows the schematic view of patterned Ni electroplating. The stress between the GaN and the Ni electrode films was released by using the patterned electroplating through thicker photo resistor (PR), which is resulted in flat film as shown in Fig. 9 (b).

Fig. 8. The bowing of films after normal Ni electroplating.

Fig. 9. Proposed patterned Ni electroplating (a) schematics of patterned Ni electroplating, (b) The bowing of films after patterned Ni electroplating.

#### **3.5 Concaved surface transfer after Laser lift-off**

Figure 10 shows the formation of concaved surface transferred from CSPSS after LLO. To remove the sapphire substrate, A 248 nm KrF excimer laser with a single pulse of 25 ns. The incident laser fluence was set to a value of about 0.75J/cm2 which was based on our earlier established threshold laser fluence by taking into account the attenuation of sapphire and the reflection in the sapphire/GaN interface. The laser beam with a size of 1 mm 1mm was incident from the polished backside of the sapphire substrate into the sapphire/GaN interface to decompose GaN into Ga and N2. Figure 10 (b), (c) show the SEM images of top surface of CSPSS substrate and removed GaN films after the LLO process. A finite amount of Ga residues appears on the top surface of the GaN and CSPSS substrate. The remaining Ga droplets on the transferred GaN surface were removed by a wet chemical etching using diluted HCl:H2O (1:2) solution for 1 min. Figure 10 (d) shows the SEM photographs of top surface of removed GaN after the LLO process.

Fig. 8. The bowing of films after normal Ni electroplating.

*PR*

*CSPSS substrate*

*PR PR*

(a) (b)

*Ni Plating Metal*

(b) The bowing of films after patterned Ni electroplating.

**3.5 Concaved surface transfer after Laser lift-off**

*n-GaN p-GaN*

*Reflector metal*

*Ni Plating Metal*

surface of removed GaN after the LLO process.

Fig. 9. Proposed patterned Ni electroplating (a) schematics of patterned Ni electroplating,

Figure 10 shows the formation of concaved surface transferred from CSPSS after LLO. To remove the sapphire substrate, A 248 nm KrF excimer laser with a single pulse of 25 ns. The incident laser fluence was set to a value of about 0.75J/cm2 which was based on our earlier established threshold laser fluence by taking into account the attenuation of sapphire and the reflection in the sapphire/GaN interface. The laser beam with a size of 1 mm 1mm was incident from the polished backside of the sapphire substrate into the sapphire/GaN interface to decompose GaN into Ga and N2. Figure 10 (b), (c) show the SEM images of top surface of CSPSS substrate and removed GaN films after the LLO process. A finite amount of Ga residues appears on the top surface of the GaN and CSPSS substrate. The remaining Ga droplets on the transferred GaN surface were removed by a wet chemical etching using diluted HCl:H2O (1:2) solution for 1 min. Figure 10 (d) shows the SEM photographs of top

Fig. 10. SEM photographs of top surface (a) LED grown on CSPSS, (b) CSPSS top surface after LLO process, (c) removed n-GaN, (d) after the LLO process

#### **3.6 Surface treatment for higher extraction efficiency**

Figure 11 (a) shows the SEM image of the top surface of the concavely patterned undoped-GaN layer after LLO process, transferred from the original CSPSS, with a uniform depth and size. The effective surface area of concavely patterned surface of VT-LED increased to about 50 % compared to that of planar surface VT-LED. The number of the based circle was calculated at about 10,000 based on the interval of ~1 m and diameter of ~4 m in 230 640 m2 device size (the device is covered with concave pattern about 75% in whole area). This concavely patterned structure reduces also the total internal reflection of the generated light in the active region of the LED and effectively scatters the light outward. For an additional efficiency improvement, concavely patterned surface was further roughened to nano-size dot by etching in 2 M KOH electrolyte at 85 ℃ for 7 min and 15 min, as shown in figure 11(b), (c), respectively. Although circular holes were generated from the initial CSPSS, the chemical etch revealed hexagonal-shaped holes. This is a result of the hexagonal crystal structure of wurtzite GaN. Especially, the concave region shows an open hexagonal inverted pyramid form which is defined by the six {10-1-1} planes.

Fig. 11. SEM images of the top surface morphology removed GaN before(a) and after an etching time of 7 min(b) and 15 min(c) in 2M KOH at 85℃, respectively.

#### **3.7 Chip separation using femtosecond laser scribing**

Figure 12 shows schematics of a typical heat distribution in the substrate when the substrate is exposed to a focused long pulse and ultra fast short pulse laser beam. As the long pulse laser hits the substrate, the heat generated by the laser power greatly increases the temperature in the vicinity of the focused laser beam spot, locally melting the substrate, and further diffuses away into the material during the pulse duration, because the duration of laser pulse is longer than the heat diffusion time [Liu, et al. 1997; Lee, et al. 2010]. Therefore, the scribing speed is slower and fairly large amount of material droplet remains. However, when an ultrafast laser beam is used for the scribing, which is quite different from those of the long pulse laser beam. As the pulse widths decrease, the laser power intensity easily reaches hundreds of terawatts per square centimeter at the focused beam spot. The heataffected volume is much smaller because the duration of the laser pulse is shorter than the heat diffusion time. Therefore, the scribing speed is faster and there is no damage.

Fig. 11. SEM images of the top surface morphology removed GaN before(a) and after an

Figure 12 shows schematics of a typical heat distribution in the substrate when the substrate is exposed to a focused long pulse and ultra fast short pulse laser beam. As the long pulse laser hits the substrate, the heat generated by the laser power greatly increases the temperature in the vicinity of the focused laser beam spot, locally melting the substrate, and further diffuses away into the material during the pulse duration, because the duration of laser pulse is longer than the heat diffusion time [Liu, et al. 1997; Lee, et al. 2010]. Therefore, the scribing speed is slower and fairly large amount of material droplet remains. However, when an ultrafast laser beam is used for the scribing, which is quite different from those of the long pulse laser beam. As the pulse widths decrease, the laser power intensity easily reaches hundreds of terawatts per square centimeter at the focused beam spot. The heataffected volume is much smaller because the duration of the laser pulse is shorter than the

heat diffusion time. Therefore, the scribing speed is faster and there is no damage.

etching time of 7 min(b) and 15 min(c) in 2M KOH at 85℃, respectively.

**3.7 Chip separation using femtosecond laser scribing**

Fig. 12. Schematics of a typical heat distribution in the substrate when the substrate is exposed to a focused long pulse (a) and ultra fast short pulse (b) laser beam. (c) SEM images of the surface of Ni plating substrate after scribing with both nanosecond and femtosecond laser scribing in the same scribing time. (d) Chip separation by using femtosceond laser scribing process.

Figure 12 (c) shows SEM images of the surface of Ni plating substrate after scribing with both nanosecond and femtosecond laser scribing in the same scribing time. The scribing depth of femtosecond laser scribing showed a nearly sevenfold increase compared to that of nanosecond laser scribing. The fabricated VT-LEDs with 230 640 m2 size were separated by backside femtosceond laser scribing process as shown in Fig. 12 (d)

#### **3.8 Characteristic of fabricated V-T LED**

Figure 13 shows the current-voltage (I-V) characteristics of the fabricated VT-LED with the concavely patterned shape surface. Relatively low forward voltage (Vf =3.2 V) was observed at 20 mA operating current, with a very low reverse leakage current of -4 nA at -5 V. The insert of Fig. 13 shows the fabricated VT-LED with concave-patterned surface and the top view emission image under a driving current of 20 mA. Although it has a long length and the very small n-contact area for application of sideview LED in cellular phone, the current spreading reveals uniform over the total area. Due to a high electron mobility and conductivity

Fig. 13. I-V characteristics of the typical VT-LED. The top view emission images under a driving current of 20 mA in the inset.

Fig. 14. Light output power of planar surface VT-LEDs and concavely patterned surface VT-LED before and after additional chemical etching in KOH, respectively.

of the n-GaN, the injected electron spreads well in the n-GaN layer without a semitransparent contact layer. Figure 14 shows the light output power as a function of injection current for these four VT-LEDs. The total output power of the devices were measured by using sideview PKG without phosphor to collect the light emitted in all directions from the LEDs. All luminous intensity (L-I) curves showed the slow-saturated characteristics up to 200 mA in relatively small chip size. Because of the higher thermal conductivity of nickel compared to sapphire, these devices are advantageous for high power operation. It should be noted that the output power at 20 mA was estimated to be 1.7, 3.8, 4.5, and 4.3 mW for a planar surface VT-LEDs, concavely patterned surface VT-LED before and after additional chemical etching in KOH, respectively. As compared with the output power for a planar surface VT-LED, the concavely patterned surface VT-LED using HPS plus KOH etching (7 min) resulted in an increase of output power by a factor of 2.7. This significant enhancement in output power could be attributed to the increase of the extraction efficiency, resulted from the increase in photon escaping probability due to enhanced light scattering at the concavely patterned and roughened surface with random nano-size dot.

### **4. Conclusion**

70 Electroplating

Fig. 13. I-V characteristics of the typical VT-LED. The top view emission images under a

Fig. 14. Light output power of planar surface VT-LEDs and concavely patterned surface VT-

LED before and after additional chemical etching in KOH, respectively.

driving current of 20 mA in the inset.

In conclusion, The ELOG–like growth mode on the CSPSS effectively suppresses the probability of dislocation propagation into the cone region and hence greatly improves the crystal quality of the GaN films. The FWHM measured with asymmetric (102) rocking curves decreased from 338 arcsec for InGaN/GaN sample grown on CSS to 225 arcsec in the InGaN/GaN sample grown on CSPSS. To enhance light extraction efficiency, the use of a CSPSS is promising for the cost-effective production of better performing VT-LEDs. The output power of VT-LEDs with a concavely patterned surface is about 3.8 mW at a forward current of 20 mA, which is about 2.2 times higher than the devices with a flat surface. This improvement in the performance of VT-LEDs is attributed to the increase in the escaping probability of photons from the corrugated LED surface as well as the use of metal substrate.

#### **5. Acknowledgment**

The author thanks Dr. Jeong-Wook Lee and Mr. In-Suck Choi, Samsung LED Co., LTD., for their useful discussions.

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## **Integration of Electrografted Layers for the Metallization of Deep Through Silicon Vias**

Frederic Raynal *Alchimer S.A., France*

#### **1. Introduction**

74 Electroplating

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reduction via lateral epitaxy in selectively grown GaN structures, Appl. Phys. Lett.,

After many years as a hypothetical possibility, 3D integrated circuits (3D IC) stacking has emerged as a potential key enabler for maintaining semiconductor performance trends. Implementing 3D, however, will almost certainly require development of through-silicon vias (TSVs), which in the past few years have been elevated by the semiconductor industry to the status of a crucial mainstream technology.

TSVs sit at the foundation of the 3D-IC revolution and are a key enabler for extending semiconductor integration trends into a new phase. Integrated device manufacturers and fabless design houses need small, high-density, fine-pitch vias for improved signal integrity and Si real-estate savings. They need them now, and cannot wait for very thin wafer processing and handling technologies to become mainstream – TSVs must cope with current mainstream wafer thickness.

Deep TSVs with aspect ratio (AR) greater than 15:1 elegantly fulfill both requirements. But they cannot be manufactured with acceptable yield/cost using traditional dry processes for liner, barrier and seed deposition. Chemical and physical vapor deposition (CVD, PVD) techniques show basic shortcomings and impose high capital investments, holding back the industry-wide adoption of 3D-IC solutions. Beyond that, physical limitations of PVD and CVD techniques prevent reaching a good step coverage of the deposited layers inside the vias (step coverage is defined by the ratio between thickness deposited on top vs. bottom of the vias), which is required to perform void-free gap filling of electroplated copper.

Electrografting (eG) and chemical grafting (cG) (Bureau et al., 1999; Palacin et al., 2004; Pinson & Podvorica, 2005; Voccia et al., 2006; Belanger & Pinson, 2011) are two fundamental molecular engineering technologies, delivering high-quality films for high-AR (HAR) TSVs (Suhr et al., 2008). The term "grafting" indicates the formation of strong chemical bonds at the molecular level between the underlaying layer's extreme surface (e.g., silicon) and the film being grown from the surface out (e.g., the isolation liner).

This nanotechnology solution generates surface-initiated conformal films which are thin, continuous, adherent and uniform. They are wet-process techniques, operated in standard plating tools, which have proven their efficiency to deposit ultra-thin (< 10nm) seed layers on PVD (Haumesser et al., 2003, 2004; Raynal et al., 2006) or atomic layer deposition (ALD) (Shih et al., 2004; Shue, 2006) diffusion barriers for interconnect back end of line (BEOL) applications.

#### **1.1 Electrografting (eG) and chemical grafting (cG) mechanisms**

Electrografting is based on surface chemistry formulations and processes. It is applied to conductive and semiconductive surfaces, and enables self-oriented growth of thin coatings of various materials, initiated by in-situ chemical reactions between specific precursor molecules and the surface. Contrary to electrodeposition which requires a potential supply throughout deposition to fuel the redox processes, electrografting is an electro-initiated process which requires a charged electrode only for the grafting step, but not for the thickening. As eG is mainly (but not only) a cathodic process, it can generally be applied to various metallic and semiconducting surfaces without any concern over oxide formation.

Electrografting of vinylic polymers onto conducting surfaces has historically been achieved via a direct electron transfer from the cathode to the electro-active monomers in solution. In this approach, eG occurs when vinylic monomers such as acrylonitrile (AN), methacrylonitrile (MAN), vinylpyridine (VP), and methyl methacrylate (MMA), all members of the family of electron-deficient alkenes, are submitted to reductive electrolysis, with a classical three-electrode setup in an anhydrous organic medium (Deniau et al., 1992a). Strictly anhydrous conditions are required here because the resulting radical-anion, together with the anions that allow the propagation of the growing grafted polymer chains, are highly sensitive to proton sources.

Fig. 1. Schematic representation of radical polymerization electrografting process.

Radical polymerization does not suffer the same drawback and is easily performed in protic conditions (Deniau et al., 2006). Mechanisms of radical polymerization (Tessier et al., 2009) presented in fig. 1 show that polymer electrografting is an electro-induced grafting process followed by a purely chemical propagation step. The first electro-induced step is crucial to form the chemical bond between the polymer and the surface. A specific organic precursor (B) is used both to form a first primer grafted layer and to initiate the polymerization of the vinyl monomer (A) in solution. The termination step of the polymerization leads to the grafting of macromolecular chains (-[A-A-A]n-B) onto the first primer grafted layer.

Chemical grafting is based on the same fundamental mechanisms as electrografting, and is used on any surface (including non-conductive surfaces), electron being replaced by a reducing agent (Mevellec et al., 2007).

#### **1.2 Benefits of electrografting (eG)**

Electrodeposition has been known for years for coating conducting surfaces with metals. Electroplating (Kanani, 2005; Schlesinger & Paunovic, 2010) is currently the most widely used method for coating surfaces in many industries (automotive, petrochemical, aerospace) including printed circuit boards, vias and copper interconnections for electronics.

Electrografting is based on surface chemistry formulations and processes. It is applied to conductive and semiconductive surfaces, and enables self-oriented growth of thin coatings of various materials, initiated by in-situ chemical reactions between specific precursor molecules and the surface. Contrary to electrodeposition which requires a potential supply throughout deposition to fuel the redox processes, electrografting is an electro-initiated process which requires a charged electrode only for the grafting step, but not for the thickening. As eG is mainly (but not only) a cathodic process, it can generally be applied to various metallic and semiconducting surfaces without any concern over oxide formation. Electrografting of vinylic polymers onto conducting surfaces has historically been achieved via a direct electron transfer from the cathode to the electro-active monomers in solution. In this approach, eG occurs when vinylic monomers such as acrylonitrile (AN), methacrylonitrile (MAN), vinylpyridine (VP), and methyl methacrylate (MMA), all members of the family of electron-deficient alkenes, are submitted to reductive electrolysis, with a classical three-electrode setup in an anhydrous organic medium (Deniau et al., 1992a). Strictly anhydrous conditions are required here because the resulting radical-anion, together with the anions that allow the propagation of the growing grafted polymer chains,

> S u b s t r a t e

Sub s t r a t e

or <sup>A</sup>

Radical polymerization does not suffer the same drawback and is easily performed in protic conditions (Deniau et al., 2006). Mechanisms of radical polymerization (Tessier et al., 2009) presented in fig. 1 show that polymer electrografting is an electro-induced grafting process followed by a purely chemical propagation step. The first electro-induced step is crucial to form the chemical bond between the polymer and the surface. A specific organic precursor (B) is used both to form a first primer grafted layer and to initiate the polymerization of the vinyl monomer (A) in solution. The termination step of the polymerization leads to the

Chemical grafting is based on the same fundamental mechanisms as electrografting, and is used on any surface (including non-conductive surfaces), electron being replaced by a

Electrodeposition has been known for years for coating conducting surfaces with metals. Electroplating (Kanani, 2005; Schlesinger & Paunovic, 2010) is currently the most widely used method for coating surfaces in many industries (automotive, petrochemical, aerospace)

A A **polymerization**

Fig. 1. Schematic representation of radical polymerization electrografting process.

grafting of macromolecular chains (-[A-A-A]n-B) onto the first primer grafted layer.

including printed circuit boards, vias and copper interconnections for electronics.

**B**

**B**

A

A A **B**

**1.1 Electrografting (eG) and chemical grafting (cG) mechanisms**

are highly sensitive to proton sources.

S u b s t r a t e

Sub s t r a t e

reducing agent (Mevellec et al., 2007).

**1.2 Benefits of electrografting (eG)**

**e**

**B**

**B**

Starting in the 80's with the electrochemical reduction of acrylonitrile on a metallic cathode (Lecayon et al., 1982), electrografting is a relatively new technique, with two major differences compared to electrodeposition: (I) eG being an electro-initiated process, i.e. a process in which Faradaïc electrochemical reactions are coupled to a range of non-Faradaïc chemical reactions, current densities applied for thickening are lower than the current densities required by electrodeposition techniques; and (II) the initial charge transfer to the first monomers leads to the formation of a direct covalent bond between some surface atoms and carbon atoms of the polymeric backbone.

Lower current densities applied are a benefit of electrografting technology when applied to resistive underlaying layers, coatings being more uniform and less sensitive to the ohmic drop involved by underlaying layer resistivity (Gonzalez et al., 2006; Mevellec, 2010).

Direct covalent bonds achieved between coatings and surfaces involve highly adherent electrografted films, via very strong substrate-molecules links, studied by quantum chemistry simulations (Bureau et al., 1996). Experimental evidence of those covalent bonds is not an easy task, and has been demonstrated by XPS analysis technique. As reported in (Deniau et al., 1992b), XPS measurements on very thin eG films exhibit a low-energy shoulder in the C1s signal. This peak cannot be observed for thicker films because it is buried under the strong C1s signals arising from the grafted polymer itself. The corresponding binding energy (283.6 eV) was later attributed to the carbon-nickel bond that links the polymer chain to the Ni electrode (Bureau et al., 1994).

#### **2. Complete metallization of high aspect ratio (HAR) TSVs using electrografting**

Aspect ratio is defined by the ratio between the diameter of the via and its depth, and a ratio greater than 10:1 defines the HAR TSVs category. Producing these vertical connections is achieved by: drill a blind hole through the silicon wafer, deposit a uniform liner layer of dielectric material to electrically isolate the via, deposit a barrier layer to prevent copper from diffusing into silicon, and then completely fill the via with electro-chemically deposited (ECD) copper. Chemical mechanical polishing (CMP) and wafer-thinning steps conclude the sequence.

#### **2.1 Comparison between dry and wet TSVs metallization scheme**

While the process flow to metallize TSVs is relatively simple, the industry's conventional approach to bringing it into volume production is, in essence, a patchwork of dry process equipment and consumables, such as plasma-enhanced CVD (PE-CVD), ionized PVD (iPVD), and ALD, which were originally designed for dual-damascene applications. One of the main benefits of electrografting is its large reduction in cost of ownership per wafer with respect to conventional dry approaches (Lerner, 2008; Truzzi & Lerner, 2009).

Comparison between dry and wet TSVs metallization scheme is presented in fig. 2. Two schemes are available for electrografting : (1) the deposition of the full stack "wet isolation/ NiB barrier/ Cu seed layer", followed by Cu filling using typical acidic Cu fill chemistry; (2) the deposition of "wet isolation / NiB barrier" followed by Cu filling using a new TSVgrade Cu fill chemistry. Path (2) is preferred because it requires only three steps (instead of four), which involves less cost and higher throughpout.

Fig. 2. Comparison between dry and wet (electrografting) TSVs metallization scheme.

#### **2.1.1 Description of electrografting path 1 for TSVs metallization**

A polymer layer is directly grafted onto the silicon surface, yielding a highly conformal and adherent coating. This first grafted layer acts as an insulating layer (fig. 3a) as well as an adhesion promoter for the subsequent barrier layer deposition, performed by chemical grafting (cG).

Chemical grafting is based on the same fundamental mechanisms as electrografting, and is used on non-conductive surfaces. Specific chemical groups have been chosen to strongly bond the barrier activator with the polymer. This improves adhesion between the barrier and the polymer through a chemical grafting step - it creates a chain of chemical bonds from the substrate to the barrier. The barrier film (fig. 3b) consists of a NiB alloy. Activation of the electrografted insulating layer is carried out at ambient temperature using a metallic catalyst.

Fig. 3. SEM cross sections of wet insulator (I), NiB barrier (II) and Cu seed layer (III) electrografted on top of silicon surface.

A bath containing specific organics and copper is used to deposit a Cu seed layer (fig. 3c) on the NiB barrier by means of the same electrografting technique. An electrochemical process is applied to provide a conformal and continuous Cu seed layer directly on the NiB barrier.

Both NiB barrier and Cu seed layer can also be deposited on top of dry dielectrics, as for example SiO2, SiC, SiOC or SiN. SEM cross-sections of barrier and Cu seed deposited on top of SiO2 are reported in fig. 4.

The electrografted copper seed is also directly applicable to various dry-deposited diffusion barriers, without any adhesion promoter in between (Ledain et al., 2008; Raynal et al., 2009).

Barrier (iPVD, CVD, ALD)

> Barrier (cG)

Barrier (cG)

Cu Seed (iPVD)

Cu Seed (eG)

Cu Fill (ECD)

Cu Fill (ECD)

I

II III

Cu Fill (New TSV-grade chemistry)

Fig. 2. Comparison between dry and wet (electrografting) TSVs metallization scheme.

A polymer layer is directly grafted onto the silicon surface, yielding a highly conformal and adherent coating. This first grafted layer acts as an insulating layer (fig. 3a) as well as an adhesion promoter for the subsequent barrier layer deposition, performed by chemical

Chemical grafting is based on the same fundamental mechanisms as electrografting, and is used on non-conductive surfaces. Specific chemical groups have been chosen to strongly bond the barrier activator with the polymer. This improves adhesion between the barrier and the polymer through a chemical grafting step - it creates a chain of chemical bonds from the substrate to the barrier. The barrier film (fig. 3b) consists of a NiB alloy. Activation of the electrografted insulating layer is carried out at ambient temperature using a metallic

Fig. 3. SEM cross sections of wet insulator (I), NiB barrier (II) and Cu seed layer (III)

Silicon

A bath containing specific organics and copper is used to deposit a Cu seed layer (fig. 3c) on the NiB barrier by means of the same electrografting technique. An electrochemical process is applied to provide a conformal and continuous Cu seed layer directly on the NiB barrier. Both NiB barrier and Cu seed layer can also be deposited on top of dry dielectrics, as for example SiO2, SiC, SiOC or SiN. SEM cross-sections of barrier and Cu seed deposited on top

I

c

II

silicon silicon

The electrografted copper seed is also directly applicable to various dry-deposited diffusion barriers, without any adhesion promoter in between (Ledain et al., 2008; Raynal et al., 2009).

**2.1.1 Description of electrografting path 1 for TSVs metallization**

b

Insulator (PE-CVD)

Insulator (eG)

Insulator (eG)

Conventional

Electrografting path 1

Electrografting path 2

grafting (cG).

catalyst.

a

electrografted on top of silicon surface.

of SiO2 are reported in fig. 4.

silicon <sup>I</sup>

Fig. 4. SEM cross sections of NiB barrier (II) and Cu seed layer (III) electrografted on top of SiO2 (I) surface.

Fig. 5. SEM cross sections of high aspect ratio via (AR 18:1, 4µm x 72µm) coated with electrografted layers; (a) top of via, (b) via middle, (c) via bottom.

Electrografting and chemical grafting formulations and processes fulfill all standard wafer fab requirements and safety guidelines and have been developed and specifically tailored for TSV diameters ranging from 1 to 200 µm, covering a depth/diameter AR range from 2:1 to 20:1 (fig. 5). Higher ARs are possible.

Electrografted and chemical grafted layers, activated from the surface, are not sensitive to its topography, and fit perfectly well with the highly scalloped TSVs sidewalls induced by Bosch etching process (fig. 6).

Fig. 6. SEM cross sections of wet insulator (I), NiB barrier (II) and Cu seed layer (III) on top of scalloped silicon surface.

Wet TSVs metallization process is scalable up to 12inch wafers, as illustrated in fig. 7 with three 12inch wafers stopped at different steps of the metallization process.

Fig. 7. Top view of 12inch wafers with various layers electrografted on them; (a) wet insulator; (b) wet insulator / NiB barrier; (c) wet insulator / NiB barrier / Cu seed layer.

#### **2.1.2 Description of electrografting path 2 for TSVs metallization**

Wet insulator and NiB barrier deposition remains exatly the same as in path 1.

Filling narrow, deep vias without voids is not an easy task. Most commercialy available chemistries encounter problems due to the sheet resistance (Rs) of the underlying layer, and this is the reason why Cu-seed layers are required. However, because of the extremely poor

Electrografted and chemical grafted layers, activated from the surface, are not sensitive to its topography, and fit perfectly well with the highly scalloped TSVs sidewalls induced by

b

Fig. 6. SEM cross sections of wet insulator (I), NiB barrier (II) and Cu seed layer (III) on top

I

III

II

silicon

Wet TSVs metallization process is scalable up to 12inch wafers, as illustrated in fig. 7 with

c

Fig. 7. Top view of 12inch wafers with various layers electrografted on them; (a) wet insulator; (b) wet insulator / NiB barrier; (c) wet insulator / NiB barrier / Cu seed layer.

b

Filling narrow, deep vias without voids is not an easy task. Most commercialy available chemistries encounter problems due to the sheet resistance (Rs) of the underlying layer, and this is the reason why Cu-seed layers are required. However, because of the extremely poor

**2.1.2 Description of electrografting path 2 for TSVs metallization**

Wet insulator and NiB barrier deposition remains exatly the same as in path 1.

three 12inch wafers stopped at different steps of the metallization process.

a

Bosch etching process (fig. 6).

II

of scalloped silicon surface.

I

silicon

a

step coverage of dry-process barriers and seed layers (< 10%), sheet resistance values at the bottom of the via are very high, making it difficult to initiate the filling process.

Via filling completion directly from the barrier requires barrier layers with low resistivity values, and copper plating chemistries with low sensitivity to ohmic drop. NiB barrier has been selected because of its barrier properties (see section 2.2.2.), and because Ni-based barrier films present much lower resistivity values than conventional dry barriers (fig. 8). Indeed, NiB chemical grafting barrier formulations have been optimized to reduce the resistivity value below 25µΩ.cm; this value makes it possible to eliminate Cu seed layers, and sets the stage for direct fill of TSVs from the barrier layer, further simplifying the TSV process sequence.

Fig. 8. Resistivity range of conventional dry barriers, compared with chemically grafted (cG) NiB barrier.

Today, a new mildly basic TSV plating chemistry is available to fill the vias (Truzzi, 2010) based on the same nanotechnology concept described in this paper. This TSV-grade chemistry is not sensitive to the sheet resistance of the underlying layer, and can be applied over Rs values up to 50 Ω/sq. It is fully compatible with industry standard wet-process tools and, in contrast with ECD solutions, it does not attack or degrade the underlying layer.

Some examples of copper filling in various TSV dimensions, achieved directly from the NiB barrier, are presented in fig. 9. The new TSV-grade Cu fill chemistry has been used in all cases. Fig. 9a shows an example of copper filling achieved in different TSV dimensions at the same time, which demonstrates the wide process window of this new TSV-grade chemistry regarding vias size.

#### **2.2 Properties of electrografted wet insulator layer, NiB barrier layer, Cu seed layer and new TSV-grade Cu fill chemistry**

Film thickness can be controlled to any value from 40 to 400 nm with maximum nonuniformity of 5% within wafer (300mm). This provides a step coverage value (bottom/top thickness ratio) up to 90% for liner and metal layers. As a reference, typical dry-process barrier step coverage values are lower than 10% for 10:1 aspect ratio TSVs. Adhesion of all layers was measured using a 16-squares scribe tape test method: all layers successfully passed the test. Film properties of each layer, as well as reliability test results, are discussed in detail in (Truzzi et al., 2009; Raynal et al., 2010). Selected basic film properties are summarized in table 1.

Table 1. Selected film properties of electrografted wet isolation, NiB barrier, Cu seed layer and new TSV-grade Cu fill, compared with industry baseline.

**Parameter Value Unit Notes Wet insulator**

Dielectric constant 3 SiO2 = 4.2 Breakdown Voltage 28 MV/cm SiO2 = 10

Leakage current 15 nA/cm2 SiO2 = 10-20 Surface Finish 1.6 Nm SiO2 = 2

Young Modulus 3.4 Gpa SiO2 = 107 Stress @ 200nm 10 Mpa SiO2 = 100 Moisture Absorption < 1% 168hrs @ 90%RH TGA (1hr/temp. point) 450 °C <4% mass loss

Chemical purity (at%) S,F,Ca,Na,K : 0 Cl : 0.2

**NiB barrier**  Resistivity 25 µOhm.cm TiN = 100-250

**Cu seed layer** Resistivity 1.8 µOhm.cm ECD-Cu = 1.8

**New TSV-grade Cu fill** Resistivity 1.8 µOhm.cm ECD-Cu = 1.8

Table 1. Selected film properties of electrografted wet isolation, NiB barrier, Cu seed layer

Grain size 110 Nm ECD-Cu = 100

Barrier property Equivalent to TiN after 400 ºC 2 hours

Hardness 14.3 GPa TiN = 25 Stress 200 MPa TaN = 1500

Organic polymer : 99.8

thickness TaN/Ta = 54

Cl : 100x less than baseline plating chemistries C : 10x less than baseline plating chemistries S : equivalent to baseline plating chemistries

TiN =-750

CTE 30 ppm/ºC

Capacitance Density 0.13 fF/µm2

Substrate resistivity < 200 Ohm.cm

Contact angle 50%

Cu penetration after

ECD gap-fill

Chemical purity

Rs uniformity 5 %

Rs uniformity 5 %

Stress 50 MPa

Rs uniformity 5 %

Stress 50 MPa

and new TSV-grade Cu fill, compared with industry baseline.

compatibility No voids

Copper gap-fill No voids

400°C 2 hours 42 % barrier

Fig. 9. SEM cross sections of copper filling achieved with the new TSV-grade Cu fill chemistry, directly from NiB barrier; (a) filling of various TSV dimensions (via diameter 3.5µm to 12µm, AR 4.5:1 to 11:1); (b) filling of TSVs 5µm x 50µm (AR 10:1); (c) middle depth of filled TSVs 5µm x 50µm, showing wet insulator layer (I); (d) via bottom of filled TSVs 5µm x 50µm, showing wet insulator layer (I).

#### **2.2.1 Properties of wet insulator**

Electrical properties of wet insulator have been characterized using conventional mercury probe analysis tool. Fig. 10 presents a typical C(V) curve recorded with the stack wet insulator / Si p-doped. Dielectric constant calculed from this curve is 3. Breakdown voltage, leakage current and capacitance density have been measured from I(V) curves performed with the same mercury probe analysis method.

Thickness of the wet insulator is measured by ellipsometry. Examples of typical n=f() and k=f() curves recorded with wet insulator are presented in fig. 11. According to n=f() curve, refractory index is measured in the range 1.7-1.8nm.

Fig. 10. Typical C(V) curve of the stack wet insulator / Si p-doped.

Fig. 11. Typical (a) n=f() and (b) k=f() curves recorded with wet insulator.

CTE (coefficient of thermal expansion) of the wet insulator is measured using an ellipsometer linked to a heater. As presented in fig. 12, a CTE of 30ppm/°C is measured for wet insulator, 30ppm/°C being the mean value obtained on four different samples. On each sample, CTE was measured after one cycle of sample warm and cool.

Wet insulator being a polymer, Tg value can be deducted from CTE curves (Fryer et al., 2001). Indeed, wet insulator thickness evolution vs. temperature being linear from 50°C to 200°C, this means that no microstructural reorganization is observed in this range of temperatures, and Tg value of the wet insulator is higher than 200°C.

Reduced modulus has been measured using nanoindentation analysis technique, with a maximum force applied of 5000 nN and a maximum indenting depth of 35 nm.Typical curve of force vs. penetration depth is presented in fig. 13a, Young modulus characterization being achieved during the loading of the indentor inside the wet insulator. Young modulus measurement of 4.05 GPa is the mean value of 15 measurements (fig. 13b).

voltage

Fig. 10. Typical C(V) curve of the stack wet insulator / Si p-doped.

capacitance

Fig. 11. Typical (a) n=f() and (b) k=f() curves recorded with wet insulator.

sample, CTE was measured after one cycle of sample warm and cool.

temperatures, and Tg value of the wet insulator is higher than 200°C.

measurement of 4.05 GPa is the mean value of 15 measurements (fig. 13b).

CTE (coefficient of thermal expansion) of the wet insulator is measured using an ellipsometer linked to a heater. As presented in fig. 12, a CTE of 30ppm/°C is measured for wet insulator, 30ppm/°C being the mean value obtained on four different samples. On each

a

b

Wet insulator being a polymer, Tg value can be deducted from CTE curves (Fryer et al., 2001). Indeed, wet insulator thickness evolution vs. temperature being linear from 50°C to 200°C, this means that no microstructural reorganization is observed in this range of

Reduced modulus has been measured using nanoindentation analysis technique, with a maximum force applied of 5000 nN and a maximum indenting depth of 35 nm.Typical curve of force vs. penetration depth is presented in fig. 13a, Young modulus characterization being achieved during the loading of the indentor inside the wet insulator. Young modulus

Fig. 12. Coefficient of thermal expansion (CTE) measured with wet insulator.

Fig. 13. (a)Typical curve of force vs. penetration depth recorded by nanoindentation analysis of wet insulator; (b) values obtained on 15 measurements.

Thermo-Gravimetry Analysis (TGA) has been performed to check the stability of the wet insulator under thermal stress. Experimental conditions are the following: anneal is achieved under nitrogen atmosphere, for a duration of one hour at each selected temperature. Range of analysis is 300°C – 500°C, with a step of 50°C between each experiment. Fig. 14 shows that less than 1% of mass loss is measured after 350°C applied during one hour to the wet insulator, and less than 4% after 450°C applied during one hour.

Fig. 14. Mass loss of the wet insulator as a function of temperature (1h / temp. point).

#### **2.2.2 Properties of NiB barrier**

Barrier property is measured by TOF-SIMS depth profile, after anneal of the complete stack (wet insulator / NiB barrier / copper) to 400°C during 2 hours under forming gas. Analysis is performed starting from the front side (copper) of the sample, or from the backside (silicon) of it. In the case of a start from the back side, a mechanical polishing and grinding of the sample is first performed to reduce silicon bulk thickness.

Examples of TOF-SIMS depth profiles are shown in fig. 15, x axis being representative of sample depth and y axis being proportional to compound quantity. Barrier property is quantified by the difference between NiB barrier and copper signals. The better is the barrier property, the higher is this difference.

Fig. 15. ToF-SIMS depth Profile of Cu layer (100nm) on top of NiB barrier (40nm) and wet insulator (200 nm) after anneal to 400°C during 2 hours using (a) front side and (b) back side analysis.

As shown in fig. 15b, diffusion of Cu atoms occurred only into the NiB barrier layer. Cu atoms are effectively blocked by this layer, which prevents diffusion into the wet insulator and the silicon substrate. NiB film acts as a very efficient copper diffusion barrier, and a proven surface for subsequent Cu deposition.

Porosity of the barrier has been checked using a method based on the chemical attack of SiO2 by Hydrofluoridric Acid (HF) solutions. The stack PE-CVD SiO2 / NiB barrier (200nm / 50nm) has been deposited on top of a Silicon substrate, the whole stack being dipped into HF 1% during 5 minutes. After this chemical treatment, if some porosity is present into the NiB barrier, than HF is going to diffuse in it, and attack the underlaying layer SiO2. Fig. 16 demonstrates that no attack of the underlaying layer SiO2 is observed after dipping in HF, and therefore NiB barrier is not porous.

#### **2.2.3 Properties of Cu seed layer**

A bath containing specific organics and copper is employed to deposit a Cu seed layer on NiB barrier by means of the same electrografting technique. The electrografted copper seed is also directly applicable to various dry-deposited diffusion barriers, without any adhesion promoter in between. Table 2 summarizes the dry diffusion barriers that have been successfully tested with the eG Cu seed layer technology. No instance of incompatibility between a diffusion barrier and eG Cu seed has been reported so far.

86 Electroplating

Barrier property is measured by TOF-SIMS depth profile, after anneal of the complete stack (wet insulator / NiB barrier / copper) to 400°C during 2 hours under forming gas. Analysis is performed starting from the front side (copper) of the sample, or from the backside (silicon) of it. In the case of a start from the back side, a mechanical polishing and grinding

Examples of TOF-SIMS depth profiles are shown in fig. 15, x axis being representative of sample depth and y axis being proportional to compound quantity. Barrier property is quantified by the difference between NiB barrier and copper signals. The better is the barrier

Fig. 15. ToF-SIMS depth Profile of Cu layer (100nm) on top of NiB barrier (40nm) and wet insulator (200 nm) after anneal to 400°C during 2 hours using (a) front side and (b) back side

As shown in fig. 15b, diffusion of Cu atoms occurred only into the NiB barrier layer. Cu atoms are effectively blocked by this layer, which prevents diffusion into the wet insulator and the silicon substrate. NiB film acts as a very efficient copper diffusion barrier, and a

Porosity of the barrier has been checked using a method based on the chemical attack of SiO2 by Hydrofluoridric Acid (HF) solutions. The stack PE-CVD SiO2 / NiB barrier (200nm / 50nm) has been deposited on top of a Silicon substrate, the whole stack being dipped into HF 1% during 5 minutes. After this chemical treatment, if some porosity is present into the NiB barrier, than HF is going to diffuse in it, and attack the underlaying layer SiO2. Fig. 16 demonstrates that no attack of the underlaying layer SiO2 is observed after dipping in HF,

A bath containing specific organics and copper is employed to deposit a Cu seed layer on NiB barrier by means of the same electrografting technique. The electrografted copper seed is also directly applicable to various dry-deposited diffusion barriers, without any adhesion promoter in between. Table 2 summarizes the dry diffusion barriers that have been successfully tested with the eG Cu seed layer technology. No instance of incompatibility

between a diffusion barrier and eG Cu seed has been reported so far.

of the sample is first performed to reduce silicon bulk thickness.

Si

a) b)

**2.2.2 Properties of NiB barrier**

property, the higher is this difference.

analysis.

Cu

Intensity (counts)

Echantillon TiN

Insulator NiB

0 500 1000 1500 2000 2500 3000 3500 4000 4500 Time (seconde)

proven surface for subsequent Cu deposition.

and therefore NiB barrier is not porous.

**2.2.3 Properties of Cu seed layer**

Fig. 16. Demonstration of the non porosity of NiB barrier by dipping the stack SiO2 / NiB in HF 1%; (a) before HF dip and (b) after HF dip.

Table 2. Compatibility of dry diffusion barriers with electrografting technology.

An example of electrografted copper seed deposited in 5µm x 50µm (AR 10:1) TSVs coated with CVD TiN is presented in fig. 17. Step coverage (step coverage is defined by the ratio between thickness deposited on top vs. bottom of the vias) of eG copper seed deposited inside those TSVs is close to 90%.

Copper grain size of eG copper seed deposited on top of dry barriers had been previously characterized in (Raynal et al., 2009). These measurements were re-visited in the case of eG copper seed deposited on top of cG barrier, with similar results obtained by XRD, EBSD and self anneal rate. One example of EBSD measurement is shown in fig. 18.

Fig. 17. SEM cross sections of eG copper seed deposited in 5µm x 50µm (AR 10:1) TSVs coated with CVD TiN: (a) overview; (b) via top (109nm of eG copper); (c) sidewalls (129nm of eG copper); (d) via bottom (98nm of eG copper).

Fig. 18. EBSD picture of eG copper seed layer deposited on top of NiB barrier.

Several studies of PVD copper microstructure have been performed in the past, especially when PVD Cu is deposited on top of PVD Ta. In this case, a strong (111) texture of the copper is reported in the literature, linked to the heteroepitaxial growth of Cu on (002) orientation of Ta. This heteroepitaxial relationship is observed between Cu and Ta, but not with TiN barriers (Wong et al., 1998).

Copper microstructure has been compared between PVD copper deposited on top of TiN barrier and eG copper seed deposited on top of NiB barrier. In both cases, weak (111) orientation of the copper layer is measured.

A summary of eG copper resistivity evolution vs. layer thickness is presented in fig 19. The trend reported in fig. 19 is similar to PVD copper layers (Barnat & Lu, 2001), copper resistivity below 100nm thick being impacted by grain boundary and surface scattering.

Fig. 19. eG copper resistivity vs. layer thickness.

Fig. 18. EBSD picture of eG copper seed layer deposited on top of NiB barrier.

with TiN barriers (Wong et al., 1998).

orientation of the copper layer is measured.

1

Fig. 19. eG copper resistivity vs. layer thickness.

10

**resistivity (µohm.cm)**

100

Several studies of PVD copper microstructure have been performed in the past, especially when PVD Cu is deposited on top of PVD Ta. In this case, a strong (111) texture of the copper is reported in the literature, linked to the heteroepitaxial growth of Cu on (002) orientation of Ta. This heteroepitaxial relationship is observed between Cu and Ta, but not

Copper microstructure has been compared between PVD copper deposited on top of TiN barrier and eG copper seed deposited on top of NiB barrier. In both cases, weak (111)

A summary of eG copper resistivity evolution vs. layer thickness is presented in fig 19. The trend reported in fig. 19 is similar to PVD copper layers (Barnat & Lu, 2001), copper resistivity below 100nm thick being impacted by grain boundary and surface scattering.

> 0 100 200 300 400 500 **thickness (nm)**

Thermal treatments need to be done to decrease copper layer resistivity and to reach the value of 1.8µΩ.cm for layers thicker than 100nm. This phenomenon is related to grain size growth during annealing, which can be observed by XRD or EBSD analysis techniques.

Successful Cu gap fillings have been demonstrated, starting from eG copper seed, in a wide range of TSV dimensions. Those results have been achieved with conventional acidic plating chemistries. SEM cross-sections presented in fig. 20 show some examples of void-free gap fillings, starting from eG copper layers with a step coverage between 60% and 90%, in the case of both 20µm x 75µm and 50µm x 100µm TSVs.

Fig. 20. SEM cross sections of TSVs filled with conventional acidic plating solutions, starting from eG copper seed: (a) 20µm x 75µm TSVs; (b) 50µm x 100µm TSVs; (c) via bottom zoomed 50µm x 100µm TSVs.

#### **2.2.4 Properties of the new TSV-grade Cu fill chemistry**

This new TSV-grade chemistry is dedicated to the copper filling of TSV structures. It is less aggressive than conventional acidic chemistries, involving no degradation of the underlying layer, and less sensitive to the ohmic drop, which allows to fill directly on top of the NiB barrier. Its formulation is simpler, which involves a better process control, and a lower contamination of the copper deposited.

Contamination in the copper bulk has been compared by TOF-SIMS depth profiles, between this new TSV-grade chemistry (New fill) and a conventional acidic plating chemistry for TSV applications (Baseline). TOF-SIMS depth profiles are presented in fig. 21, x axis being representative of sample depth and y axis being proportional to compound quantity. Fig. 21 shows an order-of-magnitude reduction in carbon contamination and a two orders-ofmagnitude reduction in chlorine contamination for the new TSV-grade copper fill compared to conventional plating chemistries. Those trends remain similar before and after copper anneal to 250°C under forming gas.

Copper grain size has been compared between new TSV-grade and conventional plating chemistries for copper 1µm thick (fig. 22), using EBSD analysis technique. Grain size is higher in the case of new TSV-grade chemistry, and more uniform compared to conventional acidic plating. Stress observed by EBSD in grain boundary mode (fig. 22e & 22f) is lower with the new TSV-grade Cu fill (stress being proportional to red lines density).

Cristalline orientation is also extracted from EBSD analysis. As observed in fig. 23, copper deposited with the new fill chemistry is more (111) oriented than baseline chemistry.

Fig. 21. TOF-SIMS depth profiles of conventional acidic plating (Baseline) vs. new TSVgrade Cu fill (New fill) chemistry: (a) Carbon as deposited; (b) Carbon after anneal 250°C; (c) Sulfur as deposited; (d) Sulfur after anneal 250°C; (e) Chlorine as deposited; (f) Chlorine after anneal 250°C.

C Aquivia Fill C Enthone ^63Cu

**Baseline**

New fill

Cu bulk

S Aquivia Fill S Enthone ^63Cu

**Baseline** New fill

Cu bulk

Cl Aquivia Fill Cl Enthone ^63Cu

New fill

Cu bulk **Baseline**

Fig. 21. TOF-SIMS depth profiles of conventional acidic plating (Baseline) vs. new TSVgrade Cu fill (New fill) chemistry: (a) Carbon as deposited; (b) Carbon after anneal 250°C; (c) Sulfur as deposited; (d) Sulfur after anneal 250°C; (e) Chlorine as deposited; (f) Chlorine

1

10

100

1000

**Intensity (counts)**

10000

e f

100000

1

1

10

100

**Intensity (counts)** 1000

10000

c d

100000

0 50 100 150 200 250 300 **Depth (nm)**

0 50 100 150 200 250 300 **Depth (nm)**

0 50 100 150 200 250 300 **Depth (nm)**

C Aquivia Fill C Enthone ^63Cu

**Baseline**

New fill

Cu bulk

S Aquivia Fill S Enthone ^63Cu

Cu bulk

**Baseline** New fill

Cl Aquivia Fill Cl Enthone ^63Cu

New fill

Cu bulk **Baseline**

10

100

1000

**Intensity (counts)**

10000

a b

100000

1

after anneal 250°C.

10

100

1000

**Intensity (counts)**

10000

100000

1

10

100

**Intensity (counts)** 1000

10000

100000

1

0 50 100 150 200 250 300 **Depth (nm)**

0 50 100 150 200 250 300 **Depth (nm)**

0 50 100 150 200 250 300 **Depth (nm)**

10

100

1000

**Intensity (counts)**

10000

Fig. 22. EBSD top views of (a) conventional plating and (b) new TSV-grade Cu fill in Band Contrast mode; (c) conventional plating and (d) new TSV-grade Cu fill in Euler Angle mode; (e) conventional plating and (f) new TSV-grade Cu fill in Grain Boundary mode.

Fig. 23. EBSD top views of (a) baseline plating and (b) new TSV-grade Cu fill in grain orientation mode.

#### **2.3 Wet process TSV - Reliability**

#### **2.3.1 Thermo-mechanical considerations of the stack**

As reported in table 1, Young modulus (elasticity module) of the wet insulator is measured below 5GPa, which is much lower than the value obtained with SiO2 (107 GPa, see table 1). This low value of Young modulus represents an obvious advantage in the use of electrografted layers, related to the mechanical properties of the metallized via. Indeed, thermally-induced stress in bulk silicon is proportional to the square of TSV radius and elasticity module (Lu et al., 2010). Silicon stress is reduced by 30x (97%) when used with the wet insulator. This comes on top of the via size reduction induced by smaller radius, as enabled by electrografting (see 2.4 section).

#### **2.3.2 Reliability tests**

Specific test vehicles, with typical TSV design rules, were used to assess the reliability of an integrated stack of electrografting and chemical grafting layers filled with the new TSVgrade Cu fill chemistry. Those tests included temperature cycling (1000 cycles from -55°C to 125°C), moisture sensitivity levels, high-temperature storage, thermal shock, and solder heat resistance (Truzzi, 2010). All samples passed the reliability tests. Fig. 24 shows a SEM crosssection and top view of filled structures after 1000 thermal cycles. Table 3 presents an overview of thermal cycles performed with various stacks.

Additionally, electrografting layers have been integrated into test vehicles and exposed to autoclave (AC) and high-temperature storage (HTS) reliability testing. The autoclave test was conducted for 96 hours at 121°C, 100% relative humidity and 2 bar absolute pressure. Hightemperature storage was performed for 20 hours at 205°C. Both tests showed positive results with no significant difference in film performance before and after the tests (Reed et al., 2010).

#### **2.4 Design considerations**

For a given TSV depth, this nanotechnology approach allows to manufacture smaller vias, thereby unlocking the possibility to design small, fine-pitch TSVs for demanding via-middle applications such as memory-on-logic for mobile computing. From the signal integrity

Fig. 23. EBSD top views of (a) baseline plating and (b) new TSV-grade Cu fill in grain

As reported in table 1, Young modulus (elasticity module) of the wet insulator is measured below 5GPa, which is much lower than the value obtained with SiO2 (107 GPa, see table 1). This low value of Young modulus represents an obvious advantage in the use of electrografted layers, related to the mechanical properties of the metallized via. Indeed, thermally-induced stress in bulk silicon is proportional to the square of TSV radius and elasticity module (Lu et al., 2010). Silicon stress is reduced by 30x (97%) when used with the wet insulator. This comes on top of the via size reduction induced by smaller radius, as

Specific test vehicles, with typical TSV design rules, were used to assess the reliability of an integrated stack of electrografting and chemical grafting layers filled with the new TSVgrade Cu fill chemistry. Those tests included temperature cycling (1000 cycles from -55°C to 125°C), moisture sensitivity levels, high-temperature storage, thermal shock, and solder heat resistance (Truzzi, 2010). All samples passed the reliability tests. Fig. 24 shows a SEM crosssection and top view of filled structures after 1000 thermal cycles. Table 3 presents an

Additionally, electrografting layers have been integrated into test vehicles and exposed to autoclave (AC) and high-temperature storage (HTS) reliability testing. The autoclave test was conducted for 96 hours at 121°C, 100% relative humidity and 2 bar absolute pressure. Hightemperature storage was performed for 20 hours at 205°C. Both tests showed positive results with no significant difference in film performance before and after the tests (Reed et al., 2010).

For a given TSV depth, this nanotechnology approach allows to manufacture smaller vias, thereby unlocking the possibility to design small, fine-pitch TSVs for demanding via-middle applications such as memory-on-logic for mobile computing. From the signal integrity

orientation mode.

**2.3.2 Reliability tests**

**2.4 Design considerations**

**2.3 Wet process TSV - Reliability**

a b

enabled by electrografting (see 2.4 section).

**2.3.1 Thermo-mechanical considerations of the stack**

overview of thermal cycles performed with various stacks.

Fig. 24. 5µm x 25µm TSVs coated with wet insulator and NiB barrier, filled with the new TSV-grade Cu fill, and exposed to 1000 thermal cycles from -55°C to 125°C: (a) SEM crosssection and (b) SEM top view after copper polishing.

Table 3. Overview of thermal cycles performed with various stacks.

standpoint, as shown in (Truzzi & Lerner, 2009), HAR TSVs with a diameter ranging from 1 to 5µm and a depth ranging from 25 to 100 µm show smaller self-capacitance and less crosstalk than larger TSVs with similar depth (Weerasekera, 2008). Fig. 25 shows how one single large TSV exhibits a worse transmission behavior than nine small properly positioned TSVs, with ground vias correctly shielding signal lines. As for the impact of TSVs on Si real estate, the area needed for vias decreases exponentially with decreasing diameter (fig. 26). In order to illustrate this point, we can consider the assumptions listed in table 4.

Fig. 26 shows an exponential dependency of Si cost on via diameter for constant depth value: savings grow exponentially with increasing aspect ratio. In other words, a technology enabling a 3X improvement in aspect ratio allows a 8X increase in the number of TSVs per given area.

Fig. 25. Eye diagram comparison between one large single TSV and nine small, correctly designed vias.

Table 4. Si area penalty model.

Fig. 26. Si area penalty for TSVs as a function of aspect-ratio, keeping a constant depth value of 50µm.

#### **2.5 Bath analysis and manufacturing**

94 Electroplating

Fig. 25. Eye diagram comparison between one large single TSV and nine small, correctly

**Die** 10 x 10 Mm **die area** 100 mm2

**TSV depth** 50 µm **Keep out area** 2.5X diameter

**TSV density** 100 TSV/mm2

4:1 5:1 7:1 10:1 20:1

Fig. 26. Si area penalty for TSVs as a function of aspect-ratio, keeping a constant depth value

**# TSVs** 10000

designed vias.

Table 4. Si area penalty model.

0.0% 1.0% 2.0% 3.0% 4.0% 5.0% 6.0% 7.0% 8.0% 9.0%

of 50µm.

The electrografting nanotechnology described in this paper is ready to be used in a production environment. The electrochemical baths are highly stable, shelf life of all the chemistries being more than 3 months.

After preparation of the chemical baths, monitoring and replenishment of the solutions can be easily carried out using conventional analytical methods, such as pH measurement or UVvisible spectrophotometry. Table 5 summarizes analytical methods available for each bath.

Fig. 27 presents the characterization of the eG copper seed solution during a marathon performed with 900 8inch wafers, using a replenishment of 1ml/h. Process performance (adhesion, copper resistivity, step coverage in TSVs, uniformity within wafer …) remained stable during the entire marathon.

Fig. 27. eG Cu seed bath evolution during a marathon performed with 900 8inch wafers.

Table 5. Analytical methods required for each wet process TSV bath.

### **3. Conclusion**

Electrografting nanotechnology has been optimized for highly conformal growth of TSV films. Complete metallization of high aspect ratio vias is available with this technique, from insulation (by electrografted wet insulator) to copper gap filling using a new TSV-grade Cu fill chemistry.

This technology is fully compatible with standard semiconductor plating tools, enabling a large reduction in cost-of-ownership per wafer compared to dry process approaches (Lerner, 2008), while also providing stable and well-monitored chemical baths.

Film properties meet or exceed current TSV requirements, and chemical formulations are production-ready. TSVs manufactured using electrografting can be very narrow and have aspect ratios up to 20:1, thus broadening the 3D-IC design space and offering a process solution that can be extended for at least several generations into the future.

#### **4. Acknowledgment**

The author would like to thank Alchimer S.A. technical team.

eG and cG are trademarks of Alchimer S.A.

#### **5. References**

This technology is fully compatible with standard semiconductor plating tools, enabling a large reduction in cost-of-ownership per wafer compared to dry process approaches

Film properties meet or exceed current TSV requirements, and chemical formulations are production-ready. TSVs manufactured using electrografting can be very narrow and have aspect ratios up to 20:1, thus broadening the 3D-IC design space and offering a process

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## **Biomass Adsorbent for Removal of Toxic Metal Ions From Electroplating Industry Wastewater**

Ronaldo Ferreira do. Nascimento1, Francisco Wagner de Sousa1, Vicente Oliveira Sousa Neto2, Pierre Basílio Almeida Fechine1, Raimundo Nonato Pereira Teixeira3, Paulo de Tarso C. Freire1 and Marcos Antônio Araujo-Silva1 *1Universidade Federal do Ceara (UFC), 2Universidade Estadual do Ceara (UECE-CECITEC), 3Universidade Regional do Cariri (URCA), 4Instituto Federal de Educação, Ciência e Tecnologia (IFCE-Crateús) Brazil*

#### **1. Introduction**

The contamination of water bodies by heavy metals has been the subject of many studies worldwide. Several alternatives have been proposed in order to minimize the harmful effects that the disposal of these metals can cause to the environment.

A major challenge for the electroplating industry is finding solutions that equate to positive environmental and economic aspects regarding the treatment of their effluent. The adsorption process has been widely studied in order to solve the problem of many industries regarding the disposal of their effluent. Systems such as ion exchange resins, electrochemical process, chemical precipitation and activated carbon have been widely used in the processes of waste water purification. Such processes could have reduced its costs from the use of alternative materials for low cost. This has led many industries worldwide to invest in research aimed at obtaining cheap and plentiful materials that may have the same or greater capacity to remove pollutants from water bodies.

The biosorption has been presented as a promising alternative to solve the problem of contamination by heavy metals with low environmental and economic impacts.

In this chapter we introduce biosorption e process of heavy metals and discuss the implications of the technologies used in the electroplating industry to remove its contaminants.

#### **1.1 Biosorbents**

Materials of natural origin are generally used in biosorption studies (such as seaweed, biological depuration plant sludge, agricultural and industrial wastes) are inexhaustible, low-cost and non-hazardous materials, which are specifically selective for different contaminants and easily disposed by incineration.

The biosorbent terms refers to material derived from microbial biomass, seaweed or plants that exhibit adsorptive properties. Biosorption is the accumulation of metals by biological materials without active uptake. This process may include ion exchange, coordination, complexation, chelation, adsorption and microprecipitation (Duncan et al., 1994) This biomass must be subjected to pre-treatment to obtain a better operating performance in pollutant removal using adsorption method (Naja et al., 2010).

An interesting feature is that the biosorbents are widely found in nature and they have low cost. In some cases they are agriculture waste such as corn cob (Shen & Duvnjak, 2005), coconut shell (Sousa, 2007), orange pulp (Almeida, 2005), peat (Gupta et al 2009) and sawdust (Yasemin & Zaki, 2007)

#### **1.2 Ions metal biosorption**

The process is based on the interaction of ions at the interface biomass / aqueous medium. The sorbent can be either a particulate material as a compact material. The separation can be performed in packed columns, fluidized beds or in the form of discs to be used in the filtration process. This configuration allows for regeneration and reuse of the adsorbent and its proper disposal (Vargas et al, 1995). The discovery and development of the biosorption process has supported the basis for an new technology in this field. Several authors have been devoted to the study and applicability of this new kind of technology (White, 1995; Volesky, 1990).

Agricultural waste is one of the rich sources of low-cost adsorbents besides industrial byproduct and natural material. Due to its abundant availability agricultural waste such as peanut husk, rice husk, coconut shell, wheat bran and sawdust offer little economic value and, moreover, create serious disposal problems (Igwe & Abia,2007).

Biosorption is the capability of active sites on the surface of biomaterials to bind and concentrate heavy metals from even the most dilute aqueous solutions. Biosorption can be used for the treatment of wastewater with low heavy metal concentration as an inexpensive, simple and effective alternative to conventional methods. The process of metal ion binding is comprised of many physico-chemical processes like ion exchange, complexation, microprecipitation, and electrostatic interactions. Biosorbents for the removal of metals mainly come under the following categories: bacteria, fungi, algae, industrial wastes, agricultural wastes and other polysaccharide materials. In general, all types of biomaterials have shown good biosorption capacities towards all types of metal ions (Febrianto et al., 2009)

The biosorption results from electrostatic interactions and/or of the formation of complexes between metal ions and functional groups present on the surface of biosorbent. So many studies have been conducted to assess the potential for removing heavy metals from various biological materials (Hayashi , 2001). We can cite the seaweeds and their derivatives (Luo et al, 2006), chitosan (Ngah et al, 2011), lignin (Guo et al, 2008), wide variety of bacteria and fungi (Watanabe et al, 2003), agricultural residues (Sousa, 2007), among others. According to Volesky, (1990) biosorbent must have certain physical characteristics (surface area, porosity, grain size etc.) to get good ability to adsorption and to be used in an adsorption process.

#### **1.3 Adsorbent used for removing pollutants**

Adsorption process is essentially a surface phenomenon. Adsorbent having a good adsorptive capacity implies that it should present a large specific surface area. The adsorptive properties depend on the distribution of size pore and the nature of the solid surface. The adsorbents most commonly used on an industrial scale are the activated carbon, silica gel, activated alumina and molecular sieves (Lopez & Gutarra, 2000) (Yasemin & Zaki, 2007). There is no doubt that the charcoal has become the most widely used solid, worldwide, as an adsorbent to remove pollutants in wastewater. According to its own characteristics, such as high porosity, chemical structure and high surface area, the activated carbon has an excellent ability to remove substances on its surface (Babel & Kurniawan, 2003). Added to this, the chemical structure of this material allows surface modifications by chemical or physical treatments, allowing an increase in adsorption capacity of this material.

On the other hand, it is also widespread agreement that even with all these features, the charcoal has some serious drawbacks to adsorptive processes. Some of them should be, for example, the fact that this material is not selective, and its market value is relatively high. Also, the reactivation of this material is not an easy process; cleaning the surface for subsequent applications is a one very expensive process. Moreover, the methods of recovery of coal, both the heat treatment as the use of chemicals, cannot regenerate the material with the same initial characteristics, leading to losses in their adsorption capacity. For these reasons, special attention has been focused on several other adsorbent materials. In particular, some natural materials, such as polysaccharides, clays, biomass, etc., that can remove pollutants from contaminated water at low cost of procurement has been widely researched around the world (Kumar, 2000; Crini, 2005, Crini, 2006). In fact, the cost of obtaining and regenerative capacity of such solid materials are important parameters when compared adsorbents materials.

#### **1.4 Modification of adsorbent**

102 Electroplating

materials without active uptake. This process may include ion exchange, coordination, complexation, chelation, adsorption and microprecipitation (Duncan et al., 1994) This biomass must be subjected to pre-treatment to obtain a better operating performance in

An interesting feature is that the biosorbents are widely found in nature and they have low cost. In some cases they are agriculture waste such as corn cob (Shen & Duvnjak, 2005), coconut shell (Sousa, 2007), orange pulp (Almeida, 2005), peat (Gupta et al 2009) and

The process is based on the interaction of ions at the interface biomass / aqueous medium. The sorbent can be either a particulate material as a compact material. The separation can be performed in packed columns, fluidized beds or in the form of discs to be used in the filtration process. This configuration allows for regeneration and reuse of the adsorbent and its proper disposal (Vargas et al, 1995). The discovery and development of the biosorption process has supported the basis for an new technology in this field. Several authors have been devoted to

the study and applicability of this new kind of technology (White, 1995; Volesky, 1990).

and, moreover, create serious disposal problems (Igwe & Abia,2007).

good biosorption capacities towards all types of metal ions (Febrianto et al., 2009)

**1.3 Adsorbent used for removing pollutants**

Agricultural waste is one of the rich sources of low-cost adsorbents besides industrial byproduct and natural material. Due to its abundant availability agricultural waste such as peanut husk, rice husk, coconut shell, wheat bran and sawdust offer little economic value

Biosorption is the capability of active sites on the surface of biomaterials to bind and concentrate heavy metals from even the most dilute aqueous solutions. Biosorption can be used for the treatment of wastewater with low heavy metal concentration as an inexpensive, simple and effective alternative to conventional methods. The process of metal ion binding is comprised of many physico-chemical processes like ion exchange, complexation, microprecipitation, and electrostatic interactions. Biosorbents for the removal of metals mainly come under the following categories: bacteria, fungi, algae, industrial wastes, agricultural wastes and other polysaccharide materials. In general, all types of biomaterials have shown

The biosorption results from electrostatic interactions and/or of the formation of complexes between metal ions and functional groups present on the surface of biosorbent. So many studies have been conducted to assess the potential for removing heavy metals from various biological materials (Hayashi , 2001). We can cite the seaweeds and their derivatives (Luo et al, 2006), chitosan (Ngah et al, 2011), lignin (Guo et al, 2008), wide variety of bacteria and fungi (Watanabe et al, 2003), agricultural residues (Sousa, 2007), among others. According to Volesky, (1990) biosorbent must have certain physical characteristics (surface area, porosity, grain size etc.) to get good ability to adsorption and to be used in an adsorption process.

Adsorption process is essentially a surface phenomenon. Adsorbent having a good adsorptive capacity implies that it should present a large specific surface area. The adsorptive properties depend on the distribution of size pore and the nature of the solid surface. The adsorbents

pollutant removal using adsorption method (Naja et al., 2010).

sawdust (Yasemin & Zaki, 2007)

**1.2 Ions metal biosorption**

In general, raw lignocellulosic biosorbents were modified by various methods to increase their adsorption capacities because metal ion binding by lignocellulosic biosorbents is believed to take place through chemical functional groups such as carboxyl, amino, or phenolics. More recently, great effort has been contributed to develop new adsorbents and improve existing adsorbents. Many investigators have studied the feasibility of using lowcost agro-based waste materials (Hashem, 2006; Hashem et al.,2006; Hashem et al. ,2006; Hashem et al., 2006; Hashem et al., 2006, Abdel-Halim et al., 2006; Hashem et al., 2006)

Agricultural by-products usually are composed of lignin and cellulose as major constituents and may also include other polar functional groups of lignin, which includes alcohols, aldehydes, ketones, carboxylic, phenolic and ether groups. These groups have the ability to some extent to bind heavy metals by donation of an electron pair from these groups to form complexes with the metal ions in solution (Pagnanelli, 2003).

In recent decades there has been a greater interest and concern about environmental issues. This has motivated the development of materials for low cost, wide availability and good adsorption capacity. At this particular point modification of adsorbent has been used in some cases with great success, with the purpose of increasing the adsorption capacity of these materials. Cellulose, hemicellulose and lignin are compounds that have structures with a large amount of hydroxyl groups. The availability of these groups are associated with good capacity to adsorb heavy metals such as Cu (II), Zn (II), Cd (II), Pb (II) among others. An interesting aspect is that these materials can be easily modified by introducing new functional groups.The modification reactions often employ a bioadsorbente polymerization reactions (Anirudhan & Noeline, 2005), functionalization with carboxylic groups, amines, amides (Shiba & Anirudhan, 2005) among others.

#### **1.5 Electroplating wastewater**

The industry of metal finishing and electroplating units are one of the major sources of pollutants which contribute greatly to the pollution load of the receiving water bodies and therefore increase the environmental risks

The industry of metal finishing and electroplating are one of the majorsource of heavy metals (Zn, Cu, Cr, …) and cyanide (Monser & Adhoum, 2002, 2002, Low & Lee,1991.). in the world. With the development of electroplating, the quantity of the electroplating wastewater have increased so fast in the last years. The heavy metals must be removed from wastewaters before discharge, as they are considered persistent, bioaccumulative and toxic (Sankararamakrishnan et al., 2007; Gupta, 2008), causing a serious threat to public health.