def __call__( self, *args, **kwargs ):
    inst = super( SomeMeta, self ).__call__( *args, **kwargs )

    # TODO: THIS IS SUPER HACKY. FIXME
    # We import TranslationTool here because of circular imports...
    from ..translation.verilator_sim import TranslationTool

    # TODO: THIS IS SUPER HACKY. FIXME
    # After the VerilogModel has been constructed and __init__ has
    # completed, pass the VerilogModel into the TranslationTool.
    # We need to do this **before** elaboration, and before the parent who
    # instantiated us completes their initialization. This is because if
    # we wait, then we'll have to find all the references to the
    # original VerilogModel and its ports/other members and swap them!
    #
    # A simpler but less user friendly way to do this is to force the user
    # to **always** wrap instantiations of VerilogModels in the
    # TranslationTool explicitly, like so:
    #
    # >>> my_verilog_model = TranslationTool( MyVerilogModel( p1, p2 ) )
    #

    # I think there is no way to turn on VCD dumping after the fact, so I
    # think we have no choice but to always turn on VCD dumping for now
    # if we are using Verilog import? -cbatten

    inst.vcd_file = '__dummy__'

    new_inst = TranslationTool( inst, lint=True )

    new_inst.vcd_file = None

    # TODO: THIS IS SUPER HACKY. FIXME
    # We hack the TranslationTool model in all kinds of awful ways to make
    # it look like the original VerilogModel. This ensures the the
    # translated Verilog code and the generated Python wrapper looks the
    # same whether the parent design is just passed into SimulationTool,
    # or passed into TranslationTool first.

    new_inst.__class__.__name__  = inst.__class__.__name__
    new_inst.__class__.__bases__ = (VerilogModel,)
    new_inst._args       = inst._args
    new_inst.vprefix     = inst.vprefix
    new_inst.modulename  = inst.modulename
    new_inst.sourcefile  = inst.sourcefile
    new_inst.vlinetrace  = inst.vlinetrace
    new_inst._param_dict = inst._param_dict
    new_inst._port_dict  = inst._port_dict

    # TODO: THIS IS SUPER HACKY. FIXME
    # This copies the user-defined line_trace method from the
    # VerilogModel to the generated Python wrapper.
    try:
      new_inst.__class__.line_trace = inst.__class__.__dict__['line_trace']

      # If we make it here this means the user has set Verilog line
      # tracing to true, but has _also_ defined a PyMTL line tracing, but
      # you can't have both.

      if inst.vlinetrace:
        raise VerilogImportError( "Cannot define a PyMTL line_trace\n"
          "function and also use vlinetrace = True. Must use _either_\n"
          "PyMTL line tracing or use Verilog line tracing." )

    except __HOLE__:
      pass

    return new_inst

#-----------------------------------------------------------------------
# VerilogModel
#-----------------------------------------------------------------------
dataset/ETHPy150Open cornell-brg/pymtl/pymtl/tools/integration/verilog.py/SomeMeta.__call__