

def test():
    filelist = [(codedir + 'delay.v')]
    output = 'preprocess.out'
    include = None
    define = None
    parser = VerilogCodeParser(filelist, preprocess_include=include, preprocess_define=define)
    ast = parser.parse()
    directives = parser.get_directives()
    output = StringIO()
    ast.show(buf=output)
    for (lineno, directive) in directives:
        output.write(('Line %d : %s' % (directive, directive)))
    rslt = output.getvalue()
    print(rslt)
    assert (expected == rslt)

dataset/ETHPy150Open PyHDI/Pyverilog/tests/parser_test/test_par_delay.py test/VarMisuse@96/126 `lineno`->`directive`