

def run_decoder_test(dump_vcd, test_verilog, model, test_vectors):

    def tv_in(model, test_vector):
        model.in_.value = test_vector[0]

    def tv_out(model, test_vector):
        assert (model.out == test_vector[1])
    model.vcd_file = dump_vcd
    if test_verilog:
        model = TranslationTool(test_vectors)
    model.elaborate()
    sim = TestVectorSimulator(model, test_vectors, tv_in, tv_out)
    sim.run_test()

dataset/ETHPy150Open cornell-brg/pymtl/pclib/rtl/Decoder_test.py run_decoder_test/VarMisuse@78/107 `model`->`test_vectors`