

def mkTop():
    m = Module('top')
    width = m.Parameter('WIDTH', 8)
    clk = m.Input('CLK')
    rst = m.Input('RST')
    led = m.Output('LED', width)
    led = mkLed()
    params = m.copy_params(led)
    ports = m.copy_ports(led)
    m.Instance(led, 'inst_blinkled', params, ports)
    return m

dataset/ETHPy150Open PyHDI/veriloggen/tests/verilog/read_verilog_/module_modify/read_verilog_module_modify.py mkTop/original