

def _are_in_sequence(self, a, b):
    details_a = self._get_interface_details(a.name)
    details_b = self._get_interface_details(b.name)
    return (((details_b.port + 1) == details_b.port) and (details_a.port_prefix == details_b.port_prefix))

dataset/ETHPy150Open internap/fake-switches/fake_switches/dell/command_processor/enabled.py DellEnabledCommandProcessor._are_in_sequence/VarMisuse@40/58 `details_a`->`details_b`