

def test():
    test_module = _class.Led()
    code = test_module.to_verilog()
    from pyverilog.vparser.parser import VerilogParser
    from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    parser = VerilogParser()
    expected_ast = parser.parse(expected_verilog)
    codegen = ASTCodeGenerator()
    expected_code = codegen.visit(expected_ast)
    assert (expected_code == code)

dataset/ETHPy150Open PyHDI/veriloggen/tests/core/_class/test__class.py test/original