def test():
    try:
        test_module = multiple_definition_variable_instance.mkLed()
    except __HOLE__ as e:
        assert(e.args[0] == "Object 'tmp' is already defined.")
        return 

    assert(False)
        
    #code = test_module.to_verilog()

    #from pyverilog.vparser.parser import VerilogParser
    #from pyverilog.ast_code_generator.codegen import ASTCodeGenerator
    #parser = VerilogParser()
    #expected_ast = parser.parse(expected_verilog)
    #codegen = ASTCodeGenerator()
    #expected_code = codegen.visit(expected_ast)

    #assert(expected_code == code)
dataset/ETHPy150Open PyHDI/veriloggen/tests/core/multiple_definition_/variable_instance/test_multiple_definition_variable_instance.py/test