a data processing unit having superscalar structure able to execute a plurality of instructions in parallel includes a memory for storing the instructions having a plurality of n - bit input / output ports , an instruction fetch unit , a coupling unit for coupling said memory with the instruction fetch unit , and an instruction stream request control unit for addressing the mmory to provide an instruction stream at its output ports . the coupling unit includes a shifter having an input and an output and a control input , the input being coupled with the output ports of the memory , the output being coupled with the instruction fetch unit , and the control input being coupled with the instruction stream request control unit . the instruction fetch unit has a register for storing said instruction stream and a shifter to shift the content of the register .