a branch prediction control circuit has a register . a main memory provides a machine language instruction to the register and an instruction buffer . the prediction control circuit decodes the instruction held in the register and predicts whether or not the branch is taken . if the instruction is a relative branch instruction , a sum of the address of the instruction and a displacement included in the instruction is computed to provide a branch address . at the same time , a branch address valid signal is provided . with this arrangement , reliable branch prediction of the relative branch instruction is realized with a small amount of hardware .