a tool for designing integrated circuits that optimizes the placement and timing of memory blocks within the circuit . given a manufactured slice that has a number of blocks already diffused and logically integrated , the memory generation tool herein automatically considers the available diffused memory and the gate array of the slices to configure and optimize them into a customer &# 39 ; s requirements for memory . the memory generation tool has a memory manager , a memory resource database , a memory resource selector , and a memory composer . together these all interact to generate memories from the available memories within the memory resource database . the memory composer actually generates the rtl logic shells for the memories , and outputs the memory designs in verilog , vhdl , or other tool synthesis language . once a memory is created , it is tested . upon successful testing , the memory manager updates the memory resource database to indicate the successfully tested memory is no longer available as a resource for the generation of further memories . a design integrator may review the memory designs output and further integrate the memory , its timing , testing , etc . with other blocks and functions of the integrated circuit .