performance of an integrated circuit design , whether embodied as a design encoding or as a fabricated integrated circuit , can be improved by selectively substituting low v t transistors in a way that prioritizes substitution opportunities based on multi - path timing analysis and evaluates such opportunities based on one or more substitution constraints . by valuing , in a prioritization of substitution opportunities , contributions for all or substantially all timing paths through the substitution opportunity that violate a max - time constraint , repeated passes through a timing analysis phase can be advantageously avoided or limited . in addition , by recognizing one or more constraints on actual low v t substitutions , particular noise - oriented . constraints , the scope of post substitution design analysis can be greatly reduced . in some realizations , substitutions are performed so long as a leakage current budget is not expended . as a result , integrated circuit designs prepared in accordance with the described techniques may exhibit substantial cycle time improvements through judicious selection of gate instances for substitution . in some realizations , improved yields of high grade parts may result .