a multiprocessing system includes , in part , a multitude of processing units each in direct communication with a bus , a multitude of memory units in direct communication with the bus , and at least one shared memory not in direct communication with the bus but directly accessible to the plurality of processing units . the shared memory may be a cache memory that stores instructions and / or data . the shared memory includes a multitude of banks , a first subset of which may store data and a second subset of which may store instructions . a conflict detection block resolves access conflicts to each of the of the banks in accordance with a number of address bits and a predefined arbitration scheme . the conflict detection block provides each of the processing units with sequential access to the banks during consecutive cycles of a clock signal .