a test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time , a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry . the output signals of two delay units are applied to a flip - flop as set input signals , while the output signals of the other two delay units are applied to the flip - flop as reset input signals , whereby the timing and / or waveform of the test signal outputted by the flip - flop is varied in dependence on the values placed in the setting circuitries .