an electronic data storage or memory array having dc stable memory cells which utilize the principle of a unique substrate biasing mechanism , whereby a channel region defined by resistive substrate material and formed under a controlled electrode becomes &# 34 ; pinched off &# 34 ; and , in the process , so affects the dc potential at that electrode as to maintain the pinched off condition . consequently , the memory cell becomes established in a first dc stable state . the principle is preferably embodied in a field effect transistor , the resistive channel region being connected in a dc conductive path to a fixed resistor and a potential source . accordingly , when appropriate signal levels representing a binary &# 34 ; one &# 34 ; are applied to word and bit lines connected to a first controlling , or gate , electrode and to a second controlling electrode , respectively , of the fet , the described pinch - off occurs , with concomitantly high resistance in the dc path , such that the potential adjacent the controlled electrode is maintained in the &# 34 ; one &# 34 ; state that was initiated by the signals on the word and bit lines . on the other hand , when signals representing a &# 34 ; zero &# 34 ; are applied to the same controlling electrodes , the resistive channel region under the controlled electrode is no longer pinched - off , whereby the memory cell becomes established in the second or &# 34 ; zero &# 34 ; dc stable state . means for reading the stored data in the cell are integrated with the cell .