to facilitate efficient communications in a multi bus master system that communicates with a plurality of peripheral devices , a two channel bus is used that shares write and read addresses with data on a transmit channel to reduce wiring density and provide efficient , reliable , and high speed data transfers . the two channel bus includes the transmit channel , a receive channel , and a single control channel that provides control information for both the transmit channel and the receive channel further reducing the signaling requirements of the two channel bus . the control information includes a control flag that specifies control information for data transfers on the two channel bus . the control flag and control information may be supplied in two bus cycles or in a single bus cycle depending on the control requirements for two data transfers occurring in parallel on the two channel bus .