an integrated circuit device includes a clock delay circuit configured to receive a clock signal and a pulse signal and to produce an output signal therefrom . the clock delay circuit is configured to transition the output signal to a first state responsive to a first state of the clock signal and to transition the output signal to a second state responsive to a first state transition of the pulse signal . the integrated circuit device further includes a pulse generator circuit configured to receive the clock signal and the output signal and to produce the pulse signal therefrom . the pulse generator circuit is configured to generate the first state transition in the pulse signal responsive to a transition of the clock signal to a second state and to generate a second state transition in the pulse signal responsive to the transition of the output signal to the second state .