an i 2 c - bus compatible device when functioning as a clock master comprises a transient active pull - up i 2 c logic module having high side driver transistors , e . g ., p - channel field effect transistors , coupled between a positive supply voltage and respective serial data and serial clock lines on the i 2 c bus . the high side output driver transistors for the sda and scl lines are sequentially pulsed on by the tap i 2 c logic module for brief periods to first precharge the capacitance of the sda line and then precharge the capacitance of the scl line during low to high logic level transitions thereof . precharging the capacitances of the i 2 c bus lines will also accelerate bus transfer operations for all i 2 c compatible devices since the capacitances of the i 2 c bus lines will be charged much faster through the low impedance active pull - up driver transistors then through the passive pull - up resistors .