a control chip having a multiple - layer defer queue therein and a method of operating the control chip . the control chip is coupled to a cpu bus and a pci bus . the control chip comprises of a pc request queue , a multiple - layer defer queue , a pci access queue and a pci controller . the multiple - layer defer queue facilitates the processing of a multiple of concurrent cpu requests that belong to a first request type . the multiple - layer defer queue supports retry and defer transactions , thereby reducing data transmission between the cpu and the control chip .