the present invention relates to a process of fabricating semiconductor memory structures , particularly deep trench semiconductor memory devices wherein a temperature sensitive high dielectric constant material is incorporated into the storage node of the capacitor . specifically , the present invention describes a process for forming deep trench storage capacitors after high temperature shallow trench isolation and gate conductor processing . this process allows for the incorporation of a temperature sensitive high dielectric constant material into the capacitor structure without causing decomposition of that material . furthermore , the process of the present invention limits the extent of the buried - strap outdiffusion , thus improving the electrical characteristics of the array mosfet .