a parallel processor is disclosed which combines the advantages of an array of bit - serial processors and an array of word - oriented processors . further , the invention provides for ready communication between data organized in bit - serial fashion and that organized in parallel . the processor comprises a plurality of word - oriented processors , at least one transposer associated with each processor , said transposer having n bit - serial inputs and m bit parallel outputs and a bit - serial processor associated with each bit - serial input of the transposer . the parallel processor further comprises a memory for each bit - serial processor and a data bus interconnecting the memory , the bit - serial processors and the bit - serial inputs of the transposer . the transposer converts serial inputs to parallel , word organized outputs which are provided as inputs to the word - oriented processors . in accordance with a preferred embodiment of the invention , three or more transposers are used in connection with each word - oriented processor so as to provide a pipelining capability that significantly enhances processing speeds .