a semiconductor memory device includes isolation circuits disconnecting cell arrays from sense amplifiers , and isolation signal generating circuits generating isolation signals that control the isolation circuits . the isolation signal generating circuits are hierarchically divided into main isolation signal generating circuits and sub isolation signal generating circuits . the sub isolation signal generating circuits generate sub isolation signals having a first potential on a high - potential side . the main isolation signal generating circuits generate main isolation signals having a second potential on the high - potential side , the second potential being lower than the first potential .