a semiconductor memory device operable at a power source voltage in a wide range and capable of stably detecting data includes a potential detector for detecting a potential of a dummy bit line having a parasitic capacitance corresponding to a parasitic capacitance of bit lines and a plurality of second precharge circuits provided correspondingly to the respective bit lines , for precharging the respective bit lines in response to a precharge signal and terminating the precharge operation in response to an output of the potential detector .