apparatus and method for concurrent dispatch of instruction words which selectively comprise instruction components which are separately and substantially simultaneously received by distinct floating point and integer functional units . the instruction words are powers of 2 in length , typically a 4 byte longword and an 8 byte quadword aligned to the natural boundaries also corresponding to powers of 2 . to provide maximum operating efficiency , each functional unit executes a component of an instruction word during an execution cycle . the type and length of the instruction word are indicated by one of the bit fields of the instruction word , which permits the apparatus to properly detect , store and transfer the instruction word to the appropriate functional unit . the invention combines the encoding efficiency of variable length instruction combined combined with the enhanced processing speed of simultaneous operation of all available functional units , to provide the execution efficiency of systems with a single instruction length .