using a combination of frequency dithering of a pwm counter and a variable time delay circuit yields improved pwm frequency resolution with realizable circuit components and clock operating frequencies . a controllable time delay circuit lengthens a pwm signal during the first pwm cycle . during the second pwm cycle , the pwm period is increased beyond the desired amount , but the delay is reduced during this second pwm cycle to achieve the correct pwm signal period . the dithering of the pwm signal period enables the time delay circuit to be “ reset ” so that an infinite delay circuit is not required . the time delay circuit provides short term frequency adjustment so that the resulting pwm cycle is not dithered and has a period at the desired frequency resolution .