an electrically - erasable , programmable rom cell , or an eeprom cell , is constructed using an enhancement transistor merged with a floating - gate transistor , where the floating - gate transistor has a small tunnel window , in a contact - free cell layout , enhancing the ease of manufacture and reducing cell size . the bitlines and source / drain regions are buried beneath relatively thick silicon oxide , which allows a favorable ration of control gate to floating gate capacitance . programming and erasure are provided by the tunnel window area , which is located near or above the channel side of the source . the window has a thinner dielectric than the remainder of the floating gate , to allow fowler - nordheim tunneling . by using dedicated drain or ground lines , rather than a virtual - ground layout , and by using thick oxide for isolation between bitlines , the floating gate can extend onto adjacent bitlines and isolation area , resulting in a favorable coupling ratio . isolation between cells in the wordline direction is by a self - aligned implanted region , in this embodiment .