a differential sensing circuit and sensing method for use in a low voltage memory device . the sensing circuit includes a cross - coupled sensing circuit for coupling with a memory element , a pull - up circuit and a multistage pull - down circuit . the multistage pull - down circuit accelerates the latching process of the cross - coupled sensing circuit by briefly pulling the cross - coupled sensing circuit to a potential below ground in order to increase the gate potential differential on at least a portion of the transistors within the cross - coupled sensing circuit . once the latching transitions have commenced at an acceptable rate , the below - ground potential is removed and the traditional logic level pull - up and ground - potential pull - down circuits are activated .