a method of manufacturing semiconductor circuits seeks timing closure on a preliminarily select , placed and routed set of cells using a delay for each cell as derated by a derate value obtained from a timing model table having a derate value corresponding to a circuit path depth in the netlist . the derate value for a predetermined number of circuit path depths below k are identical . the derate values are monotonically decreasing for increasing circuit depths in a range between 1 . 0 and 1 . 5 . separate timing model tables with differing identical values can be employed for standard and clock tree cells .