a memory array includes a plurality of sense amplifiers and a first switch module . the plurality of sense amplifiers is connected respectively to a plurality of global bit lines . the plurality of sense amplifiers are configured to read data stored in a first block of memory cells of the memory array . the memory cells in the first block are located at intersections of a plurality of local bit lines and a first plurality of word lines . the first switch module is connected to a first group of the plurality of local bit lines and to a first group of the plurality of global bit lines . the first switch module is configured to selectively connect a subset of the first group of the plurality of local bit lines to the first group of the plurality of global bit lines .