a packet generator that increases the output speed of column and row addresses and data provided by a semiconductor device test system . the packet generator receives column and row addresses and data from a conventional algorithmic pattern generator and generates column and row addresses and data in packet form , thereby allowing communications with a packet - based device under test , such as a memory . the packet generator further provides variable time spacing between column and row addresses and data packets . thereby , the packet generator advantageously allows testing of memory devices that require signal inputs at a higher rate than a conventional apg can provide .