high speed address decoders may include a predecoder and a main decoder that are both responsive to a control signal . the predecoder switches from an active state to an inactive state in response to a transition of the control signal from a first logic state to a second logic state . conversely , the main decoder commences switching from an inactive state to an active state simultaneously with the transition of the control signal from the first logic state to the second logic state . the predecoder may generate a predecoded address signal while the control signal is in the first logic state , which may then be decoded by the main decoder to activate a line enable signal when the control signal transitions to the second logic state . as a result , address decoding speed may be improved thereby facilitating higher speed operation of an integrated circuit memory device .