a digital circuit configuration includes a memory matrix having m rows and n columns and p & lt ; m additional rows and q & lt ; n additional columns , and an addressing device whose address connection contacts are sufficient precisely for addressing the m rows and n columns . to address the additional rows and columns as well , particularly , for test purposes , only a single control bit connection contact is provided with a changeover device responding to control bits from the control bit connection contact and from dedicated address connection contacts to associate applied address bits either with addressing of the m rows and n columns or the additional rows and columns . the numbers p and q are chosen such that the addressing of p elements requires at least two bits fewer than the addressing of m elements , and such that the addressing of q elements requires at least two bits fewer than the addressing of n elements .