a delayed locked loop circuit of dll comprises a buffer that receives a power - down signal and an inverted signal of a first clock signal ; first and second delay lines an output device that outputs signals corresponding to the output signals of the first and second delay lines respectively ; a replica delay unit , a phase comparator for comparing a phase difference between the output signal of the second buffer and the output signal of the replica delay unit ; and a delay line controller for controlling delay times of the first delay line and the second delay line by corresponding to a comparison result of the phase comparator . the dll circuit is configured such that the first and second buffers are disabled when the power - down mode entry notifying signal corresponding to a power - down mode is provided .