a method and implementing computer system are provided which enable a process for implementing a coherency system for bridge - cached data which is accessed by adapters and adapter bridge circuits which are normally outside of the system coherency domain . an extended architecture includes one or more host bridges . at least one of the host bridges is coupled to i / o adapter devices through a lower - level bus - to - bus bridge and one or more i / o busses . the host bridge maintains a buffer coherency directory and when invalidate commands are received by the host bridge , the bridge buffers containing the referenced data are identified and the indicated data are invalidated .