in the present invention is disclosed a flash memory for simultaneous read and write operations . the memory is partitioned into a plurality of sectors each of which have a sector decoder . the sector decoder connects a plurality of main bit lines to a plurality of sub bit lines contained within each memory sector a 2 1 decoder is used to demonstrate the invention although other decoders including a 2 m decoder and a hierarchical type decoder can be used . the memory array can be configured from a variety of architectures , including nor , or , nand , and , dual - string and dinor . the memory cells can be formed from a variety of array structures including etox , flotox , eprom , eeprom , split - gate , and pmos .