a double - gate field effect transistor structure and method of forming such a structure in which the parasitic capacitance under the source / drain regions is substantially reduced are provided . two new means to reduce the parasitic capacitance under the source / drain regions are provided . firstly , the silicon area outside the gate is converted to oxide while protecting a silicon ledge adjacent to the gate with a first spacer . the oxidation can be facilitated using a self - aligned oxygen implant , or implant of some other species . secondly , the first spacer is removed , replaced with a second spacer , and a new silicon source / drain area is grown by employing lateral selective epi overgrowth and using the now exposed silicon ledge as a seed , over the self - aligned oxide isolation region . this achieves a low - capacitance to the back - plane , while retaining control of the threshold voltages .