a cell array for eprom or rom type memories has drain and source interconnection metal lines connecting in common drain and source regions , respectively , of the cells arranged on a same row of the array formed directly on the semiconductor substrate , superimposed at crossings to uninterrupted isolation strips formed on the semiconductor substrate for separating cells belonging to two adjacent columns of the array , and gate interconnection lines , connecting the control gate electrodes of cells arranged on a same column , which run parallel to and between said isolation strips and superimposed at crossings to said underlying source and drain lines . the array is markedly more compact than an array made according to the prior art though utilizing fabrication apparatuses with similar optical resolution , while maximizing the source and drain contact areas of the cells . in rom devices , the customizing may advantageously take place during the final steps of the fabrication process by means of a gate contact mask having a reduced criticality in respect to a comparable drain contact mask used in prior art processes . the fabrication process employs self - alignment techniques and masks with a relatively low alignment criticality .