the present invention provides a wafer level chip size package having cavities within which micro - machined parts are free to move , allowing access to electrical contacts , and optimized for device performance . also a method for fabricating a wafer level chip size package for mems devices is disclosed . this packaging method provides a well packed device with the size much closely to the original one , making it possible to package the whole wafer at the same time and therefore , saves the cost and cycle time .