a clock synchroniser , for generating a local clock signal synchronised to a received clock signal , is described and claimed , along with a corresponding clock synchronisation method . the clock synchroniser incorporates a reference oscillator providing a reference signal , and a synthesiser circuit arranged to synthesise a local clock signal from the reference signal . the synthesiser circuit comprises a phase - locked - loop circuit , including a phase detector receiving the reference signal , and a controllable divider arranged in a feedback path from a controlled oscillator to the phase detector , the divider being controllable to set a frequency division value n along the path to determine a ratio of the local clock frequency to the reference frequency . the clock synchroniser also incorporates a clock comparison circuit adapted to generate a digital signal indicative of an asynchronism between the local and remote clock signals . a control link is arranged to link the clock comparison circuit to the divider . this link receives the digital signal and provides a control signal to the divider to adjust the frequency division value n according to the digital signal , to alter the local clock frequency and reduce the asynchronism . preferably , the clock comparison circuit compares the periods of the local and received clock signals .