an interface driver circuit comprises n cascaded delay cells , each including a data bit input , a delayed data bit output that communicates with the data bit input of an adjacent one of the n cascaded delay cells , and a delay time input that sets delay values between receiving data at the data bit input and generating the delayed data bit output . n predrivers receive an output enable signal that is independent of the data , receive a corresponding one of the n delayed data bit outputs and generate a predriver output signal based on the output enable signal and the corresponding one of the n delayed data bit outputs .