a semiconductor memory circuit is provided with a right memory cell group and a left memory cell group , word decoders corresponding to respective rows and ; which are located between the right and left memory cell groups and which specify an address in the word direction of these memory cell groups , and column decoders corresponding to respective column which specify an address in the bit direction of these memory cell groups . the memory circuit also includes right and left memory cell group selection and drive gates for every word decoder and circuits for detecting whether the accessed memory cell is in the right or left memory cell group . the right or left memory cell group selection and drive gates operate in a complimentary manner and in accordance with the accessed memory cell being in the right or left memory cell group .