a splittable / connectible bus 140 and a network 1000 for transmitting coherence transactions between cpus are provided between the cpus , and a directory 160 and a group setup register 170 for storing bus - splitting information are provided in a directory control circuit 150 that controls cache invalidation . the bus is dynamically set to a split or connected state to fit a particular execution form of a job , and the directory control circuit uses the directory in order to manage all inter - cpu coherence control sequences in response to the above setting , while at the same time , in accordance with information of the group setup register , omitting dynamically bus - connected cpu - to - cpu cache coherence control , and conducting only bus - split cpu - to - cpu cache coherence control through the network . thus , decreases in performance scalability due to an inter - cpu coherence - processing overhead are relieved in a system having multiple cpus and guaranteeing inter - cpu cache coherence by use of hardware .