an esd protection circuit design incorporating a single , or a plurality of , parallel inductor and capacitor , also known as lc tank , to avoid power loss by parasitic capacitance in esd circuits . the first design described incorporates a lc tank structure . the second includes two lc tank structures . these structures can be expanded to form esd protection circuit structures stacked with n - stages lc tanks . the last design described is esd protection circuits formed by stacking the first design . these designs can avoid power gain loss from parasitic capacitance of esd , because the parameters of lc tank can be designed to resonant at a desired operating frequency . each of these designs can be altered slightly to create variant designs with equal identical esd protection capabilities .