a processor architecture is described which operates with improved computational efficiency using instruction fetching functions that are decoupled from instruction execution functions by a dynamic register file . the instruction fetching function operates in free - running mode which does not stop if a fetched instruction cannot be executed due to data being unavailable or due to other instruction dependencies . branch instructions are taken in a predicted direction and the results of execution of all instructions are provisionally stored pending validation or invalidation on the basis of the dependencies becoming available later . for branches of executed instructions that are later invalidated , the results of the executed instructions are flushed from provisional storage and the initial instruction which previously executed at the beginning of a branch on predicted dependencies is re - executed on the actual data that subsequently became available , and all subsequent instructions in such branch are also re - executed on the basis of dependencies actually available from execution of previous instructions in such branch .