a process and apparatus for preparing said process for reducing the power consumption of microprocessor - based devices by reducing the frequency of the oscillator governing the logical operation of the microprocessor during periods of use in which system performance is not critical . in one embodiment of apparatus the microprocessor is controlled by a monitor circuit operable with the microprocessor and operated by the variable frequency oscillator . in another embodiment a hardware monitor circuit is utilized and which tracks microprocessor instructions to determine periods of use when performance is not critical . the shift in oscillator speed is mediated by a flip - flop latch circuit connected between one or more clock oscillators and the oscillator input of the controlled microprocessor .