asynchronously - generated digital and analog clocks in a mixed - signal test system are accurately aligned for repeatable and deterministic testing . a variable - frequency digital master clock signal is used in direct digital synthesis of an analog clock signal which is asynchronous to the master clock signal . a resync command inhibits the analog clock signal until the analog clock signal is in a desired phase relationship to the master clock signal . the analog clock signal is thus phase - aligned with the master clock signal in a known and deterministic relationship . the resync command also aligns the phase of the analog clock signal with the pattern of stimulus signals applied to the device under test . aligning the analog clock signal with the master clock signal and with the stimulus pattern assures that test results are consistent from test - to - test . a phase - locked loop removes spurs from the synthesized analog clock signal . a jitter generator is provided for controlled jittering of the analog clock signal as needed for some types of test . an nth occurrence counter allows for programmable introduction of an extra master - clock - signal period in the test pattern when needed to avoid creating a metastable condition in the device under test .