an apparatus for counting microcode instruction execution in a microprocessor includes a first register , a second register , a comparator , and a counter . the first register stores an address of a microcode instruction . the microcode instruction is stored in a microcode memory of the microprocessor . the second register stores an address of the next microcode instruction to be retired by a retire unit of the microprocessor . the comparator compares the addresses stored in the first and second registers to indicate a match between them . the counter counts the number of times the comparator indicates a match between the addresses stored in the first register and the second register . the first register is user - programmable and the counter is user - readable . a mask register may be included to create a range of microcode memory addresses so that executions of microcode instructions within the range are counted .