a method for fabricating cmos chips , using a sram cell composed of , both nfet and pfet devices , or only nfets , as well as incorporating nfet and pfet peripheral devices , is described . this process features an nfet , used in the sram cell , where a lightly doped arsenic source and drain region is used to achieve maximum device performance , in terms of saturation current , as well as gate to diffusion overlap capacitance . however the nfet used for the peripheral device is fabricated using a lightly doped phosphorous source and drain region , to allow for more protection against the deleterious hot carrier injection phenomena .