an mfis memory array having a plurality of mfis memory transistors with a word line connecting a plurality of mfis memory transistor gates , wherein all mfis memory transistors connected to a common word line have a common source , each transistor drain serves as a bit output , and all mfis channels along a word line are separated by a p + region and are further joined to a p + substrate region on an soi substrate by a p + region is provided . also provided are methods of making an mfis memory array on an soi substrate ; methods of performing a block erase of one or more word lines , and methods of selectively programming a bit .