an output coding apparatus includes a coder for coding an inputted bitstream to an error correction and / or detection code composed of information bits and check bits ; and a bitstream assembling section for assembling an outputted bitstream by inserting a synchronization code at any one of a plurality of synchronization code insertion positions previously determined in the outputted bitstream , arranging the information bits at any desired positions of the bitstream , and by arranging the check bits at positions other than the synchronization code insertion positions in the bitstream . therefore , when the coding apparatus is combined with a resynchronization method using both an error correction and / or detection code and a synchronization code , it is possible to solve a problem caused by pseudo - synchronization or synchronization - loss pull - out or step - out due to erroneous detection of the synchronization code .