disclosed is an electrical technique for clamping the bitline voltage above zero volts in a dram circuit . the technique may be used in embedded dram arrays implemented in logic - based technology employing low threshold voltages . the invention employs a low voltage generator to provide a bitline voltage slightly above zero volts . applying this slightly elevated level to the input of a dram cell access transistor effectively increases the threshold voltage of that transistor and thus limits sub - threshold leakage current . the low voltage generator may be implemented as a cascode circuit with supplemental current sources .