in a multilayer logic device or processor device with a plurality of individually matrix - addressable stacked thin layers of an active material , the active material in each layer is provided between a first electrode set and a second electrode set wherein the electrodes in the first set realize the columns and the electrodes in the second set the rows in an orthogonal array . the intersections between the electrodes in the array define logic cells in the layer of active material , and the stacked layers of active material are provided on a common supporting substrate . a separation layer with determined electrical or thermal properties is provided between each layer of active material .