a memory device formed on an ic chip includes dynamic random access memories for effecting data read and write operations , first and second data terminals for receiving data from an external side of the ic chip , and a controller having a first data input connected to the first data terminal to receive first data , a second input connected to receive second data read , a third data input connected to the second data terminal to receive a function mode signal , and operation unit for executing operations between the first data provided from the first data input and the second data provided from the second input . the operation unit includes a function setting unit responsive to the function mode signal for setting a function indicated by the function mode signal prior to receipt of the first data . the second data is read out of a selected part of the storage locations . the operation corresponding to the function set by the function setting unit is executed for the first and second data . the result of the execution is written into the selected part of the storage locations via the input of the dynamic random access memories during one memory cycle .