a method for mapping an electronic digital circuit to a look up table based programmable logic deviceoperates by selecting an unmapped or partially mapped lut , and identifying a group of circuit elements for mapping on the selected lut based on the available capacity of the selected lut and the mapping constraints . the identified circuit elements are mapped onto the selected lut . the identification of circuit elements and mapping is carried out while taking into consideration the cascade logic associated with the selected lut . the process continues until all circuit elements have been mapped . the group of circuit elements is mapped to the cascade logic prior to mapping on the luts . conversely , the cascade logic is incorporated only after all circuit elements have initially been mapped onto luts or some elements remain unmapped after all luts have been utilized . the mapping constraints include timing , placement , and size constraints .