a memory address generation method and circuit architecture for time - multiplexed rs - based ldpc code decoder is presented . the method is developed for non quasi - cyclic rs - based ldpc code decoder implementation . a circuit for the memory address generation method achieves low area . high throughput time - multiplexed rs - based ldpc code decoder design models and circuit architectures are presented . the decoder models are specifically developed for 10base - t system . these time - multiplexed architectures enable higher throughput with lower area .