a bit - line sensing control circuit includes a first circuit for activating a word line and a bit line associated with a first block of a memory cell array in response to a first initial activating clock . a delay circuit generates a second initial activating clock from the first initial activating clock a predetermined period after the first initial activation clock . a second circuit for activating a word line and a bit line associated with a second block of the memory cell array is initiated in response to the second initial activating clock . because the second block of memory cells are sensed after the first block of memory cells , spike noise related problems are substantially avoided .