a methodology and implementing system 101 are provided in which a pci bus is enhanced to operate at a plurality of data transfer speeds , including for example , 133 mhz in order to accommodate subsystem boards operating at higher frequencies , while at the same time allowing normal 66 mhz pci clocking for devices designed to operate at the lower 66 mhz standard pci speed . master strobe mstb 303 , 403 and target strobe tstb signals 309 , 411 are generated in a handshaking methodology to determine if a master data transaction requesting device and a target data transaction device are designed to operate at the higher data transfer frequency . higher frequency capable devices or boards are run at the increased frequency when both the requesting master and the selected target devices request the higher transfer rate , and standard devices or boards are run at the lower standard pci frequency , while both master and target devices are coupled to and run from the same multi - speed pci bus 125 .