a first and a second netlist of a first and a second function block of a circuit design are correspondingly partitioned into at least a first and a second partition , and a third and a fourth partition respectively . the first and third partitions include majorities of the constituting elements of the first and second netlists respectively . the second and fourth partitions include minorities of the constituting elements of the first and second netlists . placements of the constituting elements of the first and third partitions are correspondingly determined . the second and fourth partitions are merged to form a composite partition , which in turn is partitioned for joint determination of placement of these minority constituting elements of the first and second netlists of the first and second function blocks on logic devices . in one embodiment , the second and fourth partitions operate in the one clock domain , while the first and third partitions operate in one or more other clock domains .