an arithmetic - logic unit alu having three data input ports a , b and c , a modulo adder / subtracter for executing an arithmetic - logic operation of mod , a comparator for determining whether the input data a , b and c satisfy at least one of the relationship of a ≦ b ≦, a ≦ b & lt ; c , a & lt ; b ≦ c and a & lt ; b & lt ; c from a modulo operation viewpoint , and outputting a comparison judgment signal , a two - input alu for executing an arithmetic - logic operation of two data , and one data output port for outputting operation results .