an sram transistor cell on a doped semiconductor substrate comprises two access fet transistors and two storage fet transistors . a first load capacitor has a plate connected to a first node with the other plate connected to the power supply . a second load capacitor has a plate connected to the second node with the other plate connected to the power supply , a bit line and a bit line bar . the first storage transistor drain connects to the first node . the second storage transistor drain connects to the second node . the storage transistors have interconnected sources . the first node connects via a first interconnection line to the second transistor gate . the second node connects via a second interconnection line to the first transistor gate . first and second access transistor gates connect to a wordline . the first access transistor drain connects to the first node . the second access transistor drain connects to the second node . the first access transistor source connects to the bit line . the second access transistor source connects to the bit line bar .