a transport circuit is described for generating enable signals in different independent clock domains enabling data transfers across the clock domains . the transport circuit is used , for example , in an ethernet receive interface where data is to be transferred from a receive clock domain to a system core clock domain for further processing . a serial to parallel data converter is used to convert the serial ethernet data into parallel form . the output of the serial to parallel data converter is transferred to a holding register in the receive clock domain . the holding register connects to a transfer data register that is in the system core clock domain . the transport circuit provides enable signals with the proper timing to allow the transfer of data from the receive clock domain to the system core clock domain . the last data transfer swaps the interface supplied data with a status word in the holding register .