a central clock signal generator generates a plurality of odd and even clock pulses which are distributed to a plurality of logic and circuit modules by clock signal lines of equal length . the central signal generator also generates a plurality of gate pulses which are supplied to the modules on signal lines which can be different in length from one to another . the gate pulses are wide enough to coincide with the clock pulses with appropriate allowance for skew between the pulses . for each pair of pulses engaged delivered to a module a detection circuit is provided which detects if the gate pulse and the clock pulse begin and end in the proper sequence . if an improper sequence occurs , the information is stored in a scannable latch and a machine stop control is generated . the exact failing module can be traced readily from the information supplied in this manner .