this disclosure relates to a charge coupled device memory that is content or associative addressable with the respective word locations being searched concurrently although word access is serial in manner . data bits in respective word loops are arranged in a staggered manner such that when the first bit of the first word is at its comparison location , the second bit of the second word is at its comparison location and so forth . the comparand and mask bits are shifted serially from comparison location to comparison location and recirculated in synchronism with the recirculation of the word loops . content addressing logic includes a series of match bit shift registers , one for each comparison location , to record match occurrences . when a word match occurs , the address of the respective word loop is sent to the memory to read out the data bits stored therein . various embodiments are disclosed to illustrate that the memory may be formed of any number of word locations having any number of bit positions per word .