multi - step sub - ranging analog - to - digital converters utilize a plurality of converter modules to generate sub - ranges of bits for a digital output signal during a multi - phase conversion cycle . each subsequent converter utilizes reference voltage levels corresponding to conversions performed by prior converters during the timing phases of the conversion cycle . settling time for these reference voltages , which limits the speed and / or accuracy of each conversion , may be reduced by pre - charging the reference input nodes of the subsequent converters using the analog input signal during a timing phase in which a prior converter is converting the analog input signal to generate one of the sub - ranges for the digital output signal .