a circuit comprising : an execution unit ; a plurality of addressable devices ; and a data transfer engine coupled to the execution unit and to the devices , operable to fetch a plurality of descriptors under control of the execution unit , and based on each of the fetched descriptors to perform a transfer of data from a respective first to a respective second of the devices . the dma engine comprises delay circuitry operable to block , during a delay period running from an earlier of the transfers , any later of the transfers involving at least one of the same devices as the earlier transfer , the delay circuitry being arranged to control the blocking in dependence on an indication received in one of the descriptors .