the present invention utilizes clock bursting to minimize command latency in a logic simulation hardware emulator / accelerator . the emulator / accelerator includes an emulator system having logic gate functions representing a design under test . the logic gate functions further include special burst clock logic for toggling a clock signal to a plurality of latches within the design under test for a predefined number of clock cycles . a host workstation , coupled to the emulator system by a high - speed cable , provides control for the emulator system . in normal operation , the host workstation encodes a predefined number of clock cycles for the emulator to run , then transmits the encoded number of cycles to the burst clock logic via the high - speed cable . the host workstation then generates a trigger signal within the high - speed cable , which directs the burst clock logic to read and decode the predefined number of cycles and begin toggling the clock signal .