a method of completing the secure hash algorithm computation in exactly 81 clock cycles with digital hardware . the general implementation techniques include : using a combination of synchronous storage elements to store the required computation values and asynchronous circuits to perform all the logic and mathematic operations of each step of the 81 - step sha - 1 computation within a single clock cycle ; using a quad - output - channel 16 × 32 - bit circular queue memory to store the 512 - bit message segment , as a computation buffer of the wt parameter , and to supply the wt - 3 , wt - 8 , wt - 14 , and wt - 16 data parameters simultaneously ; using a combination of a counter circuit and a decoder / encoder circuit to control selecting data parameters and sequencing the 81 - step sha - 1 computation ; and using an automated controller to control internal units that perform sha - 1 and allowing external systems to access the sha - 1 computation service . the robust architecture allows for a highly efficient digital hardware implementation .