a shared memory switch is provided for storing and retrieving data from blockram memory of a pld . a set of class queues maintain a group of pointers that show the location of the incoming “ cells ” or “ packets ” stored in the memory in the switch based on the time of storage in the bram . a non - blocking memory architecture is implemented that allows for a scalable n × n memory structure to be created . a write controller stripes the data across this n × n memory to prevent data collisions on read in or read out of data . the data is scheduled for read out of this n × n shared memory buffer based on priorities or classes in the class queues , with priorities being set by a user , and then data is read out from the bram .