an array of non - volatile memory cells in a semiconductor substrate of a first conductivity type . each memory cell comprises first and second regions of a second conductivity type on a surface of the substrate , with a channel region therebetween . a word line overlies one portion of the channel region , is adjacent to the first region , and has little or no overlap with the first region . a floating gate overlies another portion of the channel region , and is adjacent to the first portion and the second region . a coupling gate overlies the floating gate . an erase gate overlies the second region . a bit line is connected to the first region . a negative charge pump circuit generates a negative voltage . a control circuit generates a plurality of control signals in response to receiving a command signal , and applies the negative voltage to the word line of unselected memory cells .