disclosed are methods for utilizing programmable logic devices that contain at least one localized defect . such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect . if the fpga is found to be unsuitable for one design , additional designs may be tested . the test methods in some embodiments employ test circuits derived from a user &# 39 ; s design to verify pld resources required for the design . the test circuits allow pld vendors to verify the suitability of a pld for a given user &# 39 ; s design without requiring the pld vendor to understand the user &# 39 ; s design .