there is a bi - level bit line architecture . specifically , there is a dram memory cell and cell array that allows for six square feature area cell sizes and avoids the signal to noise problems . uniquely , the digit lines are designed to lie on top of each other like a double decker overpass road . additionally , this design allows each digit line to be routed on both conductor layers , for equal lengths of the array , to provide balanced impedance . now noise will appear as a common mode noise on both lines , and not as differential mode noise that would degrade the sensing operation . furthermore , digit to digit coupling is nearly eliminated because of the twist design .