a semiconductor memory device comprises a word lines , pairs of complementary data lines , memory elements respectively arranged at each intersection of the word lines and the pairs of complementary data lines , pairs of complementary signal lines each associated with a sense amplifiers and selectively connected to one of the pairs of complementary data lines via a pair of transfer gate transistors , first precharge means for charging the pairs of complementary data lines and second precharge means for charging the pairs of complementary signal lines . the second precharge means charge the pairs of complementary signal lines to a first voltage , the first precharge means charge the pairs of complementary signal lines to a second voltage which is smaller than the first voltage by a threshold voltage of the transfer gate transistors and the transfer gate transistors have their gate electrodes supplied with the first voltage . the transfer gate transistors are n - channel type mos transistors and the first and the second precharge means include n and p channel mos type transistors respectively .