an apparatus comprising a plurality of buffers and a channel router circuit . the buffers may be each configured to generate a control signal in response to a respective one of a plurality of channel requests received from a respective one of a plurality of clients . the channel router circuit may be configured to connect one or more of the buffers to one of a plurality of memory resources . the channel router circuit may be configured to return a data signal to a respective one of the buffers in an order requested by each of the buffers .