disclosed is a semiconductor memory device with a reduced write recovery time and an increased refresh period . the semiconductor memory device incorporating a plurality of memory cells therein , including : a bit line sense amplifier array provided with a plurality of bit line sense amplifiers for sensing and amplifying data of the memory cells applied to bit lines ; and a blsa driving control means for overdriving a bit line connected to the bit line sense amplifier in response to an active command , and for overdriving the bit line in response to a precharge command .