the use of x &# 39 ; s in rtl design is widely common for improving synthesis results and , in some cases , verification effectiveness . however , it has certain implications on verification completeness . human design error or flawed synthesis may lead to undesirable non - determinism on design outputs , not always detected consistently by simulators . this disclosure presents a framework for formalizing observable behavior on digital design output , and a proof methodology for detecting non - determinism or proving correctness with respect to observable x , using a model checker .