in a pseudo - static random access memory of the invention , refresh operations are conducted in a normal mode and a self - refresh mode . the memory includes a plurality of bit - line pairs each having two bit lines , a precharge voltage generating circuit for precharging the plurality of bit - line pairs to a first potential level during a precharge period in the normal mode , the circuit being electrically connected to the plurality of bit - line pairs during the precharge period in the normal mode ; and bit line discharge circuit for discharging the bit - line pairs during a precharge period in the self - refresh mode , thereby decreasing the potential level of the bit - line pairs to a second potential level which is below the first potential level .