disclosed is a method of designing voltage partitions in a solder bump package for a chip , comprising : determining the current requirements of a chip voltage island , the chip voltage island including chip power and signal pads , and creating an equivalent circuit model of the chip voltage island ; defining a package voltage island , the package voltage island including power and signal package pins , and creating an equivalent circuit model of the package voltage island ; analyzing electrical attributes of a combination of the chip voltage island model and the package voltage island model ; and modifying the package voltage island until the electrical attributes are acceptable .