a semiconductor memory device includes a pair of bit lines connected to a plurality of memory cells , a first transistor connected between the pair of bit lines , a second transistor between at least one of the pair of bit lines and a first power supply voltage line , and a diffusion layer region shared between the first transistor and the second transistor , and connected to the one of the pair of bit lines . a gate of the first transistor and a gate of the second transistor are connected to each other . a gate of the first transistor is provided such that both a direction of a gate width of the first transistor and a direction of a gate width of second transistor are on one identical extension line .