a memory cell includes devices having associated isolation recesses of differing magnitudes . the effective channel width of a corresponding transistor is substantially equal to a channel top surface width plus twice a sidewall width formed by the isolation recesses . in an sram cell , a latch transistor has a larger effective channel width than an associated pass transistor by forming larger recesses , and therefore larger sidewalls in isolation layers surrounding the latch transistor and limiting such recesses for pass transistors . during manufacture of the memory cell , a mask is used to mask an area of the pass transistor while exposing an area of the latch transistor . accordingly , recesses in an isolation layer around the latch transistor are formed without affecting a corresponding area around the pass transistor .