an apparatus generates addresses for circular address buffers in a memory , in which a higher boundary of a circular buffer is implied from the current address . this approach is applied alone , and in combination with circular buffers which rely on an implied lower boundary to improve memory usage and flexibility in the design of circular buffers for integrated circuits . the dual mode address generator comprises inputs that receive a current address a , an address offset m , a buffer length l and a control signal ; and logic configured to compute a first memory address for a buffer with an implied lower boundary and a second memory address for a buffer with an implied higher boundary in response to a , m , and l . one of the first and second memory addresses is provided in response to the control signal . the first memory address corresponds the current address a plus the address offset m for a first circular buffer having an implied lower address boundary x and including addresses x through ; and the second memory address corresponds the current address a plus the address offset m for a second circular buffer having an implied higher address boundary y and comprising addresses y through .