a differential capacitive transducer system is disclosed that includes first and second capacitive cores and a chopping system . the first core a first input coupled to a first capacitor , a second input coupled to a second capacitor , and a first output . the second core includes a third input coupled to a third capacitor , a fourth input coupled to a fourth capacitor , and a second output . the chopping system has first and fourth inputs coupled to positive signals , and second and third inputs coupled to negative signals . as the chopping system switches between high and low states , it couples the core inputs to different polarity signals reducing charge buildup . the different polarity signals can have substantially same magnitudes . chopper clock and main clock frequencies can be selected to provide substantially zero average voltages at the core inputs . the system can include an integrator circuit and differential summing circuits .