an arbitration controller that temporarily raises the priority of a graphic device &# 39 ; s hwm request above that of the bitblt engine while that device &# 39 ; s lwm request is being served . in this manner , the bitblt engine cannot interrupt the transfer of data to the graphics device . each device capable of issuing memory access requests is categorized into one of four classes . the lwm requests are the highest priority requests , followed by cpu memory access requests , then bitblt engine requests , and finally by hwm requests . when a lwm request is granted , the requesting device &# 39 ; s hwm request is elevated to a priority between the cpu and the bitblt engine . once the lwm request is complete , the hwm request is served until either it completes , the cpu issues a memory access request , or another lwm request occurs .