the method for fabrication of a self - aligned gate cmos structure which employs no additional masking steps as compared to the standard cmos fabrication process , this improved process providing the advantages of self - alignment between the n + and p + source and drain diffusions with respect to their gate regions , and metal contact openings which do not overlap the edges of the p + or n + source and drain regions . the self - aligning gate region is defined by a silicon nitride gate layer . several embodiments of the novel process are described .