a pulse width digital to analog converter is constructed which provides an output clock rate that is a multiple of the input sampling rate . in one embodiment a latch is used to store n - bit digital word representing the analog signal value to be generated . of the most significant bits are stored in a counter which decrements its count in response to a clock signal . a plurality of least significant bits of said digital word stored in said latch are applied to a logic circuit . a ring counter is utilized to indicate which section of the output signal is currently being generated . the plurality of the least significant bits of the digital word stored in the latch , together with the output signals from the ring counter , are applied to said logic circuit , and the transition of the output signal of the digital to analog converter from a logical one to a logical zero is delayed , when required , to provide a slightly increased output pulse width in response to said plurality of least significant bits of said digital word , thereby maintaining or even increasing the resolution of the system .