a latch circuit for temporarily storing an input signal and successively outputting the input signal is disclosed , that comprises an input transfer circuit for inputting a reference clock signal , a first inverter for inverting an output signal of the input transfer circuit , a second inverter for inverting an output signal of the first inverter , and a hold transfer circuit for inputting an output signal of the second inverter and outputting it to the first inverter , wherein a second clock signal is input to the gate of the hold transfer circuit , the signal level of the second clock signal becoming high with a predetermined delay against a leading edge of the reference clock signal and becoming low corresponding to a trailing edge of the reference clock signal .