selectively distributing a plurality of data items to a plurality of hardware destinations that share a common bus involves , for each one of the data items , determining which of the hardware destinations the data item should be distributed to , wherein at least one of the data items should be distributed to two or more hardware destinations . the data item is then supplied to the common bus and , for each of the hardware destinations to which the data item should be distributed , a corresponding hardware destination signal is generated that causes the data item to be received in the hardware destination from the common bus , wherein for each data item , the corresponding hardware destination signals are generated substantially simultaneously . this may be applied in a number of scenarios , including the distribution of data items to a plurality of processor boards , and to the distribution of data items to a plurality of channels within a single processor board . a similar approach is provided for forming a sequence of data items by selectively collecting a plurality of data items from a plurality of processor boards in a multiprocessor system .