the digital programmable delay scheme with automatic calibration is an alternative to plls , dlls , fixed delay cells and other methods of delay . the method and circuit sets a delay in a programmable delay cell in an oscillator circuit and uses a reference clock to calibrate the oscillator clock frequency . the programmable delay , once set , may then be used to determine a desired delay for a signal that passes through the programmable delay cell as well as another portion of the oscillator circuit . the circuit preferably uses two counters that are controlled by calibration and control logic in which one counter is clocked by the reference clock and the other is clocked by the oscillator circuit clock . after a predetermined time , the calibration and control logic compares the two count values and determines if the programmable delay cell of the oscillator circuit needs to be adjusted . if the oscillator circuit is determined to need adjustment , the calibration and control logic circuit so adjusts the programmable delay cell . the resulting circuit is small , flexible , and pvt calibrated and consumes very little power . it can be used with any reference clock to support various timing requirements at different frequencies .