a low - overhead scheme for built - in self - test of digital designs incorporating scan allows for complete fault coverage without modifying the function logic and without degrading system performance . by altering a pseudo - random bit sequence with bit - fixing logic at an lfsr &# 39 ; s serial output , deterministic test cubes that detect random pattern - resistant faults are generated . a procedure for synthesizing the bit - fixing logic allows for complete fault coverage with low hardware overhead . also , the present approach permits the use of small lfsr &# 39 ; s for generating the pseudo - random bit sequence . the faults that are not detected because of linear dependencies in the lfsr can be detected by generating more deterministic cubes at the expense of additional bit - fixing logic .