a combined method of fabricating embedded flash memory cells having salicide and self - aligned contact structures is disclosed . the sac structure of the cell region and the salicide contacts of the peripheral region of the semiconductor device are formed using a single mask . this is accomplished by a judicious sequence of formation and removal of the various layers including the doped first and second polysilicon layers in the memory cell and of the intrinsic polysilicon layer used in the peripheral circuits . thus , the etching of the self - aligned contact hole of the memory cell is accomplished at the same time the salicided contact hole of the peripheral region is formed . furthermore , the thin and thick portions of the dual - gate oxide of the two regions are formed as a natural part of the total process without having to resort to photoresist masking of one portion of the gate oxide layer with the attendant contamination problems while removing the portion of the gate oxide in the other region of the substrate .