a method of testing a memory cell includes generating a logic low signal , generating a logic high signal , reducing the logic high signal to a level corresponding to the logic low signal plus an offset to produce a reduced logic high signal , providing the logic low signal and the reduced logic high signal to a memory cell , allowing the memory cell to achieve a memory state , and testing the memory cell to determine if the memory state is an expected memory state . a memory array has an array of memory blocks , a write select circuit to provide write data to the array of memory blocks , and a data retention test circuit to reduce write data having a level corresponding to a logic high to a level corresponding to a logic low plus an offset .