a semiconductor device has multilevel memory cells , each cell storing at least three levels of data each . at least a first data composed of first data bits and a second data composed of second data bits are arranged in order that at least a bit of an n - order of the first bits and a bit of the n - order of the second bits are stored in one of the cells , the n being an integral number . a voltage corresponding to the n - order bits is generated and applied to the one of the cells in response to an address information corresponding thereto . another semiconductor device has multilevel memory cells arranged so as to correspond to a physical address space , each cell storing 2 n levels of data each expressed by n number of bits . a logical address is converted into a physical address of the physical address space . judging is made whether a logical address space including the logical address matches the physical address space . when matched , the most significant bit x1 is specified once using a reference value . the specified bit is output from one of the cells corresponding to the physical address . if not matched , the bits are specified by n -- time specifying operation maximum using maximum n number of different reference values . the data writing / reading operations to / from the semiconductor devices can be stored in a computer readable medium as program codes for causing a computer to execute these operations .