a method for evaluating the upper bound fault coverage of an integrated circuit or a portion thereof from register transfer level description is provided . the method requires the analysis of a circuit described in rtl consisting of primary input and output pins as well as devices connected to each other and / or to the primary pins to determine the controllability and observability of each pin of the circuit to ‘ stuck at zero ’ and ‘ stuck at one ’ conditions . the upper bound fault coverage is then determined based on the ratio between the number of pins that are both controllable and observable and twice the number of pins in the circuit . the method does not require a dynamic simulation for its fault coverage assessment and hence is advantageous over other methods consuming significant time and resources .