a dynamic random access memory cell comprising a deep trench storage capacitor having an active transistor device partially disposed on a side wall of the trench . the side wall is aligned to a first crystallographic plane having a crystallographic orientation along a single crystal axis . a process for manufacturing such a dram cell comprises : forming a deep trench in a substrate , forming a faceted crystal region along the trench side wall having a single crystallographic orientation , and forming a transistor device partially disposed on the faceted crystal region in the side wall . the faceted crystal region may be formed by growing an oxide collar , such as by local thermal oxidation under oxidation conditions selected to promote a higher oxidation rate along a first family of crystallographic axes than along a second family of crystallographic axes .