an apparatus and a method for filtering glitches in a data communications controller receiving asynchronous input data signals varying between two signal levels representing two bit values and having a predetermined input bit period , and sending output data signals corresponding to the input data signals . the glitches comprise reversals of signal level , having a glitch duration less than the predetermined bit period , on the input data signals . glitches are detected in the input data signals by detecting reversals of signal level having a predetermined duration less than the predetermined input bit period . a glitch time value corresponding to the glitch duration is determined , and then a sampling clock rate is determined from the glitch time value . the input data signals are sampled at the sampling clock rate to generate a sequence of input data samples . a predetermined voting number of input data samples are monitored and an output signal is provided , representing the value of a majority of the sequential input data samples . finally , a voting number of subsequent input data samples are monitored and output signals are provided , representing the value of a majority of those subsequent input data samples .