a structure and a process for a self - aligned vertical pnp transistor for high performance sige cbicmos process . embodiments include sige cbicmos with high - performance sige npn transistors and pnp transistors . as the pnp transistors and npn transistors contained different types of impurity profile , they need separate lithography and doping step for each transistor . the process is easy to integrate with existing cmos process to save manufacturing time and cost . as plug - in module , fully integration with sige bicmos processes . high doping polysilicon emitter can increase hole injection efficiency from emitter to base , reduce emitter resistor , and form very shallow eb junction . self - aligned n + base implant can reduce base resistor and parasitical eb capacitor . very low collector resistor benefits from bp layer . pnp transistor can be isolated from other cmos and npn devices by bnwell , nwell and bn + junction .