the present invention relates to digital signal processors with an integrated module configured to compute a coordinate rotation digital computer in a pipeline . the pipelined module can advantageously complete computation of one cordic computation for each clock pulse applied to the cordic module , thereby providing a cordic computation for each clock pulse . one embodiment advantageously computes a first portion of a computation with a lookup table and a second portion in accordance with a cordic algorithm . advantageously , data in a cordic pipeline is automatically advanced in response to read instructions and can be automatically advanced from the beginning of the pipeline to the end of the pipeline to reinitialize the pipeline . this allows information to be retrieved from the cordic pipeline with relatively little overhead the automatic starting and stopping of the cordic pipeline advantageously allows the retrieval of computations from efficient pipeline architectures on an as - needed basis .