apparatus and a technique is disclosed for testing the access time of electronic storage arrays such as bistable storage cells fabricated in accordance with integrated circuit technology . a test pattern generator generates addresses on an &# 34 ; increment - complement &# 34 ; system and applies these addresses to a memory such as a prom being tested . all combinations of the rows and columns of the prom are exercised . output data from the prom is split into two separate buses which constitute a direct output bus and a delayed output bus . a first digital comparator compares the respective data signals for each output line on each of the buses in order to ensure that the &# 34 ; stabilized &# 34 ; output data corresponds exactly to the direct output data . a second digital comparator can be set to establish a standard for the minimum time period at which the output data from the tested prom has become acceptably stabilized . specialized clocking and controlled delay times are provided by a digital access control unit .