next , with reference to the accompanying drawings , embodiments of the present invention will be described in detail . with reference to fig2 a first embodiment of the present invention will be described . fig2 shows the structure of a latch circuit and a register circuit . referring to fig2 two stages of latch circuits are connected in series . the first stage of the latch circuit is a master side latch circuit . data is input from an input terminal in . input data is output from a connection point pm . the second stage of the latch circuit is a slave side latch circuit . in data is input from the connection point pm . input data is output from a data output terminal out . first , the master side latch circuit will be described in detail . input data received from the input terminal in is input to an input transfer circuit ( first switch ) composed of a pmos m 1 and an nmos m 2 whose source and drain are connected in parallel , respectively . a clock signal clk is input to the gate of the pmos m 1 . an inversed clock signal clkb of the clock signal clk is output to the gate of the nmos m 2 through an inverter inv 5 . an output terminal of the input transfer circuit is connected to an output driving inverter inv 1 . output data of the inverter inv 1 is output to the connection point pm . output data of the connection point pm is output to a latch pass inverter inv 2 . output data of the inverter inv 2 is output to a hold transfer circuit composed of an nmos m 3 and a pmos m 4 . output data of the hold transfer circuit is output to a connection point pfm that is an input terminal of the inverter inv 1 . here , the inverters inv 1 and inv 2 and the hold transfer circuit m 3 and m 4 construct a hold circuit . a clock signal clk 1 is input to the gate of the nmos m 3 of the hold transfer circuit . an inverted clock signal of the clock signal clk 1 is input to the gate of the pmos m 4 of the hold transfer circuit through an inverter inv 6 . the structure of the master side latch circuit is the same as the structure of the slave side latch circuit . the clock signal clk is input to the gate of an nmos m 5 of an input side transfer circuit . the inverted clock signal clkb of the clock signal clk is input to the gate of a pmos m 6 of the input side transfer circuit . however , a clock signal clk 2 is input to the gate of a pmos m 7 of a hold transfer circuit . an inverted clock signal of the clock signal clk 2 is input to the gate of an nmos m 8 of the hold transfer circuit . ( 2 ) description of operation next , with reference to fig2 the operation of the first embodiment will be descried . when the signal level of the clock signal clk changes from high to low , the input transfer circuit ( ml and m 2 ) of the master side latch circuit is turned on . thus , the input transfer circuit ( m 1 and m 2 ) become the through state . consequently , the input data is input to the connection point pm through an inverter . at this point , since the signal level of the clock signal clk 1 is fixed in the low level , the hold transfer circuit is kept off . on the other hand , when the signal level of the clock signal clk changes from low to high , the input transfer circuit is turned off . thus , the signal level of the connection point pfm becomes floating state . consequently , the voltage of the input data is kept in the level that takes place just before the input transfer circuit is turned off . this state is a latch state . after a predetermined time period elapses , the signal level of the clock signal clk 1 becomes high . thus , the hold transfer circuit is turned on . the input data at the connection point pm is input to the input terminal of the inverter inv 1 . as a result , a flip - flop circuit is structured . thus , data can be held as a circuit . at this point , the output data of the inverter inv 1 is inverted data at the connection point pm . the operation of the slave side latch circuit is the same as the operation of the master side latch circuit except that when the signal level of the clock signal clk becomes high , the slave side latch circuit becomes the through state ; when the signal level of the clock signal clk becomes low , the slave side latch circuit becomes the latch state . in addition , the hold transfer circuit is controlled with the clock signal clk 2 instead of the clock signal clk 1 . however , the controlling method for the hold transfer circuit of the slave side latch circuit is the same as that of the master side latch circuit . the register circuit is operated by controlling the through state and the latch state of the master side latch circuit and the slave side latch circuit corresponding to the signal state of the clock signal clk . thus , at a leading edge of the clock signal clk , the input data received from the input terminal in is latched to the master side latch circuit and output to the output terminal out through the slave side latch circuit . when the signal level of the clock clk becomes low , the input data is latched by the slave side latch circuit . thus , the output data at the output terminal out does not vary . at this point , since the master side latch circuit becomes the through state , the subsequent input data can be input from the input terminal in . fig3 b is a timing chart showing the above - described operation in the case that the clock signal clk is a low frequency signal . the pulse widths of the clock signals clk 1 and clk 2 can be given by the following formulas . where tkhkl represents the pulse width on the high side of the clock signals clk 1 and clk 2 ; tklkh represents the pulse width on the low side of the clock signals clk 1 and clk 2 ; and tdelay is a time period after the clock signal clk becomes high until the clock signal clk 1 becomes high or a time period after the clock signal clk becomes low until the clock signal clk 2 becomes high . when the clock signal clk is a high frequency signal and the relation of tkhkl & lt ; tdelay or the relation of tklkh & lt ; tdelay is satisfied in the formulas ( 1 ) and ( 2 ), pulses of the clock signals clk 1 and clk 2 are not generated . fig3 a is a timing chart showing the relation among the clock signal clk ( high frequency signal ), the clock signal clk 1 , and the clock signal clk 2 . in this case , the hold transfer circuits of the latch circuits are kept off state . thus , when the clock signal clk is a high frequency signal , since the time period tdelay is constant , the hold transfer circuits are not operated . in other words , they are as if they were absent . thus , in these circuits , since the number of transistors driven with the clock signal clk is as small as the half of the conventional circuits , the load applied to the clock signal clk decreases and the register circuit operates at high speed . thus , the registers are less skewed . when the clock signal clk is a high frequency signal , since the clock signals clk 1 and clk 2 are not generated . thus , the power consumption of the clock signals clk 1 and clk 2 reduces . in the slave side latch circuit , it is not necessary to turn off the hold transfer circuit . thus , only the circuit that outputs data is operated ( namely , the input transfer circuit is turned on ). consequently , a current fluctuation due to the circuit switching operation does not take place . thus , the time period after the clock signal clk is input until data is released can be shortened . when the clock signal clk is a low frequency signal , the signal level of the connection point pfm of the input transfer circuit ( m 1 and m 2 ) of the master side latch circuit and the signal level of the connection point pfs of the input transfer circuit ( m 5 and m 6 ) of the slave side latch circuit are in floating state . however , after data is latched until a constant time period tdelay elapses , the clock signals ckl 1 and clk 2 are input . thus , the data can be stably latched . the time period tdelay can be designated corresponding to an unstable factor ( such as noise ) of the product . the clock signals clk 1 and clk 2 can be easily generated by a logic circuit similar to the generating circuit for the clock signal clk . with a signal of which a leading edge of the clock signal clk is delayed by a delaying circuit , a leading edge of the clock signal clk 1 can be generated . on the other hand , with a signal of which a trailing edge of the clock signal clk is delayed by a delaying circuit , a leading edge of the clock signal clk 2 can be generated . trailing edges of the clock signals clk 1 and clk 2 can be generated so that they match a leading edge and a trailing edge of the clock signal clk . fig3 c shows the relation among cycle time periods and pulse widths of the clock signals clk , clk 1 , and clk 2 . as shown in fig3 c , the cycle time period ( 1 / f ) is reversely proportional to the frequency . thus , when the clock signal clk is an high frequency signal , the pulse width thereof is narrow . likewise , when the clock signal clk is a high frequency signal , the pulse widths of the clock signals clk 1 and clk 2 are narrow . as shown in fig3 c , when the signal level of the clock signal clk frequently varies from high to low , the clock signals clk 1 and clk 2 are not generated . [ second embodiment ] fig4 shows the structure of a second embodiment of the present invention . according to the second embodiment , clocked inverter circuits are used instead of transfer circuits . a clocked inverter circuit composed of a pmos ( m 11 ), a pmos ( m 12 ), an nmos ( m 13 ), and an nmos ( m 14 ) is disposed in series between a power supply and a reference voltage . input data received from an input terminal in is input to the gates of the pmos ( m 11 ) and the nmos ( m 14 ). a clock signal clk is input to the gate of the pmos ( m 12 ). an inverted clock signal clkb of the clock signal clk is input to the nmos ( m 13 ) through an inverter inv 13 . a clock signal clk 1 is input to the gate of an nmos ( m 17 ). an inverted clock signal of the clock signal clk 1 is input to the gate of a pmos ( m 16 ) through an inverter inv 14 . a clock signal clk 2 is input to the gate of an nmos ( m 25 ). an inverted clock signal of the clock signal clk 2 is input to the gate of a pmos ( m 24 ) through an inverter inv 15 . output data of the input transfer circuit ( m 11 to m 14 ) is output to a connection point pm through an inverter inv 11 . output data of the hold transfer circuit ( ml 9 to m 22 ) is input to a connection point pfs . the output data received from the connection point pfs is input to an output terminal out through an inverter inv 12 . a hold transfer circuit ( m 15 to m 18 ) inputs data received from the connection point pm and outputs the data to the connection point pfm . a hold transfer circuit ( m 23 to m 26 ) inputs data received from the output terminal out and outputs the data to the connection point pfs . the operation of the register circuit according to the second embodiment shown in fig4 is theoretically the same as the operation of the register circuit according to the first embodiment shown in fig2 . since the register circuit shown in fig4 transfers and shuts out a signal as an inverter circuit , the register circuit also operates as a buffer circuit . the register circuit according to the second embodiment may operate at high speed depending on the load of a downstream circuit thereof and characteristics of transistors thereof . since the signal level of the connection points of the latch circuits temporarily becomes floating state , when the input data received from the input terminal in varies , the connection points of the latch circuits should be protected from noise . thus , data should be input to the power supply side of the clocked inverter circuit ( pmos and nmos ), whereas a clock signal should be input to the drain output side . the master side circuit and the slave side circuit may be different circuits corresponding to the first embodiment and / or second embodiment . fig5 shows the structure of a third embodiment of the present invention . according to the third embodiment , the stability of the buffer circuit is improved in a floating period after a latch state in which the operation of the buffer circuit is the most unstable in the first embodiment until hold pulses are output . fig5 shows the structure of only a master side latch circuit . however , the structure of the master side latch circuit is the same as the structure of a slave side latch circuit . the size of a pmos ( wp ) of the data input transfer circuit is the same as the size of an nmos ( wn ) thereof . when data is latched , the voltage fluctuates at the floating connection point pfm due to noise . the voltage fluctuation takes place due to the stray capacitance ( cgp ) between the gate and drain of a pmos of a transfer circuit and the stray capacitance ( cgn ) between the gate and drain of an nmos thereof in the case that the clock signal clk is input to the pmos ( wp ) and the nmos ( wn ). normally , a latch circuit is designed so that the size of a pmos is twice as large as the size of an nmos ( the difference of their performances is twice due to the difference of mobilities ). in other words , the difference of the performances of transistors is compensated with the gate width w . thus , the delay time of an inverter logic circuit is prevented from depending on data . however , in a transfer circuit , the output level is raised and lowered by a pmos and an nmos , respectively . thus , the difference of performances corresponding to the types of transistors is not affected by input data . as a result , the latch circuit can be designed so that the gate width w of a pmos is the same as that of an nmos as long as the latch circuit is not affected by input data . when there is a difference of stray capacitance cgd between a pmos and an nmos , the difference should be compensated with the width w . the optimum transistor width is given by the following formula . thus , when data is latched to a latch circuit , noise at the floating connection point is offset by the pmos side and the nmos side . consequently , the voltage fluctuation due to noise does not take place at the connection point . fig6 shows the structure of a fourth embodiment of the present invention . as with the third embodiment , according to the fourth embodiment , when data is latched corresponding to the change of the signal level of a clock signal , noise is prevented from being applied to a floating connection point . fig6 shows the structure of a clocked inverter type latch circuit of a register circuit . to prevent the switching speed of the register from being affected by input data , the register should be designed so that the size of a pmos is twice as large as the size of an nmos . however , in this structure , the pmos side is more affected by noise . thus , when data is latched , the voltage at the connection point pfm floats . to prevent this problem , the size of the pmos to which the clock signal clk is input is reduced . a pull - up nmos to which the clock signal clk is input is disposed in parallel with a pmos to which the clock signal clkb is input . the ideal relation between a pull - down nmos and a pull - up nmos is given by the following formula ( 4 ). where wn 1 is the size of the pull - down nmos ; and wn 2 is the size of the pull - up nmos . thus , when data is latched to the latch circuit , noise applied to the floating connection point is offset by the pmos and the nmos . consequently , the noise does not cause a voltage to fluctuate at the connection point . fig7 shows the structure of a fifth embodiment of the present invention . according to the fifth embodiment , a latch pulse generating portion that generates latch pulses with a predetermined delay equivalent to clock signals clk 1 and clk 2 according to the first embodiment is accomplished by a transient response circuit that dulls the waveform of a signal with a high resistor . as with the first embodiment , input transfer circuits of a master side latch circuit and a slave side latch circuit are turned on and off with a clock signal clk and an inverted clock signal clkb of the clock signal clk . the clock signal clk is inverted as the inverted clock signal clkb by an inverter ( not shown ). a hold transfer circuit of the master side latch circuit is composed of an nmos m 73 and a pmos m 74 connected in parallel . when these mos transistors are turned on , a flip - flop circuit is formed and data is latched . as a gate signal of the nmos m 73 , a clock signal clk 3 is input from an intermediate connection point of registers r 1 and r 2 connected in series between the clock signal clk and a lowest power voltage ( gnd ) as a reference voltage . as a gate signal of the pmos m 74 , a clock signal clk 4 is input from an intermediate connection point of registers r 3 and r 4 connected in series between the inverted clock signal clkb and a maximum power supply voltage ( vdd ). as with the master side hold transfer circuit , the slave side hold transfer circuit is composed of an nmos m 77 and a pmos m 78 . however , as gate input signals , a clock signal clk 5 and a clock signal clk 6 are input . the clock signal clk 5 is input from an intermediate connection point of registers r 5 and r 6 connected between the inverted clock signal clkb and the gnd . the clock signal ckl 6 is input from an intermediate connection point of resistors r 7 and r 8 connected between the clock signal clk and the vdd . the resistance of each of the resistors r 1 to r 8 is on the order of mega - ohms . these resistors may be disposed for each register or in common with a plurality of registers ( in this case , the clock signals clk 3 to clk 6 are in common with one clock signal ). in a low frequency operation of the register , when data is latched to the master side latch circuit , the clock signal clk 3 of the master side latch circuit becomes an intermediate voltage corresponding to the ratio of resistors r 1 and r 2 . thus , the clock signal clk 3 causes the nmos m 73 to be turned on . likewise , the clock signal clk 4 is an intermediate volage corresponding to the ratio of the resistors r 3 and r 4 . thus , the clock signal clk 4 causes the pmos m 74 to be turned on . the operation of the slave side latch circuit is the same as the operation of the master side latch circuit . since the clock signals clk 3 to clk 6 are equivalent to signal loads of high resistors from the view point of the clock signals clk and clkb , the signals clk 3 to clk 6 do not affect the speed of signal changes . in a high frequency operation of the register , since the time constants of the clock signals clk 3 to clk 6 are long , the resistor cannot follow the changes of the signals . thus , the voltages of the clock signals clk 3 and clk 5 lower , whereas the voltages of the clock signals clk 4 and clk 6 rise . consequently , the switching performance of the hold transfer circuits deteriorates . as a result , when a signal frequency exceeds a predetermined frequency , the hold transfer circuits are always turned on . according to the fifth embodiment , when the resister is changed from latch state to through state , the turn off speed of the hold transfer circuits delays . since the gate volage is an intermediate voltage , the performance of the transfer circuits is very low . thus , the reduction of the transfer speed of the signals of the input transfer circuits is slight . however , the reduction does not take place when input data is a high frequency signal . thus , when the register is operated at a high frequency for high speed data output , such a problem does not take place . when high resistors are formed with diffused resistors of a poly - silicon layer , since they can be laid out on another transistor , the area of the register circuit does not increase at all . in addition , it is not necessary to provide a special latch signal ( other than the basis clock signal ) and a generating circuit thereof . thus , the circuit characteristics of the present invention can be accomplished without an increase of the installation area against the conventional circuit . according to the first to fifth embodiments , two staged latch circuits were described . however , when a plurality of stages of latch circuits are tandem - connected , a multi - bit register circuit can be structured . an inverter circuit of each latch circuit is composed of a pmos and an nmos that are tandem - connected between a power supply and a reference voltage . an input digital signal is input to the gates of these transistors . an output signal is obtained from the drains of these transistors as the connection point thereof . thus , both a latch circuit and a register circuit can be integrally fabricated in a mos process . according to the present invention , data received from an input terminal in is input to the source and drain of a pmos m 1 and an nmos m 2 connected in parallel as a transfer circuit . a reference clock signal is input to the gate of the pmos m 1 of the transfer circuit . an output terminal of the transfer circuit is connected to an output driving inverter . an output signal of the output driving inverter is input to a connection point pm . the connection point pm is connected to a latch pass inverter . an output signal of the latch pass inverter is input to a data hold transfer circuit . the output signal of the data hold transfer circuit is input to the output terminal of the input transfer circuit . the input transfer circuit and the data hold transfer circuit compose a latch circuit . a clock signal with a predetermined delay against the reference clock signal is input to the data hold transfer circuit . thus , the load of the clock signal line for controlling the operation of the register circuit can be reduced . in addition , the data release switching operation of the register circuit can be performed at high speed . moreover , when the register circuit is operated at high frequency , the power consumption of the register can be suppressed from increasing . although the present invention has been shown and described with respect to a best mode embodiment thereof , it should be understood by those skilled in the art that the foregoing and various other changes , omissions , and additions in the form and detail thereof may be made therein without departing from the spirit and scope of the present invention .