please refer to fig5 which is a function block diagram of a compact disk ( cd ) drive 40 according to the present invention . the cd drive 40 comprises a control circuit 42 , a motor 54 , and an optical module 52 . the motor 54 is used for forcing the cd 10 to rotate . when the cd 10 rotates over the optical module 52 , the optical module 52 generates a corresponding wobble clock cb . additionally , the optical module 52 can write data on the data track 12 according to a writing clock cw 1 . the control circuit 42 is used for generating the writing clock cw 1 and a frame clock cf 1 , which synchronizes with the writing clock cw 1 , and for making the frame clock cf 1 synchronize with a harmony signal , which is relatively generated with the wobble clock cb . the control circuit 42 has a clock generator 46 a and a stabilizing circuit 46 b . the clock generator 46 a comprises a first frequency divider 50 a , a second frequency divider 50 b , a third frequency divider 50 c , a fourth frequency divider 50 d , a phase - locking circuit 48 , a modification circuit 62 , and a debugging circuit 64 . the four frequency dividers 50 a - 50 d are used to divide frequencies of signals by a first ratio n1 , a second ratio n2 , a third ratio n3 , and a fourth ratio n4 respectively . the phase - locking circuit 48 comprises a phase detector 60 a , a current source 60 b , a low - pass filter 60 c , and voltage - controlled oscillator 60 d . the phase detector 60 a is capable of detecting a phase difference between two input signals . the current source 60 b is capable of generating current , and the magnitude of the current is determined by the phase difference detected by the phase detector 60 a , so that the low - pass filter 60 c can output a corresponding voltage . finally , the voltage - controlled oscillator 60 d can generate a clock signal , in which the duration of each period corresponds to the voltage received from the low - pass filter 60 c . the stabilizing circuit 46 b comprises two frequency dividers 58 a , 58 b , a phase detector pd , a frequency detector fd , and an activating circuit 56 . the clock generator 46 a of the control circuit 42 receives a system clock cs that has a plurality of periods with a same interval . the first frequency divider 50 a divides the system clock cs by the first ratio n1 to generate a first clock c 1 . the phase - locking circuit 48 generates a third clock c 3 . the third frequency divider 50 c divides the third clock c 3 by the third ratio n3 to generate the writing clock cw 1 . the second frequency divider 50 b divides the writing clock cw 1 by the second ratio n2 to generate a second clock c 2 . the first clock c 1 and the second clock c 2 are fed back to the phase - locking circuit 48 so that the phase - locking circuit 48 can synchronize the first clock c 1 with the second clock c 2 . additionally , the fourth frequency divider 50 d is used to divide the second clock c 2 by the fourth ratio n4 to generate the frame clock cf 1 . the time duration of one period of the system clock cs , the first clock c 1 , the second clock c 2 , and the writing clock cw 1 will later be respectively represented by ts , t1 , t2 , and tw1 . because the phase - locking circuit 48 locks the phases both of the first clock c 1 and the second clock c 2 to synchronize the first clock c 1 with the second clock c 2 , t1 is equal to t2 . as previously mentioned , the first frequency divider 50 a generates the first clock c 1 and the second frequency divider 50 b to generate the second clock c 2 , so n2 × tw1 = t2 and n1 × ts = t1 , and then the equation tw1 =( n1 / n2 )× ts is obtained . in other words , the period of the writing clock tw1 is directly proportional to the period of the system clock ts , and the ratio of the period of the writing clock tw1 to the period of the system clock ts is defined as a phase - locked rate ( i . e . n1 / n2 ). because the period of the system clock ts is fixed , the period of the writing clock tw1 can be easily adjusted by changing the phase - locked rate . additionally , the frame clock cf 1 is generated by dividing the writing clock cw 1 via the second frequency divider 50 b and the fourth frequency divider 50 d . the modification circuit 62 of the clock generator 46 a can repair the waveform of the wobble clock cb received from the optical module 52 by filtering noise . the debugging circuit 64 is used for generating a harmony signal , which synchronizes with the wobble clock cb that is repaired by the modification circuit 62 , according to the wobble clock cb , and adjusting the first dividing ratio n1 according to the frequency of the wobble clock cb and the phase difference between the harmony signal and the frame clock cf 1 . in the stabilizing circuit 46 b , a reference clock cr is generated by dividing the system clock cs via the frequency divider 58 a , and a compared clock cp is generated by dividing the wobble clock cb via the frequency divider 58 b . the phase detector pd and the frequency detector fs respectively detect the phase difference and the frequency difference between the reference clock cr and the compared clock cp , and then output the results to the activating circuit 56 so that the activating circuit 56 can control the rotation speed of the motor 54 via an activating signal terminal m of the activating circuit 56 . the major feature of the present invention is to adjust the frequency of the writing clock cw 1 for synchronizing and locking the frame clock cf 1 with the harmony signal , which is generated by the optical module 52 , so as to write data on the correct position of the data track 12 . the frequency divider 58 a of the stabilizing circuit 46 b divides the system clock cs by a ratio d1 to generate the reference clock cr , which is taken as a standard clock signal , so that the compared clock cp , which synchronizes with the wobble clock cb , is capable of archiving a steady state gradually according to the reference clock cr . that means that the motor 54 is controlled to operate with a stable rotation speed . in order to make the rotation speed of the motor 54 stable , it just needs to make the phase difference between the reference clock cr and the compared clock cp stable without completely phase - locking the reference clock cr with the compared clock cp . in other words , the stabilizing circuit 46 b is capable of controlling the rotation speed of the motor 54 to maintain in a relatively steady state according to the system clock cs as long as the phase difference between the reference clock cr and the compared clock cp is stable . when the motor operates stably , the periods of both the wobble clock cb and the harmony signal become unchanged . the frequencies and the phases of both the writing clock cw 1 and the frame clock cf 1 can be changed according to the wobble cb and the harmony signal so that the frame clock cf 1 can be locked with the harmony signal . the debugging circuit 64 generates the corresponding harmony signal according to the wobble clock cb , and obtains the phase difference between the harmony signal and the frame clock cf 1 . in another word , the debugging circuit 64 changes the first ratio n1 of the first frequency divider 50 a according to the frequency of the wobble clock cb and the phase difference between the harmony signal and the frame clock cf 1 to synchronize the wobble clock cb with the writing clock cw 1 . as previously mentioned , tw1 =( n1 / n2 )× ts and the frequency of the writing clock cw 1 is ( n2 × n4 ) times the frequency of the frame clock cf 1 . in the condition that the period of the system clock ts is fixed , the period of the writing clock tw1 and the frequency of the frame clock cf 1 can be controlled by changing the first ratio n1 . after the writing clock cw 1 is dived by the two frequency dividers 50 b , and 50 d to generate the frame clock cf 1 , the frame clock cf 1 is fed back to the debugging circuit 64 so as to adjust both the frequency and the period of the writing clock cw 1 and the frame clock cf 1 . finally , the frame clock cf 1 and the harmony signal of the debugging circuit 64 are phase locked without any phase difference . for example , when the rotation speed of the motor 54 is too high and causes the frequency of the wobble clock cb to increase , the debugging circuit 64 detects this situation and then reduces the first ratio n1 so that the frequencies both of the writing clock cw 1 and the frame clock cf 1 increase , and that the frequency difference between the writing clock cw 1 and the wobble clock cb decreases . similarly , if the frequency of the frame clock cf 1 is less than the harmony signal , the debugging circuit 64 decreases the first ratio so that the frequency of the writing clock cf 1 increases and that the frequency difference between the frame clock cf 1 and the harmony signal reduces . in contrast to the prior art , the present invention method locks the frame clock with the harmony signal by adjusting the frequencies of both the writing clock and the frame clock in the condition that the motor rotates stably . because the writing clock and the frame clock are generated electrically , there is a shorter response time for controlling operations of the motor compared to the prior art . moreover , the wobble clock and the writing clock can be phase - locked without changing the rotation speed of the motor , so it becomes simpler to control the operations of the motor . furthermore , because it is unnecessary to switch the cd drive from the constant linear velocity mode to the write mode , circuit design become easier and reduces the cost of the cd drive . those skilled in the art will readily observe that numerous modifications and alterations of the device may be made while retaining the teachings of the invention . accordingly , the above disclosure should be construed as limited only by the metes and bounds of the appended claims .