the overall structure of packet storage mechanism in a data switch according to the invention is illustrated in fig4 . the mechanism includes a memory 1 having the configuration of fig1 , but in addition a control state machine 21 and a set of storage registers 23 and status registers 25 . the memory 1 preferably functions as a shared memory for one or more queues of a plurality of ports . the control state machine 21 monitors data packets transmitted to the mechanism , and controls whether they are stored wholly in the memory 1 or partly in the registers 23 . in a first possible form of the switch , when a data packet arrives at the switch , it may initially be written the memory 1 in the manner described above in relation to fig2 . that is , it is written to the lowest - numbered packet buffer ( s ) which are completely empty . in this case , it may fill one of more of the packets completely , and usually leaves a last packet buffer only partly full . the control state machine 21 checks the last packet buffer , and determines the number of bytes contained there . if the number of bytes is low ( e . g . low compared to a threshold ) the control state machine 21 transfers the data from the last packet buffer to the set of registers 23 , thus emptying that packet buffer . the threshold may be fixed ( e . g . at 4 bytes , 8 bytes , 16 bytes or 32 bytes ) or it may be programmable , i . e . controlled by a value stored in a further memory ( not shown in fig4 ). in an alternative possible form of the switch , when a data packet arrives the control state machine 21 monitors it on - the - fly , and measures that the data packet is larger than an integer multiple of the packet buffer size by an overflow amount less than the threshold . if so , it partitions the data packet into a first portion which is stored in the packet buffers ( and which preferably has a size which is an integer multiple of the packet buffer size ) and a second portion which is transmitted directly to the registers 23 for storage without being written into the memory 1 . this means that the control state machine 21 does not have to copy data from the packet buffer memory 1 to the registers 23 . both forms of the invention achieve the same result . for example , the result of transmitting the data packets 5 , 7 , 9 , 11 in turn to the packet storage mechanism of the invention is illustrated in fig4 . the data packet 5 is less than twice the size of the packet buffers , and thus is efficiently stored in the packet buffers pb 1 and pb 2 , as in the prior art data switch of fig3 . however , the control state machine 21 determines that the packet 7 is more than one packet buffer length by an amount which is less than the threshold , and therefore divides the packet 7 into a first portion which is one packet buffer length and a second portion . the first portion is stored in the packet buffer pb 3 , and the second portion 27 is stored in the registers 23 . similarly , the third packet 9 is divided into a first portion which is stored in the packet buffer pb 4 and a second portion 29 which is stored in the registers 23 . the control state mechanism 21 determines that the final packet 11 has a length slightly less than three times the packet buffer length , and accordingly stores it in the three packet buffers pb 5 , pb 6 , pb 7 . thus , comparing fig3 and 5 , the embodiment is able to store the packets using seven packet buffers rather than nine . the status registers are used to record which of the storage registers 23 have been used , and which packets they relate to . this information is used by the control state machine 21 when deciding which of the storage registers 23 should be used to store the second portions of new data packets . specifically , when a new packet is to be stored , and when it is determined that a second portion of the packet is to be stored in the storage registers 23 , the control state machine 21 uses the states stored in the status registers 25 to decide which of the storage registers 23 should be used to store that second portion . the status registers 25 are then updated . the control state machine 21 is also operative to extract information from the packet buffers and the memory , in response to a read instruction . when a read instruction is received the control state machine 21 examines the status registers 25 to determine whether any of the storage registers 23 stores a part of the packet , and if so extracts the second portions of the packets from the storage registers 23 . the control state machine 21 then transmits the first and second portions of the packets out of the packet storage mechanism in the correct order , and updates the status registers to indicate that the packet is no longer stored in the packet storage mechanism . note that the memory 1 is typically implemented as a ram memory , which is a term which , as used in this field , does not include registers , such as the storage registers 23 and status registers 25 . a skilled reader will appreciate that other portions of the data switch than the packet queues may be implemented by any known system , such as according to the ethernet standard . although only a single embodiment of the invention has been illustrated , the invention is not limited in this respect and many variations are possible within the scope of the invention as will be clear to a skilled reader .