the illustrative embodiment of the present invention provides a microprocessor having a plurality of physical registers and data structures to track and recycle the physical registers . the data structures facilitate efficient management of the registers without hampering performance of the microprocessor . the data structures do not increase the memory requirements for tracking the various physical registers . as such , memory is conserved for other processing purposes . [ 0036 ] fig1 illustrates a microprocessor suitable for practicing the illustrative embodiment . the microprocessor 2 includes a register file 4 , an execution unit 6 , a reorder buffer 7 , a memory array 8 , an instruction fetching unit 9 , an instruction scheduling unit 10 , a retirement unit 12 , a free physical register list ( fprl ) 20 and a hold register 21 . the microprocessor 2 is of the type designed to handle concurrent multiple instructions during a single processor execution cycle . the execution unit 6 can execute instructions of different types in non - sequential order . for example , the execution unit 6 can access data from the memory array 8 , e . g ., load and store instructions of a program , perform arithmetic operations , and control execution flow . after the execution unit 6 executes instructions , results can be temporarily stored in the reorder buffer 7 . the register file 4 is used to store floating or fixed - point data . also , the register file 4 contains information regarding physical registers that are allocated for execution . a logical register can be mapped to any of the physical registers in the register file 4 . the retirement unit 12 receives data from the execution unit 6 regarding the execution of the instructions . the retirement unit 12 determines when it is safe to write results of each instruction from the reorder buffer 7 into the register file 4 . the register file 4 stores the final results of the instructions executed by the execution unit 6 . however , the register files can directly send data to the execution unit 6 . the possibility of data being thrown out is high because exceptions or pipeline flushes may occur at any point in time . thus , the retirement unit 12 manages the exceptions and other possible computational processes for the register files . the memory array 8 is used to store instructions of programs and data that are processed by the microprocessor 2 . the instruction scheduling unit 10 receives as input the instructions stored in the memory array 8 . the instruction scheduling unit 10 schedules the received instructions for processing by the execution unit 6 . moreover , the instruction scheduling unit 10 receives retirement information from the retirement unit 12 for scheduling instructions based on when the necessary source operands are available in the register file 4 . for each incoming instruction into the instruction scheduling unit 10 that requires a destination register , a specific physical register within the processor &# 39 ; s register file 4 is assigned to store the results of the incoming instruction , i . e ., act as the temporary holding cell for each resultant value . the process of assigning physical registers to temporarily hold the values referenced by an architectural register is referred to as “ register mapping .” the instruction scheduling unit 10 performs register mapping , tracks these mappings as instructions progress through the processor , and also ensures that each physical register is reused when it is no longer needed . the processor 2 reads instructions , executes the instructions in the execution unit 6 , and stores the result of the instructions in the reorder buffer 7 . the result of the instructions are then transferred from the reorder buffer 7 to the register file 4 , at which point the instructions are retired . for example , an instruction may be fetched that adds two numbers and then stores the result in a logical destination register that is mapped to a newly assigned free physical register . when the processor 2 fetches such instructions , the physical register that was used to previously store the contents of the logical register being overwritten by the current instruction is potentially becoming obsolete , and is therefore designated as potentially free . after the current instruction retires , thus updating the formal state of the processor 2 , the potentially free physical register has become officially obsolete and is therefore free to be reused . the free physical register list ( fprl ) 20 is a memory structure that keeps track of registers that are either potentially or truly not being used , and are therefore designated as “ free .” a physical register number is provided for each instruction that requires a destination register . once a physical register is assigned , or mapped , it is no longer considered “ free ” because it is now “ in - use .” the fprl 20 essentially acts as a first - in - first - out ( fifo ) buffer with free physical register pointers being written into the fprl 20 , and then being read out as free physical register pointers in the same order . however , in order to operate efficiently with a fixed capacity , the fprl must write only one free physical register pointer into the fifo buffer for each free physical register pointer that is read out of the fifo . therefore , each instruction that requires a physical register for use as a destination operand must also produce a physical register pointer that can re - enter the fprl as a free register . referring to fig2 which illustrates case 1 described above , an example of a sequence of instructions is shown to illustrate the instruction management method of an illustrative embodiment of the present invention . a first instruction 30 , a second instruction 32 , and a third instruction 34 are shown . also shown , in parentheses , are a first action 31 , a second action 33 , and a third action 35 that occur when the respective instructions are completed . in the example shown in fig2 the third instruction 34 is overwriting both the contents of logical register r 5 and the icc register . the contents of r 5 were previously stored in p 6 ( due to the first instruction 30 ), while the contents of the icc register were previously stored in p 7 ( due to the second instruction 32 ). therefore , it appears that the addcc instruction 34 is making the contents of two different physical registers ( p 6 and p 7 ) obsolete , thereby making them both eligible to return to the fprl 20 as free registers . however , the addcc instruction 34 is consuming only one physical register for use as a destination operand , making it possible to return only one of the two eligible physical registers to the fprl 20 . in this scenario , the addcc instruction 34 is only invalidating the icc portion of the previous writer of p 8 ( which is p 7 in this case ). therefore , p 7 continues to hold valid rd data , which is the results of the logical or performed by the orcc instruction , and cannot be returned to the fprl at this time . the p 7 register eventually reappears as a previous writer when the r 3 register is reused as a destination register . when that happens ( i . e ., when the fourth instruction 48 is received ), p 7 is made entirely obsolete and is then written into the fprl 20 . therefore , to correctly process this instruction sequence , the addcc instruction 34 writes p 6 into the fprl 20 and the sub instruction 48 writes p 7 into the fprl 20 . in particular , the memory array 8 stores the first , second , and third instruction 30 , 32 , and 34 . the instruction fetching unit 9 fetches the first instruction 30 that causes the instruction scheduling unit 10 to map the first destination register r 5 to the first physical register p 6 in the first action 31 . the instruction fetching unit 9 also fetches the second instruction 32 that causes the instruction scheduling unit 10 to map the condition code register icc and the second destination register r 3 to the second physical register p 7 in the second action 33 . in addition , the instruction fetching unit 9 fetches the third instruction 34 that causes the instruction scheduling unit 10 to map the condition code register icc and the first destination register r 5 to the third physical register p 8 in the third action 35 . while each of these instructions consumes a physical register for use as a destination register , they also produce a physical destination register to be written into the fprl 20 . thus , the third instruction 34 causes the first physical register p 6 to be written into the fprl 20 and designated as “ free ”; that is , with particular reference to the third instruction 34 , a pointer to the first physical register p 6 is written into the fprl 20 and designated as “ free .” the instruction fetching unit 9 may also fetch a fourth instruction 48 stored in the memory array 8 that causes the instruction scheduling unit 10 to map the second destination register r 3 to a fourth physical register p 9 in a fourth action 37 . as a result , the second physical register p 7 is written into the fprl 20 . the execution unit 6 may then execute the first , second , third , and fourth instruction 30 , 32 , 34 , and 48 , thereby producing a first instruction result , a second instruction result , a third instruction result , and a fourth instruction result , respectively . the reorder buffer 7 can store the first , second , third , and fourth instruction results . the retirement unit 12 can then retire the first , second , third , and fourth instruction 30 , 32 , 34 , and 48 after the reorder buffer 7 stores the instruction results . the first physical register p 6 becomes eligible for reuse as a destination register after the third instruction 34 retires . also , the second physical register p 7 becomes eligible for reuse as a destination register after the fourth instruction 48 retires . referring to fig3 which illustrates case 2 described above , another example of a sequence of instructions is shown to illustrate the instruction management method of the present invention . this instruction stream is similar to the example discussed above , except that an orrcc instruction 54 with a destination of g 0 is used . when an instruction uses a naught register , such as g 0 , as a destination register , a physical register is not assigned to that instruction for use as a destination register , unless that instruction also writes to the condition codes . since g 0 is a naught register , and cannot be used to store a value other than zero , this eliminates the possibility that p 7 will reappear later as a previous writer , as in the previous example . to correctly process streams of instructions such as this , a hold register 21 is added to the write path of the fprl 20 . the hold register 21 is designed to temporarily hold , under certain conditions , physical register pointers that are being used to store the icc register . in the example illustrated in fig3 it appears that the addcc instruction 56 is making obsolete two different physical registers , namely p 6 and p 7 , since it is overwriting the contents of the logical register r 5 and the icc register , which were previously being stored in physical registers p 6 and p 7 , respectively . therefore , the addcc instruction 56 appears to need to write two different previous writer physical registers into the fprl 20 . however , since the addcc instruction 56 is consuming only one physical register for use as a destination operand , it can only return one free physical register pointer to the fprl 20 . therefore , the p 6 register is written into the fprl 20 and designated as “ free ,” while a pointer to the p 7 physical register is moved into the hold register and designated as “ on hold ” where it remains until an opportunity presents itself to designate it as “ free ” and move it into the fprl 20 . in particular , the memory array 8 stores a first , second , and third instruction 52 , 54 , and 56 . the instruction fetching unit 9 fetches the first instruction 52 that causes the instruction scheduling unit 10 to map a first destination register r 5 to a first physical register p 6 in a first action 61 . the instruction fetching unit 9 also fetches the second instruction 54 that causes the instruction scheduling unit 10 to map the icc register to a second physical register p 7 in a second action 63 . the second instruction 54 also includes an arithmetic operation producing a result that is mapped to a naught register g 0 . in addition , the instruction fetching unit 9 fetches the third instruction 56 that causes the instruction scheduling unit 10 to map the icc register and the first destination register r 5 to a third physical register p 8 in a third action 65 . while each of these instructions consumes a physical register for use as a destination register , each also produce a physical destination register to be written into the fprl 20 . with particular reference to the third instruction 56 , a pointer to the physical register p 6 is written into the fprl 20 and designated as “ free .” the second physical register p 7 is moved into a hold register , where it remains until an unused slot becomes available in the fprl 20 ( see below ). referring to fig4 which illustrates case 3 described above , another example of a sequence of instructions is shown to illustrate the instruction management method of the present invention . the instructions in this figure are appended to those in fig3 . in this method , the add instruction 76 appears at first to make obsolete the contents of the previous writer of p 10 , which in this case is p 9 . however , p 9 is currently storing valid icc register values . therefore , p 9 cannot yet be designated as “ free ” and written into the fprl 20 . since add instruction 76 consumes a physical register for use as a destination operand , it must also produce a free physical register pointer to be written into the fprl 20 . to correctly process the add instruction 76 , the physical register being stored in the hold register at that time is then designated as “ free ” and written into the fprl 20 . under these conditions , the hold register holds a valid register pointer because the addcc instruction 56 placed the previous writer of icc into the hold register . it is also safe to move the hold register contents to the free physical register list 20 because the icc register must have been overwritten in order to cause this scenario . the p 9 register will reappear as a previous writer when an instruction that overwrites the icc is received , whereupon it will be designated as “ free ” and written into the fprl 20 . in particular , the instruction fetching unit 9 fetches the fourth instruction 70 stored in the memory array 8 that cause the instruction scheduling unit 10 to map the icc register and a second destination register r 3 to a fourth physical register p 9 . in addition , the unit 10 fetches a fifth instruction 76 stored in the memory array 8 that causes the instruction scheduling unit 10 to map the second destination register r 3 to a fifth physical register p 10 . while both instructions 70 and 76 consume a single physical register for use as a destination register , they also produce a physical destination register to be written into the fprl 20 . with particular reference to the fifth instruction 76 , a pointer to the physical register p 7 ( which is the register being stored in the hold register ) is written into the fprl 20 . the execution unit 6 executes the first , third , fourth and fifth instruction 52 , 56 , 70 , and 76 , thereby producing a first instruction result , a third instruction result , a fourth instruction result , and a fifth instruction result , respectively . the buffer 7 stores the first , third , fourth , and fifth instruction results . ( since it involves a naught register , the second instruction 54 does not cause the algebraic result to be stored .) the retirement unit 12 retires the first , third , fourth , and fifth instruction after the reorder buffer 7 stores the instruction results , wherein the first physical register p 6 becomes eligible for reuse as a destination register after the third instruction 56 retires . referring to fig5 an instruction management method alternative to fig4 is shown illustrating the present invention . the instructions in this figure are appended to those in fig3 . this example resembles the preceding case in that the subcc instruction 86 is overwriting the icc register , but is not overwriting an rd portion of a logic register due to the use of the naught register as a destination . therefore , the subcc instruction 86 cannot designate the physical register p 9 as “ free ” because it is still holding valid rd data ( i . e ., the results of the addcc operation from instruction 80 ). since the subcc instruction 86 is consuming a physical register for use as an icc destination operand , it must also produce a single physical register to be written into the fprl 20 . to correctly process the subcc instruction 86 , the physical register being stored in the hold register at that time is then designated as “ free ” and written into the fprl 20 . in particular , the instruction fetching unit 9 fetches a fourth instruction 80 stored in the memory array 8 that causes the instruction scheduling unit 10 to map the icc register and a second destination register r 3 to a fourth physical register p 9 . in addition , the instruction scheduling unit 10 fetches a fifth instruction 86 stored in the memory array 8 that cause the instruction scheduling unit 10 to map the condition code register icc to a fifth physical register p 10 . the fifth instruction 86 also includes a second arithmetic operation producing a second result that is mapped to a second naught register 90 . while both instructions 80 and 86 consume a single physical register for use as a destination register , they must also produce a physical destination register to be written into the fprl 20 . with particular reference to the fifth instruction 86 , a pointer to the physical register p 7 ( which is the register being stored in the hold register ) is written into the fprl 20 . the execution unit 6 executes the first , third , fourth and fifth instruction 52 , 56 , 80 , and 86 , thereby producing a first instruction result , a third instruction result , a fourth instruction result , and a fifth instruction result , respectively . the reorder buffer 7 stores the first , third , fourth , and fifth instruction results . the retirement unit 12 retires the first , third , fourth , and fifth instruction after the reorder buffer 7 stores the instruction results , wherein the first physical register p 6 becomes eligible for reuse as a destination register after the third instruction 56 retires . instead of the method presented in fig3 where the first physical register p 6 is written into the fprl 20 and the icc register is moved into the hold register , in another embodiment , the reverse can occur ; that is , the icc register can be written into the fprl 20 , and the first physical register p 6 can be moved into the hold register . in this different embodiment , the methods in fig4 and 5 that append the method in fig3 can be consistently modified by analogy . referring to fig6 a flowchart for managing physical registers in a microprocessor is shown . in step 100 , an fprl 20 for holding information indicative of the availability of the physical registers is provided . in step 102 , a first instruction is fetched that causes a first destination register to be mapped to a first physical register . in step 104 , a second instruction is fetched that causes a condition code register and a second destination register to be mapped to a second physical register . in step 106 , a third instruction is also fetched that causes the condition code register and the first destination register to be mapped to a third physical register . subsequently , in step 108 , the first physical register is written into the fprl 20 . in step 110 , a fourth instruction is fetched that causes the second destination register to be mapped to a fourth physical register . subsequently , in step 112 , the second physical register is written into the fprl 20 . next , the first , second , third , and fourth instruction are executed , thereby producing a first instruction result , a second instruction result , a third instruction result , and a fourth instruction result . the first , second , third , and fourth instruction results are buffered temporarily . after the step of buffering , the first , second , third , and fourth instruction are retired , and , after the third instruction retires , the first physical register becomes eligible for reuse as a destination register . another scenario where the principles of the present invention can be used to manage physical registers in a microprocessor is illustrated in fig7 where a flowchart for managing physical registers in a microprocessor is shown . in step 114 , a free physical register list is provided for holding information indicative of the availability of the physical registers . in step 116 , a first instruction is fetched that causes a first destination register to be mapped to a first physical register . in step 118 , a second instruction is fetched that causes a condition code register to be mapped to a second physical register . the second instruction also includes an arithmetic operation producing a result that is mapped to a naught register . in step 120 , a third instruction is also fetched that causes the condition code register and the first destination register to be mapped to a third physical register . subsequently , in step 122 , the first physical register is written into the fprl 20 . in step 124 , the second physical register is designated as “ on hold ” and moved into a hold register . two different sequences of instructions can appear after the instructions presented in fig7 . one sequence is addressed in fig8 where a flowchart is shown which includes instructions that may be appended to the instructions appearing in fig7 . in step 130 , a fourth instruction is fetched that causes the condition code register and a second destination register to be mapped to a fourth physical register . in step 132 , a fifth instruction is also fetched that causes the second destination register to be mapped to a fifth physical register . subsequently , in step 134 , the second physical register is removed from the hold register and written into the fprl 20 . the first , third , fourth and fifth instruction are then executed , thereby producing a first instruction result , a third instruction result , a fourth instruction result , and a fifth instruction result . the first , third , fourth and fifth instruction results are buffered . after the step of buffering , the first , third , fourth , and fifth instruction are retired . the first physical register becomes eligible for reuse as a destination register after the third instruction retires . the other sequence of instructions that can appear after the instructions presented in fig7 is addressed in fig9 where a flowchart is shown which includes instructions that may be appended to the instructions appearing in fig7 . in step 140 , a fourth instruction is fetched that causes the condition code register and a second destination register to be mapped to a fourth physical register . in step 142 , a fifth instruction is fetched that causes the condition code register to be mapped to a fifth physical register . the fifth instruction also includes a second arithmetic operation producing a second result that is mapped to a naught register . subsequently , in step 144 , the second physical register is removed from the hold register and written into the fprl 20 . the first , third , fourth and fifth instruction are then executed , thereby producing a first instruction result , a third instruction result , a fourth instruction result , and a fifth instruction result . the first , third , fourth and fifth instruction results are buffered . the first , third , fourth , and fifth instruction are then retired after the step of buffering . the first physical register becomes eligible for reuse as a destination register after the third instruction retires . instead of the method outlined in fig7 where the first destination register is written into the fprl 20 , and the condition code register is moved into a hold register , in another embodiment , the reverse can occur . that is , the condition code register can be written into the fprl 20 , and the first destination register can be moved into a hold register . in this different embodiment , the instructions in fig8 and 9 that append the instructions in fig7 can be consistently modified by analogy . numerous modifications and alternative embodiments of the invention will be apparent to those skilled in the art in view of the foregoing description . accordingly , this description illustrative only and is for the purpose of teaching those skilled in the art the best mode for carrying out the invention . details of the structure may vary substantially without departing from the spirit of the invention , and exclusive use of all modifications that come within the scope of the appended claims is reserved . it is intended that the invention be limited only to the extent required by the appended claims and the applicable rules of law .