the present invention solves the problems noted above and gives the added benefit of gain control and large output swings . by setting two 5 transistor transconductors in a single circuit sharing the common mode node and running them 180 degrees out of phase , we can achieve a balanced function which leaves the current source in saturation under all conditions . thus we have a low power circuit with good jitter performance and large output swings . further , by either cross - coupling the pmos loads or by using an externally generated reference , the forward gain can be either increased or decreased giving added functionality . the circuit in fig1 is a preferred embodiment fully differential large swing variable gain amplifier , according to the present invention . the circuit can be functionally viewed as two five transistor transconductors which share a bias current source ( transistor mn 21 coupled to source voltage vss ). the first transconductor is composed of transistors mn 18 , mn 19 , mp 14 , and mp 15 while the second transconductor is composed of transistors mn 262 , mn 266 , mp 73 , and mp 74 . these two transconductor circuits are operated 180 degrees out of phase ( by differential inputs in and ip ) to form a balanced , fully - differential , high gain , large output swing amplifier . transistors mp 29 and mp 30 are used as cross - coupled loads . cross coupling in the fashion shown in fig1 serves to increase the gain in a fixed ratio fashion where the gain increase is determined by the ratio of transistors mp 29 to mp 14 and mp 30 to mp 74 . transistor mn 21 sets a fixed bias current for the circuit . the amount of current is user selectable and is controlled through the gate connection to transistor mn 21 at node vbiasn . the drain of mn 21 forms the common mode node needed for proper differential functionality of the two circuits . two differential pairs are formed by transistor pairs mn 18 / mn 19 and mn 262 / mn 266 respectively . current mirror pairs are formed by transistor pairs mp 14 / mp 15 and mp 73 / mp 74 respectively . circuit operation is as follows , the logic value of output node op follows input node ip and output node on follows input node in . when node ip is ‘ high ’ and node in is ‘ low ’, the bias current provided by the current source flows in transistors mn 266 / mp 74 and mn 19 . no current is flowing in transistors mn 18 / mp 14 and mn 262 . the result is that the current flowing through transistor mp 74 is mirrored to transistor mp 73 . since node in is ‘ low ’ no current is flowing in transistor mn 262 , therefore current flows through transistor mp 73 long enough to pull output node op ‘ high ’ or to source voltage vdd . similarly , no current is flowing in transistors mn 18 / mp 14 since node in is ‘ low ’, therefore current flows through transistor mp 19 long enough to pull node on ‘ low ’ or to the common mode voltage at node cm . for this circuit , ‘ low ’ is defined as the voltage on the common mode node cm defined by the drain of transistor mn 21 and the sources of transistors mn 18 / mn 19 / mn 262 / mn 266 . additionally as current begins flowing through transistor mp 74 during a switching event , this current is mirrored through transistor mp 30 . as the current in transistor mp 30 increases it draws remaining current out of transistor mn 18 . this ‘ steals ’ some of the current that would normally be flowing into transistor mp 14 thereby shutting off transistors mp 14 and mp 15 more quickly . this is how the gain is increased by this configuration . after the circuit stabilizes , all the bias current sourced by transistor mn 21 is flowing through the leg containing transistors mn 266 / mp 74 . this function keeps the current flowing properly through the current source . when node ip switches to ‘ low ’ and thus node in switches to ‘ high ’, the bias current begins to flow through transistors mn 18 / mp 14 and mn 262 . current is being shut off in transistors mn 19 and mn 266 / mp 74 . therefore the current in transistor mp 14 is being mirrored to transistor mp 15 . this pulls output node on ‘ high ’. similarly , the current through transistor mp 73 is cut off so that the current flows through transistor mn 262 long enough to pull node op ‘ low ’ or to the common mode node voltage . similarly , the cross coupled device mp 29 begins to draw current and the current rapidly switches state . after the circuit stabilizes , all the bias current sourced by transistor mn 21 is flowing through the leg containing transistors mn 18 / mp 14 . this function keeps the current flowing properly through the current source . the circuit of fig2 is the same as the circuit of fig1 , except the cross coupling nodes are changed to the output nodes . this configuration acts as an attenuator amplifier . note that as node ip goes high , current begins flowing in transistors mn 19 and mp 30 . the gain reduction will be a ratio of transconductances between transistors mn 19 and mp 30 . the same function exists between transistors mn 262 and mp 29 as node in goes high . lastly , the circuits in fig3 and 4 are the same circuits depicted in fig1 and 2 , respectively , except that the gates of the cross coupling devices mp 29 and mp 30 are pulled out as separate nodes vb 1 and vb 2 . these are generic depictions of the circuits being proposed . fig1 and 2 show specific implementations where fixed ratios of devices are implemented . fig3 and 4 allow for infinite tuning ranges which is the most generic implementation for these circuits . 1 . figuring out a way to keep the current flowing through the current source without interruption . this increases the bandwidth and improves jitter performance . 2 . keeping the circuit in fully differential operation to take advantage of common mode rejection and power supply rejection . 3 . maintaining large output swings while achieving the above . output swings from common mode to source voltage vdd . 4 . introducing cross - coupled devices in two effective configurations to give the circuit variable gain capabilities . while this invention has been described with reference to illustrative embodiments , this description is not intended to be construed in a limiting sense . various modifications and combinations of the illustrative embodiments , as well as other embodiments of the invention , will be apparent to persons skilled in the art upon reference to the description . it is therefore intended that the appended claims encompass any such modifications or embodiments .