[ 0014 ] fig1 through 5 , discussed below , and the various embodiments used to describe the principles of the present invention in this patent document are by way of illustration only and should not be construed in any way to limit the scope of the invention . those skilled in the art will understand that the principles of the present invention may be implemented in any suitably arranged device . [ 0015 ] fig1 depicts a borehole production system including a converter / inverter system according to one embodiment of the present invention . borehole production system 100 includes an electrical submersible pump and motor assembly 101 lowered into a borehole 102 using a production tubing string 103 . a three - phase power cable 104 carries three - phase power into the borehole 102 to the motor within assembly 101 from a surface location . at the surface , a three - phase power source 105 , such as a generator or a connection to a local power grid , is coupled to power cable 104 by a converter / inverter system 106 . converter / inverter system 106 is constructed and operates in the manner described below to regulate the operating speed of the motor / pump assembly . those skilled in the art will recognize that the complete structure and operation of a borehole production system is not depicted in the drawings or described herein . instead , for simplicity or clarity , only so much of the borehole production system as is unique to the present invention or necessary for an understanding of the present invention is depicted and described . [ 0018 ] fig2 is a circuit diagram for a main circuit structure employed within a converter / inverter system according to one embodiment of the present invention . a discrete implementation of the circuit depicted is employed for each phase of the three - phase power system including power source 105 , power cable 104 and the motor within motor / pump assembly 101 . circuit 200 is a simplified topology multi - level converter / inverter including a plurality of series - connected electrical energy storage devices , capacitors c 1 - c 4 in the exemplary embodiment , defining nodes v1 - v5 each having distinct steady - state voltage levels , preferably of relatively fixed value , at the terminals thereof . networks 201 and 202 of switching devices selectively connect nodes v1 - v5 to a conductor carrying a sinusoidal input voltage v ac — in and to a conductor for an output voltage v ac — out based on control or switching signals csp 1 - csp 4 , csn 1 - csn 4 , isp 1 - isp 4 , and isn 1 - isn 4 . in the exemplary embodiment , the switching devices ( which are referenced in fig2 by the switching signals csp 1 - csp 4 , csn 1 - csn 4 , isp 1 - isp 4 , and isn 1 - isn 4 received by the corresponding switching device ) within networks 201 and 202 are npn insulated gate bipolar transistors ( igbts ) each having an intrinsic diode connected with reverse bias orientation across the anode and cathode ( or source / drain or emitter / collector ) of the ibgt . that is , the anode of the intrinsic diode is connected to the cathode or emitter of the igbt , while the cathode of the intrinsic diode is connected to the anode or collector of the igbt . switching devices csp 4 , csp 2 , csp 1 , csn 1 , csn 2 and csn 4 are connected in series within network 201 , and switching devices isp 4 , isp 2 , isp 1 , isn 1 , isn 2 and isn 4 are connected in series within network 202 , where the collectors of devices csp 4 and isp 4 within both networks 201 and 202 are connected to node v5 and the emitters of devices csp 4 and isp 4 within both networks 201 and 202 are connected to node v1 . switching devices csp 3 and isp 3 within both networks 201 and 202 are connected between the emitters of devices csp 4 and isp 4 within the respective network 201 or 202 and node v4 , while switching devices csn 3 and isn 3 within both networks 201 and 202 are connected between the collectors of devices csn 4 and isn 4 within the respective network 201 and 202 and node v2 . the conductor carrying the sinusoidal input voltage v ac — in for the power phase operated on by circuit 200 is connected , via a phase shifting device 203 ( an inductor in the example depicted ), to the junction within network 201 between the emitter of device csp 1 and the collector of device csn 1 . the conductor carrying the stepped sinusoidal output voltage v ac — out for the corresponding power phase is connected to the junction within network 202 between the emitter of device isp 1 and the collector of device isn 1 . each network 201 and 202 within circuit 200 also includes series - connected diodes d 1 and d 2 having a common forward bias orientation and connected in parallel with a reverse bias orientation across switching devices csp 1 and csn 1 or isp 1 and isn 1 , to the collector of device csp 1 or isp 1 and to the emitter of device csn 1 or isn 1 . the junction between diodes d 1 and d 2 within each of networks 201 and 202 is connected to node v3 , which is a grounded node in the example depicted . [ 0024 ] fig3 illustrates an output voltage waveform for one power phase from a converter / inverter system according to one embodiment of the present invention . the output voltage v ac — out of circuit 200 has a stepped sinusoidal waveform modeled after , and illustrated in comparison with , a “ pure ” sinusoidal waveform v ac — ref . the output voltage v ac — out is switched between a number of voltage levels ( five in the example shown ) with a timing determined by two switching parameters , switching angles θ 1 and θ 2 . in the single cycle illustrated in fig3 the output voltage v ac — out begins at a neutral or ground voltage level v3 ( although voltage level or node v3 need not necessarily be grounded ) and is initially switched to a first positive voltage level v4 at a point during the cycle corresponding to switching angle θ 1 , then is switched to a second positive voltage level v5 greater than the first positive voltage level v4 at a point during the cycle corresponding to switching angle θ 2 . the output voltage v ac — out is dropped to the first positive voltage level v4 at a point during the cycle corresponding to π − θ 2 , and then to the neutral or grounded voltage level v3 at a point during the cycle corresponding to π − θ 1 . the output voltage v ac — out is maintained at the neutral or grounded voltage level v3 through the end of the positive half of the cycle . during the negative half of the cycle , the output voltage v ac — out similarly begins at the neutral or ground voltage level v3 and is initially switched to a first negative voltage level v2 at a point during the cycle corresponding to π + θ 1 . the output voltage v ac — out is switched to a second negative voltage level v1 , having a greater magnitude than the first negative voltage level v2 , at a point during the cycle corresponding to π + θ 2 , then is switched back to the first negative voltage level v2 at a point during the cycle corresponding to 2π − θ 2 . the output voltage v ac — out is returned to the neutral or grounded voltage level v3 at a point during the cycle corresponding to 2π − θ 1 , and maintained at that voltage level v3 through the end of the negative half of the cycle . circuit 200 produces the output voltage v ac — out depicted in fig3 by asserting control signals applied to switching networks 201 and 202 in a manner to selectively connect the conductors carrying the input voltage v ac — in and the output voltage v ac — out to the nodes / voltage levels v1 - v5 . switching devices csp 1 - csp 4 and csn 1 - csn 4 within network 201 connect nodes v1 - v5 to the input voltage v ac — in to charge capacitors c 1 - c 4 , while switching devices isp 1 - isp 4 and isn 1 - isn 4 within network 202 connect nodes v1 - v5 to the output voltage v ac — out to product the appropriate output voltage level during respective portions of each cycle . the reverse - bias intrinsic diodes within each igbt act as clamping devices constraining the voltages passed to or from nodes v1 - v5 to the respective voltage levels . the output voltage levels or nodes v1 - v5 and the corresponding necessary control signal / switching device states for the switching devices within networks 201 and 202 to connect a respective input or output voltage v ac — in or v ac — out to that voltage level or node v1 - v5 are summarized below in table i ( where a logical “ 1 ” indicates that the respective control signal and switching device are asserted and on , while a logical “ 0 ” indicates that the respective control signal and switching device are not asserted and off ): table i output csp1 / csp2 / csp3 / csp4 / csn1 / csn2 / csn3 / csn4 / voltage isp1 isp2 isp3 isp4 isn1 isn2 isn3 isn4 v1 0 0 0 0 1 1 0 1 v2 0 0 0 0 1 1 1 0 v3 1 0 0 0 1 0 0 0 v4 1 1 1 0 0 0 0 0 v5 1 1 0 1 0 0 0 0 switching network 201 within circuit 200 operates as a converter ( a regulated rectifier ) while switching network 202 operates as an inverter . switching networks 201 and 202 operate in exactly the same manner and provide similar waveforms . however , counterpart switching devices within networks 201 and 202 ( i . e ., switching device csp 1 within network 201 and switching device isp 1 within network 202 , etc .) need not — and in most cases generally will not — be switched at the same instant ; instead , switching networks 201 and 202 may be operated independently , but in concert , to produce the stepped sinusoidal output voltage v ac — out for one power phase ( a , b or c ). thus , switching network 201 operates at the frequency of the input voltage v ac — in with one set of switching angles θ 1 — c and θ 2 — c and switching network 202 operates at the frequency of the output voltage v ac — out with a different set of switching angles θ 1 — i and θ 2 — i . as reflected in table i , taken in conjunction with fig2 and 3 , switching devices csp 1 / isp 1 and csn 1 / isn 1 within each network 201 and 202 , together with diodes d 1 and d 2 , connect the conductors carrying the input voltage v ac — in and the output voltage v ac — out to node v3 during the following portions of each ( respective ) cycle : from the start of the cycle to the point corresponding to switching angle θ 1 — c / θ 1 — i ; between the points corresponding to π − θ 1 — c / θ 1 — i and π + θ 1 — c / θ 1 — i ; and from the point corresponding to 2π − θ 1 — c / θ 1 — i to the end of the respective cycle . switching devices csp 1 / isp 1 , csp 2 / isp 2 and csp 3 / isp 3 within each network 201 and 202 connect the conductors carrying the input voltage v ac — in and the output voltage v ac — out to node v4 during the portions of each respective cycle from θ 1 — c / θ 1 — i to θ 2 — c / θ 2 — i and π − θ 2 — c / θ 2 — i to π − θ 1 — c / θ 1 — i . switching devices csp 1 / isp 1 , csp 2 / isp 2 and csp 4 / isp 4 within each network 201 and 202 connect the conductors carrying the input voltage v ac — in and the output voltage v ac — out to node v4 during the portion of each cycle from θ 2 — c / θ 2 — i to π − θ 2 — c / θ 2 — i . switching devices csn 1 / isn 1 , csn 2 / isn 2 and csn 3 / isn 3 within each network 201 and 202 connect the conductors carrying the input voltage v ac — in and the output voltage v ac — out to node v2 during the portions of each cycle from π + θ 1 — c / θ 1 — i to π + θ 2 — c / θ 2 — i and 2π − θ 2 — c / θ 2 — i to 2π − θ 1 — c / θ 1 — i . switching devices csn 1 / isn 1 , csn 2 / isn 2 and csn 4 / isn 4 within each network 201 and 202 connect the conductors carrying the input voltage v ac — in and the output voltage v ac — out to node v1 during the portion of each cycle from π + θ 2 — c / θ 2 — i to 2π − θ 2 — c / θ 2 — i . the number of voltage levels employed , together with the number of switching angles employed , may be greater than the five voltage levels v1 - v5 ( e . g ., seven , nine , etc .) total and two switching angles ( e . g ., three , four , etc .) per switching network illustrated in the exemplary embodiment , and / or the voltage levels selected need not be uniformly spaced ( i . e ., varying in integer unit increments ) as shown . circuit 200 has a low part count since discrete clamping diodes are not required for each voltage level and / or multiple , series - connected , discrete diodes of a given rating as needed to handle the appropriate voltage . in addition , the output voltage v ac — out exhibits relatively low harmonics , such that expensive and complex sine wave filters are not required . in addition , the system of the present invention may be scaled to medium voltage ( 1 , 500 to 15 , 000 volts ) power transmission without the requirement for a step - up transformer . control of circuit 200 may optionally be optimized for load balancing and minimization of harmonics by appropriate selection of switching angles θ 1 — c / θ 1 — i and θ 2 — c / θ 2 — i . for the purposes of such optimization , a modulation index mi may be defined as a ratio of the maximum desired output voltage magnitude ( set based on the target operating speed ) for a switching network 201 or 202 to the maximum output voltage obtainable from that switching network — that is , the desired magnitude of voltage level v1 / v5 to the maximum obtainable voltage level v1 / v5 for switching network or converter 201 , and the desired magnitude of the output voltage v ac — out to the maximum obtainable output voltage for switching network or inverter 202 . the converter ( switching network 201 ) within circuit 200 should provide approximately the same output voltage magnitude as the power source , and therefore the modulation index of the converter ( mi_c ) will generally fall within a narrow range — for instance , from 0 . 8 to 1 . 0 , depending on the power source voltage — but need not necessarily be so limited . however , the inverter ( switching network 202 ) within circuit 200 needs to provide variable voltage , with a modulation index mi_i varying from 0 . 1 to 1 . 0 depending on the desired motor speed . both the converter and the inverter have two switching angles : θ 1 — c and θ 2 — c for the converter and θ 1 — i and θ 2 — i for the inverter . the switching angles to balance voltages and minimize harmonic content of the input and output voltages may be initially calculated and optimized by intensive off - line calculation and simulation . further simulation of operation under load conditions may then be performed to balance the voltage by controlling the power factor on input for correction , to obtain the optimal switching angles for one voltage - balanced operation point . by repeating this procedure , optimal switching angles for all needed operation points ( different modulation index values ) may be obtained . for the system depicted in fig1 - 3 and described above , with a modulation index of the converter mi_c = 0 . 9 , the optimal initial switching angles ( in degrees ) for various selected values of the modulation index of the inverter ( mi_i ) are given below in table ii : table ii mi_i θ 1 c θ 2 c θ 1 i θ 2 i 1 . 0000 0 . 4510 0 . 4510 0 . 0000 0 . 0000 0 . 9750 0 . 3948 0 . 5014 0 . 0000 0 . 3176 0 . 9500 0 . 3259 0 . 5498 0 . 0000 0 . 4510 0 . 9250 0 . 2330 0 . 5970 0 . 0000 0 . 5548 0 . 9000 0 . 1550 0 . 6233 0 . 1550 0 . 6233 0 . 8750 0 . 1053 0 . 6342 0 . 2582 0 . 6711 0 . 8500 0 . 0899 0 . 6367 0 . 3463 0 . 7085 0 . 8250 0 . 1035 0 . 6345 0 . 4232 0 . 7403 0 . 8000 0 . 1201 0 . 6314 0 . 4897 0 . 7706 0 . 7750 0 . 1295 0 . 6294 0 . 5474 0 . 8009 0 . 7500 0 . 1320 0 . 6289 0 . 5987 0 . 8313 0 . 7250 0 . 1308 0 . 6291 0 . 6457 0 . 8615 0 . 7000 0 . 1285 0 . 6296 0 . 6898 0 . 8910 0 . 6750 0 . 1273 0 . 6299 0 . 7319 0 . 9197 0 . 6500 0 . 1281 0 . 6297 0 . 7723 0 . 9475 0 . 6250 0 . 1309 0 . 6291 0 . 8114 0 . 9746 0 . 6000 0 . 1350 0 . 6282 0 . 8492 1 . 0011 0 . 5750 0 . 1395 0 . 6271 0 . 8858 1 . 0271 0 . 5500 0 . 1439 0 . 6261 0 . 9213 1 . 0527 0 . 5250 0 . 1474 0 . 6252 0 . 9557 1 . 0781 0 . 5000 0 . 1499 0 . 6246 0 . 9892 1 . 1033 0 . 4750 0 . 1513 0 . 6242 1 . 0219 1 . 1282 0 . 4500 0 . 1518 0 . 6241 1 . 0538 1 . 1530 0 . 4250 0 . 1515 0 . 6241 1 . 0851 1 . 1775 0 . 4000 0 . 1509 0 . 6243 1 . 1159 1 . 2019 0 . 3750 0 . 1503 0 . 6245 1 . 1462 1 . 2260 0 . 3500 0 . 1498 0 . 6246 1 . 1761 1 . 2499 0 . 3250 0 . 1495 0 . 6247 1 . 2057 1 . 2735 0 . 3000 0 . 1497 0 . 6246 1 . 2349 1 . 2970 0 . 2750 0 . 1501 0 . 6245 1 . 2639 1 . 3203 0 . 2500 0 . 1509 0 . 6243 1 . 2926 1 . 3435 0 . 2250 0 . 1517 0 . 6241 1 . 3211 1 . 3665 0 . 2000 0 . 1526 0 . 6239 1 . 3493 1 . 3894 0 . 1750 0 . 1533 0 . 6237 1 . 3774 1 . 4123 0 . 1500 0 . 1540 0 . 6235 1 . 4053 1 . 4351 0 . 1250 0 . 1544 0 . 6234 1 . 4331 1 . 4578 0 . 1000 0 . 1547 0 . 6233 1 . 4608 1 . 4805 0 . 0750 0 . 1549 0 . 6233 1 . 4884 1 . 5031 0 . 0500 0 . 1549 0 . 6233 1 . 5159 1 . 5257 0 . 0250 0 . 1550 0 . 6233 1 . 5433 1 . 5482 0 . 0000 0 . 1549 0 . 6233 1 . 5708 1 . 5708 optimal initial switching angles under the same conditions are also plotted in fig4 . [ 0040 ] fig5 is a diagram of a control system for converter / inverter switching networks according to one embodiment of the present invention . based on source reactive current calculations , a phase a between the power source voltage v ac — in and the voltage received by converter 201 ( i . e ., the phase difference across inductor 203 in the example shown ) is determined and employed by direct current ( dc ) voltage regulation portion of controller 500 to regulate the dc voltage across the capacitors c 1 - c 4 . modulation index mi_c and modulation index mi_i are employed , by the switching pattern table and control logic within controller 500 , to compute ( or select from a table such as that in table ii ) switching angles for converter 201 and inverter 202 , with corrections . modulation index mi_c is employed by controller 500 to control the power factor on the power source , while modulation index mi_i is employed to control the output voltage . it is important to note that while the present invention has been described in the context of a fully functional system , those skilled in the art will appreciate that at least portions of the mechanism of the present invention are capable of being distributed in the form of a machine usable medium containing instructions in a variety of forms , and that the present invention applies equally regardless of the particular type of signal bearing medium utilized to actually carry out the distribution . examples of machine usable mediums include : nonvolatile , hard - coded type mediums such as read only memories ( roms ) or erasable , electrically programmable read only memories ( eeproms ), recordable type mediums such as floppy disks , hard disk drives and compact disc read only memories ( cd - roms ) or digital versatile discs ( dvds ), and transmission type mediums such as digital and analog communication links . although the present invention has been described in detail , those skilled in the art will understand that various changes , substitutions , variations , enhancements , nuances , gradations , lesser forms , alterations , revisions , improvements and knock - offs of the invention disclosed herein may be made without departing from the spirit and scope of the invention in its broadest form .