so that this invention may be better understood , embodiments thereof will now be described and reference will be made to the accompanying drawings . the description that follows is given by way of example only . the adc apparatus to be described below makes use of the essential differences between a true analogue to digital converter and the type of adc apparatus which is acceptable in a radio application . the first of these differences is that , provided the departures from the ideal transfer characteristic are not great the main consideration is the signal - to - noise ratio rather than the existence of all states . existing high accuracy adcs in the baseband radio systems mentioned above and in digital telephone systems exploit this feature . the second , and possibly more important factor is that one key piece of information about the incoming wanted signal is known i . e . the frequency . it is possible to assume in modern receiver systems that a clock signal can be generated at the incoming frequency or a multiple of it with arbitrary accuracy . it is then possible to devise a radio receiver system based on the arrangement shown in fig1 . this shows an essentially conventional adc 1 , of the ` flash ` type ( which needs no sample hold ), sampling at the input carrier frequency under control of a clock 3 , followed by a memory and averaging circuit 5 , a digital filter 7 , a digital detector 9 and an output circuit 11 , which could take the form of a d - a converter and audio output stage , or could be in the form of further processing circuitry for digital signals . as shown , the analogue - to - digital converter 1 directly follows the ` rf ` or ` if ` stage 13 of a radio receiver , from which it receives modulated analogue signal . a more detailed schematic of the adc / memory organization is shown in fig2 . the memory and averaging circuit 5 shown comprises a store 14 having 2 m memory locations 15 each of which is of n - bit word length and is loaded sequentially by demultiplexing 17 the output from the adc 1 . once loaded , each memory location 15 is read by microprocessor or other averaging circuitry 19 and an n + m bit word length signal generated at the circuitry output . the adc 1 could be essentially a conventional parallel &# 34 ; flash &# 34 ; type , of eight or more bits ` n `. it would preferably have a wide analogue input bandwith to accommodate signals up to or above the top of the hf band ( 30 mhz ). with some compromise in performance , fewer than eight bits could be used ; this may be more attractive at v . h . f . the clock 3 in this simplest system is synchronous with the nominal input carrier frequency . hence , successive samples s 1 ; s 2 ; . . . , occur at equal time intervals on the carrier waveform ( see fig3 ). if therefore a number of successive samples s 1 ; s 2 ; . . . , are stored and subsequently averaged , then the average value s will represent further bits of resolution in the equivalent adc . for example , if &# 34 ; 2 m &# 34 ; samples s 1 ; s 2 ; . . . ; s 2 m , are averaged , then &# 34 ; m &# 34 ; further bits of resolution will be obtained . the averaging would most advantageously be a &# 34 ; rolling &# 34 ; arrangement , with the oldest samples s 1 , etc ., being discarded in favour of new values s 2 m + 1 , etc . in the simplest case , a level weighting would be imposed , but for increased output bandwith it would be possible to weight the average s to the newest samples ( s = σ i ω i s i ). the total of &# 34 ; n + m &# 34 ; bits are then passed to a digital filter , which can be of many different forms : generic classes are &# 34 ; finite impulse response &# 34 ; ( fir ) and &# 34 ; infinite impulse response &# 34 ; ( iir ). the filtering provides , in addition to the inherent filtering to be described below , the selectivity of the receiver . the composite adc apparatus fig1 can be used to receive all classes of modulation by providing a suitable digital detector . single sideband and amplitude modulation will be demodulated by the action of the adc sampling . if necessary a phase control ( not shown ) may be included to prevent sampling at zero - crossing points . frequency modulation , or fsk can be demodulated using a phase and quadrature receiver of appropriate chacteristics , for example the receiver described in our united kingdom patent application g . b . no . 8602227 , brief details of which will follow below ( fig7 ). this leads to a modification of the scheme which may be generally advantageous . a phase shift at the carrier frequency is needed for the fm demodulator cited and for certain others . this is achieved in the adc apparatus described here fig1 by providing two clock pulses to the adc 1 , with a 90 degree ( i . e . quadrature ) relative phase shift . data is then sorted in two separate ( phase and quadrature , or i and q ) memories 14 . the derived n + m bits can then be processed through the filter by time interleaving , or could be passed through two separate filters for maximum speed . again , for maximum speed of operation , two phased adcs 1 could be used , but this would slightly degrade the i and q channel matching . the phase and gradrature receiver circuit shown in fig7 comprises four digital multipliers 21 , 23 , 25 and 27 , a difference amplifier 31 and a running amplifier 33 . the multipliers are arranged in pairs 21 and 23 , 25 and 27 and are connected to receive the averaged sample outputs s q and s i of the conversion apparatus , respectively . one multiplier 21 , 27 in each pair receives an in - phase multiplicand , sin ω o t , whilst the other multiplier 23 , 25 in each pair receives a quadrature multiplicand , cos ω o t . the output of each multiplier 21 , 25 and 23 , 27 is referred to the difference amplifier 31 and to the summing amplifier 33 , respectively to generate in - phase i and quadrature q detected digital signals . returning to consider the adc system fig1 several limitations can be identified . these are not major problems , but delineate the likely limits to operation . the most obvious limit is that the sample rate and hence the incoming frequency must exceed 2 m ×( maximum modulation frequency × 2 ) to allow for two samples per cycle of the modulation from 2 m successive samples of the carrier . an example would be for the averaging of 1024 samples ( m = 10 ) with 2 khz modulation , leading to a minimum input of 4 mhz . with a 10 bit adc this would give 120 db dynamic range . unusually for an adc system there is also a minimum for the modulation frequency , below which the coarse initial quantisation will become more evident . this limit occurs when the slew rate of the input modulation is such that only a small fraction of the averaged samples in a quantisation level is distinguishable from the main group of samples . a closely related limit occurs when the input signal is so small that it always remains at a single quantisation level of the coarse adc 1 . however , these are only a problem if there is no other interfering signal present which can carry the input to an adjacent level , at least for part of the time . the interfering signals , which in practical systems will always be present , can be filtered out in the subsequent stages . the ultimate dynamic range is therefore limited by the combination of &# 34 ; n &# 34 ; and &# 34 ; m &# 34 ; achievable . it has been shown above that , at low frequencies , for a 10 bit adc , 2 10 memory locations are required . raising the signal / sample rate would ease the adc requirement , at the cost of more memory . clearly , current state of art systems can barely achieve the required dynamic range . while it is to be expected that developed systems will eventually achieve larger numbers of bits (&# 34 ; n &# 34 ;) resolution , one further modification to the described arrangement ( fig1 ) could remove the limitations due to finite word length in the adc 1 by applying more memory 14 and processing 19 . since memory and digital processing power continues to fall in cost this is an advantageous route . this modification is to provide multiple samples s ( φ 1 ); s ( φ 2 ); . . . s ( φ p ), per cycle of the carrier signal . these could be provided by a single adc 1 ( fig4 ) sampled at a higher frequency , or , by several phased adcs 1 ( fig6 ) if speed is a limitation . the data is then fed to a memory array , with separate stores 14 for respective sample phases φ 1 ; φ 2 ; . . . φ p . averaging is carried out as before , but based on &# 34 ; p &# 34 ; separate samples s ( φ 1 ) to s ( φ p ) per cycle . an example of &# 34 ; p &# 34 ; = 4 is shown in fig5 . filtering is again speed dependent . fast systems ( in relation to available processing speed ) will use parallel digital filters , while slower systems may use the same filter 7 on a time - multiplexed basis . data is then stored in a further memory ( not shown ) for sequential reconstruction . essentially , the memories are polled at a rate which is either a submultiple of the original sample rate or is a multiple ( at least twice ) of the maximum output frequency . the output , after d / a conversion , is the recovered modulation . again ssb , am , fm or fsk modes are possible . the two sample per cycle method for fm detection described above is clearly one case of the more general p - sample system just described . a particular advantage of the multiple sampling scheme is that the filter 7 at the output frequency consists of several identical sections . these can be strictly separate filters for each successive sample interval . to great advantage , however , a single filter section instead could be used on a time multiplexed basis . the several section version of the filter has an analogue in the class of filters known as &# 34 ; n - path &# 34 ;. the sequential version could be regarded as a special case of &# 34 ; n - path &# 34 ; filtering . accuracy limitations of the basic adc 1 form one limit of the cross and intermodulation characteristics of the system . the most obvious limit is the finite accuracy of the steps in the adc 1 transfer characteristic . however , since most of the steps are much more accurate than the worst case error , the dynamic range limitation due to this source of error is likely to be much better than the quantisation term of 6 db per bit . taking the 10 bit example above , the dynamic range for a practical system would substantially exceed ( n × 6 ) i . e . 60 db and would probably be over 100 db , although this figure is difficult to quantify without precise knowledge of the types of adc errors and a further study of their effects . prefiltering of the r . f . signal may be necessary in some applications where significant signals are present at harmonics of the wanted signal . a higher degree of oversampling would in principle help here , but the sample rate would then need to be synchronous with the input and at a frequency at least twice that of the highest possible received frequency . the input would still need anti - alias low - pass input filtering , so each case should be considered on its merits . prefiltering is commonly used in analogue systems and the requirement is only for a reduction in the harmonics of the received frequency ; adjacent channel filtering is carried out by the digital system . the apparatus described above may be assembled from standard components . thus , for example , it could be assembled using a plessey sp9758 8 - bit ecl - adc ; plessey ha21 random access memories ; and , averaging circuits constructed from small - scale integration ( ssi ) logic gates such as plessey ecl iii series devices . ( i ) the inventive apparatus herein disclosed , incorporated as part of a digital radio receiver , offers wideband input capability ; ( iii ) it is capable of integration onto a small number only of integrated circuits ; ( v ) it may be devised for am , ssb , isb or fm mode operation and is suited to software control ; ( vi ) associated filtering functions , as may be requisite , likewise can be readily implimented under software control ; and , ( vii ) the system offers the capability of wide dynamic range performance .