referring now to the drawing , the conventional motor vehicle horn relay circuit includes a horn relay 10 connected in series with a horn switch 12 through a slip ring 14 across a vehicle battery 16 . in accordance with the present invention , a shunt resistor 18 is connected between the horn relay 10 and the slip ring 14 . the resistor 18 is of small resistance value , such as for example 1 ohm , and does not interfere with the operation of the horn relay 10 . in addition to the horn switch 12 , a plurality of momentary contact switches 20 , 22 and 24 are mounted on the steering wheel . an integrated circuit voltage regulator 26 , such as the mc78m06ct , has its input terminal connected to a junction 28 of the horn relay circuit and maintains a substantially constant output voltage v o , at the output terminal , of for example 6 volts , relative to the voltage at the common terminal . the voltage regulator 26 is only energized upon closure of one of the switches 20 , 22 or 24 and , consequently , draws no standby current . the current drawn through the resistor 18 by the regulator 26 depends upon which one of the switches 20 , 22 and 24 is closed . when a switch is closed , the total current drawn is the sum of the regulator bias current i b plus the load current i l . the bias current i b is constant at , for example , 6 ma ., while the load current i l is the regulated voltage v o divided by the load resistance . the load resistance depends on which of the switches is closed . for example , if switch 20 is closed , the load resistance is the sum of the resistors 30 , 32 and 34 . if switch 22 is closed , the load resistance is the sum of the resistors 32 and 34 and if switch 24 is closed , the load resistance is the resistor 34 . thus , for each closure of one of the switches 20 , 22 and 24 , a distinct and predetermined current is drawn through the resistor 18 . the current through the resistor 18 is converted to a voltage and amplified by a differential amplifier 36 having its inverting input connected through a current limiting resistor 38 to a junction 40 of a voltage dividing network comprising resistors 42 and 44 connected between one side of the resistor 18 and ground . the noninverting input of the amplifier 36 is connected through a current limiting resistor 46 to the junction 48 of a voltage dividing network comprising resistors 50 and 52 connected between the other side of the resistor 18 and ground . the noninverting input of the amplifier 36 is connected to ground through a resistor 54 and the output is connected to the inverting input through a resistor 55 . the output of the differential amplifier 36 is an amplified version of the voltage appearing across the resistor 18 . the output of the differential amplifier 36 is connected with the inverting input of comparators 56 , 58 , 60 and 62 . the noninverting input of the comparator 62 is connected to the output of an ic voltage regulator 64 which provides a 6 volt output and is powered from the vehicle battery through a network including a protection diode 66 , a resistor 68 , filter capacitor 70 and zener diode 72 . the noninverting input of the comparator 56 is connected with the regulator 64 through a potentiometer 74 which establishes a first reference voltage level . similarly , the noninverting inputs of the comparators 58 and 60 are connected with the regulator 64 through potentiometers 76 and 78 which establish second and third reference voltage levels . the reference voltage levels established at the noninverting inputs of comparators 56 and 58 are respectively below and above the voltage expected at the inverting inputs when the switch 20 is closed . similarly , the voltage resulting from closure of switch 22 is between that established at the noninverting inputs of comparators 58 and 60 and when switch 24 is closed , the resulting voltage is between that established at comparators 60 and 62 . the output of each comparator 56 - 62 is input to debounce circuitry 80 , 82 , 84 and 86 which may be formed from a single integrated circuit , such as the mc14490fp , and a timing capacitor 88 . the debounce circuitry 80 - 88 ensures that the logic level outputs of the comparators 56 - 62 are present for a fixed time interval before the succeeding logic is activated . a nor gate 90 receives one input from the comparator 56 and a second input from the comparator 58 through an inverter 92 . the output of the gate 90 provides a control signal designated 20cs which indicates the status of switch 20 . a nor gate 94 receives one input from the comparator 58 and a second input from the comparator 60 through an inverter 96 . the output of the gate 94 provides a control signal designated 22cs which indicates the status of switch 22 . a nor gate 98 receives one input from the comparator 60 and a second input from the comparator 62 through an inverter 100 . the output of the gate 98 provides a control signal designated 24cs which indicates the status of switch 24 . the operation of the circuit shown in the drawing is as follows assuming a value of 100 ohms for each of the resistors 30 , 32 and 34 . with none of the switches 16 , 20 , 22 or 24 closed , current through the resistor 18 is zero and the voltage applied to the inverting inputs of the comparators 56 - 62 is zero . accordingly , the outputs of the comparators 56 - 62 are high which disables the gates 90 , 94 and 98 providing a low output from each of these gates . if the switch 20 is closed while the switches 22 and 24 remain open , a current of approximately 26 ma . is drawn through resistor 18 and will produce a voltage level at the output of the amplifier 36 which is between the voltage levels established by the resistors 74 and 76 . under these circumstances , the output of the comparator 58 remains high but the output of the comparator 56 switches low . this produces two low inputs to the gate 90 causing its output to go high indicating that the switch 20 is closed . if the switch 22 is closed while the switches 20 and 24 remain open , a current will be drawn through the resistor 18 of approximately 39 ma . producing a voltage level at the output of amplifier 36 which is between that established by the potentiometers 76 and 78 . as a result , the output of the comparator 58 goes low which disables the gate 90 through the inverter 92 , thus driving the output of the gate 90 low while at the same time providing a low input to the gate 94 . since the output of the comparator 60 is high , the inverter 96 causes the other input to the gate 94 to be low . with both inputs of the gate 94 low , its output is high indicating that the switch 22 is closed . if the switch 24 is closed , while the switches 20 and 22 remain open , a current of approximately 78 ma . is drawn through the resistor 18 producing a voltage level between that established by the potentiometer 78 and the voltage regulator 64 . as a result , the output of the comparator 60 switches low which disables the gate 94 through the inverter 96 ensuring that the output of the gate 94 remains low . since the output of the comparator 62 is high , the inverter 100 provides one low input to the gate 98 . comparator 60 provides a second low input to the gate 98 causing its output to go high indicating that the switch 24 is closed . if the horn switch 16 is closed while the switches 20 , 22 and 24 are open , at least 500 ma is drawn through the resistor 18 , producing a voltage at the inverting inputs of the comparators 56 - 62 which is higher than that produced at the noninverting input of each of the comparators 56 - 62 . with the output of each of the comparators 56 - 62 being driven low as a result of closure of the horn switch 16 , the gate 98 is disabled by the comparator 62 low output , the gate 94 is disabled by the low output from the comparator 60 , and the gate 90 is disabled by the low output from the comparator 58 . in the arrangement shown , the switch 24 has the highest priority , switch 22 has next highest priority and switch 20 has the lowest priority . that is to say , the voltage set by the potentiometer 78 establishes a voltage window between it and the output of the regulator 64 which is wider than any voltage variations resulting from closure of either of the switches 20 or 22 in combination with the switch 24 . likewise , the voltage set by the potentiometer 76 forms a voltage window with that established by the potentiometer 78 such that the voltage generated by closure of the switch 20 , while the switch 22 is closed , remains within the window . the voltage set by the potentiometer 74 is less than that voltage established at the output of the amplifier 36 when the switch 20 is closed . it will be appreciated that even though all the resistors 30 , 32 and 34 are identical , there is a sufficient current variations through the resistor 18 as a result of selective closure of any of the three switches 20 - 24 to permit switch closures to be readily decoded . moreover , the encoding scheme of the present invention permits easily allocation of priority to switches without different values of resistance for the resistors 30 , 32 and 34 . furthermore , it will be noted that a malfunction in the multiplex circuitry which is added to the horn circuit ( other than the resistor 18 ), has no effect on the horn circuit so that its reliability is not degraded . on the other hand , if the horn relay 10 should open circuit rendering the horn circuit inoperative , this would be detected during operation of any of the switches 20 , 22 or 24 and thus would provide an advance warning of the horn relay circuit &# 39 ; s inoperability .