fig1 shows an auto - terminating circuit 100 according to an embodiment of the present invention . the circuit 100 has first and second input terminals 101 , 102 coupled to corresponding first and second output terminals 111 , 112 of the circuit 100 . in use the input terminals 101 , 102 are typically coupled to first and second terminals ps 1 , ps 2 of a power source or power supply ps . it is to be understood that the first and second input terminals 101 , 102 may be coupled to the power source ps via one or more other circuits 100 . other arrangements are also useful . the first and second terminals ps 1 , ps 2 of the power source ps are arranged to provide a dc power signal to the circuit 100 . it is to be understood that communications data may be superimposed on the dc power signal by devices at nodes of the network as discussed in more detail below . it is to be understood that the network devices may each be provided with an auto - terminating circuit 100 according to the present invention . the circuit 100 has four portions : a terminating portion c 1 , an output monitoring portion c 2 , an output control portion c 3 and a termination control portion c 4 . the terminating portion c 1 comprises a terminating resistor rt in series with a terminating capacitor ct . a first switch sw 1 is provided between the terminating resistor rt and the first input terminal 101 . a second switch sw 2 is provided between the terminating capacitor ct and the second input terminal 102 . thus it is to be understood that the terminating portion c 1 may be isolated from the first and second input terminals 101 , 102 by opening either one or both of the switches sw 1 , sw 2 . the circuit 100 may be said to be in a continuing condition in this state since the terminating portion c 1 is not connected between the first and second input terminals 101 , 102 . the terminating portion c 1 may be coupled between the first and second input terminals 101 , 102 thereby to terminate the circuit 100 by closing both switches sw 1 , sw 2 . the circuit may be said to be in a terminating condition in this state . in the embodiment shown the circuit 100 is arranged to control both the first and second switches sw 1 , sw 2 together by means of a termination control portion c 4 such that either both of the switches sw 1 , sw 2 are closed or both of the switches sw 1 , sw 2 are open as discussed below , although other arrangements are also useful . an input terminal c 4 in of the termination control portion c 4 is coupled to an output c 2 out of the output monitoring portion c 2 . if the logical state of the output c 2 out is low the termination control portion c 4 is arranged to control the terminating portion c 1 to close the first and second switches sw 1 , sw 2 so that the circuit 100 assumes the terminating condition . conversely , if the logical state of the output c 2 out is high the termination control portion c 4 is arranged to control the terminating portion c 1 to open the first and second switches sw 1 , sw 2 so that the circuit 100 assumes the continuing condition . in the embodiment of fig1 the switches sw 1 , sw 2 are each provided by a transistor device although other forms of solid state switching device could be used . the output control portion c 3 is provided between the second input terminal 102 and the second output terminal 112 . the output control portion c 3 is arranged to limit a maximum current that may flow through the output control portion c 3 from the second output terminal 112 to the second input terminal 102 to either a first value or a second value , the first value being less than the second value , in dependence on a state of an input terminal c 3 in of the output control portion c 3 . the input terminal c 3 in is coupled to the output terminal c 2 out of the output monitoring portion c 2 , together with the input terminal c 4 in of the termination control portion c 4 . if the state of the input terminal c 3 in is set to logical zero , the output control portion c 3 is arranged to set the maximum current that may flow therethrough to the first ( lower ) value , the circuit being in the terminating condition . if the state of the input terminal c 3 in is set to logical one , the output control portion c 3 is arranged to set the maximum current that may flow therethrough to the second ( higher ) value , the circuit being in the continuing condition . the output monitoring portion c 2 has an input terminal c 2 in coupled to the second output terminal 112 whereby the output monitoring portion c 2 may sense a potential vx of the second output terminal 112 . the output monitoring portion c 2 has first and second comparators a 1 , a 2 respectively . a negative input of the first comparator and a positive input of the second comparator are both coupled to the second output terminal 112 . the positive input of the first comparator a 1 is held at a first reference potential vref 1 and the negative input of the second comparator a 2 is held at a second reference potential vref 2 where vref 2 is less than vref 1 . the values of vref 1 and vref 2 are discussed in further detail below . respective outputs of the first and second comparators a 1 , a 2 are coupled to respective inputs of an and gate a 3 the output of which provides the output c 2 out of the output monitoring portion c 2 . it is to be understood that the output monitoring portion c 2 is configured to set the logical state of its output terminal c 2 out according to the value of vx as follows . if vx has a value that is above vref 1 or below vref 2 the output monitoring portion c 2 is arranged to set the state of the output terminal c 2 out to logical zero . this causes the output control portion c 3 to set the maximum allowable current therethrough to the first ( lower ) value and the termination control portion c 4 to control the terminating portion c 1 to assume the terminating condition . however if vx has a value between vref 1 and vref 2 the output monitoring portion c 2 is arranged to set the state of the output terminal c 2 out to logical one . this causes the output control portion c 3 to set the maximum allowable current therethrough to the second ( higher ) value and the termination control portion c 4 to disconnect the terminating portion c 1 from the input lines 101 , 102 whereby the circuit 100 assumes the continuing condition . it is to be understood that the second value of maximum allowable current is selected to be a value sufficient to allow the maximum amount of current that may be required in use to flow through the circuit 100 . it is to be understood that the value of vx is responsive to a value of impendance of a load connected between the output terminals 111 , 112 and may be used to determine whether this load has an acceptable impedance . by acceptable impedance is meant an impedance that will allow the network of which the circuit 100 may be part to perform correctly . if the output terminals 111 , 112 are connected across a load having an acceptable impedance the value of vx will have a value within a prescribed range . the values of vref 1 and vref 2 are selected such that vref 1 is greater than the maximum allowed value of vx when an allowed load is connected and vref 2 is less than the minimum allowed value of vx when an allowed load is connected . thus , if an allowed load is connected between the output terminals 111 , 112 the output monitoring portion c 2 controls the output control portion c 3 to set the maximum current that may flow therethrough to the second value . it is to be understood that if no load is connected between the first and second output terminals 111 , 112 ( i . e . open circuit conditions exist ), the second output terminal 112 is arranged to have a potential substantially equal to that of the second input terminal 102 . this is because substantially no current can flow into or out from the second output terminal 112 through c 3 and therefore the potential across c 3 will be substantially zero . if vref 2 is set to a potential greater than the second input terminal 102 then the output terminal c 2 out of the output monitoring portion c 2 will be set to logical zero when open circuit conditions exist between the output terminals 111 , 112 . this in turn causes the output control portion c 3 to set the maximum current that may flow therethrough to the first value which is less than the second value and the termination control portion c 4 to couple the terminating portion c 1 between the first and second input terminals 101 , 102 . if the output terminals 111 , 112 are directly connected to one another by means of a short circuit ( due for example to a fault in a circuit to which the terminals 111 , 112 are connected ), vx will have substantially the same potential as the first output terminal 111 which is in turn substantially the same as that of the first input terminal 101 . vref 1 is therefore set to a value that is less than the potential at the first input terminal 101 such that , if the first output terminal 111 is directly connected to the second output terminal 112 , vx is greater than vref 1 and the output monitoring portion c 2 controls the termination control portion c 4 to couple the terminating portion c 1 between the first and second input terminals 101 , 102 by closing the first and second switches sw 1 , sw 2 . the output control portion c 3 is set to limit the maximum current that may flow therethrough to the first value . the termination control portion c 4 has a control resistor rc coupled to the first input terminal 101 and third and fourth switch elements sw 3 , sw 4 of the circuit 100 coupled in series between the control resistor rc and the second input terminal 102 . the third and fourth switches sw 3 , sw 4 are both coupled to the input terminal c 4 in of the termination control portion c 4 such that when the input terminal c 4 in is set to logical one both switches sw 3 , sw 4 are closed and when the input terminal c 4 in is set to logical zero both switches sw 3 , sw 4 are open . in the embodiment shown the third and fourth switches sw 3 , sw 4 are both provided by transistor devices . it is to be understood that when the third and fourth switches sw 3 , sw 4 are closed rc is connected between the first and second input terminals 101 , 102 . the potential applied to the first and second switches sw 1 , sw 2 is therefore the same as that of the second input terminal ( logical zero ) and the first and second switches remain in the open condition such that the circuit 100 functions as a continuing circuit with the terminating portion c 1 disconnected from the first and second input terminals 101 , 102 . when the third and fourth switches sw 3 , sw 4 are open , rc is disconnected from the second input terminal 102 . the potential applied to the first and second switches sw 1 , sw 2 is therefore the same as that of the first input terminal ( logical one ) and the first and second switches assume the closed condition such that the circuit 100 functions as a terminating circuit with the terminating portion c 1 connected between the first and second input terminals 101 , 102 the arrangement described in respect of termination control portion c 4 has the feature that when the circuit is in the continuing mode with the third and fourth switches closed , a shunt path exists for spikes in the potential applied between the first and second input lines , for example due to radio frequency ( rf ) interference . voltage spikes can cause unwanted termination of known auto - terminating circuits by triggering connection of a terminating circuit between the input terminals 101 , 102 . in the circuit 100 of fig1 the termination control portion c 4 allows such voltage spikes to be shunted between the first and second input lines 101 , 102 without triggering closure of the first and second switches . this increases a stability of the network in which the circuit 100 is connected . fig2 shows a plot of vx as a function of time for different connection states of the output terminals 111 , 112 . trace a shows vx as a function of time following short circuiting of output terminals 111 , 112 at time t = 0 . the potential at vx rises sharply to a peak value vpk upon connecting the output terminals 111 , 112 together before decreasing to a steady state value vps corresponding to the potential vps of the power supply ps . it can be seen that vref 1 is set to a value that is less than vps so that the circuit remains in a terminating condition throughout the period for which the output terminals 111 , 112 are short circuited . trace b shows vx as a function of time following connection of an external load having an impedance within an allowed range . the potential vx again rises sharply to a peak value vpk upon connecting the external load before falling to an expected or normal value vnorm for such a load . it can be seen that the value of vx falls below vref 1 after a time t has elapsed following connection of the external load . furthermore it can be seen that vref 2 is set to a value such that it remains below vnorm throughout . it is to be understood that the circuit 100 assumes a terminating condition for the period for which vx exceeds vref 1 . however as soon as vx falls below vref 1 the circuit assumes the continuing condition . fig3 is a timing diagram showing the states of outputs a 1 out , a 2 out of the first and second comparators a 1 , a 2 respectively , the state of output clout of the output monitoring portion c 2 and the value of maximum current allowable to pass through the output control portion c 3 as a function of the value of vx . it can be seen that when vx is greater than vref 1 ( for the period from time t = t 1 to t = t 2 ) a 1 out is set to logical zero , a 2 out is set to logical one , a 3 is set to logical zero and the output control portion c 3 is set to allow maximum current flow therethrough of a first value 11 . when vx falls below vref 1 ( after time t = t 2 ) a 1 out transitions to logical 1 , a 2 out remains at logical one and therefore a 3 out transitions to logical one . the value of maximum current permitted through the output control portion c 3 rises to a second value i 2 greater than the first value i 1 . fig4 is a trace of the amplitude of a communications signal of a typical fieldbus network as a function of time . the communications signal is a binary digital signal superimposed on a dc ‘ offset ’ signal provided by the power supply ps . it is to be understood that other arrangements are also useful fig5 is a schematic diagram illustrating the circuit 100 having input terminals 101 , 102 coupled to a power supply ps and output terminals 111 , 112 coupled to a further circuit 100 ′ identical to the first circuit 100 . the further circuit 100 ′ presents an impedance zn between the output terminals 111 , 112 . it is to be understood that the coupling of the circuits 100 , 100 ′ provides a voltage divider arrangement such that a potential at position vx is determined by the ratio of zf to zn . fig6 is a schematic illustration of a network 10 comprising a power supply ps coupled to a chain of circuits 100 , 100 ′ according to the present invention . it is to be understood that if a short circuit occurs in a cable between any two circuits 100 , 100 ′ such that output lines 111 , 112 of one circuit 100 become directly connected to one another and input lines 101 ′, 102 ′ of the other circuit 100 ′ become directly connected , the one circuit 100 assumes automatically a terminating condition in which its terminating portion c 1 is connected between respective input lines 101 , 102 of the circuit 100 and the output control portion c 3 limits the amount of current permitted to flow therethrough to the first value . this allows any network devices between that circuit 100 and the power supply to continue functioning despite the existence of a short circuit between two circuits 100 , 100 ′ of the network . throughout the description and claims of this specification , the words “ comprise ” and “ contain ” and variations of the words , for example “ comprising ” and “ comprises ”, means “ including but not limited to ”, and is not intended to ( and does not ) exclude other moieties , additives , components , integers or steps . throughout the description and claims of this specification , the singular encompasses the plural unless the context otherwise requires . in particular , where the indefinite article is used , the specification is to be understood as contemplating plurality as well as singularity , unless the context requires otherwise . features , integers , characteristics , compounds , chemical moieties or groups described in conjunction with a particular aspect , embodiment or example of the invention are to be understood to be applicable to any other aspect , embodiment or example described herein unless incompatible therewith .