fig1 shows a high level block diagram of the inventive telecommunications interface . the interface may be located inside a telecommunications network or at a termination of the network . the basic objective of the interface is to provide transmission rate conversion , combination of input signals , and / or protocol conversion between dissimilar devices . illustratively , data is received at input section 10 of the interface from one or more sources in digitized packet format . the data packets are routed through the dual port memory 150 to one or more of a plurality of output processors 500 - 1 . . . 500 - n . each of the output processors is connected to a receiving device such as a fax machine or video monitor , not shown . the input section 10 performs functions such as framing , clock recovery , sync separation ( for video and similarly formatted signals ) and serial to parallel conversion for the inputting of data into the memory 150 . input data packets emerge from the input section 10 stripped of timing and source identification information . only user information to be transmitted through the interface is inputted into the dual port memory 150 . the input address generator 160 can randomly access all locations in the memory 150 and has a &# 34 ; write &# 34 ; lock out capability for all locations in current use . the fifo &# 39 ; s 400 - 1 , 400 - 2 . . . 400 - n store the addresses generated by the address generator 160 in an organized fashion . thus , when a user data packet enters input section 10 , the address generator 160 generates the address of a location in memory 150 where the packet is to be stored . this address is routed through demultiplexer circuitry 300 to a particular fifo 400 - 1 . . . 400 - n depending on the origin and type of the associated data packet , e . g . addresses of packets from different sources are routed to different fifo memories . data is read from the memory 150 by using the addresses stored in the fifos . a particular one of the output processors 500 - 1 . . . 500 - n can access selected data from the dual port memory 150 , by fetching the addresses of this data from the appropriate fifo ( s ) via master control 600 . the fetched addresses access the memory 150 via the output address latch 170 . after the data stored at a given address is read out of the memory 150 , the address is routed back to the address generator 160 via line 173 so that this storage location may be used again . the data output of the memory 150 goes to an output buffer 540 which can be programmed to output the data to the appropriate output processor in serial or parallel format and at a rate selected by the master control 600 . an output processor which receives data from the dual port memory 150 reformats this data so that the data can be received by the associated receiving device . thus , in an ongoing transmission between one source and one output processor and its associated receiver device , user data from the source is steadily written into the dual port memory 150 , and storage addresses for this data are steadily written into a particular one of the fifo &# 39 ; s 400 - 1 . . . 400 - n . addresses previously written into the particular fifo are fetched from the fifo and used to access data from the source previously stored in the dual port memory 150 . the fetched addresses are then routed back to the address generator so that these addresses can be used again . the data accessed from the dual port memory is then routed to the desired output processor for reformatting and further transmission to the receiving device . viewed another way , communication between particular sources and particular output processors 500 - 1 . . . 500 - n and their associated receiving devices involves two mappings which are illustratively established under the control of the master control processor 600 . a first mapping is established between data sources and the fifo &# 39 ; s 400 - 1 . . . 400 - n so that the dual port memory addresses of data from particular sources are routed to particular fifo &# 39 ; s . this mapping is established by configuring the demultiplexing circuitry 300 . a second mapping is established between the fifo &# 39 ; s 400 - 1 . . . 400 - n and the output processors 500 - 1 . . . 500 - n so that data stored at addresses fetched from particular fifo &# 39 ; s may be routed to particular output processors and their associated receiving devices . this second mapping is established by configuring the master control processor 600 itself . illustratively , the two mappings are established by configuring the interface before it is used , for example prior to the start of a video conference . the above described form of memory management maximizes the utilization of memory space , minimize contention problems , and increases the transport efficiency of data through the interface . data need not be stored in memory 150 in any particular order , as the fifo &# 39 ; s keep track of where similar and dissimilar data is stored , and the input address generator keeps a record of how much address space is available for new data and the address locations that are available for that data . a more detailed discussion of the operation of the transmission interface is presented below in connection with fig2 which is a more detailed diagram of the inventive transmission interface . the master control 600 might be implemented using a number of standard processors depending on speed and / or control complexity requirements . such processors include for example the signetics 8 × 305 or 8 × 401 , the intel 8051 , or the motorola 68 , 000 family of microprocessors all of which have sufficient intelligence to control the interface . the bidirectional buses 610 , 611 plus control lines 631 , 632 , 651 . . . 659 , 660 - 1 . . . 660 - n are used by the master control 600 to interact with other parts of the interface . the input section 10 of the telecommunications interface is shown schematically in fig2 a . data is input to the telecommunications interface on line 101 , of clock recovery and framing circuit 100 , in the form of digital packets . the first bits of the incoming packet are used to reestablish a clock frequency corresponding to that of the incoming packet , and are then fed to the input clock 190 on line 102 . the input clock 190 maintains this clock frequency for the duration of the incoming packet . the output of the clock recovery and framing circuit 100 is stripped of any timing information . the output of the clock recovery circuit 100 on line 103 is input to one of two high speed shift registers 110 and 120 . a particular shift register is selected by a t - type flip - flop circuit 130 which is initially reset to a known position by line 656 of the master control 600 . register counter 180 counts the clock pulses and issues a pulse when either shift register 110 or 120 is full . this pulse toggles the flip - flop 130 via line 181 selecting the alternative shift register . the pulse is also sent via an &# 34 ; or &# 34 ; circuit 200 to the input address generator 160 and the dual port ram 150 . at this time , the data is transferred from the full shift register to the dual port ram via n - bit bus system 105 . the register counter 180 is reset via line 181 and &# 34 ; or &# 34 ; circuit 195 and the alternate shift register 110 or 120 begins to fill in exactly the manner described above . if the incoming signal is video , the output of the clock recovery circuit 100 on line 103 is also connected to a standard sync separator chip 15 . the sync separator chip 15 produces a composite blanking signal on line 16 which inhibits the clock output at gate 17 during the horizontal and vertical blanking intervals of the video signal . this process causes only the active portion of the input video signal to be inputted to the shift registers 110 , 120 and hence to the dual port ram 150 . the input address generator 160 determines the storage location for incoming data packets in dual port ram 150 . input address generator 160 is initialized by the master control 600 over an m - bit wide bus 610 and control line 653 . it changes the address to the dual port ram 150 in response to signals on line 161 from register counter 180 via line 181 and &# 34 ; or &# 34 ; gate 200 . alternatively , the address generator 160 may be controlled by the master control processor 600 via the bus 611 and the control line 654 which enables the master control processor 600 to communicate with the &# 34 ; or &# 34 ; gate 200 . the input address generator 160 writes a copy of each dual port ram address to one of several first - in - first - out ( fifo ) memories 400 - 1 . . . 400 - n via line 162 and bus 163 of width l . the specific fifo may be determined by the leading m bits , 111 and 121 , in the shift register 110 or 120 currently being transferred to the dual port ram 150 . the m bits 111 and 121 are input to an &# 34 ; or &# 34 ; switch 220 via an m bit bus 122 . the &# 34 ; or &# 34 ; switch 220 is actually an &# 34 ; or &# 34 ;- ed m - bit bus . the &# 34 ; or &# 34 ; switch 220 could be , for example , a 74ls 442 , a standard ttl integrated circuit . the leading m - bits , 111 or 121 are written into a latch 230 under control of &# 34 ; or &# 34 ; circuit 200 which latch 230 is then decoded by the fifo select 300 . alternatively , the fifo to which a given address is routed , may be determined by the master control processor 600 via bus 610 , which is connected to &# 34 ; or &# 34 ; circuit 220 . control of the &# 34 ; or &# 34 ; switch 220 is via line 652 coming from the address demultiplexer 650 , and , in turn the master control 600 . this completes the description of data flow between the serial data input line 101 and the dual port ram 150 . at this point , user data is stored in the ram 150 and address data is stored in the fifos , 400 - 1 . . . 400 - n . the address data stored in the fifos enables particular output processors , 500 - 1 . . . 500 - n to fetch and process particular data from the dual port ram 150 . another path to the input of the dual port ram 150 is through a feedback register 140 . latch 570 is written to by the master control 600 via line 655 and the m - bit bus 610 . latch 570 controls the enable pins of shift registers 110 and 120 via line 571 and feed back latch 140 via line 572 . either registers 110 and 120 or register 140 can be active at any one time . register 140 provides access to the dual port memory 150 input for any data that has been processed by an output processor 500 - 1 . . . 500 - n and is to be rewritten back into the dual port ram . this allows data in the dual port ram 150 to be processed by an output processor and stored for later use . data rewritten into the dual port ram 150 after processing by an output processor may have a different destination than the data had when it was originally written into ram 150 . in particular , one output processor e . g . 500 - 1 might first do a data conversion of some sort and then another processor e . g . 500 - 2 might control the transmission of the data to a display device or other user equipment . thus , the storage address of data rewritten into the ram 150 may have to be routed to a different fifo than when the data was first written into the ram 150 . to accomplish this , latch 230 is written to the master control 600 by way of m - bit bus 610 and &# 34 ; or &# 34 ; switch 220 and by way of line 654 and &# 34 ; or &# 34 ; gate 200 . using this circuitry , the address for data rewritten in to the dual port ram via the feedback latch 170 can be redirected to another fifo 400 - 1 . . . 400 - n . the fifo memories 400 - 1 . . . 400 - n provide an asynchronous interface between input data on line 101 and output data on line 511 - 1 . . . 511 - n of the output processors 500 - 1 . . . 500 - n . whenever a flag e . g . 693 - 1 . . . 693 - n , on any fifo is active , the interrupt multiplexer 690 sends an interrupt to master control 600 via line 691 indicating that data is available for one of the output processors 500 - 1 . . . 500 - n . once an interrupt from the interrupt multiplexer 690 is received by the master control processor 600 , an address is fetched from a fifo 400 - 1 . . . 400 - n . this can be done using a simple polling process in simple systems , and using priority interrupt schemes in more complicated systems . the fetched address is supplied to the output address latch 170 via l - bit bus 175 . following the transfer of data from dual port ram 150 to the output buffer 540 , the address is routed back to the input address generator 160 via line 173 so that it can be used again . the input and output of the dual port ram 150 operate totally asynchronously . thus , address contention is virtually impossible in this scheme because of the fixed number of unique addresses issued by the address generator 160 . desirably , this helps to guarantee that the input and output addresses presented to the dual port ram can never be the same . the output data on n - bit wide bus 151 is input to a general purpose buffer 540 . the purpose of the buffer is to supply data to various output processors 500 - 1 . . . 500 - n on data bus system 810 . the specific bus width of bus system 810 is variable and is specified to the output buffer 540 by the master control via the m bit bus 610 . the master control processor also specifies the output processor 500 - 1 . . . 500 - n via the demultiplexer 550 using the m - bit bus 610 . the function of the demultiplexer 550 is to physically activate the particular output processor selected by the master controller 600 . for example , line 552 coming out of the demultiplexer 550 may be used by the master controller 600 to select output processor 500 - n . typically , each output processor 500 - 1 . . . 500 - n can be completely different in type . processor types include video and graphics display interfaces , ethernet interfaces , unix interfaces , printer interfaces , terminal interfaces , fax interfaces , signal and data processors , and display formating devices . a desirable feature is that an arbitrary number of output processors can be easily added , each interacting with an external device in a completely independent manner . the overall speed potential of the inventive interface comes from the inherent block move characteristic of the dual port memory . each time an address from a fifo 400 - 1 . . . 400 - n is fetched , n - bits of information are transferred to an output processor 500 - 1 . . . 500 - n . the throughput of the interface can be as high as n - times the fifo transfer rate . typical numbers today are 15 million addresses per second for a fifo . for n equal to 128 , this gives a throughput of about 2 gbps . this implies dual port memory access times of 65 ns , which are in line with currently available components . each output processor 500 - 1 . . . 500 - n can communicate with the master control processor 600 via interrupt multiplexer circuit 560 and bus 610 . for example , line 562 from output processor 500 - n would be used to signal the master control 600 that output processor 500 - n wishes to receive data transmitted to the interface from a particular user source , such as user # 1 . the master control 600 knows that addresses of data from user # 1 , are stored in a particular fifo such as fifo 400 - 1 . the master control 600 orchestrates the fetching of addresses from fifo 400 - 1 . these addresses are then used to access the appropriate data from the memory 150 , which data is then routed to output processor 500 - n . clocks for the serial data input line 101 and the rest of the interface are asynchronous . timing information is derived for each incoming data packet by clock recovery circuit 100 , which information is used to drive clock 190 . the rest of the interface may be controlled by clock 700 which is distributed via line 701 . output processor activities are in general either related to the clock 700 or are run using some other asynchronous clock mechanism . an &# 34 ; up / down &# 34 ; or other counter ( not shown ) is used to indicate whether the ram 150 is empty , full or half - way in between . the primary purpose of this counter is to indicate whether the dual port ram is being filled faster than it is being emptied . if the dual port ram is being filled faster than it is being emptied , appropriate algorithms employed by the master control processor 600 , might be used to route data to output processors 500 - 1 . . . 500 - n in such a way as to empty the dual port ram more quickly . the &# 34 ; up / down &# 34 ; counter need not be a discrete circuit . illustratively , the &# 34 ; up / down &# 34 ; counter may be a memory location or register in the control processor 600 . when the &# 34 ; up / down &# 34 ; counter indicates that the dual port ram 150 is full , algorithms employed by the master control processor 600 may be used to resolve this condition . the condition might indicate that one of the output processors 500 - 1 . . . 500 - n is not functioning . in this regard , half full and full flags in each of the fifo &# 39 ; s 400 - 1 . . . 400 - n can be used by the master control processor 600 to suggest various priority strategies . it is the function of the master control processor 600 to insure that the dual port ram 150 never fills up , in which case incoming data on line 101 will be lost . the master control processor 600 may do this by continually polling the fifo &# 39 ; s 400 - 1 . . . 400 - n and by altering the polling priorities of each fifo to insure that dual port ram 150 is emptied at an appropriate rate . one of the output processors 500 - 1 . . . 500 - n may comprise a null device which is used only to dispose of data stored in the dual port ram 150 . one of the functions of the master control 600 is to initially configure the interface to establish communication between particular user sources and particular output processors and their associated receiving devices . first the register counter 180 , toggle flip - flop 130 and the input address register 160 are reset . sequential dual port ram 150 addresses are placed in the input address generator 160 starting with value zero . next , the fifo &# 39 ; s 400 - 1 . . . 400 - n are mapped on to the output processors 500 - 1 . . . 500 - n . in addition , the fifo select circuit 300 is programmed under the control of the master control processor 600 so that the addresses of particular incoming data packets are routed to particular fifo &# 39 ; s . one possible approach here is to use defaults , based on an agreed upon convention for the meaning of the m - bit patterns in the incoming packets . another approach is to communicate with the users of the of the interface and establish a first mapping between the sources of incoming packets and particular fifo &# 39 ; s and a second mapping between the fifo &# 39 ; s and the output processors . as each user is connected to the interface , it sends information to the interface describing its terminal equipment along with significant protocol information . this information is routed by way of one of the output processors to the master control 600 which appropriately configures the interface , i . e . the master control processor establishes the two aforementioned mappings . in this application it is assumed that four remotely located users wish to participate in a video conference . each conferee has at his / her location a standard 525 - line color camera , a 525 - line color display device , a 1024 - line graphics scanner or a facsimile scanner , a 1024 - line display device or a 1024 - line facsimile receiver , a pointing device such as a light - pen and a key board . preferably , the audio is transmitted separately , or is sampled at the video line rate of 15 , 734 hz , and is inserted as a digital signal in the horizontal blanking period of the video signal . in the latter case , the audio signals are processed through the telecommunications interface as part of the video signal and are separated by the user receivers . to set up a video conference call , the initiator of the call dials into the network that he / she wishes to access a telecommunications interface configured as a video bridge . the network assigns and connects the conferees to the bridge via line 101 . as each conferee is connected , it sends information describing its terminal equipment along with significant protocol information to the interface . this information is transferred to the master control 600 by way of an output processor specifically allocated for this purpose . the master control 600 then assigns each conferee one of the output processors 500 - 1 . . . 500 - n which matches the conferee &# 39 ; s terminal equipment and sends a signal via another one of the output processors to the network to connect each conferee to his assigned output processor . in this case , the output processors assigned to the four conferees could be output processors 500 - 1 , 500 - 2 , 500 - 3 and 500 - 4 ( not shown explicitly ). at this point it is assumed that all conferees are connected to the bridge via line 101 and the four input video signals arrive at the video bridge ( i . e . the interface ) in packetized format in a time division multiplexed fashion . it is also assumed that under the control of master control 600 a mapping between the four sources of incoming packets and particular fifo &# 39 ; s , and a mapping between the output processors 500 - 1 , 500 - 2 , 500 - 3 , 500 - 4 and particular fifo &# 39 ; s is established . although the packetized video signals from the four conferees arrive in sequence on line 101 , their framing signals may be asynchronous . illustratively , each of the four video signals is composed of the same number of lines per frame and the same number of picture elements per line . typically , there are 512 lines per frame and 512 picture elements per line . the input video signals from the four conferees are blocked into groups of 128 bits ( equal to 16 picture elements quantized to 8 - bits per picture element ). in order to simplify processing by the telecommunications interface , the input signals are received as component signals of the form r ( red ), g ( green ), and b ( blue ) or y , i , and q . the component color video signals arrive , eight bits per component , at the input line 101 , in sequential order of red , green , and blue , or y , i , and q , etc ., and are inserted into the shift registers 110 and 120 in the same order . each shift register , when full , contains six sets of the three color components . in order to simplify addressing and to correlate the three components , the ram memory 150 is configured in three levels where each level stores one of the color components . thus every set of r bits is stored in a first level of ram 150 , every set of g bits is stored in a second level of ram 150 , and every set of b bits is stored in a third level of ram 150 . in sequence , a shift register 110 ( see fig2 ) is filled with 128 bits of video information plus m - bits of header information which is accounted for by the register counter 180 . when the register counter 180 reaches a count of 128 it causes the next 128 bits to be entered into a shift register 120 and the bits in the full shift register 110 are parallel loaded into the ram 150 in the correct memory color planes . the register counter 180 also signals the address generator 160 that a block of bits is being entered into ram 150 . during the horizontal and vertical blanking periods of the input video signals , the sync separator circuit 10 prevents data from being written into the dual port ram 150 . the address outputted by address generator 160 is inputted to the appropriate fifo . although the four input video messages from the four conferees may effectively be entered into the ram 150 in random order in blocks of 128 bits , the fifo &# 39 ; s store the &# 34 ; random &# 34 ; memory locations so the messages may be fetched later in the correct sequence . the address generator 160 generates a base address for each block of data plus two extra bits to define each of the three color planes . a fourth combination is added to the base address and passed to the fifo &# 39 ; s which will interpret the fourth combination to mean all three memory planes are to be accessed by the base address simultaneously . this allows the three memory planes of ram 150 to be used , as a full sequential memory for non - color messages . the output of the four video images may be done in one of at least three ways . first , a conferee may select any one of the other conferees to be displayed on a 525 - line receiver with full resolution . alternatively , all four conferees are displayed on a 525 - line receiver where each input image is 2 : 1 spatially subsampled in each spatial dimension , or the four images may be outputted and displayed as full resolution ( 525 line resolution ) on a 1024 - line display device . the conferee sends his selection to the interface , which is configured in the proper output configuration by the master control processor 600 . in the first case , where one of four pictures is selected , the receiving conferee is associated , by way of master control processor 600 with the fifo which contains the ram 150 addresses for the picture to be received . the bits comprising that picture are accessed from the ram 150 and are passed to the output buffer 540 whose output is accepted by the output processor 500 - 1 , 500 - 2 , 500 - 3 and 500 - 4 assigned to the receiving conferee . illustratively , the output processor comprises a pair of shift registers for each of the color planes ram 150 which operate in a ping - pong manner similar to input shift registers 110 and 120 . the output processor has a sync generator for its output signal which is locked to the master control 600 clock signal . during the horizontal and vertical blanking intervals of the video signal outputted by the output processor , the sync generator inhibits clock signals to the appropriate fifo , thus preventing access to the ram 150 . at the start of the active picture time , it enables the clock to the fifo , which causes the picture signals to be fetched from the ram . when the correct number of active pels per line , for instance 512 have been fetched , the sync generator produces a horizontal blanking signal and inhibits the clocks to the fifo , etc . this sequence continues until the conference is ended or the conferee changes his request . next , consider the receiving conferee selecting to view a composite of the four pictures , when each picture occupies one quadrant of the receiving conferees 525 - line display . the processing of the signals is as follows . first , the receiving conferees assigned output processor must access all four fifo &# 39 ; s and use only 1 / 4 of the information which each fifo points to . one half of each input picture signal is dropped by addressing only one field of each . ( note each input picture of 512 lines comprises two 256 line interlaced fields ). the sync generator in the receiving conferees assigned output processor controls access to the ram memory 150 in the following way . assume the addresses of the four input picture signals are stored in sequential order in fifo &# 39 ; s 400 - 1 , 400 - 2 , 400 - 3 and 400 - 4 ( not explicitly shown ). with the output pictures start of active field signal , fifo 400 - 1 is enabled and it causes ram 150 to output the first 512 pel line of the first field of picture # 1 at twice the normal clock rate to the receiving conferees assigned output processor . these bits are stored in the output processor &# 39 ; s parallel loaded shift - registers where the sequential output of the shift registers is also clocked at twice the normal rate , and every other pel is skipped by sampling the serial stream at the normal clock rate . thus 256 of the 512 pels comprising the first line of the first field of picture # 1 are passed to the receiving conferee . this is one half of one line in the first field of the video signal received by the receiving conferee . at the end of the 256 pel count , fifo 402 containing the addresses of picture # 2 is enabled and the signals retrieved by it are processed in the same manner as those signals retrieved by fifo 401 . after 256 pels of the first line of the first field of input picture # 2 have been outputted by the receiving conferee &# 39 ; s output processor for a total output of 512 pels ( which comprises the first line of the first field of the output video signal received by the receiving conferee ), the addresses for the second line of the first field of input pictures # 1 and # 2 are outputted in the above described fashion . this process is continued such that odd - numbered lines of field one of input picture # 1 and # 2 are outputted as field one of the output signal and even numbered lines of field one of the input pictures # 1 and # 2 become field two of the output video signal . after 256 lines of the output picture signal have been selected from input pictures 1 and 2 , the next 256 lines of the output picture are selected from input pictures # 3 and # 4 in the same manner as described above for the input pictures 1 and 2 . thus , input pictures # 1 and # 2 form the top half of the output video display and input pictures # 3 and # 4 form the bottom half of the output video display . for outputting a combined 1024 - line picture for all four conferees , the process is similar , except that the accessing and transmission rates are four times greater . therefore , no subsampling of data accessed from ram 150 is necessary . finally , the above described embodiments of the invention , are intended to be illustrative only . numerous alternative embodiments may be devised , by those skilled in the art , without departing from the spirit and scope of the following claims .