the present invention provides an led device with good optical extraction efficiency and larger contact area for reducing p - electrode ohmic contact resistance . the led structure includes periodic nanostructures formed in close vicinity of the active region , and a regrown p - type region over the nanostructures . the regrown p - type region is formed in such a way that the surface of the p - type region in combination with the nanostructures is not completely planarised , which enables larger contact area for the p - electrode by means of contacting the sidewall regions . the invention will be detailed through the description of embodiments , wherein like reference numerals are used to refer to like elements throughout . according to the invention , an led with good light extraction efficiency and p - electrode resistance may be obtained . as illustrated in fig6 , the led structure includes a substrate 1 , a conductive n - type region 2 , an active region 3 , a first conductive p - type region 4 , nanostructures 5 formed on the first p - type region 4 , and a second conductive p - type region 6 . the first p - type region 4 is preferably a layer grown thin to a thickness between 10 nm - 80 nm . the lateral dimension ( s ) or width ( s ) w of the nanostructures 5 , also referred to herein as the diameter ( s ) of the nanostructures 5 , are preferably & lt ; 500 nm , as this is to enable current spreading to flow directly beneath the nanostructures 5 on the p - type region 4 . the diameter of the nanostructures is more preferably less than 400 nm and even more preferably less than 300 nm . the nanostructures 5 can take any particular shape and arrangement , such as squares , circles , triangles , etc ., or any combination of these shaped structures , and are preferably arranged in any of various types of periodic arrays , although the nanostructures 5 may instead be randomly arranged , etc . for example , fig7 depicts the top view of the led structure of fig6 an embodiment which utilizes circular shaped nanostructure 5 . the height ( s ) h of the nanostructures 5 is preferably between 10 nm - 100 nm , but can be larger , and the nanostructures 5 can be made of sio 2 , sin x , tio 2 , zno , mgo , sco , srf , or any other dielectric material or combination thereof . the thin first p - type region 4 , is to allow the nanostructures 5 to be placed close to the active region 3 to enable good light extraction . the second p - type region 6 is to enable a metal electrode ( not shown ) to make contact to the p - type region 6 . a first particular embodiment of an led device in accordance with the present invention is as illustrated in fig6 . the led device includes nanostructures consisting of dielectric material 5 and a regrown second p - type region 6 to complete the structure . the n - type region 2 , active region 3 and first p - type region 4 are grown in order on the substrate 1 using metal - organic - chemical - vapour - deposition ( mocvd ), for example . fig8 a is a schematic diagram of the device construction at this stage . the next step is to form the nanostructures 5 on the first p - type region 4 . as an example , a silicon oxide layer 5 a is first deposited on the nitride ( e . g ., gan ) first p - type region 4 using plasma enhanced chemical vapour deposition ( pecvd ), as illustrated in fig8 b . in fig8 c , a masking layer 8 is then formed on the silicon oxide layer 5 a and patterned to define the nanostructures . a variety of known methods can be used to create the masking layer 8 , such as nanoimprint lithography , stepper lithography , interference lithography , immersion lithography , electron - beam lithography , extreme uv lithography and / or by other means . a wet or dry etch is then employed to pattern the nanostructures 5 in what was the silicon oxide layer 5 a as represented in fig8 d . the masking layer 8 is then removed . according to this embodiment , the second p - type region 6 is then regrown over the structure by mocvd . during mocvd growth , the nitride layer made of gan which forms the second p - type region 6 will not epitaxially form on the remaining silicon oxide layer 5 a making up the nanostructures 5 , but will only do so on regions without sio 2 . this is due to the non - crystalline property of sio 2 material . however by adjusting the growth condition of this gan layer during mocvd it is possible to form gan by extending the lateral growth over the sio 2 layer . this is called lateral epitaxy overgrowth process and is well known in the art . in a preferred embodiment , the second p - type region 6 is grown to a thickness which exceeds the height of the nanostructures 5 so as to create raised sidewalls adjacent the nanostructures 5 . these sidewalls result in a larger contact area to the p - type region 6 than if second p - type region 6 and nanostructures 5 were to be planarised . however , use of the epitaxial lateral overgrowth technique ( elog ) inherent to mocvd also allows lateral overgrowth to occur across the silicon oxide layer , forming regions 6 a as shown in fig8 e . these overgrowth regions 6 a extend partially across the upper surface of the nanostructures 5 which subsequently results in an even larger contact area to the p - type region 6 than without the lateral growth . a p - electrode 7 , which is typically indium tin oxide ( ito ), but can also be made of one or more other metallic layers such as ni , ti , au , ag , pt , hf , pd , or al , is then formed over the structure of fig8 e , and an increased contact area is obtained through sidewall contacting areas 7 a as shown in fig8 f . the electrode 7 is preferably deposited using a sputter coating system to ensure good conformal sidewall coverage . in contrast , conventional art structures with planarised surface such as the example given in fig2 will have a smaller contact area . based on an assumption of a specific p - contact resistivity of 6 × 10 − 3 ωcm − 2 and p - contact area of 200 × 500 um , an invention with a nanostructure 5 dimension of 200 nm width , 400 nm pitch p ( fig7 ), lateral overgrowth thickness og ( fig6 ) of 50 nm and a second p - type region 6 layer thickness of 200 nm , a contact area of 2 . 76 × 10 − 3 ωcm 2 is obtained for the invention structure , but is only 1 . 0 × 10 − 3 ωcm 2 in the case of a conventional planar structure . this translates to a voltage drop of only 0 . 13 v at 60 ma operation , compared to 0 . 36 v for a conventional structure . this calculation is only an example , and any combination of second p - type region 6 thickness and lateral overgrowth thickness og can be used , together with various designs and pitches p of the nanostructure 5 layout . in fig8 f , the presence of the nanostructure 5 also prevents the metal electrode 7 in area 7 b to diffuse into the active region 3 , due to its close proximity . this will help in led reliability issues , since these devices are generally rated to last at least 30 , 000 hours and gradual metal electrode diffusion into the active region over time can be an issue . according to this embodiment , the general structure in fig6 can be modified to the structure shown in fig9 a . for this structure , the second p - type region 6 is regrown without any lateral overgrowth . this can be achieved , as an example by using molecular beam epitaxy growth for the second p - type region 6 , whereby crystalline material will be grown on areas in contact with the first p - type region 4 , and amorphous material grown on areas in contact with the silicon oxide nanostructures 5 . the amorphous material can then be easily removed by immersing the sample in dilute potassium hydroxide solution , leaving the final structure as depicted in fig9 a . p - contact electrode 7 is then deposited on the sample and increased contact area is obtained through sidewall contact areas 7 a . according to embodiment 3 of the invention , the structures in fig6 and / or fig9 b can be modified to the structure shown in fig1 a to take advantage of plasmonic effects to improve light extraction ( see for eg . kao et . al , iee photonics technology letters , vol . 22 , no . 13 , jul . 1 , 2010 ). for plasmonic effects to take place , a metallic layer , typically ag , au or al is placed as close as possible to the active region . no current also should conduct between the metallic layer and semiconductor directly beneath , hence a thin oxide layer is usually placed in between . in fig1 a , a metallic layer 9 is placed directly above the oxide layer forming the nanostructures 5 , as means to achieve plasmonic effects . accordingly , the nanostructure oxide layer can be thinned down by means of wet or dry etching in order to position the metallic layer ag , au and al closer to the active region . the led structure can also be configured such that a plasmonic metal layer 9 b is sandwiched between two oxide layers 5 b forming the nanostructures 5 , as shown in fig1 b . although the invention has been shown and described with respect to certain preferred embodiments , it is obvious that equivalents and modifications will occur to others skilled in the art upon the reading and understanding of the specification . the present invention includes all such equivalents and modifications , and is limited only by the scope of the following claims . the invention thereby provides an led device with nanostructures and a regrown p - type region to obtain both good light extraction efficiency and increased contact area to improve p - electrode ohmic contact resistance . the invention further provides a method of producing the structure .