the following descriptions of the preferred embodiments are provided to understand the features and the structures of the present invention . please refer to fig1 , fig2 , and fig3 , which are a diagrams illustrating the register file structure of the present invention , the ping - pong hierarchical register file according to the present invention , and another possible embodiment of the present invention . as shown in the above figures , the present invention is a method for inter - cluster communications that employs register permutation , which can be applied on any number of clusters . the said clusters have registers partitioned into a local file and a global file . the clusters exchange the data by permuting their respective global register files , which is done by dynamically changing the port mapping between the global register files and the fus . neither the size of the said partitions nor the number of connection ports is limited and the mapping between fu and global register files is done by external routing . the said routing can be a cross - bar router or some other interconnection networks . the said permutable global registers can be regarded as shared storage of the said clusters ( as shown in fig1 ), which are divided into plurality of banks 1 a 1 b . the data exchange between the said clusters is done by switching the said register banks , and has nothing to do with actual data movements . this technique works like register banking , where the physical ports and the logical ports are dynamically mapped to reduce the complexity of the centralized register file . each fu is able to exclusively access every global register directly . by doing so , data exchange mechanism of high bandwidth is built up , which also greatly reduces the silicon area , the access time , and the power consumption . as shown in fig2 , the embodiment is carried out on a 2 - way vliw dsp , where the load / store ( l / s ) unit and the arithmetic unit ( au ) have respective local registers 12 and global registers 13 . the permutation of global registers ( r 0 ˜ r 15 ) for inter - cluster communication works as a ping - pong buffer for the two clusters . here the extra hardware needed is only a switch for each cluster to select the appropriate global register file . as shown in fig3 , the embodiment is carried out on a 4 - way vliw dsp with an additional l / s unit and au . the deployed ring structure register file is composed of 8 sub - blocks . each l / s unit or au is collocated with a set of local registers 23 ( r 0 ˜ r 7 ) and global registers 24 ( r 8 ˜ r 15 ). an offset ( 0 ˜ 3 ) is assigned for dynamic port mapping as the amount of rightward deviation of the global registers 24 . if the said amount of deviation is 0 , each global register file 24 is mapped to its original fu . if the said amount is 1 , the connection of the global register file 24 is deviated rightward by one fu , and so forth . the following is an example program for a 64 - tap fir filter . two independent clusters can be easily recognized , where the ring - structure register file comprises two sets of ping - pong hierarchical register files . each one is identical to that of the previous 2 - way vliw dsp example syntax : #, ring offset , instr0 , instr1 , instr2 , instr3 ( m halfword addressed ) i0 0 ; mov r0 , coef ; mov r0 , coef ; mov r0 , 0 ; mov r0 , 0 ; i1 0 ; mov r1 , x ; mov r1 , x + 1 ; nop ; nop ; i2 0 ; mov r2 , y ; mov r2 , y + 2 ; nop ; nop ; // assume halfword ( 16 - bit ) input & amp ; word ( 32bit ) output i3 rpt 512 , 8 ; // 2 outputs per iteration & amp ; total 1024 outputs i4 0 ; lw_d r8 , r9 ,( r0 )+ 2 ; lw_d r8 , r9 ,( r0 )+ 2 ; mov r1 , 0 ; mov r1 , 0 ; i5 rpt 15 , 2 ; // loop kernel : 60 mac_v , including 120 multiplication ( 2 out ♯ put i6 2 ; lw_d r8 , r9 ,( r0 )+ 2 ; lw_d r8 , r9 ,( r0 )+ 2 ; mac_v r0 , r8 , r9 ; mac_v r0 , r i7 0 ; lw_d r8 , r9 ,( r0 )+ 2 ; lw_d r8 , r9 ,( r0 )+ 2 ; mac_v r0 , r8 , r9 ; mac_v r0 , r i8 2 ; lw_d r8 , r9 ,( r0 )+ 2 ; lw_d r8 , r9 ,( r0 )+ 2 ; mac_v r0 , r8 , r9 ; mac_v r0 , r i9 0 ; mov r0 , coef ; mov r0 , coef ; mac_v r0 , r8 , r9 ; mac_v r0 , r i10 0 ; addi r1 , r1 ,− 60 ; addi r1 , r1 ,− 60 ; add r8 , r0 , r1 ; add r8 , r0 , i11 2 ; sw ( r2 )+ 4 , r8 ; sw ( r2 )+ 4 , r8 ; mov r0 , 0 ; mov r0 , 0 ; 35 instruction cycles for 2 output ; i . e . 17 . 5 cycle / output 66 taps / cycle simd mac : mac_v r 0 , r 8 , r 9 ; r 0 = r 0 + r 8 . hi * r 9 . hi & amp ; r 1 = r 1 + r 8 . lo * r 9 . lo this is an example of a 64 - tap fir filter , which generates 1024 results . the memory is half - word addressing , where the inputs and the outputs are stored as 16 - bit fractional and 32 - bit fixed - point numbers respectively . the inner loop ( i 7 , i 8 ) loads 4 16 - bit inputs and 4 16 - bit constants to 2 32 - bit r 8 registers and 2 32 - bit r 9 registers . the l / s units update the address registers r 0 , r 1 , and the aus execute simd mac operations simultaneously . after multiplying and accumulating 32 16 - bit items with 40 - bit accumulators , r 0 and r 1 are summed up and stored to the ring ( global ) register r 8 . in the end , r 8 is stored to the memory through ls . the preferred embodiment herein disclosed is not intended to unnecessarily limit the scope of the invention . therefore , simple modifications or variations belonging to the equivalent of the scope of the claims and the instructions disclosed herein for a patent are all within the scope of the present invention .