fig1 shows a block diagram of a dual carrier transmitter 10 suitable for use with the receiver described below . the transmitter 10 receives four data input signals dl , d2 , d3 , d4 . each of these data input signals is a four level signal (+ 3 , + 1 , - 1 , - 3 ) and can be considered as encoding two bits , a sign bit and a magnitude bit . the transmitter 10 also receives five modulating signal inputs . the data signals dl and d2 are multiplied by respective sine and cosine signals sin ( 1 . 5x ) and cos ( 1 . 5x ). in fig1 x is equal to 2πt / t s . in this example t s is equal to 800 nanoseconds . the data signals d3 and d4 are multiplied by respective modulating signals sin ( 3 . 5x ) and cos ( 3 . 5x ). in each case the data signal retains its value throughout any given transmitted symbol period . this period is equal to t s , and during this period x varies from 0 - 2 . the two lower frequency signals are summed at a summing junction 12 and the resulting signal is then multiplied with an envelope signal sin ( x / 2 ). similarly , the two higher frequency signals are summed at a summing junction 14 and then multiplied by the envelope signal . the resulting signals are then summed in a third summing junction 16 to form a composite signal which is applied via a line interface 18 to a transmission medium such as a twisted pair 20 . it should be noted that the four modulating signals sin ( 1 . 5x ), cos ( 1 . 5x ), sin ( 3 . 5x ), cos ( 3 . 5x ) and the envelope signal sin ( x / 2 ) do not need to be adjusted in phase rapidly , and for this reason can be generated in a conventional manner , for example by shaping digitally generated square wave signals using standard integration and soft limiting techniques . because each of the four components encodes one of four levels , the resulting composite signal can be characterized as a 16 quadrature amplitude modulated ( 16qam ) signal . the modulating signals at 1 . 5x and 3 . 5x are suppressed carriers , and the envelope at x / 2 creates two side bands for each suppressed carrier . thus , the composite signal is characterized by a frequency spectrum emphasizing the frequencies 1 ×, 2 ×, 3 × and 4 ×. the transmitter 10 does not per se perform part of this invention , and it has been described only to clarify the environment in which the present embodiment is used . fig2 shows a block diagram of a digital demodulator or receiver 22 which incorporates a presently preferred embodiment of this invention . this receiver 22 is coupled to the twisted pair 20 via a line interface 24 . the output of the line interface 24 is applied in parallel via automatic gain control amplifiers 26 to four idad &# 39 ; s 28a - 28d . in this connection , idad is an acronym for integrate - dump - analog - to - digital . in general , each of the idad &# 39 ; s 28a - 28d multiplies the received composite signal by a respective local oscillator signal l0 , integrates the resulting product signal over an integral number of symbol periods , and then performs a two bit a - d conversion to decode two data bits from the resulting integrated value . the local oscillator signals for the two lower frequency idad &# 39 ; s 28a , 28b are synthesized from logic signals directly generated by a lower carrier divider chain 30 , and the local oscillator signals for the two higher frequency idad &# 39 ; s 28c , 28d are synthesized from logic signals directly generated by an upper carrier divider chain 32 . the four idad &# 39 ; s 28a - 28d are identical at the block diagram level , and fig3 shows a block diagram of the one of the idad &# 39 ; s 28a . as shown , a plurality of directly generated logic signals from the divider chain 30 are summed in a weighted sum circuit or summer 34a to produce a local oscillator signal lo which is multiplied with the received composite signal at a multiplier 36 . the resulting product signal is integrated in an integrator 38 over a symbol period ( 800 nanoseconds in this embodiment ). the resulting integrated value is then applied to a sign comparator 40 which generates a sign bit on line 42 in accordance with whether the integrated value is , positive or negative . the integrated value is also rectified in rectifier 39 and then applied as an input to a magnitude comparator 44 which applies a signal on line 44 indicative of whether the magnitude is greater or less than two . the signals on lines 42 , 46 represent sign and magnitude bits . the remaining elements of fig3 relate to features of the idad not pertinent to the present invention , and will not be described here . in order for the idad to function properly it is important that the four local oscillator signals l0 used in the four idad &# 39 ; s be mutually orthogonal , and that their waveforms be chosen such that integration over a symbol period of the product of the composite signal with the local oscillator signal will result in an integrated value corresponding to one of the four input data signals d1 - d4 . in addition , during signal acquisition it is important that the phase angle of the local oscillator signals l0 be quickly adjustable to correspond to the phase angle of the composite signal received on the twisted pair 20 . the present invention is directed to an improved apparatus for generating the local oscillator signals lo used in the four idad &# 39 ; s 28a - 28d . the remaining portions of the receiver 22 have been described only generally , because they do not per se form part of this invention . according to this invention , the lower and higher carrier divider chains 20 , 32 include means for directly generating a plurality of logic waveforms , each having a respective phase . because the logic waveforms are directly generated , the phase can readily be changed , as for example during signal acquisition . the local oscillator signals l0 for the four idad &# 39 ; s 28a - 28d are directly synthesized by the weighted sum circuits 34a - 34d from the logic signals generated by the lower and higher carrier divider chains 30 , 32 . fig4 shows in block diagram form the two divider chains 30 , 32 and the resistor networks 34a - 34d of the idad &# 39 ; s 28a - 28d . the lower carrier divider chain 30 is responsive to a 24x clock signal generated by a voltage controlled oscillator 48 . this clock signal is divided by twelve by dividers or counters 50 , 52 to generate the logic signal components 2xqa and 2xqb as shown in fig5 . these signals are delayed by the delay circuit 54 to generate the logic signal components 2xia and 2xib , also as shown by fig5 . a state decoder circuit 56 and a divide by four circuit 58 in turn generate the lxia and the lxqa logic signal components as shown in fig5 . finally , the state decoding circuit 60 generates the lxib and the lxqb logic signal components as shown in fig5 . similarly , the divider chain 32 is responsive to a 24x clock generated by a voltage controller oscillator 60 and includes divider or counter circuits 62 , 64 which generate 3xi and 3xq logic signals as shown in fig5 . a divide by three circuit 66 generates 4xi and 4xq logic signals , also as shown in fig5 . appropriate ones of the logic signals generated by the circuitry of fig4 a and 4b are summed by resistor networks 34a - 34d to generate the four local oscillator signals l0 required for operation of the idad &# 39 ; s 28a - 28d . though simple resistor networks are shown , those skilled in the art will recognize other means can be used to perform the summing function . the resistor networks 34a - 34d sum selected ones of the logic signals to generate the four local oscillator signals shown in fig6 a - 6d . in fig6 a - 6d the respective ideal , sinusoidally varying waveforms that are being approximated are shown as dot - dash lines . these ideal waveforms are defined as follows : the presence of 2x in the first two waveforms , and hence in the step approximation waveforms , is important for proper operation of the current embodiment , but is not required for all embodiments of this invention . as shown in fig6 a , the local oscillator signal for the idad 28a is created by summing four directly generated logic signals weighted as follows : the local oscillator signal for the second idad 28b is shown in fig6 b . it too is the result of the summation of four directly generated logic signals weighted as follows : fig6 c shows the local oscillator for the idad 28c which is generated as an equally weighted sum of two directly generated logic signals 3xi and 4xi . fig6 d shows the local oscillator signal for the idad 28d which is generated as the equally weighted sum of two directly generated logic signals 3xq and 4xq . it is important to note that the four local oscillator signals shown in fig6 a - 6d , even though rough approximations of sinusoidally varying signals , nevertheless have been carefully selected to minimize undesired harmonics . with respect to the local oscillator signals of fig6 a and 6b , the component waveforms and their weights are chosen such that the third , fourth , fifth and sixth harmonics of 1x and the second and third harmonics of 2x are zero . thus , the spectrum of the step approximation shown in the fig6 a and 6b matches that of the ideal sinusoidally varying local oscillator signal below 7x . with respect to the local oscillator signals shown in fig6 c and 6d , the lowest harmonic present is the third harmonic of 3x , and for this reason the spectrum of the step approximation shown in fig6 c and 6d matches that of the ideal , sinusoidally varying local oscillator signal below 9x . in this embodiment , the third and fourth harmonic components of the directly synthesized local oscillator signals of fig6 a and 6b are at least 30 db less than that of the fundamental component , and the fifth harmonic component is also markedly reduced . in the absence of circuit implementation imperfections , the harmonic components at 3x , 4x , 5x and 6x would all be exactly zero . this desirable result is achieved through proper selection of the amplitudes and timing of the component logic signals . the local oscillator signals of fig6 a and 6b are characterized by at least three discrete amplitudes , and adjacent ones of these discrete amplitudes differ in amplitude by amplitude differentials selected such that at least two of the differentials differ from one another . another important feature of the local oscillator signals of fig6 a and 6b is that the transitions between the discrete amplitudes are separated from one another by time periods , and at least one of the time periods differs in duration from another one . returning now to fig4 a and 4b , the divider chains 30 , 32 each include a resync conductor which is coupled to the counters 50 , 52 , 58 , 62 , 64 , 66 , and state decoding circuits 56 , 60 . this resync conductor carries a synchronization signal which , when present , is effective to reset the counters . thus , by simply setting the synchronization signal , the phase of the logic signals generated by the divider chains 30 , 32 can be adjusted quickly and precisely . this is a direct consequence of the fact that filtering , smoothing or integration circuits are not used to generate or process the directly generated logic signals of the divider chains 30 , 32 . this synchronization signal in effect alters the counts by resetting the counters to alter the phase of the logic waveforms . fig7 shows a schematic diagram of the divider chains 30 , 32 , and this figure discloses the best mode presently known to the inventors for carrying out this invention . this diagram was prepared using xylinx schematic to lca conversion software ( x3000 library , orcad interface ). during normal operation the runmode and the hilock inputs are in the logic high state . from the foregoing it should be apparent that an improved apparatus has been disclosed for generating local oscillator signals which approximate the desired sinusoidally varying signals well enough to suppress or eliminate undesired harmonics , yet which are directly generated in a manner that facilitates high speed adjustment of the phase of the local oscillator signals during signal acquisition . it should be understood that the foregoing detailed description is illustrative and not limiting , and that the present invention is defined by the following claims .