fig3 shows a stacked structure of an array module according to the present invention and here specifically shown with five stacked array modules s 1 . . . s 5 , substantially realized as shown in fig1 . it is , however , to be understood that the number of stacked array modules is not restricted to five as will be evident from the following discussion . an array module s 1 is first formed on a suitable array 5 as shown . the array module comprises as known in the art a plurality of electrodes m , n , a functional medium 1 which well may be a memory medium in the form of an active material , and logic cells 2 defined in the logic medium 1 between an overlying portion 3 of the electrode m and underlying portion of the electrode n . only one logic cell in the array module s 1 is shown and it is to be understood that the number of logic cells in an array is given by the product x · y , where x is the number of electrodes m and y the number of electrodes n . a corresponding number of logic cells 2 may , of course , be realized in each of the succeeding array modules s 2 , s 3 , . . . without that being specifically shown . a further feature is that a dielectric isolation layer 7 1 . . . 7 5 is located between electrodes m 1 . . . m 5 and separation layer 6 1 . . . 6 5 . this provides for a dielectric isolation layer between array modules s 1 and s 2 . the array module corresponding to s 1 is formed on a suitably selected substrate 5 . thereafter a separation layer 6 1 is globally provided on the top of the array module s 1 providing a separation which may be respectively mechanical , chemical , electrical , optical or thermal , possibly also a combination of such separation types between the lowermost array module s 1 and a succeeding array module s 2 which is provided on the top of the separation layer 6 1 . now a separation layer 6 2 is provided on the top of the array module s 2 and then follow in their turn further modules s 3 , s 4 , . . . with their respective separation layers 6 3 , 6 4 . . . until the stacked array configuration is obtained with as many array modules as is desirably or realistically attainable . the array module also includes as a feature of the invention , a dielectric isolation layer 7 located between electrode m and separation layer 6 . the deposition of the separate layers , irrespective of whether they are separation layers , electrode layers or functional medium layers which together form each separate array module s 1 , s 2 and finally , the whole stacked or volumetric configuration as shown in fig3 may be realized by means of a number of different methods , for instance by deposition by doctor blading , dipping , spin coating , brushing , selfasembly sputtering , evaporation and ablation . a number of such deposition methods will be compatible with high volume production processes wherein strip - like materials are used in a reel - to - reel approach . the realized volumetric array configuration as shown in fig3 is particularly advantageous in regard of realizing high volumetric density , on the condition that each separate array module s 1 , s 2 , . . . is very thin . array modules which are used with polymer - based functional media in memory materials , will typically have a thickness less than 1 μm and it will hence at least theoretically be possible to stack up to 1000 array modules per mm , if the separation layers also are thin , i . e . have a thickness in the submicrometer range . it is for instance technically possible to realize separation layers in thin film technology and with a thickness less than 100 nm . the lower most module includes the dielectric isolation layer 7 1 between electrode m 1 and separation layer 6 1 . as known in the art the separation layer may correspond to the use of electrical isolating layers between the array modules s 1 , s 2 such as is known from the prior art according to the above - mentioned norwegian patent application . hence there is nothing against providing separation layers in connection with isolation layers or possibly combining layers of this kind . according to the present invention the separation layers can , however , be distinctly different from possible electrical isolating layers and formed by a great number of materials . in a volumetric stacked structure according to the invention as shown in fig3 a number of advantageous properties may be obtained which are not immediately connected to the electric properties of the array modules , such these latter for instance appear in connection with addressing with logic operations and storage of data in mind . a potential problem with a volumetric stacked array configuration wherein the logic cells are arranged with high density , is the occurrence of an unacceptable temperature rise due to the dissipation of electric energy in connection with addressing and processing operations in the separate array module or simultaneously in several array modules , as a great number of logic cells which is provided in an array of this kind , of course , advantageously may be addressed simultaneously or in massive parallelism . this energy dissipation may be avoided by using separation layers having good thermal conductivity . this implies that metals such as copper , aluminium or silver may be relevant in this connection , but also thin films of diamond or diamond - like carbon or carbon nanocomposites may according to the invention be preferable due to their extremely high thermal conductivity and possibility of depositing them at low to moderate substrate temperatures . certain nanocomposites also have a very high electrical conductance and this may be exploited with electrical shielding for eliminating cross talk between the separate array modules s 1 , s 2 , in mind . of course , separation layers of metals , for instance the above - mentioned , or different metal alloys may provide a shielding of this kind . another potential problem with the application of volumetric stacked array configurations as shown in fig3 is cross talk between the separate array modules s 1 , s 2 . . . due to acoustic or mechanical coupling . certain types of active materials used for storage or processing purposes respond to electrical stimuli , for instance of electrostrictive , piezoelectric or electrochemical nature etc . with a dimensional change . hence a mechanical shock may propagate from a point within the volumetric configuration , being picked up by a mechano - electrical conversion in another point and generate an array signal which may cause interference . in order to avoid this it is according to the invention hence preferred that a separation layer is realized as a mechanical , thermal or thermo - mechanical oscillation damper . finally it is also a problem in the manufacture of stacked array modules as shown in fig3 that microscopic irregularities or unevenly thick layers cause a diminishing degree of planarity in the successively deposited layers , which in its turn may cause in sum regarded a distorted structure . corresponding problems are known from common electronic technology , for instance the realization of integrated circuits on a substrate , where the integrated circuits comprise several layers which , however , are included in the same functional application in the circuits , but wherein the problem with missing planarity yet may be desirable to avoid . it is well - known to provide a planarization layer which with a precisely controlled thickness is deposited on the layer that is to be planarized and levels thickness variations or distortions therein . according to the present invention the separation layer may preferably comprise a planarization material which is admixed to the layer in the deposition which is performed under such physical conditions , for instance of thermal nature , that planarization takes place . the planarization material may also be provided in a separate layer which is integrated planar with the separation layer in a particular and carefully controlled deposition process on the top of the separation layer before the next array module is deposited .