in the following detailed description of the preferred embodiments , reference is made to the accompanying drawings , which form a part hereof , and in which is shown by way of illustration specific preferred embodiments in which the inventions may be practiced . these embodiments are described in sufficient detail to enable those skilled in the art to practice the invention , and it is to be understood that other embodiments may be utilized and that logical , mechanical and electrical changes may be made without departing from the spirit and scope of the present invention . the following detailed description is , therefore , not to be taken in a limiting sense , and the scope of the present invention is defined only by the claims and equivalents thereof . embodiments of the present invention provide a translation tool that migrates analog and rf ( intellectual property ) ip across integrated circuits processes to boost design productivity . this is accomplished by translating all databases including schematic and layout designs from one process to another . for example , the translation tool can translate original schematic and layout that were designed in one process to a schematic and layout database in another process . the new schematic database preserves almost all critical component parameters such as resistance , capacitance , transistor size and all original connectivity and is simulation ready right after the translation . in one embodiment of the present invention , the translated layout database preserves all mapped layers and devices with proper location and conductivity and is ready to restore the layout connectivity from schematic by using a connectivity - based layout tool . the translation tools of the present invention also provide means for designers to probe and compare the original design component parameters easily in the new design database and environment without having to open the original design . an example of a translation process in which the current invention is applicable is the translation of one wireless local area network ( wlan ) transceiver from an internal pure silicon bicmos process “ process 1 ” to another sige bicmos process “ process 2 ” with exact product specification requirements . the present invention maps similar devices and mask layers from one process to another . the device characteristics , models and component description format ( cdf ) parameters have to be carefully evaluated so that similar components and cdf parameters can be mapped . also , the processes have to be carefully examined so similar mask layers can be mapped as well . one common problem is resistor sheet rho ( or area resistance ) and capacitor area capacitance normally doesn &# 39 ; t match between processes , so in one embodiment of the present invention there are options to preserve either resistance / capacitance or geometry . in particular , in order to keep electrical consistency of the schematic design , the resistance and capacitance are typically preserved and in regards to layouts , the geometry , such as length and width , are preserved . in various embodiments of the present invention , higher - level schematic requirements are included to keep conductivity in the schematic with correct device rotation , polarity , program node and inherited connection as well as adding extra or removing redundant wires automatically . these higher level embodiments , layout requirements typically include correct device layout placement location and rotation , ability to use connectivity - based layout editing tool to restore the conductivity from the schematic after translation , and automatic grid and diagonal line mode check correction . after translation , there are times designers want to go back to check the original design cdf parameters . embodiments of the present invention allow the designers to do this without launching a separate design session and opening the original design in a different window . instead , in other embodiments , the original device cdf parameters are preserved in the translated design as data base properties . these properties can then be displayed side by side with the new cdf parameters for comparison reasons without opening a separate design session . limitations are generally identified before implementation , so they can be dealt with later . limitations may include unmatched devices , cdf parameters , nodes and mask layers . in one embodiment , reports are generated when a limitation is encountered during the translation process . fig1 , is a flow chart 100 illustrating a process translation of one embodiment of the present invention . the process starts by creating a configuration file ( 102 ). the configuration file describes the translation requirements . it may include device mapping , terminal mapping , insertion origin , polarity and rotation , mask layer mapping , parameter mapping and functions to be triggered after translation , resistor / capacitor options and interconnect layer options . process 1 and process 2 libraries are defined ( 103 ). the source library / cell is copied to a new library ( cell ) ( 104 ). the configuration file is then read ( 106 ). schematic and layout resistor / capacitor option is set ( 108 ). interconnect later option for layout is set ( 110 ). the original schematic database information is read ( 112 ). the schematic is translated by a predefined code ( 114 ). the original schematic information is written into a new database ( 116 ). the original device information in the new data base can be queried by a designer to obtain original design information ( 130 ). the original layout database information is read ( 118 ). the layout is then translated by a predefined code ( 120 ). the original layout information is then written into a new database ( 122 ). the original device information in the new data base can again be queried later by a designer to obtain original design information ( 130 ). the layout grid and line mode are check and corrected ( 124 ). an example of a process translation is the translation between process 1 and process 2 . examples of devices translated between process 1 and process 2 are provided in table 1 . know limitations of process 1 to process 2 include : 1 . the device parameter limits are different between process 1 and process 2 . for example , capacitor minimum 1 / w in process 1 is 5 um , while in process 2 they are 8 um , so all process 1 min caps with 1 / w less than 5 um will be set to 8 um after translation . the npn device maximum number of stripes in process 1 is 6 , while in process 2 it is 2 . so any number of strips larger than 2 in process 1 will be set to 2 in process 2 . there is no limitation in npn emitter width , but process 2 imposes a 50 um maximum , so any emitter width larger than 50 um in process 1 will be set to 50 um in process 2 . 2 . all pwell , nbl and substrate nodes will be mapped between process 1 and process 2 devices if applicable , however , in some cases , there are no correspondence , then the process 2 device will use the default pwell , nbl and substrate node connection . in one embodiment you must manually connect them for the design . referring to fig2 , a flow chart 200 illustrating the setup and steps for a process 1 to process 2 translation of one embodiment of the present invention is illustrated . as illustrated , a design framework session is started ( 202 ). it is determined if a process 1 library exists ( 204 ). if it does not exist , it is defined ( 205 ) with the use of a “ library manager -& gt ; edit -& gt ; library path .” once the process 1 libraries exist , the library manager is used to make a copy of the source process 1 design library to a new library and attach a new process techfile to the new library ( 206 ). for example , a process 1 design library “ usrlib ”, can be copied and named “ usrlib - copy20 ,” then a techfile process 2 is attached to “ usrlib - copy20 .” then the process translation menu is chosen to bring up the translation gui ( 208 ). the source library is then selected ( 210 ). the source library is the original process 1 . it will be read throughout the translation process . the source library must be attached to the process 1 library . in this example , the source library is “ usrlib .” the target library is then selected ( 212 ). the target library is the library that will be changed and converted to the process 2 design . the target library must be attached to the process 2 library . in this example the target library is “ usrlib_copy20 .” the schematic and layout resistor and capacitor translations options are exercised ( 214 ). as discussed above , the resistance / capacitance and size of the resistors and capacitors can be keep the same through the translation or modified per the application . the default is that the resistance and capacitance are kept the same for schematics and the size is kept the same for layouts . next , the layout metal portion m3 to mt or to am options are selected ( 216 ). the default option in this embodiment is m3 to mt . the translation is then started ( 218 ). an example of a graphical user interface ( gui ) 300 to initiate a translation of one embodiment of the present invention is illustrated in fig3 . as illustrated , the gui 300 includes inputs for ; source library name 302 , target library name 304 , schematic capacitor option 306 , schematic resistor option 308 , layout capacitor option 310 , layout resistor option 312 , layout m3 option 314 and run directory 316 . also illustrated is a start translation activation bar 318 . referring to fig4 , an example of a partial schematic diagram of a process 1 before translation is shown . as illustrated , the schematic diagram 400 includes transistors 402 , 404 and 406 . fig5 illustrates an example of an schematic diagram 500 after translation . as illustrated , this example includes transistors 502 , 504 and 506 . fig6 is an original display 600 of original process 1 information of one embodiment of the present invention . as illustrated this display 600 includes the library name 602 , the cell name 604 , the instance name 606 , the length 608 , the total width 610 and the gate stripes 612 . referring to fig7 , a translated display 700 of one embodiment is illustrated . the translated display 700 of this embodiment includes a label display 702 , a tracking display 704 and a cdf parameter display 706 . the label display 702 includes the library name 708 , cell name 710 , view name 712 and instance name 714 . the tracking display includes the interface last time and date 716 and modification file 718 . the cdf parameter display 706 includes a request to add nw contact to pcell 719 , width 720 , width ( parallel ) 722 , length 724 , number of fingers 726 , multiplicity 728 , connect terminals 730 , gate connection 732 , extend m1 for alignment ? 734 , left rx contact fill (%) 736 , right rx contact fill (%) 738 , center rx contact fill (%) 740 . please note that the instance name 606 of the original display 600 of fig6 is the same as the instance name 714 of the translated display 700 of fig7 in these embodiments . an example of a layout 800 before translation is illustrated in fig8 . fig8 illustrates a device location , rotation and polarity generally at 803 , an interconnect at 805 and an unnecessary layer at 801 . fig9 illustrates an example of an after layout 900 after the translation has been completed . as illustrated device layout location , rotation and polarity at 903 are preserved . moreover interconnects , such as 905 are preserved and unnecessary layers are dropped ( i . e . there is no corresponding layer to layer 801 of fig8 in fig9 ). moreover , conductivity is restored . for example , please refer to 907 and 909 of fig9 . in addition , additional layers are added as an interconnect option if required . an example of this is illustrated in fig9 a and 9 b . fig9 a illustrates two metal layers m2 920 and n3 922 coupled to each other by vias 924 before a translation . fig9 b illustrates three layers m 2 920 , mt 922 and am 926 coupled to each other respectively by vias 924 and 928 after translation . referring to fig1 , an example of a top level layout 1000 of an integrated circuit after translation is shown . as described above , embodiments of the present invention map mask layers and map device parameters between two different processes . some embodiments have callbacks that can be triggered . some embodiments provide an option to add extra interconnect layers . further embodiments , allow for the addition and deletion of wires automatically to keep the schematic design electrically correct . moreover , other embodiments preserve instance names in both schematic and layout so that layout conductivity can be restored after translation . still further embodiments , automatically grid and line mode ( diagonal ) check and provide corrections . although specific embodiments have been illustrated and described herein , it will be appreciated by those of ordinary skill in the art that any arrangement , which is calculated to achieve the same purpose , may be substituted for the specific embodiment shown . this application is intended to cover any adaptations or variations of the present invention . therefore , it is manifestly intended that this invention be limited only by the claims and the equivalents thereof .