[ 0018 ] fig4 shows relevant portions of a receiver for a digital communication system in accordance with this invention . other conventional portions of the receiver are not shown . for instance , where this receiver is used in a fast ethernet environment , the conventional higher layers of circuitry that interface to e . g . a computer that uses the received data signal are not shown . the receiver in fig4 is intended to replace elements 30 and 32 in a system as in fig1 and hence only represents the analog transition time processing portion , i . e ., the clock and data recovery portion of the receiver . in fig4 as in fig1 line 60 is coupled to the output terminal of an equalizer / slicer circuit 26 , which may be conventional . the incoming data signal on line 60 is therefore coupled to one ( clock ) input terminal of a lead / lag detector 62 , the other input terminal of which is coupled to the output terminal 88 of multiplexer 70 and to the clock terminal of the data recovery flip flop 90 . lead / lag detector 62 is e . g . a d type flip flop connected as shown . in this case the clock input terminal is connected to receive the “ data ” input while the d input terminal is connected to receive the “ clock ” input signal , so this flip flop 62 is connected in the reverse to the usual flip flop connections . this is because the data signal is being used to sample the clock signal to determine if it ( the clock ) is currently leading or lagging . the output ( q ) terminal of the detector 62 is connected to the input terminal of a non - linear digital signal processing element 64 which is part of the loop filter referred to above , further functionality of which is explained below . the output terminal of the non - linear dsp element 64 is connected to the input terminal of a phase pump 68 . the phase pump 68 is a digital circuit that essentially increases or decreases its output signal ( according to its input signal ) and holds its output signal . in this case the phase pump input signal is the amount of lead or lag as determined by 64 elements and its output goes to selector 70 . so as long as the output signal of element 64 is zero , the output signal of phase pump 68 will be held e . g . for 32 data edges . the output port of phase pump 68 is an n bit digital bus coupled to the n control terminals of a selector ( multiplexer ) 70 . the various signal input terminals of multiplexer 70 are coupled to receive various clock signals f 1 , f 2 , f 3 , f 2n . in one example n equals 5 , and so there are 32 such clock signals . the frequency of each clock signal f 1 , f 2 etc . is the same : however they are each slightly out of phase with one another , i . e . each is a successively delayed version of the clock signal . in one embodiment these clock signals are generated by applying a single clock signal from source 76 to the input terminal of a set of serially connected delay elements 78 , 80 , . . . 82 . hence in this case there are 31 such delay elements providing 32 signals f 1 , f 2 , . . . f 32 . the delay provided by each delay element is equivalent to that of ½ n times the minimum expected time between successive data signal edges ( data signal period ). hence in one example if the period between successive data signal edges is no less than 8 nanoseconds and there are 31 delay elements , each delay element gives 0 . 25 nanoseconds of delay . the source 76 of the clock signals in fig4 is here designated as being a transmission ( tx ) clock , because in one embodiment the source 76 is an on - chip “ transmission clock ” signal which is part of a transmitter . ( it is to be understood that the fig4 circuit , while it is a receiver , in this embodiment is on the same integrated circuit with an associated transmitter which has its own clock signal source .) generally such an “ on - chip ” transmission clock signal is known to be within a very small tolerance , in terms of frequency , of the received signal &# 39 ; s clock signal . hence this is a convenient source of a clock signal which is close to that of the received clock signal which is to be recovered . of course , other sources for the reference clock signal ( s ) may be used instead . hence the output signal from the selector ( multiplexer ) 70 is the selected clock signal which is used to clock the data recovery circuit 90 , which is similar to the data recovery circuit 32 in fig1 and also used as a second input signal to the lead / lag detector 62 . hence the elements 62 , 64 , 68 , 70 with feedback line 88 form a digital delay locked loop . note that only one phase of the reference clock 76 is needed at any given time . it is to be appreciated that in one embodiment this is essentially a digital device embodied in digital logic circuitry rather than by analog elements . as seen , no conventional analog filtering components are needed . instead , filtering is provided by the non - linear digital signal processing element 64 . in one embodiment this is an all digital device , i . e . having no resistors or capacitors . hence the present digital delay locked loop is all digital . the non - linear digital signal processing element 64 in one embodiment is all digital “ hardware ” ( logic circuitry ). however this is not limiting and in other embodiments this and other elements in accordance with this invention may be for instance in the form of code ( software ) to be executed by a general purpose processor or by a dedicated digital signal processor . appendix a of this disclosure shows , in the form of verilog code , one version of the relevant circuitry . verilog code is a well known representation of digital logic circuitry , for instance for use in integrated circuits . the verilog code in appendix a , at pages 1 and 2 , represents both the phase detector 62 and the non - linear digital signal processing element 64 . page 3 represents the phase pump 68 . the non - linear digital signal processing element 64 determines if the previously chosen clock signal , supplied on the d terminal of lead / lag detector 62 is arriving , in terms of time , before ( leading ) or after ( lagging ) the data edge provided on line 60 . element 64 in one embodiment counts a consecutive number of such lead / lag comparisons , e . g . 16 . clearly if the last 16 comparisons include a preponderance of data pulse edges leading the clock signal , it is desirable to advance the clock signal ; if the data edges are lagging the clock signal , it is desirable to retard the clock signal . hence in the code pos - cnt ( positive count ) refers to the number of data pulse rising edges counted . one embodiment counts both the rising and falling edge of each data pulse . one accumulates e . g . 16 such counts . in one embodiment if more than half these 16 counts indicate the existence of a lead , then one wants to delay the clock signal ; if less than half of them indicate a lead , one wants to advance the clock signal . in one embodiment the advance at each instance is only one increment , where the increment is the difference between for instance signals f 1 and f 2 or f 2 and f 3 etc . hence in this relatively simple version the advance ( or retardation ) at each decision time , e . g . 16 data edges , is only one phase ( one delay period 78 , 80 , 82 , etc .). in another version , the amount of delay or advance is made variable by using a more sophisticated non - linear dsp process in element 64 . hence the output signal from the non - linear dsp element 64 is in one embodiment merely a 0 or 1 , where 1 indicates advancing the clock phase by one delay and 0 indicates retarding the clock phase by one delay . the phase pump 68 then translates this value into the desired selection from amongst f 1 , f 2 , f 3 , etc . since the phase pump 68 keeps track of the previously selected clock signal f 1 , f 2 , etc . hence by use of such an apparatus and the accompanying method , one dynamically alters the phase of the recovered clock signal using the all - digital delay locked loop . this disclosure includes copyrightable material . the copyright owner gives permission for facsimile reproduction of material in patent office files but reserves all other copyright rights whatsoever . this disclosure is illustrative and not limiting ; further modifications will be apparent to one skilled in the art in the light of this disclosure and are intended to fall within the scope of the appended claims .