this disclosure presents a novel control method that enables hi - pf qr flyback converters with peak current mode control to ideally draw a sinusoidal current from the input source , thus performing like boost converters operated in the same way . one idea of the present disclosure stems from observing the waveforms shown on the right - hand side of fig2 and comparing them to those of a boost converter ( shown in fig6 along with the topology ). in the boost converter , the input current is the average of the inductor current , which flows both during the on - time and the off - time of the power switch . as a result , being a series of contiguous triangles , the average value of the inductor current is half the peak . also , given that the envelope of the peaks is sinusoidal , the input current will be sinusoidal . in contrast , in the prior art flyback converter of fig1 , the input current is the average of the primary current , which flows only during the on - time of the power switch and is a series of triangles separated by voids corresponding to the off - time of the power switch , as shown in fig2 . this “ chopping ” causes the average value of the primary current to be lower than half the peak value and depending on the mark - space ratio of the triangles . as a result , the input current is no longer proportional to the envelope of the peaks and , unlike the envelope that is sinusoidal , the input current will not be sinusoidal . the term i pkp ( θ ), which represents the peak envelope of the primary current , is sinusoidal so the distortion is originated by the term t on / t ( θ ), introduced by the primary current being chopped , which is not constant ( t on is constant but t ( θ ) is not ). the inventors discovered that if the current reference vcs ref ( θ ) that determines i pkp ( θ ) is distorted with a term t ( θ )/ t on , this will cancel out the term t on / t ( θ ) introduced by averaging and result in a sinusoidal average primary current , i . e . in a sinusoidal input current . then , the control objective can be expressed in the following terms : wherein t on is denoted as a function of the instantaneous line phase θ . in fact , with a method different from that of the prior art it is not necessarily constant . fig7 shows a hi - pf flyback converter 100 a according to one embodiment of the present disclosure . the converter 100 a of fig7 has on the primary side a bridge rectifier 104 having inputs 106 , configured to receive an ac voltage from an ac power line , a first output connected to ground , and a second output at which the rectifier is configured to produce a rectified voltage v in ( θ ). the converter 100 a also includes a capacitor c in , which serves as a high - frequency smoothing filter , connected across the output terminals of the bridge rectifier 104 , with a negative terminal connected to ground . a primary winding l p of a transformer 108 has one end connected to the positive terminal of the capacitor c in and includes an auxiliary winding l aux . the other end of the primary winding l p is connected to the drain of a power switch m . the power switch m has a source terminal connected to ground via a sensing resistor rs , the resistor r s allowing reading of the current flowing through m ( i . e . the current flowing through l p when m is on ) as a positive voltage drop across the resistor rs itself . a controller 102 a controls the power switch m . as in the converter 30 of fig1 , the converter 100 a includes the resistive voltage divider r a / r b connected in parallel with the capacitor c in , and the clamp circuit 39 . on the secondary side of the converter 100 a , a secondary winding l s of the transformer 108 has one end connected to a secondary ground and the other end connected to the anode of a diode d having the cathode connected to the positive plate of a capacitor c out that has its negative plate connected to the secondary ground . an output voltage v out supplies power to a load ( not shown ). the quantity to be regulated ( either the output voltage v out or the output current i out ) is compared to a reference value and an error signal i fb is generated . this signal is transferred to the primary side by an isolated feedback block 134 , typically implemented by an optocoupler ( or other means able to cross the isolation barrier complying with the safety requirements of iec60950 ). on the primary side , this error signal i fb is sunk from a dedicated pin fb in the controller 102 a , producing a control voltage v c on said pin fb . the open - loop bandwidth of the overall control loop is determined by a frequency compensation network located inside the isolated feedback block 134 . the controller 102 a has a shaper circuit 120 a , a pwm comparator 122 , an sr flip flop 124 , an or gate 126 , a starter block 128 , a zcd block 130 , and a driver 132 . the shaper circuit 120 a is configured to produce a reference voltage v csref based on a voltage v c and a portion of the instantaneous rectified line voltage v in ( θ ) received from the midpoint of the resistive divider r a / r b via the pin mult . the pwm comparator 122 is configured to receive as inputs the reference voltage v csref and the voltage v cs sensed at the resistor r s . the sr flip flop 124 has reset and set inputs r , s that respectively receive the output of the pwm comparator 122 and the output of the or gate 126 . the driver 132 receives as an input the output of the sr flip flop 124 , and configured to drive the power switch m via an output signal provided to a terminal gd coupled to the gate of the power switch m . the zcd block 130 is configured to release a pulse when a detected falling edge of a signal , received from the auxiliary winding l aux and resistor r zcd via the terminal zcd , goes below a threshold value . the starter block 128 is configured to release a pulse on start - up or when the zcd block 130 receives no input signal . the or gate 126 has inputs that respectively receive the outputs of the starter block 128 and zcd block 130 and provides a set signal to the set input s of the flip - flop 124 when either of the outputs from the starter block 128 and zcd block 130 is positive . a multiplier 140 is coupled to the shaper circuit 120 a . the shaper circuit 120 a has a current generator 142 , a resistor r t , and a switch 143 that switchably couples the resistor r t to ground . the multiplier 140 has a first input that receives the voltage v c , a second input that receives the portion of the line voltage v in ( θ ) from the terminal mult , and an output at which the multiplier produces a multiplied voltage that is the product of the two voltages received at the inputs . the current generator 142 is controlled by the output of the multiplier 140 and is configured to output a current i ch ( θ ) that acts on the switched resistor r t and an external capacitor c t having one terminal connected to ground . the resistor r t is connected in parallel to the capacitor c t when a signal q provided to the control terminal of the switch 143 is high . the signal q is provided by the output of the sr flip - flop 124 and is high during the on - time of the power switch m . the switch 143 disconnects the resistor r t from ground when the signal q is low , i . e . during the off - time of the power switch m . the voltage developed across c t is the reference voltage vcs ref ( θ ) and is fed to the inverting input of the pwm comparator 122 . in one embodiment of the present disclosure c t is integrated in a semiconductor chip with the controller 102 a , thus saving one pin of the controller 102 a and one external component . the current i ch ( θ ) provided by the current generator 142 can be expressed as : i ch ( θ )= g m k m k p ( v pk sin θ ) v c where g m is the voltage - to - current gain of the current generator 142 , k m is the gain of the multiplier , k p is the divider ratio of the resistive divider r a / r b , and v pk sin ( θ ) is the peak value of the line voltage v in ( θ ). note that the control voltage v c is nearly constant along a line half - cycle , thus the charging current i ch ( θ ) has a sinusoidal shape . an assumption for the following analysis is that t ( θ )& lt ;& lt ; r t c t & lt ;& lt ; 1 / f l . in this way , the switching frequency ripple across the capacitor c t is negligible and the current i ch ( θ ) can be considered constant within each switching cycle . the reference voltage vcs ref ( θ ) developed across the capacitor c t by charge balance is therefore : the control circuit in fig7 therefore meets the control objective ( 2 ) and achieves a sinusoidal input current in the hi - pf qr flyback converter 100 a , resulting in high power factor and low total harmonic distortion . fig8 shows the waveforms of the converter 100 a of fig7 . on the left - hand side are the waveforms on a switching period time scale , on the right - hand side the waveforms on a line cycle time scale . fig9 shows another embodiment of a qr flyback converter 100 b according to the present disclosure . the converter 100 b is identical to the converter 100 a of fig7 except that the converter 100 b includes a controller 102 b instead of the controller 102 a . the controller 102 b includes a shaper circuit 120 b that has the same components as the shaper circuit 120 a of fig7 , but the multiplier 140 is connected differently to the components in the two shaper circuits 120 a , 120 b . in particular , the output of the multiplier 140 is connected to the inverting input of the pwm comparator 122 of the shaper circuit 120 b , while the input of the multiplier 140 that is connected to the resistor divider ra - rb by the terminal mult in fig7 is connected to one terminal of the external capacitor c t in fig9 . unlike the shaper circuit 120 a of fig7 , the current generator 142 of the shaper circuit 120 b of fig9 is directly controlled by the portion of the line voltage v in ( θ ) received from the resistor divider ra - rb via the pin mult in the controller 102 b . as a result , the current i ch ( θ ) produced by the current generator 142 is proportional to the sensed input voltage : i ch ( θ )= g m k p ( v pk sin θ ). as in the controller 102 a , the capacitor c t is charged by the current generator 142 and discharged by the switched resistor r t in the controller 102 b . also in this controller 102 b the connection of the input voltage v c is unchanged from the control voltage v c of the controller 102 a . similar to the controller 102 a , the resistor r t is connected in parallel to the capacitor c t by the switch 143 only when the signal q is high , i . e . during the on - time of the power switch m . at this point it is clear that a third possible embodiment would have the current generator 142 , resistor r t , switch 143 , and capacitor c t connected to the multiplier 140 input where the control voltage v c is applied , with the current i ch ( θ ) of current generator 142 proportional to the control voltage v c . this will be taken for granted and will not be further considered . fig1 illustrates the waveforms of the circuit of fig9 . on the left - hand side are the waveforms on a switching period time scale , on the right - hand side the waveforms on a line cycle time scale . fig1 shows another embodiment of a flyback converter 100 c , using an existing pfc controller 102 c , such as the l6561 available from stmicroelectronics . in this embodiment , a shaper circuit 120 c is implemented with a small - signal mosfet ma , its gate resistor rg , the capacitor c t and the resistor rb . a small - signal bjt is also considered for the switch , in place of the small - signal mosfet . the mosfet ma is driven by the gate driver gd of the power switch m , thus connecting the lower resistor rb of the divider ra - rb to ground during the on - time of the power switch m . since the input voltage is much larger than the voltage on pin mult for most of the line cycle , resistor ra performs as the current generator , producing current i ch ( θ ) as : it is a common practice to have a bypass capacitor connected between pins mult and gnd to reduce noise pick - up in a sensitive point such as the multiplier input . the very same capacitor can serve as the capacitor c t in fig1 . the value of the capacitor c t will preferably be such that t ( θ )& lt ;& lt ; rb c t & lt ;& lt ; 1 / f l is fulfilled under all operating conditions . fig1 and 13 show computer simulated timing diagrams for the circuit of fig7 . these diagrams show a very low distortion level of the input current ( around 1 % at v in = 90 vac , around 3 . 5 % at v in = 264 vac ), due to the input emi filter and the nonidealities considered both in the controller 102 a and the power elements transformer 108 , bridge rectifier 104 , and power transistor m . fig1 shows an oscilloscope picture with some waveforms taken with the flyback converter 30 of fig1 . note the shape of the input current ( green trace ), which is a bit more rounded than , a sinusoid @ 110 vac , while it is more heavily distorted at 230 vac . fig1 shows the same waveforms as in fig1 on the same controller 38 of fig1 with the addition of the external components switch ma and gate resistor r g of fig1 . the shape of the input current ( the green trace ) is almost perfectly sinusoidal both at 110 vac and 230 vac . these results are confirmed by the measurements summarized in fig1 , which shows a comparison of the values of thd of the input current and the pf in the original and the modified board . the improvement offered by the novel method over the prior art one is dramatic , with a thd less than 4 % over the entire input voltage range . the various embodiments described above can be combined to provide further embodiments . these and other changes can be made to the embodiments in light of the above - detailed description . in general , in the following claims , the terms used should not be construed to limit the claims to the specific embodiments disclosed in the specification and the claims , but should be construed to include all possible embodiments along with the full scope of equivalents to which such claims are entitled . accordingly , the claims are not limited by the disclosure .