referring now to the figures of the drawing in detail and first , particularly , to fig1 thereof , there is shown a prior art led 1 for illustrating the initial problem . the semiconductor element 2 of the led contains , as is customary for leds in the infrared , red or yellow spectral region , a gaas substrate and an active layer 14 , for example , a structure with a simple pn - type junction , a quantum well structure or a multiple quantum well structure . current is impressed into the active layer 14 via an n - side contact and a p - side contact ( not illustrated ). the p - side contact is more critical in terms of the generation of waste heat because of the higher specific resistance than the n - side contact . in the led 1 , the p - side contact has a metallic contact pad 18 and a current widening layer 16 for homogeneously broadening the current density over the area of the active layer 14 formed as a pn - type junction . waste heat , for example , as a result of non - radiating recombination processes or as a result of ohmic losses , is produced predominantly in the region of the pn - type junction 14 and of the p - side contact 16 , 18 at the front side 15 of the led chip 2 . for conducting away heat , the led chip 2 is , inter alia , applied with a conductive adhesive 4 to a carrier 20 of an led housing ( not illustrated in more detail ). the conductive adhesive brings about both a thermal connection and an electrical connection of the led chip 2 and carrier 20 . as the bonded rear side 13 of the chip 2 is essentially planar , during the bonding , a continuous layer 4 of conductive adhesive which is uniform , apart from surface roughnesses , is typically produced with a thickness d 2 in the region of 5 μm to 10 μm between the chip and carrier . outside the chip 2 , thicker edge regions 3 are produced as a result of adhesive flowing out during the connection process . as the main heat sources are located near the front side 15 of the led chip 2 , the heat must cross virtually the entire thickness d 1 of the chip 2 and the layer of adhesive of thickness d 2 before it flows away into the carrier 20 . [ 0040 ] fig2 shows an equivalent circuit diagram of the thermal resistance of the configuration shown in fig1 . the reference symbol 60 designates the thermal resistance r th ( sc ) of the semiconductor element 2 , which is obtained essentially using : r th ( sc )= d 1 /( λ gaas * a ), λ gaas = 46 w /( m * k ) representing the thermal conductivity of the gaas substrate , and a representing the cross - sectional area of the substrate perpendicular to the flow of heat . the reference symbol 62 designates the thermal resistance r th ( adhesive ) of the layer 4 of conductive adhesive , which is given by the thermal conductivity of the conductive adhesive λ adhesive having a value in the region of 2 w /( m * k ), and , for example , a value of 1 . 8 w /( m * k ) for a typical conductive adhesive . the proportion of the thermal resistance of the metallization of the rear side of the chip with respect to the thermal resistance ( reference symbol 64 ) is small compared with the thermal resistances 60 and 62 , and can therefore be ignored , as is indicated in fig2 by the dashed lines . as the thermal resistance of the conductive adhesive is smaller , by a factor of approximately 20 , than that of the semiconductor material , the conductive adhesive layer contributes appreciably , despite its low thickness , to the overall thermal resistance : given a thickness of the semiconductor element of 220 μm and an area of 300 × 300 μm 2 , an overall thermal resistance of r overall ( sdt )= 85 k / w is obtained . the overall thermal resistance is made up of a proportion of the semiconductor element 2 of r th ( sc )= 54 k / w , and a proportion of the conductive adhesive layer 4 of r th ( adhesive )= 31 k / w . [ 0047 ] fig3 shows an exemplary embodiment of a semiconductor component , specifically an led designated generally by 10 . functionally identical elements are provided here with the same reference symbols as in fig1 and are not explained again . a number of recesses 22 are provided in the semiconductor element 12 of the led 10 from the rear side 13 — only three of these recesses are shown schematically in the illustration in fig3 . in the exemplary embodiment , the recesses 22 are arranged in the form of a regular rectangular grid which reflects the four - fold symmetry of the rectangular led chip 12 . the recesses 22 are provided with a degree of occupancy of 50 %, that is to say the entire output surface of the recesses 22 on the rear side 13 takes up a proportion of 50 % of the entire area of the rear side 13 . from the rear side 13 , the recesses extend into the semiconductor element 12 to a depth d . they divide the semiconductor element 12 into a region without patterning having a thickness d 1 − d and into a patterned region of thickness d . in the exemplary embodiment it was found that the conductive adhesive layer has a thickness of approximately 5 μm when a semiconductor element is bonded without recesses . therefore , with a degree of occupancy of 50 % a value of d = 10 μm was selected for the depth of the recesses . with this depth , the square recesses 22 can accommodate in their interior ( reference symbol 34 ) essentially the entire volume of conductive adhesive that was arranged between the led chip 2 and the carrier 20 as a conductive adhesive layer 4 with the conventional design in fig1 . only one comparatively thin continuous conductive adhesive layer 32 of thickness d 3 remains between the rear side 13 of the semiconductor element and the front side of the carrier 20 . the thickness d 3 here can be in the order of magnitude of between approximately 0 . 01 μm to 1 μm , and is preferably between approximately 0 . 05 μm and approximately 0 . 25 μm . this configuration can be described by the equivalent circuit diagram for the thermal resistance that is given in fig4 . here , in a way analogous to the representation in fig2 the reference symbol 70 designates the thermal resistance r th ( unpatterned ) of the unpatterned part of the semiconductor element 12 , r th ( unpatterned )=( d 1 − d )/( λ gaas * a ). the reference symbol 72 designates the thermal resistance r th ( struct : hl ) of the structured part of the semiconductor element 12 , given by r th ( struct : hl )= d /( λ gaas * b * a ), where b represents the degree of occupancy . reference symbol 74 characterizes the thermal resistance r th ( struct : adhesive ) of the conductive adhesive 34 which is accommodated in the recesses , with : r th ( struct : adhesive )= d /( λ adhesive *( 1 − b )* a ). reference symbol 76 finally designates the thermal resistance of the thin continuous conductive adhesive layer : in accordance with the selected geometry , the flow of heat flows in parallel through the patterned part of the substrate and the adhesive accommodated in the recesses so that the thermal resistance for this section is , as shown in the equivalent circuit diagram , given by parallel connection of the thermal resistances 72 and 74 . the thermal resistances of the unpatterned part of the substrate 70 and of the continuous conductive adhesive layer 76 are in series with respect to this , as is indicated by the series connection in fig4 . according to the invention , for the structure shown in fig3 with a thickness of the semiconductor element 12 of d 1 = 220 μm , an area of 300 × 300 μm 2 , an arrangement of the recesses with a degree of occupancy of 50 %, that is to say b = 0 . 5 and a depth of d = 10 μm , and a thickness of the remaining continuous conductive adhesive layer of d 3 = 0 . 1 μm , the overall thermal resistance that is obtained is : r overall ( inv )= r th ( unpatterned )+ 1 /[ 1 / r th ( struct : hl )+ 1 / r th ( struct : adhesive )]+ r th ( adhesive ). using the relationships stated , a thermal resistance of r overall ( inv )= 57 k / w is obtained . in comparison with the value of a conventional unpatterned led chip of r overall ( sdt )= 85 k / w , this value is considerably reduced , to almost the thermal resistance r th ( sc ) of the semiconductor element alone , which was determined above as 54 k / w . this means that , by means of the above - described patterning of the led chip on its rear side (= mounting side toward the carrier ), the proportion of the overall thermal resistance of the junction between the active layer and the carrier which originates from the conductive adhesive is reduced from the abovementioned value of 31 k / w to approximately 3 k / w , that is to say by approximately 90 %. [ 0059 ] fig5 represents the profile of the overall thermal resistance r ges as a function of the depth of the recesses for the structure shown in fig3 with a constant degree of occupancy of b = 0 . 5 . the reference symbol 80 indicates that the value of the overall resistance of the semiconductor element and the conductive adhesive without using patterning is 85 k / w . the reference symbol 82 indicates the lower limit — the thermal resistance of the semiconductor element 12 alone . here , the simulation is based on the assumption that the overall volume of the adhesive remains constant below the semiconductor element 12 . that is to say that , when the led chip is inserted into the adhesive , the amount of adhesive which is forced out to the side is not more or less than in a conventional led without patterning . as long as sufficient adhesive is present between the led chip and the carrier , in the present case for d & lt ; 10 μm , a continuous adhesive layer of the thickness d 3 = d 2 − b * d is assumed . for deeper structures for which d 3 would become zero or negative , a constant thickness of the remaining continuous adhesive layer of d 3 = 0 . 1 μm is assumed . the profile 84 of the overall thermal resistance is then broken down into two parts . starting from r th = 85 k / w , the thermal resistance initially decreases as the structure depth increases , until at approximately d = 10 μm almost the entire volume of the adhesive is accommodated in the depressions in the patterning ( reference symbol 86 ). the thermal resistance then assumes the abovementioned value of approximately 57 k / w , just above the thermal resistance of the element without any conductive adhesive . for still greater depths of patterning , the thermal resistance increases again as the heat has to flow via higher and higher gaas pillars without this effect being able to be compensated , as previously , by a further decrease in the thermal resistance of the continuous adhesive layer . this results in a minimum value of the overall thermal resistance , that is to say an optimum thickness for the selected degree of occupancy at a depth of patterning of approximately 10 μm . it is apparent that the optimum depth depends on the selected degree of occupancy . for example , the optimum depth with a degree of occupancy of 75 %, that is to say a proportion of the area of the recesses of 25 %, is approximately 20 μm . then , essentially the entire volume of adhesive is again accommodated by the recesses and only a thin residual layer remains between the semiconductor element and the carrier . on the basis of the preceding information , one of ordinary skill in the art can easily select , without departing from the basic idea of the invention , a suitable combination of degree of occupancy and patterning depth which both results in a low overall thermal resistance and fulfills the requirement for patterning processes ( no excessively deep recesses ) which can be carried out satisfactorily and easily , and the requirement in terms of mechanical stability ( no excessively small degree of occupancy ).