description will be made below of embodiments of the present invention . the present invention is not limited to the embodiments described below . fig1 shows a configuration diagram of a semiconductor device including an electronic circuit device according to one of the present embodiments . the semiconductor device includes a power supply line 101 , a reference potential line 102 , a third circuit 130 , a block 103 , a block 104 , and a switch controller 131 . the blocks 103 and 104 and the third circuit 130 are supplied with a power supply voltage from a power supply 100 via the power supply line 101 . the switch controller 131 is formed by a pmu ( power management unit ), for example . detailed description of the switch controller 131 will be made with reference to fig2 . the electronic circuit device includes a plurality of blocks . in the present embodiment , the electronic circuit device includes two blocks . the third circuit 130 is a logic circuit constantly connected to the power supply line 101 and the reference potential line 102 . meanwhile , the blocks 103 and 104 are connected to the power supply line 101 on the basis of switch control signals 132 a , 132 b , 132 c , and 132 d transmitted from the switch controller 131 . the block 103 includes a switch 110 , a first circuit 111 , a switch 112 , and a capacitive element 113 . the switch 110 turns on and off the connection between the first circuit 111 and the power supply line 101 . the switch 112 turns on and off the connection between the capacitive element 113 and the power supply line 101 . the switches 110 and 112 are controlled by switch control signals 132 a and 132 b , respectively , which are output from the switch controller 131 . the capacitive element 113 is for stabilizing the level of the power supply voltage supplied to the first circuit 111 . the block 104 includes a switch 120 , a second circuit 121 , a switch 122 , and a capacitive element 123 . the switch 120 turns on and off the connection between the second circuit 121 and the power supply line 101 . the switch 122 turns on and off the connection between the capacitive element 123 and the power supply line 101 . the switches 120 and 122 are controlled by switch control signals 132 c and 132 d , respectively , which are output from the switch controller 131 . the capacitive element 123 is for stabilizing the level of the power supply voltage supplied to the second circuit 121 . the switch controller 131 outputs the switch control signals 132 a , 132 b , 132 c , and 132 d on the basis of a state transition signal 133 which determines the next operational state of each of the blocks . the state transition signal 133 is a signal transmitted from a not - illustrated microcomputer . on the basis of the state transition signal 133 , the switch controller 131 determines which block is to be transited to which operation mode . the switch controller 131 transmits to each of the switches the switch control signals 132 a , 132 b , 132 c , and 132 d according to the determined operation mode . the switches 112 and 122 are provided to prevent current consumption by the leakage current of the capacitive elements 113 and 123 . therefore , the off - state leakage current of each of the switches 112 and 122 needs to be less than the leakage current of the corresponding one of the capacitive elements 113 and 123 . when each of the capacitive elements 113 and 123 is formed by a mos capacitor , a large capacitance value can be ensured by reduction in thickness of an oxide film formed between the gate and the drain of the mos capacitor . meanwhile , the reduction in thickness of the oxide film results in an increase in the leakage current . therefore , when each of the switches 112 and 122 is formed by a mos transistor , for example , if the oxide film of each of the switches 112 and 122 is made thickener than the oxide film of the corresponding one of the capacitive elements 113 and 123 , the off - state leakage current of the switch can be made less than the leakage current of the capacitive element . according to the present embodiment , therefore , the capacitive element 113 or 123 has been charged when the first circuit 111 or the second circuit 121 is connected to the power supply 100 . as a result , a voltage drop occurring when the first circuit 111 or the second circuit 121 is connected to the power supply 100 can be prevented . accordingly , the first circuit 111 or the second circuit 121 can be activated at high speed . fig2 is a functional block diagram for explaining the switch controller 131 . the switch controller 131 is constituted by a signal output unit 210 , a mode determination unit 211 , a state storage unit 212 , a decoder 213 , a time measurement unit 214 , a comparator 216 , a clock source 222 , and a time storage unit 218 . the switch controller 131 receives the state transition signal 133 from an external device of a microcomputer 200 , and starts a process of determining the next operation mode . the switch controller 131 determines the next operation mode on the basis of the state transition signal 133 input therein , and outputs the result of the determination as the switch control signals 132 a , 132 b , 132 c , and 132 d . the state storage unit 212 stores the current operation mode . the mode determination unit 211 stores a correspondence table of the next operation mode determined by the combination of the current operation mode and the state transition signal 133 . with the use of the state transition signal 133 input from the microcomputer 200 and the current operation mode stored in the state storage unit 212 , and on the basis of the correspondence table described later , the mode determination unit 211 performs a process of determining the next operation mode . the next operation mode determined by the mode determination unit 211 is stored in the state storage unit 212 . each operation mode is defined as a binary number including a plurality of bits . further , if the operation mode is stored in the state storage unit 212 as a nonvolatile memory , and if the operation mode is used at the time of activation , the state of the switch controller 131 at the time of activation can be determined . the state storage unit 212 stores the current operation mode and the next operation mode . on the basis of the two operation modes , the time storage unit 218 described later determines the number of counts output to the comparator 216 . the state storage unit 212 outputs an operation mode signal of the next operation mode to the decoder 213 and the time storage unit 218 . the decoder 213 decodes the input operation mode signal into an operation mode signal for each of the blocks 103 and 104 , and outputs the decoded operation mode signal to the signal output unit 210 . the signal output unit 210 decodes the input operation mode signal into the switch control signals 132 a , 132 b , 132 c , and 132 d , and outputs the decoded switch control signals 132 a , 132 b , 132 c , and 132 d . further , upon receipt of the operation mode signal , the signal output unit 210 outputs a count start signal 230 . the time storage unit 218 stores the time required to charge each of the capacitive elements 113 and 123 and so forth , as time information in the number of counts of a clock signal , for example . the number of counts is determined on the basis of the clock period of the clock source 222 . the time storage unit 218 further stores a correspondence table of the change of the operation mode and the capacitive element to be charged according to the change . the time storage unit 218 outputs to the comparator 216 the number of counts corresponding to the current operation mode and the next operation mode input therein . the relationship between the number of counts stored in the time storage unit 218 and the capacitance value of the capacitive element is defined as follows , for example . if the capacitance value of the capacitive element is represented as c , and if the on - resistance value at the turn - on of the switch which connects the capacitive element to the power supply is represented as r , a charging time t for charging the capacitive element is determined as t = c × r . the time t is time constant . therefore , if the clock period of the clock source 222 supplied to a counter is represented as t , the number of counts n corresponding to the charging time t of the capacitive element can be obtained as n = t ÷ t . the time measurement unit 214 measures the time elapsed since the receipt of the count start signal 230 , and records the result of the measurement as time information . the time measurement unit 214 can be formed by a counter , for example . the time measurement unit 214 receives the count start signal 230 output from the signal output unit 210 , starts counting on the basis of the clock signal output from the clock source 222 and having the clock period t , and outputs to the comparator 216 the number of counts accumulated since the start of the counting . the comparator 216 compares the number of counts output from the time measurement unit 214 with the number of counts output from the time storage unit 218 . then , if the two values become equal , the comparator 216 outputs an activation signal 220 . the activation signal 220 is a signal for notifying the other devices and so forth that the power supply to the first circuit 111 , the second circuit 121 , and so forth has been started . the signal can notify a clock supply unit that each of the blocks has been activated , for example , to thereby start the supply of the clock signal to the target block . the output timing of the activation signal 220 is not limited to the timing at which the number of counts output from the time measurement unit 214 becomes equal to the number of counts output from the time storage unit 218 . thus , the output timing may be set to the timing at which the difference between the two numbers of counts becomes a predetermined value . each of fig3 a to 3c represents the relationship between the operation mode and the switch control signal 132 a , 132 b , 132 c , and 132 d . fig3 a represents the relationship between the operation mode of the semiconductor device and the operation mode of each of the blocks . fig3 b represents the relationship between the operation mode of the block 103 and the operational state of each of the switches included in the block , and fig3 c represents the relationship between the operation mode of the block 104 and the operational state of each of the switches included in the block . the table of fig3 a is stored in the decoder 213 . the decoder 213 decodes the input signal in accordance with fig3 a . a column c represents the operation mode signals input to the decoder 213 . columns a and b represent the operation mode signals of the blocks 103 and 104 , respectively . in fig3 a , the operation mode on represents the state in which the switch connected in series to the circuit and the switch connected in series to the capacitive element are both in the on state . the operation mode sleep represents the state in which only the switch connected in series to the capacitive element is in the on state . the operation mode off represents the state in which the two switches are both in the off state . the tables of fig3 b and 3c are stored in the signal output unit 210 . on the basis of the decoded signal output from the decoder 213 , the signal output unit 210 outputs the switch control signals 132 a , 132 b , 132 c , and 132 d . columns a and b represent the operation mode signals input to the signal output unit 210 for the blocks 103 and 104 , respectively . columns 110 , 112 , 120 , and 122 represent the switch control signals 132 a , 132 b , 132 c , and 132 d to be transmitted to the switches 110 , 112 , 120 , and 122 , respectively . in the present embodiment , “ 1 ” represents the on state , and “ 0 ” represents the off state . for example , if the operation mode stored in the state storage unit 212 is c 1 , the decoder 213 decodes the operation mode signal c 1 to set both of the blocks 103 and 104 in the operation mode on . the decoded operation mode signal is output to the signal output unit 210 . on the basis of the input operation mode signal and fig3 b and 3c , the signal output unit 210 outputs the switch control signals 132 a , 132 b , 132 c , and 132 d corresponding to the operation mode on of each of the blocks . specifically , the signal output unit 210 outputs to each of the switches 110 , 112 , 120 , and 122 the switch control signal 132 a , 132 b , 132 c , and 132 d having a logical value “ 1 ” for turning on all of the switches . fig4 is a state transition diagram illustrating a state transition in accordance with the current operation mode and the input state transition signal 133 . the condition of the state transition of fig4 is stored in the mode determination unit 211 of fig2 . in the drawing , c 1 to c 5 represent the operation modes , which are equal to the operation modes of the column c in fig3 a . if the number of transition paths is increased , the processing by the mode determination unit 211 becomes complicated . however , if the degree of freedom of mode transition is increased , a less redundant switch control can be performed . a two - digit number accompanying each of arrows located between the respective operation modes represents the state transition signal 133 input from the microcomputer 200 . for example , if the current operation mode is c 3 , and if the input state transition signal 133 is “ 11 ,” the current operation mode c 3 transits to the operation mode c 2 . if the input state transition signal 133 is “ 00 ,” the current operation mode c 3 transits to the operation mode c 5 . if the input state transition signal 133 is “ 10 ,” the current operation mode c 3 transits to the operation mode c 4 . in the above - described manner , the next operation mode can be determined on the basis of the current operation mode and the input state transition signal 133 . the operation modes c 1 to c 5 represent the operation mode of the entire semiconductor device . meanwhile , the operation mode of each of the blocks can be defined on the basis of fig3 a . for example , if the operation mode transits from c 1 to c 2 , the operation mode of the block 103 transits from on to sleep . similarly , the operation mode of the block 104 also transits from on to sleep . meanwhile , if the operation mode transits from c 2 to c 3 , the operation mode of the block 103 is unchanged , and the operation mode of the block 104 transits from sleep to off . as described above , a plurality of operation modes are provided for the entire semiconductor device , and each of the operation modes is assigned with the operation modes of the respective blocks . accordingly , it is possible to separately control the operation modes of the respective blocks while reducing the capacity required to store the operation modes . fig5 is a flowchart illustrating a transition process of the operation mode performed in each of the blocks on the basis of the state transition signals 133 of fig4 . the operation modes on , sleep , and off of fig5 are the same as the operation modes on , sleep , and off of fig3 a to 3c . the blocks 103 and 104 perform the same operation on the basis of the flowchart of fig5 . herein , description will be made of the state transition process of the block 103 , as an example . at step s 50 , the switch controller 131 performs a process of determining the next operation mode on the basis of the input state transition signal 133 . it is now assumed that the state storage unit 212 stores the information that the current operation mode is c 5 . further , it is assumed that “ 10 ” has been input as the state transition signal 133 . in this case , on the basis of the state transition signal 133 and the current operation mode c 5 , the mode determination unit 211 determines from the state transition diagram of fig4 that the next operation mode is c 1 . the operation mode c 1 is written in the state storage unit 212 , and the switch controller 131 performs the process of step s 52 . at step s 52 , on the basis of the operation mode c 1 stored in the state storage unit 212 and the truth value table of fig3 a , the decoder 213 outputs a mode signal to the signal output unit 210 to set the block 103 in the operation mode on . on the basis of fig3 b , the signal output unit 210 outputs a switch control signal for turning on the switch 110 connected to the first circuit 111 and the switch 112 connected to the capacitive element 113 . at step s 54 , the signal output unit 210 outputs a switch control signal to the time measurement unit 214 to start counting the time until the charging of the capacitive element 113 is completed . at step s 56 , the comparator 216 compares the number of counts output from the time measurement unit 214 with the value stored in the time storage unit 218 . if the two values become equal , the comparator 216 completes the counting process and outputs the activation signal 220 at step s 58 . thereby , the block 103 is set in the operation mode on . meanwhile , if “ 11 ” is input as the state transition signal 133 , the mode determination unit 211 determines from the state transition diagram of fig4 that the next operation mode is c 3 . the operation mode c 3 is written in the state storage unit 212 , and the switch controller 131 performs the process of step s 80 . at step s 80 , on the basis of the operation mode c 3 stored in the state storage unit 212 , the decoder 213 outputs a mode signal to the signal output unit 210 to set the block 103 in the operation mode sleep . the signal output unit 210 performs a process of outputting a signal for turning on the switch 112 connected to the capacitive element 113 . at step s 82 , the signal output unit 210 outputs a signal to the time measurement unit 214 to start counting the time until the charging of the capacitive element 113 is completed . at step s 84 , the comparator 216 compares the number of counts output from the time measurement unit 214 with the value stored in the time storage unit 218 . then , if the two values become equal , the comparator 216 completes the counting process . the comparator 216 then outputs , as the activation signal 220 , the information that the charging of the capacitive element 113 has been completed . thereby , the block 103 is set in the operation mode sleep . at step s 60 , the mode determination unit 211 remains in the standby state until the input of the state transition signal 133 . at step s 62 , upon input of the state transition signal 133 to the mode determination unit 211 , the comparator 216 outputs , as the activation signal 220 , the information that the block 103 is no longer in the operation mode on . at step s 64 , the mode determination unit 211 determines the next operation mode on the basis of the input state transition signal 133 and the current operation mode stored in the state storage unit 212 . if the state transition signal 133 is “ 00 ,” the mode determination unit 211 determines that the next operation mode is c 5 . then , the mode determination unit 211 outputs the operation mode c 5 to the state storage unit 212 . at step s 66 , the switch controller 131 outputs a switch control signal for turning off the switch 110 connected to the first circuit 111 and the switch 112 connected to the capacitive element 113 . thereby , the block 103 is set in the operation mode off . meanwhile , at step s 64 , if “ 01 ” is input as the state transition signal 133 , the mode determination unit 211 determines the next operation mode as c 2 . at step s 68 , the mode determination unit 211 outputs the operation mode c 2 signal to the state storage unit 212 . further , at step s 68 , the switch controller 131 outputs a signal for turning off the switch 110 connected to the first circuit 111 . thereby , the operation mode of the block 103 is set in sleep . at step s 70 , the mode determination unit 211 remains in the standby state until the input of the state transition signal 133 . the state storage unit 212 stores the operation mode c 2 . if the state transition signal 133 is “ 11 ,” the mode determination unit 211 determines that the next operation mode is c 1 . at step s 70 , the mode determination unit 211 determines the next operation mode as c 1 , and outputs the operation mode c 1 to the state storage unit 212 . then , the switch controller 131 proceeds to the process of step s 74 . at step s 74 , the signal output unit 210 outputs a switch control signal for turning on the switch 110 connected to the first circuit 111 . at step s 76 , the signal output unit 210 instructs the time measurement unit 214 to start counting to determine whether the parasitic capacitance of the first circuit 111 has been charged . at step s 78 , on the basis of the number of counts output from the time measurement unit 214 and the number of counts output from the time storage unit 218 , the comparator 216 determines whether the parasitic capacitance of the first circuit 111 has been charged . at step s 58 , the comparator 216 outputs the activation signal 220 . thereby , the operation mode of the block 103 is set in on . meanwhile , if “ 01 ” is input as the state transition signal 133 at step s 70 , the mode determination unit 211 determines the next operation mode as c 3 . thus , the operation mode of the block 103 remains in sleep . if “ 00 ” is further input as the state transition signal 133 , the mode determination unit 211 determines the next operation mode as c 5 . then , the switch controller 131 proceeds to the process of step s 72 . at step s 72 , the signal output unit 210 outputs a switch control signal for turning off the switch 112 . thereby , the operation mode of the block 103 is set in off . if a switch connected to a capacitive element is turned off , the capacitive element maintains the charged state for a short time . after the lapse of a long time , however , the capacitive element is discharged due to a parasitic resistance of the capacitive element and so forth . thus , the operation mode sleep is provided in the transition of the operation mode from off to on . thereby , the capacitive element connected in parallel to a circuit is recharged before the start of the power supply to the circuit . accordingly , it is possible to suppress a drop in the power supply voltage occurring when the circuit is connected to the power supply , and to activate the circuit at high speed . fig6 is a state transition diagram illustrating a state transition in accordance with the current operation mode and the input state transition signal 133 . in the drawing , c 1 to c 5 represent the operation modes , which are equal to the operation modes of the semiconductor device in fig3 a . the present example includes a smaller number of transition paths than in the state transition diagram of fig4 . thus , the circuit operation becomes redundant . however , the circuit size of the switch controller 131 can be reduced . a two - digit number accompanying each of arrows located between the respective operation modes represents the input state transition signal 133 . for example , if the current operation mode is c 3 , and if the input state transition signal 133 is “ 11 ,” the current operation mode c 3 transits to the operation mode c 2 . if the input state transition signal 133 is “ 00 ,” the current operation mode c 3 transits to the operation mode c 5 . if the input state transition signal 133 is “ 10 ,” the current operation mode c 3 transits to the operation mode c 4 . in the above - described manner , the next operation mode can be determined on the basis of the current operation mode and the input state transition signal 133 . the operation modes c 1 to c 5 represent the operation mode of the entire semiconductor device . meanwhile , the operation mode of each of the blocks can be defined on the basis of fig3 a . for example , if the operation mode transits from c 1 to c 2 , the operation mode of the block 103 transits from on to sleep . similarly , the operation mode of the block 104 also transits from on to sleep . meanwhile , if the operation mode transits from c 2 to c 3 , the operation mode of the block 103 is unchanged , and the operation mode of the block 104 transits from sleep to off . as described above , a plurality of operation modes are provided for the entire semiconductor device , and each of the operation modes is assigned with the operation modes of the respective blocks . accordingly , the operation modes of the respective blocks can be separately controlled . fig7 is a flowchart illustrating a transition process of the operation mode performed in each of the blocks on the basis of the state transition signals 133 of fig6 . the operation modes on , sleep , and off of fig7 are the same as the operation modes on , sleep , and off of fig3 a to 3c . the blocks 103 and 104 perform the same operation on the basis of the flowchart of fig7 . herein , description will be made of the state transition process of the block 103 , as an example . at step s 10 , the mode determination unit 211 remains in the standby state until the input of the state transition signal 133 . it is now assumed that the state storage unit 212 stores the operation mode c 5 . at step s 10 , on the basis of “ 11 ” input as the state transition signal 133 and the operation mode c 5 stored in the state storage unit 212 , the mode determination unit 211 determines that the next operation mode is c 3 . at step s 12 , the signal output unit 210 outputs a switch control signal 132 b for turning on the switch 112 . at step s 14 , the signal output unit 210 outputs a signal for instructing the time measurement unit 214 to start counting . at step s 16 , the comparator 216 compares the number of counts output from the time measurement unit 214 with the number of counts output from the time storage unit 218 . then , if the two values become equal , the comparator 216 outputs the activation signal 220 . at step s 18 , the mode determination unit 211 is in the standby state . the operation mode stored in the state storage unit 212 is c 3 . if “ 00 ” is input as the state transition signal 133 , the mode determination unit 211 determines the next operation mode as c 5 . then , the mode determination unit 211 stores the operation mode c 5 in the state storage unit 212 , and the procedure proceeds to step s 20 . meanwhile , if “ 10 ” is input , the mode determination unit 211 determines the next operation mode as c 4 . then , the mode determination unit 211 stores the operation mode c 4 in the state storage unit 212 , and the procedure proceeds to step s 22 . at step s 20 , the signal output unit 210 outputs a signal for turning off the switch 112 . at step s 22 , the signal output unit 210 outputs a switch control signal 132 a for turning on the switch 110 . at step s 24 , the signal output unit 210 outputs the count start signal 230 to the time measurement unit 214 . at step s 26 , the comparator 216 compares the number of counts output from the time measurement unit 214 with the time required to charge the parasitic capacitance of the first circuit 111 , which is stored in the time storage unit 218 . then , if the two values become equal , the comparator 216 outputs the activation signal 220 at step s 28 . at step s 30 , the mode determination unit 211 is in the standby state . the state storage unit 212 stores c 4 as the operation mode . if “ 00 ” is input as the state transition signal 133 , the mode determination unit 211 determines the next operation mode as c 3 . then , the mode determination unit 211 stores the operation mode c 3 in the state storage unit 212 . at step s 32 , the comparator 216 outputs , as the activation signal 220 , the information that the first circuit 111 is to be brought into the stopped state . at step s 34 , the signal output unit 210 outputs a signal for turning off the switch 110 . if a switch connected to a capacitive element is turned off , the capacitive element maintains the charged state for a short time . after the lapse of a long time , however , the capacitive element is discharged due to a parasitic resistance of the capacitive element and so forth . thus , the operation mode sleep is provided in the transition of the operation mode from off to on . thereby , the capacitive element connected in parallel to a circuit is recharged before the start of the power supply to the circuit . accordingly , it is possible to suppress a drop in the power supply voltage occurring when the circuit is connected to the power supply , and to activate the circuit at high speed .