the contents of the present invention are described in details through specific embodiments with reference to the figures . the reference numerals mentioned in the specification correspond to equivalent reference numerals in the figures . as shown in fig2 , it is an overheated protection circuitry 10 for a central processing unit ( cpu ) 11 . the overheated protection circuitry 10 is used to switch off a power supply 12 of the cpu 11 when the working temperature of the cpu 11 is higher than a first preset temperature or a second preset temperature . the power supply 12 is used to supply electrical power to the cpu 11 and other circuits . in addition , the second preset temperature is higher than the first preset temperature . in practice , the second preset temperature is set 125 ° c . and the first preset temperature is set 0100 ° c . the cpu 11 has a thermal sensor ( not shown ) for detecting the working temperature of the cpu 11 . when the working temperature of the cpu 11 is higher than the second preset temperature , the cpu 11 sends a first abnormal signal to a chipset 17 . the chipset 17 sends out a first switch - off signal to a signal processing module 15 , and then the signal processing module 15 switches off the power supply 12 after receiving the first abnormal signal in practice , the first switch - off signal may be a level signal . for example , high level represents the state of switch - off and low level represents the state of switch - on . therefore , the power supply 17 is switched off by the signal processing module when receiving the first switch - off signal and the first switch - off signal is in the high level . on the contrary , high level may represent the state of switch - on and low level may represent the state of switch - off . hence , the power supply 17 switches off when receiving the first switch - off signal and the first switch - off signal is in the low level . the overheated protection circuitry 10 for a cpu of the present invention comprises a thermal module 13 , a control module 14 , and a signal processing module 15 . the thermal module 13 is connected with the thermal sensor of the cpu 11 for detecting the working temperature of the cpu 11 . the cpu 11 generates the first abnormal signal to the control module 14 when the working temperature of the cpu 11 is higher than the first preset temperature . in addition , the control module 14 is connected with the cpu 11 and the thermal module 13 , and the thermal module 13 sends out a second abnormal signal when the working temperature of the cpu 11 is higher than the first preset temperature ; therefore , the control module 14 is used to receive the first and second abnormal signals , and when receives one of the first and second abnormal signals , the control module 14 sends out a second switch - off signal to the signal processing module 15 . the signal processing module 15 switches off the power supply 12 when receiving the first switch - off signal or the second switch - off signal . the above - mentioned first and second abnormal signals may be a level signal in practice . in other word , when the working temperature of cpu is normal , the abnormal signal is a low level signal , for instance 0v . on the other hand , when the working temperature of cpu is abnormal , the abnormal signal is a high level signal , for instance 3 . 3v or 1v . therefore , the control module 14 determines the level of the received first and second abnormal signals . if one of the first and second abnormal signals is in high level , the control module 14 generates the second switch - off signal provided to the signal processing module 15 . the signal processing module 15 may an or gate . if one of the first and second switch - off signals is in high level , the power supply switches off as shown in fig3 , it is the control module 14 of a first embodiment of the present invention . in the figure , it can be seen that the control module 14 comprises a first determining circuit 141 , a second determining circuit 142 , and a signal conversion module 143 . the first determining circuit 141 is connected to the cpu 11 for receiving the first abnormal signal and outputs a first determining signal to the signal conversion module 143 . the second determining circuit 142 is connected to the thermal module 13 and used for receiving the second abnormal signal . the second determining circuit 142 outputs a second determining signal to the signal conversion module 143 when receiving the second abnormal signal . in addition , except receiving the first and second determining signals , the signal conversion module 143 further outputs the second switch - off signal to the signal processing module 15 when receiving one of the first and second determining signals . here , the determining signal may be a level signal in practice , and the level of the first determining signal may be the same as that of the second determining signal so as to convert the first and second determining signals to the second switch - off signal when the signal conversion module 143 is an or gate . besides , the first determining circuit 141 and the second determining circuit 142 may not be the same because the levels of the first and second abnormal signals are not the same . for instance , if the high level of the first abnormal signal is 1v but the high level of the second abnormal signal is 3 . 3v , the first determining circuit 141 and the second determining circuit 142 are not the same . however , it is to be noted that the level of the first and second determining signals must be the same in order to match up the conversion of the signal conversion module 143 . if the levels of the first and second determining signals are different , they need to be converted in the signal conversion module . as shown in fig4 , it is the control module 14 of a second embodiment of the present invention . in the figure , a voltage level adjusting circuit 144 receives a first abnormal signal sent by the cpu 1 . the voltage level adjusting circuit 144 adjusts the level of the first abnormal signal to be the same with the second abnormal signal and the adjusted first abnormal signal is connected with the second abnormal signal so as to generate a second switch - off signal ; therefore , in this embodiment , the signal conversion module 143 in the first embodiment can be omitted this embodiment may apply to the conditions when the level of the first abnormal signal outputted by the cpu 11 is 1v , the level of the second abnormal signal outputted by the thermal module 13 is 3 . 3v , and the second abnormal signal is an open drain pin which can generate an open drain signal . the voltage level adjusting circuit 144 can be used to adjust the level of the first abnormal signal , so that the level of the first abnormal signal , can be the same as that of the second abnormal signal , and the first and second abnormal signals can be connected to be the second switch - off signal . therefore , except the second determining circuit 142 can be omitted , the signal conversion module 143 can be omitted too . as shown in fig5 , it is a diagram of the circuit of the level adjusting circuit 144 of the present invention in the figure , it can be seen that through inputting level reference signal 1441 and the first abnormal signal sent by the cpu , then they are configured and adjusted by a transistor 1442 and a mosfet 1443 so as to obtain the potential level as same as that of the second abnormal signal which is then outputted to the signal processing module 15 . referring to fig2 the thermal module 13 further outputs a thermal signal corresponding to the working temperature of the cpu 11 to a micro processor 16 . after receiving the thermal signal the micro processor 16 converts the thermal signal into a temperature corresponding to the working temperature of the cpu 11 . when the temperature is higher than the first preset temperature , a third abnormal signal is sent to the chipset 17 . in addition , when receiving one of the first abnormal signal and third abnormal signal , the chipset 17 sends out the first switch - off signal to the power supply 12 . the chipset 17 may be a southbridge chip and the micro processor 16 is an embedded processor . the present invention being thus described , it will be obvious that the same may be varied in many ways . such variations are not to be regarded as a departure from the spirit and scope of the invention , and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims .