with reference first to fig1 a block diagram of a generic disk drive system 10 is shown , illustrating a general environment in which the invention may be practiced . the system 10 includes a stack of magnetic media disks 12 that are rotated by a spindle motor 14 and spindle driver circuit 16 . a plurality of data transducers , or heads , 18 are locatable along selectable radial tracks ( not ordinarily visible ) of respective ones of the disks 12 by a voice coil motor ( vcm ) 22 . as explained above , the radial tracks may contain magnetic states that contain information about the tracks , such as track identification data , location information , synchronization data , as well as user data , and so forth . the heads 18 typically are used both to record user data to and read user data back from the disks , as well as to detect signals that identify the tracks and sectors at which data is written , and to detect servo bursts that enable the heads to be properly laterally aligned with the tracks of the disks . the heads 18 also are used to initially write servo data to the disks 12 . analog electrical signals that are generated by the heads in response to the magnetic signals recorded on the disks are preamplified by a preamplifier 24 for delivery to read channel circuitry 26 . in addition , servo signals are detected and demodulated by one or more servo demodulator circuits 28 and processed by a digital signal processor ( dsp ) 30 to control the position of the heads 18 via the positioning driver circuit 32 . the servo data that is read and processed may be analog data that is interpreted by the dsp 30 for positioning the heads . a microcontroller 34 is typically provided to control the dsp 30 . an interface controller 36 is also provided to enable data to be passed to and from a host interface ( not shown ) in known manner . a data buffer memory 38 may be provided , if desired , to buffer data being written to and read from the disks 12 . as will become apparent below , according to the invention , when servo information is to be written to the disks 12 by an external servo writer 35 , shown in dashed lines , the write amplifiers within the preamplifier block 24 are configured to allow a low speed , low power mode of operation , as described below in conjunction with fig2 . thus , with reference now additionally to fig2 a circuit 40 is shown to provide both user write data and servo write data signals to the thin - film head 18 ( see fig1 ). the circuit 40 includes two main sections , a high - speed data writing section 44 and a low - speed , low power servo writing section 46 . the high - speed data writing section 44 and the low - speed , low power servo writing section 46 are essentially connected in parallel . therefore , one or the other section may be selectively actuated , for example , by signals on lines 52 from the servo writer , or other control circuit ( not shown ), to write data from the input terminals 48 and 50 to the head 18 , for ultimate transfer to the disks 12 . the high - speed circuit 44 includes npn transistors 54 - 57 and resistors 59 - 60 . the transistors 54 - 57 are driven in respective pairs to control the current through the head 18 to flow in one direction or the other under the control of the high - speed data path circuitry 62 in known manner . additionally , transistors 54 and 57 respectively control transistors 64 and 65 , connected between the supply line 68 and resistors 70 and 72 in an “ upper portion ” of the circuit 44 . resistor 59 is connected from the emitters of transistors 54 and 57 to vee , and resistors 74 and 75 are connected from the collectors of transistors 54 and 57 to the supply rail 68 . the high - speed data path circuitry 62 receives input signals on data lines 48 and 50 . thus , in normal data writing operation , depending upon the control signals applied by the high - speed data path circuitry 62 to the selected transistors 54 - 57 , a current path is set up in one of two directions . current flows either from the supply rail 68 , through transistor 64 , resistor 70 , head 18 , transistor 56 , and resistor 60 to vee , or from the supply rail 68 , through transistor 65 , resistor 72 , head 18 , transistor 55 , and resistor 60 to vee . on the other hand , when servo data is to be written to the disks of the drive , the external servo writer 35 operates to enable the low - speed low power data path 78 , and disable the high - speed data path 62 , via control signals on lines 52 . the low - speed section 46 shares the “ upper portion ” of the high - speed section 44 described above . more particularly , the transistors 64 - 65 , and the resistors 70 , 72 , and 74 - 75 are shared between both the high - and low - speed drivers . in addition , the low speed driver section 46 includes four npn transistors 80 - 83 having collectors connected in parallel with the collectors of transistors 54 - 57 . resistors 86 and 87 respectively connect the emitters of transistors 80 and 83 and the emitters of transistors 81 and 82 to a switch 89 , which connects them selectively either to ground or vee . the switch 89 is optional , and may not be necessary in some applications ; however , the use of the switch 89 enables the servo write power to be further reduced by providing a capability of operating with respect to a ground reference potential instead of a vee reference potential . the low - speed , low power data path circuitry 78 receives input signals on data lines 48 and 50 , which are shared with the high - speed data path circuitry 62 described above . thus , in servo information writing mode of operation , depending upon the control signals applied by the low - speed , low power data path circuitry 78 to the selected transistors 80 - 83 , a current path is set up in one of two directions . current flows either from the supply rail 68 , through transistor 64 , resistor 70 , head 18 , transistor 82 , and resistor 87 to ground or vee , or from the supply rail 68 , through transistor 65 , resistor 72 , head 18 transistor 81 , and resistor 87 to ground and vee . the write data may be externally supplied ( supply not shown ), in differential emitter - coupled - logic ( ecl ) format or pseudo emitter coupled logic ( pecl ) on input lines 48 and 50 . the differential ecl form is a digital signal and is supplied to both the high - and low - speed data path circuitry 62 and 78 , as described above . during normal write mode , the high - speed data path circuitry 62 is enabled and the “ lower write driver ” circuitry ( transistors 54 - 57 and resistors 59 - 60 ) is active . simultaneously , the low - speed , low power data path circuitry 78 is disabled , and , if used , the switch 89 is connected to the − vee position . on the other hand , during servo write mode of operation , many of the write heads 18 ( see fig1 ) are active to write data simultaneously . in this mode , therefore , a low power is desired . in this mode , the high - speed data path circuitry 62 is disabled , and the low - speed , low power data path circuitry 78 is enabled . the “ servo lower write driver ” circuitry ( transistors 80 - 83 and resistors 86 - 87 ) is active and , as mentioned , the shared “ upper driver ” circuitry ( transistors 64 - 65 and resistors 70 , 72 , and 74 - 75 ) is used . the “ lower write driver ” associated with the high speed data path circuitry 62 is disabled . the switch 89 , if used , may be switched to the gnd position for additional power savings . it should be noted that the sharing of the “ upper write driver ” circuitry ( transistors 64 - 65 and resistors 70 , 72 , and 74 - 75 ) is done in current mode . therefore , switches are not required in the high - speed data path . as a result , the normal write driver speed in servo information write mode is not compromised . however , the extra parasitic capacitance of the servo “ lower driver circuitry ” does add into the overall capacitance in normal data write mode of operation . it is believed , nonetheless , that these parasitic effects are negligible in most applications if the device sizes are properly chosen . it should also be noted that although a single circuit 40 is shown in fig3 in an actual implementation in a mass data storage device , a circuit correspondingly constructed to the circuit 40 may be provided for each head channel employed . thus , for example , if eight heads are used , the circuit 40 would be replicated eight times with each circuit 40 being used with each respective head . although the invention has been described and illustrated with a certain degree of particularity , it is understood that the present disclosure has been made only by way of example , and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention , as hereinafter claimed .