a predecoded counter is provided according to the invention . fig3 shows sequential states of a preferred predecoded counter . predecode and count are performed simultaneously . for comparison , fig4 shows sequential states of an ordinary shave - and - a - haircut ( two bit ) counter . the states are outputted to a predecoder , whose outputs are also shown . the preferred embodiment of a one - of - four predecoded counter 15 is detailed in fig5 . it includes : two dual - input master - slave d - type flip - flops 50 and 50 &# 39 ; with data inputs d0 , d1 , d0 &# 39 ;, and d1 &# 39 ;, presetting inputs s *, r *, s *&# 39 ;, and r *&# 39 ;, separate clock inputs clkm and clks *, and flip - flop outputs q , q *, q &# 39 ;, and q *&# 39 ;; and predecoder 51 with predecoded outputs p0 ( least significant ), p1 , p2 , and p3 ( most significant ). all of these elements are connected as shown in fig5 so that the flip - flops 50 and 50 &# 39 ; synchronously output directly to predecoder 51 , and feedback is taken from predecoded outputs p0 , p1 , p2 , and p3 in order to generate a next state . these elements preferably share a common semiconductor substrate . the operation of flip - flop 50 within a predecoded counter such as 15 is now summarized . the master stage is transparent when input clkm is low , and latches on clkm rising edge . the slave stage is transparent when clks * is high , and latches on clks * falling edge . because of the predecoded counter 15 feedback from outputs p0 - p2 to inputs d0 , d1 , d0 &# 39 ;, d1 &# 39 ;, flip - flops 50 and 50 &# 39 ; are not allowed to have both the master stage and the slave stage transparent at one time . to latch a new value into flip - flop 50 , clkm and clks * are simultaneously ( or almost simultaneously ) brought low and then high ( see fig6 lines 1 - 3 ). when at least one of d0 and d1 are high ( lines 2 and 3 ), a high output is latchable at q . when both d0 and d1 are low ( line 1 ), a low output is latchable at q . when flip - flop 50 is used in the preferred embodiment , d0 and d1 are never high at the same time because only one output of predecoder 51 is high at one time . to preset flip - flop 50 , one of s * and r * is brought low while clks * is low ( lines 4 and 5 ). r * and s * are both high for normal operation ( lines 1 - 3 ), but when s * goes low ( line 5 ) q asynchronously goes high , and when r * goes low ( line 4 ) q asynchronously goes low ( r * and s * low at the same time is a disallowed state ). q * is always the inverse of q . sequential states of the preferred embodiment are shown in fig7 . at time t1 in this figure , the embodiment is initialized to select p0 . clk is a signal placed on clkm and clks * simultaneously , for purposes of illustration . at each positive clk edge through times t2 - t5 the embodiment is shown predecodably counting through p1 , p2 , p3 , and p0 , respectively . at time t6 , the embodiment is preset to select p2 by bringing s * and r *&# 39 ; low . s * and r &# 39 ;* return high at time t7 but outputs p0 - p3 remain latched . at time t8 , predecoded counting resumes , beginning at selected state p2 . fig8 details the preferred embodiment used in a memory system . one - of - four predecoded counters 15a - 15d are synchronously cascaded , each predecoded counter 15 outputting to different levels in decode stage 13 , which selects one of 256 elements in array 14 , as shown . decode stage 13 is a tree decoder having four branching levels . clock clocks the master stage of predecoded counter 15d and slave stages of predecoded counters 15a - 15d . counters 15a - 15d are cascaded using logic devices 80 - 83 connected as shown so that a given predecoded counter ( for example , 15a ) will not increment until the most significant ( p3 ) outputs of all of the lesser significant predecoded counters ( for example , 15b - 15d ) are high and clock undergoes a positive transition . for clarity , in fig9 pertinent signals of cascaded predecoded counters 15d and 15c and nand gate 81 are shown in action . predecoded counter 15d is shown incrementing normally ( as was seen in fig7 ). inputting p3 of predecoded counter 15d and inverted clock to the nand gate 81 , which clocks clkm of predecoded counter 15c , causes 15c to increment only when p3 of predecoded counter 15d is high and clock undergoes a positive transition ( shown at time t of fig9 ). clearly , although not shown in fig9 predecoded counter 15b will not increment unless p3 of both 15c and 15d are high and clock undergoes a positive transition , as evidenced by the three - input gate 82 . similarly , predecoded counter 15a will not increment unless p3 of all three of 15b , 15c , and 15d are high and clock undergoes a positive transition , as evidenced by the four - input gate 83 . predecoded counters 15a - 15d in this configuration can increment only on a rising edge of clock . if all of predecoded counters 15a - 15d are ready to increment at the same time , they all will increment on the same rising edge of clock . this means that , although predecoded counters 15a - 15d are cascaded , there is no ripple effect on their outputs . this is a necessity : rippling inputs to decode stage 13 can be quite a problem , as multiple decoder branches ( not shown ) may be activated during the ripple . further , a rippling counter is actually slower . predecoded counter 15a is preset by using one or more signals in clkp to cause circuit 84a to latch a6 and a7 , passing a7 to s *, a7 * to r *, a6 to s *&# 39 ;, and a6 * to r *&# 39 ;. when predecoded counter 15a is not being preset , circuit 84a inputs high levels to s *, r *, s *&# 39 ;, and r *&# 39 ;. predecoded counters 15b , 15c , and 15d are similarly preset by circuits 84b , 84c , and 84d , respectively . referring again to fig5 the choice of nor gates in predecoder 51 and master stages of flip - flops 50 and 50 &# 39 ;, and nand gates in slave stages of flip - flops 50 and 50 &# 39 ; is deliberate . decode stage 13 , for which this embodiment was designed , happens to require active - high selection signals from predecoder 51 . using nors in predecoder 51 connected as shown in fig5 provides only one of p0 - p3 high ( active ) at one time . flip - flop 50 and 50 &# 39 ; slave stages drive predecoder 51 and have nands as output devices to avoid momentary false selections among p0 - p3 . latches like the slave stages within flip - flops 50 and 50 &# 39 ; have outputs that do not toggle instantaneously : one output will change before the other . the outputs of a nand latch ( such as the slave stage in flip - flop 50 , for example ) will both momentarily be high during a toggle . similarly , the outputs of a nor latch will both momentarily be low during a toggle . nor predecoder 51 is immune to the momentary simultaneous lows of nand slave stages of flip - flops 50 and 50 &# 39 ;, and thus avoids false selection among outputs p0 - p3 . similarly , had decode stage 13 required active - low selection signals , predecoder 51 would have comprised nand gates and the slave stages of flip - flops 50 and 50 &# 39 ; would have comprised nor gates to avoid false selection among outputs p0 - p3 . in flip - flops 50 and 50 &# 39 ; the master stages comprise nor gates and the slave stages comprise nand gates simply to make clkm and clks * have opposing active states . this means clkm and clks * can be clocked in parallel and flip - flop 50 always has a latched stage . having at least one stage latched at any one time gives flip - flop 50 stability : if both the master stage and the slave stage is transparent at one time , an infinite loop would result as feedback from outputs p0 - p2 drive inputs d0 , d1 , d0 &# 39 ;, and d1 &# 39 ;, thus changing outputs p0 - p2 . although individual circuit elements are described above , the invention is preferably embodied in an integrated semiconductor circuit . the claims should be interpreted accordingly .