there will be explained the case where a horizontal synchronizing signal is extracted from a composite synchronizing signal separated from a video signal . in fig1 x1 shows a circuit for generating a first pulse , while y1 shows a horizontal synchronizing signal extracting circuit . in the circuit x1 , a composite synchronizing signal a ( fig2 a ) separated from a video signal is supplied to a terminal 1 and a clock pulse c1 ( fig2 c1 ) having a frequency of , for example , 2 / 5 fsc is supplied to a terminal 2 . by fsc is meant the frequency ( 3 . 58 mhz ) of a color subcarrier wave generated within a tv receiver . the terminal 1 is connected through an inverter 11a to the cp terminal ( clock pulse terminal ) of a jk flip - flop circuit 3 , and the reset output , i . e . the q output , of the jk flip - flop circuit is fed back to the j and k terminals of the jk flip - flop circuit . the flip - flop circuit 3 is set at a rise of each pulse included in the composite synchronizing signal to produce a set output i . e . a q output . the q output lasts until the output of an and circuit 4 to be later described is fed back to the reset terminal of the flip - flop circuit 3 . the q output is supplied as one input to an and circuit 5 and the clock pulse c1 is supplied as the other input to the and circuit 5 . a first counting circuit 6 consists of first , second and third flip - flop circuits 6a , 6b and 6c connected in series configuration . the output of the and circuit 5 is supplied to the cp terminal of the first flip - flop circuit 6a . the q outputs of the second and third flip - flop circuits 6b and 6c are supplied to the and circuit 4 . the flip - flop circuit 3 and first counting circuit are reset by the output of the and circuit 4 . the flip - flop circuit 3 is a circuit for generating a to - be - later described reference pulse in response to each pulse included in the composite synchronizing signal a and an and circuit 7 is adapted to generate a first pulse d in synchronism with the reference pulse and is supplied with the q outputs of the first and third flip - flop circuits 6a and 6c and the q output of the second flip - flop circuit 6b . the output , i . e . the first pulse d , of the and circuit 7 is fed to the cp terminal of a jk flip - flop circuit 8 in the circuit y1 . the jk flip - flop circuit 8 is set at the rise of the first pulse d to produce a q output and adapted to generate a q output when the output of an and circuit 9 to be later described is delivered to the reset terminal r of the flip - flop circuit 8 . the q output of the flip - flop circuit 8 is fed back to the j and k terminals of the flip - flop circuit 8 . a second counting circuit 10 consists of first , second , third and fourth flip - flop circuits 10a , 10b , 10c and 10d which are connected in series configuration . the q output of the flip - flop circuit 8 and a second clock pulse c2 having a frequency of 2 / 35 fsc are delivered to an and circuit 13 , the output of which is supplied to the cp terminal of the first flip - flop circuit 10a . the output of the and circuit 13 is delivered through an inverter 11b to one input of the and circuit 9 and the q outputs of the third and fourth flip - flop circuits 10c and 10d are delivered to the other inputs of the and circuit 9 . the flip - flop circuit 8 and counting circuit 10 are set by the output of the and circuit 9 . an and circuit 14 is supplied with the first pulse d from the and circuit 7 and the q output of the flip - flop circuit 8 . the output g of the and circuit 14 represents a horizontal synchronzing pulse . let us now explain the operation of the circuit arrangement shown in fig1 by reference to fig2 and 3 . as shown in fig2 a horizontal synchronizing pulse a1 , equalizing pulse a2 and vertical synchronizing pulse a3 are included in the composite synchronizing signal a . noise pulses , not shown , are frequently included in the composite synchronizing signal . this embodiment is designed to obtain a horizontal synchronizing signal consisting of the horizontal synchronizing pulse a1 without being influenced by the noise pulses . the horizontal synchronizing pulse a1 as shown enlarged in fig2 a1 has a width of 4 . 9 ms . seven first clock pulses c1 can be included in the pulse width of the horizontal synchronizing pulse al ( fig2 c1 ). when the pulses a1 , a2 and a2 and a3 are supplied together with the noise pulse , q output is produced . while the q output is 1 , a first clock pulse c1 is supplied from the and circuit 5 to the first flip - flop circuit 6a . when the first counting circuit 6 counts six first clock pulses c1 , the and circuit 4 is opened and the first counting circuit 6 and flip - flop circuit 3 are reset by the output of the and circuit 4 . since the and circuit 4 is connected as mentioned above , the reset output is generated when the six first clock pulses c1 are counted . at the same time , the sixth first clock pulse is derived as an output from the and circuit 7 ( fig2 d ). the q output of the flip - flop circuit 3 has always a predetermined width irrespective of the input pulse ( including a noise pulse ) width . according to this invention , therefore , the q output is referred to as a reference pulse . from fig2 a1 , c1 and d it will be understood that the output of the and circuit 7 , i . e . the first pulse , is in synchronism with the horizontal synchronizing pulse . when the first pulse d is delivered to the flip - flop circuit 8 , the q output of the flip - flop circuit lasts from the rise of the first pulse until the flip - flop circuit 8 is reset . therefore , the second counting circuit 10 can count during the q output lasting period second clock pulses c2 ( 2 / 35 fsc ) passed through the and circuit 13 . since the cycle of the horizontal synchronizing pulse a1 is 63 . 5 μs , 13 second clock pulses c2 can occur during this time period . in fig3 - 10q1 to 10q4 there are shown the output waveforms of q outputs from the flip - flop circuits 10a - 10d in the second counting circuit 10 which occur from a rise of the q output until 13 second clock pulses are counted . when the thirteenth second clock pulse is counted , the and circuit is anded to cause the flip - flop circuits of the counting circuit 10 and flip - flop circuit 8 to be reset . the q output appearing at this time from the flip - flop circuit 8 is shown in fig3 - 8q . the width of the q output corresponds to one cycle of the second clock pulse . suppose that a first - clock pulse appears from the and circuit 7 in response to the horizontal synchronizing pulse . then , a second horizontal synchronizing pulse occurs during a pulse width period shown in fig3 - 8q and is passed through and circuit 14 and a horizontal synchronizing pulse shown in fig3 g is obtained . in contrast , if a first first - clock pulse is obtained in response to an equalizing pulse or a vertical synchronizing pulse , the equalizing pulse or vertical synchronizing pulse differs in cycle from the horizontal synchronizing pulse and , therefore , no pulse shown in fig3 g is obtained . if the first first - clock pulse is obtained in response to a noise pulse , no pulse shown in fig3 g is obtained , since such noise pulse has no periodicity . it is therefore possible to extract only the horizontal synchronizing pulse or horizontal synchronizing signal . let us now explain , by reference to fig4 why the first pulse d having a predetermined time relation to the rise of any pulse supplied to the cp terminal of the flip - flop circuit 3 is obtained from the and circuit 7 . in fig4 a q output , i . e . reference pulse rp , from the flip - flop circuit 3 rises when an equalizing pulse a2 - 15 rises , and falls when six first clock pulses had been counted . the waveforms of q outputs from the flip - flop circuits 6a , 6b and 6c which occur during the counting of said six first clock pulses are shown in fig4 - 6q1 to 6q3 . when said six first clock pulses had been counted , a reset pulse 4e appears from the and circuit 4 and the flip - flop circuit 3 is reset . when said six first clock pulses had been counted , the and circuit 7 is anded to generate a first pulse d . consequently , it is possible to extract any necessary horizontal synchronizing signal even during a time period including the equalizing pulse and vertical pulse . if any one of horizontal synchronizing pulses to be included in the composite synchronizing signal a is lacking , then it is impossible to extract a horizontal synchronizing pulse g in a time position corresponding to that in which the horizontal synchronizing pulse is lacking . with the embodiment of fig1 the first pulse d is generated in response to any pulse included in the composite synchronizing signal . with an embodiment of fig5 however , a first pulse d is generated only when any pulse having a width equal to , or greater than , the width of the horizontal synchronizing pulse is detected . a separate gate circuit is opened during the portion of a relatively wide time width including a point of time delayed a predetermined time period -- a period corresponding to one cycle of the horizontal synchronizing pulse -- from the rise of the detected pulse , and only the first pulse passed first through the separate gate circuit is extracted as a horizontal synchronizing signal . in fig5 a third counting circuit 21 consists of flip - flop circuits 21a , 21b and 21c connected in series configuration . a composite synchronizing signal a is supplied through an inverter 22 to the reset terminal r of the respective flip - flop circuits . the composite synchronizing signal a and first clock pulse c1 ( 2 / 5 fsc ) are delivered to an and circuit 23 , and the output of the and circuit 23 is supplied to the cp terminal of the flip - flop circuit 21a . the output of the and circuit is supplied , together with the q outputs of the flip - flop circuits 21a to 21c and q output of the flip - flop circuit 21b , to an and circuit 24 . consequently , the counting circuit 21 initiates counting of the first clock pulse c1 at the time of the rise of an incoming pulse and is reset at the time of the fall of the incoming pulse . a 4 . 9 μs horizontal synchronizing pulse can include seven 2 / 5 fsc clock pulses as explained in connection with fig2 . when , therefore , a horizontal synchronizing pulse arrives and six first clock pulses are counted , the and circuit 24 is anded and the sixth clock pulse is derived as a first pulse da . the same thing holds true when a vertical pulse arrives . however , when an equalizing pulse comes , the counting circuit is reset due to the narrow width of the equalizing pulse before it counts six first clock pulses . as a result , no first pulse da appears . the above - mentioned circuit is referred to as x2 . a circuit indicated by y2 comprises a flip - flop circuit 25 , and circuit 28 , fourth counting circuit 26 and and circuit 27 . the counting circuit 26 consists of first , second , third , fourth and fifth flip - flop circuits 26a , 26b 26c , 26d and 26e connected in series configuration . the first pulse da is supplied to the reset terminal r of the flip - flop circuit 25 and a second clock pulse c2 ( 2 / 35 fsc ) is supplied to the cp terminal of the flip - flop circuit 25 . the q output of the flip - flop circuit 25 is fed back to the j and k terminals of the flip - flop circuit 25 . the and circuit 28 is supplied with the q output of the flip - flop circuit 25 and the second clock pulse c2 . the output of the and circuit 28 is supplied to the reset terminal of the respective flip - flop circuits 26a to 26e . the q output of the flip - flop circuit 26e is fed back to the j and k terminals of the flip - flop circuit 26a to which the second clock pulse is supplied . the and circuit 27 is supplied with the first pulse da and the q outputs of the flip - flop circuits 26c and 26d to generate a horizontal synchronizing pulse ga . even if any pulse ( including a noise pulse ) having smaller width than the horizontal synchronizing pulse width ( 4 . 9 μs ) arrives at the circuit x2 , no first pulse da appears as set out above . since the flip - flop circuit 25 is reset at the time of the rise of the first pulse da , the flip - flop circuit 25 delivers only one second clock pulse as a q and is immediately reset . for this reason , the one second clock pulse c2 is delivered from the and circuit 28 to the counting circuit 24 and the counting circuit initiates counting of the second clock pulse c2 . fig6 shows the waveforms of each part of the circuit y2 when it is in an operative condition . suppose that a first pulse 30 in synchronism with a horizontal pulse detected at the circuit x2 is obtained from the and circuit 24 . then , a q output 31 ( fig6 - 25q ) is obtained from the flip - flop circuit 25 and a pulse 32 ( fig6 - 28e ) is obtained from the and circuit 28 . this causes the counting circuit 26 to initiate counting of a second clock pulse ( fig6 - c2 ). when the counting circuit 26 counts 13 second clock pulses , a first pulse 30a ( fig6 - da ), q output 31a ( fig6 - 25q ) and output 32a of the and circuit 28 ( fig6 - 28e ) are generated , since the cycle of the horizontal synchronizing pulse is 63 . 5 μs . the output waveforms of the flip - flop circuits 26a , 26b , 26c and 26d are indicated by 26q1 , 26q2 , 26q3 and 26q4 , respectively . since the q output of the flip - flop circuits 26c and 26d is 1 at a point of time when the counting circuit 26 counts 12 second clock pulses c2 , a gate pulse ( fig6 - 27e ) for the and circuit 27 is generated . in the absence of the first pulse 30a the gate pulse 33 lasts until 16 second clock pulses are counted . the output , i . e . a first pulse ga , of the and circuit 27 is passed through and circuit 27 and derived as a horizontal synchronizing pulse 34a ( fig6 ga ). at the same time , the counting circuit 26 is reset and initiates counting of the second clock pulses ready for the next horizontal synchronizing pulse 34b . even when a noise pulse having a width greater than that of the horizontal synchronizing pulse comes during the time period in which the counting circuit 26 counts 12 second clock pulses , no gate pulse 33 is generated and , consequently , no first pulse da is derived as a horizontal synchronizing pulse . even if a first pulse da is generated subsequently to the appearance of the pulse 30a during the time period in which 12 to 16 second clock pulses are counted , a gate pulse 33 is terminated in response to the pulse 30a and the first pulse da is not derived as a horizontal synchronizing pulse . it will be understood that , since a noise pulse does not come at the same cycle as a horizontal synchronizing pulse , only the horizontal synchronizing pulse can be extracted . the above - mentioned embodiments are both directed to the extraction of only a horizontal synchronizing pulse from a composite synchronizing signal which is separated from a video signal . however , only a vertical synchronizing pulse can be extracted by suitably modifying the circuits shown in fig1 and 5 . this invention is not restricted to the extraction of a synchronizing signal from a composite synchronizing pulse which is separated from a video signal . it can also be applied to the extraction , from any composite synchronizing signal including a plurality of synchronizing signals , of a synchronizing signal whose constituent synchronizing pulses have desired cycles .