hereinafter , a semiconductor memory device in accordance with the present invention will be described in detail referring to the accompanying drawing . fig3 is a block diagram setting forth a semiconductor memory device in accordance with a preferred embodiment of the present invention . referring to fig3 , the semiconductor memory device of the present invention includes a bit line sense amplifier ( blsa ) driving controller 600 , a blsa array 400 and a memory cell array 500 . furthermore , the blsa driving controller 600 is provided with an internal signal generator 100 , a blsa driving control signal generator 200 and a blsa power line driver 300 . herein , the blsa driving controller 600 is employed for overdriving a bit line connected to the bit line sense amplifier in response to an active command act , and for overdriving the bit line in response to a precharge command pcg . in detail , the blsa array 400 incorporating therein a plurality of bit line sense amplifiers that sense a potential difference of a bit line pair bl , blb and amplifies the data transferred to the bit line . the internal signal generator 100 generates a first enable signal saen and a second enable signal saen_pcg in response to an active command act and a precharge command pcg , wherein the first enable signal saen has an activation period corresponding to a row active time tras and the second enable signal saen_pcg has an activation period which is slightly shorter than the row active time tras by a predetermined time in comparison with the activation time of the first enable signal saen . the blsa power line driver 300 is used for normally driving or overdriving the blsa power line rto . the blsa driving control signal generator 200 generates a plurality of control signals sp 1 , sp 2 , sn to control the blsa power line driver 300 in response to the first enable signal saen and the second enable signal saen_pcg . fig4 is a circuit diagram setting forth the blsa driving control signal generator 200 of the blsa driving controller 600 in accordance with the preferred embodiment of the present invention . referring to fig4 , the blsa driving control signal generator 200 includes an overdriving control signal generator 220 and a normal driving control signal generator 240 . the overdriving control signal generator 220 activates an overdriving control signal sp 1 during a first predetermined time td 1 when the first enable signal saen is activated , and also activates the overdriving control signal sp 1 during a second predetermined time td 2 when the second enable signal saen_pcg is deactivated . the normal driving control signal generator 240 activates a normal driving control signal sp 2 when the first enable signal saen is activated and the overdriving control signal sp 1 is deactivated . meanwhile , the overdriving control signal generator 220 is provided with an initial overdriving unit 222 , a terminal overdriving unit 224 and a nor gate nr 1 for performing a logic nor operation to the output signals of the initial overdriving unit 222 and the terminal overdriving unit 224 , in order to output the overdriving control signal sp 1 . herein , the initial overdriving unit 222 has a first delay unit 222 a for delaying the second enable signal saen_pcg by the first predetermined time td 1 , a first inverter i 1 for inverting the output signal of the first delay unit 222 a , a first nand gate nd 1 for performing a logic nand operation to the second enable signal saen_pcg and the output signal of the first inverter i 1 , a second inverter i 2 for inverting the output signal of the first nand gate nd 1 . therefore , the initial overdriving unit 222 activates the overdriving control signal sp 1 for the first predetermined time td 1 when the second enable signal saen_pcg is activated . in addition , the terminal overdriving unit 224 has a third inverter i 3 for inverting the second enable signal saen_pcg , a second nand gate nd 2 for performing a logic nand operation to the output signal of the third inverter i 3 and the first enable signal saen , a fourth inverter i 4 for inverting the output signal of the second nand gate nd 2 , a second delay unit 222 b for delaying the output signal of the fourth inverter i 4 by the second predetermined time td 2 , a third nand gate nd 3 for performing a logic nand operation to the output signals of the third and the fourth inverters i 3 and i 4 , and a sixth inverter i 6 for inverting the output signal of the third nand gate nd 3 . thus , the terminal overdriving unit 224 activates the overdriving control signal sp 1 for the second predetermined time td 2 when the second enable signal saen_pcg is deactivated and the first enable signal saen is activated . the normal driving control signal generator 240 is provided with a seventh and eighth inverters i 7 and i 8 for delaying the second enable signal saen_pcg , a ninth inverter i 9 for inverting the overdriving control signal sp 1 , a fourth nand gate for performing a logic nand operation to the output signals of the eighth and ninth inverters i 8 and i 9 , and a tenth inverter i 10 for outputting the normal driving control signal sp 2 by inverting the output signal of the fourth nand gate nd 4 . fig5 is a circuit diagram setting forth the blsa power line driver 300 of the blsa driving controller 600 in accordance with the preferred embodiment of the present invention . referring to fig5 , the blsa power line driver 300 includes a first pmos transistor pm 1 for applying the core voltage vcore to the blsa power line rto in response to the normal driving control signal sp 2 , a second pmos transistor pm 2 for applying the external voltage vext to the blsa power line rto in response to the overdriving control signal sp 1 , a first nmos transistor nm 1 for applying the ground voltage vss to the blsa power line sz in response to the normal voltage driving signal sn , and a second nmos transistor for rendering the blsa power lines rto and sz be a same voltage level in response to an equalizing signal bleq . in general , the external voltage vext has a higher voltage level than the core voltage vcore . fig6 is a timing diagram setting forth an operational sequence of the semiconductor memory device in accordance with the preferred embodiment of the present invention . to begin with , when the active command act is activated , data stored in the memory cells are applied to the bit line pair bl , blb . then , the internal signal generator 100 activates the first enable signal saen and the second enable signal saen_pcg in response to the active command act . the blsa driving control signal generator 200 activates the overdriving control signal sp 1 for the first predetermined time td 1 when the second enable signal saen_pcg is activated so that the external voltage vext is applied to the blsa power line rto . therefore , the data applied to the bit line is rapidly sensed and amplified at the bit line sense amplifier . afterwards , in case that a voltage level of the bit line pair bl and blb becomes beyond a specific voltage level , the blsa driving control signal generator 200 deactivates the overdriving control signal sp 1 and activates the normal driving control signal sp 2 . thereafter , when the precharge command is activated , the internal signal generator 100 deactivates the second enable signal saen_pcg . in response to the activated second enable signal saen_pcg , the blsa driving control signal generator 200 deactivates the normal driving control signal sp 2 and activates the overdriving control signal sp 1 for the second predetermined time td 2 . accordingly , since the external voltage vext is applied to the bit line pair bl , blb just before the word line is deactivated due to the precharge command pcg , the voltage level is rapidly increased to thereby store the data in the memory cell with high speed . thereafter , the blsa driving control signal generator 200 deactivates the first enable signal saen and deactivates the word line so that the data of the bit line pair is stored in the memory cell . as described above , the present invention provides an advantageous merit for reducing the write recovery time . in other words , the external voltage vext of which voltage level is higher than the core voltage vcore is applied to the blsa power line rto just before performing a precharge operation even though the operational range of the core voltage vcore becomes lowered because of the low external voltage level . accordingly , it is possible to reduce the write recovery time . furthermore , in comparison with the conventional semiconductor memory device , since the voltage level of the memory cell is relatively higher than the prior art , the self refresh period can be increased . the present application contains subject matter related to the korean patent application no . kr 2004 - 31880 , filled in the korean patent office on may 6 , 2004 , the entire contents of which being incorporated herein by reference . while the present invention has been described with respect to the particular embodiments , it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the following claims .