fig2 schematically illustrates a configuration of a liquid crystal display apparatus having a function of displaying a picture of different aspect ratio in accordance with an embodiment of the present invention . as shown in fig2 this liquid crystal display comprises first to tenth drain electrode drivers dd 1 to dd 10 arranged at the upper side of a liquid crystal panel 10 , and first and second gate electrode drivers gd 1 and gd 2 arranged at the left side of the liquid crystal panel 10 . the liquid crystal panel 10 is preferably an active matrix type lcd employing thin film transistors ( tft ) formed to have an aspect ratio of 16 to 9 . also , the liquid crystal panel 10 has 800 pixels arranged in the horizontal axis and 400 scanning lines in the vertical axis . further , the liquid crystal panel 10 has 2400 drain electrodes arranged in the horizontal axis and 480 gate electrodes arranged in the vertical axis to thereby drive a red , green , and blue color per a pixel for displaying a color picture . first to tenth drain electrode drivers dd 1 to dd 10 drive the 2400 drain electrodes , each driving 240 of them . the second to ninth drain electrode drivers dd 2 to dd 9 drive drain electrodes positioned in the central region 11 where a normal picture with the aspect ration of 4 to 3 is displayed . further , the first and tenth drain electrode drivers dd 1 and dd 10 drive drain electrodes positioned in the left and right side region 12 and 13 of the normal display region , respectively . the second to ninth drain electrode drivers dd 2 to dd 9 are connected in cascade and sample picture data sequentially . on the other hand , the first and second gate electrode drivers gd 1 and gd 2 , arranged at the left side of the liquid crystal panel 10 , drive by dividing the 480 gate electrodes into upper and lower portions of 240 gate electrodes each , respectively . also , the first and second gate electrode drivers gd 1 and gd 2 are driven complimentary to each other . moreover , the liquid crystal display apparatus 10 according to the above embodiment of the present invention comprises a timing control 20 for controlling a picture data sampling time of the first to tenth drain electrode drivers dd 1 to dd 10 , and a data converter 30 for converting picture data to be supplied for the first to tenth drain electrode drivers dd 1 to dd 10 . a common clock signal clk is applied to the first to tenth drain electrode drivers , the timing control 20 , and the data converter 30 . the timing control 20 generates the first and second start pulses sp 1 and sp 2 to be applied to the first and tenth drain electrode drivers dd 1 and dd 10 , respectively , and the data reset signal dres to be applied to the data converter 30 . in order to generate signals sp 1 , sp 2 and dres , the timing control 20 inputs the clock signal clk , a horizontal synchronous signal hcy , a normal / wide mode signal nws , and the first carry signal cr 1 from the drain electrode driver dd 1 ; and the ninth carry signal cr 9 from the ninth drain electrode driver dd 9 . the first and second start pulses sp 1 and sp 2 are respectively generated once per horizontal scanning interval and in a sequence depending on the aspect ratio of a picture to be displayed on the liquid crystal panel 10 . the data reset signal dres also has a different waveform depending on the aspect ratio of a picture to be displayed on the liquid crystal panel 10 . a detailed explanation of this aspect of the present invention will now be made with reference to fig3 and 4 . fig3 is a timing chart of signals when the normal / wide mode signal nws remains at a high logic , that is , where a picture with the aspect ratio of 16 to 9 is displayed ( wide mode ). the first and second start pulses sp 1 and sp 2 are sequentially generated as shown in fig3 . on the other hand , the data reset signal dres always remains at a specified logic , for example , a high logic , regardless of the start pulses . further , the first carry signal cr 1 is generated by the first drain electrode driver dd 1 when it has completed a sampling of the picture data . likewise , the ninth carry signal cr 9 is generated by the ninth drain electrode driver dd 9 when it completes a sampling of picture data . this ninth carry signal cr 9 has the same phase as the second start pulse sp 2 . referring now to fig4 there is illustrated a timing of the first and second start pulses sp 1 and sp 2 in the case where the normal / wide mode signal remains at a low logic , that is , where a picture with the aspect ratio of 4 to 3 is displayed on the liquid crystal panel 10 . in this case , the first and second start pulses sp 1 and sp 2 are simultaneously generated as shown in fig4 . the data reset signal dres maintains a specified logic for example , a low logic in the course of a time interval from the rising edge of the first start pulse sp 1 until the rising edge of the first carry signal cr 1 and a time interval from the rising edge of the ninth carry signal cr 9 until the starting time of the horizontal blanking interval . returning to fig2 the data converter 30 selectively converts input picture data ida in accordance with a logical state of the data reset signal dres from the timing control 20 to generate the converted picture data cda . specifically , the data converter 30 passes the input picture data ida when the data reset signal dres is enabled and otherwise blanks the display data . as a result , the data converter 30 supplies converted picture data identical to the input picture data ida with the first to tenth drain electrode drivers dd 1 to dd 10 commonly when the data reset signal dres remains only at the reference level as shown in fig3 . otherwise , data converter 30 supplies converted picture data cda having a part of the input picture data ida replaced with blanking display data bd with the first to tenth drain electrode drivers dd 1 to dd 10 when the data reset signal dres has intervals of a specified logic , for example , a low logic level as shown in fig4 . the input picture data ida is a digitization of an analog image signal performed by an analog to digital converter , and is supplied to data converter 30 via a memory . the picture data is written to data converter 30 by the memory at twice the sampling clock frequency of an analog to digital converter . the memory ( not shown ), writes the digital data to data converter 30 . further , at the time of reading out the picture data to the data converter , the memory begins to read in picture data when 4 . 6 μs elapses from a start point i . e ., a rising edge of the horizontal scanning interval . the memory reads out the picture data for a period of 21 . 54 μs when a wide picture is displayed on the liquid crystal panel 10 , and reads out the picture data for a period of 20 . 16 μs when normal picture having a 4 to 3 aspect ratio is to be displayed . according to these picture display modes , a frequency of the sampling clock of the analog to digital converter and a frequency of the writing and reading clock of the memory have values as shown in table i , below . accordingly , with the wide 16 to 9 aspect ratio , the first start pulse sp 1 is produced at timing control circuit 20 when 4 . 6 μs has elapsed from the start point , ( i . e ., the rising edge of the horizontal scanning interval ); while , with the normal 4 to 3 aspect ratio , it is generated when 3 . 2 μs have elapsed from the start point . also , the input picture data ida includes red ( r ) data , green ( g ) data , and blue ( b ) data . a process in which the first to tenth drain electrode drivers dd 1 to dd 10 sample the converted picture data cda according to first and second start pulses sp 1 and sp 2 produced at the timing control 20 will now be explained in detail for the wide and normal picture . initially , if the wide picture is displayed on the liquid crystal panel 10 , the first and tenth drain electrode drivers dd 1 and dd 10 are sequentially enabled by the first and second start pulses sp 1 and sp 2 , as shown in fig3 to sample the converted picture data cda from the data converter 30 . in the period extending from the time when the first drain electrode driver dd 1 completes the sampling of the converted picture data cda to the time when the tenth drain electrode driver dd 10 initiates the sampling of the converted picture data cda , the second to ninth drain electrode drivers dd 2 to dd 9 sample the converted picture data cda sequentially . this is because each of the second to ninth drain electrode drivers dd 2 to dd 9 input the carry signals cr 1 to cr 8 from the preceding drain electrode drivers as start pulses . the first drain electrode driver dd 1 begins sampling of the converted picture data cda when 4 . 6 μs has elapsed from the start point of the horizontal scanning interval . at this time , a clock signal clk applied to the first to tenth drain electrode drivers dd 1 and dd 10 has a frequency of 31 . 18 mhz . on the other hand , if the normal picture is displayed on the liquid crystal panel 10 , drain electrode drivers ddi and dd 10 sample the converted picture data cda simultaneously . this is because the second start pulse sp 2 is generated at the same time as the first start pulse sp 1 , that is , when 3 . 2 μs have elapsed from the start point of the horizontal scanning interval . at this time , the first and tenth drain electrode drivers dd 1 and dd 10 sample the blanking display data bd generated by the data converter 30 . subsequently , the second to ninth drain electrode drivers dd 2 to dd 9 sequentially sample the converted picture data cda . further , at the time of sampling the converted picture data cda , the first to tenth drain electrode drivers dd 1 to dd 10 sequentially input the picture data corresponding to 80 picture elements or pixels by the unit of one pixel including r , g and b data by means of the clock signal clk . at this time , a clock signal clk applied to the first to tenth drain electrode drivers dd 1 to dd 10 has a frequency of 25 . 20 mhz . fig5 is a detailed circuit diagram of timing control 20 . referring to fig5 timing control 20 comprises a programmable logic array ( pla ) 21 for inputting a horizontal synchronous signal hcy , a normal / wide mode signal nws , a clock signal clk , and a reset signal reset . a multiplexer 22 inputs the normal / wide mode signal nws as a control signal . pla 21 operates on the horizontal synchronous signal hcy , the normal / wide mode signal nws , the clock signal clk , and the reset signal reset to generate the first start pulse sp 1 for every horizontal scanning interval . this first start pulse sp 1 has a phase difference from the horizontal synchronous signal hcy in accordance with a logical value of the normal / wide mode signal nws . specifically , in the case where the normal / wide mode signal nws remains at a high logic , that is , where the wide picture is displayed on liquid crystal panel 10 , the first start pulse sp 1 is generated at the time point when 4 . 6 μs has elapsed from the rising edge of the horizontal synchronous signal , as shown in fig3 . on the other hand , in the case where the normal / wide mode signal nws remains at a low logic , that is , where the normal picture is displayed on the liquid crystal panel 10 , the first start pulse sp 1 is generated when 3 . 2 μs has elapsed from the rising edge of the horizontal synchronous signal , as shown in fig4 . further , the multiplexer 22 supplies one of the first start pulse s 1 or ninth carry signal cr 9 from the ninth drain electrode driver dd 9 to the tenth drain electrode driver dd 10 as the second start pulse sp 2 in accordance with a logical value of the normal / wide mod e signal nws . specifically , the multiplexer 22 selects the ninth carry signal cr 9 as the second start pulse sp 2 when the normal / wide mode signal remains at a high logic , that is , where the wide picture is displayed on the liquid crystal panel 10 ; and selects the first start pulse sp 1 as the second start pulse sp 2 in the case where the normal / wide mode signal nws remains at a low logic , that is , where the normal picture is displayed on the liquid crystal panel 10 . accordingly , the pla 21 and the multiplexer 22 control a sampling timing of the first to tenth drain electrode drivers dd 1 to dd 10 by generating first and second start pulses sp 1 and sp 2 . moreover , the timing control 20 further comprises or gate 23 for inputting first start pulse sp 1 and the first and ninth carry signals cr 1 and cr 9 , the first flip - flop 24 for inputting the horizontal synchronous signal hcy to the reset terminal thereof , an inverter 25 connected between an output terminal q and an input terminal d of the first flip - flop 24 , and or gate 26 for inputting the normal / wide mode signal nws . flip - flop 24 initializes a signal in the output terminal q to a low logic state every horizontal scanning interval delineated by the horizontal synchronous signal hcy . also , flip - flop 24 latches a signal of the input terminal d to the output terminal q to thereby invert a signal of the output terminal q , whenever pulses from or gate 23 , that is , the first start pulse sp 1 and the first and ninth carry signals cr 1 and cr 9 are applied thereto . meanwhile , the inverter 25 inverts a signal from the output terminal q of the first flip - flop 24 and feeds it back into the input terminal d thereof . consequently , the first or gate 23 , the first flip - flop 24 , and the inverter 25 allow a range between the first start pulse sp 1 and the first carry signal cr 1 , a range between the first and the ninth carry signals cr 1 and cr 9 , and a range after the ninth carry signal cr 9 , respectively , to have a certain logical value every horizontal scanning interval , thereby establishing a data blanking region . finally , or gate 26 provides an or operation of the normal / wide mode signal nws and the output signal of the inverter 25 , i . e ., the data blanking region signal to generate the data reset signal dres . this data reset signal dres remains at a high logic state and hence allows the input picture data ida to be unchanged in the case where the normal / wide mode signal nws remains at a high logic , that is , where the wide picture is displayed on the liquid crystal panel 10 . on the other hand , it applies the data blanking region signal to the data converter 30 as the data reset signal dres and allows a part of the input picture data ida to be changed into the blanking display data , in the case where the normal / wide mode signal nws remains at a low logic , that is , where the normal picture is displayed on the liquid crystal panel 10 . fig6 is a detailed circuit diagram of data converter 30 . referring to fig6 data converter 30 comprises second to fourth flip - flops 31 , 32 , and 33 connected in cascade . these second to fourth flip - flops 31 , 32 , and 33 commonly input the clock signal clk to their clock terminals ck . the second flip - flop 31 latches the input picture data ida input to the input terminal d of flip - flop 32 . likewise , the third flip - flop 32 latches the output signal of flip - flop 31 to the input terminal of flip - flop 33 . flip - flop 33 supplies the output signal cda . if the data reset signal dres of low logic from the second or gate 26 , shown in fig5 is applied to the clear terminal of flip - flop 33 , flip - flop 33 outputs blanking display data bd . this blanking display data bd is inserted to the converted picture data cda only when the normal picture is displayed on the liquid crystal panel 10 . through this structure , noise components are not displayed on the side areas 12 and 13 of the liquid crystal panel 10 . fig7 schematically illustrates a configuration of a liquid crystal display apparatus with a displaying function of a picture of different aspect ratio in accordance with a second embodiment of the present invention . as shown in fig7 this liquid crystal display apparatus comprises first to tenth drain electrode drivers dd 1 to dd 10 arranged at the upper side of a liquid crystal panel 10 , and first and second gate electrode drivers gd 1 and gd 2 arranged at the left side of he liquid crystal panel 10 . first to tenth drain electrode drivers dd 1 to dd 10 arranged , in parallel , at the upper side of liquid crystal panel 10 drive the drain electrodes in such a manner that three drain electrodes are assigned to one pixel as red , green ; and blue electrodes . the second to ninth drain electrode drivers dd 2 to dd 9 drive drain electrodes positioned in the central region 11 to form the normal picture . the first and tenth drain electrode drivers dd 1 and dd 10 drive drain electrodes positioned in the left and right side region 12 and 13 of the normal display region , respectively . drain electrode drivers dd 2 to dd 9 are connected in cascade with one another to thereby sample picture data sequentially . gate electrode drivers gd 1 and gd 2 , on the other hand , are arranged at the left side of the liquid crystal panel d and drive the 480 gate electrodes at upper and lower portions , respectively . also , the first and second gate electrode drivers gd and gd 2 are driven complementarily to each other . moreover , the liquid crystal display apparatus 10 according to the above embodiment of the present invention comprises a timing control 20 for controlling a picture data sampling time of the first to tenth drain electrode drivers dd 1 to dd 10 , and a data converter 30 for converting picture data to be supplied for the first to tenth drain electrode drivers dd 1 to dd 10 . also , a clock signal is commonly applied to the first to tenth drain electrode drivers , the timing control 20 , and the data converter 30 . the timing control circuit 20 generates start pulses sp 1 , sp 2 and sp 3 that are applied to the first , second and tenth drain electrode drivers dd 1 , dd 2 and dd 10 , respectively , and the data reset signal dres that is applied to the data converter 30 . in order to generate signals sp 1 , sp 2 , sp 3 , and dres , the timing control circuit 20 inputs the clock signal clk , a horizontal synchronous signal hcy , a normal / wide mode signal nws , the first carry signal cr 1 from the drain electrode driver dd 1 , and the ninth carry signal cr 9 from the ninth drain electrode driver dd 9 . the first to third start pulses sp 1 to sp 3 are generated once per horizontal scanning interval in a sequence depending on the aspect ratio of a picture to be displayed . the data reset signal dres also become to have a different wave form depending on the aspect ratio of a picture to be displayed on the liquid crystal panel 10 . a detailed explanation of these will be done with reference to fig8 and 9 below . fig8 is a timing diagram of certain signals when the normal / wide mode signal remains at a high logic , that is , where a picture with the aspect ratio of 16 to 9 is displayed ( wide mode ). the first to third start pulses sp 1 to sp 3 are generated as shown in fig8 . the data reset signal dres always remains at a specified logic , for example , a high logic regardless of the start pulses . the first carry signal cr 1 is generated by the first drain electrode driver dd 1 when dd 1 completes a sampling of picture data . likewise , the ninth carry signal cr 9 is generated by the ninth drain electrode driver dd 9 when dd 9 completes a sampling of picture data . the first carry signal cr 1 has the same phase as the second start pulse sp 2 while the ninth carry signal cr 9 has the same phase as the third start pulse sp 3 . fig9 is a timing diagram of certain signals when the normal / wide mode signal remains at a low logic , that is , where a picture with the aspect ratio of 4 to 3 is displayed on liquid crystal panel 10 ( normal mode ). in this case , the first and second start pulses sp 1 and sp 2 are sequentially generated as shown in fig8 and the third start pulse sp 3 is simultaneously generated with the first start pulse sp 1 . the data reset signal dres eventually maintains a specified logic , for example , a low logic level , in the time interval measured from the rising edge of the first start pulse sp 1 until the rising edge of the second start pulse s 2 , and a time interval measured from the rising edge of the ninth carry signal cr 9 until the starting time of the next horizontal blanking interval . returning to fig7 the data converter 30 selectively converts input picture data ida in accordance with a logical state of the data reset signal dres from the timing control 20 to generate the converted picture data cda . specifically , the data converter 30 passes the input picture data ida when the data reset signal dres is enabled and otherwise blanks the display data . as a result , the data converter 30 supplies converted picture data identical to the input picture data ida with the first to tenth drain electrode drivers dd 1 to dd 10 commonly when the data reset signal dres remains only at the reference level as shown in fig8 . otherwise , data converter 30 supplies converted picture data cda having a part of the input picture data ida replaced with blanking display data bd with the first to tenth drain electrode drivers dd 1 to dd 10 commonly when the data reset signal dres has intervals converted from the reference level , i . e ., the grounding logic into a specified logic for example , a low logic and converted vice versa . the input picture data ida makes a digitization of an analog image signal by an analog to digital converter , and is supplied to data converter 30 via a memory . further , at the time of reading out the picture data to the converter , the memory begins to read in picture data when 4 . 6 μs elapses from a start point i . e ., a rising edge of the horizontal scanning interval . the memory reads out the picture data during a period of 21 . 54 μs in the case when a wide picture is displayed on the liquid crystal panel 10 and reads out the picture data for a period of 26 . 16 μs when a normal picture having a 4 to 3 aspect ratio is to be displayed . according to these picture display modes , a frequency of the sampling clock of the analog to digital converter and a frequency of the writing and reading clock of the memory becomes to have values as shown in table 1 above . accordingly , the first start pulse sp 1 produced at the timing control circuit 20 is when 4 . 6 μs has elapsed from the start point , ( i . e ., the rising edge of the horizontal scanning interval ); while with the normal 4 to 3 aspect ratio , it is generated when 3 . 2 μs has elapsed from the start point . subsequently , a process in which the first to tenth drain electrode drivers dd 1 to dd 10 sample the converted picture data cda by the first to third start pulses sp 1 and sp 2 produced at the timing control 20 will be explained in detail , by classifying into the case of displaying the wide picture and the case of displaying the normal picture . firstly , if the wide picture is displayed on the liquid crystal panel 10 , then the first , second and tenth drain electrode drivers dd 1 , dd 2 and dd 10 are sequentially enabled by the first to third start pulses sp 1 to sp 3 as shown in fig8 to sequentially sample the converted picture data cda from the data converter 30 . in a period measured from the time when the second drain electrode driver dd 2 completes the sampling of the converted picture data cda until the time when the tenth drain electrode driver dd 10 initiates the sampling of the converted picture data cda , the third to ninth drain electrode drivers dd 3 to dd 9 sequentially sample the converted picture data cda . this is caused by the fact that the third to ninth drain electrode drivers dd 3 to dd 9 input the carry signals cr 2 to cr 8 from the drain electrode drivers dd 2 to dd 8 adjacent to the left side thereof as start pulses , respectively . the first drain electrode driver dd 1 begins sampling of the converted picture data cda at the time point when a time of 4 . 6 μs elapses from the start point of the horizontal scanning interval . at this time , a clock signal clk applied to the first to tenth drain electrode drivers dd 1 and dd 10 has a frequency of 31 . 18 mhz . on the other hand , if the normal picture is displayed on the liquid crystal panel 10 , then the first to tenth drain electrode drivers dd 1 to dd 10 sample the converted picture data cda simultaneously . this is caused by the third start pulse sp 3 being generated at the same time as the first start pulse sp 1 , that is , at the time point when a time of 3 . 2 μs elapses from the start point of the horizontal scanning interval . at this time , the first and tenth drain electrode drivers dd 1 and dd 10 sample the blanking display data bd generated by the data converter 30 . meanwhile , the second to ninth drain electrode drivers dd 2 to dd 9 sample the converted picture data cda sequentially after the sampling of the converted picture data cda in the first and tenth drain electrode drivers dd 1 and dd 10 is completed . further , at the time of sampling the converted picture data cda , the first to tenth drain electrode drivers dd 1 to dd 10 sequentially input the picture data corresponding to 80 picture elements or pixels by the unit of one pixel including r , g , and b data by means of the clock signal clk . at this time , a clock signal clk applied to the first to tenth drain electrode drivers dd 1 to dd 10 has a frequency of 25 . 20 mhz . fig1 is a detailed circuit diagram of timing control 20 shown in fig7 . referring to fig1 , timing control 20 comprises a programmable logic array 21 , hereinafter referred simply to as “ pla ”, inputting a horizontal synchronous signal hcy , a normal / wide mode signal nws , a clock signal clk , and a reset signal reset ; and the first and second multiplexer 22 for inputting the normal / wide mode signal nws as a control signal . the pla 21 provides a logical operation of the horizontal synchronous signal hcy , the normal / wide mode signal clk , the clock signal clk , and the reset signal reset to thereby generate both of the first start pulse sp 1 and the quasi start pulse psp for every horizontal scanning interval . this first start pulse sp 1 has a phase difference different from the horizontal synchronous signal hcy in accordance with a logical value of the normal / wide mode signal nws . specifically , in the case where the normal / wide mode signal nws remains at a high logic , that is , where the wide picture is displayed on the liquid crystal panel 10 , the first start pulse sp 1 is generated at the time point when a time of 4 . 6 μs elapses from the rising edge of the horizontal synchronous signal , as shown in fig8 . on the other hand , in the case where the normal / wide mode signal nws remains at a low logic , that is , where the normal picture is displayed on the liquid crystal panel 10 , the first start pulse sp 1 is generated when 3 . 2 μs elapses from the rising edge of the horizontal synchronous signal , as shown in fig9 . similar to this , the quasi start pulse psp becomes to have a phase difference different from the horizontal synchronous signal hcy , and which is generated at the time point when a certain time , for example , of 1 . 3 μs elapses from the generation of the first start pulse sp 1 . further , the first multiplexer 22 supplies any one of the first start pulse sp 1 and the ninth carry signal cr 9 from the ninth drain electrode driver dd 9 to the tenth drain electrode driver dd 10 as the third start pulse sp 2 in accordance with a logical value of the normal / wide mode signal nws . specifically , the first multiplexer 22 selects the ninth carry signal cr 9 as the third start pulse sp 3 in the case where the normal / wide mode signal remains at high logic , that is , where the wide picture is displayed on the liquid crystal panel 10 ; while it selects the first start pulse sp 1 as the third start pulse sp 3 in the case where the normal / wide mode signal nws remains at a low logic , that is , where the normal picture is displayed on the liquid crystal panel 10 . meanwhile , the second multiplexer 27 supplies any one of the quasi start pulse psp and the first carry signal cr 1 from the first drain electrode driver dd 1 to the second drain electrode driver dd 2 as the second start pulse sp 2 in accordance with a logical value of the normal / wide mode signal nws . specifically , the second multiplexer 27 selects the first carry signal cr 1 as the first start pulse sp 1 in the case where the normal / wide mode signal remains at a high logic , that is , where the wide picture is displayed on the liquid crystal panel 10 ; while it selects the quasi start pulse psp as the second start pulse sp 2 in the case where the normal / wide mode signal nws remains at a low logic , that is , where the normal picture is displayed on the liquid crystal panel 10 . as a result , the pla 21 , the first and the third multiplexers 22 and 27 constitute means for controlling a sampling timing of the first to tenth drain electrode drivers dd 1 to dd 10 by generating the first to third start pulses sp 1 to sp 3 . moreover , the timing control 20 further comprises first or gate 23 inputting the first start pulse sp 1 and the first and ninth carry signals cr 1 and cr 9 , the first flip - flop 24 for inputting the horizontal synchronous signal hcy to the reset terminal thereof , inverter 25 connected between an output terminal q and an input terminal d of the first flip - flop 24 , and the second or gate 26 for inputting the normal / wide mode signal nws . since operations of first or gate 23 , first flip - flop 24 , inverter 25 and second or gate in the above embodiment are identical to those in the preceding embodiment as shown in fig5 an explanation is omitted . as described above , according to the present invention , sequential control of the picture data sampling time of the first drain electrode driver driving the drain electrodes positioned in a region of the liquid crystal panel on which the normal picture different in aspect ratio from the liquid crystal panel is to be displayed and the picture data sampling time of the second drain electrode driver driving the drain electrodes positioned in a region of the liquid crystal panel on which the normal picture is not to be displayed , so that it becomes possible to display the normal picture having an aspect ratio different from the liquid crystal panel . also , it becomes possible to display the normal picture having an aspect ratio different from the liquid crystal panel by varying a part of the picture data commonly supplied with the first drain electrode driver driving the drain electrodes positioned in a region of the liquid crystal panel on which the normal picture is to be displayed and the second drain electrode driver driving the drain electrodes positioned in a region of liquid crystal panel on which the normal picture is not to be displayed . according to the present invention , therefore , it becomes possible to display the normal picture having an aspect ratio different from the liquid crystal panel along with the blanking picture in which noise components are not included . further , the present invention can provide a liquid crystal display apparatus of simplified circuit configuration which can selectively display either of the normal picture having a different aspect ration from the liquid crystal panel or the wide picture having the same aspect ratio as the liquid crystal panel . although the present invention has been described by the preferred embodiments illustrated in drawings hereinbefore , it is apparent from the above description to those ordinarily skilled in the art that various changes and modifications of the invention are possible without departing from the spirit thereof . for instance , it should be understood that , although the liquid crystal panel is shown driven by ten drain electrode drivers , the drain electrode drivers for driving the liquid crystal panel may be provided in a number smaller or larger than ten . further , it should be understood that a resolution of liquid crystal panel different from that , i . e ., of 800 × rgb480 illustrated in the embodiments of the present invention may be applicable . moreover , it is to be understood that aspect ratios of liquid crystal panel different from those , i . e ., of 4 to 3 and 16 to 9 illustrated in the embodiments of the present invention may be applicable . accordingly , the scope of the invention should be determined not by the embodiments illustrated and described , but by the appended claims and their equivalents .