embodiments of the distributed symmetric multiprocessing ( dsmp ) presented herein include at least five unique and practical features : ( 1 ) the use of a cluster of symmetric multiprocessing ( smp ) nodes to create a large smp system ; ( 2 ) the use of high - speed communication links supporting remote direct memory access ( rdma ) to decrease latency in memory page access ; ( 3 ) the use of a two - tiered memory including a local working memory and a global shared memory construct ; ( 4 ) the use of transactional memory model to maintain memory consistency with page coherency ; and ( 5 ) the use of distributed queues to create distributed disk file access within a cluster . the emergence of multi - core processors and high - speed rdma communication links has presented the software community with powerful new tools . dsmp provides a means of fully utilizing these advances . fig1 shows an smp computing - device within a dsmp computing system 100 that is an autonomous computing - device with processors , memory , and network port ( s ). there may also be disk storage and input / output interfaces . elements 102 a , 102 b , 102 c , . . . 102 n ( collectively , servers 102 ) represent individual smp servers . attached to server 102 a is a local connection interface 104 which allows user 106 to communicate with the dsmp computing - system 100 . a switch 108 connects together the servers 102 via respective via network interfaces 110 a , 110 b , 110 c , . . . 110 n ( collectively , network interfaces 110 ). the upper limit on the number of computing - devices ( servers 102 ) that comprise the computing system 100 depends on the capacity of the switch 108 . that limit is a function of the availability of a switch 108 which can support a single - hop connection . this configuration represents a switched dsmp implementation . fig2 shows an smp computing - system 200 that includes three computing - devices ( smp servers ) 202 a , 202 b , and 202 c ( collectively , servers 202 ). each server 202 is an autonomous smp computing device with processors , memory , input / output interfaces and at least two network ports 204 . the network ports 204 of the primary server 202 a are connected directly to servers 202 b and 202 c via high - speed ( e . g ., 40 gb / s or higher ) communications links 206 , such as infiniband ® switched fabric communications links , to form a three - way mesh . this configuration represents direct connect dsmp implementation . fig3 shows three architectures 302 , 304 , and 306 for smp computer - systems including several computing - devices ( smp servers ), the number of which is a function of available network ports on the computing - devices . the computing - system in fig2 with two network ports is shown in simplified form in fig3 as example 302 . hence , a computing - device with “ n ” available network ports ( via conductive cable , optical link or rf link ) can implement a computing - system of the size “ n + 1 ”. again , referring to fig3 , shown are three examples : 302 with two ( n = 2 ) network ports forming a three ( n + 1 = 3 ) computing - device computing - system ; 304 with three ( n = 3 ) network ports forming a four ( n + 1 = 4 ) computing - device computing - system ; and 306 with four ( n = 4 ) network ports forming a five ( n + 1 = 5 ) computing - device computing - system and so on . referring again to fig1 and 2 , the network interfaces 110 each interface to a host channel adapter on a respective server 102 that supports remote direct memory access ( rdma ). this is accomplished with optimized low - level drivers that bypass the legacy drivers . directly invoking the rdma logic in the hardware to move data between computing - devices eliminates the need of going from memory space to message space and back again , minimizing the overhead for message construction and deconstruction . in addition , it permits one - sided operations where the initiating node need not explicitly interrupt the target node . fig6 includes two graphs that show that the rdma technique described above provides a level of performance previously unseen . on average , it takes less than 5 μs to randomly read in a memory page of 4 , 096 bytes and less than 6 μs to write . this level of random r / w performance makes dsmp unique and commercially viable . as a point of reference , hardware cache coherent shared - memory supercomputers take on the order of 1 μs to read one 64 - or 128 - byte cache - line and memory appliances take 3 μs . approaches that use hypervisors or other added software layers require in excess of 40 μs . embodiments of the invention include systems and methods for the implementation of a symmetric multiprocessing ( smp ) computing system that is created from an underlying collection of homogeneous smp servers that are connected together in a tightly coupled network or cluster using a high - speed communications link that supports remote direct memory access ( rdma ). the system integrates this computer hardware architecture with new and existing operating system techniques to create a new derived work which i call a distributed symmetric multiprocessing ( dsmp ) system . the system comprises the following parts : a plurality of homogeneous symmetric multiprocessing servers ; a high - speed network supporting rdma operations ; unix like operating system ( s ); transactional distributed shared memory ( t - dsm ); distributed thread management ; distributed mutex management ; a method for handling false sharing of variables in a dsm ; and a distributed message based disk i / o queues . alternative embodiments include a method for the implementation of a distributed shared memory that exists globally on an underlying network of servers and supports memory page coherency using a transactional model . the control of memory page locking and synchronization is passed to the programmer via a new set of operating system primitives . the memory is divided into a single global shared region and a plurality of local working regions ( one per node ). the physical memory on each node of the system is divided into a local and a global partition . the global partitions on each node are concatenated together to form a single global shared memory . all memory is addressable on a page basis . the global memory contains the ultimate reference copy of every memory page used by an executing application program . all memory pages in global memory use fixed logical addressing , which translates to a physical page address on a particular node in the system . this is important in that it eliminates the need to search for global memory pages , and it allows for the use of one - sided rdma operations in moving pages between global and local memory . all application program threads execute in the local memory of a node , but see a memory space that is a subset of the full global memory . memory pages are copied from global to local memory as required by the program . modified local memory pages are copied from local to global memory in order to maintain a consistent global memory representation . an application program can force the immediate availability of a modified page to global memory by issuing a memory page synchronization request using an operating system primitive fig4 shows a dsmp computing system with smp servers ( nodes ) 402 a , 402 b , . . . 402 n whose memories form a t - dsm . as shown in fig4 , the physical memory in each computing device ( node or server ) 402 that forms a dsmp system is divided into two sections : a local working memory 404 and a global shared memory portion 406 . the local memory 404 supports all operating system and application software running a multi - core processor associated with the respective local node 402 . the global memory sections 406 from the nodes 402 are joined together to create a single large distributed global memory 416 . this global memory 416 is addressed on a page level ( e . g ., 4096 bytes ) using fixed logical addressing 418 that is consistent for all nodes 402 . from the point of view of the nodes 402 , the global memory 416 serves as a backing store for virtual memory . importantly , the size of virtual memory cannot exceed that of global memory 416 , and every virtual memory page must actually exist in global memory 416 . thus a distributed virtual memory is implemented , with paging between the local memory of a node and the global distributed shared memory . the size of the local - memory is fixed at boot time . in practice , a minimal local memory 404 of 1 gb per processor - core is recommended . referring again to fig4 , the actual organization of memory within a node 402 may vary depending upon whether or not there is a single memory controller or multiple controllers . for example , in a node 402 with four processors ( i . e ., a multi - core processor ), where each processor physically has memory attached to it , there are four physical memory regions within the node 402 . it is advantageous to divide each of these regions into a local region 404 and global region 406 . the local regions 404 are logically combined and the global regions 406 are logically combined to produce the representation shown in fig4 . the two - tiered memory , with global and local memory , used by the transactional dsm approach was avoided in earlier attempts at implementing dsm . memory was much more expensive at that time , and the idea of wasting it in this way was unthinkable to computer architects . more critical was the fact that the time spent copying pages between global and local memory needed to be minimized . a two - tiered memory requires more page copying in order to keep the global memory updated . however it eliminates the need to have to search the network of nodes for a memory page . the dramatic change in the speed of communication links has meant that it is less time consuming to copy a page than it is to search for a page in a very large memory space . embodiments also include method for the implementation of memory page transaction locks . an application program thread can lock one or more memory pages for exclusive access using an operating system primitive . the lock request is handled by the node which owns the global copy of the targeted memory page . if the lock is granted , that node broadcasts a message to all other nodes invalidating and locking the page . when the lock is released , a broadcast is sent to all nodes unlocking the page . the use of transactional memory moves the responsibility of maintaining memory consistency away from the machine and operating system , to the programmer . the programmer already has the responsibility of synchronization of threads that access shared resources including data structure in memory . adding the responsibility of knowing when memory pages must be locked or updated to global memory should not be a great burden . more importantly , the operating system has no way of determining when to execute these operations without knowing the true intent of the programmer . the only alternative the operating system has is to lock memory pages on all vulnerable operations , which will dramatically decrease performance . to aid the programmer in achieving and maintaining system wide memory coherency , three transactional memory primitives are provided : sync , lock , and release . the sync primitive forces an immediate update of a local memory page to global memory . the lock and release support exclusive access to a global memory page . embodiments also include method for the implementation of distributed thread management on an underlying network of smp servers that support distributed shared memory . the method reproduces the smp program execution model across multiple servers . all application programs are started in the head server node . the program may then fork additional execution threads that run in the same node , or in a worker node . if a thread is forked to a worker node , the memory environment of the program is duplicated in the worker node , by copying page tables , etc . a thread is then launched on the worker node and memory pages are copied from global memory as needed to support execution of the thread . the head node maintains a global thread table of threads executing on remote nodes . fig5 shows a smp computing system 500 that includes two smp servers 502 a , which acts as a head node , and 502 b , which acts as a worker node . each server includes a local memory 504 a , 504 b and a global memory portion 506 a , 506 b , which are concatenated with other global memory portions 506 a , 506 b to form a global shared memory 516 that store reference copies of memory pages for access by the multi - core processors associated with the servers 502 a , 502 b . as shown in fig5 , the implementation of distributed threads , with threads forked by a process running in the head node 502 a on to worker nodes 502 b , takes advantage of the two - tiered memory used by dsmp . since all of virtual memory is actually contained in the global shared memory 516 , a thread created on a worker node 502 b can address the identical address space of the parent thread on the head node 502 a provided that page tables 522 a and 522 b in the nodes 502 a and 502 b are identical . in fig5 , a parent thread 520 a in smp server 502 a ( the head node ) forks a thread in a remote node 502 b by first cloning its virtual memory area ( vma ) and page tables 522 a and 522 b , then creating a thread 520 b in the remote node 502 b that points to the cloned vma . in the head node 502 a , a distributed thread table keeps track of remote threads . yet another embodiment is a method for the implementation of distributed mutex management on an underlying network of smp servers . synchronization between threads on different nodes is accomplished by extending the mutual exclusion lock ( mutex ) function to operated globally across all the nodes in the system . this is accomplished by adding a distributed mutex table to each node . whenever a mutex is created on the head node , a corresponding mutex is created on every worker node . the distributed mutex table handles the mapping between a global distributed mutex and its local version . all locks or waits on a mutex are first filtered through the global distributed mutex table to handle those cases where the mutex is remotely addressed . still another embodiment includes a method for the implementation of distributed disk i / o on an underlying network of smp servers . in most high performance computing problems , a major bottleneck exists around input / output devices . when a write is invoked , the entire process can be stalled due to write requests to slow input / output devices such as a hard - disk drives . to address this bottleneck , a new distributed queue mechanism is provided that allows messages up to a memory page in length to be sent between nodes . all direct disk access is assumed to occur from the head node . the method is designed to extend disk access to threads running in worker nodes . in addition , the method provides non - contentious access to disk writes that do not require waiting on a mutex . the method uses a message queue in the head node that accepts messages that are the size of a memory page . this allows writes of a logical data record to a file that are up to 4k bytes , for example . this is used to post output records from threads running in any node on the system to an input / output ( i / o ) server on the head node . using this mechanism , a replacement buffered i / o interface is provided to programs . embodiments further include a method for handling false sharing of independent variables in a distributed shared memory environment . this is accomplished by extending the operating system memory allocation to include a primitive that forces the requested allocation to begin on a new memory page boundary . using this feature , the programmer can separate independent variables when needed . while this invention has been particularly shown and described with references to example embodiments thereof , it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the scope of the invention encompassed by the appended claims . embodiments of the invention or portions thereof implemented in the form of hardware , firmware , or software . if implemented in software , the software may be any language capable of performing embodiments as discussed herein . the software may be stored as machine executable instructions on any form of machine readable medium , such as ram , rom , cd - rom , loaded by a processor , and executed by the processor .