a two pole switch - capacitor filter circit is shown in fig1 having a first input terminal 11 and a second input terminal 12 and also having an inverting integration circuit shown enclosed in the dashed lines 14 . the inverting integration circuit 14 may be of any type known to those skilled in the art , however , in the exemplary embodiment shown in fig1 the integration circuit 14 consists of an operational amplifier 19 having an inverting input 21 and a non - inverting input 22 and an output 20 . the output 20 of the operational amplifier 19 also represents the output 15 of the integration circuit 14 . the non - inverting input 22 is connected to a reference potential indicated at 17 . the output 20 of the operational amplifier is connected to the inverting input 21 for negative feedback through a feedback capacitor 13 having a capacitance value of c o . the first input terminal 11 is connected to a first circuit node 7 through a first switch s21 and to a second circuit node 8 through a second switch s33 . a first capacitor 10 is interconnected between the first circuit node 7 and the reference potential 17 and a second capacitor 16 is interconnected between the second circuit node 8 and the reference potential 17 . the second input terminal 12 is also connected to the reference potential 17 as well as to the first and second capacitors 10 and 16 . the first and second capacitors 10 and 16 also have a capacitance value of c o . a third switch s31 is interconnected between the output 15 of the integration circuit and the second circuit node 8 , and a fourth switch s43 is interconnected between the output 15 and the first circuit node 7 . a fifth switch s12 is interconnected between the inverting input 21 and the first circuit node 7 , and a sixth switch s24 is interconnected between the inverting input 21 and the second circuit node 8 . a clock pulse diagram for operating the circuit shown in fig1 is illustrated in fig2 comprised of clock pulse phases 1 , 2 , 3 and 4 . the duty times of the pulses shown in fig2 represent times during which the respective switches shown in fig1 are closed . the clock pulse controlling each of the switches shown in fig1 have been indicated in fig1 next to each switch . thus , the first and third switches s21 and s31 are each closed during the duty time of clock pulse phase 1 , the second and fourth switches s33 and s43 are closed by clock pulse phase 3 , the fifth switch s12 is closed by clock pulse phase 2 and the sixth switch s24 is closed by the clock pulse phase 4 . as indicated in fig1 by the numerals in parenthesis , the circuit can also be operated by closing the switch s31 by clock pulse phase 2 , switch s43 by clock pulse phase 4 , switch s12 by clock pulse phase 3 and switch s24 by clock pulse phase 1 . it will be understood that all of the switches s31 , s43 , s12 and s24 must be consistently operated in one manner or the other . as shown in fig2 the clock phases 1 , 2 , 3 and 4 have non - overlapping sequential pulses and each have the same frequency . the clock pulses have a period of 2t and thus exhibit a frequency of 1 / 2t which is equal to one half of the sampling frequency 1 / t . if the switches shown in fig1 are operated in either of the above - described modes of switch sequencing , during the first clock phase 1 the first capacitor 10 is charged and at the same time the second capacitor 16 is connected to the output 15 of the inverting integration circuit 14 . the first capacitor 10 then discharges to the feedback capacitor 13 and subsequently in the third clock phase the first capacitor 10 is charged from the output of the integration circuit 14 . at the same time the second capacitor 16 is connected across the first and second terminals 11 and 12 . finally , in the fourth clock phase the second capacitor 16 discharges to the feedback capacitor 13 . as stated above , the circuit is preferably operated with the capacitors 10 , 13 and 16 each having the same capacitance value , namely c o . the equivalent circuit to the circuit shown in fig1 is illustrated in fig3 with the charge q l ( z ) being transferred in the inductance l and the charge q c ( z ) being transferred in the capacitor c . the total charge is designated as q ( z ) and a voltage drop u ( z ) occurs . in order to achieve a resonance frequency which is one - sixth of the sampling frequency , namely f / 6 , the equivalent parallel resonance circuit shown in fig3 is realized employing the circuit shown in fig1 with the charge q ( z ) being received at the input terminal 11 and a voltage drop u ( z ) occurring across the terminals 11 and 12 , when the capacitors 10 , 13 and 16 are selected to have a capacitance c o = c + c l , where c l = t 2 / 4l and c = 3c l resulting in c o = t 2 / l . in general , the circuit shown in fig1 and 3 can also be utilized to achieve a grounded parallel oscillating circuit if the first and second capacitors 10 and 16 as well as the integration circuit 14 are connected to a reference potential . this embodiment is shown in fig1 by the reference potential desiganted at 17 to which the capacitors 10 and 16 and the input terminal 12 are connected . the circuit shown in fig1 can also be operated free of reference potential . a circuit for realizing a floating parallel resonance circuit having a resonance frequency which is one - sixth of the sampling frequency is shown in fig4 . the term floating parallel resonance circuit means a resonance circuit having one side which is not connected to a reference potential . comparing the circuits shown in fig1 and fig4 it will be apparent that the circuit of fig4 employs the fundamental circuit elements shown in fig1 and operates utilizing the four clock phases shown in fig2 . for those common elements , identical reference numerals are utilized in fig1 and 4 and the operation of the common elements to both circuits is the same and will not be repeated in connection with fig4 . elements shown in fig4 not present in fig1 include a seventh switch s13 operated by clock phase 3 , an eighth switch s11 operated by clock phase 1 , a ninth switch s14 which is closed during the duty times of both clock phase 1 and clock phase 4 or both clock phase 1 and clock phase 2 , and a tenth switch s23 which is closed during the duty times of both clock phase 2 and clock phase 3 , or both clock phase 3 and clock phase 4 . the latter mode of operation of the switches s14 and s23 is utilized if the switches s31 , s43 , s12 and s24 are operated in the mode shown in parenthesis . the eighth switch s11 is interconnected between the second terminal 12 and a third circuit node 7 &# 39 ;, while the tenth switch s23 is interconnected between the third circuit node 7 &# 39 ; and the non - inverting input 22 of the amplifier 19 . the first capacitor 10 is also connected to the third circuit node 7 &# 39 ;. similarly , the seventh switch s13 is interconnected between a fourth circuit node 8 &# 39 ; and the second terminal 12 and the ninth switch s14 is interconnected between the fourth node 8 &# 39 ; and the non - inverting input 22 of the amplifier 19 . the second capacitor 16 is also connected to the fourth circuit node 8 &# 39 ;. as with the circuit shown in fig1 the circuit in fig4 operates as a parallel resonance circuit having a resonance frequency which is one - sixth of the sampling frequency when the capacitor values c o are chosen as described above in connection with the equivalent circuit shown in fig3 . a further variation of the circuits shown in fig1 and 4 is shown in fig5 which utilizes only three clock phases which are illustrated in fig6 as clock pulse phases 1 &# 39 ;, 2 &# 39 ; and 3 . as with the clock pulse phases shown in fig2 the clock phases shown in fig6 are sequential and non - overlapping , however , the phases shown in fig6 have a period of 3t . again , elements common to fig5 and 1 which have already been identified and the operation thereof explained will not be repeated in describing the operation of fig5 . elements in fig5 not present in fig4 and 1 include an eleventh switch s22 operated by the clock phase 3 &# 39 ; which is interconnected between the first terminal and a fifth circuit node 9 . a twelfth switch s51 operated by the clock phase 1 &# 39 ; is interconnected between the node 9 and the inverting input 21 of the amplifier 19 . in similar fashion , a thirteenth switch s32 operated by the clock phase 3 &# 39 ; is interconnected between the second terminal 2 and a sixth circuit node 9 &# 39 ; and a fourteenth switch s15 which is closed during the duty times of both clock phases 1 &# 39 ; and 2 &# 39 ; is interconnected between the sixth node 9 &# 39 ; and the non - inverting input 22 of the amplifier 19 . when operated in the circuit shown in fig5 in contrast to the operation in fig4 the ninth switch s14 is closed during the duty times of both clock phases 3 &# 39 ; and 1 &# 39 ; and the tenth switch s23 is closed during the duty times of both of the clock phases 2 &# 39 ; and 3 &# 39 ;. a third capacitor 18 , also having a capacitance c o , is interconnected between the fifth and sixth circuit nodes 9 and 9 &# 39 ; and is connected to the output 15 of the inverting integration circuit 14 via a fifteenth switch s41 which is operated by the clock phase 2 &# 39 ;. the remaining switches shown in fig5 are operated by the clock phase shown nearest the switch , and in particular the first switch s21 is operated by the clock phase 1 &# 39 ;, the second switch s33 is operated by the clock phase 2 &# 39 ;, the third switch s43 is operated by the clock phase 3 &# 39 ;, the fourth switch s31 is operated by the clock phase 1 &# 39 ;, the fifth switch s12 is operated by the clock phase 2 &# 39 ;, the sixth switch s24 is operated by the clock phase 3 &# 39 ;, the seventh switch s13 is operated by the clock phase 2 &# 39 ;, and the eighth switch s11 is operated by the clock phase 1 &# 39 ;. although only one additional capacitor 18 was added in the embodiment shown in fig5 further capacitors also having a value c o can be added in the same manner if needed . circuits with such additional capacitors , as well as the circuit shown in fig5 operate in accordance with the rule that the sampling frequency 1 / t is equal to ( 2 + n ) times the value of the clock frequency shown in fig6 where n is the number of additional capacitors such as 18 . the additional capacitors are connected alternately to the capacitors 10 and 16 , to the pair of terminals 11 and 12 , and to the output 15 of the integration circuit 14 and each discharge to the capacitor 13 , as shown by the operation of the single additional capacitor represented by the third capacitor 18 in fig5 . as discussed above , each of the circuits shown in fig1 and 5 achieves a parallel resonance circuit having a resonance frequency which is one - sixth of the sampling frequency which can be integrated with relative ease and moreover insures that even during the switching of the individual switches the negative feedback between the output 20 of the amplifier 19 and the inverting input 21 through the capacitor 13 in the integration circuit 14 can be continuously maintained . although modifications and changes may be suggested by those skilled in the art it is the intention of the inventor to embody within the patent warranted hereon all changes and modifications are reasonably and properly come within the scope of his contribution to the art .