according to the invention and the following description the term “ sub - sampling based ” means that the output signal 3 of the frequency synthesizer having a frequency f out is sampled with a sampling unit with a sampling frequency f smp to obtain a time discrete signal , wherein f smp & lt ;& lt ; f out . by sub - sampling or under - sampling the frequency f out is mapped to a frequency f bs in the range from − f smp / 2 to + f smp / 2 . by sub - sampling , the power consuming frequency division unit or counters counting the zero crossings or cycles in the output signal of the frequency synthesizer are replaced by a sampler which consumes considerably less energy . for an ieee 802 . 15 . 4 transceiver f out has a frequency in the range of the 2 . 4 ghz band . in the embodiment described below a sampling frequency of 16 mhz is used . fig1 shows a block diagram of a frequency synthesizer 2 according to the invention . the frequency synthesizer comprises a feedback loop with the following components : a frequency or phase detection unit 4 , a digital - to - analog convertor 5 , a loop filter unit 6 , a voltage controlled oscillator unit 7 , a frequency shift unit 9 and a sampling unit 8 . in case of a sub - sampling based phase locked loop ( pll ) frequency synthesizer , the detection unit 4 is a phase detection unit . the phase detection unit 4 comprises a first input for receiving a reference frequency signal f ref and a second input for receiving a variable frequency signal . the phase detection unit 4 could be in the form of any suitable phase detector circuitry . the sampling unit 8 samples the signal at the input to obtain a multi - bit output signal , for example an 8 - bit signal . a multi - bit output signal is necessary to have phase information available in the signal . the phase detection unit 4 is configured to generate a phase difference output signal which is a function of a difference in phase between the signals supplied to its inputs . this phase difference signal is converted to an analog signal and which is filtered by the loop filter to obtain the signal to control the vco unit 7 . in case of a sub - sampling based frequency locked loop ( fll ) frequency synthesizer , the frequency detector unit 4 comprises a first input for receiving a reference frequency signal f ref and a second input for receiving a variable frequency signal . the frequency detector unit 4 is configured to generate a frequency difference output signal which is a function of a difference between a frequency value associated with the reference frequency signal f ref and a frequency value associated with the variable frequency signal . the frequency difference output signal is an error signal indicating the frequency offset of the sub - sampled output signal of the frequency synthesizer from the desired reference frequency indicated by the signal f ref . the digital - to - analog convertor 5 is configured to convert the frequency difference signal in to an analog frequency difference signal . in an embodiment the digital - to - analog convertor 5 comprises a delta sigma modulator ( dsm ) to convert the frequency difference output signal , which is a signal in the digital domain , in to an analog frequency difference signal . the digital - to - analog convertor is in an embodiment arranged to convert digital signal received at its input into a current at its output . in this embodiment de dsm comprises a charge pump so that a charge can be pumped into the loop filter unit 6 . the loop filter unit 6 is configured to receive the analog frequency difference output signal to provide a smoothed control signal . the loop filter unit 6 comprises electronic components such as resistors , capacitors and is configured to attenuate any signal component above a predetermined frequency . in this way , the loop filter ‘ averages ’ the analog frequency difference signal by removing high frequency components and feeds the result to the control input of the voltage controlled oscillator ( vco ) unit 7 . signal components with a frequency higher than the loop filter cut - off frequency which are provided to the control input of the vco unit 7 will be treated as frequency noise components at the output of the vco unit 7 . according to the present invention the loop filter unit 6 is preferably a 2 nd order loop filter with an out - of - band attenuation with a roll - off of 12 db per octave . the voltage controlled oscillator unit 7 configured to receive the smoothed control signal and to produce an output signal which frequency is a function of the smoothed control signal . the output signal of the vco unit 7 is supplied to mixer unit 9 . the mixer unit 9 performs a frequency shift on the output signal of the vco unit 7 and supplies a frequency shifted signal to its output . the sampling unit 8 is configured to under - sample the output signal from mixer unit 9 with a predetermined sampling frequency f smp to obtain the variable frequency signal that is applied to the frequency detector unit 4 , wherein the variable frequency signal is a p - bit digital signal , p being a positive integer smaller than 8 . in the following description p = 1 . in said case the sampling unit 8 is a binary sampler and the variable frequency signal is a binary signal with a frequency that can be calculated with the following formula : f bs = f vco − f smp × round ( f vco / f smp ), where f bs is frequency of binary signal , f vco is frequency of output signal and round ( x ) rounds x to the nearest integer value . fig2 illustrates the frequency conversion performed by the sampling unit 8 . the sampling frequency f smp is 16 mhz . the frequency of the under - sample signal at the output of the sampling unit 8 zigzags between 0 and 8 mhz when changing the frequency of the signal at the input of the sampling unit 8 from 2400 mhz - 2480 mhz . fig3 shows the same characteristic as in fig2 but now the channel frequencies for ieee 802 . 15 . 4 2 . 4 ghz channels for both transmission and reception are projected on the zigzag line . it can be seen that there are some channel frequencies that are present on the tips of the zigzag line , i . e . the frequencies at 2408 mhz , 2440 mhz , 2448 mhz and 2480 mhz . for fast frequency measurement and to remain in a linear transfer region of the function f bs ( f vco ), the frequency of the subsampled signal should be in a certain range to combine both accuracy and acquisition time . in that case a frequency - conversion is necessary for certain input - frequencies prior to sampling to convert the signal at the input of the sampling unit to a signal with a frequency that is at distance from 0 mhz and 8 mhz , i . e . at distance from the non - linear parts of the frequency conversion . around frequencies 2400 , 2416 , 2432 , . . . mhz it would be impossible to do fast frequency - measurement and around 2400 , 2408 , 2416 , . . . mhz the function f bs ( f vco ) is not differentiable so it is hard to build a control - loop with such a transfer - function . to provide enough room for frequency variations at the input of the sampling unit , the absolute subsampler output frequency f bs has to be larger or equal to 2 mhz and smaller than or equal to 6 mhz in order to be processed accurately . this means that there needs to be a frequency - shift for certain frequencies in order to have a valid range for the next processing stage which is the sampler . table 1 shows a possible solution for the ieee 802 . 15 . 4 2 . 4 ghz channel frequencies for both reception mode rx based on a 2 mhz if and transmission mode tx with direct modulation . column ‘ out no mix ’ shows the output frequency in case no mixing is used . column f_lo shows the lo frequency used for mixing and column ‘ out with mix ’ shows the output frequency with mixer . fig3 shows the results of table 1 graphically . shown is the zigzag characteristic illustrating the effect of under sampling a signal with a given input frequency f in and the corresponding output frequency f bs . the channel frequencies are indicated by the squares ( no mix ) and the corresponding output frequency with frequency shift are indicated by circles ( with mix ). according to table 1 , the used frequency shift depends on the input frequency f in of the channel frequency . channel frequencies that will be converted by the under - sampling to signal with a frequency in the range of 2 - 6 mhz do not have to be shifted prior to sampling . channel frequencies that will be converted to a signal with a frequency that is below 2 mhz or above 6 mhz are frequency shifted by − 4 mhz or + 4 mhz . in fig3 the process of the frequency shift is illustrated in more detail for four ieee channel frequencies c12r , c12t , c15r and c15t . for ieee channel 12 receiving mode the frequency of the signal at the output of the frequency synthesizer is 2408 mhz . after down - sampling this signal with a 16 mhz sampling clock , a signal with a frequency of 8 mhz will be obtained . as there is always some noise in the signal , the frequency will vary around 2408 mhz . if the frequency decreases , the frequency after sampling decreases . if the frequency increases , the frequency after sampling also decreases . consequently , the deviation in frequency after sampling does not provide information whether the frequency is lower or higher than the desired frequency and could therefore not be used as control signal to control the loop of the frequency synthesizer . to overcome this problem , according to the invention the 2408 mhz signal is shifted over + 4 mhz . now a signal with a frequency of 2412 mhz is supplied to the input of the sampling unit . this intermediate frequency is indicated in fig3 with an x . after sub - sampling with 16 mhz a signal with a frequency of 4 mhz will be obtained . the result of frequency shift and under - sampling is indicated by the circle below square c12r . similarly , ieee channel 12 transmission mode with a frequency of 2410 mhz , indicated by square c12t , is shifted with + 4 mhz to an intermediate signal with a frequency of 2414 mhz , which results in a signal with a frequency of 2 mhz after under - sampling . in the same way , the ieee channel 15 receiving mode and transmission frequencies , squares c15r , c15t , of 2423 and 2425 mhz are shifted by + 4 mhz prior to sub - sampling and after sub - sampling have a frequency of 5 and 3 mhz , respectively . the frequency shifts have been chosen such that for both transmission mode and receiving mode , the derivative of the sampler output frequency fbs as function of input frequency after sub - sampling has the same sign in both transmission mode and receiving mode . this has the advantage , that when switching between transmission mode and receiving mode no correction is necessary to have a correct sign of the loop gain . the derivative of the frequency for both the transmission frequency and the receiving frequency has the same sign if the frequency of the signal supplied to the sampling unit complies with the following equation : ( f smp / 2 )× truncate ( f mix , t / f smp / 2 )& lt ; f mix , r & lt ;( f smp / 2 )×( 1 + truncate ( f mix , t / f smp / 2 )) wherein f smp is the sampling frequency , f mix , t is the frequency of the selected ieee channel transmission mode after the desired frequency shift , f mix , r is the frequency of the selected ieee channel receiving mode after the desired frequency shift and truncate is a function which truncates a value to an integer value . it should be noted that instead of a frequency shift of + 4 mhz prior to sub - sampling the 2423 mhz and 2425 mhz of ieee channel 15 frequencies , a frequency shift of − 4 mhz could be used . the necessary frequency shift or conversion action could be implemented with single side band ( ssb ) such as the well - known hartley modulator . fig4 shows the architecture of a hartley modulator . the hartley modulator receives a quadrature phase signal rf - i , rf - q at its input . the quadrature phase input signal is mixed with a quadrature local oscillator signal lo - q , lo - i . the frequency of the quadrature local oscillator ( lo ) signal corresponds to the desired frequency shift . the rf - i signal is mixed with the lo - q signal and the rf - q signal is mixed with the lo - i signal . subsequently both mixed signals are combined by means of an adding function to obtain a frequency shifted signal which is shifted version of the original rf signal shifted over the lo frequency . this embodiment has the disadvantage of increased costs due to component count and reduced performance in terms of current - consumption and lo leakage . fig5 shows an embodiment of the invention wherein a binary sub - sampler 8 is coupled to the output of a frequency shift unit 9 which is based on a hartley modulator architecture . in this embodiment , the frequency - conversion or frequency shift is accomplished by a switching mixer 9 a . this switching mixer 9 a is driven by a set of low - frequency ( lf ) lo control signals which are generated by a lf lo control generator 9 b . the lf lo control generator 9 b derived its lo control signals from the sampling clock signal x smp with a sampling frequency f smp . by means of a counter , easily lo control signals could be generated with a frequency which is ½ , ¼ or ⅛ of the sampling frequency . with a sampling frequency of 16 mhz , easily a frequency shift of − 4 mhz , − 2 mhz , − 1 mhz , 0 mhz , + 1 mhz , 2 mhz and 4 mhz could be realised . the lo control signals are synchronized to the sampling - clock in such a way that the edges of the lo control signals never coincides with the sampling moment of the binary sampler 8 . this could be done by having the sampling moments be responsive to the falling edge of the sampling clock signal x smp and having a change in the lo control signals responsive to a rising edge of the sampling clock signal . in another embodiment , the sampling moments are responsive to the rising edge of the sampling clock signal x smp and have a change in the lo control signals responsive to a falling edge of the sampling clock signal . in this way , the signals at the output of the frequency shift unit 9 are stable when the sampling unit 8 samples the signal . the embodiment in fig5 is a balanced embodiment . the binary sub - sampling unit 8 with a frequency - shift unit 9 consists of : a rf mixer 9 a consisting of 8 single - pole single throw switches 9 c , 9 c ′ which connects the 4 balanced quadrature phase rf signals rf - ip , rf - in , rf - qp and rf - qn to a binary sampling unit 8 . the switches are controlled by balanced quadrature lf lo signals lo - ip , lo - qp , lo - in and lo - qn which are generated by : a lf lo - generator ( 9 b ) which generates 4 quadrature lo signals with frequency f_lo ( for instance 4 mhz ) from a clock signal x smp with frequency f smp ( for instance 16 mhz ). a binary sampler ( 8 ) which converts the rf mixer output signals if_p and if_n into a bit - stream . the lf lo signals generated by ( 9 b ) are synchronized to the sampling - clock x smp in such a way that the mixer switching moment never coincides with the sampling moment , for instance by sampling at the positive edge of x smp while switching the mixer at negative edges of x smp . synchronization of the switching moments and the sampling moment avoids any lo leakage into the sampler . furthermore , it will not be possible that a sample will become invalid in case the mixer switches at the sampling moment . the frequency shift unit 9 has a structure which corresponds to a hartley modulator scheme . a difference with existing systems is that the lf lo signal is derived from the sampling clock signal x smp . the lf lo signal is synchronized to the sampling clock such that the frequency of the lo signal is f shift = f smp / k in which k is an integer and depends on the desired rf signal generated by the frequency synthesizer . the mixer is implemented with switches to perform the mixing function . this has the advantage of reduced required chip - area in case of an integrated circuit implementation . in stead of 8 single - pole single throw switches , 4 single - pole double throw could be used . this allows to reduce the number of quadrature lo signals to two signals . the operation of the circuit in fig5 is demonstrated in fig6 . the signals shown in fig6 could be found with a corresponding reference in the block diagram shown in fig5 . in this example of operation , the frequency of the rf signal , frf , is an exact multiple of the sampling signal xsmp . this could for example be the ieee channel 20 receiving mode frequency of 2448 mhz or the ieee channel 26 transmission mode frequency of 2480 mhz . furthermore , the phase of the rf - signal at the sampling moment ( which is the positive edge of the clock ) happens to be 30 degrees . without mixing or mixing with a f shift = 0 , the signal at the output of the binary sampler out will be constant . the lo frequency used for the frequency shift is : f shift = f smp / 4 . in fig6 are shown in time from above respectively , the sampling moments , the sampling clock signal x smp , the four control signals generated by the lf lo generator unit 9 b , lo_ip , lo_qn , lo_in and lo_qp that drive the switches 9 c , 9 c ′, the phase of the lo control signals at the sampling moment , the phase of the rf signal on sampling moment , the intermediate differential signal if_p , if_n after frequency shift at the input of the sampling unit and the bit stream signal out at the output of the sampling unit . it can be observed that the switching moments of the switches occur at the negative or falling edge of x_smp and the sampling moments occur at the positive or rising edge of x_smp . the row ‘ if signal from rf signals ’ shows how the differential if signal if_p − if_n depends on the rf signals rf_ip , rf_in , rf_qp , rf_qn : due to the mixing action there are four possibilities : at the every sampling moment in fig6 , rf_ip has the value + ½sqrt ( 3 ), rf_in has the value − ½sqrt ( 3 ), rf_qp has the value ½ and rf_qn has the value − ½ . at the first sampling moment lo_in and lo_qp are 1 . now if_p = rf_ip + rf_qn = ½sqrt ( 3 )+− ½ = 0 , 366 and if_n = rf_in + rf_qp =− ½sqrt ( 3 )+ ½ =− 0 , 366 which results in a “ 1 ” at the output of the sampling unit . at the second sampling moment lo_ip and lo_qp are 1 . now if_p = rf_ip + rf_qp = ½sqrt ( 3 )+ ½ = 1 , 366 and if_n = rf_in + rf_qn =− ½sqrt ( 3 )+− ½ =− 1 , 366 , which results in a “ 1 ” at the output of the sampling unit . at the third sampling moment lo_ip and lo_qn are 1 . now if_p = rf_in + rf_qp =− ½sqrt ( 3 )+ ½ =− 0 , 366 and if_n = rf_in + rf_qn = ½sqrt ( 3 )+− ½ =+ 0 , 366 , which results in a “ 0 ” at the output of the sampling unit . at the fourth sampling moment lo_in and lo_qp are 1 . now if_p = rf_in + rf_qn =− ½sqrt ( 3 )+− ½ =− 1 , 366 and if_n = rf_ip + rf_qp = ½sqrt ( 3 )+ ½ = 1 , 366 , which results in a “ 0 ” at the output of the sampling unit . it can be observed that with the proposed circuit the output frequency of signal out at the output of the sampling unit is now 4 mhz due to the frequency shift action of the frequency shift unit 9 . the frequency transfer function of f rf to f out is a linear function now . it should be noted that fout corresponds to fbs in fig3 . linearity is important when applying the combination of a frequency shift unit and sampling unit in a control - loop of a frequency synthesizer . fig7 shows another embodiment of a combination of frequency shift unit and sampling unit . a single - ended quadrature phase rf - signal is supplied to the frequency shift unit 9 and a balanced frequency shifted signal if - p , if - n is supplied to the sampling unit 8 . this embodiment comprises a switch 9 d to the supply voltage and a switch 9 e to ground . these switches ensure that the signals if - p and if - n will never be floating at the sampling moment . the present invention provides a combination of a frequency shift unit 9 or mixing unit and sub - sampling unit 8 that allows to obtain a sub - sampling based locked loop with a closed loop response similar to a pll but having improved settling time and improved suppression of high frequency components of the quantization noise due to the sampling process . the invention allows to obtain a frequency synthesizer with improved characteristics with respect to at least one of power consumption , locking characteristic , design optimization characteristics compared to non - sub - sampling pll based frequency synthesizers . an application in which the invention could be used is to measure the frequency modulation - index of a frequency modulated signal . the measures described hereinbefore for embodying the invention can obviously be carried out separately or in parallel or in a different combination or if appropriate be supplemented with further measures ; it will in this case be desirable for the implementation to depend on the field of application of the transceiver . the invention is not limited to the illustrated embodiments . changes can be made without departing from the idea of the invention . in the claims , any reference signs placed between parentheses shall not be construed as limiting the claim . use of the verb “ to comprise ” and its conjugations does not exclude the presence of elements or steps other than those stated in a claim . the article “ a ” or “ an ” preceding an element does not exclude the presence of a plurality of such elements . the invention may be implemented by means of hardware comprising several distinct elements , and by means of a suitably programmed computer . in the device claim enumerating several means , several of these means may be embodied by one and the same item of hardware . the mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage .