many of the elements illustrated in the drawings are duplicates of each other . in general , only one such element will be illustrated in detail while all the others will be shown in block form . where a plurality of elements are used , each will be given a base reference character followed by a - number . a common practice of assigning zero to the initial unit of each series will be followed . thus , where 40 units are utilized , they will be identified as - 0 through - 39 . referring to fig1 the system comprises a group of 40 line - group networks lg - 0 through lg - 39 each of which includes a pair of multiplexers m - 0 and m - 1 and a plurality of 32 line circuits l - 0 through l - 31 . the multiplexers m - 0 and m - 1 in turn are connected to the respective line - module controllers lmc - 0 and lmc - 1 through common buses b - 0 and b - 1 and 40 individual group select leads gs - 0 and gs - 39 . the duplicated line module controllers lmc - 0 and lmc - 1 are connected to a central switching network ( not shown ) through four duplicated input ports p0 - 0 through p3 - 1 , and p4 - 0 through p7 - 1 respectively , via dual multiple data links mdl . each input port p0 - 0 through p7 - 1 has a capacity of 30 input channels in 32 time slots allowing two time slots for supervision and control . under normal operation , each controller functions as the primary controller for one - half the line - group networks and hence accesses one - half the 1280 ( 32 × 40 ) line circuits . normally therefore , 640 line circuits have access to 120 ( 4 × 30 ) channels in the switching network through each controller . however , should one primary controller lmc - 0 or lmc - 1 or any one of its associated operating multiplexers m - 0 or m - 1 be rendered unserviceable , the other controller functioning as a secondary to it , will take over control of all 1280 line circuits . since all 1280 line circuits must now share the 120 rather than 240 available channels , access to the switching system may be affected during peak traffic periods . the function of each of the controllers lmc - 0 and lmc - 1 includes scanning for originating calls , collecting digits , assigning channels to lines , controlling application of ringing signals or tones to the lines , and communicating with the central control computer in the switching network via at least some of the message channels in the two time slots allotted for supervision and control . referring to both fig1 and 2 , each of the 40 line - group networks comprises the pair of multiplexers m - 0 and m - 1 which are coupled to their respective controllers through buses b - 0 and b - 1 , except for the activity control signal actv which is coupled to only the primary controller lmc - 0 over bus b - 0 ( in this embodiment ). each of the line circuits l - 0 through l - 31 couples the subscriber loops 24 to the 32 separate bidirectional data lines dl - 0 to dl - 31 which in turn are connected in common to both multiplexers m - 0 and m - 1 . the detailed structure of the line - group network in fig2 will be readily apparent from the following detailed description of its function and operation taken in conjunction with the timing waveforms illustrated in fig3 the location of which in each bus is identified by corresponding reference characters . in fig3 boxed waveforms each represent 10 bits of binary information . as mentioned above , two channel time slots 0 and 16 are utilized for supervision and control . during these periods the line circuits l - 0 through l - 32 are selectively scanned by controllers lmc - 0 or lmc - 1 . the remaining channel slots 1 - 15 and 17 - 31 are available for pcm data . in this example embodiment , it is assumed that line circuits 4 , 8 , 17 and 23 ( assigned channel time slots 5 , 13 , 1 and 12 by the controller ) are carrying traffic in one line - group network while line circuits 6 , 14 , 17 and 29 ( assigned time slots 8 , 26 , 20 and 27 by the controller ) are carrying traffic in one or more of the other line - group networks , for the duration of the respective telephone calls . in addition , line circuits 8 and 9 of the said one line - group network are scanned during time slots 0 and 16 respectively of one frame , while channel 10 of another line - group network is scanned during time slot 0 of the following frame . the balance of the channels for this port are idle at this time . the 10 - bit addresses addr for the networks normally from their primary controller , are transmitted over buses b - 0 and b - 1 to serial / parallel converters 10 . after a complete address is received , the parallel output of converter 10 is loaded into a receive address register 11 under control of a group select signal g - s and a channel pulse c - p ( which indicates the beginning of each 10 - bit channel period ) during the succeeding time slot . the output of the register 11 then enables a demultiplexer 12 which then accepts the received serial data rdat which is coupled through an and gate 13 , under control of a delayed group select signal g - s , to the signal input of the demultiplexer 12 . the serial data rdat is steered through the demultiplexer 12 to the selected data line where it is coupled to the input of the selected line circuit l - 0 through l - 32 . in the present example , the address addr for channel 8 in time slot 0 in conjunction with the presence of the group select signal g - s , causes the received control data rctl on the receive data path rdat to be directed to the line circuit l - 8 during time slot 1 . similarly , the address addr during time slot 1 together with g - s causes the received pcm data rpcm on the receive data path rdat to be directed to the line circuit l - 17 during time slot 2 , and so on . however , the address for channel 6 which occurs during time slot 8 will not enable the demultiplexer 12 in the one group select network due to the absence of the delayed group select signal g - s at the input to the and gate 13 ( n . b .- rdata in fig3 ). it will however enable an alternate group - select network if the signal g - s is applied to it over another group select lead g - s as shown in fig1 . at the end of time slot 1 , the address in register 11 is shifted to transmit address register 14 which enables the multiplexer 15 so as to steer incoming information tdata from the selected line circuit to the transmit data path tdat through an and gate 16 which is opened by the group - select signal g - s that has now been delayed two time slots . this is illustrated in fig3 where the scan information xscn from line circuit 8 is transmitted during time slot 2 over data line dl - 8 and the xpcm information from line circuit 17 is transmitted over the data line dl - 17 and the transmit data path tdat during time slot 3 . the activity signal actv from the primary controller lmc - 0 enables both the clk and demultiplexer 12 . during normal operation , different channel information is transmitted to each of the multiplexers m - 0 and m - 1 since they are driven by controllers lmc - 0 and lmc - 1 respectively , each of which acts as the primary controller for a different half of the 1280 line circuits . however , since each actv signal actuates only one of the multiplexers m - 0 or m - 1 at a time , the channel data going to the non - operating multiplexer is not transmitted through to its associated line circuits . failure of either of the controllers lmc - 0 or lmc - 1 or any one of the operating multiplexers m - 0 or m - 1 is sensed by the other controller as well as the switching network . this causes the actv signal to be removed from the affected multiplexer in each of the line - group networks lg - 0 through lg - 39 , thereby resulting in the other multiplexer of that network taking over . concurrently the channel information for that line - group network is routed from the switching network through the secondary controller to its associated multiplexer . hence , the line circuits l - 0 through l - 31 continue to function over the common data line dl . the non - operating multiplexer is monitored continuously by its associated controller through test codes sent via rdat , tdat , using special address codes . detection of a failure causes an alarm for repair but no switch - over of the system . referring again to fig3 the group - select signal g - s together with the serial address signal addr determines during each channel period the line to be accessed from the controller during the succeeding two time slots . actual data ( pcm or control / scan ) is transmitted serially over the receive data rdat bus to the line group and over the transmit data tdat but to the controller . each data exchange extends over periods of three channel time slots . in the first period , the line address is transmitted ; in the second period , data is received from the controller by the line circuit ; in the third period , data is transmitted from the line circuit back to the controller . thus , during the second and third periods , the operating multiplexer m - 0 or m - 1 is transparent to data being transmitted or received from the selected line circuits . the access to different line circuits in successive transaction periods overlaps the time to allow effective use of all 32 channel time slots . the only restriction is that the same line not be accessed in successive channel time slots . thus , in the example embodiment , pcm data information for channel 8 cannot be received or transmitted during time slots 1 and 2 since the control and scan information for that channel occupies these periods . to avoid overlap , even scanning / control addresses are transmitted during time slot 0 while those for pcm data for the even address lines are never transmitted during time slots 31 or 1 . odd scanning / control addresses are transmitted during time slot 16 while those for pcm data for the odd address lines are never transmitted during time slots 15 or 17 . various other arrangements are also possible . referring again to fig2 and the expanded portions of fig3 data on the data line dl - 8 ( not specifically shown in fig2 -- refer to typical data line dl - 1 and line circuit l - 1 ) is received by the line control circuit 21 in the line circuit l - 1 under control of the clock clk . each 20 bit exchange between the line circuit and the controller is initiated by a start bit s = 1 ( not the expanded portions of fig3 ). this is followed by a mode bit m = 1 which indicates that control / scan information will follow or m = 0 which indicates that pcm information will follow . after reception of the bit m = 1 , 8 bits of control data rctl are transmitted from the controller to the line control circuit 21 . this information which provides control for ringing , or operation of numerous test functions , is steered to the scan and control registers 22 where it is utilized to actuate a line interface circuit 23 which is connected to the subscriber loop 24 . this is followed by 8 bits of scanning information xscn , which transmits status and dialling information from the line circuit back to the controller . finally , line status ls and on / hook supervision sv bits are transmitted again from the line circuit during the last two bits of the exchange . every line , whether it is carrying traffic or not , is accessed for scanning and control once every n × 5 msec ; 5 msec being the basic cycle time of the controllers . the value of n depends upon the number of lines being scanned and the status of the line ( supervision or dialling ). during an exchange of pcm information , the start bit s = 1 and mode m = 0 are followed by 8 bits of rpcm transmitted from the switching network , through the controller to the line circuit . these 8 bits are steered through the line control circuit 21 to a codec 25 . the codec 25 converts the rpcm signal to analog form for transmission through the line interface circuit 23 to the subscriber loop 24 . conversely , a coded analog sample spcm is transmitted from the codec 25 through the line circuit 21 back through the controller to the switching network . again , line status ls and supervision sv are transmitted at the end of this data exchange to the controller . the s and t leads between the circuits 21 , 22 and 25 provide start and timing information in a well known manner . in an alternate embodiment , the channel information fed to the input ports p0 - 0 through p3 - 1 may be a duplicate of that to ports p4 - 0 through p7 - 1 respectively . with this arrangement both multiplexers m - 0 and m - 1 transmit and receive the same information although at any point in time only one of any pair is activated by the actv signal . in yet another embodiment , several telephone line circuits ( e . g . 4 ) may be served by a single bidirectional data line with all lines in a line - group network ( e . g . 32 ) being accessed in a fixed sequence , from the multiplexer . all line circuits on the single data line are accessed in sequence so that only a single synchronizing pulse ( one per frame ) is required in addition to a clock signal , to identify the start of the sequence . with this arrangement failure of one line circuit could render unserviceable the balance of the line circuits ( e . g . the other 3 ) coupled to its associated bidirectional data line . however , the balance of the lines in the line - group network would be unaffected .