fig8 shows schematically the entire structure of a semiconductor neural network according to an embodiment of the present invention . the structure shown in fig8 corresponds to that of the conventional semiconductor neural network shown in fig7 and the same or equivalent parts are denoted by the same reference numerals . in fig8 the semiconductor neural network employs complementary bit line pairs of bl and bl also as internal data output line pairs . output signal lines of an input register 106a are of a single line structure . amplifying circuits 101 are provided corresponding to the bit line pairs and comprises amplifiers for differentially sensing and amplifying potentials on the corresponding bit line pairs . second transfer gates 115 are provided to connect the bit line pairs ( internal data output line pairs ) of bl1 and bl1 to bl4 and bl4 to the amplifying circuits 101 selectively according to operation modes . the second transfer gates 115 are rendered conductive in response to a connection control signal mux . in operation modes such as learning mode , or self - organizing mode where coupling strengths of the respective coupling elements in the coupling matrix 100 are programmed , the control signal mux falls to &# 34 ; l &# 34 ; to disconnect the coupling matrix 100 from the amplifying circuits 101 . on the other hand , in operation modes such as recalling mode where operational processings are performed on externally applied input data signals , the control signal mux attains the &# 34 ; h &# 34 ; level to connect the coupling matrix 100 to the amplifying circuits 101 . that is , the first and second transfer gates 112 and 115 perform complementary operations to each other . fig9 shows a specific structure of the coupling element tij shown in fig8 . in fig9 the coupling element tij comprises inverting amplifiers in10 and in11 for storing information for a complementary bit line blj , and inverting amplifiers in12 and in13 for storing information for a bit line bl . the inverting amplifiers in10 and in11 are arranged anti - parallel with each other , or cross - coupled to each other to constitute a latch circuit . likewise , the inverting amplifiers in12 and in13 are arranged anti - parallel with each other , or cross - coupled to each other to constitute another latch circuit . the coupling element tij further comprises a switching transistor s5 responsive to a signal potential on the word line wlip for being turned on to connect a node n3 to the bit line blj , a switching transistor s6 responsive to a signal potential on the word line wlip for being turned on to connect another node n1 to the complementary bit line blj , and a switching transistor s7 responsive to a signal potential on the internal data input line ai for being turned on to connect the node n1 to the complementary bit line blj . the coupling strength information stored in the latch circuit constituted of the inverting amplifiers in10 and in11 is transmitted to the complementary bit line blj in response to the signal potential on the data input line ai . the coupling element tij further comprises switching transistors s9 and s10 responsive to a signal potential on the word line wliq to connect nodes n2 and n4 to the bit line blj and the complementary bit line blj , respectively , and a switching transistor s8 responsive to the signal potential on the internal data input line ai to connect the node n2 to the bit line blj . the coupling strength information stored in the storage circuit portion constituted of the inventing amplifiers in12 and in13 is transmitted onto the bit line blj in response to the signal potential on the internal data input line ai . the coupling state of the coupling element tij is determined according to the combination of signal potentials stored at the storage nodes n1 and n2 . when signal potentials of the &# 34 ; l &# 34 ; and &# 34 ; h &# 34 ; levels have been stored at the nodes n1 and n2 , respectively , the coupling element tij indicates the &# 34 ; excitatory state &# 34 ;. when potentials of the same level have been stored at the storage nodes n1 and n2 , no potential difference appears on the bit line pair of blj and blj so that the coupling element tij indicates the &# 34 ; don &# 39 ; t care ( open ) state &# 34 ;. when signal potentials of the &# 34 ; h &# 34 ; and &# 34 ; l &# 34 ; levels have been stored at the nodes n1 and n2 , respectively , the coupling element tij has been programmed to indicate the &# 34 ; inhibitory state &# 34 ;. in the following , operation of the neural network shown in fig8 and 9 will be described with reference to the operation waveform chart of fig1 . when the control signal mux is set to the &# 34 ; h &# 34 ; level and the complementary control signal mux is set to the &# 34 ; l &# 34 ; level , the semiconductor neural network is put in an operation mode where coupling strength data are written in or read out of the respective coupling elements contained in the coupling matrix 100 . the control signal mux determines a period for which storage contents in the storage elements are rewritten to change weighting of the synapse couplings in the self - organizing process , or learning . when the control signal mux attains &# 34 ; h &# 34 ;, the first transfer gates 112 are rendered conductive so that the data register 104 is connected to the coupling matrix 100 . subsequently , a row address and a column address are externally applied to the row decoder 102 and the bit decoder 103 , respectively , to select a corresponding word line ( wlip or wliq ) and a corresponding bit line pair of blj and blj . meanwhile , the ram i / o 106b converts externally applied information of coupling strength din into a complementary data pair and transmits the converted data to the internal data buses i / o and i / o . the complementary data pair transmitted to the internal data buses i / o and i / o is transmitted through a selective gate ( one pair of transistors contained in the gates 111 ) selected by the bit decoder 103 to a corresponding data register to be latched therein . the switching transistors s5 and s6 associated with the selected word line ( for example , wlip ) are turned on connecting the latch circuits constituted of the inverting amplifier circuits to the bit line pairs of blj and blj . as a result , the data latched in the data register is transmitted through the switching transistors s5 and s6 to the storage nodes n1 and n3 to be latched therein . meanwhile , the driving capability of the data register 104 is of course larger than the latching capability of the inverting amplifier circuit of in10 and in11 ( in12 and in13 ). therefore , it is possible to write signal potentials indicative of desired coupling strength information into the storage nodes n1 and n3 . when the word line wliq has been selected , information indicative of a desired coupling strength is written in the latch circuit constituted of the inverting amplifiers in12 and in13 so that signal potentials corresponding to the coupling strength information are stored in the nodes n2 and n4 , respectively . by performing the above - described operation for the respective storage elements of the coupling elements t11 to t44 in the coupling matrix 100 , information of coupling strengths can be programmed in the coupling matrix 100 . this writing of the coupling strength information into the coupling matrix 100 is similar to the data writing operation in a general static random access memory . subsequently , when the control signal mux falls to the &# 34 ; l &# 34 ; level and the complementary control signal mux attains the &# 34 ; h &# 34 ; level , the first transfer gates 112 are put in the non - conductive state and the second transfer gates 115 are rendered conductive , putting the neural network in an operation mode specific to the neural network . an external data signal applied from outside of the neural network chip 200 is first held by the input register 106a and then the thus held external data signal is transmitted from the input register 106a to the internal data signal lines a1 to a4 as an internal data signal . in this operation mode , all the output potentials of the row decoder 102 are fixed at the &# 34 ; l &# 34 ; level so that all the switching transistors s5 , s6 , s9 and s10 ( see fig9 ) contained in the coupling elements are in the off - state . now , when the signal potential on the internal data input line ai rises to the &# 34 ; h &# 34 ; level in response to the internal data signal , the switching transistors s7 and s8 of the coupling element tij are turned on so that the signal potentials stored in the coupling element tij are transmitted to the bit line pair ( internal data output line pair ) of blj and blj . when the coupling element tij has been programmed to be in the &# 34 ; excitatory state &# 34 ;, the bit line blj receives a signal potential of the &# 34 ; h &# 34 ; level and the complementary bit line blj receives a signal potential of the &# 34 ; l &# 34 ; level . when the coupling element tij has been programmed to be in the &# 34 ; inhibitory state &# 34 ;, the bit lines blj and blj receive signal potentials of the &# 34 ; l &# 34 ; and &# 34 ; h &# 34 ; level , respectively . when the coupling element has been programmed to be in the &# 34 ; don &# 39 ; t care ( open ) state &# 34 ;, the bit lines blj and blj receive potentials of the same level . when the signal potential on the internal data signal line ai is at the &# 34 ; l &# 34 ; level , the switching transistors s7 and s8 are in the off state . thus , the coupling element is in a state equivalent to the &# 34 ; don &# 39 ; t care ( open ) state &# 34 ; since no potential change occurs on the bit line pair blj and blj , irrespective of the storage information of the coupling element tij . such changes of signal potentials on the bit line pairs ( internal data output line pairs ), which occur according to the signal potentials on the internal data signal lines , proceeds at a time and in parallel in the respective coupling elements of the matrix 100 . the signal potentials appearing on the bit line pairs of bl1 and bl1 to bl4 and bl4 as a result of the parallel operation are sensed and amplified by the amplifying circuits 101 and then converted into corresponding data signals to be output as neuron output data . in the structure of coupling element shown in fig9 a word line , a bit line and an internal data input line are each connected to the same number of transistors and have the same stray capacitance associated therewith . however , the number of transistors connected to the input portion of one inverting amplifier circuit is different from the number of transistors connected to the output portion of the same circuit . this leads to an imbalanced stray capacitance in one storage element portion and also to imbalanced latching capability of the latch circuit . as a result , the writing or reading operation of the coupling strength information becomes unstable , and in some cases , the coupling strength information may not be precisely stored and read out . in fig1 , there is shown a structure of coupling element which can avoid such an unbalanced stray capacitance in the storage element portion and stabilize the operations of reading and writing the coupling strength information in the storage element portion . in the structure of coupling element shown in fig1 , dummy capacitors c1 and c2 are connected between the nodes n3 and n4 and the internal data input line ai , respectively . the dummy capacitors c1 and c2 are formed by connecting conductive terminals of mis transistors and equalize stray capacitances in the inverting amplifier circuits of in10 and in11 , and of in12 and in13 . in this case , the switching transistors s5 , s6 , s7 , s8 , s9 and s10 and the dummy capacitators c1 and c2 are constituted of mis transistors of the same size . with this structure , the stray capacitances in the storage element portions can be easily balanced , making the reading and writing operations of the coupling strength information stable . fig1 shows a second modified structure of the coupling element shown in fig9 . the coupling element comprises a switching transistor s5 responsive to a signal potential on a first word line wlip ( 1 ) for being turned on to connect the node n3 to the bit line blj , a switching transistor s6 responsive to a signal potential on a second word line wlip ( 2 ) for being turned on to connect the node n1 to the complementary bit line blj , and inverting amplifiers in10 and in11 cross - coupled to each other between the nodes n1 and n3 . the coupling element further comprises a switching transistor s9 responsive to a signal potential on a third word line wliq ( 1 ) for being turned on to connect the node n2 to the bit line blj , a switching transistor s10 responsive to a signal potential on a fourth word line wliq ( 2 ) to connect the node n4 to the complementary bit line blj , and inverting amplifier in12 and in13 cross - coupled to each other between the nodes n12 and n4 . the first and second word lines wlip ( 1 ) and wlip ( 2 ) receive the same row select signal . the third and fourth word lines wliq ( 1 ) and wliq ( 2 ) receive the same row select signal . further , the word lines wlip ( 1 ) and wliq ( 1 ) are used also as an internal data input line ai to receive the same internal data signal . in the basic element structure shown in fig1 , the stray capacitances in the storage element portions can be balanced without providing the dummy capacitors to balance them . furthermore , since the number of transistors constituting a basic coupling element is less , the area occupied by the coupling element can be reduced . additionally , in the basic coupling element structures shown in fig9 and 12 , the double - end structure is employed so that the coupling strength information is written in through both bit line blj and its complementary bit line blj . instead of such structure , a single - end structure may be employed which is obtained , for example , by eliminating the switching transistors s6 and s9 from the coupling element structure shown in fig9 so that information of a desired coupling strength be written in through only one of the paired bit lines . fig1 shows the entire structure of a semiconductor neuron network with coupling matrix 100 having coupling elements as shown in fig1 arranged in 4 rows and 4 columns . in the structure shown in fig1 , the word lines and the internal data input lines share the same signal lines . therefore , in addition to the structure shown in fig8 there are provided connection gates 116 responsive to control signal mux for being turned on to connect row decoder 102 to the coupling matrix 100 and connection gates 117 responsive to complementary control signal mux to connect neuron input register 106a to the coupling matrix 100 . further , since the internal data input lines are required to correspond to the respective two storage element circuit portions of the coupling elements , two signal lines transmitting the same internal data input signal are provided as internal data input lines for a single coupling element . furthermore , a single coupling element requires four word lines , the output signal lines of the row decoder 102 , or word lines are doubled in number when compared with the structure shown in fig8 . for the output signal lines , or the word lines of the row decoder 102 shown in fig1 , word lines denoted by the same reference numeral receive the same row select signal . in such a structure as shown in fig1 where either the neuron input register 106a or the row decoder 102 is connected to the coupling matrix 100 according to operation modes , the word lines and the internal data input lines can share the same signal lines , as previously described . thus , in practice , a doubled number of signal lines are not required , but the number of signal lines increases by only one for one row , so that a coupling matrix occupying a small area can be realized . meanwhile , the semiconductor neural networks shown in fig8 and 13 have non - hopfield &# 39 ; s type structures where paths for feeding back the internal output data signals into the coupling matrix are not provided . however , these structures can be easily modified to constitute hopfield &# 39 ; s type neural networks only with the provision of the feedback paths . fig1 shows an example of structure of a hopfield &# 39 ; s type semiconductor neural network using coupling elements according to the present invention . in fig1 , the hopfield &# 39 ; s type semiconductor neural network according to the present invention comprises inverting amplifiers 120a , 120b , 120c and 120d for inverting outputs of complementary bit lines bl1 , bl2 , bl3 and bl4 and transmitting the inverted outputs to internal data input lines a1 , a2 , a3 and a4 . the inverting amplifiers 120a and 120d allow the internal data output signals from the coupling matrix 100 to be fed back through the internal data input signal lines . thus , a neural network according to the hopfield &# 39 ; s model is configured . fig1 shows an example of structure of a hopfield &# 39 ; s type semiconductor neural network obtained by modifying the non - hopfield &# 39 ; s type semiconductor neural network shown in fig1 . in the semiconductor neural network shown in fig1 , feedback amplifying circuits 121 are provided to transmit signal potentials on the respective bit line pairs of bl1 and bl1 to bl4 and bl4 to the internal data input line pairs a1 to a4 . each of the feedback amplifying circuits 121 comprises an inverting amplifier 20a for inverting potential on a complementary bit line bli and transmitting the inverted potential onto a corresponding internal data input line ai , and inverting amplifiers 20b and 20c connected in series over two stages for transmitting potential on a positive bit line bli onto another corresponding input data signal line ai . in the structure shown in fig1 , the feedback paths are provided in the same manner though both the internal data input lines and the internal data output lines form pairs , so that a hopfield &# 39 ; s type neural network is configured . fig1 shows an example of structure of an inverting amplifier comprised in the storage element portion of a coupling element . in fig1 , an inverting amplifier circuit is formed of a complementary ( cmos ) logic circuit comprising a p - channel mis transistor pmos and an n - channel mis transistor nmos . the structure shown in fig1 is characterized by its large output driving capability and large noise margin . these characteristics allow the circuit to transmit precise coupling strength information onto a corresponding bit line in a reliable manner . fig1 shows another structure of an inverting amplifier comprised in the storage element portion of a coupling element . in the structure shown in fig1 , an inverting amplifier circuit is constituted of a load resistor r1 formed of , for example , polysilicon and an n - channel mis transistor nmos . the resistor r1 transmits a predetermined supply potential vcc to the output portion . the n - channel mis transistor nmos receives an input signal in at its gate and drives the output portion according to its gate potential . since in the structure of inverting amplifier shown in fig1 , the load resistor is employed , the circuit size can be made smaller than that of the inverting amplifier shown in fig1 . while in all the embodiments described above , it has been simply stated that in the operational processings of the neural network , the data register 104 is disconnected from the coupling matrix 104 and instead , the amplifying circuits 101 are connected to the coupling matrix 100 , no reference has been made to initialization of the bit line potentials . in initializing the bit lines that are to be held in the floating state , it takes a long time in the operational processings to establish potentials on the bit lines that have been held at the levels transmitted in programming the coupling strengths of the respective coupling elements in the coupling matrix 100 . on the other hand , if all the bit lines are set either to the &# 34 ; l &# 34 ; or &# 34 ; h &# 34 ; level in the initialization , it takes a long time to establish the &# 34 ; h &# 34 ; or &# 34 ; l &# 34 ; level on the bit lines . this leads to longer charging and discharging time , resulting in an increased power consumption . to overcome such disadvantages , a circuit structure which can drive the bit lines reliably at a high speed and with low power consumption is shown in fig1 . referring to fig1 , the bit line driving circuit comprises a signal change detecting circuit 701 for detecting a time of change of an external or internal input data signal ai and generating a one - shot pulse signal ( input change detecting signal ) atd having a predetermined time interval , a bleq generating circuit 702 responsive to the input change detecting signal atd for generating an equalize signal bleq having a predetermined time interval , and an sae generating circuit 703 responsive to the input change detecting signal atd and the equalize signal bleq for generating a sense amplifier activating signal sae . the equalize signal bleq from the bleq generating circuit 702 is transmitted to equalize transistors eqt provided to short - circuit paired bit lines . the signal change detecting circuit 701 has the same structure as that of a circuit for generating an address change detecting signal which generates internal operation signals , for example , in a random access memory . the generation of the input change detecting signal atd allows a starting point of an computing operation cycle to be reliably detected . since it is desirable that operation timings of the circuit can be detected as early as possible , an externally applied input data signal may be preferably supplied as the input data signal ai to the signal change detecting circuit 701 . in the following , operation of the circuit shown in fig1 will be described with reference to the operation waveform chart of fig1 . when the neural network enters the operational processing mode , or recalling operation mode , the control signal mux falls to &# 34 ; l &# 34 ; and the complementary control signal mux attains the &# 34 ; h &# 34 ; level . as a result , the transfer gates 115 are rendered conductive , connecting the bit lines blj and blj to the amplifying circuits 101 . subsequently , the input signal ai is applied and then a point of change of the input signal ai is detected by the signal change detecting circuit 701 to generate the input change detecting signal atd . this input change detecting signal atd has a predetermined time interval . in response to the input change detecting signal atd , the bleq generating circuit 702 is activated to generate the equalize signal bleq . in response to this equalize signal bleq , the equalize transistors eqt are rendered conductive so that potentials on the paired bit lines blj and blj are equalized . meanwhile , the signal waveform chart shown in fig1 shows a case where the bit line pairs of blj and blj are equalized at an intermediate potential between the &# 34 ; h &# 34 ; and &# 34 ; l &# 34 ; levels . this can be realized by providing the respective bit lines with transistors which are rendered conductive , in response to the equalize signal bleq , to precharge the bit lines to the intermediate potential . the equalize signal bleq is a one - shot pulse signal having a predetermined time interval . therefore , when the generation of the pulse signal terminates , subtle potential differences appear over the bit lines blj and blj due to functions of the coupling elements . subsequently , when the generation of the input change detecting signal atd and the equalize signal bleq terminates , the sae generating circuit 703 is activated to generate the sense amplifier activating signal sae . then , the amplifying circuits 101 are activated to differentially sense and amplify the subtle differences of signal potentials on the corresponding bit line pairs of blj and blj and output the results as neuron output signals . meanwhile , in the operation waveform chart shown in fig1 , a case is shown where the signal potentials of the bit line pairs of blj and blj make full - swing between the &# 34 ; h &# 34 ; and &# 34 ; l &# 34 ; levels due to functions of the sense amplifier circuits 101 . however , the differences of signal potentials can be sensed and amplified for output without the potentials on the bit lines being affected by such full - swing if only current - mirror type differential amplifier circuits are employed , for example . as described above , by equalizing potentials on the bit line pairs immediately after the neuron input data signal has changed , potentials changes which might be caused under the influences of noise and the like on the bit line pairs can be prevented . accordingly , it becomes possible to shorten the time taken until effective information appears on the bit lines , so that a neural network operable at a high speed and with low power consumption can be obtained . if the equalize transistors eqt for equalizing the bit line pairs have been adapted to be able to function also in programming coupling strengths of the coupling elements in the coupling matrix 100 , the programming of coupling states of the coupling matrix can be performed also at a high speed . additionally , a circuit structure for precharging the bit line pairs to the predetermined potential may be separately provided . further , if the equalize / precharge transistors are provided as described above , subtle differences of the potentials can be differentially sensed and amplified in a reliable manner . accordingly , activation timings of the amplifying circuits can be made earlier , so that a neural network operable at a high speed can be obtained . when a large scale parallel operation is performed in the coupling matrix corresponding to the internal input data signal applied for a long time , potentials on the respective bit line pairs may have full - swing . in this case , since those coupling elements whose internal input data signals are at the &# 34 ; h &# 34 ; level have the storage nodes of their storage elements connected to the bit lines , the contents stored in the storage elements may be rewritten by the potentials on the bit lines due to the full - swing , and further , the storage contents of the storage elements may be even destructed . a circuit structure for stabilizing the storage information in the coupling elements is shown in fig2 . referring to fig2 , the circuit structure for stabilizing the storage information in the coupling elements comprises signal change detecting circuit 710 for detecting a time of change of an externally applied input data signal ex . ai and generating , in response to the detected change , input change detecting signal atd of one - shot pulse having a predetermined time interval , and gate circuits 711 and 712 which receive the input change detecting signal acd and the externally applied input data signal ex . ai for generating one - shot internal input data signals int . ai . the gate circuits 711 , 712 and the like are provided corresponding to the respective bits of the external input data signal . an operation waveform chart of the circuit structure shown in fig2 is shown in fig2 . when the internal input data signal ai is formed as a one - shot pulse signal using such a circuit structure as shown in fig2 , the time taken to perform operational processings on the internal input data signal becomes short , no longer allowing the full - swing of signal potentials on the bit line pairs of blj and blj even if a large scale parallel operation is performed in the coupling matrix . that is , since the operation time is short , only small potential changes occur which appear usually before full - swing . thus , the destruction of the storage information in the coupling elements can be prevented . further , when the input data signal is converted into a one - shot pulse signal according to the input change detecting signal acd , the switching transistors in the coupling elements are turned off at earlier timings . this means that the coupling elements are disconnected from the bit line pairs at earlier timings , preventing the destruction of the storage contents in the coupling elements . in the signal waveform chart shown in fig2 , the signal potentials on the bit lines blj and blj are equalized every time the input change detecting signal is generated , because the equalize signal as shown in fig1 is generated . when such a one - shot internal input data signal as shown in fig2 is employed , the amplifying circuits can differentially sense and amplify signal potentials on the bit line pairs in a reliable manner , no matter how small the potential changes on the bit lines blj and blj may be . accordingly , operation performance of the neural network can not be reduced . when the circuit structure shown in fig2 is employed , the input change detecting signal acd shown in fig2 is applied also to bleq generating circuit 702 generating bit line equalize signal bleq and to sae generating circuit 703 generating activation signal sae to activate amplifying circuits . in the embodiments above , a circuit structure for programming coupling strengths in the coupling matrix has been described as allowing writing of the coupling strength information for one column after another , or bit by bit , with the use of bit line decoder 103 . instead of such structure , however , shift registers may be provided over a number of stages corresponding to the number of coupling elements in one row . in this case , coupling strength information of one row is written in the shift registers and then the coupling strength information is transferred from the shift registers to one row of coupling elements at a time . as has been described above , according the present invention , each of the coupling elements contained in the coupling matrix of a neural network is constituted of storage element portions comprising cross - coupled inverting amplifiers , and elements responsive to potentials on word lines for writing signal potentials on bit lines into the storage elements and also responsive to potentials on internal input data signal lines for transmitting the storage information in the storage element portions onto the bit line . further , the signal lines for transmitting coupling strength information in the learning mode where the coupling strength information is to be written and the data lines for outputting the internal data output signals in the neural network operating mode , or recalling mode share the same lines . accordingly , the number of interconnections in the coupling matrix and also the number of elements constituting a coupling element can be reduced , so that coupling elements which have a simple structure and occupy a small area can be provided . thus , a highly integrated and high - density semiconductor neural network can be obtained . furthermore , since the internal input data signal is formed as a one - shot pulse signal to be transmitted into the coupling matrix , the bit line potentials do not make full - swing and the coupling elements are disconnected from the bit lines , or internal data lines at earlier timings . accordingly , the neural network can be driven at a high speed and with low consumption power and stable operation can be assured without causing destruction of the storage information in the coupling element . furthermore , since potentials on the bit lines are equalized in response to the input data signal change detecting signal , it becomes possible to sense and amplify the potentials on the bit lines at a high speed without being influenced by noise and the like . consequently , a semiconductor neural network operable at a high speed and with low consumption power can be obtained . although the present invention has been described and illustrated in detail , it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation , the spirit and scope of the present invention being limited only by the terms of the appended claims .