the invention will now be taught using an exemplary embodiment . although the embodiment is described in detail , it will be appreciated that the invention is not limited to just this embodiment , but has a scope that is significantly broader . the appended claims should be consulted to determine the true scope of the invention . one embodiment of this invention resides in a computer system . here , the term “ computer system ” is to be understood to include at least a memory and a processor . in general , the memory will store , at one time or another , at least portions of an executable program code ( also referred to as computer executable code ), and the processor will execute one or more of the instructions included in that executable program code . it will be appreciated that the term “ executable program code ” and the term “ software ” mean substantially the same thing for the purposes of this description . on a practical level , the software that enables the computer system to perform the operations described further below in detail , may be supplied on any one of a variety of media . furthermore , the actual implementation of the approach and operations of the invention are actually statements written in a programming language . such programming language statements , when executed or interpreted by a computer , cause the computer to act in accordance with the particular content of the statements . furthermore , the software that enables a computer system to act in accordance with the invention may be provided in any number of forms including , but not limited to , original source code , assembly code , object code , machine language , compressed or encrypted versions of the foregoing , and any and all equivalents now known or hereafter developed . one of skill in the art will appreciate that “ media ”, or “ computer - readable media ”, as used here , may include a diskette , a tape , a compact disc , an integrated circuit , a rom , a cd , a cartridge ( regardless of shape such as cartridges shaped like memory sticks , or sized to fit on a key ring , or any other shape ) a remote transmission via a communications circuit , or any other similar medium useable by computers , now known or hereafter developed . for example , to supply software for enabling a computer system to operate in accordance with the invention , the supplier might provide a diskette or might transmit the software in some form via satellite transmission , via a wireless link , via a direct telephone link , or via the internet as a download or in an asp arrangement . thus , the term , “ computer readable medium ” is intended to include all of the foregoing and any other medium by which software may be provided to a computer . although the enabling software might be “ written on ” a diskette , “ stored in ” an integrated circuit , or “ carried over ” a communications circuit , it will be appreciated that , for the purposes of this application , the software may be referred to as being “ on ” the computer readable medium . thus , the term “ on ” is intended to encompass the above and all equivalent ways in which software is associated with a computer usable medium . for the sake of simplicity , therefore , the term “ program product ” is thus used to refer to a computer useable medium , as defined above , which has on it any form of software to enable a computer system to operate according to the above - identified invention which is described in detail below . herein , the term “ pin ” is used to mean a point of primary input , primary output , or primary input / output ( i / o ) to any circuit or ic , as well as an input , output , or i / o of a gate within the ic . a primary pin is a place where the circuit or the ic connects to external components . the term “ gate ” as used herein shall mean a single logic device or another single electronic device included in a circuit or an ic . in an ic , a plurality of gates are connected to each other , as well as to primary pins . such an arrangement is typically described using a register transfer level ( rtl ) description of such a circuit . a rtl description is a higher level description that does not require all the final gates to be known and allows for easy description of a circuit under design . each of the devices has at least a single pin by which it is able to connect to other devices and / or primary pins of the circuit . each pin may be controllable , observable or both controllable and observable . a pin may be controllable to “ 0 ” or controllable to “ 1 ” or may not be controllable to a “ 0 ” or not controllable to a “ 1 ”. for the purpose of assessing the controllability of the pins in the ic , each pin is assigned two variables : c 0 and c 1 , which provide information of the pin &# 39 ; s controllability to “ 0 ” and “ 1 ” respectively , each of them capable of receiving either the value “ n ” or “ y ” denoting “ no ” and “ yes ” respectively relative to the specific controllability . therefore a pin having a sequence of “ ny ” is not be controllable to “ 0 ” but is controllable to “ 1 ”. similarly each pin can be checked for observability , “ o ”, which can also be defined as “ n ” or “ y ” denoting “ no ” or “ yes ”, for not being observable or being observable respectively . hence , if a pin is defined as being “ nyy ” it would mean that the pin is not controllable to “ 0 ”, that it is controllable to “ 1 ” and that it is observable . the determination of these values is within the ability of one familiar in this field , and therefore the manner of determining controllability and observability are not discussed further . it is therefore possible to assess the controllability in the case of a pin stuck at 0 [ s @ 0 ] and a pin stuck at 1 [ s @ 1 ]. for the purpose of detection of a fault , a pin must be both controllable for that type of fault as well as observable . reference is now made to fig1 a where a non - limiting example of a circuit 100 is shown . circuit 100 could be any circuit under consideration , even one much more complex with many more gates and pins . circuit 100 comprises of three primary input pins , 130 - 1 through 130 - 3 ; one primary output pin , 140 - 1 , and two gates . firstly , the circuit has an or gate 110 having two input pins 110 - i 1 and 110 - i 2 ( not labeled in the figure ), connected to primary inputs 130 - 2 and 130 - 3 respectively , as well as an output pin 110 - o . secondly the circuit has an and gate 120 having two input pins 120 - i 1 and 120 - i 2 , connected to primary input 130 - 1 and pin 110 - o respectively , as well as an output pin 120 - o , connected to primary output 140 - 1 . one familiar with this field will understand that all pins in this circuit , including the pins of both gates 110 and 120 , are all controllable to both “ 0 ” and “ 1 ”, and are as well observable from the primary output 140 - 1 . reference is now made to fig2 which shows an exemplary flowchart of one embodiment of the method for determining the upper limit fault coverage of a circuit . it will be appreciated that deviations from the order of the steps may be possible , and such deviations are meant to be included in the scope of the invention . in step s 210 the total number of pins is determined . referring back to fig1 a there are ten pins in the circuit , four primary pins and three for each of gates 110 and 120 . in step s 220 it is determined for each pin whether it is controllable to “ 0 ” and whether it is controllable to “ 1 ”, followed by step s 230 where the observability of each pin is determined . then , in step s 240 the upper bound of the fault coverage is determined as a ratio between the number of pins that are both controllable and observable for s @ 0 plus the number of pins that are both controllable and observable for s @ 1 and twice the number of pins . it should be noted that the reason for using twice the number of pins is to account for both cases of s @ 0 and s @ 1 possible for each of the pins involved . in step s 250 , a report is optionally provided which may include at least the upper bound fault coverage value , usually provided as a percent value . in addition the pins that do not comply with the full controllability and observability characteristics may also be reported in respect of their rtl description . a designer can then easily modify the design to achieve a higher level of fault coverage . that is to say , a comparison may be made between the upper bound for fault coverage in the present circuit design ( present upper bound ) and a goal or target upper bound for fault coverage . when the comparison indicates the threshold is not met , the circuit may be redesigned to provide improved possible coverage at an early stage of the design phase . furthermore , it would be possible for a designer performing traditional preparation of test vectors to compare the resultant fault coverage to the upper bound fault coverage determined in accordance with the disclosed method . if the values are too far apart , it may be desirable to add test vectors in order to attempt to achieve higher fault coverage for the ic . in other words , when a set of one or more test vectors has a coverage that is not within a predetermined threshold of the estimated maximum coverage , then the set of test vectors can be modified , for example by adding additional test vectors , in an attempt to achieve higher coverage . to put it another way , this approach is a method for identifying a significant discrepancy ( i . e ., a significant difference in fault coverage ) in the fault coverage achieved by a predetermined set of test vectors and a fault coverage upper bound . reference is now made to fig1 b where a table is shown filled out in accordance with at least some of the steps described in fig2 , for the circuit shown in fig1 a . for each gate , for example gate 110 , all pins are checked for the conditions of s @ 0 and s @ 1 for both controllability and observability . for gate 110 , pin 110 - i 1 is both controllable and observable for the s @ 0 case as well as for the s @ 1 case . the determination is repeated for each fault possibility in this circuit , in this example a total of twenty , resulting from the fact that there are 10 pins each being able to be at s @ 0 or s @ 1 . a score is then determined for each of the possible faults . the score is “ 1 ” only in the case were the fault is both controllable and observable . in this exemplary circuit all the faults are both controllable and observable and hence the total score is “ 20 ”. the fault coverage is then calculated in accordance with the method , i . e ., dividing the score by the number of pins times two . as the number of pins is ten , as explained above , the result of dividing the score by twice the number of pins is “ 1 ”, representing an estimated upper bound fault coverage of 100 %. reference is now made to fig3 a where a circuit 300 is shown generally similar to the circuit shown in fig1 a , with the exception that input 330 - 3 is tied to a logic value of “ 1 ”. as a result there are several changes in the determination of the controllability and observability of the pins in this circuit . for example , pin 310 - i 2 and primary input 330 - 3 are now not controllable to “ 0 ”, however they are still controllable to “ 1 ” and remain observable . this results in a determination that they both have a “ nyy ” status . pin 310 - i 1 of gate 310 and primary input 330 - 2 are fully controllable , however , due to the fact that pin 330 - 3 is tied to “ 1 ”, pin 310 - i 1 and primary input pin 330 - 2 are no longer observable as the output of gate 310 is always “ 1 ” regardless of the values present on pin 310 - i 1 and 330 - 2 . therefore it is now determined that pin 310 - i 1 is has a “ yyn ” status . as 310 - o is not controllable to “ 0 ”, because input 310 - i 2 holds it at “ 1 ” we determine that 310 - o is not controllable to “ 0 ” and therefore this pin is now a “ nyy ”. fault coverage can now be determined in accordance with the method disclosed . reference is now made to fig3 b where a table is shown filled out in accordance with at least some of steps described in fig2 , for the circuit described in fig3 a . for pin 310 - i 1 it is determined that for s @ 0 it is controllable but not observable , leading to a score of “ 0 ”. this score is the result of not having the pin being both controllable and observable for s @ 0 . for pin 310 - i 1 it is determined that for s @ 1 it is controllable but not observable , leading to a score of “ 0 ”. for pin 310 - i 2 it is determined that for s @ 0 it is controllable and observable , leading again to a score of “ 1 ”. for pin 310 - i 2 it is determined that for s @ 1 it is not controllable but is observable resulting in a score of “ 0 ”. this analysis is repeated for each pin of the circuit . once the score of each and every pin is determined , the total score is found , which in this non - limiting example amounts to a score of “ 12 ”. now the fault coverage is determined by finding the ratio between the score and twice the number of pins in the circuit . in this case the ratio is 12 / 20 , giving 60 % for the estimated upper bound fault coverage . many variations to the above - identified embodiments are possible without departing from the scope and spirit of the invention . possible variations have been presented throughout the foregoing discussion . moreover , it will be appreciated that combinations and subcombinations of the various embodiments described above will occur to those familiar with this field , without departing from the scope and spirit of the invention .