as discussed earlier , there is need for deep , oxide - filled , trenches that are free of trapped voids . the present invention achieves this by forming the trench - filling oxide by thermal oxidation . this approach has several advantages ( in addition to eliminating void formation ). it makes possible the filling of deeper trenches with oxide . by using thermal oxide ( as compared to the lpcvd oxide that is standard in the prior art ), a less porous oxide of much better quality is obtained . additionally , the dielectric strength of thermal oxide is better than lpcvd oxide . for applications involving accelerometers and gyroscopes , the oxide shell that holds the isolation island can be reinforced by a thin unoxidized polysilicon layer . this greatly improves the mechanical stability of the isolation structure for such applications . this new approach can provide excellent trench isolation for 40 - 50 micron deep trenches with aspect ratios as high as 20 . the process of the present invention will now be disclosed through a description of four embodiments . referring now to fig2 the process of this embodiment begins with the provision of silicon body 12 on whose upper surface silicon oxide layer 21 is deposited . photoresist layer 22 is then laid down and patterned to form an etch mask that includes openings such as 23 that define the trench . all unprotected silicon oxide is then removed , resulting in the formation of hard mask 31 as seen in fig3 . using both masks , trenches 41 are then etched to a depth of at least 40 - 50 microns . the hard mask ensures accurate dimensioning of the trenches even if the photoresist is attacked by the etchant . etching of the trenches was achieved as follows : in an sts scp system , using a cyclical etch process — etching with sf 6 ( 100 sccm ), o 2 ( 10 sccm ), and c 4 f 8 ( 40 sccm ); 600 watt coil power , 14 watt platen ; 7 . 5 seconds cycle time ; passivating with c 4 f 8 ( 180 sccm ); 600 watt coil power ; 0 . 5 seconds cycle time ; pressure 22 - 30 mtorr at 54 % valve position , for a total process time between about 40 and 50 minutes ( depending on required trench depth ), for an etch rate of about 1 . 2 microns per minute . after removing all photoresist , all silicon oxide ( notably hard mask 31 ) is also removed . this sequence of steps are shown in fig2 , 4 a and 4 b . then , a new layer of silicon oxide ( layer 51 in fig5 d ) is formed on all exposed surfaces by means of thermal oxidation or lpc teos deposition . layer 51 has a thickness between about 4 , 000 and 6 , 000 angstroms . this is followed by a key feature of the invention which is the deposition of conformal polysilicon layer 52 over silicon oxide layer 51 . the polysilicon is deposited to a thickness between about 4 , 000 and 6 , 000 angstroms by means of the following lpcvd process : using asm furnace lb45 at a temperature about 580 ° c . ; pressure about 300 mtorr ; with sih 4 at about 165 sccm , for a deposition rate of about 0 . 33 microns / minute , deposition time depending on requirements . as shown in fig5 e , in another key step , polysilicon layer 52 is then thermally oxidized though its full thickness by means of wet thermal oxidation . this is achieved by means of a stabilizing temperature of about 700 ° c . which is ramped up to about 1 , 050 ° c ., for wet oxidation using oxygen at 500 sccm and hydrogen at 6 slpm ( standard liters per minute ) for as long as needed , followed by a nitrogen anneal ( 5 slpm ) at about 1 , 050 ° c . for about 30 minutes , after which the temperature is ramped back down to about 700 ° c . through careful choice of the thicknesses of layers 51 and 52 ( the trench has a width that is between about 2 and 3 times the combined thickness of layers 51 and 52 ), as the oxide grows , opposing sides of the trench will just meet , causing the trench to fill with oxide 55 and avoiding the formation of any voids . the surface oxide layer can then be removed , giving the final structure the appearance seen in fig5 f . as illustrated in fig1 , oxide filled trench 55 can stand alone within silicon body 12 or can take the form of multiply connected trenches that surround a series of silicon beams 12 , as shown in fig1 . as in the first embodiment , the process of this embodiment begins with the provision of silicon body 12 on whose upper surface silicon oxide layer 21 is deposited . photoresist layer 22 is then laid down and patterned to form an etch mask that includes openings such as 23 that define the trench . all unprotected silicon oxide is then removed , resulting in the formation of hard mask 31 as seen in fig3 . using both masks , trenches 41 are then etched to a depth of at least 40 - 50 microns , the hard mask ensures accurate dimensioning of the trenches even if the photoresist is attacked by the etchant . a typical aspect ratio for the trench would be between about 15 and 25 , depending on trench depth and width . etching of the trenches was achieved by means of a deep rie process , as follows : using an sts multiplex icp system , etching with sf 6 ( 100 sccm ), o 2 ( 10 sccm ), c 4 f 8 ( 40 sccm ), 600 watt coil power , and 140 watt platen power . this was followed by passivation in c 4 f 8 ( 180 sccm ) with 600 watt coil power for a 5 second cycle time . pressure was 22 - 30 mtorr at 54 % fixed valve position , for an etch rate of about 1 . 2 microns / minute , with total etch time depending on required trench depth . after removing all photoresist , the silicon oxide ( notably hard mask 31 ) is still retained . then , a new layer of silicon oxide ( layer 51 in fig5 a and 5 b ) is formed on all exposed surfaces by means of thermal oxidation or deposition , following which it is selectively removed from the top and floor of the trench . layer 51 is deposited to a thickness between about 4 , 000 and 6 , 000 angstroms . this is followed by the formation of beam 61 ( fig5 c ) which is achieved by subjecting all exposed silicon to a release etch which causes all silicon 62 between the floors of trenches 41 to be removed . at user &# 39 ; s discretion , either of the following processes may be used for the release etch ( sts multiplex icp system }: then , all silicon oxide ( notably layers 31 and 51 ) is removed , following which fresh silicon oxide layer 64 is formed on all exposed surfaces by means of thermal oxidation or lpcvd teos deposition . the latter consisted of teos ( about 100 sccm ), at a temperature of about 720 ° c . and a pressure of about 150 mtorr , for a deposition rate of about 25 angstroms / minute . then , in a key feature of the invention , conformal polysilicon layer 52 is deposited over silicon oxide layer 64 . the polysilicon is deposited to a thickness between about 4 , 000 and 6 , 000 angstroms by means of lpcvd ( sih 4 at 165 sccm , at about 580 ° c . and a pressure of about 300 mtorr ) for a deposition rate of about 0 . 33 microns / minute . as shown in fig8 in another key step , polysilicon layer 52 is then thermally oxidized though its full thickness by means of wet thermal oxidation . this is achieved by means of a stabilizing temperature of about 700 ° c . which is ramped up to about 1 , 050 ° c ., for wet oxidation using oxygen at 500 sccm and hydrogen at 6 slpm ( standard liters per minute ) for as long as needed , followed by a nitrogen anneal ( 5 slpm ) at about 1 , 050 ° c . for about 30 minutes , after which the temperature is ramped back down to about 700 ° c . through careful choice of the thicknesses of layers 51 and 52 ( the trench has a width that is between about 2 . 5 and 3 times the combined thickness of layers 51 and 52 ), as the oxide grows , opposing sides of the trench will just meet , causing the trench to fill with oxide 85 and avoiding the formation of any voids . this is illustrated in fig8 . the surface portion of 85 can then be removed , giving the final structure the appearance seen in fig9 . as illustrated in fig1 , a plurality of silicon beams 61 may be formed . these are anchored to main silicon body 12 at one end and are surrounded everywhere else ( except their top surface ) by silicon oxide 85 . this embodiment is similar to the second embodiment but with additional process steps after the structure has reached the stage illustrated in fig9 . this additional processing comprises the formation of a cantilever beam ( such as 112 in fig1 ) by masking the upper surface 113 ( seen here as a lower surface with mask not shown ) and then etching unprotected parts of surface 113 so that part of the beam becomes cantilever 112 , which extends away from surface 113 , as shown . this embodiment is also similar to the second embodiment , but with one key difference . after the polysilicon layer 52 has been laid down , as illustrated in fig7 the next step of fully oxidizing it by means of wet thermal oxidation , is modified to only partial oxidation so that , instead of filling the trench entirely with silicon oxide , it becomes filled with a laminate of silicon oxide - polysilicon - silicon oxide ( not shown ) that has greater mechanical strength than silicon oxide alone . said laminate surrounds the silicon beam on four sides and , as in the oxide only case , is free of voids . as in the earlier embodiments , the trench has a width that is between about 2 . 5 and 3 times the combined thickness of silicon oxide layer 64 and the polysilicon layer 52 , while silicon oxide layer 64 , the remaining ( unoxidized ) polysilicon layer , and the oxidized polysilicon layer that form the laminate , have relative thicknesses of about 5 , 000 to 1 , 000 to 8 , 000 angstroms , respectively . while the invention has been particularly shown and described with reference to the preferred embodiments thereof , it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention .