before proceeding with various types of preferred embodiments of the invention , a basic idea of a data and power transmitting / receiving system according to the invention will now be described . fig1 a is a schematic diagram of an entire system according to a basic idea of the invention . fig1 b schematically illustrates an n - bit data used in this system . fig1 c schematically illustrates a communication signal containing the n - bit data and synchronization ( sync ) signal . in the data and power transmitting / receiving system 100 of the invention shown in fig1 a , a plurality of communication units 10a , 10b , . . . , 10n are connected via a single common signal transmission line ( signal bus ) 30 to terminal units 20a to 20n , respectively . data 40 shown in fig1 b is transmitted through the transmission line 30 . as shown in fig1 b the figure , the data 40 comprises binary data b 0 , b 1 , . . . , b n each representing one or the other of two values . the bits of the data 40 correspond to functions of the terminal units 20a to 20n , respectively . for example , a determination is made that a high level in the two values of one bit activates a function of one terminal unit and a low level stops the same function . as shown in fig1 c , a sync signal 50 is combined with the data 40 in time sequence . even if all the communication units 10a to 10n simultaneously transmit and receive signals , the respective communication units can identify which of the signals operates which of the terminal units 20a to 20n , or which of the terminal units 20a to 20n is operating . in other words , the sync signal 50 is generated by sync generators 2a to 2n employed in the respective communication units 10a to 10n and added to the data 40 at a predetermined timing . the data 40 combined with the sync signal 50 is processed by data processing units 4a to 4n employed in the communication units 10a to 10n , respectively , to identify or discriminate controlling conditions of the terminal units 20a to 20n from each other . as previously described , the data and power transmitting / receiving system of the invention includes a plurality of communication units and a single common transmission line to freely interrupt , start and release operations of selected one of a plurality of terminal units , thereby improving communication speed between the communication units and terminal units . a data and power transmitting / receiving system 200 according to a first embodiment of the invention will be described . the system 200 is arranged based on the basic idea explained before . fig2 is a block diagram showing the entire system 200 . in fig2 like parts shown in fig1 are represented with like reference numerals . the system 200 includes four communication units 10a , 10b , 10c and 10d . in the communication unit 10a , a sync signal generator 11 periodically generates a sync signal 50 at a predetermined time interval . the sync signal 50 determines commencement of signal transmission and reception . the sync signal generator 11 produces the sync signal by dividing a frequency of clock signals supplied from a logic calculator 16 , and generates the sync signal 50 . the logic calculator 16 is a microcomputer . all the communication units 10a to 10d simultaneously transmit and receive signals in response to the sync signal 50 . as shown in fig3 communication data 40 comprises four bits b 0 , b 1 , b 2 and b 3 following the sync signal 50 . the first bit b 0 represents a function of turning on and off a lamp 71a connected to the terminal unit 20a . the terminal unit 20a is connected to the communication unit 10a . the second bit b 1 , third bit b 2 and fourth bit b 3 represent functions of turning on and off lamps 71b , 71c and 71d , respectively . in this way , the data 40 represents and identifies the destinations and contents of communication . each of the communication units 10a to 10d has the sync signal generator 11 to generate the sync signal 50 to determine commencement of signal transmission and reception . a switching means 12 determines whether or not the sync signal of each sync signal generator 11 will be transmitted before the data 40 . the switching means 12 of the communication unit 10a is set to be on , and the switching means 12 of the other communication units 10b to 10d are set to be off in the first preferred embodiment . a transmitter 13 shown in fig4 a receives the communication data 40 from the logic calculator 16 and transmits the data 40 to the common transmission line 30 only after receiving the sync signal 50 . a demodulator 14 shown in fig4 b demodulates the communication data 40 transmitted through the transmission line 30 from the transmitter 13 . a sync signal discriminator 15 shown in fig4 c discriminates the communication data 40 from the sync signal 50 . a data converter 17 connects the terminal unit 20a ( 20b , 20c or 20d ) to the transmitter 13 and converts the data from the terminal unit 20a into discriminable data . with the data converter 17 , the lamps 71a , 71b , 71c and 71d are turned on and off according to instructions given by switches 72a , 72b , 72c and 72d of the terminal unit 20a ( 20b , 20c or 20d ). they are applied with a power source voltage vcc and connected to a data line of the terminal unit connected to the logic calculator 16 . the logic calculator 16 includes a data decrypter 20 , an output controller 21 and a data output 24 . the data decrypter 20 decrypts the communication data demodulated by the demodulator 14 . the output controller 21 determines , according to an output of the data decrypter 20 , whether or not an output should be given to the terminal unit . the data output 24 outputs the data to the terminal unit only when the output controller determines to give the data to the terminal unit . the logic calculator 16 is operated under the control of the microcomputer . operation of the system 200 will now be described in connection with turning on and off the lamps 71a to 71d from four remote locations . in the communication unit 10a , the switch 72a of the terminal unit 20a may be pushed to generate a signal . a first bit b 0 of the signal is set to &# 34 ; 1 &# 34 ; in the communication unit 10a , and a digital signal of &# 34 ; 1 , 0 , 0 , 0 &# 34 ; is sent to the transmitter 13 ( see fig2 ) after the sync signal 50 . the signal is applied to a base terminal of a transistor 81a ( see fig4 a ) to produce a signal of &# 34 ; 0 , vcc , vcc , vcc &# 34 ; from a collector terminal of the transistor 81a . the signal then appears on the transmission line 30 . if no switches are pushed in the remaining communication units 10b to 10d , these communication units 10b to 10d transmit signals each of &# 34 ; vcc , vcc , vcc , vcc &# 34 ; to the transmission line 30 after the sync signal 50 . at this time , the transistor 81a of the communication unit 10a becomes conductive between the collector and emitter . therefore , the signal of &# 34 ; 0 , vcc , vcc , vcc &# 34 ; will appear on the transmission line 30 . however , if other switches 72b to 72d were pushed at the moment , bits of the data corresponding to the pushed switches are each &# 34 ; 0 &# 34 ; on the transmission line 30 . each of the demodulators 14 connected to the transmission line 30 demodulates the signal on the transmission line , and provides the signal of &# 34 ; 1 , 0 , 0 , 0 ,&# 34 ; if only the switch 72a has been pushed , to the data decrypter 20 . each of the output controllers 21 determines , according to an output of the data decrypter 20 , whether or not an output will be given to the terminal unit 20a ( 20b , 20c or 20d ). in the communication unit 10a , therefore , the output controller 21 determines to supply an output to the terminal unit 20a . however , the output controllers 21 of the other communication units 10b to 10d determine not to give outputs to the terminal units 20b to 20d . therefore , only the data output 24 of the communication unit 10a outputs the data to the terminal unit 20a . as a result , only the lamp 71a is lighted up . the display units 18a to 18d turn on leds , if the data bits from the data decrypter 20 corresponding to the leds are &# 34 ; 1 .&# 34 ; therefore , at any of the communication units 10a to 10d , it is possible to judge which of the lamps 71a to 71d are illuminated . a sequence of the operations described above will briefly be explained with reference to a flowchart of fig5 . firstly , 4 - bit data is set to initialize a transmission data memory ( step s1 ). a first bit of the transmission data is designated ( step s2 ). the transmission data is converted ( step s3 ). this conversion is needed to match the data with a wired - or gating operation of the transmission line . it is checked to see whether or not an interval of 1 / 2 - bit data has elapsed in response to clock signals ( step s4 ). then , reception data is demodulated to decrypt this data ( step s5 ). a check is made to see whether or not an interval of one bit data has elapsed in response to clock signals ( step s6 ). another check is made to see whether or not the 4 - bit data has been obtained ( step s8 ). in the last step , the reception data is set to &# 34 ; b 0 , b 1 , b 2 , b 3 &# 34 ; ( step s9 ) and transferred to the display controller ( step s10 ). a circuit arrangement of the communication unit 10a of the system 200 according to the first embodiment will be described in detail with reference to fig6 . the sync signal generator 11 periodically generates the sync signal 50 at a predetermined time interval . the sync signal 50 determines a transmission start timing of the data signal 40 . the sync signal generator 11 may be formed of a frequency dividing circuit composed of logic gates and a generally known oscillator circuit . if a microcomputer is employed , reference clock signals of the microcomputer may be used with the combination of hardware logic gates to form the frequency dividing circuit as of the sync signal generator 11 . alternatively , software of the microcomputer may establish the same function of the frequency dividing circuit . for example , a clock circuit 69 of a single - chip microprocessor 68 provides clock pulses , and the frequency of the clock pulses is divided by a frequency dividing circuit 70 to obtain the sync signal 50 , as shown in fig7 . to discriminate the sync signal 50 from the communication data 40 , the sync signal 50 will be changed to a signal having a level different from that of the communication data 40 , or the sync signal 50 will be converted into a special code . also , the sync signal 50 may be modulated in the different way from the communication data . a switching means 12 determines whether or not the sync signal 50 from the sync signal generator 11 is transmitted before the communication data 40 . the switching means 12 may be realized by any device functioning as a switch . the switching means 12 is closed if the communication unit 10 including the switching means 12 in question is used as a communication controller among a plurality of the communication units 10 connected to the single common transmission line 30 . the switching means 12 of the remaining communication units 10 are not closed . any other disconnecting means may be used as the switching means 12 . a transmitter means 13 transmits the communication data 40 sent from the logic calculator 16 to the transmission line 30 only after receiving the sync signal 50 . the transmitter means 13 comprises a parallel - to - serial converter for temporarily storing the communication data 40 and outputting the communication data 40 in time sequence , or division in response to an input of the sync signal 50 . the transmitter means 13 may include either a circuit for handling an output of the parallel - to - serial converter as it is as a voltage signal , or a circuit for converting the output of the parallel - to - serial converter into a tone burst wave . alternatively , the logic calculator 16 may incorporate a program for temporarily storing the communication data 40 and outputting the communication data 40 in time sequence , or division after the sync signal 50 . the circuits and programs materializing the transmitter 13 are not particularly limited but any ones currently used may be employed . a demodulator means 14 demodulates the communication data 40 transmitted through the transmission line 30 . the demodulator means 14 may be realized by a circuit for demodulating the signal or the tone burst wave sent from the transmitter means 13 . alternatively , the demodulator means 14 may be realized by a circuit which uses the voltage signal from the transmitter 13 as is . the demodulator means 14 further includes a serial - to - parallel converter . the serial - to - parallel converter converts the communication data 40 demodulated by the demodulating circuit , into parallel data and temporarily stores the resultant parallel data . the parallel data is easily processed . alternatively , the logic calculator 16 may incorporate a program to convert the time - sequence communication data 40 demodulated by the demodulating circuit , into the parallel data and temporarily store the parallel data . the circuits and programs materializing the demodulator 14 are not particularly limited but any ones currently used may be employed . a sync signal discriminator means 15 discriminates the communication data 40 from the sync signal 50 . if the sync signal 50 and communication data 40 have different levels respectively , the sync signal discriminator 15 will have a comparator as shown in fig8 a . the comparator compares the levels of the sync signal 50 and communication data 40 with reference levels . the reference levels correspond to threshold levels of the sync signal 50 and communication data 40 . if the sync signal 50 and communication data 40 have the save level but the sync signal is represented with a specific code as shown in fig8 b , the sync signal discriminator 15 will be a circuit for decrypting the specific code or will be a code decrypting program provided in the logic calculator 16 . if the sync signal 50 is modulated differently from the communication data 40 , the sync signal discriminator 15 will be a circuit for demodulating only the sync signal 50 . as previously described , each of the communication units 10a to 10d of the first preferred embodiment mainly comprises the sync signal generator means 11 , switching means 12 , transmitter means 13 , demodulator means 14 , sync signal discriminator means 15 and logic calculator means 16 . generally , the logic calculator 16 is a combination of logic elements , or a microcomputer circuit incorporating software . the logic calculator means 16 includes the data converter means 17 , data decrypter means 20 , output controller means 21 , display controller means 23 and data output means 24 for a terminal unit . the data converter means 17 connects the terminal unit to the transmitter means 13 . the terminal unit transmits the data 40 to the data converter 17 . the data 40 specifies the destinations and contents of communication . the data converter means 17 converts the data 40 into identifiable data . the terminal unit may have many switches such as keys of a keyboard . the data converter 17 may be realized by a combination of predetermined logic gates incorporated in the logic calculator means 16 , or by a program for carrying out data conversion according to a predetermined format . a data decrypter means 20 decrypts the data 40 sent from the data converter means 17 . the data decrypter means 20 may be realized by a combination of predetermined logic gates incorporated in the logic calculator means 16 , or by a program for carrying out data decryption according to a predetermined format . a display controller means 23 outputs the communication data 40 from the data decrypter 20 to the display unit for displaying the communication data 40 . the display controller means 23 may be realized by a combination of predetermined logic gates incorporated in the logic calculator 16 or by a program for carrying out data conversion according to a predetermined format . if the display unit uses leds ( light emitting diodes ), etc ., operated by electric current , there is provided a latch circuit for holding the data 40 until the next data 40 is received , and a current amplifier for displaying the data held in the latch circuit on the leds . if the display unit is connectable to the microcomputer , there are provided an interface and a program . the program is for controlling data to be outputted via the interface . an output controller means 21 determines , according to the data 40 from the data decrypter 20 , whether or not the data will be given to the terminal unit . 0000 the data output 24 outputs the communication data 40 from the data decrypter 20 to the terminal unit only when the output controller 21 operates to provide the data to the terminal unit . the output controller 21 and data output 24 may be realized by the combination of predetermined logical gates incorporated in the logic calculator 16 , or by a program for carrying out conversion according to a predetermined format . a data and power transmitting / receiving system 300 according to a second embodiment will be described . the system 300 employs a circuit arrangement similar to that of the system 200 according to the first preferred embodiment shown in fig2 . therefore , only a circuit different from the circuit arrangement of the system 200 will be described . a sync signal generator 11 periodically generates a sync signal 50 with a predetermined time interval . the sync signal 50 determines commencement of transmission of a data signal 40 . the sync signal generator 11 receives clock signals from a clock signal circuit 69 of a single - chip microcomputer hdd401010 ( a trade - name of hitachi ltd .,) and divides the frequency of the clock signals by using a frequency dividing circuit shown in fig7 employed therein so as to produce the sync signal 50 . as shown in fig9 the sync signal 50 has a duration time of 1 msec and a time period of 12 msec . a snap switch 42 determines whether or not the sync signal 50 will be transmitted before the communication data 40 . the snap switch 42 is connected to an output of the sync signal generator 11 . as shown in fig1 , the snap switch 42 is connected between the sync signal generator 11 and an input terminal 52 of a transmitter 44 . only when the communication unit is used as a communication controller of the system 300 is the snap switch 42 closed . the sync signal 50 is transmitted from the communication unit acting as the controller to the remaining communication units ( not shown ) through a transmission line 30 . the transmitters , demodulators and sync signal discriminators employed in the remaining communication units , rectify and smooth the sync signal 50 to obtain the rectified and smoothed signal to power sources 70 of the remaining communication units as shown in fig1 . if the communication unit is not used as the communication controller , the sync signal discriminator provides the sync signal 50 to determine transmission and reception timings . the transmitter circuit 44 ( see fig1 ) transmits the transmission data only after receiving the sync signal 50 . similar to the sync signal discriminator 15 shown in fig4 c , a user work area of a memory of the single - chip microcomputer is used to temporarily store the transmission data . an output terminal of the memory is connected to a parallel signal input terminal of a parallel - to - serial conversion shift register 90 . the parallel - to - serial conversion shift register 90 starts to carry out the conversion at a falling edge of the sync signal . an output of the parallel - to - serial conversion shift register 90 is connected to a data input terminal 53 of the transmitter circuit 44 shown in fig1 . a demodulator 45 shown in fig1 demodulates the communication data 40 transmitted through the transmission line 30 . the demodulator 45 corresponds to the demodulator 14 shown in fig2 . the demodulator 45 comprises a comparator 55 . an inverting input terminal of the comparator 55 is connected to the transmission line 30 . the comparator 55 discriminates the sync signal 50 from the communication data 40 . the demodulator 45 further comprises a comparator 57 . by detecting a falling edge of the discriminated sync signal 50 , the communication data 40 following the sync signal 50 is passed through the comparator 57 . a reference voltage of the comparator 57 is 2 . 5 v . then , the communication data 40 is converted from the time - sequence data into parallel data which is easy to be processed , and temporarily stored in a serial - to - parallel conversion shift register 84 . after the storage of the communication data 40 and the detection of a rising edge of the sync signal 50 , the communication data 40 is transferred to and stored in an area that is different from the area for storing the transmission data in the single - chip microcomputer . the logic calculator 16 ( see fig2 ) is realized by a single - chip microcomputer hd401010 ( a trade - name of hitachi ltd .) the microcomputer is capable of parallel - processing of eight bits data . a controller of the preferred embodiment is provided with many switches such as keys of a keyboard . as shown in fig1 , the switches are arranged in a matrix form . an address selector is connected to the matrix such that the address selector can select a single address with respect to one of rows 61 . addresses of the rows 61 are sequentially scanned according to a program . if a switch is depressed , an output appears on a corresponding line among lines 62 . the signal of the line 62 in question is transferred to a memory in the microcomputer . a program in the microcomputer changes only a bit corresponding to a function of the terminal unit to be controlled to have a state different from those of the other bit to form the transmission data 40 . a display controller 47 outputs reception data to be displayed to a display unit 18a ( 18b , 18c , 18d ). the display controller 47 comprises an 8 - bit latch circuit 95 employed in an output interface of the microcomputer . this latch circuit 95 temporarily stores the data derived from a memory 93a into which the reception data have been stored . an output of the latch circuit 95 is connected to a base terminal of a transistor 97 of the display unit 18a to turn on and led corresponding to a function of the terminal unit 20a , as shown in fig1 a . in the communication unit , it is determined , according to the received data 40 , whether or not the data will be given to the terminal unit to be controlled as shown in fig1 b . to expedite the determination , there is employed an 8 - bit dip switch 93b . the dip switch 93b outputs data corresponding to the function of the terminal unit . both the bits of the dip switch 93b and the bits of the received data 40 are exclusive - or gated . if all bits become 1 as a result of the exclusive or gating operation , it means that the received data 40 coincides with the function represented by the dip switch 93b . only in this case , a gate of the buffer 95b , shown in fig1 c , i . e ., the output interface is opened to output the communication data from the communication unit to the terminal unit via the signal transmission line 30 . a data and power transmitting / receiving system 400 of the third embodiment will now be described . since the system 400 has substantially the same circuit arrangement as that of the system 200 of the first embodiment , only a circuit different from the system 200 will be described . a logic calculator 16 is the same as the logic calculator of the first embodiment shown in fig2 . a common data format communicated between communication units 10a to 10d is the same as that of the first embodiment . data conversion from parallel data to serial data is carried out as shown in fig1 . instead of the parallel - to - serial converting shift register 90 ( see fig4 c ) for transmission of the first embodiment , a program is incorporated in a microcomputer . as shown in fig1 , bits in an accumulator 65 of the cpu of the microcomputer are shifted to upper positions bit by bit while the most significant bit is shifted to a position of the least significant bit ( a left rotate instruction ). the left rotate instruction and an instruction for outputting the contents of the accumulator 65 to a specific address q are repeated alternately . as shown in fig1 , the most significant bit of the address q is connected to a data input terminal of a transmission line . data conversion from serial data to parallel data is carried out as shown in fig1 . the serial - to - parallel converting shift register 84 ( see fig1 ) for reception is replaced with a program incorporated in the microcomputer . according to the program , an instruction is executed to transfer the demodulated serial data to the most significant bit of another specific address n , set other bits of the address n to 0 , and transfer the data from the address n to the accumulator 65 of the cpu of the microcomputer . then , the left rotate instruction is carried out to shift the data in the accumulator to upper positions bit by bit while shifting the most significant bit to a position of the least significant bit . then , an instruction is carried out to obtain an or gating operation between the left - rotated data and the next serial data set to the address n with a new data at the most significant bit and 0 for the remaining bits . these instructions are combined in the program to convert the serial data into the parallel data . other arrangements of this third embodiment are the same as those of the first embodiment . fig1 is a schematic block diagram showing basic operation of the data and power transmitting / receiving system according to the invention . a plurality of communication units simultaneously can transmit and receive the communication data 40 each combined with a single sync signal 50 . each of the communication data contains the destination and content of communication specific to the relevant communication unit and terminal unit . since this communication data owns the identifiable format , the operations of the selected terminal units can be freely stopped , commenced , and left as they are . in addition , communication speed between a plurality of controllers , i . e ., communication units and terminal units can be improved . in other words , a sync signal is added to n - bit data (&# 34 ; n &# 34 ; is an integer ), n bits thereof representing operation conditions of &# 34 ; n &# 34 ; terminal units . according to the systems of the invention , such as information signal can be simultaneously transmitted and received between the communication units . this is because &# 34 ; n &# 34 ; communication units are connected to a common data bus in a wired - or state . since the information signal is simultaneously transmitted and received , communication speed of the invention systems can be remarkably improved as compared with the conventional systems . in addition , the systems of the invention can utilize the sync signal as power source to the terminal units . therefore , various information such as operating conditions of the terminal units can be transmitted and received through the single common data bus between the communication units . further , the information as well as electric power can be transmitted and received with respect to the terminal units in a time divisional ( sequential ) method . a hot - water supply system fueled by gas according to a fourth embodiment of the invention will now be described in detail . as shown in fig1 , a hot - water supplying system 500 fueled by gas according to the embodiment comprises an actuator ( fan 503 , a solenoid valve 505 ) and sensors ( a rotation sensor 507 , a flame sensor 508 , a water level sensor 510 and a hot - water temperature sensor 513 ). according to the present embodiment , a first data communication circuit 515 is arranged for the fan 503 and rotation sensor 507 . a second data communication circuit 516 is arranged for the solenoid valve 505 and flame sensor 508 . a third data communication circuit 517 is arranged for the water level sensor 510 and hot - water temperature sensor 513 . the first to third communication circuits 515 , 516 and 517 are connected to the respective actuators and sensors through a short control line 518 and a short signal line 519 . the data communication circuits 515 , 516 and 517 are connected to a power / data communication line 521 . the power / data communication line 521 is capable of supplying electricity as well as communicating data . the power / data communication line 521 is connected to a control unit 520 . the control unit 520 is connected to a control panel 502 . a signal transmitted through the power / data communication line 521 is controlled in a time divisional or sequential manner with respect to a time &# 34 ; t &# 34 ; as shown in fig1 . the power / data communication line 521 is used for supplying electricity in a time band w1 and for communicating data in the next time band w2 . the time band w2 is further subdivided into a signal transmission time band w3 and a signal reception time band w4 . fig1 shows internal circuits of the control panel 502 and control unit 520 . the control unit 520 comprises a 5 - volt power source 522 , a microcomputer 523 ( hd6805u2 of hitachi ltd .,) and a data communication circuit 524 . a power source terminal v of the microcomputer 523 is connected to the power source 522 . input and output terminals l and s of the microcomputer 523 are connected to a switching mechanism of the control panel 502 to be described later . a grounding terminal g of the microcomputer 523 is grounded to a printed circuit board . terminals osc1 and osc2 of the microcomputer 523 are connected to a crystal oscillator 525 . three ports p0 , p1 and p2 of the microcomputer 523 are connected to three ports i0 , i1 and i2 of the data communication circuit 524 . an output terminal o of the data communication circuit 524 is connected to a voltage line 521a of the power / data communication line 521 . the power / data communication line 521 comprises the voltage line 521a and a grounding line 521b . one end of the grounding line 521b is grounded to the circuit board of the control unit 520 . the control panel 502 is provided with a voltage of 5 v from the power source 522 through a resistor 526 . the control panel 502 comprises the switching mechanism including a switch 527 . when turned on , the switch 527 lowers a potential of the input terminal s of the microcomputer 523 to a grounding voltage . the switching mechanism further includes an led lamp 530 . the led lamp 530 receives a voltage of 5 v through a resistor 528 and is lighted up in response to activation of a transistor 529 . the transistor 529 is operated according to a voltage of 5 v outputted from the output terminal l of the microcomputer 523 . if the switch 527 is depressed in the arrangement of the control panel 502 and control unit 520 , the microcomputer 523 may recognize the fact that the switch 527 has been depressed , through the input terminal s . then , the output terminal l of the microcomputer 523 outputs a voltage of 5 v to light up the led lamp 530 to indicate an operating state . after receiving an instruction due to the operation of the switch , the microcomputer 523 communicates with the ports i0 , i1 and i2 of the data communication circuit 524 through the ports p0 , p1 and p2 . thus , two - way communication is established with respect to the actuators and sensors shown in fig1 via the power / data communication line 521 . as shown in fig2 in detail , the data communication circuit 524 of the control unit 520 comprises a 5 - volt power source 531 and a 15 - volt power source 532 for supplying electric power . the 15 - volt power source 532 is connected to the voltage line 521a of the power / data communication line 521 through a transistor 534 . the transistor 534 is provided with a bias resistor 533 . in the power supply time band w1 shown in fig1 , the microcomputer 523 activates transistors 536 and 534 through the port i0 to supply a voltage of 15 v to the voltage line 521a . a base of the transistor 534 is connected to the port i0 through a transistor 536 . the transistor 536 is provided with a bias resistor 535 . the 5 - volt power source 531 is connected to the voltage line 521a through a communication pull - up resistor 537 . a node &# 34 ; 0 &# 34 ; between the power source 531 and the resistor 537 is connected to the port i1 through a transistor 539 . the transistor 539 is provided with a bias resistor 538 . in the data transmission time band w3 shown in fig1 , the microcomputer 523 sends a data transmission command to the input port i1 to activate the transistor 539 . as a result , a dc data signal is transmitted to the voltage line 521a . the power source 531 is grounded through voltage dividing resistors 540 and 541 . a junction between the resistors 540 and 541 is connected to a negative (-) terminal of a comparator 542 . an output terminal of the comparator 542 is connected to the port i2 . a positive (+) terminal of the comparator 42 is connected to the voltage line 521a via a connection line . the connection line is grounded through a resistor 543 . in the data reception time band w4 shown in fig1 , the comparator 542 is operated according to a potential change in the voltage line 521a . the data supplied through the voltage line 521a is given to the microcomputer 523 through the port i2 . fig2 is a circuit diagram showning the details of the first data communication circuit 515 connected to the fan 503 , among the data communication circuits on the actuator and sensor side . as shown in the figure , the first data communication circuit 515 of the fan 503 is connected to the control unit 520 via the power / data communication line 521 . the first data communication circuit 515 is connected to the sensor 507 through a power source supplying terminal 544 , a sensor signal input terminal 545 and a grounding terminal 546 . the first data communication circuit 515 is connected to the fan 503 through connection terminals 547 and 548 . a driving power source of the fan 503 is an ac power source 549 of 100 v according to the preferred embodiment . the ac power source 549 is connected to the fan 503 through terminals 550 and 551 . the power / data communication line 521 is connected to a power accumulating capacitor 554 and to an input terminal of a 3 - terminal regulator 555 via terminals 552 and 553 , a bridge circuit and diodes d4 and d5 . the bridge circuit comprises diodes d0 , d1 , d2 and d3 . one end of the power accumulating capacitor 554 is grounded . an output terminal of the 3 - terminal regulator 555 is connected to a voltage smoothing capacitor 556 . the other end of the voltage smoothing capacitor 556 is grounded . in the power supply time band w1 shown in fig1 , the power line 521a is supplied with a voltage of 15 v . then , the capacitor 554 is charged to output a stable power source voltage of 5 v from the output terminal of the 3 - terminal regulator 555 . in the center of the circuit 515 , a microcomputer 558 is arranged . terminals osc1 and osc2 of the microcomputer 558 are connected to a crystal oscillator 557 . the microcomputer 558 has a power source terminal v for receiving a voltage of 5 v from the 3 - terminal regulator 555 . the microcomputer further employs a grounding terminal g and five ports p0 , p1 , p2 , p3 and p4 . the port p1 is used to receive the number of rotations detected by the rotation sensor 507 . the rotation sensor 507 receives a voltage of 5 v from the 3 - terminal regulator 555 via the terminal 544 to output pulse signals in response to the number of rotations to the terminal 545 . the pulse signals are inputted to the port p1 via photocoupler 560 for a noise eliminating purpose . the photocoupler 560 receives a voltage of 5 v through a resistor 559 and grounds the received voltage to provide a positive output voltage . the port p4 is used to detect a phase of the ac power source 549 . the port p0 controls the phase of the ac power source 549 to drive the fan 503 . the input terminals 550 and 551 of the ac power source 549 are connected to a series circuit comprising a resistor 561 and a diode 562 . a diode 564 of a photocoupler 563 is connected in parallel with the diode 562 . an output terminal of the photocoupler 563 is connected to the port p4 to detect a phase of the ac power source 549 according to a voltage input to the port p4 . the port p0 is connected to a transistor 566 . the transistor 566 is provided with a bias resistor 565 . the transistor 566 activates a thyristor driving type photocoupler 568 to provide predetermined electricity to the fan 503 . the photocoupler 568 receives a voltage of 5 v through a resistor 567 . the photocoupler 568 is connected to snubber circuits 569 and 570 for absorbing surge . according to the phase of the ac power source 549 to be inputted to the port p4 , the microcomputer 558 activates the transistor 566 to control the phase of the ac power source through the photocoupler 568 , thus driving the fan 503 at a required rotational speed . according to an input signal from the rotation sensor 507 to the port p1 , the port p3 transmits predetermined data to the control unit 520 . the port p3 is connected to a transistor 572 . the transistor 572 is provided with a bias resistor 571 . an output terminal of the transistor 572 is grounded through a resistor 573 . at the time of communication , the output terminal of the transistor 572 is connected to the power / data communication line 521 via output terminals of the diodes d2 and d3 . the output terminals of the diodes d2 and d3 are set to 5 v . in the time band w4 shown in fig1 for data reception for the control unit 520 , a pulse wave corresponding to the transmission data is given to the port p3 to lower a potential of the voltage line 521a from 5 v to 0 v according to activation of the transistor 571 . as a result , the data containing codes each of 1 or 0 can be transmitted to the control unit 520 . the port p2 is used to receive the data transmitted from the control unit 520 . the power / data communication line 521 is connected to a positive (+) terminal of a comparator 574 via the diodes d2 and d3 . a negative (-) terminal of the comparator 574 is connected to a node between series resistors 575 and 576 . the series resistors 575 and 576 are connected to the 3 - terminal regulator 555 . an output terminal of the comparator 574 is connected to the port p2 . the negative (-) terminal of the comparator 574 receives a reference voltage smaller than 5 v . the positive (+) terminal of the comparator 574 receives a voltage in the range of 0 to 5 v . the voltages applied to the negative and positive terminals of the comparator 574 are compared with each other in the comparator 574 . then , according to a voltage state of the power / data communication line 521 , a data transmitted through the power / data communication line 521 is inputted to the port p2 in the time band w3 shown in fig1 . the control unit 520 and the data communication circuit 515 of fan 503 shown in fig1 can supply electric power and communicate data through the power / data communication line 521 to properly control rotation of the fan 503 . the control unit 520 controls time based on the crystal oscillator 525 shown in fig1 . according to the time divisional operation shown in fig1 , the control unit 520 determines the power supply and communication time bands w1 and w2 ( w3 , w4 ) to carry out the power supply and data communication in the respective time bands . the data communication circuit 515 shown in fig2 is provided with another crystal oscillator 557 . the oscillation of the crystal oscillator 557 is synchronized with that of the crystal oscillator 525 with the use of proper data or a waveform of data to carry out data communication by using various dc signals such as single current signals , single current rz signals and 0 inverting signals . similarly , the control unit 520 can supply electric power and communicate data with respect to the second data communication circuit 516 connected to the solenoid valve 505 and flame sensor 508 , and with respect to the third data communication circuit 517 connected to the water level sensor 510 and hot - water temperature sensor 513 . the control unit 520 can properly control the respective actuators according to output signals of the respective sensors . the control unit 520 and data communication circuits 515 , 516 and 517 are connected to each other only through the power / data communication line 521 comprising the power line 521a and grounding line 521b so that connection may be easily performed , and occurences of line disconnection and noise may be avoided . in this embodiment , the power / data communication line 521 has been used to supply power and communicate data . namely , the embodiment is based on a low - voltage dc type power - line - transmission system . alternatively , a general ac type power - line - transmission system may be adopted . in this case , a proper modem is used to transmit a data signal of 100 to 200 khz with an ac of 100 v . in this arrangement , the ac power source 549 for the fan 503 may be omitted . in the embodiment , the data communication circuits 515 , 516 and 517 for the actuators and sensors have been controlled by the control unit 520 . alternatively , the microcomputer 558 may contain a program to independently control the data communication circuits according to an output of the rotation sensor 507 . namely , the data communication circuits act as control centers to separately control the respective actuators to reduce the load on the control unit 520 and further improve reliability . the data communication circuits shown in fig2 may be integrated to one or a plurality of standard circuits . by slightly modifying a program in the microcomputer 558 , the actuators and sensors may be adopted for the standard circuits . the present invention is not limited by the above - described embodiments but proper modifications may be made on the design of the invention to achieve the invention in various forms . as described above , the present invention causes no erroneous operation due to external noise and line disconnection , and makes connection and maintenance tasks easier .