referring first to fig1 volt , 60 hz ac from a conventional household branch circuit is applied to ac input terminals 10 and 12 connected through an electromagnetic interference ( emi ) filter 14 to the ac input terminals 16 and 18 of a full wave bridge rectifier 20 . as indicated , the emi filter 14 may comprise a pair of series inductors 22 and 24 , each for example having an inductance of 250 microhenries , with a 0 . 05 microfarad capacitor 26 in shunt on the output side of the emi filter 14 . for additional system protection a 150 volt metal oxide varistor ( mov ) ( not shown ) may be connected on the output side of the emi filter 14 . pulsating dc output from the bridge rectifier 20 is applied to respective positive and negative dc supply conductors 28 and 30 , and a low value filter capacitor 32 is connected across the dc supply conductors 28 and 30 . the capacitor 32 is sized to further reduce electromagnetic interference and to provide adequate local energy storage for supplying chopping components of current while , at the same time , having minimum adverse impact upon input power factor . the voltage across the dc supply conductors 28 and 30 thus remains a relatively high ripple dc input voltage or , expressed alternatively , substantially unfiltered rectified ac power . in order to sense the instantaneous current supplied to the remaining elements of fig1 a 0 . 05 ohm current sensing resistor 34 is connected in series between the negative dc supply conductor 30 and an extension 30 &# 39 ; thereof . a current sensing line v i is connected on one terminal of the current sensing resistor 34 to sense the voltage drop thereacross . the current sensing signal on the v i line is referenced to a circuit reference point 36 connected to the extended negative dc supply conductor 30 &# 39 ;. also shown in fig1 is an electronically commutated bi - directional , variable speed dc motor generally designated 38 intended for application in a direct drive clothes washing machine . more particularly , the motor 38 is represented by stator windings a , b and c , connected in a &# 34 ; y &# 34 ; configuration . it will be appreciated that the motor 38 requires a rotor such as a conventional permanent magnet rotor ( not shown ) which rotates in either direction depending upon the energization sequence of the windings a , b and c . connected to the windings a , b and c of the motor 38 and supplied from the positive and negative dc supply conductors 28 and 30 &# 39 ; are three power switching sections respectively designated 40 , 42 and 44 . generally speaking , each of the switching sections 40 , 42 and 44 comprises a power switch which is capable of connecting the end of the respective motor winding a , b or c to either the positive supply line 28 or the negative supply line 30 &# 39 ;. for motor 38 winding a , the top switch is designated q at , and the bottom power switch is designated q ab . the same nomenclature is employed for similar power switches the other two switching sections 42 and 44 . for purposes of illustration , the power switches are illustrated as power field effect transistors capable of switching 200 volts dc , with three amperes average current , and ten amperes peak current . however , other switching devices may equally well be employed , such as bipolar transistors or insulated - gate transistors . in order to provide current paths for decay ( flyback ) current induced by collapsing magnetic fields as the individual windings a , b and c are de - energized , free - wheeling diodes are connected to the windings a , b and c . in the particular circuit illustrated , six free - wheeling diodes designated d at , d ab , d bt , d bb , d ct , and d cb are provided and connected electrically in parallel with respective ones of the field - effect transistor power switches and oppositely poled with respect thereto . despite the apparent connection of the free - wheeling diodes across the switching transistors , analysis of the circuit operation will reveal that the free - wheeling diodes in actuality are effectively connected in shunt with the motor windings to provide paths for circulating flyback current in the motor windings . in the general operation of the power switching circuit of fig1 as thus far described , suitable gate drive signals are applied to the power switching transistor gate terminals 48 . as is more fully explained hereinbelow , both the top switching transistors q at , q bt and q ct and the bottom switching transistors q ab , q bb and q cb are used for the commutating function to sequentially energize the windings in appropriate pairs to cause motor rotation in a particular direction and at a particular velocity . whichever one of the bottom switching transistors q ab , q bb and q cb happens to be active depending upon the particular point in the commutation cycle is additionally rapidly switched on and off in chopper fashion ( duty cycle control ) to control the average current through whichever pair of the motor windings a , b and c is energized at any given time . in this manner , effective applied motor voltage is controlled to be that required to maintain motor velocity , with the inductance of the motor windings a , b and c providing current smoothing . more particularly , in accordance with the invention the on / off switching of the bottom transistors q ab , q bb and q cb is under control of simulation circuitry , generally designated 50 , which simulates the on / off duty cycle control of the general type which continuously measures motor winding current and maintains this current at an average value between an upper and lower thresholds . in the simulation circuitry 50 , the v i sensing line from the current - sensing resistor 34 is applied to the inverting (-) inputs of a lower threshold comparator 52 which drives a lower line and of an upper threshold comparator 54 which drives an upper line . the comparator 52 and 54 non - inverting (+) inputs serve as reference inputs and are respectively supplied from a lower threshold reference voltage source 56 and an upper threshold reference voltage source 58 . the comparators 52 and 54 comprise conventional integrated circuit voltage comparators , current to voltage conversion being accomplished by the current - sensing resistor 34 . for an electronically - commutated motor controllable over a wide range of operating conditions , the lower and upper threshold reference sources 56 and 58 are adjustable , as indicated . it will be appreciated that a number of variations are possible . for example , the lower and upper threshold reference voltage sources may be combined into a single circuit with a single adjustment input and which provides two reference outputs with a fixed offset therebetween . similiarly , a variety of specific comparator circuits may be employed . another example is the one disclosed in alley et al u . s . pat . no . 4 , 250 , 435 . depending upon the particular comparator circuit employed , the lower 52 and upper 54 comparators may be supplied from a single reference voltage source , with a resistive network ( not shown ) associated with the comparators 52 and 54 themselves to establish a predetermined offset between the thresholds . as another variation , a single integrated circuit voltage comparator may be employed with appropriate resistive biasing , for example to establish hysteresis , in combination with suitable digital logic elements connected to the comparator output . in any event , in the overall operation of the comparator circuits , the lower threshold comparator 52 is responsive to the magnitude of current supplied from the dc power source to the motor winding 38 as sensed via the resistor 34 and is operable to drive the lower line to logic high when current is at or above a lower threshold current level . similarly , the upper threshold comparator 54 is responsive to the magnitude of current supplied from the dc power source to the motor windings 38 and is operable to drive the upper line to logic high when current is at or above an upper threshold current . the upper line is connected to the set ( s ) input of a set / reset flip - flop 60 , the q output of which drives a switch off line . the switch off line is in turn connected to the commutation and driver circuitry shown in fig3 . while the circuitry of fig3 is described in detail hereinbelow , for present purposes it is sufficient to state that , whenever the switch off line is low , whichever of the bottom power switching transistors q ab , q bb or q cb is currently selected in accordance with the commutation sequence is turned off to de - energize the motor windings a , b and c until such time as the switch off line again goes high . thus , the switch off line may be viewed as the actual control line which controls the on / off duty cycle switching of the motor windings . the remainder of the circuitry 50 of fig1 comprises an adaptive timing circuit 62 and includes , in addition to the set / reset flip - flop 60 , an up / down digital counter 64 driven by a fixed - rate clock pulse source 66 , a decoder 68 for recognizing a particular predetermined state of the counter 64 , and a monostable multivibrator ( one shot ) 70 connected between the lower line from the lower threshold comparator 52 and the counter 64 reset input for conditioning the counter reset signal . referring also to the timing diagram of fig2 the operational function of the adaptive timing circuit 62 is repetitive , and is as follows : upon energization of the motor 38 windings , the adaptive timing circuit 62 measures the on time or rise time required for current to increase from the lower threshold current level ( the reaching of which is indicated by the lower line going high ) to the upper threshold current level ( the reaching of which is indicated by the upper line going high ). as already described above , when the upper line goes high , the switch off line is driven low through the flip - flop 60 , and this in turn causes one of the power switching elements q ab , q bb or q cb to de - energize whichever pair of motor 38 windings a , b and c which happens to be energized at that particular time in accordance with the commutation sequence . at that point , the adaptive timing circuit 62 establishes an off time or decay time interval as a function of the measured on time . in the particular embodiment of fig1 the off time interval approximately equals the measured on time . at the end of the off time interval , the adaptive timing circuit 62 causes re - energization of the selected motor windings , a , b and c by causing the switch off line to again go high . as depicted in fig2 the flyback current decays at a rate related to the rate of current rise , typically about the same , or slightly faster due to circuit losses . based on this observation , decay time is simulated without actually measuring current during the decay time interval . considering the adaptive timing circuit 62 in greater detail , it will be appreciated that the up / down digital counter 64 , together with the clock pulse source 66 , comprises a timer of the type which measures an input time interval and provides an output time interval as the function of the input time interval . thus , in operation , when the lower threshold current level is reached , the lower output line of the comparator 52 goes high , and a pulse output from the one shot 70 resets the counter 64 to an initial state , for example zero . the decoder 68 recognizes this state , and an output 72 thereof goes high . the output line 72 is connected to the reset ( r ) input of the set / reset flip - flop 60 , and thus insures that the flip - flop 60 is initially in its reset state , during which the q output is high . in addition , a line 74 from the flip - flop 60 q output to an up / down input of the counter 64 ensures that the counter 64 is commanded to count up . during the on or rise time interval , current supplied to the motor windings a , b and c as sensed by the current sensing resistor 34 increases from the lower current threshold level to the upper threshold current level , and the counter 64 accumulates a count of clock pulses from the source 66 as a direct function of the duration of the on time interval and thus measures it . when the upper current threshold level is reached , the upper line goes high , setting the flip - flop 60 . this causes the flip - flop 60 q output and the switch off line to go low , de - energizing the motor windings a , b and c . at the same time the counter 64 is commanded to count down , and at the same rate , under the control of the clock pulse source 66 . as an example of operation at a specific point during the commutation cycle , it may be assumed that the commutation sequence in calling for transistors q at and q bb to be on , thus energizing motor windings a and b in series from the dc power supply conductors 28 and 30 &# 39 ;. the rising current thus flows through the current - sensing resistor 34 to be processed by the simulation circuitry 50 as described above . when the switch off line goes low , the switching transistor q bb turns off for the off time or decay time interval ( even though the transistor q bb would otherwise be on in accordance with the commutation sequence ). this de - energizes the windings a and b , and the collapsing magnetic field induces a voltage in the windings a and b opposite to the voltage which was applied thereto , this induced voltage then driving flyback current . considering the flyback current path in detail , it will be appreciated that , when the windings a and b are de - energized , collapsing magnetic fields cause the outer end of winding a to be negative with respect to the outer end of winding b , just the opposite of the polarity of the applied voltage when transistor q bb was on . starting for purposes of analysis at the outer end of winding b , positive current flows from winding b through free - wheeling diode d bt ( not the diode d bb across the transistor q bb just turned off ) to the positive supply line 28 . since switching transistor q at is still turned on in accordance with the commutation sequence , transistor q at completes the flyback current path back to the outer end of winding a . thus , the windings a and b are effectively shunted during flyback intervals by a network comprising diode d bt , allowing flyback current to circulate in the windings . during flyback intervals , no current circulates through the power supply . in particular , no current flows through the current - sensing resistor 34 . in any event , no attempt is made to directly measure the flyback current during the decay interval . rather , the decay time is simulated by the circuitry 50 , as described above . thus , during the decay time interval , the up / down counter 64 counts down . when the count of zero is reached , the output of the decoder 68 again resets the flip - flop 60 to begin another cycle . as noted above with reference to fig2 due to circuit losses , typically the flyback current decays slightly faster than the current rise such that , at the end of the off time interval , the current is below the threshold . thus , when the exemplary switching transistor q bb is again turned on , current rises through the lower threshold , resetting the counter 64 at the appropriate moment . if it is desired to simulate a decay time which is not equal to the rise time , but which is a linear function thereof , the adaptive timing circuit 62 of fig1 can readily be modified to alter the frequency of the clock pulse source 66 depending upon whether a risetime interval or a decay time interval is occurring . another approach is to either preset the counter 64 to a count other than zero , or to arrange the decoder 68 to detect a count other than zero . as another modification , rather than a digital counter in the adaptive timing circuit 62 , an analog timer ( not shown ) may be employed . a suitable analog timer charges a capacitor from a constant - current source during the rise or on time interval . the capacitor voltage then reflects the duration of the measured on time . to establish the off time interval , the capacitor is discharged through a constant - current sink until a zero voltage or other lower reference voltage is reached . referring now to fig3 an electrical schematic diagram of typical commutation circuitry is shown , including a connection for the switch off line . important elements of the fig3 circuitry are a commutation control clock 76 and a rotation sequencer 78 comprising a bi - directional ring counter 80 and driver logic 81 , in turn comprising six or gates 82 , 84 , 86 , 88 , 90 and 92 , each corresponding to one of the power switching transistors q at through q cb of fig1 . the function of the commutation control clock 76 is to output periodic commutation sequence advancing signals to the bi - directional ring counter 80 clock input . as is known in the art , there are a variety of techniques for determining when the commutation sequence is to be advanced . typically , these techniques require knowledge of the actual rotor position . thus , a rotor position signal is shown as an input to the commutation control clock 76 . many such means are possible , such as light choppers or hall effect sensors . one particularly advantageous approach is that which is described in commonly - assigned wright u . s . pat . no . 4 , 162 , 435 , which also happens to be the approach employed in the above - incorporated alley et al u . s . pat . no . 4 , 250 , 435 . it will be appreciated that the present invention is not directed to the specific details of the commutation control or the manner in which current threshold signals are determined . rather , the present invention is directed to an implementation technique which assumes the existence of a basic motor control system in accordance with known principles . referring briefly to the commutation sequence chart of fig4 the series of lines designated q at through q cb designates specifically during which of the commutation intervals the power switching transistors of fig1 are energized . it will be seen that at any instant , one of the top switching transistors q at , q bt or q ct is energized , and one of the bottom switching transistors q ab , q bb or q cb is energized , thus energizing two of the three motor windings a , b and c by appropriately connecting respective ends thereof to the positive and negative dc supply conductors 28 and 30 &# 39 ;. the commutation sequence shown results in motor rotation in one direction as interval numbers repeatedly count up going from left to right across the drawing sheet , and results in motor rotation in the other direction as interval numbers repeatedly count down going from right to left across the drawing sheet . referring again to fig3 to implement the fig4 commutation sequence , the six outputs q 0 through q 5 of the ring counter 80 are appropriately connected to the inputs of the or gates of the driver logic 81 . for example , the transistor q at is switched on during commutation interval numbers 0 and 1 . accordingly , the inputs of the or gate 82 are connected to the q 0 and q 1 outputs of the ring counter 80 . the three upper switching transistors q at , q bt and q ct are used for commutation only . thus , the output lines at , bt and ct of the respective or gates 82 , 84 and 86 are connected directly to suitable transistor gate drivers 94 , 96 and 98 which are of conventional design compatible with the gate drive requirements of the particular power switching transistors employed . as previously described , the lower switching transistors of fig1 q ab , q bb and q cb are rapidly switched on and off during each commutation interval to provide motor winding current control . thus , in order to turn off the selected one of the lower switching transistors q ab , q bb or q cb when the upper threshold current limit is reached and the switch off line goes low , the switch off line is connected to enabling inputs of three and gates 100 and 102 and 104 having their signal inputs respectively connected to lines ab , bb and cb from the or gates 88 , 90 and 92 . the outputs of the and gates 100 , 102 and 104 supply respective lines ab &# 39 ;, bb &# 39 ;, and cb &# 39 ; which , in turn , are connected to respective transistor gate driver circuits 106 , 108 and 110 . while specific embodiments of the invention have been illustrated and described herein , it is realized that numerous modifications and changes will occur to those skilled in the art . it is therefore to be understood that the appended claims are intended to cover all such modifications and changes as fall within the true spirit and scope of the invention .