the inventor of the subject matter disclosed and claimed herein has met the above - mentioned needs in the art by developing a programmable upc interface which is easily reconfigurable by resizing the transmit and receive shift registers to accept any of a variety of communications protocols used by the communications devices connected to the input / output communications lines of the upc interface . although the present invention will be described with respect to a preferred embodiment of a upc interface which interfaces to a supervisory computer for a supervisory control and data acquisition ( scada ) system , those skilled in the art will appreciate that the description given herein is for exemplary purposes only and is not intended in any way to limit the scope of the invention . in other words , the programmable receive and transmit shift registers of the invention may be used in interfaces to a variety of other communications devices which support a variety of bit - oriented protocols as described herein . all questions regarding the scope of the invention should be resolved by referring to the appended claims . in a preferred embodiment of the invention , the upc interface described herein is embodied in a single upc board and is connected via a vme bus to a vme computer processor board ( backplane ). the upc interface of the invention typically provides an interface between the vme computer backplane and the communications channels to any of a plurality of remote data collection units ( rtus ) at remote data collection sites . in the implementation illustrated in fig1 eight transmit / receive lines with control lines are provided on each upc board , where each transmit / receive line communicates via a standard rs - 232 line interface to the rtus . typically , the rtus monitor some open or closed loop process to provide control data to the supervisory control ( host ) computer via the upc interface of the invention . as noted above , previous scada systems have been limited in that the supervisory control computer and rtus have had to communicate over the communications lines via a single predetermined bit - oriented protocol . such an arrangement has proven to be unacceptable because as the rtus are updated and replaced there is no guarantee that the replacement rtus will have the same data protocols as the rtus which they are replacing . the upc interface of the invention has thus been designed to support a plurality of bit - oriented protocols by providing a plurality of independently programmable , highly configurable input / output channels on each upc board . in other words , the upc interface of the invention may be configured to transmit / receive a data packet of any size between 1 and 256 bits for the transfer of data to / from the rtus . fig1 illustrates a preferred embodiment of a upc board including a upc interface in accordance with the invention . as illustrated , a common vme bus interface 100 interfaces an internal bus of the upc board to a vme bus connected to the vme computer backplane of the supervisory control ( host ) computer . the host computer typically has a bit protocol which is known to the system programmer and has previously been used for all communications to / from the rtus . however , in accordance with the present invention , the upc interface of the invention permits the host computer to communicate with rtus despite any variations in the bit protocols of the rtus . the upc board further includes a vme / communications controller 102 responsive to a clocking signal from a clock 104 to control the timing of interface 100 for passing data as well as to control the read or write direction of the interface 100 . interface 100 may be a conventional interface which cycles in response to timing signals provided by vme / communications controller 102 in a manner known to those skilled in the art . the upc board preferably further includes an interrupt controller 106 such as an intel 82c59 processor which is responsive to a plurality of event driven system interrupts from the host processor to provide appropriate control of data communications to / from the rtus when various error conditions and the like are detected . in a preferred embodiment , 44 interrupts per upc board are recognized . as further illustrated in fig1 a plurality of input / output ( i / o ) groups 108 - 114 are connected to the internal bus of the upc board . these i / o groups 108 - 114 provide separate i / o channels for communication with the rtus via an rs - 232 or other known line interface . in a preferred embodiment , each i / o group 108 - 114 is identical and comprises two receive / transmit channels and two control channels . access to these i / o groups 108 - 114 is preferably controlled by separate i / o addresses , bus arbitration and the like provided by vme / communications controller 102 . the circuitry of each i / o group will now be described with further reference to fig1 . for ease of description , only i / o group 108 will be described , for , as noted above , i / o groups 110 , 112 , and 114 are typically identical in design to i / o group 108 . as illustrated in fig1 each i / o group includes a buffer 116 which provides a gateway or a pathway to the interface 100 via the upc board internal data bus and hence a connection to the vme bus and vme computer backplane . each i / o group further includes a conventional direct memory access ( dma ) circuit 118 for providing addresses to data stored in a conventional memory 120 . dma circuit 118 and memory 120 are connected via a common data bus 122 to respective usarts 124 and 126 for each receive / transmit line . as will be described in more detail below with respect to fig2 usarts 124 and 126 are typically identical and are specially designed in accordance with the invention such that they may be dynamically reconfigured to support a plurality of different bit - oriented protocols . each input / output group further includes a group controller 128 which controls accesses to data bus 122 by arbitrating between dma transfers and vme communications activity , preferably on a first come - first served basis . a preferred embodiment of a usart in accordance with the invention is illustrated in fig2 . as noted above , usart 124 and 126 are typically identical . each usart in accordance with the invention preferably includes a control register 200 for detecting flags in an input data stream and for providing receive start and transmit start signals and the like . the receive circuitry of each usart is particularly characterized in accordance with the invention by a bit counter 202 which can be programmed by the user via the interface to the vme bus to count a predetermined number of bits in the received serial input data to control grouping and storage of the input data in memory 120 . in other words , as will be described in more detail below with respect to fig3 the programmer may set a terminal count ( tc ) value in bit counter 202 so that the number of specified bits in the received serial input data is grouped and stored in memory 120 in accordance with the bit protocol of the rtu connected to that particular usart . a receive control state machine 204 responsive to the terminal count tc from bit counter 202 , a baud rate clock , a receive start signal from control register 200 and the received serial input data controls the loading and shifting of a fixed bit length ( preferably 8 - bit ) receive shift register 206 . receive control state machine 204 and fixed bit length receive shift register 206 together control the serial to parallel conversion of the received serial input data which is to be placed on the data bus 122 and stored in memory 120 . as illustrated in fig2 receive control state machine 204 may also send interrupt requests to group controller 128 and dma requests to the dma circuit 118 . message interrupts may also be sent via data bus 122 to vme / communications controller 102 . as will be described in more detail below , receive control state machine 204 further controls the loading and clocking of bit counter 202 . finally , as illustrated , the receive circuitry further includes a latch 208 for double buffering the parallel output data from the receive shift register 206 before storing it in memory 120 at an address specified by dma circuit 118 . the transmit circuitry of each usart is also characterized by a bit counter 210 for counting the bits of an output data stream . as illustrated in fig2 bit counter 210 is programmed via the vme bus with a terminal count tc corresponding to the word bit length of the output protocol of the rtu connected via the line interface to that particular usart . preferably , the output data is output in the ieee or ansi standard format to a line interface which in turn transmits the serial output data to the rtu at the other end of that communications line . as will be described in more detail below with respect to fig4 a transmit control state machine 212 controls the parallel to serial data conversion via a fixed bit length ( 8 - bits in a preferred embodiment ) transmit shift register 214 by providing appropriate load and clock signals to transmit shift register 214 and bit counter 210 . in a preferred embodiment , the transmit data read from memory 120 is double buffered at latch 216 before being output via transmit shift register 214 . the serial output data from transmit shift register 214 is then provided to the line interface via latch 218 and transmitted at the specified baud rate under control of a clock signal from clock 104 . as noted above , receipt of serial input data is controlled by receive control state machine 204 . a flow diagram of a preferred embodiment of receive control state machine 204 is illustrated in fig3 . as illustrated , receive control state machine 204 starts its processing at step 300 . it then determines at step 302 whether a start data receipt signal has been received from control register 200 to enable data reception . when an enable signal has been received , at step 304 the word bit length of the serial data input word ( i . e ., the bit protocol length of the rtu transmitting to the usart over the current input line ) is loaded from a holding register into bit counter 202 as the terminal count to . in a preferred embodiment , this bit length may range from 1 to 256 bits in accordance with the bit protocol of the remote rtu . of course , greater bit lengths may be readily supported using the techniques of the invention . receive shift register 206 is then initialized at step 306 . once a start bit in the serial input data is received at step 308 , the bit clock 104 is synchronized to the start bit at step 310 for the specified baud rate r . the receive circuitry of the usart is then ready to receive data . when a rising edge of clock 104 is received at step 312 , the serial input data is clocked into receive shift register 206 at step 314 and bit counter 202 is incremented by clk for each bit received . receive control state machine 204 then determines at step 316 whether the bit counter 202 has reached terminal count tc . if not , control state machine 204 determines at step 318 whether the receive shift register 206 is full . if the receive shift register 206 is not full , clk is checked at steps 320 and 312 for the next rising clock edge . the next bit of serial input data is then clocked at step 314 as before . however , if the receive shift register 206 is determined at step 318 to be full , a dma request is sent over data bus 122 to dma circuit 118 at step 322 to request that the contents of the receive shift register 206 be transferred to memory 120 via buffer 208 at the address specified by the dma circuit 118 . the receive shift register 206 is then initialized at step 324 and control returned to step 314 for clocking in the next serial input data bit upon receipt of the next rising edge of the clock . the above process continues until it is determined at step 316 that the terminal count tc has been reached . at this time , it is determined at step 326 whether receive shift register 206 is full . if receive shift register 206 is full , the contents of the receive shift register 206 are transferred at step 328 to memory 120 via latch 208 at the address specified by dma circuit 118 . it is then determined at step 330 whether more data packets of serial input data are being received , and if so , the word bit length of the next data packet is loaded into bit counter 202 at step 332 and the receive shift register 206 initialized at step 334 . the serial input data is then clocked in at step 314 on the rising edge of the clock signal as before . this process continues until it is determined at step 330 that no further input data is coming . at that time , processing control returns to step 302 . however , if it is determined at step 326 that receive shift register is not full , it is known that tc ( and hence the word bit length of the transmitting rtu ) is not a multiple of the bit length of the receive shift register 206 . since memory 120 generally stores data in bytes ( eight bits ), the data bits remaining in the receive shift register 206 are shifted at step 336 to the least significant bit position of the receive shift register 206 before being transferred to memory 120 at step 338 . steps 336 and 338 help assure that the data stored in memory 120 may be easily reconfigured into a contiguous serial bit stream . as noted above , transmission of serial output data is controlled by transmit control state machine 212 . a flow diagram of a preferred embodiment of transmit control state machine 212 is illustrated in fig4 . as illustrated , transmit control state machine 212 starts its processing at step 400 . once transmission is enabled at step 402 by , for example , receipt of a start transmission signal from control register 200 , the word bit length of the receiving rtu is then loaded into bit counter 210 at step 404 . as with the receive circuitry , the word bit length may be any value between 1 and 256 bits . a dma request is then sent to dma circuit 118 and data is read from memory 120 starting at the address specified by the dma circuit 118 . this data is double buffered by latch 216 and then transferred to transmit shift register 214 at step 406 . after monitoring the clock at steps 408 and 410 for the next rising clock edge , the data stored in transmit shift register 214 is then shifted out one bit at a time at step 412 at each rising edge of the clock signal from transmit control state machine 212 . bit counter 210 is also incremented at step 412 by clk for each bit of data shifted out of transmit shift register 214 . transmit control state machine 212 then checks at step 414 whether the terminal count tc has been reached . if not , it is determined at step 416 whether the transmit shift register 214 is empty . if not , the next bit of data is shifted out of transmit shift register 214 at step 412 upon receipt of the next rising clock edge . however , if the transmit shift register 214 is empty , a further dma request is sent to memory 120 and another byte of data is transferred from memory 120 to transmit shift register 214 via latch 216 at step 418 . the above process continues until tc is reached at step 414 . it is then determined at step 420 whether there is further data to be transmitted by checking the contents of latch 216 . if it is determined at step 420 that latch 216 is empty , transmission stops and control returns to step 402 . however , if there is further data to be transmitted , the word bit length for the next data packet is loaded into the bit counter at step 422 and the next byte of data is transferred from memory 120 into the transmit shift register 214 via latch 216 at step 424 in accordance with the techniques described above . the parallel data provided from memory 120 is thus serialized by transmit shift register 214 , output to the line interface via latch 218 and transmitted to the rtu connected to that transmission line . those skilled in the art will appreciate that the upc board described above contains several highly configurable i / o channels which are readily configurable due to the user &# 39 ; s ability to dynamically resize the transmit and receive shift registers for any of the various protocols of the transmitting and receiving rtus connected to the respective usarts of the upc board of the invention . this technique is in marked contrast to prior art techniques using fixed bit length shift registers to transmit / receive data in a particular predetermined protocol . to further illustrate the beneficial features of the invention , operation of the upc board will be described for the transmission and receipt of 12 - bit data words via a standard rs - 232 line interface using a usart having 8 - bit shift registers configured as herein described . in transmit mode , a terminal count of 12 is stored in bit counter 210 and the usart configured for transmission of 12 - bit data words . dma circuit 118 is thus instructed to transfer [( int ( 12 / 8 + 1 )*( n 12 - bit words )] bytes from memory 120 to the usart connected to the appropriate communications line . the designated usart accepts the bytes transferred from memory 120 and assembles them into the appropriate 12 - bit serial data stream as follows . to transmit ten 12 - bit words ( where it is assumed that the first bit is a start bit and the last bit can be a stop bit or a data bit ), bit counter 210 is first loaded with the value 12 . an external baud rate generator is then set to the desired rate ( t ) and provided to transmit control state machine 212 . at a user defined address , memory 120 is then loaded with the transmission data as follows ( where bit 0 is typically set to 0 as the start bit of a word ): ______________________________________address nnnn + 00 word0 bits 0 - 7 nnnn + 01 word0 bits 8 - 11 nnnn + 02 word1 bits 0 - 7 nnnn + 03 word1 bits 8 - 11 nnnn + 04 word2 bit 0 - 7 nnnn + 05 word2 bits 8 - 11 + + + + + nnnn + 18 word9 bit 0 - 7 nnnn + 19 word9 bits 8 - 11______________________________________ dma circuit 118 is then loaded with the address nnnn + 00 identifying the beginning of the data stored in memory 120 which is to be transmitted . a byte count register within dma circuit 118 is then loaded with a value of 20 to indicate that 10 words are to be transmitted , where 2 bytes are included in each word . data transfer is then enabled and transfer start signal sent to transmit control state machine 212 from control register 200 . transmission then proceeds in accordance with the flowchart described above with respect to fig4 . however , such transfer is also subject to arbitration by group controller 128 for competing vme and dma requests for data bus 122 . data is transmitted until bit counter 210 reaches the terminal count tc or the transmit shift register 214 has shifted 8 bits out under control of the transmit control state machine 212 . any excess bits remaining in the transmit shift register 214 are discarded . transmit control state machine 212 then sends a dma request to dma circuit 118 to transmit another byte of data into memory 120 . at the appropriate time , this byte ( or word fragment ) is transferred to latch 216 and to transmit shift register 214 for transmission . at this point , latch 218 will output a serial stream of data which will appear to have come from a 12 - bit usart . however , by changing the terminal count stored in the bit counter 210 , the transmit channel can be easily reconfigured to transmit words having any number of bits desired . in receive mode , a terminal count of 12 is stored in bit counter 202 and the usart configured for receipt of 12 - bit data words . dma circuit 118 is thus instructed to transfer [( int ( 02 / 8 + 1 )*( n 12 - bit words )] bytes from the appropriate usart to memory 120 . memory 120 accepts the bytes transferred from the usart and stores them in the conventional manner . the process of receiving serial input data proceeds as follows . to receive ten 12 - bit words ( where the first bit may be a start bit and the last bit can be a stop bit or a data bit ) bit counter 202 is first loaded with the value 12 . the baud rate generator is then set to the desired data rate r . dma circuit 118 is then requested to provide a pointer to the next free location in memory 120 . for example , dma circuit 118 may specify address nnnn for storage of received data . dma circuit 118 also has its byte count register loaded with the value of 20 to indicate that 10 words of 2 bytes each are to be stored in memory 120 . dma circuit 118 is then enabled and a receive start signal provided to receive control state machine 204 from control register 200 . data reception may then begin . data is then received by receive shift register 206 on a serial basis until bit counter 202 reaches the terminal count tc or the receive shift register 206 is full . the receive control state machine 204 then requests the transfer of a byte of data to latch 208 and from latch 208 into the next memory location in memory 120 . the usart then receives the next word or word fragment of input data and continues receiving data in accordance with the flow diagram of fig3 until the byte count in dma circuit 118 is reached . at that time , memory 120 will have received data in the following form : ______________________________________address nnnn + 00 word0 bits 0 - 7 nnnn + 01 word0 bits 8 - 11 nnnn + 02 word1 bits 0 - 7 nnnn + 03 word1 bits 8 - 11 nnnn + 04 word2 bits 0 - 7 nnnn + 05 word2 bits 8 - 11 + + + + + nnnn + 18 word9 bits 0 - 7 nnnn + 19 word9 bits 8 - 11______________________________________ to the user and the transmitting rtu , the receiving usart functions like a 12 - bit device even though it may have a receive shift register of only 8 bits . however , as noted above , the usart of the invention may be reconfigured to allow reception of input data words having bit lengths from 1 to 256 bits in accordance with the techniques herein described . although an exemplary embodiment of the invention has been described in detail above , those skilled in the art will readily appreciate that many additional modifications are possible in the exemplary embodiment without materially departing from the novel teachings and advantages of the invention . for example , the transmit and receive shift registers may have fixed bit lengths of 16 bits , 32 bits , and the like . in addition , the line interfaces may be in the isdn format and the data packets formulated in the appropriate protocol . accordingly , all such modifications are intended to be included within the scope of this invention as defined in the following claims .