the present invention will be better understood upon reading the following detailed description of an embodiment and variations thereof in connection with the drawings . the illustrative embodiment of an interface device 200 shown in fig2 includes a bus interface block 201 , a programmable state machine ( psm ) 202 , serialization hardware 203 , a clock controller and / or clock generator block ( for simplicity &# 39 ; s sake referred to hereinafter as the clock control block or ccb , without loss of generality ) 204 and a bit counter 205 . these five basic elements are interconnected as follows . the bus interface block 201 is connected to a system bus 206 . commands and responses may be transferred by the bus interface block 201 between the psm 202 and the system bus 206 as required . commands received by the bus interface block 201 from the system bus 206 may also be transferred to the ccb 204 , as required . data is transferred by the bus interface block 201 between the serialization hardware 203 and the system bus 206 . the psm 202 executes a software program by which it generates command signals which control operation of the serialization hardware 203 , the clock controller and clock generator 204 and the bit counter 205 , as well as responses and other outputs handled by the bus interface block 206 . the interface provided by the interface service 200 to the external world is serial i / o signals 208 . each of the blocks shown in fig2 is now described in greater detail , as they are constructed in the illustrative embodiment . the bus interface block 201 provides outside access to the interface device 200 . the bus interface block 201 connects the interface device 200 to the system bus 206 and to other outside signals 207 . the signals may include bus control signals such as a bus clock , chip select , address signals , data signals , etc . the bus clock may also be the system clock , or that signal may be distributed as a separate signal . the system bus 206 or outside signals 207 may also carry interrupt signals , such as may be used to indicate a transmit event or a receive event , etc ., which are connected to the interface device 200 through the bus interface block 201 . the bus interface block 201 may also receive a system reset signal , as well as other external signals 207 not part of the system bus 206 , but required by the interface device 200 . the bus interface block 201 may simply receive and buffer signals , which are then communicated to the internal elements requiring them . alternatively , the bus interface block may latch the signals before communicating them to the internal elements requiring them , or the signal values at a determined point in time may be loaded into registers . the bus interface block 201 may use any or all of these techniques in the manner known in the art , in order to supply the interface device 200 elements with the information needed to perform their respective functions . the outputs of the bus interface block 201 include signals for configuring and controlling each element of the interface device 200 . for example , there may be a reset signal responsive to the system reset signal mentioned above . there may be a signal designating a clock prescale value , whose purpose is discussed further below . a clock control signal may command the ccb 204 to turn the clock on or off . a register may hold values designating parameters for the serialization hardware 203 , such as parity , the number of bits in the shift registers and status information . the bus interface block 201 may further include one or more memory locations that together form a transmit and / or receive buffer for the serialization hardware 203 . the bus interface block 201 may include one or more registers through which program commands and data can be transferred to the psm 202 . the bus interface block 201 may further include other signals for controlling i / o operations on the external signals mentioned above , as well as on the system bus 206 and through the serialization hardware 203 . some parameters and settings may be controlled by values held in registers loaded by the psm 202 , as described below . the programmability of the interface device 200 is provided by the psm 202 . however , it should be noted that the psm 202 does not include an arithmetic logic unit ( alu ) or other circuits conventionally associated with microprocessors , digital signal processors or other general purpose computing engines , although that possibility is not precluded . the psm 202 sequences predefined operations to be performed , rather than computing arithmetic results that define operations or parameters thereof . the psm 202 includes three main circuits , a programmable logic array ( pla ) 301 , memory 302 and address control 303 . some number , m , of the pla 301 outputs 304 are fed back through the address control 303 to select the next instruction to be executed , based on the current state of the psm 202 . a remaining number , n , of the pla 301 outputs 305 control other elements of the interface device 200 , according to the state reached in the sequence of instructions executed by the psm 202 . the pla 301 executes the instructions ; the memory 302 stores the instructions . in this embodiment , the pla 301 does not modify the instructions of the memory 302 , although that possibility is not precluded . memory 302 may include one or more registers that hold values modifiable by the psm 202 representing some setup parameters of operation of elements controlled by the psm 202 . for example , there may be a register whose value controls serialization parameters . outputs of the psm 202 may be latched or non - latched , as shown in fig4 . a pla 301 output 400 is received as data by a latch 401 . the latch also receives an enable signal 402 that indicates when the pla 301 output 400 is valid . a clock 403 , for example the system clock , causes the latch 401 to transfer the value of the pla 301 output 400 to the latched output 404 , if the enable signal 402 indicates that the pla 301 output 400 is valid at the time the clock signal 403 is received . the pla 301 output 400 may also be simply combined with the enable signal 402 using an and gate 405 or the like , to produce a non - latched output signal 406 . the psm 202 of the illustrative embodiment executes three classes of instruction : control instructions , program flow instructions and timing / power saving instructions . the instructions include those shown in the table , below . the serialization hardware 203 converts parallel data carried by the system bus 206 into serial data carried by serial i / o signals 208 according to a desired serial i / o standard or converts serial data carried by serial i / o signals 208 according to the desired serial i / o standard into parallel data carried by the system bus 206 . each interface device 200 according to the illustrative embodiment is a half - duplex device . in order to provide full - duplex operation , two interface devices 200 would be connected in parallel and each configured to perform the operations of one direction of the full - duplex channel . when configured to serialize data , the serialization hardware 203 includes a shift register arranged for parallel - to - serial operation , a parity generator and output controls . when configured to receive serial data the shift register is arranged for serial - to - parallel operation . the serialization hardware 203 also uses the parity generator for receiving serial data . when receiving serial data , the serialization hardware 203 also employs an edge detector to determine when the start bit of a sequence has been received . detection of the start bit is used , together with the wait and delay instructions , as described below in connection with the ccb 204 to save power when the interface device 200 is not transmitting or receiving data . the ccb 204 of the illustrative embodiment receives a system clock from outside the interface device 200 and redistributes it to elements of the interface device 200 requiring a clock signal . alternatively , the ccb 204 could generate a clock internally and redistribute it to elements of the interface device 200 requiring a clock signal . as shown in fig5 the ccb 204 receives the system clock 501 into a prescaler 502 that divides or multiplies the clock from the system rate to the rate used by the interface device 200 . the prescaler 502 can be a set of programmable divider circuits or can include a phase - locked loop frequency multiplier . the output 509 of the prescaler 502 clocks a synchronization gate 503 , as well as a wait latch 504 and a delay latch 505 . the wait latch 504 and the delay latch 505 receive wait 506 and delay 507 commands , respectively , from the psm 202 , and latch them as enable inputs to the synchronization gate 503 . the synchronization gate 503 produces the interface device clock signal 508 , which can be selectively turned on and off by the wait 506 and delay 507 commands of the program executing in the psm 202 . 1 the output 509 of the prescaler 502 is a clock signal internal to the ccb 204 , which is not selectively turned on and off . this internal clock signal 509 is not widely distributed , hence does not impose a significant power load on the circuit , but allows the ccb 204 to determine when the wait command or delay command has terminated . the wait instruction is particularly useful in connection with the edge detection of the serialization hardware 203 . the psm 202 can execute a wait instruction , causing the ccb 204 to shut off the clock , until an edge , i . e ., a start bit , is detected by the serialization hardware 203 . execution of the software program by the psm 202 then resumes , processing any incoming data . the wait instruction can be made to test for other signals , such as a clear to send ( cts ) signal , such as used in modem applications . the fifth element of the illustrative embodiment of interface device 200 is the bit counter 205 . this counter saves programming instructions , hence memory space , because bit counting code need not be written into the loops of the software program of the psm 202 which operate on the serial data one bit at a time . instead , a register stores the number of bits over which to perform an operation . at the end of each loop , the psm 202 increments the bit counter 205 via a suitable group 1 , group 2 or group 5 instruction and then checks the value in the bit counter 205 against that in the register storing the number of bits over which to perform the operation . program branching and other decisions can depend on the result of this test . alternatively , the no overhead loop instruction can implement all the required jumps and branches to execute a loop using the bit counter 205 , using only one instruction . when such a loop completes , execution continues with the next instruction in the memory 302 . the present invention has now been described in connection with a number of specific embodiments thereof . however , numerous modifications , which are contemplated as falling within the scope of the present invention , should now be apparent to those skilled in the art . therefore , it is intended that the scope of the present invention be limited only by the scope of the claims appended hereto .