in the industrial process control system shown in fig1 , a distributed architecture is designed to be used in different sil environments , so that if a high sil is required it can be provided , but if a low sil is all that is needed , the system can be reduced in complexity in order to reduce unnecessary costs . an exemplary industrial process control system 10 , comprises a workstation 12 one or more controllers 14 and a gateway 16 . the workstation 12 communicates with the controllers 14 and the gateway 16 via ethernet connections 18 to one or more control networks 13 . multiple ethernet connections 18 provide redundancy to improve fault tolerance . the workstation 12 may be connected via a conventional ethernet connection 11 to another external network 15 . a controller 14 will now be described in more detail with reference to fig2 and 3 . fig2 illustrates a schematic diagram of the controller 14 comprising an input assembly 22 , a processor assembly 24 and an output assembly 26 . in this schematic illustration the input assembly 24 and output assembly 26 are on different backplanes but they may equally well share a single backplane . assemblies 22 , 24 , 26 are created from one or more communications backplane portions which have three slots to accommodate up to three modules together with termination assemblies which have one , two , or three slots , and which interface to field sensors and transducers . a termination assembly may straddle two contiguous backplane portions . a module comprises a plug in card with multiple connectors for plugging onto a communications backplane and a termination assembly . it will be appreciated that having three slots in a communications backplane portion is one design option and other design options with greater ( or fewer ) slots are possible without departing from the scope of the invention as defined in the appended claims . fig3 illustrates a possible physical configuration of the controller 14 . in this embodiment of the invention , the input assembly 22 , output assembly 26 and processor assembly 24 are physically separated from one another by grouping the modules of different types onto separate communications backplanes . in the example shown , the input assembly 22 comprises two communications backplane portions , 22 ′, 22 ″. the first backplane portion 22 ′ has a triplex input termination assembly and three input modules 22 a , 22 b , 22 c , the second backplane portion 22 ″ has a duplex input termination assembly 22 ″ and two input modules 22 d , 22 e . the processor assembly 24 comprises a single processor backplane portion 24 ′ having three processor modules 24 a , 24 b and 24 c . the output assembly 26 comprises two backplane portions 26 ′, 26 ″. the first backplane portion 26 ′ has a duplex output termination assembly with two output modules 26 a , 26 b and the second backplane portion 26 ″ has a simplex output termination assembly with a single output module 26 c . the flexibility of the input assembly 22 , will now be described , in more detail with reference to fig4 . an input assembly 22 comprises one or more backplane portions and termination assemblies 22 ′ 22 ″ 22 ′″ etc . for example , a triplex portion 22 ′ having three modules 22 a , 22 b , 22 c might be used for high availability requirement , a duplex portion 22 ″ having two modules 22 d , 22 e might be provided for fault tolerant applications and a simplex portion 22 ′″ with a single module 22 f might be provided for failsafe applications . the termination assemblies may be provided with different types of field conditioning circuits . for example assembly 22 ′ may be provided with a 24v dc field conditioning circuit 41 , assembly 22 ″ may be provided with a 120v dc field conditioning circuit 42 , and assembly 22 ′″ may be provided with a 4 - 20 ma field conditioning circuit 43 . similarly possible configurations are shown for an output assembly 26 . it will be appreciated that numerous configurations of backplane portions and termination assemblies with various different numbers of modules and various different types of field conditioning circuits are possible and the invention is not limited to those shown in these examples . where an assembly provides more than one module for redundancy purposes it is possible to replace a failed module with a replacement module whilst the industrial process control system is operational which is also referred to herein as online replacement ( i . e . replacement is possible without having to perform a system shutdown ). online replacement is not possible for a simplex assembly without interruption to the process . in this case various “ hold last state ” strategies may be acceptable or a sensor signal may also be routed to a different module somewhere else in the system . the processor assembly configures a replacement processor module using data from a parallel module before the replacement module becomes active . the field conditioning circuits 41 , 42 , 43 transform a signal received from a sensor monitoring industrial process control equipment to a desired voltage range , and distribute the signal to the input modules as required . each field conditioning circuit 41 , 42 , 43 is also connected to field power and field return ( or ground ) which may be independently isolated on a channel by channel basis from all other grounds , depending on the configuration of the input termination assembly . independent channel isolation is the preferred configuration because it is the most flexible . the field conditioning circuits 41 , 42 , 43 comprise simple non active parts and are not online replaceable . fig5 and fig6 illustrate the flexibility of the architecture described herein showing different configurations for a triplex system for generating a signal with a high availability requirement . referring to fig5 , a three module input assembly 51 receives a signal from a sensor 50 via a field conditioning circuit in termination assembly 54 . the field conditioning circuit 54 transforms the signal to a desired voltage range and distributes the signal to three replicated input modules 53 a , 53 b , 53 c . each input module processes the signal and the results are sent to a two out of three voter 52 to generate a result signal in dependence thereon . referring to fig6 , replicated sensors 60 a , 60 b , 60 c each send a signal to a respective simplex assemblies 61 a , 61 b , 61 c via respective field conditioning circuits in termination assemblies 64 a , 64 b , 64 c . each input module 63 a , 63 b , 63 c processes the signal and sends an output to a two out of three voter 62 to generate a signal in dependence thereon . it will be appreciated that many variations and configurations are possible in addition to those illustrated here . fig7 illustrates schematically an input module 70 in accordance with the present invention : an input module 70 comprises eight isolated channels 71 . each channel 71 receives signals 72 , 73 a , 73 b from field conditioning circuits in a termination assembly 74 . each channel communicates with a field programmable gate array ( fpga ) 75 which interfaces to an backplane ( not shown ) via a non - isolated backplane interface 76 . light emitting diodes ( leds ) 77 are used to indicate status of the module via red and green indicators . it will be appreciated that having eight channels is one design option and other design options with greater ( or fewer ) channels are possible without departing from the scope of the invention as defined in the appended claims . programmable i / o pins of the fpga 75 are used to directly drive low power isolated supplies , supplying the channels 71 without the need for additional power amplifiers . referring now to fig8 the channel 71 is shown in more detail . the input channel 71 comprises a blown fuse circuit 111 receiving blown fuse signal 72 , a primary input circuit 113 receiving primary sense signal 73 a and a secondary input circuit 112 receiving secondary sense signal 73 b . the input channel also comprises microcomputers 114 and 115 for processing signals 72 , 73 a and 73 b . the input channel 71 further comprises a power isolator circuit 118 receiving power inputs 78 from the fpga 75 which will be described in more detail below . the signal isolator 20 receives a command signal 80 and returns a response signal 79 which are routed to and from the microprocessor 114 . the signal isolator 120 is not discussed further here . isolated power for each input channel 71 is created with direct drive from pins of the fpga 75 by complementary square wave signals 78 . multiple pins of the fpga may be paralleled to provide greater drive current capability . fig9 shows the power isolator 118 in more detail . the signals 78 are input into a transformer 103 ( which in the preferred embodiment is an ultra miniature 1 : 1 or 1 : 1 . 5 isolation transformer ). clamping diodes 101 are used to ensure that the output pins of the fpga 75 are protected from switching transient spikes from the leakage inductance of the transformer 103 . low value damping resistors 102 may be used to absorb ringing from any switching transients . the advantages of this approach are the small size , low cost , and small number of components that are required to generate the isolated supply . in a preferred embodiment of the invention , multiple isolated channels 71 are driven with square wave signals having slightly different excitation frequencies or phases to distribute the emi / rfi peak amplitudes , which provides improved radiated and conducted emissions performance . all of the input and output modules require a power supply which is protected from overvoltage faults . fig1 is an illustration of a power supply for providing two voltages to an input or output module . the supply is protected from over - voltage faults in such a manner that over - voltage faults can be detected and tolerated as will now be described . a primary dc / dc converter 121 provides a 3 . 4v +/− 1 % output from a 24v input . this output is not directly protected from an over - voltage fault . however , low dropout linear regulators 122 and 125 discussed below protect downstream circuitry from an over - voltage fault on the dc / dc converter 121 . a low dropout linear regulator 122 receives this output where it is regulated down to 3 . 2v +/− 1 %. if the low dropout regulator 122 develops an input - to - output short - circuit fault , the worst case fault , then the output supplied cannot rise above 3 . 4v , which is still within the acceptable recommended operating range for 3 . 3v +/− 5 % integrated circuitry . extreme over - voltage fault protection components , consisting of a series fuse 123 and transient over - voltage protection avalanche diode 124 , are provided for the case where the dc / dc converter 121 develops an output fault condition where the output would otherwise rise above the tolerance level of the low dropout regulators 122 and 125 . a further over - voltage protected output voltage is provided by the combination of a further low dropout regulator 125 providing 1 . 3v +/− 1 % from the 3 . 4v source and an ultra - low dropout regulator 126 . in this example the ultra low dropout regulator 126 provides 1 . 2v +/− 1 % from the 1 . 3v source voltage provided by the further low dropout regulator 125 , at an amount of current that is adequate to supply an fpga core , so that there is no possible short circuit fault that will result in more than 1 . 3v being applied to an fpga core and resulting in un - predictable operation . a supervisor micro - computer 127 is responsible for enabling the regulators 122 , 125 , 126 in sequence after the output from the dc / dc converter 121 has stabilized . this provides a confidence level in the functionality of the linear supplies . the supervisor micro - computer 127 may generate a test signal 128 to the converter 121 and / or regulators 122 , 125 , 126 to coerce the generated voltages by +/− 0 . 5 %, allowing the linear operation of the linear regulators to be verified by monitoring the generated voltages via monitor signals 129 a , 129 b , 129 c , 129 d . this test can be performed either just at power - up , or periodically during normal system operation if desired . the supervisor micro - computer 127 is also responsible for monitoring the over / under - voltage operation of the linear regulators , and shutting the system down using enable signals in the event of an out - of - tolerance fault using enable signals 130 a , 130 b , 130 c . an alternative to protecting power supplies from over - voltage faults is to sense the over - voltage condition with a comparator and then “ crowbar ” the output to deliberately create a short circuit fault which must blow the fuse , but saves the system from the consequences of an over - voltage event . obviously this alternative would be difficult to test and maintain . the advantage of the arrangement of the present is that un - testable crowbar circuits are not required , with their large and un - testable components . with an isolated dc / dc power supply such as 121 shown in fig1 it is desirable to provide noise filtering . fig1 illustrates a power supply protection circuit in accordance with the present invention . a capacitor network 119 provides a low impedance path for any high frequency noise spikes due to the interaction of a primary winding being driven by a switching power supply controller , and the primary - secondary coupling parasitic capacitances of a flyback transformer . filter capacitors in the network 119 are sized so that the individual capacitors can withstand the necessary isolation voltage , and the series combination of two of them ( half that of a single one ) provides enough filtration . the resulting system can withstand a short circuit or open circuit fault of either of the capacitors . it will be appreciated that certain features of the invention , which are , for clarity , described in the context of separate embodiments , may also be provided in combination in a single embodiment . conversely , various features of the invention which are , for brevity , described in the context of a single embodiment , may also be provided separately , or in any suitable combination . it is to be recognized that various alterations , modifications , and / or additions may be introduced into the constructions and arrangements of parts described above without departing from the scope of the present invention as defined in the appended claims .