the fabrication of a lateral pnp transistor , according to this invention , can be easily integrated into the npn transistor fabrication previously described with reference to fig1 - 7 . in this respect , the pnp transistor can be considered a free lateral pnp transistor because it involves no major additional processing steps , although the steps are somewhat modified , from those required for the npn technology . referring now to fig8 a structure of an n - epitaxial layer 70 and an overlying field oxide 72 are fabricated according to the previously described npn technology at the step shown in fig3 . the n - epitaxial layer can , for instance , be that part 74 of the n - epitaxial layer isolated from the pnp transistor by the isolation region 36 , as shown in fig3 . a level of photo - resist 76 is deposited on top of the thin portion of the field oxide 72 and its width w b defines the width of the base of the pnp transistor . this photo - resist layer 76 is deposited at the same time as the blocking mask 44 shown in fig5 which is used to mask the implant of the p - type resistor 46 . the photo - resist level 76 is then plasma - hardened or alternatively hardened by ultraviolet radiation and then high temperature post - baked . thereafter the ion implant for forming the p - type resistor passes through the field oxide 72 and forms a nascent emitter region 78 and a nascent collector region 80 . then a second photo - resist layer 84 and 86 is simultaneously deposited and then patterned to define an emitter contact window 88 , a collector contact window 89 as shown in fig9 and base contact and resistor contact windows ( not shown ) corresponding to base contact and resistor contact 50 of fig6 . the second photo - resist layer 86 partially overlays the first photo - resist layer 76 and also overlays part of the nascent collector region 80 , as shown in fig9 . as a result , the first photo - resist layer 76 continues to define the emitter - base junction of the pnp transistor . this junction is self - aligned and no additional level - to - level tolerances need to be assigned to the emitter - base junction . previous methods of fabricating a lateral pnp transistor within an npn technology have removed the first photo - resist layer 76 before replacing it with the second photo - resist layer 86 . the second photo - resist layer was thus necessarily symmetric with respect to the base and could not provide the graded collector to be described later . furthermore , the emitter - base junction was not self - aligned and thus required larger emitter areas to compensate for level - to - level tolerances of the two photo - resist layers 76 and 86 . then , as shown in fig1 , the emitter contact window 88 and collector contact window 89 are opened by etching off the silicon dioxide 72 by reactive ion etching . all of the nascent emitter region 78 and part of the nascent collector contact region 80 are exposed by this opening . emitter and collector contacts are then formed by a high dose ion implantation of boron to make the two regions degenerate or nearly degenerate . then , as illustrated in fig1 , both levels of photo - resist 76 , 84 and 86 are stripped and an interconnection metallurgy 90 and 91 are deposited . the pattern covers all of the exposed emitter and collector regions 78 and 80 . the interconnection metallurgy 90 and 91 can be either an aluminum - silicon - copper alloy or heavily doped p - type polysilicon . in the latter case , the emitter / collector ion - implantation step can be avoided . instead , a heat treatment step is carried out to drive the p - type dopants from the polysilicon 90 and 91 in to form a p + emitter 92 and a p + collector contact region 94 . the part of the nascent collector 80 which is not further doped in this drive - in forms a main collector 96 . the combination of the main collector region 96 and the p + collector contact region 94 forms a graded collector . the doping profile that results from this drive - in is shown by profile 98 in fig1 . profile 82 is the doping profile for the epitaxial layer 70 which has a depth of about 0 . 7 μm on top of the substrate 20 . profile 84 represents the acceptor concentration introduced by the resistor ion implantation which has a depth of about 0 . 5 μm . the profiles shown in fig1 are the final profiles which may have been broadened by heat treatment subsequent to implantation . of course , when the acceptor concentration n a as represented by profile 84 falls below the donor concentration n d as represented by profile 82 , then the effective carrier type and concentration is represented by the larger value . as is evident by the two p - type profiles 84 and 98 , the collector contact region 94 is not simply a surface contact but extends approximately to the depth of the main collector 96 . as a result , the conduction path is substantially horizontal into the collector 96 and 94 . the absence of additional conduction paths vertically into the area of the emitter contact 92 eliminates slow response on the emitter side of the pnp transistor caused by vertical injection . the n - type doping profile 82 is the profile for the base , the p - type profile 84 is the profile for the main collector 96 , and the p - type profile 98 is the profile for the emitter 92 and the collector contact region 94 . also included in the structure for the lateral pnp transistor but not shown in fig1 is an n + reach - through to the n - base region 70 . this reach - through is similar to the reach - through 34 to the n + sub - collector 28 shown for the npn transistor of fig7 . both reach - throughs perform the same purpose of providing a surface contact to a buried region . aside from the compatibility of this process with npn technology , the lateral pnp transistor of fig1 has the following advantages . the base width w b is defined by a single level of photo - resist 76 , although additional side diffusion occurs in a controlled way in subsequent heat treating steps . the emitter - base junction is self - aligned so that the emitter 92 can be designed with minimal surface area . a small emitter 92 reduces vertical injection and provides higher lateral injection efficiency , has a low capacitance and thus provides a higher speed transistor and one with higher current gain . the main collector 96 has a low doping or a high resistance and thus helps to reduce the field concentration at the base - collector junction , resulting in an increased punch - through voltage and reduced avalanche multiplication at the collector - base junction . the highly doped and relatively large p + collector contact region 94 reduces the collector resistance . an alternative embodiment of the resultant pnp transistor is shown in fig1 . device definition is provided by thick oxide regions 100 and 102 ( or called shallow sio 2 trenches ) that reach down to the n + layer 70 . device isolation is provided by an even deeper oxide region 104 ( or called deep sio 2 trenches ) that reaches down to the p - substrate 20 and replaces the p + isolation region 36 . a n + reach - through 106 extending down to the n + epitaxial layer 70 provides a contact to the base 106 . in other respects , this device corresponds to the pnp transistor shown in fig1 . a numerical simulation of the pnp transistor illustrated in fig1 shows that if the base width w b equals 1 . 5 μm and if the area of the emitter 92 equals 8 . 2 μm 2 , then the current gain is equal to 43 at v eb = 0 . 6 v ( i c = 82 na ) and is 2 . 2 at v eb = 0 . 9 v ( i c = 0 . 32 ma ). in comparison with a conventional lateral pnp transistor with an emitter area of 12 . 7 μm 2 and with resistor ion implants in both the emitter and collector , this device at v eb = 0 . 9 v has twice the current gain and 27 % less capacitance across the emitter - base junction .