referring now to fig2 , an example of a disk controller is shown . a disk controller 100 includes a processing module 102 , a bus interface module 107 , a buffer 104 , a universal serial bus ( usb ) controller 106 , and a serial advanced technology attachment ( sata ) controller 108 . the usb controller 106 includes a usb interface module 110 that interfaces with the host 14 and a usb direct memory access ( dma ) module 112 that communicates with the usb interface module 110 , the processing module 102 , and the buffer 104 . the sata controller 108 includes a sata interface module 114 that interfaces with the disk drive 18 and a sata dma module 116 that communicates with the sata interface module 114 , the processing module 102 , and the buffer 104 . the bus interface module 107 communicates with the usb dma module 112 , the sata dma module 116 , the processing module 102 , and the buffer 104 . the bus interface module 107 provides the usb dma module 112 and the sata dma module 116 a dma path to the buffer 104 . when the host 14 issues a write command to write data on the disk drive 18 , the usb dma module 112 receives the data from the host 14 via the usb interface module 110 and stores the data in the buffer 104 . the sata dma module 116 retrieves the data from the buffer 104 and forwards the data to the sata interface module 114 , which writes the data to the disk drive 18 . when the host 14 issues a read command to read data from the disk drive 18 , the sata dma module 116 receives the data from the disk drive 18 via the sata interface module 114 and stores the data in the buffer 104 . the usb dma module 112 retrieves the data from the buffer 104 and forwards the data to the usb interface module 110 , which outputs the data to the host 14 . buffering data during read / write operations can decrease the rate at which data is transferred between the usb interface module 110 and the sata interface module 114 . consequently , performance of high - speed interfaces such as usb 3 . 0 and sata 3 . 0 can degrade despite having data transfer rates of 5 gigabits per second ( gbps ) and 6 gbps , respectively . moreover , buffering data during read / write operations generates many interrupts which the processing module 102 has to process and which can increase overhead and downgrade io performance . buffering data during read / write operations can be eliminated by using a high - speed bridge instead of using a buffer between the usb and sata controllers . as explained below , the bridge may work , for example , with bulk - only transport ( bot ) and usb attached scsi ( uas ) protocols of the usb interface and native command queuing ( ncq ) protocol of the sata interface . the bridge determines a command phase , a data phase , and a status phase of data transfer between the usb and sata controllers based on the bot and uas protocols . the command phase includes command conversion . the data phase includes data transfer according to the command . the status phase includes returning status of the command and associated data transfer to the host . the bridge can automatically convert an incoming command from the host . the sata dma module can directly receive / transmit data from / to the bridge without using the buffer . after determining that a data transaction is completed , the bridge returns status automatically based on the information received from the sata controller . the bridge thus improves throughput and optimizes io performance . the present disclosure uses usb and sata interfaces for example only . the teachings of the present disclosure are not limited to usb and sata interfaces . the teachings of the present disclosure can be applied to other interfaces used to transfer data at high speed between a host and a disk drive . referring now to fig3 , a disk controller 200 includes a processing module 202 , a usb controller 204 , a bridge module 206 , a usb dma module 222 , a bus interface module 208 , and a sata controller 108 . the disk controller 200 can be implemented as an integrated circuit ( ic ) or a system - on - chip ( soc ). as explained below , a command handling module 220 in the bridge module 206 interrupts the processing module 202 when a usb command is received from the host 14 . the processing module 202 converts the usb command to a sata command . when the command is a write command to write data from the host 14 to the disk drive 18 , the sata controller 108 accesses the memory of the host 14 and transfers data from the memory of the host 14 directly to the disk drive 18 . when the command is a read command to read data from the disk drive 18 , the sata controller 108 reads data from the disk drive and transfers data from the disk drive 18 directly to the memory of the host 14 . the bridge module 206 allows the sata controller 108 to directly receive / transmit data from / to memory of the host 14 without using the buffer 104 ( not shown ). the usb controller 204 includes the usb interface module 110 , a receive fifo 212 , and a transmit fifo 214 . the usb interface module 110 stores the command received from the host 14 in the receive fifo 212 . the bridge module 206 includes an arbitration module 218 , a command handling module 220 , a data handling module 224 , a status handling module 228 , and an interrupt handling module 230 . the bridge module 206 does not include the buffer 104 . the command handling module 220 interrupts the processing module 202 when an incoming command is received from the host 14 . the processing module 202 converts the command received from the host 14 to a sata command and outputs the sata command to the sata controller 108 via the bus interface module 208 . the sata controller 108 is configured to transfer data according to the sata command after the sata controller 108 is configured to transfer data according to the sata command , the sata controller 108 sends a request to the data handling module 224 for bus ownership to transfer data directly between the sata controller 108 and the usb controller 204 . depending on the type of command ( e . g ., read or write command ), the arbitration module 218 arbitrates bus ownership and data flow between the usb dma module 222 and the bridge interface module 206 . the arbitration module 218 can also perform the arbitration for the command phase , data phase , and status phase automatically without software involvement . during the read operation , the arbitration module 218 arbitrates bus ownership and data flow from the data handling module 224 to the transmit fifo 214 to provide a direct data path for the sata dma module 116 to transfer the data read from the disk drive 18 directly to the memory of the host 14 via the usb controller 204 . during the write operation , the arbitration module 218 arbitrates bus ownership and data flow from the receive fifo 212 and the data handling module 224 to provide a direct data path for the sata dma module 116 to transfer the data from the memory of the host 14 directly to the disk drive 18 via the usb controller 204 . when each read / write command is completed , the sata interface module 114 provides information directly to the status handling module 228 . the status handling module 228 can interpret the information and send out status automatically without software intervention once the data phase is completed without error . while only one sata controller is shown for simplicity of illustration , a plurality of sata controllers can be interfaced with the bus interface module 208 . for each additional sata controller interfaced with the bus interface module 208 , the bridge module 206 can include an additional set of the data handling module 224 and the status handling module 228 . the usb dma module 222 handles dma for the plurality of sata controllers and allows each sata controller to transfer data using a corresponding set of the data handling module 224 and the status handling module 228 . the data handling module 224 provides a direct data path for the sata dma module 116 to receive / transmit data directly from / to the memory of the host 14 without storing the data in the buffer 104 . the data handling module 224 actively transfers data in and out of the usb controller 204 according to the sata command . the status handling module 228 also generates status information for a command when the status handling module 228 receives command completion information directly from the module sata interface module 114 after the data transfer corresponding to the command is completed . if an error occurs at the usb controller 204 , the interrupt handling module 230 notifies the processing module 202 . referring now to fig4 , data flows 300 for a usb bulk - only transport ( bot ) command are shown . at 302 , the host 14 issues a usb bot command . at 304 , the usb controller 204 receives the usb bot command . at 306 , the usb dma module 222 or the command handling module 220 interrupts the processing module 202 . the processing module 202 converts the usb bot command to a sata command and sends the sata command to the sata controller 108 . at 308 , the sata controller 108 receives the sata command . the sata controller 108 prepares to transfer data according to the sata command . at 310 , the sata controller 108 transfers data directly from the host 14 to the disk drive 18 if the usb command is a write command . at 312 , the sata controller 108 transfers data directly from the disk drive 18 to the host 14 if the usb command is a read command . at 314 , the sata controller 108 interrupts the processing module 202 when the data transfer is completed . at 318 , at the same time , the sata interface module 114 sends information directly to the status handling module 228 . the status handling module 228 interprets the information and generates status without involvement of the processing module 202 . at 320 , the host 14 receives the status information . referring now to fig5 , data flows 400 for usb attached scsi ( uas ) commands are shown . at 402 , the host 14 issues usb uas commands ( e . g ., a burst of up to 32 commands at a time per one sata port ). at 404 , the usb controller 204 receives the usb uas commands . the usb uas commands are not merged together . at 406 , the usb dma module 222 or the command handling module 220 interrupts the processing module 202 ( e . g ., up to 32 times ). the processing module 202 converts the usb uas commands to sata commands ( one - to - one conversion ) and sends the sata commands to the sata controller 108 ( e . g ., up to 32 at a time ). at 408 , the sata controller 108 receives the sata commands ( e . g ., up to 32 at a time ). the sata controller 108 prepares to transfer data according to the sata commands . the sata controller 108 sets up one dma operation for the data transfers ( read or write operations ) of all the sata commands . at 410 , the sata controller 108 transfers data directly from the host 14 to the disk drive 18 if the usb commands are write commands . for example , the sata controller 108 performs up to 32 write operations ( data transfers ). at 412 , the sata controller 108 transfers data directly from the disk drive 18 to the host 14 if the usb commands are read commands . for example , the sata controller 108 performs up to 32 read operations ( data transfers ). at 414 , the sata controller 108 interrupts the processing module 202 when the data transfers for the sata commands are completed ( e . g ., up to 32 at a time ). at 416 , the processing module 202 receives the interrupts ( e . g ., up to 32 at a time ). at 418 , at the same time , the sata interface module 114 sends information directly to the status handling module 228 ( e . g ., up to 32 at a time ). the status handling module 228 interprets the information and generates status without involvement of the processing module 202 . at 420 , the host 14 receives the status information ( e . g ., up to 32 status information at a time ). referring now to fig6 a , a flowchart for command handling according to the present disclosure is shown . at 502 , the command handling module 220 is idle after power up . at 504 , the command handling module 220 receives a usb read / write command from host 14 . at 508 , the command handling module 220 notifies the processing module 202 , and the processing module 202 converts the received usb command to a sata command . at 510 , the processing module 202 initiates a sata read / write operation . at 512 , data is transferred directly between the high - speed bridge and the sata controller 108 . during the direct data transfer between the high - speed bridge and the sata controller 108 , if the command handling module 220 receives a next command , the command handling module 220 notifies the processing module 202 , which processes the next command in parallel to the previous command for which the data is being transferred . at 514 , a determination is made if an error occurred during data transfer and / or command processing ( e . g ., at 504 , 508 , 510 , and / or 512 ). at 516 , if an error occurred during data transfer and / or command processing ( e . g ., at 504 , 508 , 510 , and / or 512 ), the interrupt handling module 230 takes charge and notifies the processing module 202 for further instruction , and the command handling module 220 returns to the idle state . referring now to fig6 b , a method 600 for status handling according to the present disclosure is shown . at 602 , the status handling module 228 is idle after power on . at 604 , when the sata controller 108 completes any read / write command , the sata controller 108 interrupts the processing module 202 . at the same time , the sata interface module 114 notifies and sends command completion information directly to the status handling module 228 . at 606 , a determination is made if data transfer for current command is completed . at 608 , if data transfer for current command is completed , a determination is made if the data transaction is completed without error . at 610 , the status handling module 228 sends out status without involvement of the processing module 202 . at 612 , if an error occurred in the data transaction , the interrupt handling module 230 notifies the processing module 202 for further instruction . the foregoing description is merely illustrative in nature and is in no way intended to limit the disclosure , its application , or uses . the broad teachings of the disclosure can be implemented in a variety of forms . therefore , while this disclosure includes particular examples , the true scope of the disclosure should not be so limited since other modifications will become apparent upon a study of the drawings , the specification , and the following claims . for purposes of clarity , the same reference numbers will be used in the drawings to identify similar elements . as used herein , the phrase at least one of a , b , and c should be construed to mean a logical ( a or b or c ), using a non - exclusive logical or . it should be understood that one or more steps within a method may be executed in different order ( or concurrently ) without altering the principles of the present disclosure . as used herein , the term module may refer to , be part of , or include an application specific integrated circuit ( asic ); an electronic circuit ; a combinational logic circuit ; a field programmable gate array ( fpga ); a processor ( shared , dedicated , or group ) that executes code ; other suitable hardware components that provide the described functionality ; or a combination of some or all of the above , such as in a system - on - chip . the term module may include memory ( shared , dedicated , or group ) that stores code executed by the processor . the term code , as used above , may include software , firmware , and / or microcode , and may refer to programs , routines , functions , classes , and / or objects . the term shared , as used above , means that some or all code from multiple modules may be executed using a single ( shared ) processor . in addition , some or all code from multiple modules may be stored by a single ( shared ) memory . the term group , as used above , means that some or all code from a single module may be executed using a group of processors . in addition , some or all code from a single module may be stored using a group of memories . the apparatuses and methods described herein may be implemented by one or more computer programs executed by one or more processors . the computer programs include processor - executable instructions that are stored on a non - transitory tangible computer readable medium . the computer programs may also include stored data . non - limiting examples of the non - transitory tangible computer readable medium are nonvolatile memory , magnetic storage , and optical storage .