fig1 represents a device msec for securing a memory mem , according to one embodiment of the present invention , arranged between the memory mem and circuits using the memory , such as a processing unit cpu . the memory is of word - accessible type , of 8 , 16 or 32 bits for example , and is divided into zones z ( 1 ), z ( 2 ), . . . z ( i ), . . . z ( n ). the device msec is connected to the memory and to the processing unit so as to intercept the orders for writing and reading the memory , sent by the processing unit . the device msec controls the memory to execute these orders and transmits the word read in response to an order for reading a word in the memory . fig2 represents an embodiment in hard - wired logic of the security device msec according to one embodiment of the present invention . the device msec comprises an address register lta that keeps the address ad applied at input of the device msec instead of the memory mem throughout an operation of accessing the memory , including the signature calculation . the address register lta comprises for example d flip - flops or latches each storing bits constituting the address ad applied at input of the device msec . the device msec comprises an address management circuit amg comprising inputs receiving activation signals cs and read or write selection signals rw , received by the security device msec instead of the memory mem , and an address input connected to the address register lta . the device msec comprises a first multiplexer mux 1 comprising two groups of inputs . the inputs of a first group of inputs are respectively connected to the inputs of signals for activating cs and read - or write - selecting rw the device msec , and to the address register lta . the inputs of the second group of inputs are connected to address outputs adc , activation outputs csc , and read or write selection outputs rwc of the address management circuit amg . the multiplexer mux 1 comprises address outputs adm , activation outputs csm and read or write selection outputs rwm , connected to an interface int of the memory mem . the security device msec further comprises a first signature calculation circuit siga to calculate a current signature . a word input of the signature calculation circuit siga receives the words dr read in the memory mem . the signature calculation circuit siga comprises an output connected to a comparator cmp 1 which compares the current signature calculated by the circuit siga with an expected signature sm stored in a signature storage memory sigmem . an expected signature is selected in the signature storage memory sigmem using the most significant bits adh of the address ad applied at input of the device msec . the output of the comparator cmp 1 is connected to the d input of a flip - flop ff comprising a clock signal input and a non - inverting q output supplying an error indicator signal er . the state of the signal er corresponds to the state of the signal applied to the d input of the flip - flop following a pulse applied to the clock signal input of the flip - flop . the words dr read in the memory mem are applied to an output do of the device msec through a tristate buffer tsb , in response to a read order intended for the memory . for this purpose , the buffer tsb receives the signals cs , rw , csig as control signals and copies at the output do the words read in the memory mem when these control signals indicate that the memory is read - selected and that the signature calculation is not active . in the opposite case , the output of the buffer is in the high impedance state , such that the data read in the memory mem cannot be accessed at the output do . the device msec also comprises a control circuit ctl for controlling the address management circuit amg , the signature storage memory sigmem and the flip - flop ff . the control circuit ctl comprises inputs respectively receiving the activation signals cs , and the read or write selection signals rw , applied at input of the device msec , and the address stored in the address register lta . the control circuit applies a signature calculation activation signal csig to the circuit amg and to the selection input of the multiplexer mux 1 , and receives an end of signature calculation signal esc from the circuit amg . the control circuit also applies a synchronization signal sync to the clock signal input of the flip - flop ff , and activation css and read or write selection rws signals to the memory sigmem . the control circuit manages a memory busy signal by that is sent at output of the device msec . advantageously , the device msec comprises a second signature calculation circuit sigb for calculating a new current signature . the circuit sigb receives the words dr read in the memory mem through a second multiplexer mux 2 , another input of which is connected to the word output dw of a word register reg . the output of the calculation circuit for calculating a new signature sigb is connected to a word input of the signature storage memory sigmem . the multiplexer mux 2 comprises a selection input receiving a test result signal tst supplied by the circuit amg . the word register reg comprises a word input connected to a word input din of the device msec , to which a word to be written in the memory mem is applied . the word output dw of the register reg is also connected to an input for words to be written of the memory . the word register is for example made up of d flip - flops or latches . a clock signal ck applied at input of the device msec is distributed to the memory mem , to the signature storage memory sigmem , to the register reg , and to the address management amg and control ctl circuits . one embodiment of the address management circuit amg is represented in fig3 . in this figure , the circuit amg comprises a counter cpt that is initialized upon a change of state of the read or write selection signal rw applied at input of the address management circuit . the counter cpt is triggered upon a change of state of the signature activation signal csig sent by the control circuit ctl . the counter cpt is designed to successively generate , at an output adlc , all of the addresses of a memory zone z ( i ). at its address output adc , the circuit amg supplies an address the most significant bits of which correspond to the most significant bits adh of the address applied at input of the address management circuit , and the least significant bits of which are supplied by the output adlc of the counter cpt . the counting frequency is supplied by a clock signal ck 1 that is for example the clock signal ck applied at input of the circuit amg . preferably , the frequency of the counting clock signal is a multiple of the frequency of the clock signal ck applied at input of the address management circuit , so as to read the words of a memory zone z ( i ) more rapidly when calculating the signature of this memory zone . in this case , the clock signal ck 1 must also be applied to the signature calculation circuits siga and sigb to synchronize the signature calculation with the scanning of the memory zone z ( i ). when the last address of the memory zone z ( i ) is reached , the counter cpt supplies an end of counting signal that is applied on the end of signature calculation signal output esc of the address management circuit amg . furthermore , the circuit amg comprises a comparator cmp 2 a first input of which receives the least significant bits adl of the address applied at input of the address management circuit , and a second input of which is connected to the output adlc of the counter . the comparator cmp 2 supplies a signal representative of the result of the comparison at the output tst of the address management circuit . this signal indicates whether or not the address adc at output of the circuit amg corresponds to the address ad stored in the address register lta . the expected signatures of the memory zones z ( i ) are calculated and stored in the signature storage memory sigmem , when the device msec is initialized for example . the signature calculation circuits siga and sigb are initialized at the beginning of a signature calculation by an initialization signal rs that can be the memory activation signal cs or the signal csig . the initialization signal is also applied to the initialization input of the flip - flop ff , in order to initialize the state of the flip - flop . upon receiving a write order , a word to be saved din and a write address are respectively present at the word din and address ad inputs of the security device msec , and the signals for activating cs and read or write selecting rw the device are respectively on 1 and 0 . the word to be saved , which is present at the word input din , is stored in the word register reg . similarly , the address present at the address input ad is stored in the address register lta . the control circuit ctl triggers the signature calculation , using the signal csig applied to the address management circuit amg and to the multiplexer mux 1 . the multiplexer mux 1 then selects the outputs adc , rwc and csc of the circuit amg and applies them to the interface int of the memory mem . in parallel , when the signal csig changes state , the counter cpt of the circuit amg is activated and scans the memory zone z ( i ), successively supplying at each cycle of the clock signal ck 1 the address adc of all of the words in the zone z ( i ) to which the write address stored in the address register lta belongs . the zone z ( i ) is selected by the most significant bits adh of the address applied at input ad of the device msec . then , at its word output dr , the memory mem successively supplies all of the words saved in the memory zone z ( i ) to the signature calculation circuits siga , sigb . during the scanning of the words of the memory zone z ( i ), when the address adc generated by the counter cpt of the management circuit amg is equal to the address ad present at the input of the device msec , the signal tst at output of the address management circuit changes state and controls the multiplexer mux 2 so that the latter applies at input of the signature calculation circuit sigb , not the word read in the memory , but the word stored in the register reg . at the next cycle of the clock signal ck 1 , the signal tst changes state , such that the next words , read in the memory zone z ( i ), are applied to the signature calculation circuit sigb . thus , the memory zone z ( i ) is only read once to simultaneously calculate the current signature sa and the new current signature sb , the word read in the memory zone at the write address being replaced on - the - fly by the word to be written to calculate the new signature sb . at the end of the counting performed by the counter cpt , the signature calculation circuits siga and sigb respectively supply the current signature sa of the memory zone z ( i ), i . e ., representative of the current content of the memory zone , and a new current signature sb of the memory zone in which the word to be saved , appearing in the word register reg , replaces the word appearing in the memory mem at the write address supplied by the address register lta . the new current signature sb is thus representative of the content of the memory zone as it will be after writing the word to be saved at the write address . also at the end of the counting , the address management circuit amg sends the end of signature calculation signal esc to the control circuit ctl . upon receiving this signal , the circuit ctl controls the signature storage memory sigmem using selection css and read rws signals for reading the expected signature sm of the memory zone z ( i ), and applies the synchronization signal sync to the flip - flop ff . the current signature sa coming from the signature calculation circuit siga and the expected signature sm read in the signature storage memory sigmem are then applied to the inputs of the comparator cmp 1 . the control circuit ctl changes the state of the signal csig to control the multiplexer mux 1 so as to apply to the interface int of the memory mem the signals cs and rw applied at input of the device msec , and the address stored in the address register lta . thus , the word appearing in the register reg is saved in the memory mem . the control circuit also controls the signature storage memory sigmem using the signals css and rws so as to save the new current signature sb therein as expected signature sm of the memory zone z ( i ). the write address in the memory sigmem is given by the most significant bits adh of the address stored in the address register lta . if one or more words saved in the memory zone z ( i ) have undergone an alteration , the current signature sa supplied by the signature calculation circuit siga is different from the expected signature sm read in the signature memory . in this case , the output signal of the comparator cmp 1 indicates a signature error and causes a state change of the flip - flop ff following the application of the synchronization signal sync . the indicator signal er at output of the device msec then indicates an error . in the opposite case , if the current signature sa is equal to the expected signature sm read in the signature storage memory sigmem , the output signal of the comparator cmp 1 does not indicate any error and does not trigger any state change of the flip - flop ff . the writing of the word in the memory mem , and the update of the signature storage memory sigmem can be done systematically , even in the event of an error detection , given that the error indicator signal er supplied by the device msec can for example trigger the activation of an alarm signal , the erasure of the memory zone z ( i ) or of the entire memory mem , or even the read - and / or write - disabling of the memory . alternatively , the error indicator signal er is applied at input of the control circuit ctl which does not control the writing of the word in the memory and the updating of the signature memory if the signal er indicates an error . upon receiving an order for reading a word in the memory mem , a read address is present at the input ad of the device msec and stored in the address register lta . the input signals cs and rw of the device are on 1 . these signals are applied to the memory mem by the multiplexer mux 1 . the memory mem then supplies the word read on the output do of the device . before or after the execution of the order for reading the memory mem , the control circuit ctl controls the address management circuit amg and the multiplexer mux 1 to calculate a signature of the memory zone z ( i ) in which the address read is located . the signature is calculated in the same way as during the execution of a write order . at the end of the signature calculation , the current signature sa supplied by the signature calculation circuit siga and the expected signature sm of the memory zone z ( i ) are applied to the input of the comparator cmp 1 . according to the result of the comparison performed by the comparator cmp 1 , the error indicator signal er at output of the device msec indicates an error or not . it shall be noted that during the execution of an order for reading the memory mem , the second signature calculation circuit sigb also produces a signature sb , but the latter is not saved in the memory sigmem . the memory busy signal by generated by the control circuit ctl is in the busy state during the execution of write and read orders and during the corresponding signature calculations , to indicate to the processing unit cpu accessing the memory mem that the latter is busy and cannot execute new write or read orders . the division of the memory mem into memory zones z ( i ) impacts both the size of the signature storage memory sigmem and the time required to calculate a signature . indeed , the greater the number of memory zones , the smaller their size is , and the greater the number of expected signatures to be stored in the memory sigmem is . however , the time for calculating a signature will be all the shorter as the size of the memory zones is reduced . fig4 and 5 respectively show a procedure of writing 10 and a procedure of reading 30 in a memory mem in accordance with the method according to one embodiment of the present invention . these procedures are respectively executed by a security device comprising a processing unit , at each write and read access to an address ad [ d ] in a zone z ( i ) of the memory , d being a word to be read or to be written in the memory . in the first step 11 of the procedure of writing 10 the word d , an error indicator er is initialized at a value indicating that no error has been detected . the device msec also initializes the value k of a counter at the start address ad [ z ( i )] of the memory zone z ( i ), as well as variables sa , sb provided for respectively receiving the cumulative values of a current signature and of a new current signature of the zone z ( i ). in the next step 12 , the device msec calculates the next value of the current cumulative signature sa using the previous value of the current cumulative signature sa and of the word mem ( k ) read in the memory at the address given by the value k of the counter . in the next step 13 , the device msec compares the value k of the counter with the write address ad [ d ] of the word d to be written in the memory zone z ( i ). if the value k of the counter is different from the write address , the device msec calculates the next value of the new current signature sb using the previous value of the signature sb and of the word mem ( k ) previously read in the memory . on the other hand , if the value k of the counter is equal to the write address , the next cumulative value of the new current signature sb is calculated using the previous value of the new signature and the value of the word d to be written in the memory . the word d to be written in the memory zone z ( i ) thus replaces the word saved in the memory at the write address in the calculation of the signature sb . in the next step 16 , the value k of the counter is incremented by 1 to point on the word saved at the next address in the memory zone z ( i ). in the next step 17 , the device msec tests whether the end of the memory zone z ( i ) is reached , for example by comparing the value k of the counter with the start address of the next zone z ( i + 1 ). if the end of the memory zone z ( i ) is not reached , the procedure continues at step 12 where the device msec calculates the next values of the current cumulative signature sa and of the new cumulative signature sb . in the opposite case , the procedure continues at step 18 , during which the device msec reads the expected signature sm [ z ( i )] of the memory zone z ( i ) in a memory zone sigmem reserved for storing signatures , and compares the current signature sa obtained with the expected signature read . if the current signature sa is equal to the expected signature , the device msec saves the word d in the memory zone z ( i ) at the address ad [ d ] and the expected signature of the memory zone z ( i ) is updated in the memory zone sigmem with the value of the new cumulative signature sb . on the other hand , if the current signature sa is different from the expected signature , the value of the error indicator er is changed to indicate an error . the read procedure 30 takes place in a manner substantially identical to the write procedure 10 , except that during the reading of a word in the memory the signature of the memory does not change . it is not therefore necessary to calculate a new current signature . in the first step 31 of the read procedure 30 shown in fig4 , the security device msec initializes the error indicator er at a value indicating that no error has been detected . it also initializes the value k of the counter at the start address ad [ z ( i )] of the memory zone z ( i ), and the value of the current cumulative signature sa . in the next step 32 , the device msec calculates the next value of the current cumulative signature sa using the previous value of the signature sa and the word mem ( k ) read in the memory at the address given by the value k of the counter . in the next step 33 , the value k of the counter is incremented by 1 to point on the word situated at the next address in the memory . in the next step 34 , the security device msec tests whether the end of the memory zone z ( i ) is reached by the value k of the counter . if the end of the memory zone z ( i ) is not reached , the procedure continues at step 32 where the next value of the current cumulative signature sa is calculated . in the opposite case , the procedure continues at step 35 , during which the security device msec reads the expected signature sm [ z ( i )] of the memory zone z ( i ) in the memory zone sigmem , and compares the current signature sa with the expected signature . if the current signature sa is equal to the expected signature , the word d is read in the memory zone z ( i ) at the address ad [ d ]. on the other hand , if the current signature sa is different from the expected signature , the value of the error indicator er is changed to indicate an error . it will be understood by those skilled in the art that various other alternative embodiments of the method and the device according to the present invention are possible , particularly concerning the measures taken when an inconsistency is detected between a current signature and an expected signature . thus , it is not necessary to prevent the word from being written and the signature memory from being updated in the event that an inconsistency is detected between the expected signature and the current signature calculated . the order of the operations of reading a word in the memory and of checking signatures can also be inverted . thus , the word read can systematically be supplied to the processing unit , the signature checking merely producing a signal er representative of a possible signature error that is then used by the processing unit connected to the device . in the event that a signature inconsistency is detected , any appropriate measure can thus be taken by the device or by the processing unit . furthermore , any type of word cumulative signature calculation algorithm can be used to determine the signature of a memory zone . thus , the signature calculation algorithm can be invariable or use an invariable signature key . in one advantageous embodiment of the present invention , the size of the signatures obtained is identical to the size of the words , whether they comprise 8 , 16 or 32 bits . generally , the comparison method applied by the signature comparator cmp 1 is adapted to the signature calculation algorithm chosen , so as to detect the existence of a correspondence between the current signature and the expected signature revealing the absence of error . indeed , depending on the algorithm chosen , two signatures may correspond and thus not reveal any error without necessarily being identical . in addition , as it will be understood from the above description , all or part of the functions of the security device msec described above can be produced by software , i . e ., using a programmed calculation unit , whether or not distinct from the processing unit cpu that accesses the memory mem , or by logic circuits . it is possible for the signature storage memory sigmem not to be a specific memory , but merely be a reserved memory zone of the memory mem to be secured . in general , the memory sigmem can be internal or external to the security device msec . all of the above u . s . patents , u . s . patent application publications , u . s . patent applications , foreign patents , foreign patent applications and non - patent publications referred to in this specification and / or listed in the application data sheet , are incorporated herein by reference , in their entirety .