fig6 represents a top - level view of three variations of a differential circuit , for example the differential circuit of fig4 . fig6 ( a ) represents the differential circuit as shown in fig4 , which as explained above has a non - zero average voltage across the electrodes in the transducer 402 . fig6 ( b ) represents the differential circuit as shown in fig4 with the bridge capacitor inputs inverted . this only reverses the polarity of the voltage waveforms on the bridge capacitors , which does nothing to reduce the non - zero average voltage across the electrodes . fig6 ( c ) represents the differential circuit as shown in fig4 with the inputs to the bridge capacitors swapped . this only moves the voltage waveform from core c a to core c b and moves the voltage waveform from core c b to c a , which also does nothing to reduce the non - zero average voltage across the electrodes . in essence , all three circuits in fig6 are the same . it would be desirable to design a circuit that has a substantially zero average voltage across the electrodes in the transducer to reduce surface charge build - up and reduce drift in dc offset . fig7 ( a ) and 7 ( b ) show the two separate cores c a and c b of a differential system with each core having two variable capacitors . core c a includes variable capacitors c 1a and c 2a , and core c b includes variable capacitors c 1b and c 2b . the corresponding capacitors of the two cores react to the input signals in a substantially identical way ( i . e ., c 1a = c 1b and c 2a = c 2b ) and move in the same direction due to a transducer input . for example when an accelerometer like the one shown in fig1 experiences an acceleration input , the common electrode for core c a and the common electrode for core c b both move in the same direction . however , the electrical signals processed by the two cores have opposite polarity . fig7 ( a ) and 7 ( b ) show four inputs a , b , c and d to the cores ; and two outputs e and f from the cores . fig7 ( a ) shows the nominal direct connection used by the circuit in fig4 and depicted in fig6 ( a ). in the configuration of fig7 ( a ), variable capacitor c 1a is coupled to input a , variable capacitor c 2a is coupled to input b , variable capacitor c 1b is coupled to input c , variable capacitor c 2b is coupled to an input d , variable capacitors c 1a and c 2a share a common node that is coupled to output e , and variable capacitors c 1b and c 2b share a common node that is coupled to an output f . fig7 ( b ) shows the swapped connections depicted in fig6 ( c ). in the configuration of fig7 ( b ), variable capacitor c 1a is coupled to input c , variable capacitor c 2a is coupled to input d , variable capacitor c 1b is coupled to input a , variable capacitor c 2b is coupled to an input b , variable capacitors c 1a and c 2a share a common node that is coupled to output f , and variable capacitors c 1b and c 2b share a common node that is coupled to an output e . note that in the configurations of fig7 ( a ) and 7 ( b ), the pairs of exchanged terminals belong to variable capacitors , which are nominally identical ( i . e . c 1a = c 1b and c 2a = c 2b ). if the transducer is connected to the readout circuit with its terminals configured in the way shown in fig7 ( b ), instead of fig7 ( a ), the resulting system will be substantially electrically identical to the system in fig4 and will have the same transfer function . the important difference , however , is that the voltage waveform across a particular transducer capacitor ( c 1a , c 1b , c 2a , c 2b ) in the configuration of fig7 ( a ) has the opposite polarity from the voltage waveform across the same transducer capacitor in the configuration of fig7 ( b ). in order to obtain zero - average voltage waveforms across the transducer capacitors , the readout circuit of fig4 can be redesigned so that it periodically switches between the transducer configurations of fig7 ( a ) and fig7 ( b ). fig8 shows an exemplary embodiment of a differential self - balancing bridge that can provide substantially zero average voltage across the transducer capacitors . the circuit of fig8 is like the circuit of fig4 except that chopping switches have been added that swap the input and output terminals of the transducer cores c a and c b . when the chopping clock φ ch is in the high state then the transducer terminals are in the configuration shown in fig7 ( a ), and when the chopping clock is in the low state then the transducer terminals are swapped to the configuration shown in fig7 ( b ). thus , the voltage across a particular transducer capacitor has both positive and negative polarity that switches at the chopping clock frequency which can create substantially zero average voltage on each of the transducer capacitors . by periodically swapping the terminals , for example every other cycle , the transducer capacitors will each experience positive and negative voltages with substantially zero average voltage . fig9 shows an exemplary clocking diagram for the circuit of fig8 in which the frequency of the chopping clock φ ch ( switching or swapping the transducer terminals ) is half of the nominal sampling frequency of the main clock . the main clock switches between a charge phase φ 1 in which charge is gathered by the capacitors and a discharge phase φ 2 in which charge is discharged by the capacitors through the integrator 412 other switching frequencies can also be used that will create substantially zero average voltage on the transducer capacitors . fig1 shows the voltage waveforms across the transducer capacitors of fig8 when using the clocking diagram of fig9 . when the chopping clock φ ch is in the high state then the transducer terminals are connected as shown in fig7 ( a ) and the voltages across the transducer capacitors c 1a , c 1b , c 2a and c 2b are the same as shown in fig5 , namely v c1a and v c2b have positive polarity and v c1b and v c2a have negative polarity . then when the chopping clock φ ch switches to the low state , the transducer terminals are swapped as shown in fig7 ( b ). this swaps the transducer core terminals so that the voltages across capacitors c 1a and c 1b are swapped , and the voltages across capacitors c 2a and c 2b are swapped . it is apparent from fig1 that the average voltage across each of the capacitors c 1a , c 1b , c 2a and c 2b is now zero . this is beneficial in avoiding surface charge build - up on the capacitor terminals which avoids drift in charge . fig1 a and 11b illustrate an exemplary embodiment of a pseudo - differential bridge that alternates transducer cores and outputs based on a chopping clock to alternate polarity on the capacitors which reduces charge build - up and bias . fig1 a shows the system during a low chop state and fig1 b shows the system during a high chop state . the chopping switches are not shown for simplicity . only one transducer core , c a or c b , is receives the fed back output signals during any particular chopping clock phase , and the other transducer core is put in a dummy state . in the low chop phase , fig1 a , core c a receives the feedback output signals and core c b is in a dummy state just receiving the reference signal . in this state , variable capacitor c 1a receives feedback signal v s − v 0 , variable capacitor c 2a receives feedback signal − v s − v 0 , variable capacitor c 1b receives the positive reference voltage v s and variable capacitor c 2b receives the negative reference voltage − v s . the signal input from core c a is input to the inverting input of the integrator and the dummy input from core c b is input to the non - inverting input of the integrator . in the high chop phase , fig1 b core c b receives the feedback output signals and core c a is in a dummy state receiving the reference signal . in this state , variable capacitor c 1b receives feedback signal − v s + v 0 , variable capacitor c 2b receives feedback signal v s + v 0 , variable capacitor c 1a receives the negative reference voltage − v s and variable capacitor c 2a receives the positive reference voltage v s . the signal input from core c b is input to the non - inverting input of the integrator and the dummy input from core c a is input to the inverting input of the integrator . note that as the chopping clock is switched between the high and low phases , the voltage on each of the variable capacitors changes polarity . in the low state , variable capacitors c 1a and c 1b have a positive voltage and variable capacitors c 2a and c 2b have a negative voltage . while in the high state , variable capacitors c 2a and c 2b have a positive voltage and variable capacitors c 1a and c 1b have a negative voltage . thus , charge build - up and bias is reduced due to the change in polarity , even though the average voltage is not zero . the sensor core signal is also switched between the inverting and non - inverting inputs of the integrator during the chopping clock phase changes which provides a pseudo - differential effect . while this invention has been described as having an exemplary design , the present invention may be further modified within the spirit and scope of this disclosure . this application is therefore intended to cover any variations , uses , or adaptations of the invention using its general principles .