preferred embodiments of the present invention will now be described in detail . in the present example , a wafer was held on a wafer stage of a magnetically - enhanced microwave plasma etcher , using a single electrode electrostatic chuck , and an etching mask for sram bit line processing was formed by a three - layer resist process . then , residual charge of the single electrode electrostatic chuck was removed . first , a process sequence of the present embodiment will now be described with reference to fig2 a to 2d . in fig2 a , a wafer 4 is set on a single electrode electrostatic chuck 1 on a wafer stage 5 in a processing chamber , not shown , of a magnetically - enhanced microwave plasma etcher , and an underlying resist layer ( 30 in fig3 a ) on the wafer 5 is etched using an o 2 plasma formed through electron cyclotron resonance ( ecr ) discharge . the single electrode electrostatic chuck 1 has a constitution in which a single internal electrode 3 is buried in an insulation member 2 . a dc power source 9 capable of applying a positive dc voltage and a dc power source 10 capable of applying a negative dc voltage are connected , in parallel to each other , to the internal electrode 3 via a high frequency cutting filter 7 comprised of a coil and via a changeover switch 8 . these dc power sources 9 and 10 are commonly grounded . in fig2 a , as the dc power source 10 is connected , the internal electrode 3 is negatively charged . consequently , a positive charge is induced to the surface of the insulation member 2 while a negative charge is induced to the surface of the wafer 4 . the surface of the wafer 4 is negatively charged because of the negative self - bias of the wafer 4 due to the ecr discharge . the wafer 4 is adsorbed and held on the single electrode electrostatic chuck 1 by a coulomb force between the negative charge of the wafer itself and the positive charge of the surface of the insulation member 2 . a facing ground is taken through a chamber wall , not shown , via the o 2 plasma . on the other hand , a cooling pipe 6 is buried in the wafer stage 5 , so that the wafer 4 is cooled to a predetermined temperature by circulating an appropriate coolant in the cooling pipe 6 . also , an rf power source 13 is connected to the wafer stage 5 via a switch 11 and a blocking capacitor 12 for cutting off dc components . during the etching , the switch 11 is turned on to apply an rf bias , thus producing a predetermined incident ion energy . after the etching of the underlying resist layer , the supply of a microwave is stopped so as to suspend the ecr discharge , and the switch 11 is turned off not to apply the rf bias , as shown in fig2 b . thus , o 2 is exhausted once . then , a he gas is introduced into a processing chamber and the microwave is re - supplied , thus forming an ecr plasma , as shown in fig2 c . it is possible to effectively reduce the residual charge on the surfaces of the internal electrode 3 , the insulation member 2 and the wafer 4 , by connecting the changeover switch 8 temporarily to the side of the dc power source 9 so as to turn the dc voltage applied to the internal electrode 3 to the opposite polarity . in addition , the changeover switch 8 is turned off and the ecr discharge of the he gas is continued , as shown in fig2 d . the ecr plasma causes the residual charge to be eliminated , and causes the inside of the processing chamber to be cleaned . meanwhile , the above - described process is one example of the process sequence , allowing various modifications thereof . for example , though the polarity of the dc voltage applied to the internal electrode 3 is changed in such an order that negative → positive → none in the above example , it may be that positive → negative → none . also , in the o 2 exhaust process shown in fig2 b , a he gas may be introduced at the time of the exhaust , so as to substitute for o 2 . a process example in which the above - described process sequence is applied to the etching of the underlying resist layer in actual sram bit line processing will now be described with reference to fig3 a and 3b . fig3 a is a schematic cross - sectional view showing an arrangement of a wafer before being etched . that is , a gate electrode 25 made of a first - layer polycide film is formed via an sio 2 gate oxide film on a silicon substrate 21 in which an element separation region 22 of shallow trench type is formed in advance . the gate electrode 25 is formed by a polysilicon layer 23 on the lower layer and a tungsten silicide ( wsi x ) layer 24 on the upper layer being stacked thereon . in addition , the entire surface of the wafer is covered with an sio 2 interlayer insulation film 26 formed by stacking sio 2 by cvd , and a second - layer polycide film 29 is formed thereon . the second - layer polycide film 29 , which is formed by a polysilicon layer 27 on the lower layer and a wsi x layer 28 on the upper layer being stacked thereon , is a portion constituting the sram bit line . further , in order to pattern the second - layer polycide film 29 , a lower resist layer 30 is first formed with a thickness to substantially absorb the surface step of the wafer for flattening , and then a sog middle layer pattern 31 and an upper resist pattern 32 are sequentially formed thereon . the lower resist layer 30 is formed of , for example , a novolak positive type photoresist ( trade name ofpr - 800 , made by tokyo oka kogyo ). the thickness of the lower resist layer 30 is approximately 1 . 0 μm in a thick portion . the sog middle layer pattern 31 is formed by forming a coating film with a thickness of about 0 . 15 μm using , for example , sog ( trade name ocd - type 2 , made by tokyo oka kogyo ), and then carrying out reactive ion etching ( rie ) with the upper resist pattern 32 as a mask , as later described . the etching condition in this rie is : chf 3 flow rate of 75 sccm ; o 2 flow rate of 8 sccm ; gas pressure of 6 . 5 pa ; and rf power of 1350 w ( 13 . 56 mhz ), using a hexode type rie device . the upper resist pattern 32 is formed by forming a coating film with a thickness of about 0 . 5 μm using , for example , a chemical amplification negative type three - component resist ( trade name sal - 601 , made by shipley co . ), and then patterning by using a krf excimer laser stepper . then , for etching the under resist layer 30 , the wafer was set on the single electrode electrostatic chuck 1 in the processing chamber of the magnetically - enhanced microwave plasma etcher , and an o 2 gas was introduced in the processing chamber . in the cooling pipe 6 provided within the wafer stage 5 , an alcohol based coolant was supplied and circulated from a chiller , not shown , provided outside the device . ______________________________________o . sub . 2 flow rate 10 sccmgas pressure 0 . 27 pamicrowave power 900 w ( 2 . 45 ghz ) rf bias power 100 w ( 800 khz ) wafer temperature - 50 ° c . dc voltage to internal electrode - 600 v______________________________________ in this etching process , anisotropic etching proceeded wish a mechanism that the burning reaction of the upper resist pattern 32 and the lower resist layer 30 due to o * is assisted by the incident ion energy of o x + . the upper resist pattern 32 was eliminated in the process , and then the middle layer pattern 31 functioned singly as the etching mask . as a result , a lower resist pattern 30a having a highly anisotropic shape was formed , as shown in fig3 b . after this etching , the o 2 gas was exhausted as shown in fig2 b . the exhaust time was set to 10 minutes , and the ultimate vacuum was set to 1 × 10 - 3 pa . since the switch 11 was turned off so as not to apply rf bias power , the sputtering of the underlying second - layer polycide film 29 due to unnecessary ions was not carried out . then , the residual charge was removed , for example , under the following conditions . ______________________________________he flow rate 50 sccmgas pressure 0 . 67 pamicrowave power 1200 w ( 2 . 45 ghz ) rf bias power 0 wwafer temperature - 50 ° c . discharging time 15 secondsdc voltage to internal + 100 v ( for first 0 . 2 seconds ) electrode 0 v ( for remaining 14 . 8 seconds ) ______________________________________ in this plasma processing , a dc voltage of the opposite polarity was applied to the internal electrode 3 for the first 0 . 2 seconds of the total processing time of 15 seconds , as shown in fig2 c , while the dc voltage was not applied for the remaining time , as shown in fig2 d . in this manner , the residual charge was removed almost perfectly . meanwhile , the total processing time is set to have a certain margin , and therefore may be shortened depending on conditions . in addition , since few o * existed in the plasma , the anisotropic shape of the lower resist pattern 30a achieved by the preceding etching was not deteriorated , even though the rf bias power was not applied . meanwhile , the above - mentioned process is different from the conventional process described with reference to fig1 a to 1c , in that the wafer 4 remains to be set on the wafer stage 5 until the removal of the residual charge is finished . this is highly advantageous for preventing the wafer crack in separating the wafer 4 from the wafer stage 5 , and for preventing plasma irradiation damages affecting the surfaces of the wafer stage 5 and the single electrode electrostatic chuck 1 . in the present comparative example , the o 2 exhaust process described above in example 1 was omitted , and the residual charge removal was carried out shortly after the etching of the lower resist layer 30 . that is , the state shown in fig2 b is omitted , and o * co - exists with he * in the plasma in the states of fig2 c and 2d . when the residual charge removal was carried out in accordance with such a process sequence , the anisotropic shape of the lower resist pattern 30a shown in fig3 b was lost , and a lower resist pattern 30c having an undercut was produced , as shown in fig4 . this is because the residual o * in the gaseous phase isotropically etched the lower resist pattern 30a from its sidewall surfaces at the time when the application of the rf &# 39 ; bias power was stopped . in the present example , gas compositions different from that of example 1 was employed for the etching of the lower resist layer 30 and the residual charge removal . that is , an o 2 / cl 2 mixed gas was used for the etching of the lower resist layer 30 , while an n 2 gas was used for the residual charge removal . an example of etching conditions for the lower resist layer 30 is shown as follows . ______________________________________o . sub . 2 flow rate 8 sccmcl . sub . 2 flow rate 2 sccmgas pressure 0 . 27 pamicrowave power 900 w ( 2 . 45 ghz ) rf bias power 100 w ( 800 khz ) wafer temperature - 30 ° c . ______________________________________ in these etching conditions , cl 2 was added to the etching gas composition , in expectation of sidewall protection effects due to an etching reaction product , ccl x polymer , which has a low vapor pressure when cooled at a low temperature . actually , despite the higher wafer temperature than in example 1 , the lower resist pattern 30a having a highly anisotropic shape was able be formed . then , o 2 and cl 2 were exhausted . the exhaust time was 10 seconds and the ultimate vacuum was 5 × 10 - 3 pa . further , the residual charge was removed , for example , under the following conditions . ______________________________________n . sub . 2 flow rate 50 sccmgas pressure 0 . 67 pamicrowave power 1200 w ( 2 . 45 ghz ) rf bias power 0 wwafer temperature - 30 ° c . discharging time 15 secondsdc voltage to internal + 100 v ( for first 0 . 2 seconds ) electrode 0 v ( for remaining 14 . 8 seconds ) ______________________________________ in the present example , the sidewall protection effects due to ccl x polymer were utilized in the previous etching process . however , sidewall protection films , not shown , formed in this process do not have a uniform thickness to be adhered to the pattern sidewalls . accordingly , if the residual charge removal is carried out with the exhaust process being omitted , isotropic etching proceeds from the portion having a thin sidewall protection film , causing the cross - sectional shape of the lower resist pattern 30a to be deteriorated in a complex manner . however , according to the present example , the residual charge was able to be removed , while maintaining the highly anisotropic shape of the lower resist pattern 30a . in the present example , o 2 used for etching was exhausted by substituting he for o 2 . first , the lower resist layer 30 was etched using o 2 under the same conditions as in example 1 , and exhaust / substitution was carried out , for example , under the following conditions . ______________________________________he flow rate 50 sccmgas pressure 0 . 67 pamicrowave power 0 wrf bias power 0 wwafer temperature - 50 ° c . exhaust time 2 seconds______________________________________ in the present example , the exhaust time was able to be shortened to 2 seconds by simultaneously carrying out exhaust of o 2 and substitution by he , and therefore , a reduction in throughput was able to be limited to the minimum . then , electric discharge was carried out , for example , under the following conditions . thus , the residual charge was removed almost perfectly , and the inside of the processing chamber was cleaned . in the present example , a depositional ch 2 f 2 gas was used in the process of residual charge removal , for the purpose of higher shape control . this process is described with reference to fig5 a and 5b . first , the etching of the lower resist layer 30 using o 2 and exhaust of o 2 were carried out under the same conditions as in example 1 . up to this stage , however , a lower resist patter 30b having a slight undercut was formed , as shown in fig5 a , depending on the timing of the turning off of the switch 11 and the exhaust . this undercut was generated in the form of retreating inside about 0 . 02 μm from an edge of the middle layer pattern 31 . then , the residual charge removal was carried out , for example , under the following conditions , and the cross - sectional shape of the lower resist pattern 3ob was corrected . ______________________________________ch . sub . 2 f . sub . 2 flow rate 10 sccmgas pressure 0 . 67 pamicrowave power 1200 w ( 2 . 45 ghz ) rf bias power 0 wwafer temperature - 50 ° c . exhaust time 10 seconds______________________________________ a cf x polymer 32 formed in the plasma by the electric discharge was deposited with a thickness of about 0 . 02 to 0 . 03 μm on the entire surface of the wafer under the condition of non - bias application . the deposition thickness is sufficient for compensating the undercut and flattening the pattern sidewall surface . thus , the cross - sectional shape of the lower resist pattern was corrected as shown in fig5 b . meanwhile , the cf x polymer 32 deposited on the exposed surface of the second - layer polycide film 29 has the above - mentioned small thickness , and therefore can easily be removed before the second - layer polycide film 29 is etched so as to carry out bit line processing in a latter process . in the present example , after just etching was finished in polycide gate electrode processing , exhaust / substitution of an etching gas used for the just etching was carried out by dividing the process thereof into several times , that is , by cycle purge . in this manner , exhaust / substitution efficiency was improved . the etching process at this time is now described with reference to fig6 a to 6d . a wafer used as an etching sample in the present example is constituted by a polycide film 45 stacked on a single crystal silicon substrate 41 via a thin gate oxide film 42 , with a resist pattern 46 being formed in a predetermined shape on the polycide film 45 , as shown in fig6 a . the polycide film 45 is constituted by stacking , from the bottom , a polysilicon layer 43 having a thickness of about 100 mm and a wsi x layer 44 having a thickness of about 100 mm . the wafer was set on the rf - bias magnetically - enhanced microwave plasma etcher , and the polycide film 45 was just - etched , for example , under the following conditions . ______________________________________sf . sub . 6 flow rate 30 sccmhbr flow rate 20 sccmgas pressure 1 . 3 pamicrowave power 900 w ( 2 . 45 ghz ) rf bias power 200 w ( 400 khz ) wafer temperature - 40 ° c . ______________________________________ the just etching was finished shortly before the underlying gate oxide film 42 was exposed , as shown in fig6 b . in this process , high - rate etching due to f * and high selective etching due to br * proceeded with assistance of incident energies of ions such as sf x + and br + . also , since the wafer was cooled to a low temperature , sibr x having a low vapor pressure was deposited on the pattern sidewalls , forming sidewall protection films , not shown . meanwhile , the pattern formed by etching is denoted by reference numbers of the original material layers with an additional character a , in fig6 b . in this manner , the etching gas has a gas composition capable of conducting high - selective processing . however , if over etching is directly carried out without changing any condition , underlying selectivity and shape anisotropy , particularly shape anisotropy of a lower layer polysilicon pattern 43a , may be deteriorated by the residual f *. thus , the cycle purge was carried out , for example , under the following conditions . ______________________________________exhaust process : ultimate vacuum 10 . sup .- 2 pa or lowerhe substitution process : flow rate 100 sccmgas pressure 3 pasubstitution time 10 seconds______________________________________ the exhaust process and the he substitution process were alternately repeated three times , with the total processing time of approximately 1 minute . thus , the only chemical species present in the gaseous phase was substantially he , as shown in fig6 c . after that , the polycide film 45 was over - etched , for example , under the following conditions . ______________________________________hbr flow rate 50 sccmgas pressure 1 . 3 pamicrowave power 900 w ( 2 . 45 ghz ) rf bias power 15 w ( 400 khz ) wafer temperature - 40 ° c . ______________________________________ in this process , as f * was removed almost perfectly from the gaseous phase , a gate electrode 45a having a highly anisotropic shape was formed , as shown in fig6 d . in addition , the main etchant in this process was br *, and the rf bias power was reduced . therefore , a high selective ratio of not lower than 100 was achieved for the underlying sio 2 interlayer insulation film 26 . in the present example , electric discharge of he was carried out as a modification of the cycle purge in example 5 . first , the polycide film 45 was just - etched in a similar manner to example 5 . then , the cycle purge was carried out , for example , under the following conditions . ______________________________________exhaust process : ultimate vacuum 10 . sup .- 2 pa or lowerhe substitution process : flow rate 100 sccmgas pressure 2 pamicrowave power 1200 w ( 2 . 45 ghz ) wafer temperature - 40 ° c . discharging time 10 seconds______________________________________ the exhaust process and the he substitution process wire alternately repeated three times , with the total processing time of approximately 1 minute . thus , the only chemical species present in the gaseous phase was substantially he *, as shown in fig6 c . the degree to which the exhaust and the substitution proceeded was confirmed in situ by monitoring an emission spectrum of f *. the emission spectrum is shown in fig7 . the emission peaks due to f * are observed at 634 . 8 mm , 760 . 7 mm and 775 . 5 mm . the cycle purge was finished at the time when these peaks were extinguished , or when the peak height , that is , the emission intensity was equal to a background value . after that , over etching was carried out in a similar manner to example 5 , thus carrying out high - selective , high - anisotropic processing . the present invention has been described on the basis of the above six examples . however , the present invention is not limited to these examples . for example , the process to which the present invention is applicable is not limited to the etching of the lower resist layer or the polycide film , but can be any other process in which selectivity and anisotropy may be deteriorated by a residual gas used in a preceding process . in addition , it is a matter of course that wafer constitution , etching conditions , exhaust conditions , kinds of devices to be used , and composition of etching gases and inactive gases can be changed suitably .