in the following , an embodiment of the present invention is described by reference to fig1 and fig3 to fig6 . fig3 shows perspective views of the chip 1 and chip 2 . in the chip 1 , the multi - layered cu wires 10 and bonding bumps 13 are formed on a si substrate 12 . in the chip 2 , the multi - layered cu wires 10 , conductive paths 14 which extend through the substrate , the bonding bumps 13 , and the groove 6 which straddles the ferrite core are formed . the bonding bumps are formed from low - melting solders and melt at about 150 c . in heat treatment . the chips are disposed as shown in fig1 and bonded to each other by melting the bonding bumps . external electrical connections are provided through bonding pads 7 at an end of the chip 1 and current is supplied through wire - bonded wires 8 . fig4 shows processes for manufacturing the chip 1 . first , cu wires 15 are formed on the si substrate 12 by plating ( fig4 ( a )). then an inter - layer insulating film 17 with through holes 16 is formed by using a photoresist and then second - layered cu wires 15 &# 39 ; are formed by plating ( fig4 ( b )). an inter - layer insulating film ( photoresist ) 17 &# 39 ; with through holes 16 &# 39 ; and third - layered cu wires 15 &# 34 ; are formed ( fig4 ( c )). finally , a protective film 18 made up of al 2 o 3 is formed , through holes 16 &# 34 ; are made though the protective film 18 , and then the bonding bumps 13 are formed by evaporation of low - melting solders in mask evaporation ( fig4 ( d )). according to the above processes , the multi - layered cu wires are formed . incidentally , the size of the chip is approximately 0 . 3 mm × 1 . 5 mm and about 5000 chips can be obtained from a three - inch wafer . fig5 shows processes for manufacturing the chip 2 . in the chip 2 , it is necessary to form conductive paths through a si substrate . to do this , first a metallic film ( ni ) 20 and an insulating resins film 21 , which can be a plating base , are laminated on one surface of the si substrate 12 and a mask film ( ni ) 22 , which can be a mask for etching , is coated on the other surface of the si substrate 12 . in the mask film 22 , openings for holes made through the substrate are formed by a usual photoetching ( chemical etching ) method and reactive ion etching is applied to si . a gas used for etching is chf 3 which erodes the ni film very little . holes 23 through the substrate can be thus made at sufficient process allowance ( fig5 ( a )). then the metallic film 20 is used as a plating base and ni plating is applied to form conductive paths 14 through the si substrate . then low - melting solders are evaporated by mask evaporation to form the bonding bumps 13 ( fig5 ( b )). then , as shown in fig5 ( c ), on the opposite side of the bonding bumps the multi - layered cu wires 10 are formed in the same manner as in manufacturing the chip 1 . finally , on the side of the bonding bumps the groove 6 is formed by mechanical processing ( fig5 ( d )). fig6 shows another method for forming conductive paths through the si substrate . a si substrate 24 used is one with ( 110 ) plane . on the surface of the substrate , a sio 2 film 25 of 200 nm thickness is formed , then openings 26 for holes which penetrate the substrate are formed by usual photoetching ( fig6 ( a )). then the sio 2 film is masked and etching using a 40 % koh solution at 40 c . is applied to the si substrate . in this case , ( 111 ) plane is taken on the side surfaces of holes and holes 23 , which penetrate the substrate , are formed with no side etching ( fig6 ( b )). then the surface of the si substrate is oxidized by a thermal oxidation method to form a sio 2 film 27 of 100 nm thickness ( fig6 ( c )). after the above processing , a metallic leaf 28 and an insulating film 21 are formed on the bottom surface of the si substrate . then the metallic leaf 28 is used as a plating base and cu plating is applied to form the conductive paths 14 which penetrate the si substrate . then low - melting solders are evaporated by mask evaporation to form the bonding bumps 13 ( fig6 ( d )). processes following the formation of the bonding bumps are the same as in fig5 . in the embodiment , the metallic leaf is used as a plating base . however , it will be recognized that a metallic film coated by evaporation or sputtering can be used as the plating base . in the embodiment , the holes made in the si substrate are filled up by plating . however , it will be appreciated that they can be filled up by capillary action . that is , the si substrate with the holes , which penetrate it , is submerged in melted solders to fill up the holes . further , in the embodiment , the si substrates are used as substrates for the chip 1 and chip 2 by consideration on evenness of the surface of the substrate and workableness in etching . however , it will be appreciated that a resins substrate may be used if those conditions are satisfied . that is , a resins substrate , for example , an epoxy resins substrate may be used instead of the si substrate shown in fig5 and etched by reactive ion etching using an oxygen gas . since the types of the selective removal of unwanted material exceeds 100 between the epoxy resins and the ni film used as a masked material in etching , holes which penetrate the resins substrate can be easily formed . in the following , another embodiment according to the present invention is described by reference to fig7 . as shown in fig7 conductive paths straddling the ferrite core 4 are formed from a chip 2 &# 39 ; with multi - layered cu wires . now , the chip 2 &# 39 ; has not conductive paths which penetrate a substrate , but only the multi - layered wires on its surface . chips are disposed as follows . first , a chip 1 is disposed so that its bottom faces the slider and the slender portion of its end is inserted in a winding window . then the bottom of the chip 1 is bonded to the side surface of the slider . then the chip 2 &# 39 ; is disposed so that it faces the chip 1 and alignment is applied to the bonding bumps of both chips . after alignment , the bonding bumps of both chips are melted by heat treatment at 150 c . the multi - layered wires are thus bonded and a coil encircling the magnetic core is formed . fig8 shows perspective views of chip 1 and chip 2 &# 39 ;. both chips with an insulating film 17 and cu wires 15 alternately laminated on a substrate 19 are formed in the same manner as in fig4 . on the surface of the chip 1 , bonding bumps 13 , which are low - melting solders , and bonding pads 7 are formed . a magnetic gap is provided below the ferrite core . fig9 shows still another embodiment of the present invention . in the figure , conductive paths straddling the ferrite core 4 are formed from a chip 2 &# 39 ; with multi - layered cu wires . however , the chip is at a position where it is turned by 90 to a slider differently from the previous embodiments . that is , the chip is disposed so that its surface on which the multi - layered wires are formed and the side surface of the slider intersect each other . in the embodiment , first the slender portion of a chip 1 is inserted in a winding window and the side surface of the chip is bonded to the side surface of the slider . then the chip 2 &# 39 ; is disposed so that its surface faces the surface of the chip 1 and alignment is applied to the bonding bumps of both chips . after alignment , their bonding bumps are melted by heat treatment at 150 c . then the side surface of the chip 2 &# 39 ; is bonded to the slider , thus joints between the chip and the slider become firm . in the above construction , a magnetic gap can be provided either above or below the ferrite core . in the following , yet another embodiment of the present invention is described by reference to fig1 . in the figure , a chip straddling the ferrite core 4 is formed from a flexible substrate and multi - layered cu wires and bonding bumps are formed on the substrate . as shown in the preceding embodiments , the chip 1 with the multi - layered cu wires formed on the si substrate is inserted in a winding window and bonded to the side surface of the slider . then the flexible substrate 29 is disposed so that it faces the chip 1 and the ferrite core 4 and the bonding bumps contact with each other , melt , and are bonded . fig1 shows a further embodiment of the present invention . a coil is formed only on a flexible substrate 29 . that is , the flexible substrate described in the embodiment 2 is inserted in a winding window 5 and circled around the ferrite core 4 . then bonding bumps 13 at both ends of the flexible substrate contact with each other and melt , thereby the coil is formed . fig1 shows still a further embodiment of the present invention . in the figure , conductive paths straddling the ferrite core 4 are formed by wire bonding . that is , the si chip 1 with multi - layered cu wires , already described is inserted in the winding window 5 and bonded to the side surface of the slider 3 . then bonding is applied to wires 8 so that bonding bumps 13 at both ends of the substrate are connected with each other . in the above embodiments , the magnetic head to which the laminated coil is applied , what is called monolithic - type head in which the slider itself is made of ferrite was described . another type of head for a hard disk is a composite - type head in which a magnetic core is implanted in a nonmagnetic slider . also in the composite - type head , the shapes of a winding window and the magnetic core are like those of the monolithic type and needless to say , the present invention can be applied also to the composite type head . the laminated coil formed as described above can be a significantly smaller size than a conventional coil of wound cu wire . the size of a ferrite core and a winding window can become significantly smaller , for example , decrease to one - half or less of that of a conventional core and winding window , thus high - frequency characteristic and head efficiency are improved . further , since the laminated coil is directly bonded to the slider and not heavy , a heavy load is not applied to the ferrite core and construction strong for an external shock can be implemented . further , since the laminated coil is formed by simply bonding two chips to each other , cost in coil winding can be significantly reduced .