[ 0021 ] fig3 is a block diagram of a bank control circuit in rambus dram comprising : n memory bank units 130 & lt ; n & gt ; for storing data ; n + 1 sense amp units 140 & lt ; n + 1 & gt ; disposed on upper and lower parts of each memory bank unit 130 & lt ; n & gt ; for sensing data in write and read operations ; n + 1 sense amp driver units 150 & lt ; n + 1 & gt ; for controlling operations of the sense amp unit 140 & lt ; n + 1 & gt ;; n main word line and sub word line driver units 160 & lt ; n & gt ; for driving word lines and sub word lines of the memory bank units 130 & lt ; n & gt ;; and n / 2 control units and address latch units 170 & lt ; n / 2 & gt ;, one being shared by two memory bank units 130 & lt ; n & gt ;, for receiving active signals , precharge signals and global address signals and for generating signals to control two sense amp driver units , two main word line and sub word line driver units and bit lines disposed in the two memory banks . according to the present invention , two memory bank units 130 & lt ; 0 : 1 & gt ; share one control unit and one address latch unit 170 & lt ; n & gt ; since two banks are not activated at the same time . first , the active signal and the precharge signal are generated as global signals and then each control unit and address latch unit 170 & lt ; n & gt ; check whether the received global address signal is the address signal of the two memory banks including them . therefore , one control unit and one address latch unit are selected by the received global address signal . and , the selected control unit and the address latch unit operate a memory bank corresponding to the received global address signal in active mode or precharge mode by the received active signal and the precharge signal . moreover , the selected control unit and address latch unit maintain word lines in the memory bank by latching the global address signal received in active mode although the external global address signals are changed . [ 0025 ] fig4 is a block diagram of bank a control circuit in rambus dram according to another embodiment of the present invention , comprising : n memory bank units 230 & lt ; n & gt ; for storing data ; a n + 1 sense amp unit 240 & lt ; n + 1 & gt ; disposed on upper and lower parts of each memory bank unit 230 & lt ; n & gt ;, for sensing data in write and read operations ; n + 1 sense amp driver units 250 & lt ; n + 1 & gt ; for controlling operations of the sense amp units 240 & lt ; n + 1 & gt ;; n / 2 main word line and sub word line driver units 160 & lt ; n & gt ;, one being shared by two memory bank units 230 & lt ; n & gt ;, for generating signals to drive word lines and sub word lines of the two memory bank units ; and a n / 2 control unit and an address latch unit 170 & lt ; n / 2 & gt ;, one being shared by two memory bank units 230 & lt ; n & gt ;, for receiving active signals , precharge signals and global address signals from outside and for generating signals to control two sense amp driver units , one main word line and sub word line driver unit and bit lines of the two memory banks . according to the present invention , two memory bank units 130 & lt ; 0 : 1 & gt ; share one control unit and address latch unit 170 & lt ; n & gt ; and one main word line and sub word line driver unit 260 & lt ; 0 & gt ; by the property that two banks are not activated at the same time . first , the active signal and the precharge signal are generated as global signals and then each control unit and address latch unit 170 & lt ; n & gt ; check whether the received global address signal is the address signal of the two memory banks including them . therefore , one control unit and address latch unit are selected by the received global address signal . and , the selected control unit and address latch unit operate a memory bank corresponding to the global address signal received in active mode or precharge mode by the received active signal and precharge signal . moreover , the selected control unit and address latch unit maintain word lines in the memory bank by latching the global address signal received in active mode to the inner address latch circuit although external global address signals are changed . here , main word lines and sub word lines are driven in one memory bank corresponding to the address signal by the main word line and sub word line driver unit 260 & lt ; n & gt ; receiving the global address signals latched by the control unit and address latch unit 270 & lt ; n & gt ;. as described above , according to the present invention , one control circuit and address latch circuit is shared by two banks , thereby reducing circuit area . although the preferred embodiments of the invention have been disclosed for illustrative purposes , those skilled in the art will appreciate that various modifications , additions and substitutions are possible , without departing from the scope and spirit of the invention as disclosed in the accompanying claims .