fig1 is a simplified schematic diagram of an exemplary integrating 3 - bit dac architecture 100 . in some implementations , the architecture 100 can include an analog comparator 102 , current sources 104 a - 104 c ( e . g ., linear current sources ), buffer 106 , state machine 108 , digital counter 110 , switches s 1 - s 12 and capacitors c 1 - c 3 . the architecture 100 can include multiple parallel circuit branches , each branch can include a current source and a capacitor . in the architecture shown , a first branch includes the current source 104 a and the capacitor c 1 , a second branch includes the current source 104 b and the capacitor c 2 and a third branch includes the current source 104 c and capacitor c 3 . the architecture 100 can have two or more parallel branches , where at least two branches can be configured through switches to provide a continuous voltage output . in each branch switches are operable to connect and disconnect the current source to the capacitor and to short the capacitor to ground to remove charge on the capacitor . the current sources 104 a - 104 c can be selected to be closely matched . in some implementations , an integrator can be used as a source , or capacitors and large resistors as pull - up sources , rather than current sources 104 a - 104 c . the state machine 108 can be implemented using a programmable logic device , a programmable logic controller , logic gates and flip flops or relays . in some implementations , a register can store state variables , a first block of combinational logic can determine the state transition , and a second block of combinational logic can determine the output of the state machine 108 . the state machine 108 , together with the digital counter 110 , can be used to close and open the switches s 1 - s 12 to affect various stages of circuit operation , as described in reference to fig2 - 7 . the digital counter 110 can be implemented using register - type circuits such as a flip - flop ( e . g ., up - down counter ), or any other known digital counter design . switches s 1 - s 12 can be semiconductor switches ( e . g ., mosfet transistors ). the control inputs to the switches s 1 - s 12 can be determined by the state machine 108 . the voltage reference connected to the analog comparator 102 can be any suitable voltage reference ( e . g ., zener reference , bandgap reference ). the buffer 106 can be an operational amplifier configured for unity gain . for example , a unity gain buffer amplifier may be constructed by applying a full series negative feedback to an op - amp by connecting its output to its inverting input , and connecting the signal source to the non - inverting input . other known buffer designs also can be used . the analog comparator 102 can be a standard op - amp operating in open loop configuration ( without negative feedback ) or a dedicated analog comparator integrated circuit chip ( e . g ., atmel avr1302 analog comparator ). fig2 is a schematic diagram of a portion of the exemplary integrating dac architecture of fig1 illustrating capacitor charge removal and reset during a self - calibration stage . the portion includes the analog comparator 102 , the first branch of architecture 100 ( which includes current source 104 a and capacitor c 1 ), buffer 106 and switches s 1 , s 4 , s 7 , and s 10 . the analog comparator 102 is connected to a voltage reference . the calibration stage can start by opening switches 51 , s 4 and s 7 and closing switch s 10 . opening switch s 1 disconnects the analog comparator 102 from the first branch . opening switch s 4 disconnects the current source 104 a from the capacitor c 1 . opening switch s 7 disconnects the buffer 106 from the branch . closing switch s 10 shorts the capacitor c 1 to ground , thus removing any charge stored over the capacitor c 1 . fig3 is a schematic diagram of a portion of the exemplary integrating dac architecture of fig2 illustrating the establishing of a reference during the self - calibration stage . the calibration stage continues establishes a reference by opening switches s 10 and s 7 and closing switches s 1 , s 4 and s 10 . opening switch s 10 disconnects the capacitor from ground so that it can be charged by the currents source 104 a . opening switch s 7 disconnects the buffer 106 from the branch . closing switch s 1 connects the analog comparator 102 to the capacitor c 1 . closing switch s 4 connects the current source 104 a to the capacitor c 1 . in this configuration , the capacitor c 1 is connected to the current source 104 a and the capacitor c 1 is charged while the digital counter 110 counts cycles until the voltage over the capacitor c 1 is about equal to the reference voltage ( or differs by a threshold amount ), at which point the analog comparator 102 triggers and the digital count is stored ( e . g ., stored in a register ). a mathematical relationship can be established between the voltage over the capacitor and a digital value expressed as where v count is the voltage change from one cycle , v reference is the analog reference voltage and digital count is the number of cycles counted by the digital counter 110 . v reference can also be described as the voltage stored over the capacitor plus the offset error in the analog comparator 102 . the digital count can be normalized to a standard resolution using the following expression digital count ⁢ ⁢ _ ⁢ ⁢ lsb = digital count 2 n , [ 2 ] where digital count lsb is the number of cycles per lsb step and n is the desired resolution and is a positive integer . expression [ 2 ] provides the required number of cycles for a voltage charge corresponding to 1 lsb step . fig4 is a schematic diagram of a portion of the exemplary integrating dac architecture of fig2 illustrating charge removal and reset during a conversion stage . in the start of the conversion stage , switch s 10 is closed and switches s 1 , s 4 and s 7 are opened . switch s 10 shorts the capacitor c 1 to ground to remove any charge before the current source 104 a is connected to the capacitor c 1 and starts charging the capacitor c 1 . fig5 is a schematic diagram of a portion of the exemplary integrating dac architecture of fig1 illustrating setting a target analog voltage during a conversion stage . the conversion stage continues by opening switches s 1 , s 10 and s 7 and closing switch s 4 to allow the current source 104 a to charge the capacitor c 1 . the capacitor c 1 is charged until a count by the digital counter 110 is equal to digital output — count · digital count — lsb · v reference described in expression [ 1 ] can also be described as the voltage stored over the capacitor c 1 . with this observation , expression [ 1 ] can lead to the following new expression : where v out is the output voltage after digital output — count cycles . based on expression [ 3 ], the required cycles to reach the desired output voltage can be calculated . fig6 is a schematic diagram of a portion of the exemplary integrating dac architecture of fig2 illustrating setting an output voltage . to set the output voltage , switches s 1 , s 4 and s 10 are opened and switch s 7 ( connected to the buffer 106 ) is closed . after charging the capacitor c 1 to a target analog voltage , the charged capacitor c 1 is connected to the unity output buffer 106 , resulting in the voltage stored over the capacitor c 1 being transferred to the buffer 106 where it is held at the output of the dac . fig7 is a schematic diagram of an exemplary integrating dac architecture illustrating multiple branches in different stages of operation to provide continuous output . more particularly , fig7 illustrates how two or more branches in architecture 100 can be in different stages of operation at the same time to ensure continuous output from the dac . since the branches are calibrated and operated separately , mismatch between the circuit elements in different branches do not affect operation . in the present configuration , switches s 1 , s 4 , s 5 and s 9 are closed and switches s 2 , s 3 , s 6 , s 7 , s 8 , s 10 , s 11 and s 12 are opened . this configuration results in the first branch operating in the calibration stage , the second branch operating in the conversion stage , and the third branch setting the output voltage of the dac . table i below illustrates the states of switches s 1 - s 12 for the various stages of operation for the 3 branches of the architecture 100 shown in fig7 . fig8 is a flow diagram of an exemplary calibration process 800 using an integrating dac architecture . the process 800 can be operated independently in multiple branches of the integrating dac architecture 100 . in some implementations , the process 800 begins by removing capacitor voltage and resetting a digital counter ( 802 ). for example , the capacitor voltage can be removed by shorting the capacitor to ground , as described in reference to fig2 . the current source and an analog comparator are connected to the capacitor ( 804 ). the digital counter is started ( 806 ). after starting the digital counter ( 806 ), the current source charges the capacitor ( 808 ) until the voltage over the capacitor is about equal to a reference voltage or differs by a threshold amount . for example , the reference voltage and the capacitor can be input into the analog comparator that is configured to trigger when the capacitor voltage is about equal to the reference voltage . the trigger can be used to stop the digital counter . the count of the digital counter is the number of clock cycles completed when the comparator triggers . when the analog comparator triggers ( 810 ), a mathematical relationship is established between the capacitor voltage at the time of the trigger and a digital value based on the number of cycles counted by the digital counter ( 812 ). fig9 is a flow diagram of an exemplary conversion process 900 using an integrating dac architecture . in some implementations , the process 900 begins by disconnecting the current source and analog comparator from the capacitor ( 902 ). the voltage over the capacitor is removed ( 904 ). the current source is re - connected to the capacitor ( 906 ). the digital counter is started ( 908 ). the current source charges the capacitor ( 910 ). the charging continues until a target analog voltage is reached ( 912 ). the output voltage of the dac is set to the capacitor voltage ( 914 ). for example , a unity gain buffer can be connected to the capacitor to hold the analog voltage at the output of the dac , as described in reference to fig6 . while this document contains many specific implementation details , these should not be construed as limitations on the scope what may be claimed , but rather as descriptions of features that may be specific to particular embodiments . certain features that are described in this specification in the context of separate embodiments can also be implemented in combination in a single embodiment . conversely , various features that are described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable sub combination . moreover , although features may be described above as acting in certain combinations and even initially claimed as such , one or more features from a claimed combination can in some cases be excised from the combination , and the claimed combination may be directed to a sub combination or variation of a sub combination .