fig1 is a block diagram for explaining a ram interface according to a preferred embodiment of the present invention . a semiconductor memory device 200 of fig1 is obtained by modifying the semiconductor memory device 100 of fig1 in which the logic ic 10 and the dram memory ic 11 are formed independently of each other . in semiconductor memory device 200 , the dram memory ic 11 is replaced with an sram , and a memory ic ( sram ) 60 is controlled by the logic ic 10 which is designed on the premise that the memory ic 11 is a dram . the semiconductor memory device 200 comprises a ram interface 30 between the logic ic 10 and the memory ic 60 . now , a structure of the ram interface 30 will be described . the ram interface 30 is comprised of a bi - directional switch circuit 31 , a row - column address dividing circuit 32 and an sram control signal generation circuit 33 . under the control of the bi - directional switch circuit 31 , inputting to and outputting from a data bus are performed in accordance with writing or reading of data . the bi - directional switch circuit 31 is controlled by the we signal received from the logic ic 10 . the row - column address dividing circuit 32 divides a serial address into a row address and a column address using the ras signal and the cas signal , respectively , and supplies the row address and the column address to the sram . the row - column address dividing circuit 32 is governed by the ras signal from the logic ic 10 . receiving a dram control signal from the logic ic 10 , the sram control signal generation circuit 33 modifies the dram control signal into an sram control signal which is necessary to control the sram . the structures of the respective circuits will be described in the following . fig2 shows an example of a structure of the bi - directional switch circuit 31 . in fig2 tri - state buffers a1 to an and b1 to bn are formed respectively for output terminals out1 to outn and input terminals in1 to inn of data bus lines pin1 to pinn . the we signal is supplied from the logic ic 10 to control the tri - state buffers a1 to an . the we signal is supplied from the logic 10 through an invertor i1 as a control signal from the tri - state buffers b1 to bn . next , operations of the bi - directional switch circuit 31 will be described with reference to the timing chart of fig3 . as shown in fig3 since a write mode is invoked while the we signal from the logic ic 10 is at the low level , the tri - state buffers a1 to an are enabled so that output signals dout are supplied to the output terminals out1 to outn from the data bus lines pin1 to pinn . at this stage , the tri - state buffers b1 to bn are not enabled , and therefore , the input terminals in1 to inn are at a high impedance state ( hi - z ). on the other hand , since a read mode is invoked while the we signal from the logic ic 10 is at the high level , the tri - state buffers b1 to bn are enabled so that input signals din are supplied to the data bus lines pin1 to pinn respectively from the input terminals in1 to inn . here , since the tri - state buffers a1 to an are not enabled , the output terminals out1 to outn are at a high impedance state ( hi - z ). thus , by switching the inputs and the outputs in accordance with whether the we signal is at the low level or at the high level , the read timing and the write timing as those shown in fig2 and 22 are attained in the sram . fig4 shows an example of a structure of the row - column address dividing circuit 32 . in fig4 d - type flip - flops c1 to cn which operate in response to a trailing edge of the ras signal are connected to address lines a1 to an , respectively . in general , in a d - type flip - flop , an input supplied to a d - terminal at a rising edge or a trailing edge of a latch signal which is supplied to a t - terminal is stored as an output of a q - terminal ( this behavior is known as triggering ), and the output of the q - terminal will not be changed even if the input to the d - terminal changes until a rising edge or a trailing edge of the next latch signal . as can be seen in fig4 the address lines a1 to an are connected to the d - terminals of the d - type flip - flops c1 to cn , respectively . the ras signal is supplied from the logic ic 10 to the t - terminals of the d - type flip - flops c1 to cn . address lines a1 &# 39 ; to an &# 39 ; are connected to the q - terminals of the d - type flip - flops c1 to cn , respectively . the address lines a1 to an each branch before reaching the relevant d - terminal . these branches are address lines a1 &# 34 ; to an &# 34 ; on which original signals are outputted as they are . now , operations of the row - column address dividing circuits 32 will be described with reference to fig5 and 6 which , combined with each other at dotted line a -- a , illustrate a timing chart . fig7 shows a structure of fig5 and 6 . in fig5 and 6 , a row - column serial address signal rc consists of a row signal and a column signal which are supplied alternatively and an optional signal which is indicated by the crosshatching . for a convenience sake , the row and the column signals are numbered as a row 1 , a column 1 , . . . in the order of appearance . when the row - column serial address signal rc is supplied to the d - terminals of the d - type flip - flops c1 to cn and the ras signal is supplied to the t - terminals , the state of the row - column serial address signal rc at a trailing edge of the ras signal is stored . until a trailing edge of the next ras signal , the q - terminals keep outputting the row - column serial address signal rc of such a state . returning again to fig5 at a trailing edge of the first ras signal which is supplied to the t - terminals , the row - column serial address signal rc still remains as the row 1 signal . hence , the row 1 signal is outputted from the q - terminals . this continues until a trailing edge of the next ras signal . at the trailing edge of the next ras signal , the row - column serial address signal rc stays as the row 2 signal so that the row 2 signal is outputted from the q - terminals . thus , by triggering at timings of the row address signals which constitute the row - column serial address signal rc , only the row address signals are outputted from the address lines a1 &# 39 ; to an &# 39 ;. with respect to the column address signal , on the other hand , it is not necessary to output the column address signal alone using the d - type flip - flops . through the address lines a1 &# 39 ; to an &# 39 ;, the row - column serial address signal rc as it presently is is supplied to the memory ic 60 . the row - column serial address signal rc is triggered at a trailing edge of the cas signal , whereby the column address is designated in the memory ic 60 . the extracted row address signal is triggered at a trailing edge of the cas signal in the memory ic 60 so that the row address is finally designated . in this case , the cas signal corresponds to the ce signal of fig2 and 22 . therefore , the read and the write operation timings as those shown in fig2 and 22 are attained in the sram . as an example of a structure of the sram control signal generation circuit 33 , fig8 sows an sram control signal generation circuit 33a which is suitable for an early write cycle . in fig8 the sram control signal generation circuit 33a comprises an invertor i2 for inverting the cas signal , a cas signal latch circuit e which is formed by a d - type flip - flop which outputs an inverted signal received from the invertor i2 after a certain delay time in accordance with a clock signal clk , and an or circuit f which performs or operations in accordance with a signal from the cas signal latch circuit e and the we signal . as shown in fig8 the cas signal latch circuit e receives the inverted signal of the invertor i2 at its d - terminal . at its t - terminal , the cas signal latch circuit e receives the clock signal clk . the clock signal clk as herein termed refers to a master clock which is used for overall control of the system . next , operations of the sram control signal generation circuit 33a will be described with reference to fig9 and 10 which , combined with each other at dotted line a -- a , illustrated a timing chart . fig1 shows a structure of fig9 and 10 . basically , since it is only necessary to supply a rising edge of a wec signal , or a latch signal for writing sram data , in such a manner that data is written while the we signal stays at the low level , only the inverted signal of the cas signal and the we signal are necessary for the or operations . however , this is not sufficient in that designation of an address by the cas signal could take place concurrently with fixing of written data by the wec signal ( that is , d35 of fig2 could be 0 ). since data will not be written if this happens , writing of the data must be performed after a certain time from designation of the address . this is why the cas signal latch circuit e is disposed between the invertor i2 and the or circuit f . the cas signal latch circuit e receives an inverted signal of a cec signal ( which is the same as the cas signal but is to be referred to as such for discrimination from the cas signal ) from the invertor i2 at its d - terminal . at its t - terminal , the cas signal latch circuit e receives the clock signal clk . at a time when a rising pulse of the clock signal clk is supplied to the cas signal latch circuit e , the inverted signal of the cas signal is at the high level . since the inverted signal of the cas signal is at the low level at a rising pulse of the next clock signal clk , the cec signal after the clock clk is latched is shifted from the clock signal clk by half the cycle . hence , by supplying the cec signal after latching of the clock clk and the we signal to the or circuit f , it is possible to supply the wec signal , or the latch signal for writing sram data , from the or circuit f during the low - level period of the we signal . a shift of the cec signal after the clock clk is latched is determined so as to satisfy the relation between the time d32 and the time d35 of fig2 . as described above , the sram control signal generation circuit 33a , the bi - directional switch circuit 31 and the row - column address dividing circuit 32 having such structures constitute a ram interface circuit for an early write cycle . fig1 shows an sram control signal generation circuit 33b which deals with a delayed write cycle , as one of other examples of the sram control signal generation circuit 33 . in fig1 , the sram control signal generation circuit 33b comprises a we signal latch circuit h which is formed by a d - type flip - flop which delays the we signal for a certain delay time and outputs the we signal in response to a frequency - divided signal clks of the clock signal clk , a clock frequency - division circuit g which generates the frequency - divided signal clks of the clock signal clk which is used to govern the system as a whole , and an or circuit j which performs negative logic or operations in accordance with a qc signal which is received from a qc - terminal of the d - type flip - flop h and the we signal . the clock frequency - division circuit g of fig1 is formed by one d - type flip - flop which has a qc - terminal and a d - terminal connected to each other . from a q - terminal , the clock frequency - division circuit g outputs a signal which is shifted from the clock signal clk by one cycle as the frequency - divided signal clks . next , operations of the sram control signal generation circuit 33 will be described with reference to fig1 and 14 which , combined with each other at dotted line a -- a , illustrate a timing chart . fig1 shows a structure of fig1 and 14 . similarly to an early write cycle , a rising edge of the wec signal for writing of sram data must be supplied in a delayed write cycle as well . however , in a delayed write cycle , there is no latch signal which has an appropriate timing as the cas signal which is used in an early write cycle . hence , by latching we signal by the frequency - divided signal clks in the we signal latch circuit h to generate the qc signal which is outputted after a certain delayed time and thereby performing the or operations by the we signal and the qc signal in the or circuit j , a rising edge of the wec signal is generated . referring again to fig1 and 14 , when the we signal at the low level is supplied to the d - terminal of the d - type flip - flop h , the we signal latch circuit h delays the we signal for a certain delay time in accordance with the frequency - divided signal clks which is generated by the divider g , and outputs the delayed signal from the qc - terminal as an inverted signal . the output signal from the qc - terminal and the we signal are supplied to the or circuit j which performs negative logic or operations so that the wec signal , or a latch signal for writing sram data , is supplied during the low level period of the we signal . the frequency - divided signal clks is generated by frequency - dividing the clock signal clk once by the divider g in fig1 and 14 . however , as far as the relation between the time d32 and the time d35 of fig2 is satisfied , the clock signal clk may be frequency - divided for more times to generate the frequency - divided signal clks . a ram interface circuit for a delayed write cycle is formed by the sram control signal generation circuit 33b , the bi - directional switch circuit 31 and the row - column address dividing circuit 32 having such structures . while the invention has been described in detail , the foregoing description is in all aspects illustrative and not restrictive . it is understood that numerous other modifications and variations can be devised without departing from the scope of the invention .