having summarized various aspects of the present invention , reference will now be made in detail to the description of the invention as illustrated in the drawings . while the invention will be described in connection with these drawings , there is no intent to limit it to the embodiment or embodiments disclosed therein . on the contrary , the intent is to cover all alternatives , modifications and equivalents included within the spirit and scope of the invention as defined by the appended claims . it will be appreciated by persons skilled in the art that the cache memory and method for retrieving data described herein is not limited to the specific embodiments illustrated and described herein . further , it will be appreciated by persons skilled in the art that the invention described in connection with the various embodiments herein is applicable to a wide variety of cache architectures and organizations . as one example , the invention has been illustrated herein in connection with a rather generic cache architecture . it will be appreciated that the invention is readily applicable to cache memories having separate data and instruction caches , as well as unified caches . likewise , the concepts of the present invention are equally applicable to synchronous as well as asynchronous cache architectures . further still , the concepts and teachings of the present invention are applicable to caches having a direct - mapped architecture , a fully - associative architecture , or a set - associative architecture . further still , as is known by persons skilled in the art , and described in co - pending application ser . no . ______ ( tkhr docket 252207 - 1020 ), filed on apr . 3 , 2003 , the memory areas ( both data and tag ) are often partitioned into smaller cache blocks for simplicity and ease of implementation . the concepts and teachings of the present invention , as described herein , are completely applicable to cache architectures of this type . in such an architecture , the inventive concepts may be applied to each data memory area of each cache block . other extensions and applications of the present invention will be readily apparent to those skilled in the art from the discussion provided herein below . reference is now made to fig2 which is a block diagram illustrating portions of the internal architecture of a cache memory 100 constructed in accordance with one embodiment of the present invention . before describing the details of this diagram , or other embodiments , it is noted that the diagrams provided herein are not intended to be limiting upon the scope or spirit of the present invention . indeed , the embodiments illustrated herein , including the embodiment of fig2 have been selected for illustration and more ready comparison to the prior art illustrated in fig1 . further , the internal structure and operation of the various logic blocks illustrated in fig2 beyond that illustrated or described herein , are known and readily implementable by persons skilled in the art . consequently , the internal architecture and operation of these components need not be described herein . turning now to the diagram of fig2 a cache memory 100 is illustrated having a data memory 112 and a tag memory 14 . to facilitate the ready identification of certain inventive aspects of the embodiment of fig2 like reference numerals have been used to designate components within the cache memory 100 that may be identical to components of the conventional cache memory 10 of fig1 . in this regard , what is different with regard to fig2 is the read strobe control logic 140 . the latch 113 , and the addition of multiplexer 160 are also added in the embodiment of fig2 . as summarized above , the present invention takes advantage of the fact that a significant number of memory accesses are sequential . taking advantage of this known property , accesses to the data memory 112 may be reduced , thereby reducing the power used by the data memory 112 and likewise the power consumed by the cache 100 . in the embodiment illustrated in fig2 the latch component 113 may be designed to contain multiple words of data read from the data memory 112 . desirable sizes for the latch 113 may be two words , four words , or eight words . in one application , the data memory area 112 of the cache 100 contains cache lines that are eight data words each . therefore , the latch 113 in such an embodiment is preferably eight data words or less . further still , for design ease and implementation , the latch may be sized to be a power of two , such that it accommodates two data words , four data words , or eight data words . an output is provided for each data word of the latch 113 . there are four such outputs 126 illustrated in the embodiment of fig2 . it should be appreciated that each of these illustrated outputs 126 may be thirty - two bits , or one data word , in width . these outputs may be directed to a multiplexer 160 , or other appropriate circuit component , for selection to be delivered to the output 38 of the cache 100 . that is , the multiplexer select lines 161 may be controlled to selectively route the desired output 126 from the latch 113 through the multiplexer 160 to the output 38 . a novel component to the embodiment of fig2 is the read strobe control logic 140 . this logic 140 is desired to operate to inhibit the normal strobing of the read strobe signal 141 , when it is determined that the desired data already resides in the latch element 113 . by inhibiting the normal strobing and reading of data from the data memory , switching of the various gate elements within the data memory 112 is inhibited , which significantly reduces the power consumption thereof ( particularly when fabricated from cmos ). accordingly , one aspect of this embodiment of the present invention is the generation of the read strobe signal 141 for the data memory 112 . reference is made to fig3 which is a block diagram illustrating one embodiment of a potential implementation for the read strobe control logic 140 . for simplicity in illustration , a component of this control logic is the logic 40 ( of fig1 ) that may be used for generating the read strobe signal in conventional cache memories . assuming , in the context of the particular illustrated embodiment , that the read strobe 141 is an active low signal , then an or gate 142 may be utilized to gate an inhibit signal 143 with the read strobe 41 generated by conventional read strobe logic 40 . thus , when the inhibit signal 143 is a logic 1 , then the read strobe signal 141 is a logic 1 , thereby inhibiting the strobing of the data memory 112 . the remainder of the logic for generating the read strobe signal 141 operates to inhibit the read strobe if the data that is sought already resides in the latch . this determination may be made by recognizing that : ( 1 ) the data sought is sequentially located with respect to the previously - retrieved data ; and ( 2 ) the data currently sought is not in the first location of the latch 113 . logic 170 may be provided for indicating whether the currently - requested data is sequentially located with respect to the previously - retrieved data . if the cache memory is designed as a part of a processor circuit ( e . g ., onboard ), then other signals or circuitry within the processor ( if designed appropriately ) may generate this signal 171 automatically . for example , this signal 171 may be readily generated from logic associated with the program counter , for an instruction cache . alternatively , logic may be provided within the execution portion of a processor pipeline for generating the signal 171 . alternatively , the logic 170 may be designed as part of the cache itself . in such an embodiment , the logic may simply compare the tag held in the latch 15 , from a previous data access , with the tag currently carried on the address bus 20 in connection with the identification of the data currently requested . the circuitry for performing such a comparison need not be described herein , as its design or development will be readily appreciated by persons skilled in the art . if signal 171 indicates that the data access is sequential , for the embodiment of fig2 and 3 , it must then ensure that the currently - requested data would not be the first data word of the latch 113 . this determination can be readily made by ensuring that the two least significant address bits ( e . g ., a 1 and a 0 ) are not both logic zero . therefore , in one implementation , an or gate 146 may compare the two least significant address bits ( a 1 and a 0 ). if either or both of these address bits is a logic one , then output of or gate 146 is a logic one . this value may be compared by and gate 144 with the signal 171 , which indicates whether the currently - requested data is sequentially located with respect to the previously - retrieved data . if signal 171 is a logic one , and the output from or gate 146 is a logic one , then the read strobe 141 will be inhibited . on the other hand , if the signal carried on line 171 is a logic zero ( indicating the currently - requested data is not sequential ), or if the currently - requested data resides in the first location of the latch 113 , then the read strobe signal 141 will simply be the read strobe 41 output from the conventional read strobe logic 40 . to further illustrate , consider a data memory 112 having an eight word cache line , with an output latch 113 designed to hold four words read from the data memory 112 . if the first data word requested corresponds to the first data word on a cache line , then ( after filling the cache line from system memory ) the read strobe control logic 140 does not inhibit the conventional read strobe signal ( since the two least significant bits of the requested data would be logic zero , regardless of whether the requested data was sequential or not ), so the first four words of the cache line would be retrieved into the latch 113 . the multiplexer 160 would be controlled to direct the first word to the output 38 . if the following request for data was for the second data word on that same cache line , then the logic 170 indicates that the request is a sequential access , and the value of the least significant address bits is one . therefore , the logic 140 operates to inhibit the read strobe 141 . this prevents the data memory 112 from consuming the power required to access and retrieve data therein , thereby reducing the power that would otherwise be consumed by the data memory in retrieving the data . the multiplexer 160 could then be selected to deliver the second data word to the output 38 . to further illustrate with a slightly different example , if the first request for data was for a data word residing in the second location of a cache line ( assuming the cache retrieves the data from system memory from even cache line boundaries ), the read strobe signal 141 would not be inhibited . although the least significant address bits would not indicate that the data resides in the first location of the latch 113 , the logic 170 for generating the sequential access signal 171 wold be at a logic zero , thereby indicating that the data access is not sequentially located with respect to the previous data retrieved . it should be appreciated that the embodiment of fig3 which uses the two least significant bits of the address bus ( a 1 and a 0 ) is designed for a latch 113 that holds four data words . it can , however , be readily expanded for latches of different sizes . for example , if the latch held only two data words , then only address line a 0 would be needed , and or gate 146 would not be required ( address line a 0 would be input directly to and gate 144 ). likewise , if the latch held 8 data words , then address lines a 2 , a 1 , and a 0 would be utilized ( all input to a three - input or gate ). reference is now made to fig4 which is similar to fig2 but illustrates a slightly different embodiment of the present invention . it should be appreciated from the foregoing discussion that a key aspect of the present invention is the recognition that the data currently requested resides in a latch , or other circuit component within the cache , so that the data need not be separately and independently retrieved from the data memory portion of the cache . due to the largely sequential nature of data accesses , this results in a significant power savings by inhibiting needless data reads of the data memory . in the embodiment illustrated in fig4 the data memory 212 may be designed such that a latch is not an integral part of the data memory . accordingly , a data hold component 213 is illustrated as being coupled to the output of the data memory 212 . the data hold component , in one embodiment , may be a latch . however , consistent with the scope and spirit of the present invention , the data hold component 213 may be any of a variety of other components as well . [ 0033 ] fig4 also illustrates logic 240 for inhibiting data memory accesses . the logic 240 may be implemented identically to the logic 140 of fig2 . in other embodiments , however , the logic 240 may take on a different form . as one example , the logic 140 illustrated in connection with fig2 was used in combination with conventional read strobe generation logic . it should be appreciated that the present invention is not limited to embodiments that inhibit a read strobe signal , but is readily applicable to embodiments that may otherwise inhibit the active operation of the data memory 212 . in one embodiment , an enable signal may be provided in connection with a data memory element , separate and distinct from the read strobe input . the logic 240 of the embodiment of fig4 may generate such a signal and direct it to an enable input or other input of the data memory 212 for inhibiting its normal operation . in such an embodiment , conventional read strobe generation circuitry ( not illustrated in fig4 ) may be coupled to the read strobe input of the data memory 212 . having described certain architectural embodiments of the invention , reference is now made to fig5 which is a flowchart illustrating a top - level functional operation of one embodiment of the present invention . in a first step , a read request is made ( step 302 ), or data is otherwise requested from the data memory portion of the cache . the embodiment then determines whether the requested data is sequentially located with respect to the previously - retrieved data ( step 304 ). if the data is not sequentially located , then data is retrieved from the data memory portion of the cache ( step 306 ) and latched into a latch component coupled to the output of the data memory ( step 308 ), as in conventional cache operation . thereafter , data may be read from the latch ( step 310 ) and output from the cache . if , however , step 304 determines that the requested data is sequentially located with respect to the previously - retrieved data , then the method determines whether the least significant bits of the address line are all logic zero ( step 312 ). if so , it is determined that the data will reside in the first location of the latch , and the method proceeds to step 306 . if , however , the least significant address bits are not equal to zero , then the method operates to inhibit the data memory from performing an active data retrieval ( step 314 ), and reads the data directly from the latch or other component capable of holding data ( step 310 ). reference is now made to fig6 which is a flowchart illustrating the top - level functional operation of another embodiment of the invention . like fig5 the method of fig6 begins when a read request is made to the data memory ( step 402 ). thereafter , the method determines whether the current tag is the same as the previous tag . if not , then data must be read from a different cache line , and therefore cannot reside in the latch . therefore , if step 404 resolves to no , then data is retrieved from the data memory ( step 406 ) and latched ( step 408 ) as described in connection with fig5 . thereafter , data may be read from the latch ( step 410 ). if , the tag of the currently - requested data is the same as the tag from the previously - retrieved data , then it is determined that the currently - requested data resides in the latch . for this determination to hold consistently true , it will be appreciated that the latch of the embodiment of fig6 is of equal size to the cache line of the data memory area . thereafter , if the determination of step 404 resolves to yes , then the method inhibits the data memory from active data retrieval ( step 412 ) and the data may be read from the latch or other component capable of holding data ( step 410 ). reference is now made to fig7 which is a flowchart illustrating the top - level functional operation of yet another embodiment of the invention . like the embodiments of fig5 and 6 , the method of fig7 begins with a read request for data within the data memory of the cache ( step 502 ). the method of fig7 is suitable for cache architectures different than those illustrated in fig2 and 4 . specifically , it is recognized that certain cache architectures may be provided that do not have a latch or other holding component coupled to the output of the data memory . however , certain architectures may nevertheless retrieve data from the data memory and hold that data in yet another circuit component , until a later cache line is read . in the embodiment of fig7 a determination is made as to whether the requested data is currently available in another component within the cache ( step 504 ). by “ another ” component , step 504 is referring to a component other than the data memory . therefore , the “ another ” component could be a latch ( as in fig2 ), a data hold circuit component ( as in fig4 ), or some other component within the cache . if the data is not readily available in another component , then it may be retrieved from the data memory ( step 506 ) and latched ( or held ) by another circuit component ( step 508 ), as described above in connection with fig5 and 6 . thereafter , the held data may be read ( step 510 ). if , however , step 504 determines that the currently - requested data is available in another component within the cache , then the data memory may be inhibited from normal operation ( step 512 ) and the currently - requested data may be directly read from the “ another ” component from which it is currently available ( step 514 ). it should be appreciated from the foregoing that a variety of alternative embodiments , applicable to a variety of cache architectures , a readily implementable , consistent with the scope and spirit of the invention . the embodiments and described herein have been particularly chosen for simplicity in illustration of certain aspects of the present invention . the foregoing description is not intended to be exhaustive or to limit the invention to the precise forms disclosed . obvious modifications or variations are possible in light of the above teachings . in this regard , the embodiment or embodiments discussed were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated . all such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly and legally entitled .