fig2 a is a schematic diagram depicting one embodiment of my invention . pulse width digital to analog converter 10 of fig2 a is shown as a nine bit digital to analog converter . naturally , other embodiments of this invention can be constructed to operate on other than nine bit words . digital to analog converter ( dac ) 10 includes nine bit latch 11 which , upon application of a clock signal sample or load ( shown in fig2 c ) receives and stores nine bits a1 through a9 of a digital input word which represents the desired analog output voltage . latch 11 stores this nine bit (&# 34 ; first &# 34 ;) word during the entire sampling period , until a subsequent nine bit word is stored in latch 11 in response to the next load signal . a second output clock signal reload or 4 - load ( shown in fig2 d ) having four times the frequency of the clock signal load is applied to the input lead of counter 12 and causes the seven most significant bits 03 through 09 (&# 34 ; second &# 34 ; word ) to be loaded into down counter 12 from latch 11 . the n ( nine ) bit first word is in effect divided by k 2 ( four ), to produce an n - k ( seven ) bit second word , with a k ( two ) bit remainder . the n - k ( seven ) bit value is reloaded and recounted k 2 ( four ) times , and the value of the remainder is added back , one unit to a recount , to produce k 2 ( four ) output pulses of a total duration equal to the n ( nine ) bit value times the count clock period p . the signals load and 4 - load are synchronized so that a rising edge of load always coincides with a rising edge of 4 - load . once the seven most significant bits d3 through d9 are loaded into counter 12 , counter 12 decrements its count by one in response to each count signal ( shown in fig2 b ), ultimately causing the count stored in counter 12 to be equal to 0000000 . in this embodiment , the frequency f count = 2 9 f load . the output signals d3 through d9 from counter 12 are applied to the input leads of nor gate 30 . nor gate 30 provides a logical one output signal when the count stored within counter 12 has been decremented to 0000000 , and provides an output signal of logical zero at all other times . inverter 32 , therefore , provides a logical zero output signal when the count d3 through d9 stored within counter 12 has been decremented to 0000000 , and provides a logical one output signal at all other times . thus , because the output signal from inverter 32 is applied to one input lead of nor gate 28 , the output signal from nor gate 28 , is a logical zero at least until the count stored within counter 12 has not been decremented to 0000000 . the output signal from nor gate 28 is applied to the s input lead of rs flip flop 33 , and thus causes the q signal of flip flop 33 to become a logical zero when the output signal from nor gate 28 becomes a logical one . the q signal remains a logical zero until the end of the subperiod t . the reload signal which reloads counter 12 also resets flip - flop 33 to output a high q signal . as soon as counter 12 is reloaded upon receipt of the next 4 - load signal , it decrements its count by 1 in response to each count signal as described above . thus , the number represented by the seven most significant bits d3 through d9 in counter 2 is counted down to zero four times during each period of the load signal . in contrast to prior art dac &# 39 ; s in which the input sample frequency is identical to the output clock frequency , the present invention utilizes an output clock frequency reload which is a multiple ( in this example , 4 ) of the input sample frequency . in this manner , the noise component of the analog output signal due to the output clock frequency is increased in frequency as compared with prior art dac &# 39 ; s having the same input sample frequency and resolution , thereby moving the frequency of the noise component further away from the frequency band of interest . in one embodiment , the dac of this invention is used to generate analog audio signals , and the noise component due to the sampling frequency is increased in frequency above the range of human hearing , thereby eliminating or at least minimizing the filtering requirements necessary to remove the noise component of the output signal . the two least significant bits 02 and 01 stored in latch 11 , ring counter 13 , and full - period extension decision circuitry 77 operate in unison in order to determine whether the output signal from nor gate 27 is to remain a logical one for one count clock period after the complete decrementation of the count stored within counter 12 to a value of 0000000 in each of four output clock time periods t1 through t4 ( determined by the 4 - load signal ) associated with a input signal sample time period . the four consecutive time periods t1 through t4 divide the input sample period into four equal parts . in this manner , by allowing the output signal to remain a logical one for an additional single period of the count signal in a selected number 0 , 1 , 2 , or 3 of time periods t1 through t3 , ( as shown in fig2 e ) the resolution of the novel dac of this invention is equal to the resolution of prior art dac &# 39 ; s which utilize a lower output clock frequency . four bit ring counter 13 provides four output bits p0 through p3 reflecting the current time period t1 through t4 of the current input sample period . in this embodiment output bit p0 is not used . ring counter 13 is reset upon receipt of a load signal at its reset terminal 103 such that p3 is a logical one , and p0 through p2 are logical zeros . ring counter 13 then shifts the logical one one bit to the right in response to receipt of each 4 - load signal ( having a frequency equal to four times f load ) at its count terminal 102 . referring to table 1 , the truth table representing the output signal provided by nor gate 26 of full period extension decision circuitry 77 as a function of input signals 01 , 02 , and time periods t1 through t4 is shown . for example , with the two least significant bits 01 and 02 both equal to zero , no extension of the trailing edge of the output signals provided during time periods t1 through t4 is desired . similarly , when 02 is zero and 01 is one , a single extension during time period t1 is desired ; when 02 is 1 and 01 is zero , two extensions ( during time periods t1 and t2 ) are desired ; and when 02 and 01 are both one , three extensions are desired , one each in time periods t1 , t2 , and t3 . the output signal from nor gate 26 represents whether a full count period extension is required during the time periods t1 through t4 . nor gate 26 provides a logical zero output signal when a full period extension is required , and provides a logical one output signal when a full period extension is not required . the output signal is applied to one input lead of nor gate 27 whose other input lead is connected to one count delay means 29 , which provides a logical one output signal one count period after the output signal from nor gate 30 becomes a logical one in response to the complete decrementation of the count stored within counter 12 . thus , if the output signal from nor gate 26 is a logical zero and the output signal from delay means 29 is a logical zero , nor gate 27 will provide a logical one output signal applied to one input lead of nor gate 28 , thereby causing the output lead of nor gate 28 to remain a logical zero , and prevent the setting of rs flip flop 33 . thus , even after the complete decrementation of the count within counter 12 , upon which the output signal from inverter 32 becomes a logical zero , the output signal from nor gate 27 remains a logical one for one count period if full period extension decision logic 77 provides a logical one signal on an input to nor gate 26 , thereby indicating that an extension is required . after that one count period , the output signal from delay means 29 becomes a logical one , thereby causing nor gate 27 to provide a logical zero output signal , which does not keep the output signal from nor gate 28 from becoming a logical one . in general , following the above teaching , a positive n bit word is stored in a latch in response to a load signal having frequency f load and period p . the most significant ( n - k ) bits of the n bit word are loaded into a counter in response to a second load ( reload ) signal having a frequency of 2 k × f load , where n and k are positive integers . the ( n - k ) bit word is decremented by one ( until it becomes zero ) in response to a count clock signal having a frequency of 2 n × f load so that the ( n - k ) bit word is decremented to zero 2 k times in each period p . a ring counter having 2 k output signals operates together with the full - period extension decision circuitry and the one count delay means to hold the output signal of the digital to analog converter high for an additional count clock period in each sample period p the first j times the n - k bit word is decremented to zero , where j is the value of the k bit word consisting of the k least significant bits of the n bit word . in another embodiment of this invention , as shown in fig2 f , an additional means is provided for providing additional one bit resolution without increasing f count , the frequency of the count signal . in this case , a 10 bit word a0 , a1 ,-- a9 is stored in latch 11 on the rising edge of the load signal and the seven most significant bits 03 through 09 and the second and third least significant bits 01 and 02 are treated as described in the first embodiment described above . the least significant bit 00 is used together with output signal p0 from ring counter 13 to provide the input signals to nand gate 23 , which serves as the one - half period extension logic . as shown in table 2 , nand gate 23 will provide a logical zero output signal if and only if the least significant bit 00 is a logical one and signal p0 from ring counter 13 is a logical one , indicating time period t4 . in this event , the output signal from nor gate 24 is determined by the output signal from one - half count delay means 25 , which serves as the second input signal to nor gate 24 . delay means 25 provides an output signal of a logical zero during the first one - half count period after the output signal from nor gate 30 becomes a logical one indicating that the count stored within counter 12 has been completely decremented to 0000000 , thus causing the output signal from nor gate 24 to be a logical one , thus allowing nor gate 28 to continue providing a logical zero output signal . one - half count period later , however , the output signal from delay means 25 is a logical one , thus causing nor gate 24 to provide a logical zero output signal , thereby causing nor gate 28 to provide a logical one output signal . this , in effect , allows , during time period t4 , an additional one - half count period extension of the output pulse . in one embodiment of my invention one count delay means 29 ( fig2 a ) comprises a flip flop , such as a d type flip flop well known to those who are skilled in the art . when a d type flip flop is used as one count delay means 29 , its d input lead is connected to the signal to be delayed provided on the output lead of nor gate 30 , its q output signal provides the delayed signal , and the d type flip flop is controlled by a suitable clock such as count . similarly , in one embodiment of my invention , one - half count delay means 25 also comprises a flip flop , such as a d type flip flop . when a d type flip flop is used as the one - half count delay means 25 , its d input lead is connected to receive the signal to be delayed by one - half count ( i . e ., the signal provided on the output lead of nor gate 30 ), and its q output lead provides the delayed signal . the d type flip flop is controlled by a suitable clock signal , such as by count . in general , following the above teaching , a positive n bit word is stored in a latch in response to a load signal having a frequency f load and period p , where n is a positive integer . the first ( n - k ) most significant bits of the n bit word are loaded into a counter in response to a second load signal having a frequency of 2 k - 1 × f load . the ( n - k ) bit word is decremented by one ( until it becomes zero ) in response to a clock signal having a frequency of 2 n - 1 × f load , so that the ( n - k ) bit word is decremented to zero 2 k - 1 times in each period p . a ring counter having 2 k - 1 output signals operates together with the full - period extension decision circuitry , the one count delay means and the one - half count delay means to hold the output signal of the digital to analog converter high for an additional clock period the first j times the n - k bit word is decremented to zero , where j is the value of the word consisting of the ( k - 1 ) most significant bits of the k least significant bits of the n bit word and to hold the output signal high for an additional one - half clock period in each period p when the least significant bit of said first digital word is one . in another embodiment , an n bit digital word is stored in a latch in response to a first load signal having a frequency of f load . then the n bit word is stored in a counter in response to a second load signal having frequency m × f load where m is a positive integer greater than or equal to 2 . the n bit word in the counter is then decremented by one ( until it becomes zero ) in response to each pulse of a clock signal having a frequency of m × 2 n × f load where m is a positive integer greater than one , so that the n bit word is decremented to zero m times in each period p . the output signal of the digital to analog converter is high when the word in the counter is positive and low when the decremented number stored in the counter is zero . in this manner the output clock rate is a multiple of the input sampling rate . the above embodiments are intended to be exemplary and not limiting and many substitutions and modifications may be made therein by one of ordinary skill in the art without departing from the spirit and scope of the invention . table 1__________________________________________________________________________decimalvalue 02 01 p3 p2 p1 p0 period 19a 19b 20a 20b 21a 21b 20 22 19 21 26 extension ? value__________________________________________________________________________0 0 0 1 0 0 0 t1 0 1 0 0 1 1 1 0 0 0 1 no 0 0 0 0 1 0 0 t2 1 1 1 0 1 1 1 0 0 0 1 no 0 0 0 0 1 0 t3 1 1 0 0 0 1 1 0 0 0 1 no 0 0 0 0 0 1 t4 1 1 0 0 1 1 1 0 0 0 1 no1 0 1 1 0 0 0 t1 0 0 0 0 1 1 1 0 1 0 0 yes 1 0 1 0 1 0 0 t2 1 0 1 0 1 1 1 0 0 0 1 no 0 1 0 0 1 0 t3 1 0 0 0 0 1 1 0 0 0 1 no 0 1 0 0 0 1 t4 1 0 0 0 1 1 1 0 0 0 1 no2 1 0 1 0 0 0 t1 0 0 0 1 1 1 1 0 1 0 0 yes 2 1 0 0 1 0 0 t2 1 0 1 1 1 1 0 1 0 0 0 yes 1 0 0 0 1 0 t3 1 0 0 1 0 1 1 0 0 0 1 no 1 0 0 0 0 1 t4 1 0 0 1 1 1 1 0 0 0 1 no3 1 1 1 0 0 0 t1 0 0 0 1 1 0 1 0 1 0 0 yes 3 1 1 0 1 0 0 t2 1 0 1 1 1 0 0 1 0 0 0 yes 1 1 0 0 1 0 t3 1 0 0 1 0 0 1 0 0 1 0 yes 1 1 0 0 0 1 t4 1 0 0 1 1 0 1 0 0 0 1 no__________________________________________________________________________ table 2______________________________________decimal value 00 p0 23 extension______________________________________0 0 0 1 no0 0 1 1 no1 1 0 1 no1 1 1 0 yes______________________________________