hereinafter , embodiments will be described with reference to drawings . however , the embodiments can be implemented with various modes . it will be readily appreciated by those skilled in the art that modes and details can be changed in various ways without departing from the spirit and scope of the present invention . thus , the present invention should not be interpreted as being limited to the following description of the embodiments . in this embodiment , a semiconductor memory device in fig1 a will be described . the semiconductor memory device in fig1 a includes a row driver 101 , a column driver 102 , a plurality of word lines 103 connected to the row driver 101 , a plurality of bit lines 104 ( indirectly ) connected to the column driver 102 , and memory cells 105 each provided at the intersection of the word line 103 and the bit line 104 . this structure is the same as that of the conventional dram in fig2 a and 2b . the semiconductor memory device in fig1 a further includes back gate transistors 108 each inserted between the column driver 102 and the bit line 104 . it can also be said that the back gate transistor 108 is inserted in the bit line 104 . it can also be said that a source of the back gate transistor 108 is connected to the column driver 102 , and a drain of the back gate transistor 108 is connected to the bit line 104 . it can also be said that the back gate transistor 108 is inserted between the column driver 102 and the memory cell 105 that is the closest to the column driver 102 . a gate of the back gate transistor 108 is connected to a bit line controlling line 112 , and a back gate of the back gate transistor 108 is connected to a back gate line 111 . the potential of the bit line controlling line 112 is set by a bit line controlling circuit 110 . the back gate line 111 is connected to one electrode of a capacitor 109 , and the potential thereof is held at an appropriate negative value regardless of whether or not an external power supply is provided . for that purpose , charge may be injected so that the potential of the capacitor 109 ( the back gate line 111 ) becomes appropriate , and then the back gate line 111 may be brought into a floating state . alternatively , with the back gate line 111 placed in a floating state , an electron beam with an energy of several tens of kilo electron volts or higher may be injected into part thereof . note that as illustrated in fig1 b , the back gate line 111 may be connected to a negative electrode of a battery 113 provided over a substrate where the semiconductor memory device is formed or in a package including the substrate . since the amount of current flowing through the back gate line 111 is significantly small , the capacity of the battery 113 can be extremely low . when the semiconductor memory device is powered by an external power supply and is determined to be usable , the bit line controlling circuit 110 supplies the bit line controlling line 112 with an appropriate potential to turn on the back gate transistor 108 . when interruption of power from the external power supply is detected , or termination of the use of the semiconductor memory device is detected even while the semiconductor memory device is powered by the external power supply , the bit line controlling circuit 110 sets the potential of the bit line controlling line 112 to 0 v or less to rapidly turn off the back gate transistor 108 . a semiconductor memory device according to this embodiment will be described with reference to fig3 . the semiconductor memory device in fig3 has sense amplifiers 114 inserted in bit lines 104 . the sense amplifier 114 is used to divide the bit line 104 into appropriate lengths to lower the bit line capacitance during read operation so that read accuracy can be increased . with the sense amplifier 114 inserted in the bit line 104 in this manner , when power from an external power supply is interrupted , for example , the charge in the bit line 104 flows out also through the sense amplifier 114 . as a result , when power from the external power supply is interrupted , the potential of the bit line 104 connected to the sense amplifier decreases to 0 v . therefore , it is necessary to prevent charge in the bit lines 104 from flowing out when power from the external power supply is interrupted , by providing the back gate transistors such that the sense amplifier 114 is sandwiched therebetween . the semiconductor memory device in fig3 includes a column driver 102 , a plurality of word lines 103 , a plurality of bit lines 104 , and memory cells 105 each provided at the intersection of the word line 103 and the bit line 104 . in addition , the sense amplifier 114 is inserted in the bit line 104 . like the semiconductor memory device described in embodiment 1 , the semiconductor memory device in fig3 further includes back gate transistors 108 _ 1 each inserted between the column driver 102 and the bit line 104 . a gate of the back gate transistor 108 _ 1 is connected to a bit line controlling line 112 _ 1 , and a back gate of the back gate transistor 108 _ 1 is connected to a back gate line 111 _ 1 . the potential of the back gate line 111 _ 1 is held at an appropriate negative value regardless of whether or not the external power supply power is provided . the semiconductor memory device in fig3 further includes back gate transistors 1082 and back gate transistors 108 _ 3 each provided between the sense amplifier 114 connected to the bit line 104 and the memory cell 105 that is the closest to the sense amplifier 114 . a gate of the back gate transistor 108 _ 2 is connected to a bit line controlling line 112 _ 2 , and a gate of the back gate transistor 108 _ 3 is connected to a bit line controlling line 112 _ 3 . a back gate of the back gate transistor 1082 is connected to a back gate line 111 _ 2 , and a back gate of the back gate transistor 108 _ 3 is connected to a back gate line 111 _ 3 . the potentials of the back gate line 111 _ 2 and the back gate line 111 _ 3 are each held at an appropriate negative value regardless of whether or not the external power supply power is provided . in such a semiconductor memory device , the potentials of the bit line controlling lines 112 _ 1 to 112 _ 3 change according to conditions in a manner similar to that in embodiment 1 . in other words , when the semiconductor memory device is powered by an external power supply and is usable , the bit line controlling lines 112 _ 1 to 112 _ 3 are supplied with such a potential that the back gate transistors 108 _ 1 to 108 _ 3 are turned on . in contrast , when power from the external power supply is interrupted or when the use of the semiconductor memory device is terminated even while the semiconductor memory device is powered by the external power supply , the bit line controlling lines 112 _ 1 to 112 _ 3 are supplied with such a potential that the back gate transistors 108 _ 1 to 108 _ 3 are turned off . for example , when power from the external power supply is interrupted , the potential of the bit line controlling lines 112 _ 1 to 112 _ 3 rapidly becomes 0 v or less to turn off the back gate transistors 108 _ 1 to 108 _ 3 . consequently , the bit line 104 is divided by the back gate transistors 108 _ 1 to 108 _ 3 . thus , even if the potential of portions of the bit line 104 connected to the column driver 102 and the sense amplifier 114 becomes 0 v , the potential of the other portions ( portions connected to the memory cells 105 ) can remain at an appropriate value (& gt ; 0 v ). on the other hand , because the potential of the word line 103 is 0 v , the cell transistor in the memory cell has sufficiently high resistance , and thus enables charge accumulated in the capacitor to be retained for a long period of time . a semiconductor memory device in fig4 a and 4b will be described . memory cells 117 in the semiconductor memory device in fig4 a and 4b have the same configuration as those described in patent document 4 . refer to patent document 4 for the operation and the like of the memory cells 117 . as illustrated in fig4 b , the memory cell 117 according to this embodiment includes a write transistor 118 , a read transistor 119 , and a capacitor 120 . a source of the write transistor 118 and a source of the read transistor 119 are connected to a bit line 104 . a gate of the write transistor 118 is connected to a write word line 115 . a drain of the write transistor 118 and a gate of the read transistor 119 are connected to one electrode of the capacitor 120 . the other electrode of the capacitor 120 is connected to a read word line 116 . the potentials of the write word lines 115 and the read word lines 116 are controlled by a row driver 101 . the potential of the bit line 104 is controlled by a column driver 102 . while there are such many differences between the memory cell 105 according to embodiment 1 or 2 and the memory cell 117 according to this embodiment , these memory cells are the same in that the source of the write transistor 118 ( which corresponds to the cell transistor 106 in the memory cell 105 in fig1 a ) is connected to the bit line 104 and the drain of the write transistor 118 is connected to one electrode of the capacitor 120 . in other words , for data retention , the write transistor 118 needs to exhibit high resistance in the off state . thus , in a manner similar to that in embodiments 1 and 2 , back gate transistors 108 each inserted between the column driver 102 and the bit line 104 are provided , which can achieve sufficiently high resistance even when power from an external power supply is interrupted ( see fig4 a ). a gate of the back gate transistor 108 is connected to a bit line controlling line 112 , and a back gate of the back gate transistor 108 is connected to a back gate line 111 . the potential of the back gate line 111 is held at an appropriate negative value regardless of whether or not the external power supply is provided . in such a semiconductor memory device , the potential of the bit line controlling line 112 changes according to conditions in a manner similar to that in embodiment 1 . in other words , when the semiconductor memory device is powered by the external power supply and is usable , the bit line controlling line 112 is supplied with such a potential that the back gate transistor 108 is turned on . in contrast , when power from the external power supply is interrupted or when the use of the semiconductor memory device is terminated even while the semiconductor memory device is powered by the external power supply , the bit line controlling line 112 is supplied with such a potential that the back gate transistor 108 is turned off . for example , when power from the external power supply is interrupted , the potential of the bit line controlling line 112 rapidly becomes 0 v or less to turn off the back gate transistor 108 . consequently , the potential of the bit line 104 can remain at an appropriate value (& gt ; 0 v ). on the other hand , because the potential of the write word line 115 is 0 v , the write transistor 118 in the memory cell 117 has sufficiently high resistance , and thus enables charge in the capacitor 120 to be retained for a long period of time . the memory cell 117 is characterized by being capable of amplifying a signal with the read transistor 119 and output the amplified signal to the bit line even if the capacitance of the capacitor 120 is low . however , the fact that the capacitance of the capacitor 120 is low means that it is difficult to retain data for a required time if the resistance of the write transistor 118 in the off state is not sufficiently high . therefore , keeping , during power interruption , the potential of the bit line 104 at an appropriate positive value with the back gate transistor 108 to increase the resistance of the write transistor 118 in the off state is particularly effective in this embodiment . a brief description is given of a process for manufacturing the semiconductor memory device illustrated in , for example , fig1 a and 1b or fig3 with reference to fig6 a to 6c , fig7 a and 7b , and fig8 . refer to known semiconductor integrated circuit manufacturing techniques for the details . note that fig6 a to 6c , fig7 a and 7b , and fig8 illustrate the concepts of the manufacturing process and do not show specific cross sections . first , device isolation insulators 202 , n - type impurity regions 203 n , p - type impurity regions 203 p , an n - channel transistor gate 204 n , a p - channel transistor gate 204 p , a first interlayer insulator 205 , first contact plugs 206 a to 206 d , and the like are formed over a surface of a substrate 201 of a semiconductor or the like by known semiconductor integrated circuit manufacturing techniques . the n - channel transistor or the p - channel transistor here may be used in a row driver , a column driver , a sense amplifier , or the like in a semiconductor memory device . next , first layer wirings 208 a to 208 d are formed so as to be embedded in a first embedment insulator 207 . these wirings are used in , for example , the row driver 101 or the column driver 102 in fig1 a and 1b , or the sense amplifier 114 . further , a second interlayer insulator 209 , a second contact plug 210 , a second embedment insulator 211 , second layer wirings 212 a to 212 c are formed . here , the second layer wiring 212 b corresponds to the back gate of the back gate transistor 108 or the back gate line 111 in fig1 a and 1b . note that one or more layers including another wiring may be additionally provided between a layer including the second layer wirings 212 a to 212 c and a layer including the first layer wirings 208 a to 208 d . further , a third interlayer insulator 213 , third contact plugs 214 a to 214 c , a third embedment insulator 215 , and third layer wirings 216 a to 216 e are formed . note that the first contact plug 206 a , the first layer wiring 208 a , the second contact plug 210 , the second layer wiring 212 a , the second layer wiring 212 c , the third contact plug 214 a , the third contact plug 214 b , the third layer wiring 216 a , and the third layer wiring 216 b serve as part of the bit line 104 in fig1 a and 1b . subsequently , an oxide semiconductor layer 217 a and an oxide semiconductor layer 217 b are formed , and a gate insulator 218 is formed so as to cover them . at this time , it is preferable that the physical thickness of the gate insulator 218 be two or more times that of the oxide semiconductor layer 217 a and the oxide semiconductor layer 217 b , because this enables the oxide semiconductor layer 217 a and the oxide semiconductor layer 217 b to be covered with the gate insulator 218 reliably , thereby preventing shorts between wirings . on the other hand , it is preferable that the effective thickness of the gate insulator ( e . g ., the equivalent oxide thickness ) be less than or equal to that of the oxide semiconductor layer 217 a and the oxide semiconductor layer 217 b . therefore , it is preferable that the gate insulator 218 be formed using a material whose dielectric constant is twice that of the oxide semiconductor layer 217 a and the oxide semiconductor layer 217 b . for example , the gate insulator 218 may be formed using a high dielectric constant material such as hafnium oxide , tantalum oxide , or zirconium oxide . materials such as barium oxide , strontium oxide , calcium oxide , and lithium oxide which form silicides on silicon semiconductor have been prevented from being used with silicon semiconductor , but may be used with an oxide semiconductor without problems . therefore , any of these materials can be used for the gate insulator 218 as long as it has high dielectric constant . then , fourth layer wirings 219 a to 219 d are formed . the fourth layer wiring 219 a here corresponds to the gate of the back gate transistor 108 or the bit line controlling line 112 in fig1 a . the fourth layer wirings 219 b to 219 d correspond to the word lines 103 in fig1 a . stacked capacitors are formed by known dram manufacturing techniques . specifically , a fourth interlayer insulator 220 , a fourth contact plug 221 a , and a fourth contact plug 221 b are formed , and then a fifth interlayer insulator 222 , a capacitor electrode 223 a and a capacitor electrode 223 b are formed thereover . subsequently , a capacitor insulator 224 and a cell plate 225 are formed . thus , the semiconductor memory device can be manufactured . a brief description is given of a process for manufacturing the semiconductor memory device illustrated in fig4 a and 4b with reference to fig9 a to 9d and fig1 a to 10c . refer to known semiconductor integrated circuit manufacturing techniques or patent document 2 for the details . note that fig9 a to 9d and fig1 a to 10c illustrate the concepts of the manufacturing process and do not show specific cross sections . first , a box layer 302 , an soi layer 303 a , and an soi layer 303 b are formed over a surface of a substrate 301 of a semiconductor or the like by known semiconductor integrated circuit manufacturing techniques . next , read gates 304 a and 304 b are formed , and an impurity is added to the soi layer 303 a and the soi layer 303 b by using these gates as a mask to form impurity regions 305 a to 305 d . here , the impurity region 305 a corresponds to the back gate of the back gate transistor 108 or the back gate line 111 in fig4 a . the read gates 304 a and 304 b correspond to the gates of the read transistors 119 in fig4 a and 4b . then , a first interlayer insulator 306 is formed and then is planarized to expose top surfaces of the read gates 304 a and 304 b . first layer wirings 307 a to 307 e and a first embedment insulator 308 are formed . subsequently , an oxide semiconductor layer 309 a and an oxide semiconductor layer 309 b are formed , and a gate insulator 310 is formed so as to cover them . then , second layer wirings 311 a to 311 e are formed . the second layer wiring 311 a here corresponds to the gate of the back gate transistor 108 or the bit line controlling line 112 in fig4 a . the second layer wirings 311 c and 311 d correspond to the write word lines 115 in fig4 a and 4b . the second layer wirings 311 b and 311 e correspond to the read word lines 116 in fig4 a and 4b . a second interlayer insulator 312 with a plane surface is formed . then , contact plugs 313 a , 313 b , and 313 c connected to the first layer wirings 307 a , 307 b , and 307 d are formed . third layer wirings 314 a and 314 b are formed . the third layer wirings 314 a and 314 b correspond to the bit line 104 in fig4 a . a third interlayer insulator 315 is formed . any other wirings , interlayer insulators , and the like may additionally be formed . through the aforementioned process , a semiconductor memory device including a back gate transistor 316 , a read transistor 317 , a write transistor 318 , and a capacitor 319 is formed . the back gate transistor 316 corresponds to the back gate transistor 108 in fig4 a . the read transistor 317 , the write transistor 318 , and the capacitor 319 form one memory cell . the read transistor 317 , the write transistor 318 , and the capacitor 319 correspond to the read transistor 119 , the write transistor 118 , and the capacitor 120 in fig4 b , respectively . note that fig1 c illustrates two memory cells ( a memory cell 320 a and a memory cell 320 b ). these memory cells are connected to the same bit line . this application is based on japanese patent application serial no . 2011 - 129685 filed with japan patent office on jun . 10 , 2011 , the entire contents of which are hereby incorporated by reference .