an ofdm subscriber receiver must handle three uncertainties on initial ofdm frame reception . these uncertainties may include a preamble index ( that identifies which preamble is being used ), a signal frequency and a signal time offset in a negative snr environment . in order to demodulate and decode the ofdm data symbols located in a frame , the receiver must shift the sub - carriers to their correct frequencies and commence a demodulation and the decoding process for each symbol . the receiver described herein is assumed to be a digital receiver that can detect a frame pre - amble . upon detection , the digital receive can provide the results of the detection available to digital synchronization circuitry to enable decoding of the received signal . while the present claimed subject matter described herein is based on specific specification , characteristics and techniques based on the 802 . 16 standard , such specifications , characteristics and techniques are used for purposes of illustrating and describing the present invention . while description and drawings herein represent a preferred embodiment of the present invention , it will be understood that various additions , modifications and substitutions may be made to the specifications , characteristics and techniques of the 802 . 16 standard without departing from the spirit and scope of the present invention as defined in the accompanying claims . in particular , it will be clear to those skilled in the art that the present invention may be embodied in other specific forms , preamble formats and structures , data formats and structures , arrangements , proportions , and with other elements , materials , and components , without departing from the spirit or essential characteristics thereof . the presently disclosed embodiments are therefore to be considered in all respects as illustrative and not restrictive , the scope of the invention being indicated by the appended claims , and not limited to the foregoing description . furthermore , it should be noted that the order in which the process is performed may vary without substantially altering the outcome of the process . returning now to fig1 , an ofdm wimax data frame 10 comprises a dl sub frame 14 that includes a predetermined preamble 12 and a ul sub frame 16 . the wimax frame has a total duration of 5 msec , with each symbol having a period duration of about 100 microseconds . the duration between the dl subframe 14 and ul subframe 16 is fixed to about 30 usec , while the duration between the ul subframe 16 and dl subframe 14 is fixed to about 40 usec . the preamble 12 comprises a symbol that has a predetermined duration and number of bits which are defined by the 802 . 16 standard , which is hereby incorporated by reference . preamble 12 is shown having four bits just for illustrative purpose . the actual number of bits of the preamble may be a higher number such as the size defined in the 802 . 16 specification . preamble 12 is illustrated in the frequency domain by 20 . each symbol in wimax frame 10 also includes a cyclic prefix extension 18 that is positioned in time at the beginning and end of the symbol . cyclic prefix extension 18 may be included in frame 10 to preserve the orthogonally of the sub - carriers over the fft processing interval in un - equalized channels . examples of such channels include the wimax multi - path channels . data of one of the symbols is represented in the frequency domain by 22 having multiple bits with random amplitude . the ul sub frame 16 likewise comprises multiple symbols each having a cyclic prefix extension . referring to fig2 , circuit 29 may be used to identify the preamble . circuit 29 comprises an antenna 30 and is coupled with translation circuit 32 . circuit 32 is coupled with cyclic prefix removal circuit 34 and has an output connected to fast fourier transform circuitry 36 . fast fourier transform circuitry 36 provides an output signal that is fed to afdcc ( averaged frequency domain differential correlator ) circuit 38 and frequency domain processing circuit 40 . the ofdm signal may be in the form of a data frame 10 . the ofdm signal may be received by antenna 30 and fed to time domain translation circuit 32 . translation circuit 32 filters the signal ; performs rate conversion and other time domain processing of the signal . the resultant output of translation circuit 32 is fed to cyclic prefix removal circuit 34 . removal circuit 34 removes the cyclic prefix 18 from the resultant output . the output of removal circuit 34 is fed to fast fourier transform circuit 36 to generate a discrete fft signal . the output 48 of circuit 36 may be fed to afdcc circuit 38 and to frequency domain processing circuit 40 . afdcc circuit 38 identifies the location of the preamble , details of which are described in fig3 and 4 , and feeds a signal indicating the location to frame timing control block ( not shown ). frame timing control block receives a number corresponding to the time of the preamble location within a data frame as determined by the afddc circuit 38 . frame timing control block determines a frame time and feeds the resulting location and frame time to time domain translation circuit 32 . circuit 40 may identify , derive and output the data bits embedded in the frame . these data bits may then be stored in a memory of an electronic circuit or a computer for further processing . circuits 36 - 40 may include a one or more processors and memory ( not shown ) or other electronic hardware , or may be coupled with a processor for performing the operations described in fig3 and 4 . the processor may execute instructions stored in any type of computer readable memory , examples may include , but are not limited to , flash memory , hard disk drives , optical disks , semiconductor , ram or rom memory . referring to fig4 , the output 48 of the fft circuit 36 is received in block 50 . output 48 is shown in fig4 as a frame 0 through frame m − 1 ( and labeled as fft out ), where m is the number of frames being sampled to identify the preamble . frame 0 through m − 1 is designated in fig4 as 52 a - 52 m . each of these frames has a symbol 0 through k , designated in fig4 as 52 a s 0 - 52 a sk . in block 54 of fig3 , each of the unknown variables for a hypothesis are generated for the following equation 1 : in this equation the fddc value ( also referred to as the frequency domain differential correlator ) ( fddc ( x , y , z )) is generated for preamble x , with frequency offset y , at symbol z within the frame . plen is a length of the predetermined preamble symbol in bits , stepsize is a difference in fft bins between consecutive bits of the preamble symbol , y 0 is a frequency offset of the fft bin where the first symbol bit is transmitted , and the output of function dp ( x , k ) where , k is bit k of preamble x in differential form , is selected from a group consisting of − 1 or + 1 . in block 56 , each of the hypothesis values determined in block 54 are fed into equation 1 to calculate multiple values for each of the symbols ( such calculation is referred to herein as nhypothesis , where n is the number of different outcomes from a change in the variables calculated using equation 1 ). for example , where n = 1 , a unique value for x ( the preamble index ) and y ( the frequency offset ) is assigned by placing numbers instead of variables into equation 1 . for an exemplary preamble number 0 , the first 5 differential bits may be assigned such that dp ( x = 0 , k = 0 : 4 )=+ 1 ,+ 1 ,− 1 ,+ 1 ,− 1 . when x is known , dp ( x , k ) would represent the known preamble sequence . the results using equation 1 generated for each symbol within a frame , and are referred to as a frequency domain differential correlator ( fddc ), 55 a - 55 m ( fig4 ). the resultant fddc 55 a - 55 m is fed to block 58 . in block 58 , a maximum fddc for each of the nhypothesis for each symbol in a frame is determined by using the formula for the absolute value of fddc , which is defined as the squareroot ( real ^ 2 + imag ^ 2 ) component of the fddc . the average highest fddc may be referred herein to as the afddc ( 57 in fig4 ), or averaged frequency . domain differential correlator . the afddc may be determined using the following equation 2 : x is a specific preamble sequence , x is the range of possible preambles , y is a specific frequency offset for the preamble symbol , and y is a ; range of possible frequency offsets ( also referred to as fft bins ). in block 60 , the complex component for afddc having the maximum value for one symbol in the frame is summed with the fddc complex component for each symbol at a same frame location in consecutive frames of the ofdm signal . ( offset 63 shown in fig4 ) likewise in block 62 , the segment power of the winning hypothesis is summed to enable power normalization in later stage . ( value 61 for n hypo in fig4 ). in block 64 , the absolute value of the combination of ( the sum of the maximum value for each of the nhypothesticals from block 60 divided by the sum of the win segment power from 62 ). the maximum of such absolute value would be the preamble location . for example , in fig4 , such a location is indicated by slot # 0 of set n 2 . one advantage of using the maximum value in consecutive frames to determine the preamble location is that the number of values that has to be stored in memory is reduced by several factors . such maximum value corresponds to the span of z , which is the number of symbols in a frame . by using only the highest fddc value per symbol , at the end of the process one may not be able to determine the preamble index of frequency offset but rather the location or symbol number of the preamble . however , once the preamble location is known , other parameters ( e . g . frequency offset and preamble index ) can easily be determined .