referring to fig3 the graph shown generally represents the control states of the apparatus of this invention compared with the control voltage cvol at the control node 84 according to this invention . trace 404 generally represents the control path with portion 406 representing the part of the control path followed during increasing control voltages or the slow decay of the control voltage node and with portion 408 representing the part of the control path followed during decreasing voltages or fast attack of the control node . in general , during a lock condition , the control voltage is at a level represented by 410 , 4 volts ( also equal to ac ground ). control of the stereo receiver requires no special signal processing during the locked condition . when the control voltage falls below 1 . 5 volts , at level 412 , the circuit switches into the second control state , at which the phase lock loop remains in narrow band width operation , while the frequency detector remains inactive , the stereo light remains enabled , the variable band width low pass and notch filters 102 , 103 , 106 and 107 are active and variable attenuator 104 is active . when the control voltage falls below 1 . 2 volts , level 414 , the third control state is reached in which the phase locked loop 226 is switched to medium frequency band width operation . frequency detector 319 remains inactive and the stereo light ( not shown ) is disabled . when the control voltage falls below 0 . 5 volts , level 416 , the fourth control state is reached , in which phase locked loop 226 is switched to wide frequency band width operation and frequency detector 319 is activated . the stereo light remains disabled . when phase lock loop 226 locks back onto a signal , the control voltage cvol at the control node begins rise . when the control voltage rises to 1 . 2 volts , level 414 , the system changes to the third state at which phase lock loop 226 is switched to the medium band width , the frequency detector is switched off and the stereo light remains disabled . as the control voltage rises to 1 . 5 volts , level 412 , the system changes to the second control state where phase locked loop 226 switches to narrow band width operation , frequency detector 319 remains inactive , the stereo light is enabled , the variable band width low pass and notch filters 102 , 103 , 106 and 107 and blend attenuator 104 are active . as control voltage cvol rises to 4 volts , phase lock loop 226 is in full locked condition and there is no audio processing by phase lock loop 226 or frequency detector 319 to re - attain lock , or by the variable low pass and notch filters 102 , 103 , 106 , and 107 , or attenuator 104 . referring to fig4 trace 418 shows the fast attack - slow decay ( settling ) of this invention as controlled by the control voltage cvol at the control node . typically , when signal lock is lost , the control voltage rapidly decreases ( in a first direction ) through points 420 , 422 and 424 . point 420 corresponds to level 412 in fig3 point 422 corresponds to level 414 and point 424 corresponds to level 416 . in the slow decay ( settling , in a second direction ), point 426 corresponds to level 414 , point 428 corresponds to level 412 and point 432 corresponds to level 410 . referring to fig5 the structure of this invention is shown . audio processing signal control circuit 233 which is shown in more detail in fig2 provides the output through transistor 120 to the control node 84 . transistor 120 is coupled to a 1 . 5 volt supply so that the control circuit 233 is capable of bringing control voltage cvol at node 84 down to the 1 . 5 voltage level and switch the circuit between the control states at level 412 , fig3 . phase lock loop control circuit 402 is shown in more detail in fig6 and described in copending u . s . patent application ser . no . 07 / 954 , 997 , filed on oct . 1 , 1992 referenced above . phase lock loop control circuit 402 includes an out - of - lock detector ( described in detail in application , ser . no . 07 / 954 , 997 ), filed on oct . 1 , 1992 which provides a control signal to transistor 82 , which in turn pulls control node cvol down to zero volts when an out - of - lock condition is detected . thus , through the single control node 84 shown in fig5 the audio processing control circuit can switch the am detector to the second control state at level 412 ( fig3 ), in which the variable band width low pass notch filters are activated and the attenuator is activated to process the signal when less than ideal input signals are received from the antenna 210 . phase locked loop control circuits 402 can pull the system into the third and fourth control states 414 and 416 , in which the band width of phase locked loop 226 is widened to medium or wide band width operation in an attempt to maintain the hold on a locked channel or to re - acquire a lock when the fourth control state is reached and frequency detector 319 is activated . referring to fig6 the circuit comprising resistors 64 , 72 , 76 and 78 , capacitor 66 , comparator 70 and inverter 80 comprise the out - of - lock detector described in the above mentioned copending patent application . lock and band width control circuit 86 has two outputs : lock b , output on line 88 , and wbcon output on line 90 . the lock b signal on line 88 controls whether the i or e signal is coupled to the matrix and audio processing circuitry 233 . the lock b signal also controls whether frequency detector 319 is activated and whether the loop filter 224 is in wide frequency band width operation . when the out - of - lock signal is present on line 88 , the frequency detector 319 is activated and the loop filter is placed in the wide frequency operation . when the wbcon signal is present on line 90 and no out - of - lock signal is present on line 88 , the loop filter is placed in medium frequency band width operation . referring to fig7 the lock and band width control circuit 86 is shown comprising comparators 446 and 452 , resistors 448 and 450 , inverter 454 and nand gate 456 . control node 84 is coupled through buffer 440 to the inverting input of comparator 446 . comparator 446 outputs the signal , lock b on line 88 , which is effectively an inversion of the lock signal output from the lock detector circuit 60 , 62 in fig6 . inverter 454 inverts the lock b signal back to the lock signal and provides the signal to one input of nand gate 456 . the buffered cvol signal is also coupled to the non - inverting input of comparator 452 , of which the inverting input is set to reference voltage equal to 1 . 5 volts by resistors 448 and 450 coupled to a 4 volt reference voltage supply line . the output of comparator 452 is equal to 1 only when the buffered cvol signal is greater than 1 . 5 volts . the output of comparator 452 is coupled to the second input of nand gate 456 . with the circuitry shown , lock and band control circuitry 86 functions as follows . during attack mode , when the voltage cvol at node 84 is decreasing , both the wbcon and lock b signals are zero when the voltage is falling from 4 - 1 . 2 volts . when the voltage falls below 1 . 2 volts , but is still above 0 . 5 volts , wbcon becomes 1 and lock b remains 0 . when the cvol signal falls below 0 . 5 volts , both wbcon and lock b are 1 . during the slow decay when cvol is rising , while the voltage cvol is still below 1 . 2 volts , both wbcon and lock b are 1 . when cvol rises above 1 . 2 volts , but is below 1 . 5 volts , wbcon is 1 and lock b changes to zero . when cvol rises above 1 . 5 volts , both wbcon and lock b are 0 . referring to fig8 a detailed schematic of loop filter 224 is shown including the circuitry necessary for band width control responsive to signals lock b and wbcon on lines 88 and 90 . in general , the signal q provided on line 16 passes through low pass filter 472 having a 1 khz cutoff and is provided to amplifier 482 through resistor 474 . amplifier 482 , with resistor 480 and capacitor 481 , acts as a buffer and provides its output to amplifier 492 , which through resistors 484 , 486 , 490 and 494 and capacitor 488 , filters the signal q providing the output on line 496 to vco 222 . a supply voltage is provided to the circuit through line 478 , coupled to ac ground , which is typically half the integrated circuit supply voltage ( here set at 4 volts ). in the above described circuit operation , loop filter 224 has a narrow band width , desirable during a normal lock condition . when cvol changes such that a wbcon signal is generated on line 90 , inverter 464 , transmission gate 466 and resistor 470 are activated to widen the filter band width of loop filter 224 to the medium band width . when the lock b signal is present on line 88 , inverter 460 , transmission gate 462 and resistor 468 are activated to widen the frequency band width of loop filter 224 to the widest possible frequency band width to enable phase locked loop 226 to re - acquire lock on the signal . the values of the resistors shown and of capacitor 488 can easily be determined by those skilled in the art to implement the desired frequency response of loop filter 224 and will vary from implementation to implementation as system constraints require . referring to fig9 the schematic shown represents a detailed implementation of frequency detector 319 with circuitry including nor gate 500 for interfacing to the lock b signal on line 88 . the signals i and 0 are input to frequency detector 319 from lines 14 and 16 through low pass filters 60 and 472 , respectively . comparators 512 and 514 have their non - inverting inputs coupled to reference voltage level equal to 4 volts , which is the system ac ground . comparators 512 and 514 determine when the filtered q signal is just above and just below ac ground and provide output signals to xor gate 516 , which outputs a signal to nor gate 522 indicative of the zero crossing of the signal q . comparator 508 compares the filtered i signal to ac ground and provides a positive output signal if the filtered i signal is above ac ground . the output of comparator 508 is enabled through transmission gate 510 from signals lock b and proset via inverter 502 and nand gate 500 . nor gate 524 is coupled to nor gate 522 as shown and to one - shot 531 . one - shot 531 outputs the one - shot signal to the clock input ( line 523 ) of flip - flop 521 in response to a detected zero crossing of filtered q output from nand gate 522 . in general , flip - flop 521 changes the &# 34 ; q &# 34 ; output on line 563 when i is positive ( d input to flip - flop 521 ) at the zero crossing of the signal q , enabling phase locked loop 226 to lock in on the if signal with increased speed . frequency detector 319 is disabled when a zero signal is applied to line 88 through nand gate 500 , indicating that phase lock loop 226 is in a locked condition . referring to fig1 , the circuitry for the out - of - lock detector , including comparator 70 , and the circuitry for computer interface control of the cvol voltage is shown . in general , the output of low pass filter 60 ( fig6 ) is coupled to line 58 and provided to one input of comparator 70 . the other input of comparator 70 is coupled to a reference voltage with hysteresis by resistors 72 , 76 and 78 and the output of comparator 70 . the signal output by comparator 70 is inverted by inverter 80 and coupled to control node 84 by transistor 82 , which , when activated , pulls cvol down close to zero volts . the microcomputer interface is provided on line 590 and coupled through inverter 596 to transistor 598 . when activated , the computer interface input controls transistor 598 to pull cvol down to 1 volt , which voltage level is set by resistors 592 and 594 . as set forth above , this invention reduces the number of external capacitors necessary in an integrated am stereo receiver by tying the band width control of phase locked loop 226 to control node 84 and the control voltage cvol across capacitor 126 . this advantageously eliminates the requirement of an additional external capacitor to control phase locked loop 226 as was previously known . in connection with the advantage of a reduced external component count , this invention enables the elimination of an integrated circuit pin due to the elimination of a required connection to an external component . the circuitry blocks discussed above but not shown in detail are straight forward implementations of prior art circuitry well known to those skilled in the art and need not be set forth in detail herein . moreover , the implementations set forth herein are example implementations and alternative embodiments performing the same functions as those embodiments set forth herein that may be achievable by those skilled in the art are considered equivalents . in addition , various improvements and modifications to this invention may be achieved by those skilled in the art and such improvements and modifications will fall within the scope of this invention as set forth below .