the following detailed description sets forth numerous specific details to provide a thorough understanding of the invention . however , those skilled in the art will appreciate that the invention may be practiced without these specific details . in other instances , well - known methods , procedures , components , protocols , algorithms , and circuits have not been described in detail so as not to obscure the invention . fig1 illustrates one embodiment of a network element 10 that may be configured to implement an embodiment of the invention . the invention is not limited to a network element configured as illustrated , however , as the invention may be implemented on a network element configured in many different ways . the discussion of the specific structure and methods of operation of the embodiment illustrated in fig1 is intended only to provide one example of how the invention may be used and implemented in a particular instance . the invention more broadly may be used in connection with any network element configured to handle protocol data units on a communications network . the network element of fig . i may be configured to be used in many different areas of a communication network to handle traffic on the network . as shown in fig1 , a network element 10 generally includes input / output ( i / o ) cards 12 configured to connect to links on the communications network . one example of an i / o card will be described in greater detail below in connection with fig2 . one or more forwarding engines 14 are provided in the network element to process frames received over the i / o cards 12 . the forwarding engines 14 forward the received frames to a switch fabric interface 16 , which passes the frames to a switch fabric 18 . the data may be logically associated into packets , frames , segments , or into another type of protocol data unit . although reception of a frame will be used to illustrate an embodiment of the invention , the invention is not limited in this manner as the network element may similarly operate on any other type of protocol data unit . the switch fabric 18 enables a frame entering on a port on an i / o card 12 to be output at a different port on the same or a different i / o card in a conventional manner . a packet returning from the switch fabric 18 is received by one of the forwarding engines 14 and passed to one or more of the i / o cards 12 . the packet may be handled by the same forwarding engine 14 on both the ingress and egress paths . optionally , where more than one forwarding engine 14 is included in the network element 10 , a given packet may be handled by different forwarding engines on the ingress and egress paths . the invention is not limited to any particular forwarding engine 14 , switch fabric interface 16 , or switch fabric 18 , but rather may be implemented in any suitable network element configured to handle packets from data flows on a network . one or more application specific integrated circuits ( asics ) 20 , 22 and processors 24 , 26 may be provided as well to implement instructions and processes on the forwarding engines 14 . optionally , a memory 28 may be included to store data and instructions for use by the forwarding engines . an interface manager 30 and other control plane components may be provided to establish an environment for creation of interfaces over the ports on the i / o cards , and otherwise control operation of the i / o cards and forwarding engines . the invention is not limited to a particular control plane structure or the manner in which the transport plane , including the i / o cards , forwarding engines , and switch fabric components , are controlled or managed in the network element 10 . fig2 illustrates an example of an i / o card 12 that may be used in the network element of fig1 . as shown in fig2 , the i / o card in this example includes several ports 32 , each of which includes one or more physical interfaces 34 such as an optical port , electrical port , wireless port , infrared port , or ports configured to communicate with other conventional physical media . the port 32 also includes a network processor 36 or other type of configurable logical element to enable the port 32 to operate as a mac ( layer 2 ) port under the direction of the interface manager 30 . for example , the network processor 36 may be configured to perform a service label lookup or an ip lookup on a received packet to determine an egress port for the received packet . the invention is not limited in this manner , however , as other processing may be performed by the network processor 36 . frames received at the port 32 are processed by the network processor 36 and placed in queues 38 in a memory 40 to be output via multiplexer 42 to the remainder of the processing circuitry such as to forwarding engines 14 of the network element 10 . the queues may be formed in shared memory to minimize the number of memory modules that must be used to implement the port 32 . a given port may be required to maintain multiple queues to enable the network element to maintain control over how traffic is handled on the network element . for example , the network element may want traffic to be queued at the ingress port on a per - egress port basis . in this scheme , the ingress port would determine an egress port for an incoming received packet and place the packet in an queue in the shared memory for the particular egress port . queuing packets in the input card on a per egress port basis allows each input port card to output some traffic over a particular egress port in a fair manner and provides sundry other benefits . there are many different queuing strategies that may be employed to enable traffic to be controlled on the ingress and egress ports . for example , packets may be queued on a per input port basis , per flow basis , or in many other ways . the invention is not limited to a particular queuing strategy . additionally , frames may be queued at the egress ports as well as at the ingress ports . these queues may share the same memory 40 with the ingress queues or may be provided with their own memory . queues are used in other contexts within a network element as well . for example , in a network element , data frames are usually transmitted between internal modules using internal data buses . a data bus here may be represented by the communication signals between chips within a same board or between chips on separate boards . whenever a data bus may experience momentary contention , i . e ., periods of time in which there is more data to be sent through the data bus than the data bus can handle , data frames may be queued ( i . e ., stored in memory ) to avoid being dropped . analogously , whenever a data link may experience momentary contention in a data network , data frames may be queued to avoid being dropped . when frames are queued , a queue service policy is required to determine which frame will be served next among all the frames stored in the memory . a simple scheduling policy is to serve frames in first - come - first - served order , where frames are served in the order in which they arrived at the memory . that is , the first stored frame is served first followed by the second stored frame and so on . a data structure designed to provide access to frames in this manner is called a first - in - first - out ( fifo ) queue . as discussed above , if a shared memory is divided into a plurality of physical memories in a rigid fashion , the shared memory may not be fully used since one of the queues may be full while another of the queues may be empty . in this event , a rigidly partitioned shared memory will cause packets destined to a full queue to be dropped , even though the memory as a whole contains empty memory locations and is thus capable of storing additional data words . additionally , this requires the memory to be over - sized to enable sufficient memory space to be allocated to each queue . according to an embodiment of the invention , new queue structures referred to herein as linked lists and interleaved linked lists are used to form the queues 38 in the shared memory 40 to allow the shared memory to be used to store incoming packets or other types of protocol data units in a way that allows the queue size to be adjusted dynamically as required . an example of a conventional algorithm to implement a simple fifo queue using a dual - port memory is depicted in fig3 . to simplify explanation of the concepts associated with the invention , the following discussion will assume that a dual - port shared memory is being used . a dual - port memory has one read port and one write port , where the two ports are independent , i . e ., they have separate data , address , and control signals , and allow for concurrent read and write operations to take place in a same clock cycle of the memory controller . other types of memory , for example single - port memory , can be “ wrapped ” by a control layer that creates the abstraction of a dual - port memory used in this example . thus , a single - port memory can be made to appear as a dual - port memory by running the memory with a clock frequency twice as fast as the clock used for the memory controller , and using odd clock cycles for writes and even clock cycles for reads ( or vice - versa ). in effect , the memory would then allow one write and one read access per clock cycle of the memory controller . the invention is not limited to a particular memory structure or to a particular manner of controlling the memory . the memory can be composed of a single chip or bank , or multiple chips or banks connected in series or parallel . the invention is not limited to a particular type of memory . thus , the invention may be used with static memory , dynamic memory , or memory that is pipelined or not pipelined . where dynamic memory is used , a portion of the clock cycles will be reserved to perform memory refresh operations , which will reduce the throughput of data from the memory . in the following description , it will be assumed that the memory is configured to allow a concurrent enqueue operation ( i . e ., saving of a frame in the fifo ) and dequeue operation ( i . e ., extraction of a frame from the fifo ). while the following description will focus on the handling of frames , the invention is not limited to an embodiment that is configured to handle frames as other types of protocol data units such as packets or segments may be handled as well . fifos that are configured to store data words will be referred to herein as data fifos . in the following discussion , frame delineation will be assumed to be done independently from data word storage , thus a given frame may span multiple data words in the fifo . for example , one way to handle frame delineation is to use a separate size fifo for each data fifo . a size fifo stores the sizes of all the frames stored in its corresponding data fifo , and can be embedded into the data fifo controller or elsewhere in the memory . size fifos provide advance information related to the sizes of the frames stored in the data fifo . this advance size information may be required by certain scheduling policies , e . g ., deficit round robin . another way to handle frame delineation is to increase the memory width of the data fifo to include control bits . these control bits can be used to flag the beginning and end of data frames , and can also be used to indicate which bytes of a memory word contain data . this is useful when the size of a frame in bytes is not a multiple of the number of bytes in a memory word . as frame delineation is handled separately , the rest of the discussion will be restricted to explaining the storing of data words irrespective of frame boundaries . fig3 illustrates a conventional fifo having 28 allocated memory locations . this fifo queue has a defined length which is not easy to modify to allow the queue length to vary depending on the amount of traffic to be input to the queue . in fig3 , the variables head_fifo and tail_fifo can be implemented as hardware registers in a fifo controller . an enqueue operation causes a frame to be written to the fifo , and a dequeue operation causes a frame to be read from the fifo . when an enqueue operation is issued , the provided data word is written to the fifo memory at the position addressed by the content of the tail_fifo register , and the tail_fifo register is incremented by 1 . if the tail_fifo register advances beyond the end of the memory ( in the example this would be indicated by having a new tail_fifo register equal to 28 ), the tail_fifo register is set to 0 ( that is the tail_fifo register is set to the remainder of ( tail_fifo + 1 ) divided by the memory size ). when a dequeue operation is issued , the content of the memory position addressed by the head_fifo register is returned , and the head_fifo register is incremented in the same way as the tail_fifo register . fifo errors such as reading from an empty fifo or writing to a full fifo are easily identifiable and available by comparing the contents of the tail_fifo and head_fifo registers , or by keeping a counter of the number of words stored in the fifo . to avoid such errors , fifos usually provide additional signals to indicate if the fifo is full or empty , has only one data word stored in it , or has only one memory location left to store a data word . these convenience signals are not shown here , but are easy to implement . the invention is not limited to any particular manner of implementing control signals on the memory or to the manner of managing fifos once established . fig4 illustrates an embodiment of the invention in which fifos may be implemented using linked list data structures , so that any given fifo may use any quantity of the shared memory . to enable fifos to share the memory , the area of the memory to be used to implement the fifos is initially reserved as a pool of free memory that can be used by any fifo requiring memory space . when a fifo requires a memory location , the memory location is allocated to the fifo . whenever a fifo releases a memory location , that memory location is returned to the free memory pool . although the invention will be described in connection with fifos , other memory structures may be implemented as well and the invention is not limited to an implementation that uses a fifo memory structure . in the embodiment illustrated in fig4 , both the fifo and the free memory pool of available memory addresses are implemented using a data structure referred to herein as a linked list . in a linked list data structure 44 , each memory location 46 includes a data structure having two fields : a data field 48 , which is used to store a data word to be saved in the fifo , and a pointer field 50 , which is used to address the next memory location belonging to the next memory address in the linked list . a head_fifo register 52 contains the address of the first memory location belonging to the fifo . a tail_fifo register 54 contains the address of the last memory location belonging to the fifo . the data field 48 of the memory location addressed by the content of the tail_fifo register is left “ empty ,” i . e ., it does not contain a data word because it is reserved for the next enqueue operation , as explained below . similarly , the pointer field 50 of the memory location addressed by the content of the tail_fifo register is set to null since the next memory location for the fifo has not been determined . for example , in fig4 , the linked list includes three filled memory locations and an empty memory location . memory location at memory address 15 includes a data word and a pointer to memory address 23 . the memory location at memory address 23 includes a data word and a pointer to memory address 1 . the memory location at memory address 1 includes a data word and a pointer to memory address 5 . the memory location at memory address 5 is empty , and ready for an enqueue operation to write data to the fifo . by obtaining a memory address location and reserving that memory address for a subsequent enqueue operation , the fifo always contains a free memory location to receive a data word when data is received to be stored in the fifo . an empty fifo is shown in fig5 . as shown in fig5 , an empty fifo has the head_fifo register set to the same memory address as the tail_fifo memory address , and the memory location at the memory address is empty to allow the fifo to process a subsequent enqueue operation . fig6 a and 6b illustrate a process of executing an enqueue operation on the fifo of fig5 . as shown in fig6 a and 6b , when an enqueue operation is issued , the data word to be stored in the fifo is written to the data field of the memory location addressed by the content of the tail_fifo register , a free memory address is written to the pointer field of the memory location addressed by the tail_fifo register , and the value of the tail_fifo register is set to the memory address of the memory location that was just written into the pointer field . thus , in the example illustrated in fig6 a - 6b , a data word is written into the data field 48 at memory location 5 , and a new free memory address ( memory location 14 ) is assigned to the fifo and written into the pointer field at memory location 5 . the tail fifo is changed to refer to memory address 14 , to complete the enqueue operation . the memory location at memory address 14 is empty to receive a subsequent data word and new pointer for a subsequent enqueue operation . once a memory location is assigned to a particular fifo , it is no longer a free memory location but rather is allocated to that fifo . note that the actual content of the data and pointer fields of the last memory location of the fifo is not relevant . thus , the memory location may contain old data or the memory location may be erased or set to all zeros or any other information . the figures have illustrated these data fields as being set to “ empty ” and “ null ” but the invention is not limited in this manner as the content of these fields is irrelevant to the fifo . fig7 a - 7b illustrate a process of executing a dequeue operation on a fifo such as the fifo of fig5 . when a dequeue operation is issued , the data field 48 of the memory location addressed by the content of the head_fifo register 52 is returned , and the head_fifo register 52 is set to the value contained in the pointer field 50 at that memory location . the memory location associated with the previous value of the head_fifo register is then returned to the free memory pool to be used by any fifo that requires a free memory location . in a linked list data structure , the integrity of the fifo depends on the pointer values maintained in the pointer fields 50 . thus , if a pointer is damaged , the rest of the linked list is lost , which causes data loss and memory loss . accordingly , it may be advantageous to incorporate a way to detect ( and perhaps recover from ) bit errors occurring in the pointer value . there are many techniques that can be used to detect or correct errors , such as by performing a cyclic redundancy check ( crc ), parity check , or performing forward error correction ( fec ). the invention is not limited to any particular technique of detecting or correcting errors . for example , one simple solution may be to store the binary complement of the pointer value along with the pointer value and compare both values before using the pointer value . this technique allows for the detection of errors and the identification of which bits are in error . the invention is not limited to this embodiment , however . where an error occurs and is not correctable , the fifo will need to be re - initialized thus resulting in a loss of data . since a data plane of a network element is expected to handle data that is arriving at a very high rate of speed , often at up to 10 gigabits per second , to be useful the fifos must be able to be implemented in hardware , since a software implementation using available technology would either be too slow or too expensive to be practicable . to allow an enqueue and dequeue operation to be executed during each clock cycle of the fifo controller , a new free memory location must be provided to the fifo during every clock cycle . specifically , as discussed above , an enqueue operation results in the fifo writing a data word and the memory address of a free memory location to the fifo . thus , an enqueue operation may only be performed each clock cycle if a new free memory location is able to be provided during each clock cycle . assuming this is possible , as discussed in greater detail below , an enqueue operation simply performs one memory write and a tail_fifo register update each clock cycle . a dequeue operation , however , requires that the new head_fifo value be known and transferred to the memory read circuit by the next clock transition . this is very difficult to achieve , if not economically impossible , even for an embedded memory , i . e ., a memory located on the same chip as the fifo controller . specifically , due to memory , logic , and hardware pipeline delays , the data read from a memory is usually available a few clock transitions after the memory read operation is issued . therefore , the dequeue operations will return data with a delay of a few clock cycles . since a dequeue operation requires the head_fifo register to be updated from the value of the pointer , the head_fifo register will not be updated for several clock cycles while the memory executes the read instruction on the previous pointer field of the previous memory location . thus , a simple linked list may take several clock cycles to update the head_fifo register , which precludes a dequeue operation from occurring during every clock cycle . since dequeue operations affect the availability of free memory locations , as the free memory locations are used up , the delay in effecting dequeue operations may affect the ability of the memory to perform enqueue operations as well . according to an embodiment of the invention , multiple linked lists are interleaved to enable dequeue operations to be performed on the memory during every clock cycle . fig8 - 10 illustrate an example of several interleaved linked lists according to an embodiment of the invention . the number of interleaved linked lists may be adjusted depending on the type of memory being used , the number of click cycles it takes to return data from a data read instruction , and other factors . for example , if it takes 8 clock cycles to return the value of a pointer from a data read instruction , 8 linked lists may be interleaved to pipeline the read cycles so that the data may be updated in time to execute a subsequent dequeue operation . the set of linked lists that are interleaved together form a given fifo in the shared memory . thus , a memory having 24 fifos would include 24 sets of interleaved linked lists , each set of interleaved linked lists forming one of the fifos . for example , assume that a dequeue operation in a linked list , as discussed above , takes n clock cycles to complete — that is it takes n clock cycles to update the content of the head_fifo register after executing a read instruction on the pointer field associated with the previous memory location . if a single linked list is used , a dequeue operation may be executed on the memory every n clock cycles . however , if n linked lists are interleaved , and dequeue operations are executed on the n linked lists successively , the head_fifo registers for each of the linked lists may be provided with n clock cycles for their respective head_fifo registers to be updated , before that linked list in the interleaved structure will be required to execute another dequeue operation . assuming transactions may be pipelined in the memory , and that a pipelining implementation has been used such that subsequent linked list dequeue operations may be initiated before the head_fifo register of a previous linked list has been updated , it is possible to execute a dequeue operation on the fifo during each clock cycle . as illustrated in fig8 , each linked list in the interleaved structure has its own head_fifo and tail_fifo registers . where the interleaved linked lists are all empty , the head_fifo and tail_fifo registers for each linked list in the interleaved structure will point to respective memory locations as illustrated in fig1 . this may occur at initialization where all linked lists of a fifo are empty , or where the queues are emptied during a run - time environment . to enable the lists to be dequeued in a particular order , the fifo controller uses a next_dequeue register to maintain an indication of which linked list in the interleaved structure is to be used for the next dequeue operation . initially , this register can point to any linked list . for example , in the embodiment illustrated in fig8 , it will be assumed that the next_dequeue register initially points to linked list 0 . when a dequeue operation is issued , a dequeue operation is performed on that linked list , just as it would have been performed on a linked list not included in an interleaved structure as discussed above in connection with respect to fig7 a and 7b , and a read operation is issued to update the head_fifo_ 0 register with the value of the pointer at the present memory location . the next_dequeue register will also be updated to point to the next linked list , which in this example is linked list 1 . the register next_dequeue can be updated following the sequence of linked lists from 0 to n − 1 and back to 0 , or it can follow any other order , as long as it always uses the same order . by the time a dequeue operation is issued again on the first linked list 0 , the head_fifo_ 0 register will already have been resolved . that is , the interleaving technique is used to allow individual linked lists to complete their dequeue operations and update the head_fifo register before they are required to perform another dequeue operation . therefore , the degree of interleaving , i . e ., n in this example , should be chosen large enough to allow for completion of a dequeue operation before next_dequeue register points again to the same linked list . note that from the point of view of an external circuit making use of the fifo controller , interleaved linked lists are completely unperceivable . in the embodiment illustrated in fig8 , the dequeue sequence will follow the dashed lines 56 . although as mentioned above , the dequeue sequence may follow any desired sequence . since the enqueue and dequeue operations are independent and may take place on different linked lists , the fifo controller also uses a register called next enqueue to indicate the next linked list to be used for enqueue operations . maintaining the enqueue operations independent of the dequeue operations allows the fifo to contract or expand as traffic demands change over time . initially , the next_enqueue register will point to the same linked list as the linked list initially used for next_dequeue register . as enqueue operations are performed , this register will be updated to point to the next successive linked list . the next_dequeue register will follow the same linked list order as the next_enqueue register to allow data to be read from the interleaved linked lists in the same order as it was written to the interleaved linked lists . in the example illustrated in fig8 - 9 , it will be assumed that the next_enqueue is currently assigned to point to linked list 0 . when an enqueue operation is issued , an enqueue operation is performed as described above in connection with fig6 a - 6b , and the next_enqueue register is updated to point to the next linked list following the same sequence that is being used to update the next_dequeue register . in the preceding examples and embodiments , it was assumed that the fifos were able to be supplied with a free memory at every clock cycle . enqueue operations need a constant supply of free memory locations so that an enqueue operation may be performed at every clock cycle . according to an embodiment of the invention , a free pool of memory is also organized as an interleaved linked list . this free memory list will be referred to herein as a free memory fifo ( or free fifo 58 for short ), as opposed to the data fifo 44 , which is used to store the actual fifo data as discussed in greater detail above . fig1 illustrates an embodiment in which the shared memory supports one data fifo 44 and a free fifo 58 , and fig1 illustrates an embodiment in which the memory supports multiple data fifos 44 and a free fifo 58 . since the memory in the examples set forth herein is capable of performing only one dequeue operation and one enqueue operation per clock cycle regardless of the number of data fifos supported by the memory , only one free memory location will be required for each clock cycle . accordingly , only one free fifo will be required per physical memory . where the memory is able to support multiple enqueue operations per clock cycle , multiple free fifos may be used to supply multiple free memory locations per clock cycle . initially , the data fifo will be empty and the free fifo will contain an interleaved linked list of all free memory locations in the memory that are available for use by the fifos on that memory . the data fields at the memory locations of the free fifo are not used and may contain any information , as the data fields will be ignored by the network element . a dequeue operation on a fifo results in the generation of a free memory location . for example , where the memory location is being used by a data fifo , a dequeue operation from the data fifo results in data being read from the memory location and , thus , the memory location becomes a free memory location . according to an embodiment of the invention , after the fifos have been initialized , at every clock transition for which a dequeue operation is not issued on the data fifo , a dequeue operation is issued on the free fifo . as a result , a free memory location is produced at every clock transition ; either by the dequeue operation on the data fifo or the dequeue operation on the free fifo . since there will thus be a free memory location generated at each clock cycle , the free memory location must be used during every clock cycle . according to an embodiment of the invention , if a data fifo enqueue operation is not issued on a clock transition , an enqueue operation is then issued on the free fifo . in this manner , the free memory location may either be used by a data fifo or added back to the free fifo to be made available at a later time . in this manner , at every clock transition in which a data fifo does not undergo a dequeue or enqueue operation , the free memory fifo is concurrently dequeued and enqueued . since a dequeued memory location becomes free only after its data and pointer fields are examined , and memory read operations may take a few clock cycles to complete , free memory locations will be provided only a few clock cycles after the fifo controller is started . accordingly , care must be taken to provide immediate free memory locations during the first few clock cycles after the controller is initiated . those immediate free locations can be reserved , i . e ., kept outside the free memory fifo , to allow the fifo to start smoothly . since a given shared memory may need to support several data fifos , a new linked list may be generated for each data fifo to be added to the shared memory . the memory will support one enqueue and one dequeue operation per clock cycle , although these operations do not need to be on the same data fifo . thus , the manner in which the fifos are created using interleaved linked lists , and the manner in which free memory locations are supplied , does not impose any restriction on the order in which fifos are written or read . for instance , a scheduler can serve one word at a time from different data fifos in a round - robin fashion or it may read consecutive words from a single fifo until a complete frame is served , if desired . the invention is not limited to any particular manner of selecting fifos to be read from a shared memory . the proposed scheme uses all of the available throughput of the memory , i . e ., it can write data to the fifos at the allowed write throughput of the memory and can read data from the fifos also at the allowed read throughput of the memory . for example , if a static memory has a 128 - bit data bus ( i . e ., it is 16 bytes wide ) for the read port and a 128 - bit data bus for the write port and one memory location is read and one memory location is written at every 12 . 8 ns , the memory has a 10 gb / s read throughput and a 10 gb / s write throughput . with this memory , 10 gb / s traffic may pass through the fifos without experiencing congestion . it should be understood that all functional statements made herein describing the functions to be performed by the methods of the invention may be performed by software programs implemented utilizing subroutines and other programming techniques known to those of ordinary skill in the art . the control logic may be implemented as a set of program instructions that are stored in a computer readable memory within the network element and executed on a microprocessor , such as a network processor . however , in this embodiment as with the previous embodiments , it will be apparent to a skilled artisan that all logic described herein can be embodied using discrete components , integrated circuitry , programmable logic used in conjunction with a programmable logic device such as a field programmable gate array ( fpga ) or microprocessor , or any other device including any combination thereof . programmable logic can be fixed temporarily or permanently in a tangible medium such as a read - only memory chip , a computer memory , a disk , or other storage medium . programmable logic can also be fixed in a computer data signal embodied in a carrier wave , allowing the programmable logic to be transmitted over an interface such as a computer bus or communication network . all such embodiments are intended to fall within the scope of the present invention . it should be understood that various changes and modifications of the embodiments shown in the drawings and described in the specification may be made within the spirit and scope of the present invention . accordingly , it is intended that all matter contained in the above description and shown in the accompanying drawings be interpreted in an illustrative and not in a limiting sense . the invention is limited only as defined in the following claims and the equivalents thereto .