the present invention will be described in detail in the following in connection with the embodiments thereof . fig1 ( a ) and 1 ( b ) is a block diagram showing one embodiment of the present invention . generally indicated at reference numeral 1 is a microprocessor which is constructed into a one - chip monolithic semiconductor integrated circuit composed of such respective circuit blocks 2 to 18 as will be described in the following . an accumulator 2 has its data input and output terminals coupled to an internal data bus line bus . an accumulator latching circuit 3 is coupled to the accumulator 2 . a temporary register 4 has its data input and output terminals coupled to the internal data bus line bus . an arithmetic and logic unit 5 is made receptive to the output data of the accumulator latch circuit 3 and the temporary register 4 as its operand . the circuits 2 to 5 thus far described construct together an arithmetic unit and have their respective operations controlled by the control signals which are generated by a timing control circuit 8 . the arithmetic and logic unit 5 has its operation so controlled by the output signal of the timing control circuit 8 as to perform an arithmetic operation such as addition or subtraction or an or , and , exclusive or logical operation . the output data of the arithmetic and logic unit 5 are different in accordance with the control signal , which is generated by the timing control circuit 8 , but are fed out to the accumulator 2 through the internal data bus line bus , for example . an instruction register 6 , an instruction decoder and machine cycle encoder 7 and a timing control circuit 8 construct together a control unit . the instruction register 6 is provided to receive the instruction which is fed to the internal data bus line bus through an external data bus line dt and a data buffer 11 from such as rom ( i . e ., a read only memory ) 19 as is disposed at the outside of the microprocessor 1 . the instruction , which is received by the instruction register 6 , is fed to the circuit 7 so that it is decoded by the instruction decoder in that circuit 7 . the resultant output of the instruction decoder is fed to the machine cycle encoder in the circuit 7 . the machine cycle encoder generates a variety of timing signals which are determined by the output signal of the instruction decoder . the timing control circuit 8 has its operational timing controlled by the clock signals fed from grouped external control terminals cont so that it generates both a bus control signal for receiving the data fed from the external data bus line dt and a strobe signal for writing out the data to the external data bus line dt . moreover , the timing control circuit 8 examines a series of signals such as an interrupt signal fed from the grouped external control terminals , cont a hold signal for holding the operations of the system and a reset signal so that it feeds out a series of signals such as a flag signal indicating the reception of the interruption or a flag signal indicating the reception of the requirement for the hold through the grouped external control terminals in response to those signals examined . a register group 9 is composed , although not shown , of general purpose registers , a stack pointer and a program counter . the general purpose registers of the register group 9 are used for memory operation in addition for handling data ( including double length data ). the stack pointer is used to memorize the return address of a subroutine jump . the program counter is a register for memorizing the address of the instruction to be subsequently read out , and its data are increased one by one each time one instruction is executed except for that the instruction to be fed to the instruction register 6 is the jump instruction . an address decoder 18 is made responsive to the output of the general purpose register of the register group 9 thereby to generate a signal for controlling later - described circuits 15 to 17 . incidentally , the circuits 15 to 17 can be controlled by the general purpose registers of the register group 9 . however , by using the address decoder circuit 18 , as shown , the circuits 15 to 17 can also be controlled even with the use of a small number of the general purpose registers . an address buffer 10 is made receptive to the output signals from the register group 9 thereby to generate an address signal to be fed to the rom 19 , the ram 20 and an interface circuit 21 . a data buffer 11 effects interchanges of the data between the external data bus line dt and the internal data bus line bus . in the embodiment being described , the external terminals p 1 to p 3 of the microprocessor 1 are used as the input terminals for exclusively receiving the analog signals , and the external terminals p 6 to p 7 are used as the input and output terminals for exclusively feeding and receiving the digital signals . on the other hand , the external terminals p 4 and p 5 are used as common terminals for the input of the analog signals and for the input and output of the digital signals . in the present embodiment , although not limited thereto , the external terminal p 4 is fed with the analog signals which are generated by an analog sensor det 4 , and the external terminal p 5 is fed with the digital signals which are generated by a switch sw . the external terminal p 6 is fed with the digital signals which are generated by a digital sensor det 5 . the external terminal p 7 is fed with the digital signals which are used to drive a lamp pl . a digital input output port 12 is connected between the external terminals p 4 to p 7 and the register 15 . whether or not the respective external terminals p 4 to p 7 are used as the digital input terminals or the digital output terminals is determined by the control data which are set in the register 15 . the control data to be fed to the register 15 are fed out of the rom 19 together with the instruction . the input timing of the control data is controlled by the control signal which is fed out of the address buffer 10 in accordance with the execution of the program written in the rom 19 . the register 15 is set with both the digital input data , which are fed through the input output port 12 , and the digital output data which are fed from the internal data bus line bus until it is to be fed to the external terminals p 4 to p 7 . the digital input data , which are set in the register 15 , are written in the ram 20 through the internal data bus line bus and the data buffer 11 . the setting operation of the control data in the register 15 , the setting operation of the digital output data , and the reading operation of the digital input data , which are set in the register 15 , are under the control of the program which is written in advance in the rom 19 . for example , at the timing of writing the digital input data , which are fed to the external terminal p 5 , into the ram 20 , there is fed out of the address decoder 18 the control signal for transferring the set data of the register 15 , which is set to have a value corresponding to the digital input data fed to the external terminal p 5 , to the internal data bus line bus . likewise , at the time of writing the digital input data , which are fed to the external terminal p 6 , into the ram 20 , a control signal similar to the signal for transferring input data from register 15 to the internal bus line bus is fed out of the address decoder 18 . the program for writing the digital input data , which are fed from an element such as the starter switch of an automotive engine , into the ram 20 , is executed for a predetermined time period at the start of the engine . furthermore , the program for writing the digital input data , which for example are fed from the crank angle sensor of the engine , into the ram 20 is executed once for a relatively short period of several milliseconds . in order to use the external terminal p 7 as the output terminal for the digital signals , the rom 19 is written with the program such as the control data presetting program which is executed immediately after the system is fed with the power from a power source . as a result , the input output port 12 is so controlled by the control data set in the register 15 as to transfer the digital output data in the register 15 to the external terminal p 7 . from the address decoder 18 , there is fed a control signal which is used for setting such digital output data in the register 15 as are fed from the circuit 5 to the internal data bus line bus . an analog multiplexer 13 has its input terminals coupled to the corresponding external terminals p 1 to p 5 , respectively , and its output terminal coupled to the input terminal of an a / d converter 14 . the a / d converter 14 is fed with such one of the analog input signals fed to the plural external terminals as is selected by the analog multiplexer 13 . such external terminal of the plural external terminals and such selecting timings thereof as are to be selected by the analog multiplexer 13 are determined by the control signals which are fed out of a control register 17 . the control signals to be set in the control register 17 are fed to the internal data bus line bus through the data buffer 11 from the rom 19 written with the program , and the control signals for setting the control signals in the control register 17 are fed out of the address decoder 18 . the respective input timings of the analog input signals are suitably determined by a program which is written in advance in the rom 19 . for example , the level of the analog input signals to be fed out of a temperature detecting element such as a thermistor is varied at a relatively slow rate . it is , therefore , sufficient that such analog input signals are selected once for a relatively long period . on the contrary , the analog input data to be fed out of a detecting element such as the tachometer of the engine are selected once for a relatively short period . the analog input data thus selected by the analog multiplexer 13 are converted by the a / d converter 14 into digital data signals of several bits . the digital data signals fed from the a / d converter 14 are held in a register 16 . the digital data signals thus held in the register 16 are transferred to the internal data bus line bus by the control of the register 17 with the control signals which are fed from the address decoder 18 . the digital data signals in the internal data bus line bus are written in the ram 20 through the data buffer 11 . in order to receive the analog input signal fed to one of the external terminals , therefore , the group of the programs both for setting the control signals in the control register 17 and for transferring the digital data signals from the register 16 to the internal data bus line bus at the time of the end of the a / d conversion are executed . in the embodiment being described , the terminal p 5 of the common terminals p 4 and p 5 is fed with the digital signals . therefore , the signal fed to the common terminal p 5 is not detected as an analog signal . as a result , the rom 19 is not set with the program for transferring the signal , which is fed to the common terminal p 5 , to the internal data bus line bus through the analog multiplexer 13 , a / d converter 14 and register 16 . in other words , the rom 19 is not written with the instruction of setting the control signals , which select the terminal p 5 , in the control register 17 . the rom 19 is not written with the instruction of transferring the set data having no special meaning from the register 16 to the internal data bus line bus . in the manner thus far described , the a / d converter 14 can be prevented from being unnecessarily operated , and the number of the instructions to be written in the rom 19 can be reduced . incidentally , the signals at the terminal p 5 may be unconditionally set in the register 16 through the analog multiplexer 13 and the a / d converter 14 . even in this case , the terminal p 5 can be prevented from being substantially selected by the fact that the instruction of transferring the data from the register 16 to the internal data bus line bus is not written in the rom 19 . incidentally , when the common terminals p 4 and p 5 are used as the analog signal input terminal or the digital signal input terminal , the input output port 12 is made to exhibit high output impedance characteristics for those terminals p 4 and p 5 . as a result , the analog input signal level or the digital input signal level to be fed to the terminals p 4 and p 5 is prevented from being disturbed by the input output port 12 . the operations and a specific construction of the circuits thus far described will be understood in more detail in view of the following description taken in conjunction with the circuit diagram shown in fig2 . in fig2 the multiplexer 13 is constructed of transfer gate misfets q 16 to q 20 which have their respective gate electrodes coupled to the register 17 . the register 17 is constructed of a latching circuit 17a and a decoder circuit 17b . the latching circuit 17a has its plural input terminals coupled to the internal data bus line bus through transfer gate misfets q 1 to q 3 and its plural output terminals coupled to the plural input terminals of the decoder circuit 17b . the register 17 is set with the signal in the internal data bus line bus by rendering the misfets q 1 to q 3 conductive in response to the output signal of the address decoder 18 . the decoder circuit 17b decodes the signal of the latching circuit 17a thereby to generate a signal for selecting such one from the transmission misfets q 16 to q 20 in the multiplexer 13 as corresponds to the signal received by the latching circuit 17a . as a result , the selecting operations of the multiplexer 13 are executed such that the address signal instructing the latching circuit 17a is fed from the grouped registers 9 to the address decoder 18 and such that the multiplexer selecting data are fed to the internal data bus line bus . the register 16 has its plural input terminals coupled to the plural output terminals of the a / d converter 14 and its plural output terminals coupled to the internal data bus line bus through transmission gate misfets q 4 to q 6 . the transmission gate misfets q 4 to q 6 are rendered conductive when the address signal instructing the register 16 is fed from the grouped registers 9 of fig1 ( b ) to the address decoder 18 . as a result , the a / d conversion signals , which are fed from the a / d converter 14 to the register 16 , are further fed to the internal data bus line bus through the transmission gate misfets q 4 to q 6 . the input output port 12 for receiving and feeding the digital signal is constructed , as shown , of input and output buffer amplifiers 12a and 12b which are to be coupled in a one - to - one relationship to the terminals p 4 to p 7 , respectively . the input buffer amplifier 12a is further constructed of a high input impedance circuit such as an inverter made of a well - known misfet in order that it may not adversely affect the level of the signal fed from either the output buffer amplifier 12b or the external sensor . the output buffer amplifier 12b is constructed of a well - known tri - state circuit which in turn is made of a misfet . the gate signal for controlling the operation of the output buffer amplifier 12b is fed from the latching circuit 15c in the register 15 . if the output signal of the latch circuit 15c is at a high level , for example , the output buffer amplifier 12b is rendered operative so that a digital signal at a high or low level is fed from the output buffer amplifier 12b to the external terminal p 4 . if , on the contrary , the output signal of the latching circuit 15c is at a low level , the output terminal of the output buffer amplifier 12b is rendered to have a high impedance state or a floating state . the register 15 is constructed of a latching circuit 15a , which is receptive of the output signal fed from the input buffer amplifier 12a of the input output port 12 , a latching circuit 15b , which is operative to feed the signal to the input terminal of the output buffer amplifier 12b , and the latching circuit 15c which is operative to feed the gate input signal to the output buffer amplifier 12b , as has been described in the above . although not especially limited , all of the output terminals of the latching circuit 15a , which is provided to correspond to the external terminal p 4 , the input terminal of the latching circuit 15b , and the input terminal of the latching circuit 15c are commonly coupled , as shown , to the one bit line of the internal data bus line bus through transmission gate misfets q 7 , q 8 , and q 9 , respectively . likewise , the input and output terminals of the latching circuits in the register 15 , which are provided to correspond to the external terminal p 5 , are commonly coupled to another bit line through transmission misfets q 10 , q 11 , and q 12 , respectively , whereas the input and output terminals of the latching circuit in the register 15 , which are provided to correspond to the external terminal p 7 , are commonly connected with another bit line through transmission gates misfets q 13 , q 14 , and q 15 , respectively . the transmission gates misfets q 7 to q 15 are fed with the addresses which are selected by the address decoder 18 , respectively . in accordance with the construction thus far described , the analog input converted into a digital signal , and the digital input are made common by the internal data bus line bus . as a result , the reception of the input signals of the two kinds is performed by different address instructions of the registers 16 and 15 . in case the common external terminal p 5 is used as the digital input terminal , as shown in fig1 ( b ), the rom 19 is written with the program containing both the instruction of resetting the latch circuit in the register 15 , which corresponds to the transmission gate misfet q 12 , and the instruction of feeding the digital signal , which is fed to the external terminal p 5 , to the internal data bus line bus through the transmission gate misfet q 10 . in this case , incidentally , the rom 19 is neither written with the instruction of selecting the transmission gate misfet q 11 nor the instruction of selecting the misfet q 20 of the multiplexer 13 . likewise , in case the common external terminal p 4 is used as the analog input terminal , the rom 19 is written with both the instruction of resetting the latch circuit 15c of the register through the transmission misfet q 9 and the instruction of selecting the transmission gate q 19 , of the multiplexer 13 but not with the instruction of selecting the transmission gates q 7 and q 8 . the integrated circuit shown in fig1 ( a ) and 1 ( b ) is used to control the engine although not limited thereto . for this purpose , a thermistor det 1 for detecting the temperature of engine cooling water is connected between the external terminal p 1 of the microprocessor 1 and the grounded point of the circuit , and a load resistor r 1 is connected between that thermistor det 1 and a power source terminal v b . if an element having a negative temperature coefficient is used as the thermistor det 1 , the voltage to be applied to the external terminal p 1 is decreased with the temperature rise of the engine cooling water . likewise , a thermistor det 2 for detecting the sucked air temperature of the engine and a load resistor r 2 therefor are connected with the external terminal p 2 . a suction flow meter det 3 is connected with the external terminal p 3 . the suction flow meter det 3 is constructed , for example , of a resistance member and a sliding contact which is shifted with respect to the resistance member in accordance with the suction flow fate . as a result , that suction flow meter feeds the external terminal p 3 with a voltage according to the suction flow rate . the tachometer of the engine det 4 is connected with the external terminal p 4 . the tachometer det 4 feeds the terminal p 4 with a voltage according to the rpm of the engine . the starter switch sw of the engine is connected with the external terminal p 5 . a crank angle sensor of the engine det 5 is connected with the external terminal p 6 . the sensor det 5 is so constructed as to generate such pulse signals as take a high level when the crank shaft comes to a predetermined angular position , e . g ., of 0 degrees . on the other hand , the external terminal p 7 is used as an output terminal for a warning concerning the engine temperature , for example . the lamp pl is so driven by a buffer circuit 30 which is made receptive of the output of the terminal p 7 that it is lit when the engine temperature reaches an abnormal level . the interface circuit 21 is fed with the control signal from the grouped external terminals cont of the microprocessor 1 , the address signal from an address bus ad and the data from the data bus dt . the interface circuit 21 has a plurality of output lines l 1 and l 4 and contains therein such ( not - shown ) memory circuits as are respectively selected by the address signals of the address bus ad and as have their states determined by the data signals of the data bus dt . the signal of the output line l 1 of the interface circuit 21 is fed through an output buffer circuit 22 to an ignition coil 26 , whereas the signal of the output line l 2 is fed through an output buffer circuit 23 to a solenoid 27 for adjusting the throttle valve in the suction manifold of the engine . on the other hand , the signal of the output line l 3 is fed through an output buffer circuit 24 to an electromagnetic type fuel pump 28 , whereas the signal of the output line l 4 is fed through an output buffer circuit 25 to a relay 29 for driving the starter of the engine . in the embodiment being described , in order to control the engine , the rom 19 is stored with not only the program but also the various interpolation data which are determined by the characteristics of the engine to be controlled . for example , the angle of ignition advance of the ignition plug is determined by not only the rpm of the engine but also the engine characteristics . therefore , the ignition timing data for the rpm of the engine have to be set in advance in the rom 19 . in this instance , the data of the engine characteristics for the ignition timing data are not set in the rom in a manner to correspond to all the rpms of the engine but are set as such interpolation data in the rom as correspond to only several rpms of the engine so that the capacity of the rom can be reduced . likewise , the solenoid for control of the throttle valve is controlled in accordance with the suction temperature , the engine temperature , the rpm of the engine and the engine characteristics . the data of these engine characteristics for controlling the solenoid are set as the interpolation data in the rom . the various engine control data when the engine is practically at its operating condition are prepared by the arithmetic operations of the microprocessor 1 , which is made receptive of the data fed from the various sensors and the various interpolation data written in advance in the rom 19 . referring to fig1 ( a ), when a key switch s o is turned on , the power source voltage is fed from a battery b to a constant voltage circuit 40 so that the power source voltage v b is fed from that constant voltage circuit 40 to the respective circuits . the analog data such as the temperature of the engine cooling water or the suction temperature , which are generated by the thermisters det 1 , det 2 , and the like when the microprocessor 1 becomes operative , are converted in a time - division manner into digital data by the action of the analog to digital converter 14 . the respective digital data thus converted are written through the data bus in the random access memory ram 20 . the fuel pump 28 is rendered operative by the output from the interface circuit 21 . when the starter switch sw is turned on , the relay 29 is rendered operative so that the starter ( not shown ) starts its operation . in order to reduce the capacity of the rom 19 , the data therein concerning the ignition timing , for example , are made to correspond only to the predetermined rpms sampled . as a result , the data of the ignition timing from the tachometer det 4 for any rpm of the engine is processed by the arithmetic operation , in which the interpolation data in the rom 19 for the sampled rpm near any of the engine rpms are corrected in view of any engine rpm above - specified . thus , the practical ignition timing is calculated from the standard ignition timing based upon the output of the crank angle sensor det 5 and from the ignition timing data determined by the arithmetic operations . in accordance with the ignition timing thus calculated , the ignition coil 26 is driven . the interpolation data of the rom 19 for controlling the throttle valve in accordance with the rpm data of the engine , the temperature data of the engine cooling water and the suction temperature data are considered so that the pulse control signals for controlling the throttle valve are generated . by these pulse control signals , the duty ratio of the pulse current of the solenoid 27 to be coupled through the interface circuit 21 is changed . the solenoid 27 has its mean current changed by the duty ratio of the pulse current so that the throttle valve is controlled in accordance with the duty ratio . according to the embodiment thus far described , the various process controls of different requirements , in other words , the various process controls having different numbers of analog signal inputs and digital signal inputs and outputs are made possible by a reduced number of terminals so that the general usability of the various process controls of the microprocessor for controlling the automotive engine or the like can be improved . moreover , the process controls of high quality , i . e ., of high density are also made possible merely by changing a portion of the program even for the change in the system from the digital input to the analog input . the present invention should not be limited to the embodiment thus far described but can be so modified that the port is constructed of such input and output ports as are independent of each other . in this modification , the common use of the terminals is made between the input port and the analog input . even in the case of commonly using the terminals , various modifications can be made such that all of the analog inputs are made common or such that all the digital inputs are made common . moreover , the system construction of the microprocessor can be modified in various manners . still moreover , the system for effecting the various process controls is constructed , generally speaking , of a digital semiconductor integrated circuit of several chips , which is made of a microprocessor , a rom ( or ram ) written with a control program , and a ram for holding various data . therefore , the analog to digital input output circuit containing the a / d converter may be provided , for example , as shown in fig3 in the digital semiconductor integrated circuit 100 constructing with the rom written with the control program . more specifically , the digital semiconductor integrated circuit 100 , which is constructed of the address decoder ram 20 and the memory array 21 written with the program instruction , is similarly provided with the input output port 12 , the register 15 , the multiplexer 13 , the a / d converter 14 and the registers 16 and 17 . with this construction , similar operations can be effected by connecting the data and address buses dt , ad of the digital semiconductor integrated circuit 100 and the microprocessor ( not shown in fig3 ) through the external data and address buses . moreover , in the digital control system containing the ram , the analog to digital input output circuit containing the a / d converter may be provided in the digital semiconductor integrated circuit constructing the ram , and the whole system of the microprocessor , rom and ram may be similar constructed of a one - chip digital semiconductor integrated circuit . while a preferred embodiment has been set forth with specific details , further embodiments , modifications and variations are contemplated according to the broader aspects of the present invention , all as determined by the spirit and scope of the following claims .