hereafter , referring to the drawings , a description will be given of embodiments of the invention . fig1 is a circuit diagram illustrating an overall configuration of a switching power source device according to the embodiment . the switching power source device is configured in such a way that an input direct voltage vi is applied to a series resonant circuit which includes a resonant inductor lr and a resonant capacitor cr , generating a predetermined output voltage v 0 on a load ld via a transformer t . it is also acceptable , not providing any inductance other than the transformer t , to have the current resonant inductor lr as leakage inductance . alternatively , it is also acceptable to provide external inductance other than the transformer t , and configure the current resonant inductor lr as a combination of the external inductance and leakage inductance . mosfets qa and qb are main switch elements which , by switching alternately on a primary side of the transformer t , switch a current path to the series resonant circuit . one extremity of the resonant inductor lr is connected to one extremity of a first coil l 1 of the transformer t , while the other extremity of the first coil l 1 is connected to one extremity of the resonant capacitor cr . a second coil l 2 and a third coil l 3 being mutually connected in series on a secondary side of the transformer t , their connection point is connected to one extremity of an output capacitor c 0 and the load ld . also , the other extremities of the second coil l 2 and third coil l 3 are connected to the other extremity of the ground side of the output capacitor c 0 and load ld via mosfets qs 1 , qs 2 respectively . the mosfets qs 1 , qs 2 being synchronous rectification switch elements which supply the predetermined output voltage v 0 to the load ld by turning on and off secondary currents 11 and 12 , induced from the transformer t , in response to operations of the mosfets qa , qb , the kinds of internal diode ( body diodes , or body diodes and external diodes ) ds to be described hereafter are connected in parallel to each of them . the output voltage v 0 supplied to the load ld is returned to a drive circuit 3 of the mosfets qa , qb via an error amplifier 1 and a voltage control oscillation circuit ( vco ) 2 . at this time , gate signals vga , vgb , which alternately turn on and off in a predetermined timing , are generated in the drive circuit 3 and , by controlling in such a way as to send currents ia , ib of the mosfets qa , qb in the directions of the arrows in a predetermined timing , control a current and voltage flowing in the first coil l 1 of the transformer t , and control the secondary side output voltage v 0 at a constant voltage . the vco 2 functions in such a way that , when determining that due to an output of the error amplifier 1 the output voltage v 0 is higher than a set voltage , or is a light load , it increases an output frequency thereof , while when determining that the output voltage v 0 is lower than the set voltage , or is a heavy load , it reduces the output frequency thereof . in maximum on width control circuits 41 , 42 , in synchronization with an on timing of the mosfets qa , qb , a maximum on width signal tmot which is a maximum on width period h ( a period other than this is low ( l )), for indicating a maximum on width of a predetermined time for which the mosfets qs 1 , qs 2 are mandatorily turned off on exceeding the period , or a maximum on width completion signal tmot 2 which is a signal indicating a completion of the maximum on width , is generated and output to the synchronous rectification mosfets qs 1 , qs 2 . a start of the maximum on width , being indicated by the gate signals vga , vgb to the mosfets qa , qb , is the same as a timing in which the gate signals vga , vgb become h , and the mosfets qa , qb are turned on . then , in synchronous control circuits 51 , 52 , which actually generate synchronous drive signals vgs 1 , vgs 2 of the synchronous rectification mosfets qs 1 , qs 2 , a timing of the mosfets qs 1 , qs 2 being turned on is decided synchronized with a timing indicating the start of the maximum on width ( that is , a timing of the maximum on width signal tmot changing from l to h ), or a timing of a conduction of the internal diodes ds detected by drain - to - source voltages vds 1 and vds 2 of the mosfets qs 1 , qs 2 , whichever timing is later , and furthermore , a timing of the mosfets qs 1 , qs 2 being turned off is decided synchronized with an off timing of the mosfets qa , qb , or a timing of indicating the completion of the maximum on width , whichever timing is earlier . next , a description will be given of a control circuit ( a switching power source control circuit ) of the switching power source device shown in fig1 . fig2 is a circuit diagram illustrating a maximum on width control circuit and synchronous control circuit of the switching power source device . herein , the synchronous control circuit 5 is illustrated representing either one of the synchronous control circuits 51 , 52 . also , with regard to the maximum on width control circuits 41 and 42 , by configuring them of a one - shot multivibrator which adjusts its pulse width by means of an external part connected to an mot terminal , the maximum on width control circuits 41 , 42 can realize an embodiment which outputs the maximum on width signal tmot , and this is taken as a first embodiment . however , as the one - shot multivibrator itself is commonly known , any further description relating to the first embodiment will be omitted . herein , a description will be given of a second embodiment realized by the maximum on width control circuit 4 which operates in conformity with the first embodiment . the maximum on width control circuit 4 illustrated in fig2 is illustrated representing either one of the maximum on width control circuits 41 or 42 . also , in the case of realizing the maximum on width control circuits 41 , 42 with a one - shot multivibrator too , it is possible to use the same synchronous control circuit 5 . also , the internal diodes ds are connected in parallel to a drain - to - source of a synchronous rectification mosfet qs , which controls a secondary current is of either one of the second coil l 2 or third coil l 3 ( described as ls in fig2 ) on the secondary side of the transformer t . the maximum on width control circuit 4 includes a gate signal input terminal 4 a , to which either one of the gate signals vga or vgb ( hereafter described simply as a gate signal vgp ) is supplied from the drive circuit 3 shown in fig1 , and an mot terminal 4 b , to which is connected an external part for adjusting the size of the maximum on width ( corresponding to the pulse width of the maximum on width signal tmot , which is the output of the one - shot multivibrator when using the one - shot multivibrator ). the maximum on width control circuit 4 is a circuit which , rather than outputting the maximum on width signal tmot itself , outputs the maximum on width completion signal tmot 2 indicating the timing of the completion of the maximum on width . the maximum on width control circuit 4 is configured of an inverter 43 connected to the gate signal input terminal 4 a , a constant current source 44 connected to a power source voltage vdd , a capacitor c 1 , of which one extremity is connected to the constant current source 44 and the other extremity is grounded , a switch s 1 , which is on - off controlled by the inverter 43 in such a way as to control a charge and discharge of the capacitor c 1 , and a comparator 45 which compares a charging voltage to the capacitor c 1 with a reference voltage ref 1 . in the maximum on width control circuit 4 , on the switch s 1 being turned off by the gate signal vgp of the gate signal input terminal 4 a , the current from the constant current source 44 starts to charge the capacitor c 1 . then , in a timing in which the voltage of an inverting input terminal (−) of the comparator 45 exceeds the reference voltage ref 1 to a non - inverting input terminal (+), the maximum on width completion signal tmot 2 , which is the output of the comparator 45 , reverses from h ( high ) to l ( low ), and communicates the completion of the maximum on width to the synchronous control circuit 5 . on the maximum on width completion signal tmot 2 becoming l , the output of a negative and ( nand ) circuit 54 of the synchronous control circuit 5 becomes h , resetting a flip - flop circuit 55 . subsequently , on the switch s 1 being turned on by the gate signal vgp , the capacitor c 1 is discharged , and the maximum on width completion signal tmot 2 becomes h . the start of the maximum on width signal tmot being in the timing in which the gate signal vgp becomes h , as heretofore described , the gate signal vgp is input into the nand circuit 54 connected to a reset terminal of the flip - flop circuit 55 , by which means the maximum on width control circuit 4 of the second embodiment can indicate the start of the maximum on width ( the completion of the resetting of the flip - flop circuit 55 ). consequently , in the second embodiment too , it is possible to indicate the same timing for the start and completion of the maximum on width as with the maximum on width signal tmot when using the one - shot multivibrator of the first embodiment , because of which it is possible to set a maximum on width having an optimum on width . a resistor , a capacitor , or the like is connected to the mot terminal 4 b for adjusting the output timing of the maximum on width completion signal tmot 2 , output from the comparator 45 , in accordance with a resonance frequency fr 1 . in the case of connecting a resistor , the current from the constant current source 44 is split by the resistor , and it is possible to delay the output timing of the maximum on width completion signal tmot 2 in accordance with a resistance value of the resistor . also , in the case of connecting a capacitor , it is equivalent to a capacity value of the capacitor c 1 increasing , because of which it is possible to delay the output timing of the maximum on width completion signal tmot 2 . herein , as a logical product ( a negative thereof ) of the gate signal vgp and maximum on width completion signal tmot 2 is taken in the nand circuit 54 , the flip - flop circuit 55 is reset in either the timing in which the maximum on width completion signal tmot 2 becomes l , or the timing in which the on period of the gate signal vgp is completed , and the gate signal vgp becomes l , whichever is earlier . the synchronous control circuit 5 is a circuit which , including a signal input terminal 5 a to which is supplied a very light load condition signal vll which becomes h when a very light load is detected by a circuit ( not shown ), and furthermore , to which are supplied the drain - to - source voltage vds from the synchronous rectification mosfet qs , the maximum on width signal tmot or the maximum on width completion signal tmot 2 output from the maximum on width control circuit 4 , and the gate signal vgp which on - off controls the mosfets qa , qb , controls an on period of the mosfet qs by outputting the synchronous drive signal vgs . the synchronous control circuit 5 is configured of a comparator 53 which , based on a reference voltage ref 2 , outputs a level detection signal vdsc from the drain - to - source voltage vds , the nand circuit 54 , which computes nand signals of the maximum on width signal tmot and gate signal vgp , the flip - flop circuit 55 , in which the level detection signal vdsc of the comparator 53 and the nand signals of the nand circuit 54 are supplied to a set terminal s and a reset terminal r respectively , and an and circuit 57 , into which are input a q output signal of the flip - flop circuit 55 , and a signal which is the very light load condition signal vll to the signal input terminal 5 a inverted by an inverter 56 . in the synchronous control circuit 5 , an inverting input terminal (−) of the comparator 53 , as well as being grounded via a zener diode zd , is connected to the power source voltage vdd via a resistor r 1 , and furthermore , is connected to a drain terminal of the synchronous rectification mosfet qs via a resistor r 2 . the reference voltage ref 2 of the comparator 53 is applied to a non - inverting input terminal (+). now , taking the power source voltage vdd to be a , and a threshold value voltage ( vds_th ) which is the mosfet qs drain - to - source voltage vds when the level detection signal vdsc , which is the output of the comparator 53 , inverts to be x , as the two inputs of the comparator 53 are equal when vds = x , the following expression holds true . the above mentioned threshold value voltage ( vds_th ) is different from a threshold value relating to an on - off of the mosfet qs . consequently , the mosfet qs drain - to - source voltage threshold value voltage ( vds_th ) when the level detection signal vdsc inverts is , when the drain - to - source voltage vds exceeds ( vds_th ) ( strictly speaking , when both are negative values , and an absolute value of vds is greater than an absolute value of ( vds_th )), the level detection signal vdsc , which is the output of the comparator 53 , inverts from l to h . incidentally , in a condition in which no current is flowing in the drain - to - source , the value of the drain - to - source voltage vds is positive , and the level detection signal vdsc is l . while the level detection signal vdsc of the drain - to - source voltage vds is supplied as a set signal of the flip - flop circuit 55 , an output signal of the nand circuit 54 , into which are input the gate signal vgp , and the maximum on width signal tmot or maximum on width completion signal tmot 2 , is taken to be a reset signal of the flip - flop circuit 55 . also , the q output signal of the flip - flop circuit 55 being supplied to the and circuit 57 along with the inverted very light load condition signal vll output from the inverter 56 , the output signal is taken to be the gate drive signal vgs of the synchronous rectification mosfet qs . the flip - flop circuit 55 is a reset prioritizing circuit . that is , when the gate signal vgp is in the l condition before indicating the start of the maximum on width , it is not possible to set the flip - flop circuit 55 , even in the event that the drain - to - source voltage vds exceeds ( vds_th ). because of this , it is possible to prevent a malfunction which may occur in a dead time set in the primary side gate signals vga , vgb . next , a description will be given of a control method of the switching power source device . fig3 is a timing diagram illustrating a secondary side current control operation by the synchronous control circuit of fig2 . herein , a description is given of a case in which the maximum on width control circuits 41 , 42 are realized with a one - shot multvibrator . in ( a ) of fig3 , the gate signal vgp from the drive circuit 3 shown in fig1 is shown for six operational modes , modes 1 to 6 , lined along the same time axis . ( b ) of fig3 shows the secondary current is flowing in the synchronous rectification mosfet qs compared with an absolute value (| vds_th |) of the mosfet qs drain - to - source voltage when the level detection signal vdsc inverts converted into a current by dividing by an on resistance ron of the mosfet qs . also , the threshold value voltage vds_th can be calculated using the heretofore described expression 5 . alternatively , it is also possible to decide the voltage vds_th first , and adjust other parameters using the expression 5 . in ( c ) of fig3 , a waveform of the level detection signal vdcs is shown . the | vds_th |/ ron shown in ( b ) of fig3 shows a level of the secondary current is for which the level detection signal vdsc output from the comparator 53 is h . also , ( d ) of fig3 is the maximum on width signal tmot , ( e ) of fig3 the very light load condition signal vll , and ( f ) of fig3 the synchronous drive signal vgs output from the synchronous control circuit 5 . in the first operational mode ( mode 1 ), the synchronous drive signal vgs turns off the mosfet qs in synchronization with the timing in which the gate signal vgp is turned off , or the timing in which the maximum on width signal tmot indicates off , whichever timing is earlier . for this reason , it is possible to reliably prevent a reverse flow in a range a which has heretofore occurred in a latter half of a half cycle ( top / 2 ) of a switching operation . in the second and fifth operational modes ( modes 2 and 5 ), the synchronous drive signal vgs turning - on the mosfet qs in synchronization with the timing in which the maximum on width signal tmot indicates on , or the timing in which the conduction of the internal diodes ds detected by the level detection signal vdsc of the drain - to - source voltage vds , whichever timing is later , it is also possible to reliably prevent a reverse flow in a range b ( fig3 ) or a range d ( fig3 ) which has heretofore occurred in a first half of a half cycle ( top / 2 ) of the switching operation . also , once the mosfet qs has been turned on , a fluctuation of the drain - to - source voltage vds is ignored . consequently , there is no occurrence of the phenomenon seen in the configuration of patent document 2 wherein a high frequency oscillation is invariably repeated every time the secondary current is decreases to zero . also , as the very light load condition of the load ld is detected by the very light load condition signal vll , the synchronous drive signal vgs is not output from the synchronous control circuit 5 in the third and sixth operational modes ( modes 3 and 6 ). for this reason , the mosfet qs not being turned on in the very light load condition , it is also possible to reliably prevent a reverse flow which has heretofore occurred in a range c ( fig3 ) or a range e ( fig3 ). the very light load condition signal vll has been defined as a case in which the load ld actually connected is 20 % or less of a rated load ( maximum load ) of the switching power source device , but the setting of this ratio can be changed as appropriate . as heretofore described , as it is possible to supply the synchronous drive signal vgs to the synchronous rectification mosfet qs with the kind of timing shown in fig3 , a stable synchronous rectification function is realized , with no reverse current occurring , in the case of any of the first to sixth operational modes . in the heretofore described embodiments , a description is given of a half bridge type of switching power source device , but the invention is also applicable to a full bridge type of switching power source device or switching power source control circuit , and to a control method of the full bridge type of switching power source device . fig4 is a circuit diagram illustrating an overall configuration of the full bridge type of switching power source device . in the full bridge type of switching power source device shown in fig4 , the gate signals vga , vgb , which alternately turn on and off in a predetermined timing , are generated in the drive circuit 3 , and a first main switch element group of mosfets qa 1 , qa 2 and second main switch element group of mosfets qb 1 , qb 2 are alternately switched by the gate signals vga , vgb on the primary side of the transformer t . a current ia flowing in the direction of the arrow in the timing in which the first main switch element group of mosfets qa 1 , qa 2 is turned on , and a current ib flowing in the direction of the arrow in the timing in which the second main switch element group of mosfets qb 1 , qb 2 is turned on , in each case the input direct voltage vi is applied to the series resonant circuit which includes the resonant inductor lr and resonant capacitor cr . on the secondary side of the transformer t , the mosfets qs 1 , qs 2 , acting as synchronous rectification switch elements , supply the predetermined output voltage v 0 to the load ld by turning on and off the secondary currents 11 , 12 , induced from the transformer t , in response to operations of the first main switch element group of mosfets qa 1 , qa 2 , or of the second main switch element group of mosfets qb 1 , qb 2 . in the maximum on width control circuits 41 , 42 , in synchronization with an on timing of the first main switch element group or second main switch element group of mosfets qa 1 , qa 2 , qb 1 , and qb 2 , the maximum on width signal tmot which is the maximum on width period h ( a period other than this is low ( l )), for indicating the maximum on width of the predetermined time for which the mosfets qs 1 , qs 2 are mandatorily turned off on exceeding the period , or the maximum on width completion signal tmot 2 which is a signal indicating the completion of the maximum on width , is generated and output to the synchronous rectification mosfets qs 1 , qs 2 . herein too , the start of the maximum on width , being indicated by the gate signals vga , vgb to the mosfets qa 1 , qa 2 , qb 1 , and qb 2 , is the same as the timing in which the gate signals vga , vgb become h , and the mosfets qa 1 , qa 2 , qb 1 , and qb 2 are turned on . then , in the synchronous control circuits 51 , 52 , which actually generate the synchronous drive signals vgs 1 , vgs 2 of the synchronous rectification mosfets qs 1 , qs 2 , the timing of the mosfets qs 1 , qs 2 being turned on is decided synchronized with the timing indicating the start of the maximum on width ( that is , the timing of the maximum on width signal tmot changing from l to h ), or a timing of the conduction of the internal diodes ds detected by the drain - to - source voltages vds 1 , vds 2 of the mosfets qs 1 , qs 2 , whichever timing is later , and furthermore , the timing of the mosfets qs 1 , qs 2 being turned off is decided synchronized with the off timing of the mosfets qa 1 , qa 2 , qb 1 , and qb 2 , or the timing of indicating the completion of the maximum on width , whichever timing is earlier . the switching power source control circuit and the control method thereof being the same as in the case of the half bridge type of switching power source device , their descriptions will be omitted . the disclosure of japanese patent application no . 2009 - 132333 . filed on jun . 1 , 2009 is incorporated as a reference . while the invention has been explained with reference to the specific embodiments of the invention , the explanation is illustrative and the invention is limited only by the appended claims .