referring to fig1 computer system 10 runs programs enabling a user to view a video stream . the computer system 10 includes a digital computer 12 ( such as a personal computer or a work station ), a display 14 to display a video picture 46 , speakers 16 , a mass storage device 18 ( such as a floppy disc drive , a hard disc drive , a cd - rom drive , or a magneto - optical disc drive ), a keyboard 20 , and a mouse 22 or other pointer device ( such as an input tablet ). the computer 12 is of conventional construction and includes a memory 24 , a microprocessor 25 , and other customary components , such as a memory bus and a peripheral bus ( not shown ). the computer 12 includes a decoder 30 for decoding or decompressing a video signal . the computer 12 also includes communications hardware and programs ( not shown ) by which the computer system 10 is connected by a communications link 26 to a video source 28 . programs often access a series of consecutive memory addresses . dram chips may be configured to operate in a &# 34 ; page mode &# 34 ; to take advantage of the sequential nature of program execution . in page mode dram , the dram chip compares the row of the most recently retrieved memory address to the row of the memory address currently being retrieved . if the new address is in a new page ( accessing a new page is called a &# 34 ; page crossing &# 34 ;), the dram proceeds in the traditional fashion . however , if the new address is in the same page , the dram chip immediately identifies the new column and skips the ras / cas delay . therefore , so long as the dram chip is accessing memory locations in the same page , the dram chip can skip the ras / cas delay , thereby significantly increasing the speed of the memory . in addition , the dram chip can wait until a page crossing and then recharge the entire row . this permits the dram chip to avoid the precharge delay until a page crossing occurs . in addition , dram chips may be configured with an interleaved memory architecture . in an interleaved memory architecture , the memory is broken into two banks . while the computer is accessing memory locations in one bank , the other bank is being recharged . assuming that the dram chip is operating in a page mode , and assuming that the new page is in a different bank , then the previously accessed page ( in the first bank ) can be recharged while the new page ( in the second bank ) is being read . this permits the dram chip to &# 34 ; hide &# 34 ; the precharge delay at the page crossing . however , if the computer reads from a different page in the same bank , then the memory must wait for the precharge delay . referring to fig2 memory 24 is a synchronous dynamic random access memory ( sdram ) which is of sufficient size to store a field or frame of a video image . the memory 24 is configured using an interleaved memory architecture with two banks 34 and 36 , referred to respectively as bank a and bank b ( bank b is shown as shaded in fig2 for clarity ). in addition , the memory 24 is configured to operate in a page mode with a plurality of pages 38 . the even pages are stored in bank a and the odd pages are stored in bank b . preferably , the memory 24 uses words with a length which is a multiple of 16 bits . typically , a 16 - mbit memory chip uses 16 - bit words , whereas a 32 - mbit memory chip uses 32 - bit words , although this is not required . in addition , the memory 24 may constitute a single chip or multiple chips in parallel , and may include more than two banks . for example , the memory may be a 64 - mbit memory chip configured with 16 - bit words and four banks . preferably , each page in the memory 24 stores 256 words . thus , in a 16 - mbit memory chip using 16 - bit words , each page stores 512 bytes , whereas in a 32 - mbit memory chip using 32 - bit words , each page stores 1 , 024 bytes . as previously discussed , an advantage of the interleaved memory architecture of memory 24 is the ability to hide precharge delays . specifically , as the computer is reading from bank b , the memory locations in bank a are being recharged . the number of memory addresses read consecutively from the same page is called the &# 34 ; burst size &# 34 ;, because precharging requires a significant period of time , a minimum burst size is needed to completely hide the precharge delay at a page crossing . in currently available sdram chips , precharging requires about nine cycles . since one address may be read per cycle , about nine addresses must be read consecutively within the same page in order to completely avoid the precharge delay . thus there is a minimum burst size of nine memory addresses to entirely hide precharge delay . as previously discussed , if the computer must read from different pages in the same bank , then the memory 24 must wait for the precharge delay , and the advantage of the interleaved memory structure is lost . however , if the computer alternates between reading from bank a and bank b , then ( assuming that the minimum burst size is met ) the precharge delay will be entirely avoided . returning to fig1 a decoder 30 is provided to decode or decompress a video signal and to display the resulting video stream on the display 14 . the decoder 30 may also extract audio information from the video signal and play the resulting audio signal on the speakers 16 . as described in detail below , the decoder 30 uses the memory 24 to store previously decoded and decompressed video pictures . the decoder 30 may be implemented as software , firmware , or hardware , or a combination of software , firmware and hardware . the video signal may originate from the memory 24 , from the mass storage device 18 , or from the video source 28 . the video source 28 may be a broadcast signal or a consumer electronics device which has been configured to transmit an encoded or compressed video signal , such as a video camera , a laser disc player or a video cassette player . alternatively , the video source can be a device connected to an external computer system . for example , the decoder 30 may cooperate with a browser program and the computer system 10 may be coupled via the link 26 through the internet to a computer which runs server software . in the implementation described below , the video signal is encoded in the mpeg - 2 standard . however , the invention may also be applicable to video signals using other standards , such as mpeg - 1 . many of the details described are specific to the implementation , and can be changed as is known by those skilled in the art if other standards are used . referring to fig3 a video picture 46 to be displayed is divided into rows 40 of macroblocks 42 . in the mpeg - 2 standard , each macroblock 42 is sixteen pixels wide and sixteen lines high . in a ccir 601 compliant video signal , the video picture 46 is 720 pixels wide . thus , in the mpeg - 2 standard of a ccir 601 compliant video signal , there are forty - five macroblocks 42 in each of the rows 40 . the number of lines in the video picture is preferably a multiple of 16 . in a phase - alternation line ( pal ) video signal , the video picture 46 may be either a 576 line frame or a 288 line field , whereas in an national television systems committee ( ntsc ) video signal , the video picture 46 may be 480 line frame or a 240 line field . assuming that each pixel in the video picture 46 requires one byte , each macroblock 42 will occupy 256 bytes of memory . thus , if the memory is a 16 - mbit chip with each page storing 256 16 - bit words , two macroblocks 42 can be stored in each page . similarly , if the memory is a 32 - mbit chip with each page storing 256 32 - bit words , four macroblocks 42 can be stored in each of the pages . referring to fig4 the distribution of the video picture 46 in a memory using 16 - bit words is shown schematically . specifically , the video picture 46 ( see also fig1 ) is divided into macroblocks , and two consecutive macroblocks ( e . g ., macroblocks 42a and 42b ) are stored in each page ( e . g ., page 38 - 0 ) of the memory . in this configuration the data representing a complete line of pixels across the video picture is stored as a portion of each page rather than as a series of sequential addresses . when the video picture is stored in the memory using this storage scheme , the macroblocks stored in bank a and bank b ( shown as shaded ) become aligned in a skew direction ( represented in fig4 by a dotted arrow 50 ). a group of contiguous macroblocks stored in the same bank define the skew direction 50 . in a memory using 16 - bit words the skew direction 50 is from the upper right to the lower left . as discussed above , because the video picture 46 is 720 pixels across and each macroblock is sixteen pixels across , each row contains forty - five macroblocks . because each page of a 16 - bit word memory stores two macroblocks , a single row , such as row 40a , requires twenty - two and one - half pages of memory . consequently , the twenty - third page 38 - 22 stores a first macroblock 42c in the first row 40a and a second macroblock 42d in a second row 40b . since each row creates an offset of one - half page , the location of each bank will be offset by one macroblock per row , resulting in the skew direction 50 . as previously discussed , the mpeg standards use motion compensation to encode and decode the video stream . the encoded video stream will include a flag or switch for each macroblock indicating the type of decoding to be used to reconstruct that macroblock . the types of decoding include : intracoding , in which a macroblock is constructed without motion compensation ; forward prediction , in which a macroblock uses a previous picture as a reference ; backward prediction , in which a macroblock uses the next picture as a reference ; and bi - directional prediction , in which macroblock uses both the previous picture and next picture as references . returning to fig3 assuming an encoded macroblock 44 in an encoded video picture 32 is to be decoded with prediction , a reference macroblock 60 must be fetched from the reference video picture 46 stored in the memory . in the mpeg - 1 standard , the reference macroblock is a sixteen pixel by a sixteen line square , whereas in the mpeg - 2 standard , the reference macroblock is a sixteen pixel by eight - line rectangle . for each macroblock 44 , the video signal 32 includes a motion vector 48 and error terms ( not shown ). the motion vector 48 points from the macroblock 44 being decoded to the position of the reference macroblock 60 in reference picture 46 . to decode the macroblock 44 , the decoder fetches the reference macroblock 60 from the memory . then the reference macroblock 60 is combined with the error terms to generate the decoded macroblock 44 . referring to fig4 and 5a , the reference macroblock 60 includes three portions : an upper left portion 61 , an upper right portion 62 and a lower portion 63 . the upper left portion 61 overlies a section of a macroblock stored in page 38 - 0 ; the upper right portion 62 overlies a section of a macroblock stored in page 38 - 1 ; and the lower portion 63 overlies sections of two macroblocks 63a and 63b stored in page 38 - 23 . the upper right portion 62 and the lower portion 63 are stored in the bank b , whereas the upper - left portion 61 is stored in bank a . when the video decoder fetches the reference macroblock 60 from the 16 - mbit memory , it will scan the portions 61 - 63 in the following order : either upper right portion 62 , upper left portion 61 , lower portion 63 ; or lower portion 63 , upper left portion 61 , upper right portion 62 . that is , the decoder will scan the portions by either decreasing the page within the same row and then increasing the row , or by decreasing the row and then increasing the page within the same row . in both sequences , the upper left portion 61 is the second portion read in the sequence . in addition , a line 64 connecting the upper left portion 61 to its diagonally opposed macroblock 63b in lower portion 63 is generally perpendicular to the skew direction 50 . referring to fig6 a , to scan the reference macroblock 60 , the decoder starts with a pixel 100 located in the upper left corner of the upper right portion 62 . the decoder then scans rightwardly , reading each pixel in a line 102 within the portion 62 . at the end of the line 102 , the decoder jumps to the beginning of the next line 104 . thus , the decoder scans the portion 62 from left to right and from top to bottom . referring to fig7 each line of pixels in the two adjacent macroblocks stored in a single page is located at a series of contiguous addresses in the memory 24 . since each macroblock is sixteen pixels wide , a single line of pixels crossing two macroblocks is thirty - two pixels long and requires thirty - two consecutive bytes in the memory 24 . similarly , each line across the two adjacent macroblocks is stored consecutively in the memory 24 . thus , when the decoder advances from line 102 to line 104 , it merely advances to a new address in the same page of memory . this memory configuration increases the number of memory locations consecutively accessed from the same bank and thereby permits the decoder to effectively use the page mode of sdram . returning to fig6 a , once the decoder reads the last pixel 106 in the lower right corner of the upper right portion 62 of the reference macroblock 60 , the decoder jumps to a pixel 110 in the upper left hand corner of the upper left portion 61 of the reference macroblock 60 . the decoder then scans each line in the upper right portion 61 from left to right and from top to bottom . once the upper left portion 61 has been scanned , the decoder jumps to a pixel 120 in the upper left hand corner of the lower portion 63 of the reference macroblock 60 . by scanning all the pixels in portion 62 , then all the pixels in portion 61 , and then all the pixels in portion 63 , the decoder scans first from bank b , then from bank a , and then again from bank b . thus , each page crossing results in a switch to an alternate bank . because the scanning sequence alternates between banks , one bank can be recharged while the other bank is being read . therefore , the scanning sequence permits the decoder to take advantage of the interleaved memory structure of the sdram to hide precharges . in addition , the scanning sequence ensures that all of the memory locations in one page are read before proceeding to the next page . this maximizes the number of memory locations read in a single burst , and increases the likelihood of exceeding the minimum burst size . the scanning sequence may be controlled by software , firmware , or hardware , or a combination of software , firmware and hardware . the processor 25 may be configured to perform the scanning sequence . referring to fig6 b , in the second sequence , the decoder starts at the pixel 120 in the upper left hand corner of the lower portion 63 . when the decoder has completed scanning the lower portion 63 , it jumps to the pixel 110 located in the upper left hand corner of the upper left portion 61 . finally , when the decoder has completed scanning the upper left portion 61 , it jumps to the pixel 100 in the upper left hand corner of the upper right portion 62 . this scanning sequence has the same advantages as the sequence described with reference to fig6 a . referring to fig4 and 5b , the decoder may fetch a second reference macroblock 65 from a different position in the reference picture 46 . the reference macroblock 65 includes an upper portion 66 , a lower left portion 67 , and a lower right portion 68 . the first portion 66 overlies two macroblocks stored in page 38 - 1 ; the lower left portion 67 overlies a section of a macroblock stored in page 38 - 23 ; and the lower right portion 68 overlies a section of a macroblock stored in page 38 - 24 . the upper portion 66 and the lower left portion 67 are stored in bank b , whereas the lower right portion 68 is stored in bank a . the decoder will scan the portions 66 - 68 in the following order : either upper portion 66 , lower right portion 68 , lower left portion 67 ; or lower left portion 67 , lower right portion 68 , upper portion 66 . thus , the decoder will either increase the page within the same row and then decrease a row or increase a row to move to a new page , and then decrease the page within the same row . in both scan sequences , the lower right portion 68 is the second portion read in the sequence . referring to fig4 and 5c , the decoder may fetch a third reference macroblock 70 . the reference macroblock 70 includes an upper left portion 71 , a upper right portion 72 , and a lower portion 73 . the upper left portion 71 overlies a section of a macroblock stored on page 38 - 1 ; the upper right portion 72 overlies a section of a macroblock stored on page 38 - 2 ; and the lower portion 73 overlies sections of two macroblocks stored on page 38 - 24 . the upper right portion 72 and the lower portion 73 are stored in bank a , whereas upper left portion 71 is stored in bank b . to fetch the reference macroblock 70 from the memory , the decoder will scan the portions 71 - 73 in the following order : either upper right portion 72 , upper left portion 71 , lower portion 73 ; or lower portion 73 , upper left portion 71 , upper right portion 72 . thus , the decoder will either decrease the row and then increase the page within the same row , or decrease the page within the same row and then increase the row . in both scan sequences , the upper left portion 71 is the second portion read in the sequence . referring to fig4 and 5d , the decoder may fetch a fourth reference macroblock 75 . the reference macroblock 75 includes an upper portion 76 , a lower left portion 77 , and a lower right portion 78 . the upper portion 76 overlies sections of two macroblocks stored on page 38 - 2 , the lower left portion 77 overlies a section of a macroblock stored on page 38 - 24 , and the lower right portion 78 overlies a section of a macroblock stored on page 38 - 25 . the upper portion 76 and the lower left portion 77 are stored in bank a , whereas the lower right portion 78 is stored in bank b . to fetch the reference macroblock 75 from the memory , the decoder will scan a portion 76 - 78 in the following order : either upper portion 76 , lower right portion 78 , lower left portion 77 ; or lower left portion 77 , lower right portion 78 , upper portion 76 . thus , the decoder will either increase the row and then decrease the page within the row , or increase the page within the row and then decrease the row . in both scan sequences , the lower right portion 78 is the second portion read in the sequence . for a 16 - mbit memory using 16 - bit words , the scanning sequence may be summarized as follows : if the portion overlying two macroblocks is on the bottom , then the upper left portion will be second in the sequence ; if the portion overlying two macroblocks is on the top , then the lower right portion will be second in the sequence . referring to fig8 the distribution of the video picture 46 ( fig1 ) in a 32 - mbit memory using 32 - bit words is shown schematically . specifically , the video picture is divided into macroblocks , and four consecutive macroblocks ( e . g ., 42a &# 39 ;- 42d &# 39 ;) are stored in a single page ( e . g ., 38 - 0 &# 39 ;). in this configuration , the macroblocks stored in bank a and bank b in a memory using 32 - bit words are aligned with a skew direction 55 . specifically , in the memory using 32 - bit words , the skew direction 55 is from the upper left to the lower right . because each page of a memory using 32 - bit words stores four macroblocks , the forty - five macroblocks in each row require eleven and one - quarter pages of the memory . consequently , the twelfth page 38 - 11 &# 39 ; stores one macroblock 42e &# 39 ; in a first row 40a &# 39 ; and three macroblocks 42f &# 39 ;- 42h &# 39 ; in a second row 40b &# 39 ;. because a row of macroblocks needs an odd number of pages in a 16 - bit word memory , but an even number of pages in a 32 - bit word memory , the resulting respective skew directions 50 and 55 are generally perpendicular . referring to fig8 and 9a , the decoder may fetch a reference macroblock 80 from reference picture 46 ( fig1 ) stored in the 32 - bit word memory . the reference macroblock 80 includes an upper left portion 81 , an upper right portion 82 and a lower portion 83 . the upper left portion 81 overlies a section of a macroblock stored on page 38 - 0 &# 39 ;; the upper right portion 82 overlies a section of a macroblock stored in page 38 - 1 &# 39 ;; and the lower portion 83 overlies sections of two macroblocks 83a and 83b stored in page 38 - 12 &# 39 ;. the upper left portion 81 and the lower portion 83 are stored in bank a , whereas the upper right portion 82 is stored in bank b . to fetch reference macroblock 80 from the memory , the decoder will scan the portions 81 - 83 in the following order : either upper left portion 81 , upper right portion 82 , lower portion 83 ; or lower portion 83 , upper right portion 82 , upper left portion 81 . in either order , the upper right portion 82 is second in the sequence . a line 84 connecting the upper right portion 82 to its diagonally opposed macroblock 83b in lower portion 83 is substantially perpendicular to the skew direction 55 . referring to fig8 and 9b , the decoder may fetch a second reference macroblock 85 from a different position in the reference picture 46 ( fig1 ). the reference macroblock 85 includes an upper portion 86 , a lower left portion 87 , and a lower right portion 88 . the upper portion 86 overlies two sections of macroblocks stored in page 38 - 1 &# 39 ;; the lower left portion 87 overlies a section of a macroblock stored in page 38 - 12 &# 39 ;; and the lower right portion 88 overlies a section of a macroblock stored in page 38 - 13 &# 39 ;. the upper portion 86 and the lower right portion 88 are stored in bank b , whereas the lower left portion 87 is stored in bank a . to fetch the reference macroblock 85 from the memory , the decoder will scan portions 86 - 88 in the following order : either upper portion 86 , lower left portion 87 , lower right portion 88 ; or lower right portion 88 , lower left portion 87 , upper portion 86 . thus , the decoder will either increase the row and then increase the page within the row or decrease the page within the row and then decrease the row . in both scan sequences the lower left portion 87 is second in the sequence . referring to fig8 and 9c , a third reference macroblock 90 includes an upper left portion 91 , an upper right portion 92 , and a lower portion 93 . the upper left portion 91 overlies a section of a macroblock stored on page 38 - 11 &# 39 ;; the upper right portion 92 overlies a section of a macroblock stored on page 38 - 12 &# 39 ;; and the lower portion 93 overlies sections of two macroblocks stored on page 38 - 23 &# 39 ;. the upper left portion 91 and the lower portion 93 are stored in bank b , whereas the upper right portion 92 is stored in bank a . to fetch the reference macroblock 90 , the decoder will scan the portions 91 - 93 in the following order : either upper left portion 91 , upper right portion 92 , lower portion 93 ; or lower portion 93 , upper right portion 92 , upper left portion 91 . in either order , the upper right portion 92 is second in the sequence . referring to fig8 and 9d , a fourth reference macroblock 95 is fetched from the reference picture 46 . the reference macroblock 95 includes an upper portion 96 , a lower left portion 97 and a lower right portion 98 . the upper portion 96 overlies sections of two macroblocks stored in page 38 - 12 &# 39 ;; the lower left portion 97 overlies a section of a macroblock stored on page 38 - 23 &# 39 ;; and the lower right portion 98 overlies a section of a macroblock stored on page 38 - 24 &# 39 ;. as shown , the upper portion 96 and the lower right portion 98 are stored in bank a , whereas the lower left portion 97 is stored in bank b . to fetch the reference macroblock 95 , the decoder will scan the portions 96 - 98 in the following order : upper portion 96 , lower left portion 97 , lower right portion 98 ; or lower right portion 98 , lower left portion 97 , upper portion 96 . in either sequence , the lower left portion is the second portion read in the sequence . for a 32 - mbit memory , the scan sequence may be summarized as follows : if the portion overlying two macroblocks is on the bottom , then the upper right portion is second in the sequence , whereas if the portion overlying two macroblocks is on the top , then the lower left portion is second in the sequence . the scanning sequence for both 16 - mbit and 32 - mbit memory may be summarized as follows : one of the two portions located in the same row will be the second portion in the sequence , and a line connecting the second portion in the sequence to its diagonally opposed macroblock in the portion which overlies two macroblocks will be substantially perpendicular to the skew direction . since numerous modifications and changes will readily occur to those skilled in the art , it is not desired to limit the invention to the exact construction and operation as illustrated and described . hence , all suitable modifications and equivalents may be resorted to as falling within the scope of the invention .