referring now to the drawings , in particular to fig3 a through 3o , there is shown a combined method of forming salicide and self - aligned contact ( sac ) structures in a flash memory with embedded peripheral logic circuits . though the method is disclosed in conjunction with memory circuits where both p doped and n doped wells are provided for making p - and n - channel fets , it should be understood that the method equally applies to other semiconductor integrated circuits where both salicide and sac are desired , including cmos . in the drawings in fig3 a - 3o , a cross - sectional view of a partially completed flash memory cell formed on and in the surface of a semiconductor substrate ( 100 ) is shown having a common boundary ( b ) separating a memory cell region ( c ) and a peripheral logic device region ( p ). viewing the semiconductor substrate of fig3 a - 3o across the boundary region ( b ) serves to better illustrate how the forming of the self - aligned contact ( sac ) of the cell region ( c ) can be combined with the forming of the salicide contact ( c ) can be combined with the forming of the salicide contact of the peripheral region ( p ) using a single combined mask for both . in order to differentiate more readily those portions of the material that are formed over the respective regions , reference numerals referring to the same material parts on the peripheral region are primed while those that are on the cell region are not . it is preferred that substrate ( 100 ) comprises p + type single - crystal silicon having a & lt ; 100 & gt ; crystallographic orientation . peripheral region ( p ) is of an opposite conductivity n - well while cell ( c ), formed after defining the active regions , is to be of conductivity p - well . deep n - well and the subsequent p - well ( not shown ) are formed , respectively , by ion implanting phosphorous at a dosage level between about 5 × 10 12 to 5 × 10 13 atoms / cm 2 and at an energy between about 100 to 200 kev , and boron at a dosage level between about 1 × 10 13 to 5 × 10 13 atoms / cm 2 and at an energy between about 20 to 80 kev . a thick field oxide , fox , ( 105 ) is formed around both the memory and logic device regions to provide electrical isolation between them . the most commonly used field oxide is formed by the method of local oxidation of silicon ( locos ) in which silicon nitride ( si 3 n 4 ) layer ( not shown ) is deposited and patterned leaving portions over device regions . another commonly used method is the shallow - trench - isolation ( sti ). the substrate is then subjected to thermal oxidation to oxidize the exposed surface of the silicon substrate to form field oxide ( 105 ), as shown in fig3 a . after the forming of the two wells , or tubs as they are sometimes known , and of the active and passive field oxide regions , a first gate oxide layer ( 110 ), or tunnel oxide , is formed over the device regions ( both logic and memory device regions ) of fig3 a by thermal oxidation . gate oxide ( 110 ), which will eventually serve as the tunneling oxide for the memory cell access transistor , is preferably grown thermally in dry oxygen in an oxidation furnace at temperature range between about 750 to 1000 ° c ., and to a thickness between about 50 to 200 å . alternatively , other oxidation methods can be used , such as oxidation in a dry oxygen and anhydrous hydrogen chloride in atmospheric or low pressure environment , or low temperature , high - pressure , and the like . a first polysilicon layer ( 120 ) is next deposited over gate oxide layer ( 110 ) and elsewhere on the field oxide regions , as shown in fig3 a . the polysilicon layer is preferably deposited by lpcvd using , for example , silane ( sih 4 ) as the reactant gas , and is deposited in a temperature range of between about 500 to 800 ° c . the preferred thickness of the first polysilicon layer is between about 500 to 2000 å . the polysilicon is then in - situ doped by adding a dopant gas , such as phosphine ( ph 3 ) to the chemical vapor deposited ( cvd ) reactant gas silane . alternatively , the polysilicon can be doped by ion implantation using arsenic ( as 75 ) or phosphorous ( p 31 ) ions . using conventional photolithographic techniques a phtoresist layer is spin - coated ( not shown ) on the first polysilicon layer ( 120 ) and patterned leaving portions of the photoresist over the memory device region ( c ) while exposing the polysilicon layer ( 120 &# 39 ;) over the peripheral logic region ( p ). the first polysilicon layer ( 120 &# 39 ;) is then etched to the gate oxide layer ( 110 &# 39 ;) over the peripheral logic region ( p ) and the polysilicon ( 120 ) over the cell region is formed with a gate pattern which is to serve as a floating gate of the flash memory cell , as shown in fig3 b . the etching is performed using anisotropic plasma etching , for example in a reactive ion etcher ( rie ), and using an etchant gas such as chlorine ( cl 2 ) and a carrier gas , such as argon ( ar ). this results in selective etching of the polysilicon layer ( 120 &# 39 ;) to the gate oxide ( 110 &# 39 ;). referring now to fig3 c , after the removal of the photoresist layer of the previous step , another oxide layer ( 130 ) is formed , where this layer will serve as an interpoly oxide between the first polysilicon layer and the second polysilicon layer to be deposited . it is preferred that interpoly layer ( 130 ) comprises oxide - nitride - oxide ( ono ) and is chemical vapor deposited by reacting sih 4 with n 2 o and nh 3 to a thickness between about 100 to 500 å . a conformal second polysilicon layer ( 140 ) is then formed over the interpoly oxide layer by using lpcvd similar to the deposition for the first polysilicon layer and also in - situ doped . the preferred thickness of the second polysilicon layer is between about 500 to 3000 å . at the next step , a layer of silicide , ( 150 ) is formed over the second polysilicon layer ( 140 ), as seen in the same fig3 c . silicides are formed by depositing metal on silicon ( i . e ., onto single crystal and / or polycrystalline si ) and then heating it . they can also be formed by simultaneous evaporation of silicon and refractory metal from two sources ( co - evaporation ), or by sputter - depositing silicide , either from a composite target , or by co - sputtering or layering . it is preferred in this embodiment that tungsten silicide ( wsi ) be sputter deposited to a thickness between about 500 to 3000 å . this is followed by forming an oxide layer capping the aforesaid layers as shown in fig3 c . the oxide capping layer ( 160 ) is oxynitride ( on ) and has a thickness between about 500 to 5000 å . it will be noted from fig3 c that the layers , including the on layer , cover all regions of the substrate including the cell region ( c ) and the peripheral region ( p ), where the layers in the ( p ) region are indicated by primed numerals , namely , ( 110 &# 39 ;), ( 130 &# 39 ;), ( 140 &# 39 ;) ( 150 &# 39 ;) and ( 160 &# 39 ;). the on layer is then used to protect the cell ( c ) region while all the layers in the peripheral ( p ) region are removed down to the silicon surface of substrate ( 100 ) as shown in fig3 d . this is accomplished by using a series etch recipes comprising gases as follows : for on layer ( 130 ): cf 4 , c 2 f 6 , or cl 2 ; for ws i layer ( 150 ): sf 6 or cl 2 ; for second polysilicon layer ( 140 ): cl 2 ; and for ono interpoly layer ( 130 ): cf 4 , c 2 f 6 , or cl 2 . as an important aspect of the present invention , a second gate oxide layer ( 113 &# 39 ;), but thinner than the first gate oxide layer ( 110 &# 39 ;), is next thermally grown over the peripheral logic region ( p ). the thermal oxidation is preferably performed in an oxidation furnace in a temperature range of between about 750 to 1000 ° c . using dry oxygen similar to the thermal oxidation used to form the first gate oxide layer . this thermal oxidation also forms an oxide layer on the on layer ( 160 ). preferably the second gate oxide layer ( 113 &# 39 ;) is grown to a thickness between about 40 to 400 å . it will be appreciated by those skilled in the art that the second gate oxide layer ( 113 &# 39 ;) of region ( p ) different from the first gate oxide layer ( 110 ) of region ( c ) together form the dual - gate oxide of the embedded flash memory of this invention . thus , a thin gate oxide has been formed in the peripheral logic region to enhance the fet device performance there , while providing a thicker gate oxide for the higher gate voltage requirement on the access transistors in the memory cell region . furthermore , the two differently thick oxides of the dual - gate oxide layers have been formed independently and without affecting each other , such as the case of a protective photoresist layer of prior art that would be used to first etch one gate oxide layer and grow the next one , as described earlier in related art . an intrinsic polysilicon layer is now deposited over the substrate of fig3 e , including the cell ( c ) regions as well as the peripheral ( p ) regions , where the portions ( 170 ) over the ( c ) region lie on the previous layers underlying on cap layer ( 160 ) of the memory cell while portions ( 170 &# 39 ;) over the ( p ) region lie directly over the new second gate oxide layer ( 113 &# 39 ;). using another photoresist mask ( not shown ), the intrinsic polysilicon layer in the peripheral region is patterned to form poly - gate ( 170 &# 39 ;) as shown in fig3 f . the photoresist mask protects only the poly - gate patterns of region ( p ) so that all of the intrinsic polysilicon layer ( 170 ) of the ( c ) region is etched away at the same time the poly - gate of region ( p ) is formed . this is accomplished by using an etch recipe comprising cl 2 gas . using as a mask the poly - gate ( 170 &# 39 ;) so formed , a lightly doped drain ( ldd ) is next formed by ion implanting phosphorous ( p ), or arsenic ( as ), or boron fluoride ( bf 2 ) at a dosage level between about 5 × 10 12 to 5 × 10 13 atoms / cm 2 , and energy level between about 20 to 200 kev . the stacked gate ( 165 ) of the memory cell of region ( c ) is next defined and etched as shown in fig3 g . this is accomplished by forming and patterning a photoresist mask such that the peripheral ( p ) region is protected . preferably , the etch recipe comprises for on layer ( 130 ): cf 4 , c 2 f 6 , or cl 2 ; for ws i layer ( 150 ): sf 6 or cl 2 ; for second polysilicon layer ( 140 ): cl 2 ; and for ono interpoly layer ( 130 ): cf 4 , c 2 f 6 , or cl 2 . using the stacked gate as a mask , a mild doped drain ( mdd ) region is formed by ion implanting the cell with phosphorous at a dosage level between about 5 × 10 13 to 5 × 10 14 atoms / cm 2 and energy level between about 20 to 100 kev . as another aspect of the invention , a source line ( 107 ) for the memory cell in region ( c ) can be defined and formed at this step by using a self - aligned source ( sas ) mask . the field oxide along the source line is removed by using an etch recipe comprising gas cf 4 . this results in selective etching of the field oxide with respect to the silicon substrate . a dual diffused drain ( ddd ) is next formed by ion implanting the source and drain regions of the cell with arsenic at a dosage level between about 1 × 10 15 to 5 × 10 15 atoms / cm 2 and energy level between about 20 to 100 kev . next , oxide , or nitride spacers ( 180 ) and ( 180 &# 39 ;) are formed on the side - walls of the stacked gate and the poly - gate respectively , as shown in fig3 h . the forming of the spacers is accomplished by depositing and anisotropically etching an oxide or nitride layer ( not shown ) and they have a thickness between about 500 to 3000 å . then source and drain regions ( 111 ) and ( 111 &# 39 ;) are formed by ion implanting with as , or bf 2 at a dosage level between about 1 × 10 15 to 5 × 10 15 atoms / cm 2 and energy level between about 10 to 50 kev . the spacers so formed and the remaining walls of the stacked gate ( 165 ) are covered with a lining layer ( 190 ) shown in fig3 i . the lining can be an oxide , but it is preferred that it be nitride having a thickness between about 100 to 500 å . this lining will protect the cell region ( c ) during the salicide formation in the peripheral region ( p ) as will be seen in fig3 j . it is formed by reacting dichlorosilane ( sicl 2 h 2 ) with ammonia ( nh 3 ) in an lpcvd at a pressure between about 0 . 1 to 100 torr , temperature between about 600 to 800 ° c . and at flow rates between about 0 . 1 to 10 sccm . the lining layer ( 190 ) is removed from the peripheral region ( p ) as shown in fig3 i by using a resistor protecting oxide ( rpo ) as a mask which protects the ( c ) region . the removal of the nitride lining in the ( p ) region is accomplished with an etchant gas such as cf 4 . as another important aspect of the present invention , salicidation in the peripheral region is now performed . this is accomplished preferably by depositing titanium and then subjecting it to a rapid thermal anneal process . the preferred thickness of the titanium silicide is between about 100 to 500 å . following the silicide formation , a selective etch removes the unreacted metal portions form non - silicon areas , such as from over the spacers , while leaving the reacted portions ( 195 &# 39 ;) on the polysilicon - gate and portions ( 195 &# 34 ;) on the silicon substrate as shown in fig3 j . silicides so formed are self - aligned with respect to the poly - gate , and hence forming salicides . substrate ( 100 ) is next deposited with an interlevel dielectric layer ( 200 ). blanket dielectric layers may be formed from materials including but not limited to silicon oxide materials , silicon nitride materials , and silicon oxynitrides materials formed within integrated circuits through methods including but not limited do cvd , pecvd , pvd sputtering methods . for the preferred embodiment of the present invention , the blanket dielectric layer ( 200 ) is preferably formed of a dielectric material chosen from the group of dielectric materials consisting of silicon oxide dielectric materials , silicon nitride , and silicon oxynitride and has a thickness between about 5000 to 20000 å . dielectric layer ( 200 ) is next etched to form contact holes both in the cell region ( c ) and the peripheral region ( p ). however , as a main feature and key aspect of the present invention , a single mask can be used to form the contact holes simultaneously in both regions as shown in fig3 l . here , hole ( 205 ) shown in the cell region is self - aligned with respect to the stacked gate , hence the sac process of the present invention . at the same time , the contact holes ( 205 &# 39 ;) of the peripheral region are also formed by using the same photomask ( not shown ) containing both the sac and the salicide contact hole patterns . the etch is performed with a recipe comprising cf 4 or chf 3 . subsequent to the forming of the contact holes , ( 205 ) and ( 205 &# 39 ;), in the respective regions of the substrate , the usual back - end processes of semiconductor manufacturing , such as forming of the various metallized layers , are continued to completion . the resulting sac and salicide structures of the present invention are shown in fig3 m - 3o . fig3 m shows the structures at the common boundary ( b ) between the cell ( c ) region and the peripheral ( p ) region , where first metal layer ( 210 ) interconnects the devices of single poly gate in the two regions . fig3 n , on the other hand , shows the stacked gate structure of the cell region . finally , fig3 o shows a device with tunnel oxide . thus , for the device shown in fig3 n , metal line ( 210 ) is used to connect the contact on first poly ( 120 ) of the cell region with the periphery poly ( 170 &# 39 ;). therefore , first poly is the control gate for the device with tunnel oxide ( 110 ) shown in fig3 n . by the same token , in the device shown in fig3 o , first poly ( 120 ) is again the control gate for the device with the tunnel oxide ; however , this time the first poly of the cell region is connected to the first poly of the periphery through a shorted connection between the first poly ( 120 ) and the silicide layer ( 150 ) which in turn is connected to the poly of the periphery through the metal interconnect ( 210 ). in the descriptions of the embodiments given above , numerous details were set forth , such as specific materials , process parameter , etc ., in order to provide a thorough understanding of the present invention . it will be obvious , however , to those skilled in the art that these specific details need not be employed to practice the present invention . that is to say , while the invention has been particularly shown and described with reference to the preferred embodiments thereof , it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention .