in the following detailed description , reference is made to the accompanying drawings , which form a part hereof and illustrate specific embodiments in which the invention may be practiced . in the drawings , like reference numerals describe substantially similar components throughout the several views . these embodiments are described in sufficient detail to enable those skilled in the art to practice the invention , and it is to be understood that other embodiments may be utilized , and that structural , logical and electrical changes may be made without departing from the spirit and scope of the present invention . the terms “ wafer ” and “ substrate ” are to be understood as including silicon , silicon - on - insulator ( soi ), or silicon - on - sapphire ( sos ) technology , doped and undoped semiconductors , epitaxial layers of silicon supported by a base semiconductor foundation , and other semiconductor structures . furthermore , when reference is made to a “ wafer ” or “ substrate ” in the following description , previous process steps may have been utilized to form regions or junctions in the base semiconductor structure or foundation . in addition , the semiconductor need not be silicon - based , but could be based on silicon - germanium , germanium , or gallium - arsenide . the term “ pixel ” or “ pixel cell ” refers to a picture element unit cell containing a photo - conversion device for converting electromagnetic radiation to an electrical signal . referring to the drawings , fig3 depicts an image sensor 300 according to an exemplary embodiment of the invention . image sensor 300 includes a pixel array 311 comprising an active array region 12 and two black regions 313 , 315 . light is prevented from reaching pixel cells of the black regions 313 , 315 by , for example , a metal layer , a black color filter array , or any opaque material ( not shown ). there is also peripheral circuitry 15 adjacent to the array 311 . as shown in fig3 , the peripheral circuitry can include row select circuitry 16 and column select circuitry 17 for activating particular rows and columns of the array 11 ; and other peripheral circuitry 18 , which can include analog signal processing circuitry , analog - to - digital conversion circuitry , and digital logic processing circuitry . the configuration of image sensor 300 is exemplary only . accordingly , image sensor 300 need not include peripheral circuitry 15 adjacent to the array 311 . fig4 a depicts a portion of the black region 313 , and fig4 b depicts a portion of the black region 315 . like black region 13 ( fig1 ), the illustrated black regions 313 , 315 include black pixel cells 20 ′. preferably , the black regions 313 , 315 also include buffer pixel cells 20 ″. the first black region 313 includes guard row pixel cells 353 , and the second black region 315 includes guard column pixel cells 355 . light is prevented from reaching the photo - conversion devices 21 of the pixel cells 20 ′, 20 ″, 353 , 355 in the black regions 313 , 315 by , for example , a metal layer , a black color filter array , or any opaque material ( not shown ). as shown in fig4 a , the first black region 313 includes rows 314 of guard row pixel cells 353 , rows 14 a of black pixel cells 20 ′, and rows 14 b of buffer pixel cells 20 ″. there can be any number of rows 14 a , 14 b , 314 . preferably , there are between approximately two and approximately twenty rows 314 of guard row pixel cells 353 . preferably , the rows 14 b , 314 flank the rows 14 a of black pixel cells 20 ′, as shown in fig4 a . it is also preferable that the buffer pixel cells 20 ″ are between the guard pixel cells 353 and black pixel cells 20 ′. although fig4 a shows an equal number of buffer pixel cells 20 ″ and guard row pixel cells 353 above and below the rows 14 a of black pixel cells 20 ′, embodiments of the invention include an image sensor 300 having different numbers of buffer pixel cells 20 ″ and / or guard row pixel cells 353 above the black pixel cells 20 ′ than are below the black pixel cells 20 ′. additionally , embodiments of the invention include an image sensor 300 , having buffer pixel cells 20 ″ and / or guard row pixel cells 353 only on one side of the black pixel cells 20 ′. fig5 a is a schematic diagram of rows 314 , including a detailed diagram of a guard row pixel cell 353 ; fig5 b is a top plan view of a guard row pixel cell 353 . similar to a conventional active array pixel cell 20 , each guard row pixel cell 353 includes a transfer transistor 27 , a floating diffusion region 25 , a reset transistor 28 , a source follower transistor 29 , and a row select transistor 26 . the guard row pixel cell 353 , however , includes different connections and , therefore , operates differently than active array pixel cell 20 as described in more detail below . as shown in fig5 a and 5b , the gates 27 a , 28 a of the transfer and reset transistors 27 , 28 are coupled to a power supply voltage ( vaa - pix ) rail 303 . this is in contrast to the active array pixel cells 20 ( fig2 a and 2b ), where the gates 27 a , 28 a of the transfer and reset transistors 27 , 28 receive tx and rst signals , respectively . since all pixel cells in the guard rows 314 are guard pixel cells 353 , connections ( e . g ., metal lines ) are not needed to provide tx and rst signals to the rows 314 . also , if desired , the gate of the row select transistor 26 can be coupled to a ground potential . as shown in fig4 b , the black region 315 includes columns 317 a of black pixel cells 20 ′, columns 317 b of buffer pixel cells 20 ″, and columns 316 of guard column pixel cells 355 . there can be any number of columns 317 a , 317 b , 316 . preferably , there are between approximately two and approximately twenty columns 316 of guard column pixel cells 355 . preferably , the columns 317 b , 316 flank the columns 14 a of black pixel cells 20 ′, as shown in fig4 b . it is also preferable that the buffer pixel cells 20 ″ are between the guard pixel cells 355 and black pixel cells 20 ′. although fig4 b shows an equal number of buffer pixel cells 20 ″ and guard column pixel cells 355 on each side of the columns 317 a of black pixel cells 20 ′, embodiments of the invention include an image sensor 300 having different numbers of buffer pixel cells 20 ″ and / or guard column pixel cells 355 on one side of the black pixel cells 20 ′ than are on the other side of the black pixel cells 20 ′. additionally , embodiments of the invention include an image sensor 300 , having buffer pixel cells 20 ″ and / or guard column pixel cells 355 only on one side of the black pixel cells 20 ′. fig5 c is a schematic diagram of the columns 316 , including a detailed diagram of a guard column pixel cell 355 . similar to a conventional active array pixel cell 20 , each guard column pixel cell 355 includes a transfer transistor 27 , a floating diffusion region 25 , a reset transistor 28 , a source follower transistor 29 , and a row select transistor 26 . the guard column pixel cell 355 , however , includes different connections and , therefore , operates differently than active array pixel cell 20 , as described in more detail below . the guard column pixel cell 355 is similar to the guard row pixel cell 353 , except that in the guard column pixel cell 355 the gate of the row select transistor 26 is not coupled to a ground potential . additionally , connections ( e . g ., metal lines ) are provided over the guard column pixel cells 355 to supply tx and rst signals to the active array pixel cells 20 , black pixel cells 20 ′, and buffer pixel cells , 20 ″ located in the same row as the guard column pixel cell 355 . accordingly , as shown in fig5 c , the gates of the transfer and reset transistors 27 , 28 are coupled to the vaa - pix rail 303 , in contrast to the active array pixel cells 20 ( fig2 a and 2b ). excess charge ( e . g ., blooming charge from the active array pixel cells 20 ) is collected in the photo - conversion devices 21 of the guard pixel cells 353 , 355 . since the gates 27 a , 28 a of the transfer and reset transistors 27 , 28 are coupled to the vaa - pix rail 303 , the gates are held open . that is , the gates 27 a , 28 a are continuously operated . therefore , charge in the photodiode 21 and the floating diffusion region 25 is drained from the pixel cells 353 , 355 through the vaa - pix rail 303 . in this manner , the guard pixel cells 353 , 355 serve to isolate the black pixel cells 20 ′ from interference , particularly from interference from the active array pixel cells 20 . further , the connection to the vaa - pix rail 303 creates a gradient in the electric field of the photodiode 21 and floating diffusion region 25 with respect to the substrate ( not shown ), which is biased at a ground potential . the electrical gradient promotes the collection of negative photon - generated charge ( e . g ., blooming charge from adjacent pixel cells 20 ) in the photodiode 21 and the floating diffusion region 25 , where it is removed via the vaa - pix rail 303 . the guard pixel cells 353 , 355 can be formed similarly to the other pixel cells 20 , 20 ′, 20 ″ of the array , except that the guard pixel cells 353 , 355 are formed having the connections described above with reference to fig5 a - 5c . also , the guard pixel cells 353 , 355 can be formed concurrently with the other pixel cells 20 , 20 ′, 20 ″. in one embodiment of the invention , the pixel cells 353 , 355 are formed by known methods on a substrate ( not shown ). although the image sensor 300 is shown including black region 313 having pixel cells 20 ′, 20 ″, 353 arranged in rows and black region 315 having pixel cells 20 ′, 20 ″, 355 arranged in columns , embodiments of the invention include an image sensor 300 having additional or fewer black regions 313 , 315 . for example , the image sensor 300 can include only one of the first or second black regions 313 , 315 , if desired . according to another exemplary embodiment of the invention , the image sensor 300 can include active array pixel cells having configurations other than a 4t configuration . for example , the image sensor can include active array pixel cells 30 having a three - transistor ( 3t ) configuration , as shown in fig6 , instead of active array pixel cells 20 . the 3t active array pixel cell 30 is known in the art and differs from the 4t active array pixel cell 20 ( fig2 a ) by the absence of the transfer transistor 27 . the image sensor 300 can also include black pixel cells and buffer pixel cells having 3t configurations ( not shown ), instead of 4t pixel cells 20 ′, 20 ″. further , the image sensor 300 can include guard row pixel cells 753 and guard column pixel cells 755 having 3t configurations , as shown in fig7 a and 7b , instead of 4t guard pixel cells 353 , 355 . the 3t guard row pixel cells 753 are similar to the 4t guard row pixel cells 353 , except that the 3t guard row pixel cells 753 lack a transfer transistor 27 . accordingly , as shown in fig7 a , the gates of the reset transistors 28 are coupled to a power supply voltage ( vaa - pix ) rail 303 . this is in contrast to the 3t active array pixel cell 30 ( fig6 ), where the gate reset transistor 28 receives rst signals . also , if desired , the gate 26 a ( fig5 b ) of the row select transistor 26 can be coupled to a ground potential . likewise , 3t guard column pixel cells 755 are similar to the 4t guard column pixel cells 355 , except that the 3t guard column pixel cells 755 lack a transfer transistor 27 . accordingly , as shown in fig7 b , the gate 28 a ( fig5 b ) of the reset transistor 28 is coupled to the vaa - pix rail 303 , in contrast to the 3t active array pixel cells 30 ( fig6 ). it should be noted that the configuration of the pixel cells 20 , 30 , 20 ′, 20 ″, 353 , 355 , 753 , 755 is only exemplary and that various changes may be made as are known in the art and pixel cells of the image sensor 300 may have other configurations . for example , although the invention is described in connection with four - transistor ( 4t ) guard pixel cells 353 , 355 and three - transistor ( 3t ) guard pixel cells 753 , 755 , the invention may also be incorporated into other pixel circuits having different numbers of transistors . without being limiting , such a circuit may include five - transistor ( 5t ) pixel cell , six - transistor ( 6t ), and seven - transistor ( 7t ) guard pixel cells . the 5t , 6t , and 7t guard pixel cells would differ from the 4t pixel cell by the addition of one , two , or three transistors , respectively , such as a shutter transistor , a cmos photogate transistor , and an anti - blooming transistor . in each case , the gates of the transistor ( s ) connected to the photo - conversion device and the floating diffusion region would be coupled to a power supply voltage ( e . g ., vaa - pix ) such that charge from the photo - conversion device and the floating diffusion region is drained from the guard pixel cells through the connection to the power supply voltage . for example , when a guard pixel cell 353 , 355 further includes an anti - blooming transistor ( not shown ) connected to the photodiode 21 , the gate of the anti - blooming transistor would be coupled to vaa - pix . also , while the above embodiments are described in connection with p - n - p - type photodiodes the invention is not limited to these embodiments . the invention also has applicability to other types of photo - conversion devices , such as a photodiode formed from n - p or n - p - n regions in a substrate , a photogate , or a photoconductor . if an n - p - n - type photodiode is formed the conductivity types of all structures would change accordingly . fig8 illustrates a processor - based system 800 including an image sensor 300 of fig3 having guard pixel cells 353 , 355 ( fig5 a - 5c ). instead , as described above , the image sensor 300 could include guard pixel cells 753 , 755 ( fig7 a and 7b ). the processor - based system 800 is exemplary of a system having digital circuits that could include image sensor devices . without being limiting , such a system could include a computer system , camera system , scanner , machine vision , vehicle navigation , video phone , surveillance system , auto focus system , star tracker system , motion detection system , image stabilization system , and data compression system . the processor - based system 800 , for example a camera system , generally comprises a central processing unit ( cpu ) 860 , such as a microprocessor , that communicates with an input / output ( i / o ) device 861 over a bus 863 . image sensor 300 also communicates with the cpu 860 over bus 863 . the processor - based system 800 also includes random access memory ( ram ) 862 , and can include removable memory 864 , such as flash memory , which also communicate with cpu 860 over the bus 863 . image sensor 300 may be combined with a processor , such as a cpu , digital signal processor , or microprocessor , with or without memory storage on a single integrated circuit or on a different chip than the processor . it is again noted that the above description and drawings are exemplary and illustrate preferred embodiments that achieve the objects , features and advantages of the present invention . it is not intended that the present invention be limited to the illustrated embodiments . any modification of the present invention which comes within the spirit and scope of the following claims should be considered part of the present invention .