with reference to the schematic diagram of fig1 a compensated schmitt trigger circuit is shown . the circuit operates from a v cc power supply connected + to terminal 10 and - to ground terminal 11 . since the circuit is to be compatible with ttl logic , this supply is ordinarily 5 ± 0 . 5 volts . the circuit shown is for n well cmos construction in which the p channel transistors have individual back gate connections as shown . all of the n channel transistor back gates ( not shown ) are connected to the substrate which is grounded . input terminal 12 responds to the preceding logic circuitry which is at ttl levels . in this logic family a logic one is typically in excess of 2 volts and a logic zero is less than 0 . 8 volt . output terminal 13 which swings substantially rail - to - rail , or zero to five volts , responds as a noninverting buffer with hysteresis to input terminal 12 . n channel transistor 14 , which has its gate returned to a reference source 15 , supplies current to node 16 . this part of the circuit operates in accordance with the teaching in u . s . pat . no . 4 , 430 , 582 . the voltage at node 16 is regulated to make the inverter gates in a gate array operate with ttl logic inputs and to make them operate substantially independent of temperature , supply voltage and transistor parameters . while node 16 is shown connected to a single schmitt trigger circuit it is to be understood that a single transistor 14 and reference source 15 could supply a plurality of similar trigger circuits . it is only necessary that transistor 14 be made large enough to handle the combined currents of the plural trigger circuits . v ref is obtained as follows . resistors 28 and 29 form a voltage divider across the power supply . they are proportioned so that about 1 . 4 volts is applied to the input of inverter 30 . transistors 31 and 32 are proportioned so that a 1 . 4 volt input produces a v cc / 2 output or about 2 . 5 volts . inverter 33 is designed to act as a level shifter so that its output is close to v cc . transistor 34 which acts as a source follower supplies operating current to inverter 30 . thus a negative feedback loop exists around inverter 30 which is operated against a 1 . 4 volt reference . the potential at node 35 will adjust the circuit operating point so that the inverter 30 will be in its high gain states or active , at the ttl logic reference level . if node 35 is connected to supply a number of similar logic gates in an array , they all will be compensated for variations in temperature , supply voltage and device parameters . the schmitt trigger circuit itself is made up of transistors 17 - 20 and inverter 21 . n channel transistors 18 and 19 together form a cmos inverter with p channel transistor 17 . the gates of all three devices are returned to input terminal 12 . n channel transistor 20 is coupled between nodes 16 and 23 with its gate returned to node 22 which could be described and the hysteresis node . the graph of fig2 portrays the operation of the circuit of fig1 . when the input at terminal 12 is zero transistors 18 and 19 are off and node 22 is pulled high by transistor 17 . due to the action of inverter 21 the output at terminal 13 is low or close to zero . since node 22 is high transistor 20 will be on and will pull node 23 high . as the input rises transistor 19 will turn on first at an input of v tn , or one n channel transistor threshold , and start to pull node 23 down . at this point transistors 19 and 20 act as a voltage divider . as the input continues to increase node 23 will be pulled lower and at some point transistor 18 will turn on . when this occurs transistors 18 - 20 form an active high gain regenerative loop that will rapidly pull node 22 down as a function of the rising input . the output of inverter 21 will suddenly snap up close to + v cc . this produces transition 25 of fig2 . the parameters of transistors 18 - 20 are selected so that transition 25 occurs at close to 1 . 6 volts which is below the ttl logic one but higher than the ttl logic reference of 1 . 4 volts . as the input is increased further the output will remain at + v cc . note the left to right arrows in the graph of fig2 . at this output high point transistors 18 and 19 are on while transistors 17 and 20 are off . nodes 22 and 23 are low . when the input is swung from high to low at terminal 12 the right to left arrows of fig2 are invoked . the input will drop until the threshold of the inverter formed by transistors 17 - 19 is reached . at this point transistor 17 will pull node 22 up to where transistor 20 turns on to engender transition 26 of fig2 . during this transition transistors 17 - 20 form a regenerative combination that acts to rapidly pull nodes 22 and 23 high . as node 23 rises it will turn transistor 18 off so as to allow transistor 17 to snap node 22 high . inverter 21 responding to node 22 produces a logic zero at terminal 13 . the parameters of transistors 17 - 19 are selected so that transition 26 occurs at about 1 . 1 volts which is higher than a ttl logic zero of 0 . 8 volt but lower than the ttl logic reference of 1 . 4 volts . from the above it can be seen that the circuit hysteresis is 0 . 5 volt . simulation of the circuit of fig1 shows that over the temperature range of - 40 ° c . to 105 ° c ., the supply voltage range of 4 . 5 to 5 . 5 and the maximum processing variables that affect transistor threshold values , transition 25 occurred at 1 . 6 volts ± 0 . 35 volt , transition 26 occurred at 1 . 1 volts ± 0 . 25 volt , and the hysteresis voltage varied over the range of 0 . 3 volt minimum to slightly over 1 volt maximum . fig3 shows the invention embodied in cmos p well construction . in this form of construction all of the p channel transistors back gates ( not shown ) are returned to the substrate which is connected to + v cc . n channel transistors 14 &# 39 ;, 18 &# 39 ;, 19 &# 39 ;, and 20 &# 39 ; have their back gates returned to their sources . this eliminates body effect in these n channel transistors . in turn this simplifies the ratioing of transistors 19 &# 39 ; and 20 &# 39 ; which controls the potential present at node 23 . it furthermore permits scaling transistors 17 &# 39 ;- 20 &# 39 ; up so as to increase the circuit speed . in such scaling the w / l ratios should be maintained so that the transitions 25 and 26 of fig2 are unchanged . fig4 shows an alternative n well cmos construction embodiment of the invention . the circuit is similar to that of fig1 except that the gate of transistor 17 is grounded . this means that transistor 17 is always turned on so that it acts as a resistor . thus when transistor 18 is off , node 22 will be pulled up towards node 16 . fig5 illustrates the embodiment of fig1 with a power down circuit added . terminal 25 has been added to control the circuit operation . pwr dwn is applied to terminal 25 so that it is normally high . this turns transistor 26 on and transistor 27 off . thus , circuit 15 &# 39 ; will operate normally as did circuit 15 of fig1 . the value of v ref at the output of inverter 33 will adjust v ref for ttl signal input levels . n channel transistor 26 is ratioed to provide a negligible &# 34 ; on &# 34 ; resistance compared to resistors 28 and 29 . when the pwr dwn signal at terminal 25 goes low , for a power down condition , transistor 26 turns off and transistor 27 turns on . this pulls the input to inverter 30 high so that the output from inverter 33 also goes high . as a result of this action , node 35 is pulled close to + v cc by conduction in transistor 34 . since conduction in transistor 27 has pulled the gate of transistor 31 high it will be off so that inverter 30 will not pass any current . thus inverter 30 , and therefore circuit 15 &# 39 ;, is disabled by pulling its input high . the input to inverter 33 is so low that it does not draw any power either . in the power down state node 16 will also be close to + v cc . the currents passed by the schmitt triggers connected to node 16 will then be determined by their input states . for example , if the trigger input terminal 12 is returned to + v cc through a conventional pull up device , transistor 17 will be turned off so that no power drain occurs . this action will also turn transistors 18 and 19 on so that node 22 will be pulled low . if terminal 12 is returned to ground by means of a conventional pull down device , transistors 18 and 19 will be off so that no current flows and transistor 17 will be on so as to pull node 22 high . however , since node 22 has two series transistors to + v cc it might not go sufficiently close to v cc to turn inverter 21 completely off . for this reason transistor 36 is added to inverter 21 to form a soft latch . when terminal 13 goes low it turns transistor 36 on so as to pull node 22 sufficiently close to + v cc to fully turn inverter 21 off . the invention has been described and several embodiments detailed . when a person skilled in the art reads the foregoing description , alternatives and equivalents , within the spirit and intent of the invention , will become apparent . accordingly , it is intended that the invention be limited only by the claims that follow .