fig1 is a block diagram showing an example of a communication controller having a microprocessor of the present invention . a communication controller 8 is connected between a host computer 9 and a network 11 . the communication controller 8 is constructed of a microprocessor 1 , an instruction memory 2 , a local memory 3 , a buffer memory 5 , a host computer interface 6 , an mac . lsi 7 and a control bus 4 . the instruction memory 2 stores instruction sets ( microprograms ) to be executed by the microprocessor 1 . the buffer memory 5 stores data to be transmitted , and received data . the mac . lsi 7 interfaces with the network 11 . the host computer interface 6 interfaces with the host computer 9 . the control bus 4 interconnects the microprocessor 1 , local memory 3 , buffer memory 5 , mac . lsi 7 and host computer interface 6 . the microprocessor 1 controls communications by processing a communications protocol or the like , in accordance with instruction sets stored in the instruction memory 2 . fig2 is a block diagram showing the detailed structure of the microprocessor 1 shown in fig1 . the microprocessor 1 is constructed of a sequencer 10 , a memory access control unit 50 , a bus controller 80 , an alu 20 , condition code registers 40 , general registers 30 , a bus buffer 60 and an internal data bus 70 . the sequencer 10 controls the internal operations of the microprocessor 1 in accordance with an instruction read from the external instruction memory 2 . the memory access control unit 50 controls access to the external buffer memory 5 and local memory 3 . the bus controller 80 interfaces with the control bus 4 . the alu 20 is provided with a function of executing high speed modulo operations to be described later . the condition code registers 40 temporarily store comparison operation results . the general registers 30 temporarily store operation data . the bus buffer 60 temporarily stores memory - accessed data . the internal data bus 70 interconnects the general registers 30 , alu 20 , sequencer 10 and bus buffer 60 . the function of alu 20 will be described below , the function of alu 20 being provided when the microprocessor 1 executes the transport protocol , class 4 ( hereinafter called tp4 ) of the open systems interconnection ( osi ) communication protocol ( layer 4 ). first , the outline of tp4 will be described . fig3 is a diagram showing a data transfer protocol sequence of tp4 . a data transmitting station txst sequentially transmits data in the form of dt packets , each assigned a particular sequence number . sequence numbers are assigned to dt packets in ascending order . after a predetermined maximum number , the sequence number resets to 0 . in tp4 , if the sequence number has a general format represented by seven bits for example , it cyclically changes its value from a maximum 127 to a minimum 0 . upon reception of a dt packet , a data receiving station rvst returns an ak packet to the transmitting station txst . the ak packet contains the sequence number of a dt packet expected to be received next and the number of packets capable of being received in succession ( hereinafter , this number of packets will be called a credit number cdt ). upon reception of the ak packet from the receiving station rvst , the data transmitting station txst can recognize that the data was correctly transmitted to the receiving station rvst . the data transmitting station txst can successively transmit data ( dt packets ) falling within a predetermined range ( hereinafter called a window ), without waiting for reception of an at packet . examples of the formats of the dt and ak packets are shown in fig4 a and 4b . fig5 is a schematic diagram showing a window at a time point a shown in fig3 . the transmitting station can recognize , from the contents of the packet ak 127 received just before the time point a , that the transmitted packets up to the packet dt126 were correctly received by the destination station , and can recognize , from the credit value cdt &# 34 ; 15 &# 34 ; informed by the received packet ak127 , that packets up to the packet dt13 can be transmitted in succession without waiting for a new ak packet from the destination station . each time the transmitting station transmits a dt packet , the sequence number is updated , and each time the transmitting station receives an ak packet from the destination station , the window is slid . in this specification , such an operation is called a &# 34 ; window control process &# 34 ;. in this embodiment , the window control process is executed using four parameters , including a transmission state variable vs , a window lower limit value lwe , a window upper limit value uwe and a credit value cdt . the transmission state variable vs indicates the sequence number nr of a dt packet to be transmitted next . the window lower limit value lwe indicates the sequence number of a dt packet expected to be responded next , and is equal to the sequence number nr of the ak packet last received . the window upper limit value uwe indicates the maximum sequence number of a dt packet up to which dt packets can be transmitted in succession without waiting for reception of an ak packet , and is equal to the number of the window lower limit value lwe added to the credit value cdt . the credit value cdt indicates the number of dt packets which the destination station can receive , and is informed by the ak packet last received . one of the objects of the present invention is to speed up the window control process . fig6 is a flow chart showing the window control process to be executed by the communication controller at the time of transmitting a dt packet . when transmitting a dt packet , it is first judged whether the transmission state variable vs is within a predetermined range defined by the window lower and upper limit values lwe and uwe ( step 1000 ). if the transmission state variable vs is within that range , it indicates a dt packet transmission ready state . after transmitting a dt packet of transmission data having the format shown in fig4 a and an assigned sequence number nr ( step 1001 ), the transmission state variable vs is incremented by 1 to prepare the next transmission ( step 1002 ). at this time , modulo operation is executed . namely , if the transmission state variable vs incremented by 1 exceeds a predetermined maximum value , it is set to &# 34 ; 0 &# 34 ;. if it is judged at the step 1000 that the transmission state variable vs is not within the predetermined range defined by the window lower and upper limit values lwe and uws , it indicates a dt packet transmission inhibited state . therefore , the data transmission is inhibited until a new ak packet is received ( step 1003 ). fig7 is a detailed flow chart of the judgment process at the step 1000 shown in fig6 . this flow chart shows the judgment process by a conventional microprocessor having an embedded alu with a two - input operation function , the judgment process judging whether a transmission state variable vs is between the window lower and upper limits values lwe and uwe . as seen from fig7 in judging whether the variable vs is between the lower and upper limit values lwe and uwe ( three - input modulo comparison process ), the conventional microprocessor requires a routine of six comparison judgment steps 1000 - 1 to 1000 - 6 . this routine needs to execute a microprogram having a plurality of instructions . fig8 is a flow chart showing the window control process to be executed by the communication controller upon receiving an ak packet . when receiving an ak packet , the sequence number nr and credit value cdt are extracted from the received ak packet ( step 1004 ), and thereafter , it is checked whether the sequence number nr is correct ( step 1005 ). if the sequence number nr is not correct , an error process is executed ( step 1008 ). if correct , the sequence number nr is used as a new window lower limit value lwu ( step 1006 ), and the new window lower limit value lwu added to the credit value cdt is used as a new window upper limit value uwe ( step 1007 ). at this time , modulo operation is executed . fig9 is a detailed flow chart showing the ak packet sequence number nr check operation by a conventional microprocessor having an embedded alu with a two - input operation function ( two - input alu ). as seen from this flow chart , the conventional microprocessor requires six comparison judgment steps 1005 - 1 to 1005 - 6 for the modulo - based sequence number nr judgment process . similar to the above - described transmission state variable judgment , it is necessary to execute a microprogram having a plurality of instructions . fig1 is a connection block diagram of the alu 20 of the present invention . alu 20 has a three - input modulo operation function in addition to a conventional two - input operation function , for allowing a high speed window control process . alu 20 is provided with three data input ports a , b and c , one data output port f , an input enable signal line ie , inputs lines for an operation command cmd and output enable signal oe , and output lines for a carry output flag cf , a zero output flag zf and comparison judgment flag tf . in this embodiment , the data input ports a , b and c and data output port f are connected to four independent internal data busses 70 ( bus a , bus b , bus c and bus f ). the operation command cmd , input enable signal ie and output enable signal oe are supplied from the sequencer 10 . the carry output flag cf , zero output flag zf and comparison judgment flag tf are input via the condition code registers 40 to the sequencer 10 . next , a description will be given for an operation by the sequencer 10 of activating alu 20 , according to the embodiment . fig1 a and 11b show examples of the formats of macro instructions for the window control process to be executed by the sequencer 10 . in this embodiment , as the window control process instruction , there are prepared three types of instructions , including a modulo addition instruction madd , a modulo subtraction instruction msub and a three - input modulo comparison instruction mcmpn . the modulo addition and subtraction instructions madd and msub are used for updating the sequence number and window for example . the three - input comparison instruction mcmpn is a single instruction for a window check at the time of transmitting a dt packet ( process at the step 1000 shown in fig6 ) or a validity check at the time of receiving an ak packet ( process at the step 1005 shown in fig8 ). in this embodiment , such a macro instruction processes data stored in some of the general registers 30 within the microprocessor 1 . as shown in fig1 a , the modulo addition / subtraction instruction ( modulo addition instruction madd or modulo subtraction instruction msub ) is constructed of an inst field for storing an instruction code representative of the type of operation , s1 and s2 fields for storing the numbers of two registers storing two operation data , a mod field for storing the number of a register storing mask data necessary for modulo operation , and a dst field for storing the number of a resister which stores the operation results . the value of the register number stored in the mod field takes one of the values from &# 34 ; 0 &# 34 ; to &# 34 ; 2 n - 1 &# 34 ; in this embodiment . as shown in fig1 b , the three - input comparison instruction mcmpn is constructed of an instruction code inst field , s1 , s2 and s3 fields for storing the numbers of registers storing comparison data , and an adr field for storing a jump address of an instruction to be executed next if the comparison results do not meet the conditions . in the embodiment , as the three - input comparison instruction mcmpn , the following four instructions are provided by way of example to allow flexible setting of boundary values : mcmp3 instruction for judging whether a relation s1 & lt ; s2 ≦ s3 is satisfied ; and mcmp4 instruction for judging whether a relation s1 & lt ; s2 & lt ; s3 is satisfied . these judgment instructions are used not for comparing three values , but for judging whether a parameter value is within a range defined by the window upper and lower limit values . next , the control operation of the sequencer 10 to execute an instruction will be described with reference to the flow charts shown in fig1 to 14 . referring to fig1 , the sequencer 10 retrieves an instruction to be executed , from the instruction memory 2 ( step 1010 ), and decodes its instruction code inst field ( step 1011 ). if the retrieved instruction is a modulo addition instruction madd or modulo subtraction instruction msub , the contents of the registers designated by the fields s1 , s2 and s3 are output in parallel to the busses a , b and c , respectively ( step 1015 ) shown in fig1 . the input enable signal ie , output enable signal oe and operation command cmd are supplied to alu 20 ( step 1016 ). next , the operation results output from alu 20 are transferred via the bus f to the registers designated by the dst field ( step 1017 ). if the retrieved instruction is a three - input comparison instruction mcmpn , the contents of the registers designated by the s1 , s2 and s3 fields are output in parallel to the busses a , b and c , respectively ( step 1018 ) shown in fig1 . the input enable signal ie and operation command cmd are supplied to alu 20 ( step 1019 ). next , the state of the judgment flag tf representing the three - input comparison results of alu 20 is fetched from the condition code register 40 to check the comparison results ( step 1020 ). in this case , if the judgment flag tf bit is &# 34 ; 1 &# 34 ;, an instruction immediately after the presently executed instruction is used as an instruction to be executed next , and if not &# 34 ; 1 &# 34 ;, an instruction at the address designated by the adr field is used as an instruction to be executed next ( step 1021 ). if in the flow chart shown in fig1 , the command is none of the modulo addition and subtraction instructions madd and msub and three - input comparison instruction mcmpn , a two - input operation is executed ( step 1014 ). the internal structure of alu 20 will be described with reference to fig1 . alu 20 is constructed of a first input latch a 100 , a second input latch b 200 , a third input latch c 300 , an instruction decoder 800 , a three - input alu 400 , a two - input alu 500 and an output latch 700 . the first input latch a 100 , second input latch b 200 and third input latch c 300 latch the data on the busses a , b and c , respectively connected to alu 20 , in response to the input enable signal ie from the sequencer 10 . the instruction decoder 800 decodes an operation command cmd from the sequencer 10 , and outputs a control signal cmd3 if the operation command is a modulo addition / subtraction instruction ( madd / msub ) or three - input comparison instruction ( mcmpn ), or a control signal cmd2 if it is a two - input operation command . the three - input alu 400 responds to the control signal cmd3 from the instruction decoder 800 , and executes an operation using three data in the first to third input latches . the two - input alu 500 responds to the control signal cmd2 , and executes an operation using two data in the first and second input latches . the output latch 700 responds to the output enable signal oe from the sequencer 10 and an output from the decoder 800 , and selectively outputs the data from the three - input alu 400 or two - input alu 500 to a data output port f . the three - input alu 400 is constructed , for example as shown in fig1 , of a modulo adder - subtracter 401 , a three - input comparator 450 , and an instruction decoder 460 . this instruction decoder 460 supplies activation instructions cmd3 &# 39 ; and cmd3 &# 34 ; to the modulo adder / subtracter 401 and three - input comparator 450 , respectively , in accordance with the contents of the operation command cmd3 output from the decoder 800 shown in fig1 . the modulo adder / subtracter 401 receives data latched at a port a ( input latch a ) and port b ( input latch b ) as addition / subtraction data , and data latched at a port c ( input latch c ) as mask data for modulo operation , the operation results f1 being output to the output latch 700 . the three - input comparator 450 receives data latched at the ports a and b as the window upper and lower limit values , and data latched at the port b as the data to be judged . the comparator 450 judges whether the data received at the port b is within the range defined by the window upper and lower limit values , and outputs the judgment results as the tf bit . fig1 is a flow chart showing the internal operation of alu 20 . alu 20 first decodes an operation command cmd supplied from the sequencer 10 ( step 1030 ). if the operation command is a modulo addition / subtraction instruction ( madd / msub ), the modulo adder / subtracter 401 in the three - input alu 400 starts operating upon reception of the control signal cmd &# 39 ; from the decoder 401 , and receives data on the busses a , b and c latched by the input latches 100 , 200 and 300 , the operation results being output to the bus f via the output latch 700 ( step 1033 ). if the operation command is a three - input comparison instruction mcmpn , the three - input comparator 450 in the three - input alu 400 starts operating upon reception of the control signal cmd &# 34 ; from the decoder 460 , and receives data on the busses a , b and c , the comparison results being output as the tf bit ( step 1034 ). if the operation command is none of the modulo addition / subtraction instruction and three - input comparison instruction , the two - input alu starts operating upon reception of the control signal cmd2 from the decoder 800 , and receives data on the a and b , the operation results being output to the bus f . if a carry generates during this operation , the cf bit is output , and if the operation results indicate &# 34 ; 0 &# 34 ;, the zf bit is output ( step 1035 ). the modulo adder / subtracter 401 is constructed of an adder / subtracter 402 and an and gate 403 , this combination performing modulo addition / subtraction . the adder / subtracter 402 performs either an addition operation or subtraction operation of two data input from the ports a and b . the and gate 403 obtains a logical multiplication of the outputs from the adder / subtracter 402 and from the port c for each bit . for example , in the case of modulo 128 , the operation results to be output are 127 + 2 = 1 , 1 - 127 = 2 , and so on . the three - input comparator 450 is constructed of an a : b comparator 451 , a b : c comparator 452 , an a : c comparator 453 , an a ≦ b & lt ; c judgment circuit 454 , an a ≦ b ≦ c judgment circuit 455 , an a & lt ; b ≦ c judgment circuit 456 , an a & lt ; b & lt ; c judgment circuit 457 , and a selector 458 . the a : b comparator 451 compares input data from the ports a and b . the b : c comparator 452 compares input data from the ports b and c . the a : c comparator 453 compares input data from the ports a and c . in accordance with the comparison results by the comparators 451 to 453 , the four judgment circuits 454 to 457 judge whether the data b is within the range defined by the window lower and upper limits values a and c . the selector 458 selects the judgment results for the operation command cmd ( control signal cmd3 &# 34 ;), from the judgment results by the judgment circuits 454 to 457 , and outputs them as the tf bit . for example , for the tp4 communications protocol , a judgment a ≦ b & lt ; c is made during the window control process at the time of transmitting a dt packet , and a judgment a & lt ; b ≦ c is made during the window control process at the time of receiving an ak packet . in this embodiment , in addition to such a judgment function , the a ≦ b ≦ c and a & lt ; b & lt ; c judgment circuits are prepared to allow flexible dealing with various requirements for judgment conditions at boundary points ( equal values ). fig2 is a table showing a relation between input conditions and output signals of the a : b , b : c and a : c comparators 451 , 452 and 453 . fig2 shows an example of the circuit structure of the a ≦ b & lt ; c judgment circuit 454 , and fig2 is a table showing a relationship between input signals and output signal . fig2 shows an example of the circuit structure of the a ≦ b ≦ c judgment circuit 455 , and fig2 is a table showing a relation between input signals and output signal . fig2 shows an example of the circuit structure of the a & lt ; b ≦ c judgment circuit 456 , and fig2 is a table showing a relation between input signals and output signal . fig2 shows an example of the circuit structure of the a & lt ; b & lt ; c judgment circuit 457 , and fig2 is a table showing a relation between input signals and output signal . fig2 a to 29e are timing charts of the operation by alu 20 of the embodiment , showing timings of data inputs to the ports a , b and c , alu operation and operation result output . according to the above - described embodiment , alu 20 has hardware for modulo addition , subtraction and three - input comparison operations , as well as conventional two - input operation . therefore , the window control process necessary for the communication controller can be performed using simple instruction sets . furthermore , a plurality of independent internal data busses 70 are provided within the microprocessor 1 , and a plurality of data necessary for operation are supplied in parallel to alu as shown in fig2 a to 29c . therefore , the time period necessary for a ready state of instruction execution can be shortened , providing the operation results quickly . fig3 shows the internal structure of a microprocessor 1 according to the second embodiment of the present invention , in which an internal bus 70 is shared by all ports of an alu . in this embodiment , alu 20 controls data inputs to ports a , b and c in accordance with three input enable signals iea , ieb and iec supplied from a sequencer 10 . fig3 shows an example of the internal structure of alu 20 shown in fig3 . the input enable signal iea controls data input to an input latch a . similarly , the input enable signal ieb controls data input to an input latch b , and the input enable signal iec controls data input to an input latch c . the other structure of alu 20 is the same as that of the first embodiment . next , the operation flow of the sequencer 10 of this embodiment will be described below . the operation of retrieving an instruction from the instruction memory 2 and decoding it is the same as the first embodiment described with fig1 . fig3 is a flow chart showing the control operation by the sequencer 10 of issuing a modulo addition instruction madd or modulo subtraction instruction msub to alu 20 . the sequencer 10 outputs the contents of the register designated by the s1 field of an instruction read from the instruction memory 2 , to the internal data bus 70 , and outputs the input enable signal iea to alu 20 , to thereby input data on the data bus to the port a ( input latch a ) of alu 20 ( step 1040 ). next , the sequencer 10 outputs the contents of the register designated by the s2 field to the internal data bus 70 , and outputs the input enable signal ieb to alu 20 , to thereby input data to the port b of alu 20 ( step 1041 ). similarly , the sequencer 10 outputs the contents of the register designated by the s3 field to the internal data bus 70 , and outputs the input enable signal iec to alu 20 , to thereby input data to the port c of alu 20 ( step 1042 ). next , an instruction command cmd is supplied to alu 20 ( step 1043 ), and an output enable signal oe is supplied to alu 20 while stopping the data output from the general registers 30 to the internal data bus 70 ( step 1044 ). data output from alu 20 to the internal data bus 70 is transferred to the register designated by the dst field ( step 1045 ). fig3 is a flow chart showing the control operation by the sequencer 10 of issuing a three - input modulo comparison instruction to alu 20 . the sequencer 10 outputs the contents of the register designated by the s1 field of an instruction read from the instruction memory 2 to the internal data bus , and outputs the input enable signal iea to alu 20 , to thereby input data to the port a of alu 20 ( step 1050 ). next , the sequencer 10 outputs the contents of the register designated by the s2 field to the internal data bus 70 , and outputs the input enable signal ieb to alu 20 , to thereby input data to the port b of alu 20 ( step 1051 ). similarly , the sequencer 10 outputs the contents of the register designated by the s3 field to the internal data bus 70 , and outputs the input enable signal iec to alu 20 , to thereby input data to the port c of alu 20 ( step 1052 ). next , an instruction command cmd is supplied to alu 20 ( step 1053 ), and the state of the judgment flag tf representing the three - input comparison results of alu 20 is fetched from the condition code register 40 to check the comparison results ( step 1054 ). in this case , if the judgment flag tf bit is &# 34 ; 1 &# 34 ;, an instruction immediately after the presently executed instruction is used as an instruction to be executed next , and if not &# 34 ; 1 &# 34 ;, an instruction at the address designated by the adr field is used as an instruction to be executed next ( step 1055 ). fig3 a to 34e are timing charts showing the operation of alu 20 of the second embodiment . in this embodiment , the microprocessor has a single internal data bus 70 , and data for three - input operation cannot be supplied to alu in parallel . therefore , data inputs to the ports a , b and c , alu operation and operation result output are sequentially executed . however , three - input operation can be executed by using a single instruction to alu 20 . in the first and second embodiments , mask data necessary for modulo addition / subtraction is supplied to the data input port c of alu 20 each time a modulo operation is carried out . there are some cases where the modulo value used in a communications protocol is not changed once it is determined by negotiation with a communications partner apparatus . in such a case where the modulo value is used as fixed value data during communications operation , the operation of inputting the modulo value to alu 20 each time a modulo operation is carried out , is redundant . particularly in the case where a plurality of data are sequentially supplied as in the case of the second embodiment , such operation becomes one of the reasons for increased operation time . in the third embodiment , mask data necessary for modulo operation is stored in alu . as shown in fig3 , a modulo adder / subtracter 401 is constructed of an adder / subtracter 402 and and gate 403 like those shown in fig1 , a mask data register 404 for storing data input to the port a , and an instruction decoder 405 . the instruction decoder 405 responds to an initialization instruction and an addition / subtraction instruction supplied from the sequencer 10 , and selectively activates the mask data register 404 or adder / subtracter 402 . in this embodiment , the sequencer 10 supplies the initialization instruction to alu prior to processing a communications protocol , to initially set the modulo value to the mask data register 404 . thereafter , when the modulo adder / subtracter 401 receives a modulo addition / subtraction instruction from the sequencer 10 , it outputs the mask data in the mask data register 404 to the and gate 403 . according to this embodiment , the mask data necessary for modulo addition / subtraction is first stored in alu 20 for later use . therefore , it is not necessary to externally supply mask data to alu 20 each time a modulo operation is carried out , thereby reducing an operation time . as appreciated from the foregoing description , according to the present invention , there are provided an alu to be used for modulo addition , subtraction and comparison , and specific instructions for such modulo operations . alu and microprocessor suitable for executing a communications protocol can thus be realized .