fig1 is a block diagram showing the association of the hardware utilized by the present invention with a portion of the hardware utilized by the invention described and the above mentioned copending application for &# 34 ; method and apparatus for performing binary equalization in voice - band phase - modulated modems &# 34 ;. the x and y components of a received vector symbol , corrected as explained in the above mentioned patent application are received on lines 15 , 13 by selectors 17 and 19 , respectively . the output of selector 17 on line 21 goes to the x component normalizer 25 . the output , on line 23 , of selector 19 goes to the y component normalizer 27 . the normalizer circuitry 25 , 27 for the x and y components are fully described in the above noted copending patent application . the output of each normalizer circuit is magnitude and a sign indication for the component . thus , normalizer 25 has a sign indication on line 29 and a magnitude indication on line 31 for each received x component . normalizer 27 has a sign indication on line 33 and a magnitude indication on line 35 for each received y component . the sign and magnitude indications from both normalizers are supplied to a multiplier - adder circuit 36 and is well known in the art and will not be further described herein except to say that it is the same type of multiplier - adder circuit utilized in the above referenced copending patent application . the multiplier - adder 36 multiplies the difference between x and y magnitudes by the constant0 . 707 and the sum of the x and y magnitudes by the constant 0 . 707 to generate a 45 ° rotated x component value on line 39 and a 45 ° rotated y component value on line 41 . a 0 . 707 constant generator 37 supplies a binary 0 . 707 value on line 38 to the multiplier - adder circuit 36 . these rotated x and y values are supplied as inputs to selectors 17 and 19 , respectively . the multiplier - adder 36 comes into play only after the corrected x , y components on lines 15 and 13 have been selected by selectors 17 and 19 to be sent to normalizers 25 and 27 . the output from these normalizers is sent to address a location read - only memory ( rom ) 45 and an ideal point and phase read - only memory ( rom ) 53 . the location rom 45 is addressed by the magnitude of the x component on line 31 and the magnitude of the y component on line 35 . the location rom 45 generates binary indications on lines 47 , 49 and 51 , as explained in the above noted copending patent application . this information , in conjunction with the sign information on lines 29 and 33 addresses the ideal point and phase rom 53 . this memory contains the ideal x and y components of the received symbol and generates these x and y components on lines 55 , 57 , respectively . line 59 carries the ideal phase of the symbol vector represented by the x and y components on lines 55 and 57 . this entire operation of generating the ideal x and y components and phase angle upon receiving the corrected x and y components is more fully explained in the above noted copending patent application . the ideal x component on line 55 is supplied to a full adder 73 . the other input to the adder 73 being the normalized magnitude of the x component from normalizer 25 . the ideal x component line 55 carries the x value in its 2 &# 39 ; s complement form . thereby , the addition operation by full adder 73 generates a difference indication on line 77 that is supplied to demultiplexer 81 . likewise , the ideal y component on line 57 is supplied to a full adder 75 in 2 &# 39 ; s complement form , the other input to full adder 75 being the magnitude of the y component from the y normalizer 27 . the output of the full adder 75 on line 79 is a difference indication between these two values . this indication is supplied to demultiplexer 83 . the select signal on line 11 , besides direction selectors 17 and 19 to choose the x and y components on lines 15 and 13 , directs demultiplexers 81 and 83 to pass the information on lines 77 and 79 to lines 85 and 91 , respectively . line 85 and 91 are the input lines to the e x storage register 93 and the e y storage register 97 , respectively . upon the e x value being stored in register 93 and the e y value being stored in register 97 , the control signal on line 11 directs selectors 17 and 19 to pass the rotated component values on lines 39 and 41 to the normalizers 25 and 27 , respectively . the output of the x normalizer 25 is a sign indication on line 29 and a magnitude indication on line 35 of the rotated x component . the sign indication on line 33 and the magnitude indication on line 35 are of the rotated y component . these rotated x and y components relate to the x and y components previously received on lines 15 and 13 which caused the rotated x and y components to be generated by the multiplier - adder 36 . these rotated x and y component values are now utilized to address the location rom 45 and the ideal point and phase rom 53 , in the same manner that the unrotated x and y component values were utilized . the magnitudes of the rotated x component on line 31 and the magnitude of the rotated y component on line 35 address rom 45 causing it to read out binary information on lines 47 , 49 and 51 . this information along with the sign information of the rotated x and y components on lines 29 and 33 , respectively , cause the ideal point and phase rom 53 to generate the ideal x and y components on lines 55 and 57 . the select signal on line 11 inhibits the ideal point and phase rom 53 from generating on ideal phase indication on line 59 at this time . as is explained in the above noted copending patent application , the ideal phase indication is stored in the phase store register 61 and compared with the ideal phase indication from the previously received vector symbol by full adder 65 which generates a phase differential indication on line 67 . this phase differential is supplied to a grey code converter circuit 69 . this grey code converter 69 , upon receiving an amplitude indication on line 47 and the differential phase indication on line 67 , generates binary data on line 71 . at the time that the rotated x and y components are being utilized to address the location rom 45 and the ideal point and phase rom 53 , the grey code converter 69 is not generating data . the output of the ideal point and phase rom 53 , in response to the rotated x and y components being processed is an ideal rotated x component on line 55 and an ideal rotated y component on line 57 . the magnitude of the rotated x component is received on line 31 by full adder 73 . the magnitude of the rotated y component is received on line 35 by full adder 75 . full adder 73 generates a difference indication between these two values on line 77 for the x component , thereby generating an e x φ value . full adder 75 generates a difference indication between the y magnitudes on line 55 , thereby generating an e y φ value . demultiplexer 81 , in response to the control signal on line 11 routes the e x φ information on line 77 to the e x φ storage register 95 by way of line 87 . likewise , the demultiplexer 83 routes the e y φ information on line 79 to the e y φ register 99 by way of input line 89 . the contents of e x storage register 93 , the e x φ storage register 95 , the e y register 97 and the e y φ register 99 are supplied over lines 101 , 103 , 105 and 107 respectively , to a selector 109 that connects either the e x , e y , values or the e x φ , e y φ , values to its output lines 111 , 112 . the values on lines 111 and 112 are utilized to calculate the equalization constants that correct the raw x and y components representing the received vector symbol . such operation is fully explained in the above noted copending patent application . whether the e x , e y information or the e x φ , e y φ information is selected , depends upon the signal on line 153 supplied to selector 109 from flip - flop 151 . the e x φ and e y φ from registers 95 , 99 , respectively , are selected only when it has been determined that a phase - jump has occurred in the communication link . the following procedure is utilized to determine whether a phase - jump has occurred . the e x , e x φ , e y and e y φ values in registers 93 , 95 , 97 and 99 , respectively are supplied to logic circuitry 113 , 115 , 117 and 119 , respectively . these logic circuits generate the absolute magnitude of the binary information in the registers 93 , 95 , 97 and 99 , respectively . the absolute magnitude of e x from logic circuitry 112 is supplied , over line 121 , to a full adder 129 . line 123 supplies the e x φ absolute magnitude , line 125 supplies the e y magnitude and line 127 supplies the e y φ magnitude to the full adder 129 . the full adder 129 generates a pair of output indications , for convenience called a and b on lines 131 and 133 , respectively . the a indication represents the binary sum of the absolute values of e x and e y . the b indication represents the binary sum of the absolute values of e x φ and e y φ . these a and b values are supplied to a comparator circuit 135 that generates an a & gt ; b signal on line 137 , and an a & lt ; b signal on line 139 . as long as the b indication is larger or equal to the a indication , no phase - jump is assumed to have occurred . however , if the a indication becomes larger than the b indication , a phase - jump is indicated . if a is smaller than b the signal on line 139 passes through conditional complement logic 141 onto line 143 causing a reset counter 147 to generate a signal on line 149 which is supplied to flip - flop 151 . the flip - flop 151 generates a signal on line 153 which is supplied to the selector 109 , directing the selector to choose the e x and e y values from registers 93 , 97 , respectively for connection to lines 111 and 112 . the signal on line 153 is also transmitted to signal quality indicator logic 157 that will pass the a indication received on line 131 to line 159 , this a value indicating the quality of the vector symbol received . if the a indication happens to be larger than the b indication , the signal on line 137 from comparator 135 passes through the conditional complement logic 141 which generates a signal on line 145 , causing the reset counter 147 to start counting . counter 147 will continue counting for as long as the signal on line 145 indicates that a is larger than b . upon the passage of ten comparisons , the counter 147 generates a signal on line 149 that causes flip - flop 151 to generate a signal on 153 . the signal on 153 directs selector 109 to connect the e x φ , e y φ values out of registers 95 , 99 , respectively 95 , 99 , respectively , to lines 111 and 112 . the signal output , on line 155 , of flip - flop 151 directs the signal quality indication logic 157 to select the b indication on line 133 as the value to be supplied to line 159 , this b value indicating the quality of the received vector symbol . the output signal of flip - flop 151 on line 153 is fed back to the conditional complement logic 141 to switch line 139 to the a greater than b line and line 137 to the a less than b line , since the rotated x and y components are now the correct x and y components acting as the standard against which future rotation must be checked . the constant generator 37 is shown in fig2 as consisting of an eight bit parallel - in / serial - out shift register that stores the binary indication for the decimal fraction 0 . 707 . it should be understood that this constant is utilized for the detection of 45 ° phase jumps . for systems that utilize other than 45 ° spacing between the phase vectors , different appropriate constants must be utilized . a source of clock signals on line 167 clocks the binary information stored therein , in serial fashion , out of the q 8 output on lines 39 of the register 166 . register 166 receives a binary zero , at its 1 , 3 , 6 and 8 inputs and a binary 1 at its 2 , 4 , 5 and 7 inputs . the number 1 input acts as a sign bit . the number 2 input is the most significant bit of the fraction 0 . 707 . the serial output of the register 166 would be most significant bit first in this order : 01011010 . this string of binary ones and zeros represents the decimal point fraction 0 . 707 . the binary 0 . 707 constant is clocked out of the register 166 after a load command is received on line 161 . the constant on line 39 is supplied to both a rotated x multiplier - adder circuit 171 and a rotated y multiplier - adder circuit 173 ( fig3 ). a rotated x component value is generated by multiplier - adder circuit 171 in accordance with the equation : the 45 ° rotated y component value is generated by multiplier - adder circuit 173 according to the equation : for a rotation of 45 °, k 1 = cos45 °, k 2 = sin 45 ° the multiplier - adder 171 for generating the 45 ° rotated x component value on line 41 , receives a multiply command signal on line 169 , a sign of y component indication on line 33 , a y magnitude indication on line 35 , a sign of x component indication on line 29 , and an x magnitude indication on line 31 . the magnitudes of the x and y components on lines 31 and 35 respectively are loaded into the multiplier - adder 171 least significant bit first . the multiplier - adder 173 for generating the 45 ° y rotated component on line 39 also receives the x and y component magnitude signals least significant bit first , on lines 31 and 35 , respectively . it receives the sign of x and sign y information on lines 29 and 33 , respectively . multiplier - adder 171 receives a multiply command at inputs 1 and 2 . it receives the sign of y information at input 3 , the y magnitude information , least significant bit first , an input 4 , a 0 . 707 constant information at input 5 , the sign of x information at input 6 , the x magnitude information at input 7 and a 0 . 707 constant information at input 8 . multiplier - adder 173 receives a multiply command at inputs 1 and 2 , the sign of y information at input 3 , magnitude of y information at input 4 , 0 . 707 constant information at input 5 , sign of x information at input 6 , magnitude x information at input 7 and 0 . 707 constant information at input 8 . upon a multiply command indication on line 169 , the multiplier - adder chips 171 , 173 , respectively generate the 45 ° rotated x component and y component values on lines 41 and 39 . these rotated x and y components values are supplied to selectors 17 and 19 , respectively ( fig1 ) from where they are supplied to the normalizers and furtheron , as above described . upon full adder 73 ( fig1 ) generating the e x φ value , the magnitude information is placed on parallel lines 87 and routed into e x φ storage register 95 by a load command on line 177 and select signal on line 178 directing selector 176 ( fig4 ) to connect input lines 87 to its output lines . the e x φ register 95 is a parallel in / serial - out shift register that produces the e x φ values in serial fashion on output line 103 . upon full adder 75 generating the e y φ value on lines 89 , selector 176 ( fig4 ), in response to the control signal on line 178 connects lines 89 to its output lines . this information is loaded into the e y 101 register 99 in response to a load command on line 179 . the e y φ register 99 is a parallel - input / serial - output register that produces the binary values stored therein in serial fashion on line 107 . in addition to the magnitude of e x φ and e y φ information , the full adders 73 , 75 supply a sign indication for the e x φ and e y φ values on line 181 . these sign indications are stored in e x φ , e y φ sign storage register 183 . these sign indications which are one bit long are made available on lines 185 and 187 . where a is the signal quality indication for an unrotated symbol and b is the signal quality indication for the symbol rotated 45 °, the e x and e y information received from storage registers 93 , 95 , 97 and 99 ( fig1 ) must be converted into absolute magnitude indications . this is accomplished by an approximation of a 2 &# 39 ; s complement operation in which the e x , e y and e x . sup . φ and e y . sup . φ binary information is complemented conditionally on the basis of the sign indication for the respective magnitude indications . the e x magnitude indication is received by an exclusive or gate 113 on line 101 along with the sign of e x indication on line 191 . the output of exclusive or gate 113 is an absolute magnitude of e x indication on line 121 . the e y indication is received by an exclusive or gate 117 which also receives a sign of e y indication on line 193 . the output of the exclusive or gate 117 is a magnitude of e y indication on line 125 . exclusive or gate 115 receives a e x φ indication on line 103 and a sign of e x φ indication on line 185 generating an absolute magnitude e x φ indication on line 115 . likewise , exclusive or gate 119 receives a e y φ indication on line 107 and a sign e y φ indication on line 187 , generating in response thereto , an absolute magnitude of e y φ indication on line 127 . a double full adder 129 receives the binary information on lines 121 , 125 , 115 , 127 . in response to the e x and e y information on lines 121 and 125 , respectively , the full adder 129 generates the a signal quality indication on line 131 , least significant bit first . in response to the e x φ and e y φ information on lines 115 and 127 , respectively , the full adder 129 generates the b signal quality information on line 133 , least significant bit first . the e x , e y , e x φ and e y φ binary information is also supplied , to a selector 109 , over lines 101 , 105 , 103 and 107 . upon the control signal on line 153 indicating that a 45 ° phase - jump had occurred the selector 109 would respond thereto by disconnecting lines 101 and 105 from lines 111 and 112 and connecting lines 103 and 107 to lines 111 and 112 . lines 111 and 112 go to logic circuitry , described in the above - noted copending patent application , for calculating the equalization constants that are to be used in correcting the x and y components of the received vector symbols . an alternate preferred embodiment for the generator of a quality indication signal is apparatus for calculating the equation : the apparatus for generating the square of the rotated and unrotated e x and e y which is seen as well within the purview of a person of ordinary skill in the art and will not be disclosed herein . the a in - phase error indication and the b rotated error indication is received least significant bit first on lines 131 and 133 by an exclusive or gate 197 and a pair of and gates 201 , 199 ( fig6 ). the a and b indications from full adder 129 ( fig5 ) are generated simultaneously so that comparable bits are compared by exclusive or gate 197 ( fig6 ). whenever the bit received on line 131 is identical to the bit on line 133 , the output of exclusive or gate 197 , on line 196 , is a binary zero . this binary zero disables and gates 199 and 201 thereby causing binary zeros to be placed on lines 198 and 200 which go to the j and k inputs , respectively , of jk flip - flop 203 . at the time a clock pulse is received on line 195 by the jk flip - flop 203 the outputs q and q of the flip - flop will not change because of the binary zero signals on lines 198 and 200 . assuming now that the binary bit received on line 131 is a binary 1 while the bit received on line 133 , at the same time , is a binary zero , the output of exclusive or gate 197 is a binary 1 . this binary 1 level is supplied to and gates 201 and 199 causing these and gates to be enabled . and gate 201 will pass the binary 1 information on line 131 to line 198 . and gate 199 will pass the binary zero information on line 133 to line 200 . as a consequence of a binary 1 on line 198 and a binary zero on line 200 , at the time of occurrence of the next clock pulse on line 195 , the jk flip - flop 203 , irrespective of the previous outputs , will have a binary 1 output signal on line 204 and a binary zero output on line 202 . assuming now that the binary information on line 131 is a binary zero at the time that the binary information on line 133 is a binary 1 , exclusive or gate 197 will generate a binary 1 at its output on line 196 . this binary 1 information enables and gates 199 and 201 . as a consequence , and gate 201 passes the binary zero information on line 131 to the output line 198 and and gate 199 passes the binary 1 information on line 133 to its output line 200 . as a result of a binary zero on line 198 and a binary 1 on line 200 , at the occurrence of the next clock signal , on line 195 , the jk flip - flop 203 , irrespective of its previous output signals , will have a binary 1 on output line 202 and a binary zero on output line 204 . the above described interaction between exclusive or gate 197 , and gates 201 and 199 and jk flip - flop 203 occurs for all the bits of the a and b indications . as a consequence of this interaction , at the reception of the most significant bits of such a and b indications on lines 131 and 133 , respectively , the q and q outputs on line 204 and 202 , respectively , of jk flip - flop 203 indicate whether the a binary indication is larger than the b binary indication or the b indication is larger than the a indication . therefore , if , as a consequence of the most significant bits of the a and b indications being received on lines 131 and 133 , the jk flip - flop 203 generates a binary 1 indication on q output 202 , this means that the b error indication is larger than the error indication is larger than the a error indication . in the alternative , if the jk flip - flop 203 generates a binary 1 on output 204 , this means that the a binary indication is larger than the b binary indication . assuming that the system has been running without the occurrence of a 45 ° phase - jump , the d - type flip - flop 217 will have a binary zero signal on q output line 153 and a binary one signal on q output line 218 . the binary 1 signal on line 218 is supplied to and gate 219 thereby enabling that and gate to pass the a indication bits being received on line 131 to or gate 223 over lines 224 . the binary zero signal on line 153 is supplied to and gate 221 preventing that and gate from passing any b information being received at line 133 . or gate 223 will supply the information received on line 224 to line 225 . this information serves as the signal quality indicating information for the received vector symbol . the q output of d - type flip - flop 217 is supplied to the selector 109 ( fig5 ) as the control signal for directing whether the e x , e y components or the e x φ , e y φ components are to be selected . the q output signal indication is also fed back to the inputs of two exclusive or gates 205 and 207 . the q signal indication is fed back to the d input of flip - flop 217 . with the signal on line 153 being a binary zero , exclusive or gates 205 and 207 have no effect on the binary signals appearing on lines 202 and 204 , in effect , simply passing them on to lines 206 , 208 , respectively . the signals on lines 206 and 208 are the first input to the nand gate 211 and an and gate 209 , respectively . the other inputs to the nand gate and and gate is a strobe signal on line 213 that is present is a binary 1 only when the most significant bit of the a and b indications are being presented on lines 131 and 133 . assuming for purposes of example , that no phase - jump has occurred , thereby leaving the q output of flip - flop 217 on line 153 a binary zero , and q output of jk flip - flop 203 a binary 1 while the q output on line 204 is a binary zero , indicating that the rotated error indication b is larger than the unrotated error indication a . as a consequence , the output of exclusive or gate 205 , on line 206 , is a binary 1 , while the output of exclusive or gate 207 , on line 208 , is a binary zero . at the occurrence of a binary one indication on strobe line 213 , the output of nand gate 211 on line 210 is a binary zero while the output of and gate 209 on line 212 is a binary one , thereby loading a logic zero into the 10 - bit binary counter 215 . assume now that the q output of jk flip - flop 203 is a binary 1 on line 204 and the q output of flip - flop 203 is a binary zero on line 202 , indicating a possible phase - jump . the q output of d - type flip - flop 217 on line 153 is still a binary zero , causing the output of exclusive or gate 207 , on line 208 , to be a binary 1 . the output of exclusive or gate 205 on line 206 , will be a binary zero . at the occurrence of the strobe pulse , on line 213 , the output of nand gate 211 on line 210 would be a binary 1 while the output of and gate 209 , on line 212 , will also be a binary 1 , thereby loading a logic one level into the 10 - bit counter 215 . if the q output of jk flip - flop 213 is a binary one for ten consecutive strobe pulses , the module of the 10 - bit counter 215 is exceeded and a binary one indication appears on line 216 . it should be remembered that the strobe pulse appears on line 213 every time that a vector symbol is received . the occurrence of a binary 1 signal on line 216 is an indication that the unrotated error indication was larger than the 4520 rotated error indication for 10 consecutive received vector symbols . it is assumed from this indication that a phase - jump has occurred . the logic 1 symbol on line 216 will , therefore , clock the binary 1 q output of flip - flop 217 into the d input , thereby changing the q output of the flip - flop from a logic zero to a logic 1 and the q output from a logic 1 to a logic 0 . as a consequence of this change of state , the selector 109 ( fig5 ) will exit the e x φ and e y φ values to lines 111 and 112 and the q output signal on line 153 will enable and gate 221 to pass the b error information to or gate 223 thereby changing the signal quality indicating signal from the a to the b error indication . in addition , the binary 1 q output signal on line 153 is supplied to exclusive or gates 205 and 207 , causing them to complement any binary information received on lines 202 and 204 , respectively . as a result of this complementing action , the q output of jk flip - flop 203 will represent the condition , a & lt ; b , and the q output will represent the condition a & gt ; b . it can be seen that in this complemented mode whenever the q output , 202 of jk - flip - flop 203 is a binary 1 , indicating that the error a indication is larger than the error b indication , the error b now being the reference of zero phase - jump signal , the 10 - bit counter 215 is loaded with a logic 1 level at the occurrence of the strobe pulse 213 . if this situation persists for 10 - bit times a binary 1 signal will be supplied to output line 216 , clocking the logic zero from the q output of d - type flip - flop 217 into the d input . this will cause the q output on line 153 to become a binary zero and re - establish the error a indication as the reference or zero phase - jump reference . what has been described herein is a phase - jump detector for phase modulated binary information that also provides a means for automatically compensating for the occurrence of a phase - jump in a manner that eliminates the requirement for re - equalizing the entire transmission channel every time that a phase - jump occurs . in addition to detecting and correcting for the occurrence of phase - jumps , the invention provides a highly accurate signal quality indication that represents the quality of the vector symbol being received . obviously many modifications and variations of the present invention are possible in light of the above teachings , it is , therefore , to be understood that within the scope of the appended claims the invention may be practiced otherwise than as specifically described .