one or more exemplary embodiments of the invention are described below in detail . the disclosed embodiments are intended to be illustrative only since numerous modifications and variations therein will be apparent to those of ordinary skill in the art . aspects of the present invention relate to differing mechanisms that are used to support the functional gating of execution units and data paths that are situated within central processing units using techniques that specifically correlate to the width of operation data . depending on the specific processor design , the functional gating as implemented within aspects of the present invention can include clock gating , power gating , or both . a central objective of the present invention is to capture and utilize operand information from different processor sources , such operand information being obtained from , but not limited to , instruction operation code , pre - decoded bits , machine state registers , and partial value information . the acquired operand information is subsequently utilized assist in power - saving operations pertaining to gating off of unneeded parts of the execution unit and data path . the information that is necessary for performing the functional aspects of the present invention ( i . e ., the instruction operating code , pre - decode bits , machine state registers , etc . . . ) already exist by design in current computing processing system . within aspects of the present invention , the application of the operand information is extended to functional gating operations so that finer - grain clock and power gating operations can be utilized to reduce the power consumption within a processing system . specifically , within aspects of the present invention , for partial register value information the integer register file is appended with non - performance critical extra register bits ; the bits being used to represent indications of specific register value information . within aspects of embodiments of the present invention the extension bits are updated during register write operations . therefore , as a result of this particular configuration , the extension bit updating function does not impact the system critical path . conventionally , previous approaches have required that extra logic be added to the critical path , the logic thereafter being accessed every time the critical path is exercised . this arrangement results in slower processing timing , in addition to the high power consumption . in contrast , the present approach only exercises an update logic operation when the register value is updated . thus , no indirect timing impact is introduced , and the modifications to the micro - architecture of a computing system are required to accommodate the present approach . as mentioned above , current central processing unit design is based on specific system requirements ( e . g ., for 64 - bit mode executions , 64 - bit data path exist to accommodate 64 - bit data and computation operations ). however , during program execution , full - size data paths are rarely needed . that is , typically a partial data path is large enough to carry out any systematic data and computational needs . thus , higher order data paths within a processing system can be turned of for partial width operations ( e . g ., byte , half word , or word operations ) in order to assist in the conservation of power . turning now to the drawings in greater detail , it will be sen that in fig1 there is a high level diagram detailing the generation of resister extension bit values . within aspects of the preset invention the register extension bit values are generated , and subsequently updated , within register writing operations . as show in fig1 , during a register write operation , the lower register value 110 , and upper register value 105 are input to the register 125 , concurrently , the upper register value is input to detect logic component 115 . the detect logic component 115 functions to read the upper register input value 105 , and thereafter generate or update an extension register value 120 . in its simplest embodiment , the extension register value 120 can be comprised with a single bit , the bit being used to indicate the value state of the upper register value 105 ( e . g ., whether or not the upper register value contains all 0s , and therefore no significant data ). the register values 105 and 110 are written to the register 125 , wherein the values are respectfully stored at the register file locations 135 , 140 , and the extension register value 120 is written to an extended register file location 130 . the extension register value 120 is input to a power control component 145 , wherein the extension register value 120 is used as a power control signal 150 . as a power control signal 150 , the extension register value 120 serves as either a power gate for the subsequent upper register value 105 data path , or as a control signal to influence a clock gating signal that will disable the data path of the upper register value 105 . within further aspects of the present invention , for combined clock / power gating control , the register extension bit values from different operands are combined to generate a final control signal , and thereafter used to gate a power rail for a specific data path potion . fig2 shows a flow diagram of an aspect for the partial data functional gating operation of the present invention . at step 200 a register value is acquired during a data register write computational function , wherein after , an upper bit data register value 105 and a lower bit data register value 110 are identified for the data register value . at step 205 , the upper bit data register value 105 is input to a detect logic component 115 , wherein the upper bit data register value 105 is used to generate a data register extension value 120 . after the generation of the data register extension value 120 , at step 215 , the data register extension value 120 is output from the detect logic component 115 . thereafter , the register write operation is completed by the lower bit data register value 110 and the upper bit data register value 105 being written to the register file 125 , and the generated data register extension value 120 being written to an extended register file location 130 ( step 220 ). lastly , at step 225 , the register extension value 120 is used as a power control signal 150 in order to affect either clock gating or power gating operations within a processing system . register value based functional gating is a straightforward approach for certain computational operations in which a register value computation width of an operand can easily be determined using simple register extension bits . however , for some logical operations ( e . g ., shift and rotate operations ), the computational width of the register value may not be straightforward . nonetheless , within aspects of the present invention there are several approaches to mitigate this problem . within additional aspects of embodiments of the present invention the greater extension value is used in conjunction with control logic to make determinations in regard to clock / power gating operational modes within a processing system . for example , in exemplary embodiments , a data path segment is turned off , or deactivated , only in the event that implemented control logic can properly determine the part of the data path segment that will not be used , otherwise , the data path is left on . thus , potential power savings will be lower , in addition to the benefit of having incurred minimal complexity in regard to the processing design . a yet further aspect of the present invention comprises that the data path segment being turned off , or deactivated in the event that the control logic predicts only the part of the data path that is currently needed . in this case , pre - existing recovery logic is implemented , and subsequently activated to handle any determination errors , for example , in the event that the functional gating control logic has not properly predicted the data path segment usage and turned off a needed portion of the data path . the capabilities of the present invention can be implemented in software , firmware , hardware or some combination thereof . as one example , one or more aspects of the present invention can be included in an article of manufacture ( e . g ., one or more computer program products ) having , for instance , computer usable media . the media has embodied therein , for instance , computer readable program code means for providing and facilitating the capabilities of the present invention . the article of manufacture can be included as a part of a computer system or sold separately . the flow diagrams depicted herein are just examples . there may be many variations to these diagrams or the steps ( or operations ) described therein without departing from the spirit of the invention . for instance , the steps may be performed in a differing order , or steps may be added , deleted or modified . all of these variations are considered a part of the claimed invention . while the preferred embodiment to the invention has been described , it will be understood that those skilled in the art , both now and in the future , may make various improvements and enhancements which fall within the scope of the claims which follow . these claims should be construed to maintain the proper protection for the invention first described .