[ 0021 ] fig1 diagrammatically illustrates pertinent portions of an exemplary portable wireless communications terminal according to the invention . the baseband processor , for example a dsp or mcu ( microprocessor or microcontroller ), is provided in the terminal controller 11 . the terminal controller 11 is coupled to a transmitter 12 , a receiver 13 and a gps ( global positioning system ) receiver 14 by a communication bus designated generally at 15 . according to the invention , power control and frequency control functions applicable to the transmitters and receivers at 12 , 13 and 14 are advantageously integrated into those components in order to relieve undesirable overloading of , for example , the communication bus 15 and the baseband processor of the terminal controller 11 . [ 0022 ] fig3 diagrammatically illustrates pertinent portions of exemplary embodiments of a transmitter , receiver or transceiver according to the invention . fig3 is representative , for example , of any of the components 12 , 13 and 14 illustrated in fig1 . each of the components 12 , 13 and 14 can be implemented , for example , as an individual integrated circuit , or all of the components 12 , 13 and 14 could be integrated into a single integrated circuit . although fig1 illustrates only transmitter and receiver components , the exemplary embodiments of fig3 are also representative of a transceiver component in which , for example , the transmitter 12 and receiver 13 of fig1 are combined . although the exemplary embodiments of fig3 are hereinafter referred to as transceiver embodiments , the term transceiver should be understood to be indicative of transmitter embodiments such as illustrated at 12 in fig1 receiver embodiments such as illustrated at 13 and 14 in fig1 and combined transmitter / receiver embodiments in which the transmitter and receiver are combined , for example , in a single integrated circuit . the invention is applicable , for example , to transceivers such as bluetooth transceivers , ieee 802 . 11b transceivers , and others . the transceiver of fig3 includes a conventional transceiver section 34 , designated as tx / rx which , as indicated above , is representative of a conventional transmitter section ( with or without a power amplification function ), a conventional receiver section , or a conventional combined transmitter / receiver section ( with or without a power amplification function ). the transceiver section 34 includes a disable input and an enable ( en ) input , which respectively cause the transceiver section to enter and awaken from a powered - down sleep state wherein either the entire transceiver section , or at least a portion thereof , is in a powered - down sleep state . the transceiver section 34 also receives a frequency signal 36 from a frequency generator circuit 30 such as a pll ( shown in fig3 ) or a ddfs ( direct digital frequency synthesizer ). in response to the above - described input signals , the transceiver section 34 performs conventional transceiver operations , for example conventional cellular telephone communication operations or conventional gps acquisition operations . according to the invention , the aforementioned transceiver enable and disable signals can be generated within the transceiver itself rather than on the baseband processor side as is conventional ( see 23 and 25 in fig2 ). in the embodiment of fig3 the enable and disable signals are respectively driven by the outputs 38 and 39 of a signal selector 35 that is controlled by a mode selector 37 . the mode selector 37 can be programmed from the baseband processor , for example , via a serial programming interface spi in the communication bus 15 ( see also fig1 ). the mode selector determines whether the enabling and disabling of the transceiver section 34 will be controlled by locally ( i . e ., transceiver side ) generated signals 27 and 29 , or by the conventional interrupt signals 23 and 25 ( see also fig2 ) received from the baseband processor ( e . g . a dsp ) via the communication bus 15 ( see also fig1 ). the pll can be enabled by the baseband processor interrupt signal 21 discussed above with respect to fig2 . in response to this interrupt signal , the pll awakens from its sleep state and produces the frequency signal 36 for use by the transceiver section 34 . if the mode selector 37 has been programmed for conventional power control operation , then the transceiver section 34 is enabled and subsequently disabled by the conventional software interrupt signals 23 and 25 discussed above with respect to fig2 . on the other hand , if the mode selector 37 has been programmed to select local ( transceiver side ) power control operation , then the transceiver enable and disable signals are driven by the aforementioned signals 27 and 29 as generated locally by a timing sequencer 31 . the timing sequencer 31 can be implemented in some embodiments as a state machine that is programmable from the baseband processor side via the serial programming interface spi . the timing sequencer 31 is operable in response to the initial interrupt signal 21 received from the baseband processor side , is coupled to the pll at 33 for purposes of pll lock detection , and also receives the conventionally available pll comparison frequency 32 . [ 0025 ] fig4 diagrammatically illustrates pertinent portions of an exemplary embodiment of the timing sequencer 31 . a divider 41 receives the pll compare frequency 32 ( or another system clock ) and divides it down into a suitable ( e . g . 10 khz ) clock signal 40 that is provided to a lock detector 43 , a lock delay timer 42 and a transceiver timer 44 . the divider 40 , lock delay timer 42 and transceiver timer 44 are programmable via the serial programming interface spi . when the interrupt signal 21 is received from the baseband processor side to wake up the pll ( see also fig2 and 3 ), the lock delay timer 42 also receives this interrupt signal and begins timing a delay period during which the pll is expected to lock its output frequency . in one example , the lock delay time can be programmable from 0 to 6 . 4 milliseconds in 100 microsecond intervals . the lock delay timer 42 outputs a signal 45 to the lock detector 43 when the lock delay time has elapsed . the lock detector 43 also receives at 33 conventionally available pll information from which the lock detector can , using conventional techniques , determine whether or not the pll has locked . if the lock detector 43 determines that the pll has not yet locked even though the lock delay time has elapsed , then the lock detector 43 outputs a fault indication to the baseband processor . otherwise , if the lock detector 43 determines that the pll has locked , then the lock detector activates signal 27 at the input of the signal selector 35 ( see also fig3 ) in order to drive the signal 38 which enables the transceiver section 34 . the signal 27 from the lock detector 43 is also input to the transceiver timer 44 which , in response to activation of the signal 27 , begins tracking the time duration of the operation of transceiver section 34 . the transceiver timer 44 is programmable via the serial programming interface spi to track any desired time of operation for the transceiver section 34 . for example , if the transceiver section 34 is a gps receiver , then the gps acquisition time can be programmed into the transceiver timer 44 . as one example , the transceiver timer 44 can be programmed to track a gps acquisition time within a range of 0 to 17 minutes in four millisecond steps . when the transceiver timer 44 determines that the pre - programmed time has elapsed since activation of the signal 27 , the transceiver timer 44 activates the signal 29 at the input of selector 35 in order to drive the selector output 39 , which disables the transceiver section 34 and the pll , thereby returning both of those components into their respective powered - down sleep states . in some embodiments , separate selector outputs can be provided at 39 for permitting the pll and transceiver section 34 to be disabled independently from one another . [ 0027 ] fig5 is a timing diagram which illustrates exemplary timing relationships between various ones of the above - described signals of fig4 . [ 0028 ] fig6 illustrates exemplary operations which can be performed by the timing sequencer of fig3 - 5 . at 61 , the divider 40 , lock delay timer 42 and transceiver timer 44 are programmed with desired operational parameters . when an interrupt signal is received from the baseband processor side at 62 , the frequency generator is enabled at 63 , and a frequency generator delay ( e . g ., the lock delay implemented by lock delay timer 42 ) begins at 64 . after the frequency generator delay has expired , it is determined at 65 whether or not the frequency generator ( e . g . pll ) has locked . if not , a fault is indicated at 66 , and the next interrupt is awaited at 62 . if it is determined at 65 that the frequency generator ( e . g . pll ) has locked , then the transceiver section is enabled at 67 ( this can include , in some embodiments , turning on a transceiver power amplifier according to a power ramping profile ), and the transceiver operation delay is started at 68 . after completion of the transceiver operation delay at 68 , the transceiver and frequency generator are disabled at 69 ( this can include , in some embodiments , ramping down a transceiver power amplifier ), after which the next interrupt is awaited at 62 . [ 0030 ] fig7 diagrammatically illustrates pertinent portions of further exemplary transceiver embodiments according to the invention . the transceiver of fig7 includes integrated frequency shift control capabilities which can in varying degrees remove the frequency shift control burden from the baseband processor side . the transceiver of fig7 includes shadow registers 74 which can be pre - programmed from the baseband processor ( e . g . a dsp or mcu ) via a serial programming interface spi to contain information indicative of desired frequencies among which the frequency generator 70 ( shown as a pll in the example of fig7 ) is to sequentially shift . for example , each shadow register can include a respective divisor which can be loaded from the shadow register into the feedback loop of a conventional pll at 70 in order to set a desired output frequency at 77 . the use of a feedback divisor ( integer - n or fractional - n ) in a pll in order to set the pll output frequency is well known in the art . the shadow registers 74 are accessible via an input 73 which can control the sequence in which the shadow registers are accessed and their corresponding divisors loaded at 75 into the pll . as shown by broken line in fig7 the shadow register access sequence information can be received directly from the baseband processor side . in other embodiments , a shadow register accessor 72 receives at 71 control information from the baseband processor side and , responsive to the received control information , produces the shadow register access sequence information at 73 . [ 0032 ] fig8 diagrammatically illustrates pertinent portions of exemplary embodiments of the shadow register accessor 72 of fig7 . in one embodiment of fig8 sequence shadow registers 85 are employed in combination with an access sequencer 86 . the access sequencer 86 ( e . g . a programmable state machine ) outputs the shadow register access sequence information at 73 in response to information received from the sequence shadow registers 85 . each of the shadow registers 85 can be pre - programmed with frequency shift sequence information from the baseband processor side via the serial programming interface spi . a control code received from the baseband processor side at 71 is latched at 81 and decoded at 83 in order to select the shadow register 85 which contains the desired frequency shift sequence information . this information is then loaded into the access sequencer 86 , which responds thereto by sequentially accessing the shadow registers 74 of fig7 for example , to load into a pll at 70 the divisor sequence required to implement the desired frequency shift sequence . the access sequencer 86 has an input 78 for receiving a time reference signal ( e . g . the pll compare frequency or other system clock frequency ) from which can be derived a suitable time base for sequential access of registers 74 . the information in sequence shadow registers 85 can indicate a sequence in which registers 74 are to be accessed , and the desired timing between each access ( i . e ., between each frequency shift ). in other embodiments , the desired frequency shift sequence information can be loaded directly into the access sequencer 86 from the baseband processor side , as shown by broken line in fig8 . the above - described use of shadow registers in the embodiments of fig7 and 8 relieves a significant burden from the baseband processor side . for example , in the broken line embodiment of fig7 the baseband processor provides the shadow register access sequence information at 73 , but need not provide the specific frequency information , which has already been programmed into the shadow registers 74 . in the shadow register accessor embodiment illustrated by broken line in fig8 the baseband processor can load information indicative of the desired frequency shift sequence directly into the access sequencer 86 , thereby relieving the baseband processor of the task of directly controlling the sequential access of the shadow registers 74 in fig7 . in embodiments which utilize the sequence shadow registers 85 , the baseband processor need only provide , for example , a two bit code in order to access any one of four shadow registers 85 , each of which can be pre - programmed with frequency shift sequence information for loading into the access sequencer 86 . [ 0035 ] fig1 diagrammatically illustrates pertinent portions of exemplary embodiments of a transmitter , receiver or transceiver according to the invention . fig1 is generally similar to fig3 and is therefore similarly representative , for example , of any of the components 12 , 13 and 14 illustrated in fig1 . in fig1 , the frequency generator 300 is embodied as a direct digital frequency synthesizer ddfs . the ddfs architecture illustrated in fig1 is well - known in the art , including a phasor look - up table / interpolator 301 for providing n - bit digital codes to a digital - to - analog converter ( dac ) whose output is coupled to a filter which filters out quantization noise and higher order harmonic frequency energy . the filter outputs the desired frequency signal 36 to the transceiver section 34 ( see also fig3 ). the phasor look - up table / interpolator 301 and dac are clocked by a gated clock signal 302 produced at the output of gating logic 303 whose inputs are driven by a clock signal 320 , the interrupt signal 21 ( see also fig3 ) received from the baseband processor ( e . g . a dsp ), and the output 39 of a signal selector 35 ( see also fig3 ). the interrupt signal 21 drives an enable ( en ) input of the ddfs , and thereby serves to enable the phasor look - up table / interpolator 301 and the clock signal 320 ( via gating logic 303 ). this causes the ddfs to awaken from its powered - down sleep state and assume its powered - up operating state . the n - bit digital codes contained in the phasor look - up table / interpolator 301 can be loaded therein from the baseband processor via , for example , a serial programming interface ( spi ). in some embodiments , the codes can be downloaded from any suitable memory device . in other embodiments , an appropriate sinusoid generator function can be integrated within the ddfs in order to populate the coefficients of the look - up table . the baseband processor can also provide , for example , via the serial programming interface spi , information indicative of the radians per clock cycle at which the ddfs is to operate . the embodiments of fig1 also include a timing sequencer 310 which produces output signals 270 and 290 for input to a signal selector 35 ( such as described above with respect to fig3 ) whose outputs 38 and 39 respectively drive enable and disable inputs of the transceiver section 34 . the output 39 is also used at gating logic 303 to disable the gated clock signal 302 , and the output 39 could also be used , in some embodiments , to disable operation of the phasor look - up table / interpolator 301 of the ddfs . the timing sequencer 310 receives as inputs the clock signal 320 and the interrupt signal 21 , and is also programmable from the baseband processor via the serial programming interface spi . [ 0038 ] fig1 diagrammatically illustrates pertinent portions of exemplary embodiments of the timing sequencer 310 of fig1 . the timing sequencer of fig1 includes a clock divider 410 similar to the clock divider 41 of fig4 and a transceiver timer 440 similar to the transceiver timer 44 of fig4 . the clock divider 410 receives the clock signal 320 and can divide this signal appropriately to produce a desired clock signal 400 . the clock signal 400 is input to the transceiver timer 440 and to a programmable delay timer 110 . the timers 110 and 440 , and the clock divider 410 are all programmable from the baseband processor via the serial programming interface spi . the interrupt signal 21 from the baseband processor is input to the programmable delay timer 110 , which implements a desired delay , for example a delay time which is adequate to avoid any undesirable start - up noise in the frequency signal 36 initially produced by the ddfs 300 of fig1 . after the delay period has expired , the timer 110 activates the signal 270 , which in turn enables the transceiver section 34 of fig1 ( via selector 35 ) and the transceiver timer 440 of fig1 . at this point , the transceiver section 34 awakens from its powered - down sleep state and begins its normal powered - up operations , and the transceiver timer 440 begins tracking the operational time of the transceiver section 34 . when the timer 440 expires , it activates the signal 290 , thereby disabling ( via selector 35 ) the transceiver section 34 and the ddfs 300 ( see also fig1 ) into their sleep states . referring again to fig6 exemplary operations illustrated therein can also be performed by the timing sequencer embodiments of fig1 and 11 . in particular , with the exception of operations 65 and 66 , all operations illustrated in fig6 can also be performed by the embodiments of fig1 and 11 . operations of the embodiments of fig1 and 11 are thus illustrated by considering the broken line of fig6 . [ 0040 ] fig1 is generally similar to fig7 but illustrates that information from shadow registers 74 can be loaded into the phasor look - up table / interpolator of a ddfs 120 . in the embodiments of fig1 , the shadow registers 74 contain , for example , information indicative of various radians per clock cycle values associated with various desired frequencies in a frequency shift sequence to be executed by the ddfs 120 . exemplary embodiments of the shadow register accessor 72 and the shadow registers 74 are described above with respect to fig7 and 8 . [ 0041 ] fig9 illustrates exemplary operations which can be performed by the embodiments of fig7 and 12 . after the appropriate control information is received from the baseband processor side at 91 , the frequency shift sequence is determined at 92 in response to the control information . at 93 , a shadow register is accessed according to the frequency shift sequence , and the information ( e . g . pll divisor or ddfs radians per clock cycle ) from the accessed shadow register is loaded into the frequency generator . the sequence of accessing information from a shadow register and loading the frequency generator with the accessed information is continued at 93 until the sequence is completed at 94 . the broken line 95 in fig9 corresponds to the broken line embodiments of fig7 and 12 , wherein each information element of the sequence is individually communicated from the baseband processor side . the broken line at 96 in fig9 illustrates that , in some embodiments , the frequency shift sequence can be repeated as desired . the operations illustrated in fig9 can be performed , for example , during the transceiver operation delay 68 of fig6 . thus , the pll of fig3 and ddfs of fig1 can be controlled in the manner described with respect to fig7 - 9 ( fig7 - 9 and 12 for ddfs ) during the period of transceiver operation tracked by the transceiver timers 44 and 440 of fig4 and 11 ( and indicated by the delay 68 of fig6 ). accordingly , the capability of loading the pll of fig3 and ddfs of fig1 from the shadow registers 74 of fig7 and 12 is also indicated in fig3 and 10 . in some embodiments , the arrangements of fig7 and 12 can shift to the next desired frequency while the transceiver section 34 of fig3 and 10 is powered down ( e . g ., between operations 69 and 63 in fig6 ). it will be evident to workers in the art that the embodiments of fig1 and 3 - 12 can be readily implemented , for example , by suitable modifications in software , hardware , or a combination of software and hardware , in conventional portable wireless communication terminals . although exemplary embodiments of the invention are described above in detail , this does not limit the scope of the invention , which can be practiced in a variety of embodiments .