the encoding and precompensation device of fig1 comprises an oscillator 1 which generates a frequence of 18 mhz , a timing circuit formed by flip - flops 2 and 6 and binary counters 4 and 5 , a data source 7 , two shift registers 8 and 9 , a memory 10 , a binary counter 11 , a flip - flop 12 and a recording device 13 . the data source 7 and the device 13 will not be described in detail , since their construction does not concern the present invention . however , the data source 7 may be constituted by a computer , a controller receiving signals from a transmission line , a data reading device or other similar device . it is only required that the device 7 be able to supply coded information in the form of characters including a predetermined number of binary information units . these information characters are transferred to the shift register 8 serially character by character in the form of binary signals ( bits ) by means of the channel by . similarly , regarding the recording device 13 , it can be said that this must comprise a recording carrier or support , such as , for example , a magnetic tape or a magnetic disc ( rigid or flexible ), and a corresponding recording element of the magnetic head type . those skilled in the art will appreciate the fact that the present arrangement is not confined to the above - mentioned applications , but may be used with advantage in all those systems employed in the field of data processing which require encoding with possible precompensation of errors . in fig1 the signal v indicates connection to a constant signal having a logical 1 level , while the signal m indicates connection to a constant signal having logical 0 level . the oscillator 1 generates the timing signal f18 having a period of 55 ns which is applied to the timing input of the flip - flop 2 and to one of the inputs of a nand gate 3 . the reset input k is connected to a signal code coming from the data source 7 and signifying the choice of the recording code . if code = 0 , the flip - flop 2 emits a signal f9 of logical 1 level and therefore enables the nand circuit 3 to pass the signal f18 . it follows that tenon = f18 . on the other hand , if code = 1 , the signal f9 has a period of 110 ns and it follows that the signal tenon will also have a period of 110 ns . the signal tenon is sent to the incrementing input of the counters 4 , 5 and 11 . the counter 4 counts from eight to fifteen and then supplies the end - of - count signal tc4 at every eight signals tenon . the signals tenon and tc4 are sent respectively to the incrementing and enabling inputs of the counter 5 . the counter 5 emits as output the signals rebco and pusun , rebco having a period double that of pusun . the flip - flop 6 has its inputs j and k connected to the signal rebco and the timing input t connected to the signal pusun . the result is that the signal daclo generated by the flip - flop 6 has a period equal to that of the signal rebco , but in which the duration of the negative half - wave is much smaller than the duration of the positive half - wave ( see fig3 and 4 ). the signal daclo is sent to the shift inputs of the shift registers 8 and 9 . the result is that the register 8 emits a bit signal at each period of daclo and , correspondingly , the shift register 9 stores a fresh bit signal and shifts its contents to the left at each period of daclo . the parallel outputs cl1 - 5 of the shift register 9 , together with the signals rebco , cloco and code , address the memory 10 , the signal cloco being another signal from the data source with a significance emplained below . for each configuration of the bits cl1 - 5 and of the signals cloco and code , the memory 10 generates an output a word m1 - 4 for each half - wave of the signal rebco . as will be explained better hereinafter , the first word generates , if necessary , a bit signal , while the second generates , if necessary , a clock signal . the word m1 - 4 read from the memory 10 presets the counter 11 , the reset enabling input of which is connected to the signal pusun , while the incrementing input is connected to the signal tenon . the outputs of weights one and two of the counter 11 are applied to direct and negated inputs , respectively , of an and gate 14 , while the output of weight eight is applied to the input j of the flip - flop 12 . the signal regi which is the output from the and circuit 14 is applied to the timing input of the flip - flop 12 , while the direct reset input c is connected to the signal pusun . the flip - flop 12 generates as output the signal inreo , which is used by the recording element ( not shown ) included in the recording device 13 . in the case of the memory illustrated in fig2 the arrangement is employed for encoding information in accordance with the frequency doubling recording code ( hereinafter called fd ) and the modified frequency modulation recording code ( hereinafter called mfm ). moreover , for each of these codes there is provided the use of a special encoding which suppresses the timing pulses ( hereinafter called missing ), which is used during the stage of writing the sector addresses , in the case of magnetic discs , or for the addresses of the blocks , in the case of magnetic tapes . more particularly , the memory 10 is divided into eight sections selected by the logical levels of the signals code , cloco and rebco in accordance with the following table : ______________________________________ select - ed en - code cloco rebco zone inreo coding______________________________________ fd0 0 0 27 clock missing fd0 0 1 26 bit missing0 1 0 23 clock fd data0 1 1 22 bit fd data mfm1 0 0 25 clock missing mfm1 0 1 24 bit missing mfm1 1 0 21 clock data mfm1 1 1 20 bit data______________________________________ during the operation of the arrangement of fig1 the data source 7 sends the signals cloco and code which select one of the quadrants of the memory 10 . more particularly , therefore , the combination cloco = 1 , code = 1 requires that the data on the channel by be encoded in mfm ; the combination cloco = 0 , code = 1 requires that the data on the channel by be encoded in mfm with , moreover , suppression of the timing signals ( missing ); the combination cloco = 1 , code = 0 requires that the data on the channel by be encoded in fd ; the combination cloco = 0 , code = 0 requires that the data on the channel by be encoded in fd with , moreover , suppression of the timing signals ( missing ). let us assume , for example , that the data source 7 selects the zones 20 and 21 for the encoding of the data in mfm ( cloco = 1 , code = 1 ). in this case the signal tenon will have a frequency of 18 mhz and , therefore , a period of 55 ns and , correspondingly , the signal daclo will have a period of 2 μs ( see fig3 ). the positive half - wave of the signal daclo defines the time in which the bits cl1 - 5 remain constant in the shift register 9 . during the first half of this period the signal rebco is at logical 1 level , while during the second half it is at logical 0 level , thus selecting the zones 20 and 21 alternately . as has been said , the logical one level of the signal pusun enables the counter 11 and the flip - flop 12 and therefore the signal inreo can appear only during the positive half - wave of the signal pusun ( fig3 ). the generation of a recording signal inreo takes place when the counter 11 reaches the configuration &# 34 ; 1001 &# 34 ;, so that the generation of the signal inreo presupposes that the word read from the memory 10 contains a bit configuration less than &# 34 ; nine &# 34 ;. more particularly , as regards the bits which do not require precompensation , this configuration is &# 34 ; six &# 34 ;, that is &# 34 ; 0110 &# 34 ;. in those cases in which it is not necessary to generate inreo , the word m1 - 4 contains the configuration &# 34 ; 1110 &# 34 ;, which does not allow the counter 11 to reach the configuration &# 34 ; 1001 &# 34 ; within the limits of the positive half - wave of the signal pusun during which the counter 11 and the flip - flop 12 are enabled . it is pointed out that in the word read from the memory 10 the bit m1 is that of minimum weight , while the bit m4 is that of maximum weight . if , on the other hand , the data source 7 requires encoding in fd , it will send the signal cloco = 1 and the signal code = 0 . in this case , the signal daclo will have a period of 4 μs ( fig4 ). similarly , the signal inreo will be generated at each negative half - wave of the signal rebco for recording the clock signals which define the bit cells provided for by the encoding code . the bit signals , on the other hand , will be generated within the limits of the positive half - waves of the signal rebco only if the bit cl3 examined in the shift register 9 has logical &# 34 ; 1 &# 34 ; level . when the signal inreo is not generated in correspondence with the positive half - waves of the signal pusun ( see fig3 or 4 ), the word m1 - 4 read from the memory 10 assumes the configuration &# 34 ; 1110 &# 34 ;. in the preferred embodiment , precompensation of errors in writing is effected only in correspondence with the mfm code ( zone 20 of fig2 ), since the fd code does not have such a high bit packing density as to require precompensation of reading errors . obviously , if the fd code is replaced another code , the corresponding zones 22 , 23 , 26 , 27 can also include error precompensation . in fig3 precompensation is performed on the pulses of types b and c , inasmuch as they are recorded very close together and , moreover , the preceding or following pulse is spaced to the maximum . this corresponds to having in the shift register 9 one of the bit configurations shown in the table which require the corresponding correction . ______________________________________type cl1 - 5 word m1 - 4 correction______________________________________c 01101 1001 advanceb 10110 0011 delayb 10111 0011 delayc 11101 1001 advance______________________________________ from the table and from fig3 it can be observed how the generation of the signal inreo is effected taking account not only of the bit to be encoded which corresponds to the signal cl3 which is fed into the memory 10 , but also of the two previously encoded bits cl1 and cl2 and of the two bits cl4 and cl5 which will be encoded subsequently . the word m1 - 4 which is the output of the memory 10 therefore takes account of the configuration of the signals inreo which will be recorded in a certain zone of the carrier . this means that in the generation of the current signal inreo the memory 10 considers whether its position in relation to the preceding signal and the following signal requires to be shifted in advance or with delay . as can be seen from fig3 in the configurations of type b the preceding signal inreo is spaced apart to the maximum , while the following one is spaced apart to the minimum . the error in reading will act on the signal b , shifting it towards the preceding signal and it is for this reason that the signal b is generated with delay during the writing ( see fig5 ). since the counter 11 is incremented by the signal tenon , while the flip - flop 12 generates the signal inreo when the counter reaches the configuration &# 34 ; 1001 &# 34 ;, the signal inreo is generated in a theoretical position if the word read from the memory 10 assumes the configuration &# 34 ; 0110 &# 34 ; ( type a ). there is an advance if the word read is &# 34 ; 1001 &# 34 ;, while there is a delay if the word read is &# 34 ; 0011 &# 34 ;. the advance or delay of the signal inreo in the theoretical position is by 165 ns , which corresponds to the error of delay or advance , respectively , encountered in reading in the signals c and b . it is clearly apparent from the present description how , by means of a few hardware elements , the encoding arrangement enables encoding and precompensation in the recording stage in any codes , selectable by means of external signals , of information emitted by a data source to be effected .