preferred embodiments of the present invention will now be described with reference to the accompanying drawings . in the drawings , identical , similar , or equivalent elements are designated by identical or similar reference numerals . ( configuration of d - ff circuit ) a semiconductor integrated circuit according to an embodiment of the present invention includes a master - slave d - ff circuit , which is shown in fig3 , and a switch control circuit 10 , which is shown in fig4 . fig3 is a diagram illustrating an example configuration of the d - ff circuit . referring to fig3 , the d - ff circuit includes an input buffer 1 , a master ff 2 , a master - slave switch 3 ( hereinafter referred to as the m - s switch 3 ), a slave ff 4 , and an output buffer 5 . data data input into the d - ff circuit is input into the master ff 2 through the input buffer 1 . data qm output from the master ff 2 is input into the slave ff 4 through the m - s switch 3 . output data generated by the slave ff 4 is output as data out through the output buffer 5 . the input buffer 1 shown in fig3 includes an inverter 11 and a cmos transfer gate 12 . the inverter 11 inverts the signal level ( logic value ) of input data and outputs the inverted logic value to the cmos transfer gate 12 . in accordance with control clocks n 3 , n 4 , which are complementary to each other , the cmos transfer gate 12 controls a signal transmission between the output of the inverter 11 and the master ff 2 ( input terminal nin ). more specifically , the cmos transfer gate 12 includes an n - channel mos transistor and a p - channel mos transistor . the sources and drains of these transistors are coupled to each other to form input and output terminals . the n - channel mos transistor inputs the control clock n 3 at its gate , whereas the p - channel mos transistor inputs the control clock n 4 at its gate . when the control clock n 3 is at a high level ( hereinafter referred to as the “ h ” level ) and the control clock n 4 is at a low level ( hereinafter referred to as the “ l ” level ), the cmos transfer gate 12 turns on and outputs output data received from the inverter 11 to the input terminal nin of the master ff 2 . further , when the control clock n 3 is at the “ l ” level and the control clock n 4 is at the “ h ” level , the cmos transfer gate 12 turns off and blocks the signal transmission between the output of the inverter 11 and the input terminal nin . while the signal transmission is blocked by the cmos transfer gate 12 , it can be said that a high - impedance ( hereinafter referred to as “ hi - z ”) output is generated from the cmos transfer gate 12 . the master ff 2 shown in fig3 includes a nand circuit 21 , an inverter 22 , and a cmos transfer gate 23 . the nand circuit 21 outputs the nand of an output signal from the input buffer 1 and the signal level ( logic value ) of a set signal sb to the m - s switch 3 as internal data qm . the internal data qm output from the nand circuit 21 is fed back to the input terminal nin through the inverter 22 and cmos transfer gate 23 . setting the set signal at the “ l ” level sets the internal data qm of the master ff 2 at the “ h ” level asynchronously . the cmos transfer gate 23 controls the signal transmission between the output of the inverter 22 and the input terminal nin of the master ff 2 in accordance with control clocks n 1 , n 2 , which are complementary to each other . more specifically , the cmos transfer gate 23 has the same circuit configuration as the cmos transfer gate 12 . the control clock n 1 is input into the gate of the n - channel mos transistor , whereas the control clock n 2 is input into the gate of the p - channel mos transistor . when the control clock n 1 is at the “ h ” level and the control clock n 2 is at the “ l ” level , the cmos transfer gate 23 turns on . the internal data qm is then inverted by the inverter 22 and output ( fed back ) to the input terminal nin of the master ff 2 . further , when the control clock n 1 is at the “ l ” level and the control clock n 2 is at the “ h ” level , the cmos transfer gate 23 turns off , blocks the signal transmission from the output of the inverter 22 to the input terminal nin , and generates a “ hi - z ” output . the control clock n 2 and control clock n 4 are substantially complementary to each other , and the control clock n 1 and control clock n 3 are also substantially complementary to each other . therefore , when the cmos transfer gate 12 is on , the cmos transfer gate 23 is off so that input data data is loaded into the master ff 2 . when , on the other hand , the cmos transfer gate 12 is off , the cmos transfer gate 23 is on so that loaded data qm is retained ( stored ) in the master ff 2 . the m - s switch 3 shown in fig3 includes a cmos transfer gate 30 , which controls the input of the internal data qm from the master ff 2 to the slave ff 4 . more specifically , the cmos transfer gate 30 has the same circuit configuration and the same clock signal coupling to the gate as the cmos transfer gate 23 . when the control clock n 1 is at the “ h ” level and the control clock n 2 is at the “ l ” level , the cmos transfer gate 30 turns on and outputs the internal data qm output from the master ff 2 to the input terminal of the slave ff 4 . further , when the control clock ni is at the “ l ” level and the control clock n 2 is at the “ h ” level , the cmos transfer gate 30 turns off , blocks the signal transmission from the output of the master ff 2 to the input of the slave ff 4 , and generates a “ hi - z ” output . the slave ff 4 shown in fig3 includes a nand circuit 41 , an inverter 42 , and a cmos transfer gate 43 . the nand circuit 41 outputs the nand of an output generated from the master ff 2 through the m - s switch 3 and the signal level ( logic value ) of a reset signal rb ( the term “ rb ” is an acronym for “ reset bar ”) to the output buffer 5 . a signal output from the nand circuit 41 is fed back to the input of the nand circuit 41 through the inverter 42 and cmos transfer gate 43 . setting the reset signal rb at the “ l ” level sets output data out at the “ l ” level asynchronously . the cmos transfer gate 43 controls the signal transmission between the output of the inverter 42 and the input terminal of the slave ff 4 ( the input of the nand circuit 41 ) in accordance with the control clocks n 2 , n 1 , which are complementary to each other . more specifically , when the control clock n 2 is at the “ h ” level and the control clock n 1 is at the “ l ” level , the cmos transfer gate 43 turns on to output ( feed back ) the inverted output of the nand circuit 41 to the input of the slave ff 4 . further , when the control clock n 2 is at the “ l ” level and the control clock n 1 is at the “ h ” level , the cmos transfer gate 43 turns off to block the signal transmission from the output of the inverter 42 to the input of the nand circuit 41 . when the cmos transfer gate 30 is on , the cmos transfer gate 43 is off so that the internal data qm input from the master ff 2 is loaded into the slave ff 4 . when the cmos transfer gate 30 is off , the cmos transfer gate 43 is on so that the loaded internal data qm is retained ( stored ) in the slave ff 4 . as described above , in the d - ff circuit according to an embodiment of the present invention , the opening and closing of an input control switch ( the cmos transfer gate 12 shown in fig3 ) that controls the loading of data data into the master ff 2 is controlled by the control clocks n 3 , n 4 , which differ from the control clocks n 1 , n 2 that control the opening and closing of the other switches . consequently , the opening / closing timing of the input control switch ( cmos transfer gate 12 ) for the master ff 2 can be adjusted independently of the other switches . the other switches are a feedback control switch ( the cmos transfer gate 23 shown in fig3 ) for controlling the selection of a storage mode in which the internal data qm is retained in the master ff 2 , an input control switch ( the cmos transfer gate 30 shown in fig3 ) for controlling the loading of the internal data qm into the slave ff 4 , and a feedback control switch ( the cmos transfer gate 43 shown in fig3 ) for controlling the selection of a storage mode in which the output value of the slave ff 4 is retained in the slave ff 4 . the switching timing of each switch in the d - ff circuit according to an embodiment of the present invention is controlled by the switch control circuit 10 shown , for instance , in fig4 . fig4 is a diagram illustrating an example configuration of the switch control circuit according to an embodiment of the present invention . referring to fig4 , the switch control circuit 10 includes inverters 101 , 102 , 103 , 104 and generates the control clocks n 1 , n 2 , n 3 , and n 4 in accordance with an input clock clk . more specifically , the inverter 101 inverts the signal level of the input clock clk , and outputs the inverted clock to the inverters 102 , 104 and d - ff circuit as the control clock n 2 . the inverter 102 inverts the signal level of the input control clock n 2 , and outputs the inverted clock to the inverter 103 and d - ff circuit as the control clock ni . the inverter 103 inverts the signal level of the input control clock n 1 , and outputs the inverted clock to the d - ff circuit as the control clock n 3 . the inverter 104 inverts the signal level of the input control clock n 2 , and outputs the inverted clock to the d - ff circuit as the control clock n 4 . in the switch control circuit 10 according to an embodiment of the present invention , a pair of control clocks n 1 , n 2 , which are complementary to each other , are input into the inverters 103 , 104 to generate another pair of control clocks n 3 , n 4 , which are also complementary to each other . therefore , the timings of the control clocks n 3 , n 4 can be adjusted by adjusting only the driving capacities of the inverters 103 , 104 . further , the outputs of the inverters 103 , 104 are coupled to the cmos transfer gate 12 , but are not coupled to the other control switches ( cmos transfer gates 23 , 30 , 43 ). it means that the outputs of the inverters 103 , 104 are not affected by the load capacitances provided by the other control switches . therefore , when the driving forces of the inverters 103 , 104 are to be adjusted , only the load capacitance provided by the cmos transfer gate 12 needs to be taken into consideration . conversely , changes in the driving capacities of the inverters 103 , 104 would not affect the timings of the other control clocks n 1 , n 2 . in other words , the driving capacities of the inverters 103 , 104 can be adjusted independently . the inventors have found that when only the timing at which the data data is loaded into the input buffer 1 is adjusted , the timing of the d - ff circuit can be adjusted in accordance with the speed of the data data even if the timings of the other switches ( the timing of data retention in the master ff 2 and the timings of loading and retaining the internal data qm ) are not adjusted . in an embodiment of the present invention , therefore , the opening and closing of the input control switch ( cmos transfer gate 12 ) for controlling the loading of data data into the master ff 2 can be adjusted independently of the other switches ( cmos transfer gates 23 , 30 , 43 ). further , when the opening / closing timing of the input control switch ( cmos transfer gate 12 ) is to be adjusted , only the inverters 103 , 104 need to be adjusted without considering the load capacitances provided by the other switches . consequently , the present invention ensures that the timing adjustments of the d - ff circuit can be made more efficiently ( more easily ) than ever . a setup time improvement mechanism of the d - ff circuit according to an embodiment of the present invention will now be described with reference to fig5 a and 5b . as an example , the d - ff circuit operating at the rising edge is described below . for the sake of brevity of explanation , it is assumed in the following description that the phase difference between the control clock n 1 and the control clock n 2 , which are complementary to each other , is negligible , and that the phase difference between the control clock n 3 and the control clock n 4 , which are also complementary to each other , is also negligible . fig5 a is a timing diagram illustrating an exemplary data transfer operation that is performed before the timing adjustments of the d - ff circuit according to an embodiment of the present invention . referring to fig5 a , it is assumed that the setup time tstp required for the loading of data data is “ tstp 1 ,” and that the time interval between the time of conversion of the data data and the active edges of the control clocks n 3 , n 4 at which the cmos transfer gate 12 starts operating is “ tda 1 .” when “ tstpl ” is longer than “ tda 1 ,” the data data may not be loaded into the d - ff circuit because the setup time required for the loading of the data data is not secured . however , when the setup time tstp required for the loading of the data data is shortened to “ tstp 2 ,” which is shorter than “ tda 1 ,” the data data can be successfully loaded to permit the d - ff circuit handle high - speed data . to shorten the setup time tstp , which is required for the loading of the data data , to “ tstp 2 ,” it is necessary to increase the gate width w of a transistor included in the cmos transfer gate 12 . however , if the above - mentioned transistor gate width is increased , the output load capacitance of the switch control circuit 10 , which drives the cmos transfer gate 12 , is increased to dull the control clocks n 3 , n 4 . to avoid such a situation , the present invention increases the driving capacity of the clock buffers ( inverters 103 , 104 ) by increasing the gate width w of transistors included in the inverters 103 , 104 . this decreases the load capacitance as viewed from the clock buffers ( inverters 103 , 104 ). in this instance , the control clocks n 3 , n 4 are not output to the other control switches ( cmos transfer gates 23 , 30 , 43 ). therefore , the timing adjustments can be made without considering the operations performed relative to the other control switches . in an embodiment of the present invention , the setup time required for the loading of the data data can be adjusted without changing the driving capacities of the clock buffers ( inverters 101 , 102 ), which output the control clocks n 1 , n 2 . in other words , the timing adjustments can be made so as to handle high - speed data without increasing the sizes of the clock buffers ( inverters 101 , 102 ), which output the control clocks n 1 , n 2 . further , when timing adjustments are to be made in order to transfer high - speed data , the setup time can be secured by dulling the waveforms of the control clocks n 3 , n 4 . fig5 b is a timing diagram illustrating the waveforms of the control clocks n 3 , n 4 that are obtained after timing adjustments . referring to fig5 b , the time interval between the time of conversion of the data data and the active edges of the control clocks n 3 , n 4 at which the cmos transfer gate 12 starts operating is changed to “ tda 2 ,” which is longer than the required setup time tstpl , by dulling the waveforms of the control clocks n 3 , n 4 . this ensures that the required setup time is secured even when high - speed data is handled . when the control clocks n 3 , n 4 are to be retarded as shown in fig5 b , the gate widths of transistors included in the clock buffers ( inverters 103 , 104 ) should be decreased . in this instance , the control clocks n 3 , n 4 are not output to the other control switches ( cmos transfer gates 23 , 30 , 43 ). therefore , the timing adjustments can be made without considering the operations performed relative to the other control switches . further , when the control clocks n 3 , n 4 are to be retarded , as is the case with the above paragraph , the setup time required for the loading of the data data can be adjusted without changing the driving capacities of the clock buffers ( inverters 101 , 102 ), which output the control clocks n 1 , n 2 . in other words , the timing adjustments can be made so as to handle high - speed data without changing the sizes of the clock buffers ( inverters 101 , 102 ), which output the control clocks n 1 , n 2 . the propagation delay time tpd of the d - ff circuit according to an embodiment of the present invention is determined by the control clocks n 1 , n 2 and is not dependent on the control clocks n 3 , n 4 , which determine the loading timing of the data data . hence , the propagation delay time tpd of the d - ff circuit remains unaffected even when the control clocks n 3 , n 4 are adjusted in order to adjust the setup time . in other words , the present invention makes it possible to improve the setup time without having to consider the influence upon the propagation delay time tpd of the d - ff circuit . in an embodiment of the present invention , the outputs of the clock buffers ( inverters 103 , 104 ) are not coupled to the master ff 2 , m - s switch 3 , or slave ff 4 , but are coupled only to the input control switch ( the cmos transfer gate 12 in the present example ) of the input buffer 1 . according to an embodiment of the present invention , therefore , the waveforms of the control clocks n 3 , n 4 can be adjusted without considering the load capacitances provided by control switches ( cmos transfer gates 23 , 30 , 43 ) other than the input control switch ( cmos transfer gate 12 ) of the input buffer 1 . conversely , even if the waveforms of the control clocks n 3 , n 4 are adjusted , the timings of the other control clocks n 1 , n 2 remain unaffected . it means that the control clocks n 3 , n 4 can be adjusted independently . hence , the waveforms of the control clocks n 3 , n 4 can be adjusted in accordance with an increase in the speed of the clock clk without unduly changing the sizes of the clock buffers ( inverters 103 , 104 ). consequently , the timing adjustments can be made to cope with speed enhancement more efficiently ( more easily ) than ever . as described above , in the master - slave d - ff according to an embodiment of the present invention , the clock buffers used to generate the control clocks n 3 , n 4 , which control the loading of the data signal data into the master ff 2 , are different from the clock buffers used to generate the control clocks n 1 , n 2 , which control the retention of data in the master ff 2 and the loading of data into and the retention of data in the slave ff 4 . therefore , the timings of the control clocks n 3 , n 4 , which control a data input control switch for the master ff 2 , can be adjusted without considering the load capacitances provided by the other control switches . this not only facilitates the timing adjustments of the master - slave d - ff but also prevents an undue increase in the sizes of the clock buffers . although only specific embodiments of the present invention have been described in detail , the present invention is not limited thereto but is meant to include all embodiments modified within the spirit of the present invention . for example , the switch control circuit 10 shown in fig4 uses inverters as the clock buffers that generate the control clocks n 3 , n 4 . however , as shown in fig6 , non - inverting buffers 203 , 204 may be used in place of the above - mentioned inverters . fig6 is a diagram illustrating another example configuration of the switch control circuit 10 according to an embodiment of the present invention . referring to fig6 , the switch control circuit 10 includes inverters 101 , 102 and non - inverting buffers 203 , 204 , and generates control clocks n 1 , n 2 , n 3 , and n 4 in accordance with an input clock clk . more specifically , the inverter 101 inverts the signal level of the input clock clk , and outputs the inverted clock to the inverter 102 , non - inverting buffer 204 , and d - ff circuit as the control clock n 2 . the inverter 102 inverts the signal level of the input control clock n 2 , and outputs the inverted clock to the non - inverting buffer 203 and d - ff circuit as the control clock n 1 . the non - inverting buffer 203 buffers the input control clock n 1 to obtain the control clock n 4 , and then outputs the control clock n 4 to the d - ff circuit . the non - inverting buffer 204 buffers the input control clock n 2 to obtain the control clock n 3 , and then outputs the control clock n 3 to the d - ff circuit . in the example shown in fig6 , outputs n 3 and n 4 are interchanged because the buffers 203 , 204 are used in place of the inverters 103 , 104 . operations concerning the other timing adjustments are the same as described above . the non - inverting buffers 203 , 204 include an even number of ( usually two ) cascade - coupled inverters . therefore , the amount of delay of the control clocks n 3 , n 4 relative to the control clocks n 1 , n 2 is increased so that operations can be performed even when the setup time is shorter than in the example described earlier . further , as the rise time and fall time ( tr , tf ) of the control clocks n 3 , n 4 can be decreased , higher - speed operations can be handled . furthermore , the load capacitance as viewed from the inverters 101 , 102 is limited to the first - stage inverters of the buffers 203 , 204 . therefore , even if the dimensions of transistors forming the output stages of the buffers 203 , 204 are changed in order to provide a different driving capacity , the load capacitances of the inverters 101 , 102 remain unchanged . this eliminates the influence on the control clocks n 1 , n 2 and provides an advantage in that the setup time can be adjusted with ease . although the cmos transfer gate 12 , which is based on a cmos transistor , is described as an input control switch of the data data for the master ff 2 with reference to fig3 , the present invention is not limited to such a configuration . a switch circuit having a different configuration may alternatively be used . moreover , a clocked inverter 13 whose operation is controlled by the control clocks n 3 , n 4 may be used in place of the inverter 11 and cmos transfer gate 12 shown in fig3 . fig7 is a diagram illustrating another example configuration of the d - ff circuit according to an embodiment of the present invention . the d - ff circuit shown in fig7 includes an input buffer 1 , which includes a clocked inverter 13 . the other elements are the same as for the d - ff circuit shown in fig3 . the clocked inverter 13 inverts the signal level ( logic value ) of input data and outputs the inverted data to the input terminal nin of the master ff 2 . more specifically , the clocked inverter 13 turns on when the control clock n 3 is at the “ h ” level and the control clock n 4 is at the “ l ” level , and outputs the inverted data of the data data to the input terminal nin of the master ff 2 . further , the clocked inverter 13 turns off when the control clock n 3 is at the “ l ” level and the control clock n 4 is at the “ h ” level , and places the input terminal nin of the master ff 2 in a high - impedance state . the operations of the d - ff circuit shown in fig7 are the same as described earlier . further , . the d - ff circuit shown in fig7 facilitates the timing adjustments as described earlier . however , the layout area of the clocked inverter is at an advantage in that it is smaller than the layout area of a transfer gate . more specifically , the input buffer 1 shown in fig3 needs to be configured in such a manner that the transistors for the inverter 11 and cmos transfer gate 12 are separately formed . on the other hand , the clocked inverter 13 can be configured so that a diffusion layer is shared by a switch transistor , which provides switching control in accordance with the control clocks n 3 , n 4 , and an inverter transistor , which inverts a signal . therefore , using the clocked inverter 13 as the input buffer 1 makes it possible to reduce the area of the input buffer 1 . the above - described d - ff circuit and switch control circuit 10 can be combined as far as no technical discrepancy arises . further , although the d - ff circuit operating at the rising edge is described as an example with reference to fig5 a and 5b , the present invention is also applicable to the d - ff circuit operating at the falling edge . furthermore , in the example described earlier , the master ff 2 , the m - s switch 3 , and the slave ff 4 operate in synchronism with the same control clocks n 1 , n 2 . however , the present invention is not limited to such a situation . the present invention is also applicable to a situation where the master ff 2 , the m - s switch 3 , and the slave ff 4 operate in synchronism with different control clocks as far as they differ from the control clocks n 3 , n 4 . in an embodiment of the present invention , the load capacitance as viewed from the clock buffers in the switch control circuit 10 is lower than before because it results from the input buffer 1 only . therefore , even when the gate width of a transistor forming the input control switch ( cmos transfer gate 12 or clocked inverter 13 ) is increased to shorten the delay time in the input buffer 1 , it is possible to suppress an increase in the sizes of the clock buffers . further , the clock buffers ( inverters 103 , 104 or non - inverting buffers 203 , 204 ) that double as delay elements are merely expected to drive the gate of an n - channel mos transistor or p - channel mos transistor forming the input control switch ( cmos transfer gate 12 or clocked inverter 13 ). therefore , even when the transistor size is reduced for timing adjustment purposes , the influence on the overall layout size is small . in addition , the influence on the other components ( not shown ) coupled to the clock buffers is limited . consequently , the setup time can be adjusted with ease .