the structure and operation of the present invention is dependent upon the partitioning of one of the multiplying factors into a plurality of k bit - wide pieces . thus , instead of representing a binary number a as ∑ i = 0 n - 1 ⁢ ⁢ a i ⁢ 2 i , one of the multiplying factors in the present invention is represented instead in the form a m - 1 ⁢ r m - 1 + … + a 2 ⁢ r 2 + a 1 ⁢ r + a 0 = ∑ j = 0 m - 1 ⁢ ⁢ a j ⁢ r i , where ⁢ ⁢ r = 2 k . in this representation , the number a is represented in block form where each of the m blocks includes k bits . that is , each a i represents an integer having k bits . in the present system , multiplication modulo an odd number n is a significant object . also , for purposes of understanding the present invention , the symbol n is used to denote the number of bits in the binary representation for n . also , for present purposes , it is assumed that the number a , as stored in register a ( reference numeral 10 in fig1 ), is the number that is partitioned into m blocks . in general , the number of blocks m is selected to be the smallest integer for which mk ≧ n + 2 . additionally , it is understood that n 0 represents the least significant k bits of the number n . likewise , the constant s is equal to the negative reciprocal of n 0 taken modulo r ( that is , − 1 / n 0 mod r ). from a mathematical point of view , the present applicants have employed an algorithm for which the input variables are the two numbers being multiplied , namely , a and b , the modulo number n , the constant s associated with n , and the parameters m , k and r = 2 k . the output of the function provided by the present invention z is given by z = ƒ ( a , b )= ab 2 − mk mod n . the procedure specified by applicants &# 39 ; method initializes the value z 0 to be zero and , for the integer i ranging from 0 to m − 1 , calculations are carried out to produce x i and y i and z i + 1 . the values for x i and y i are computed during a first operational phase of each one of m cycles . the value z i is computed during a second phase of each cycle . the adders and multipliers used to calculate x i are “ time shared ” to also carry out the calculation needed to produce z i . in particular , at each stage i , x i is given by z i + a i b . at this stage , the value of y i is also computed as the constant s times the least significant k bits of x i modulo r . if one represents the least significant k bits of x i as x i , 0 then y i = s x i , 0 . this completes the operations that are carried out in a first phase ( x - phase ) during one of the cycles of the present process . in the second phase ( z - phase ), an updated value for z register ( 50 in fig1 ) is computed as ( x i + y i n )/ r . at the last stage of processing , the desired value of z is present in the z register . in particular , at this stage , z m = ab 2 − mk mod n . at each stage ( cycle ), values for x i , y i , and z i are stored for purposes of computation in subsequent steps . it is noted that if both input variables a and b have n + 1 bits , the output of the function provided by the present invention z = ƒ ( a , b )= ab 2 − mk mod n , for n being an n - bit odd number , has no more than n + 1 significant bits . that is , the output is less than 2 n + 1 . the hardware circuit described herein takes as inputs a and b of n + 1 bits each and generates as output z of n + 1 bits . a hardware circuit for carrying out this process is illustrated in fig1 . in particular , the factor a of n + 1 bits , which is the factor which is treated as being in partitioned form , is stored in a register ( 10 ). multiplexor 11 supplies sequential blocks of k bits from register 10 to multiplexor 31 , with k = 32 bits for illustration . multiplexors 31 , 21 , and 52 operate in conjunction with one another selecting one of two possible input values depending upon whether or not the circuit is operating in the x - phase or the z - phase . accordingly , during the first phase of its operation , multiplexor 11 provides the k bits in a 0 . in the first phase of the second cycle , the next k bits a 1 in a are supplied via multiplexor 11 . a sub - block of k bits from a is provided during the initial or x - phase portion of each cycle . in the third cycle , multiplexor 11 , therefore , provides the next k bits in a , namely , the bits denoted above and herein as a 2 . accordingly , multiplexor 11 is seen to operate selectively as a function of the cycle number ( namely , cycles 0 through m − 1 ). during the x - phase of each cycle , the value a l is selected from the a register ( 10 ) via multiplexor 11 and correspondingly multiplexor 21 selects the contents of the b register ( 20 ). thus , in accordance with the present invention , the numbers to be multiplied are stored in registers 10 and 20 . it does not matter which number is stored in which register . it is also noted that , whether or not the circuit is operating in the initial x - phase or in the final z - phase in each cycle , multiplexors 31 and 21 supply k bits and n + 1 bits , respectively , to multiplier array 70 in each phase . it is thus seen that , during the x - phase , multiplexors 31 and 21 select contents from the b register and part of the a register . it is also noted that , in typical situations , the value of n is often around 512 or more and the value of k is approximately 32 . accordingly , it is seen that multiplier array 70 strikes a balance between 1 bit × n bit multiplication and full n bit × n bit multiplication . it is also noted that increases in the value of n are almost always , in practice , an increase by a factor of at least a power of 2 . as with any binary multiplier with inputs that are n + 1 bits wide and k bits wide respectively , multiplier array 70 produces an output which is n + 1 + k bits wide . the lower order k bits from multiplier array 70 are supplied to adder 65 which is designed to add two k bit addends at a time . in this regard , it is noted that adder 65 is present in the circuit for computing y i . as such , and given that the value of y i is dependent upon the last k bits of the value x i which is a sum which has not yet been fully computed , it is necessary to perform this addition which is essentially the addition for the low order k bits of x i . the first addend comes from the rightmost k bits in the z register as selected by multiplexor 52 . these bits are added to the k bits in the rightmost portion of the product a i b . the output of adder 65 is x i , 0 which is the least significant k bits of x i = z i + a i b . this output is stored in register 55 and is also supplied to multiplier 80 which multiplies two k bit numbers together . this is not , however , a multiplication modulo n . the other factor supplied to multiplier 80 is the number s from the s register ( 60 ). since this result is required modulo r , only the rightmost k bits from multiplier 80 are supplied back to the y register ( 30 ) in this x - phase . the value stored in this register is used during the calculation carried out in the z - phase as discussed below . the rest of the x - phase calculation is devoted to calculation of the high order n + 1 bits of the sum z i + a i b . multiplier 70 is configured as a circuit for multiplying together the bits from the b register ( 20 ) and a sequence of m blocks of k bits each from selected k bit blocks a i from the a register . multiplication of two k bit numbers generally produces a number having 2 k bits and , in particular , this is the situation with respect to applicants &# 39 ; multiplier 80 . however , it is noted that the calculation of y i is computed modulo r . the modulo requirement of the computation is easily accomplished simply by returning only the rightmost k bits from the output of multiplier 80 to the input of the y register ( 30 ). as pointed out above , multiplication of numbers generally produces outputs having bit lengths greater than either of the two input number bit lengths . in particular , with respect to multiplier 70 , the output is considered to be n + 1 + k bits in length . the low order ( rightmost ) k bit output is supplied from multiplier 70 to adder 65 . however , each k bit block multiplication carried out in multiplier array 70 produces 2 k bits formed as a k bit “ result ” and a k bit “ carry ” into the next position . the summation to produce the desired intermediate output a i is carried out in adder 75 which adds together two portions , the first portion which is n + 1 bits long and the second portion which is only n + 1 − k bits long . the n + 1 − k bits represent the “ carry ” portion of the multiplication . accordingly , the output of adder array 75 is the result of the high order n + 1 bits of a i b . this result is supplied directly to adder array 85 which adds to it a shifted value of z i from z register 50 . and appropriately , this high order n + 1 bits of x i = z i + a i b is stored in z register 50 in preparation for the z - phase calculation . the low order k bits of x i are stored in register 55 as described above . in the z - phase of an operation cycle , multiplier array 70 and adders 75 and 85 are again employed except that now the inputs to multiplier array 70 are the contents of they register ( 30 ) as selected by multiplexor 31 . the other factor supplied to multiplier array 70 is the contents of the n register ( 40 ) which is selected during the z - phase of an operation cycle by means of multiplexor 21 . as before , multiplier array 70 computes the product of an n + 1 bit number and a k bit number . adder array 75 performs the natural addition operation associated with multiplication in which there is an effective carry - like operation from one k bit subfield to the next k bit subfield . accordingly , the output of adder array 75 during the z - phase of operation is the high order n + 1 bits of the product y i n . the addition of y i n and the value x i together with its division by r in the present method is accomplished by discarding the low order k bits from the output of adder 65 and storing only the high order n + 1 bits from adder 85 to register 50 . the differences in the x - phases and z - phases of operation are more fully appreciated from an inspection of the differences between fig2 and 3 . in particular , fig2 illustrates the active data flow paths that are present in the first or x phase of each operational cycle . likewise , fig3 illustrates the data flow paths which are active during the second or a z - phase of each operational cycle . the calculations that are carried out in the x - phases and z - phases are repeated a total of m times with the final result z m being one of the desired results at the end of m cycles of operation with each cycle including an x - phase and a z - phase . at this stage of operation , the value present in z register 50 is ab 2 − mk mod n . the circuit illustrated in fig1 - 3 is also capable of producing the multiplicative result ab mod n . this is accomplished by first using the circuit shown to compute ab 2 − mk mod n and then by using the circuit again with either the a or b register being provided with the output from the first operational stage and multiplying this value by 2 2mk mod n . since each operation of the circuit ( through m cycles ) introduces the factor of 2 − mk , the multiplication by 2 2mk cancels the first factor 2 − mk introduced during the first stage of operation of the circuit and also cancels the other factor of 2 − mk introduced during the second multiplicative stage of operation . thus , using two passes ( two stages ) with m cycles each through the circuit of fig1 - 3 , the result ab mod n is computed . for purposes of clarity and ease of understanding and description as used herein , an operational stage of the process of the present invention refers to m cycles of circuit operation following the loading of the factors into the a and b registers . the operation of the above circuit is perhaps more easily understood by means of the following example in which k = 3 , r = 2 3 , n = 107 = r 2 + 5r + 3 =( 1 , 5 , 3 )=( n 2 , n 1 , n 0 ), n 0 = 3 , m = 3 , s =− 1 / n 0 mod r = 5 , a = 83 = r 2 + 2r + 3 =( 1 , 2 , 3 ), b = 70 = r 2 + 0r + 6 =( 1 , 0 , 6 ). decimal digits are employed here merely for the sake of example and for an easier understanding of the process . for a more detailed illustration , the decimal numbers may be represented as blocks containing 3 bits each . the process carried out by the circuit disclosed above occurs in three steps as follows ( i = 0 , i = 1 , and i = 2 ): x 0 = z 0 + a 0 b = ( 3 , 2 , 2 ), y 0 = 2 s mod r = 2 z 1 =( x 0 + y 0 n )/ r =( 0 , 6 , 5 ) x 1 = z 1 + a 1 b =( 3 , 0 , 1 ), y 1 = s = 5 x 2 = z 2 + a 2 b =( 2 , 4 , 1 ), y 1 = s = 5 although it is the objective to compute ab mod n where ab and n are all n bits long , for convenience , the process herein employs a , b , and z registers that are n + 1 bits or mk bits long . this avoids the necessity for checking the final and intermediate results to determine whether or not they are in fact greater than n . this aspect , for example , shows up in step 2 in the example provided above . the present inventors have also recognized that , at least partly due to the typically large difference between the size of n and k , there is a certain disparity in processing that occurs in the construction of an n by k multiplier . accordingly , it is possible to partition the calculation carried out in the circuit shown in fig1 - 3 . in particular , the circuit shown in fig1 is in fact constructable in the form a plurality , d + 1 , of processor elements ( pe ) which are connected together in a chained or cascaded fashion . each of the processing elements is constructed in the same way . however , the processing element for the rightmost portion of the data , herein referred to as pe 0 , has a somewhat more complicated structure , as shown in fig4 . a simpler circuit is employed for processing elements 1 through d . however , in preferred embodiments , the leftmost or last processor element pe d can in fact be constructed much more simply as shown in fig6 . accordingly , fig4 shows a structure for a processing element circuit for the rightmost portion of the data . fig5 illustrates a circuit for a processing element which is usable in a repeated fashion which utilizes as many individual processing elements as necessary and thus , illustrating the scalability aspects of the present invention . lastly , fig6 illustrates a preferred , simplified embodiment for the last or leftmost processing element . for purposes of understanding and appreciating the present invention , the registers r 0 through r d , as illustrated in fig4 , 5 , and 6 , are not considered as a part of the processing elements per se but rather are best understood as part of a separate , partitioned register structure . it is these registers that contain the desired results of the modulo n multiplication operation . these registers thus serve the same function as the z register in fig1 . with specific reference to fig4 , it is seen that multiplexor 193 operates during the x - phase to supply a 2 k bit augend to adder 185 . during the first or x - phase of operation , multiplexor 193 supplies a 2 k bit number which has leftmost bits from register r 2 ( reference numeral 192 ) and rightmost bits from register r 1 ( reference numeral 191 ). during the second or z - phase of prosecution , multiplexor 193 supplies a different 2 k bits of data to adder 185 . in particular , during the z - phase multiplexor 193 supplies as its leftmost k bits the contents of register r 1 , and as its rightmost k bits the contents of register r 0 ( reference numeral 190 ). in contrast to the full - width registers 10 , 20 , 40 , and 50 in fig1 , the corresponding registers in a partitioned system have fewer bits . in particular , the corresponding b and n variable registers in a general processing element pe preferably employs a width equal to 2 k bits . however , for the rightmost processing element , a larger number of bits is desired . in particular , in the case in which n equals 512 , registers 120 and 140 in fig4 preferably have a width of 96 bits . multiplexor 121 selects the contents of register b ( reference numeral 120 ) during the x - phase of computation and likewise selects the contents of register n ( reference numeral 140 ) during the z - phase of computation . in general , the overall n - bit wide series of computations is broken down into partitions of any convenient size . it is not even necessary that all of the processor elements are the same size or process the same data width . however , for conveniences of circuit design and circuit layout , it is preferable that each of the individual processing elements ( except for the rightmost element , pe 0 ) have the same data processing capability in terms of data width . therefore , in general , for purposes of consideration and discussion herein , it is assumed that there are a total of d + 1 processing elements labeled from pe 0 through pe d . processing element pe 0 preferably has a structure such as that shown in fig4 , pe d has the preferred structure illustrated in fig6 , although it is noted that a more generic structure , such as that shown in fig5 , may be employed for the leftmost processor element pe d though it is not necessary that this leftmost processing element be any more complicated than that shown in fig6 . also , for purposes of convenience of circuit design , layout , and packaging efficiency , it is generally desirable that the data width , w , of each processing element be an integer multiple of k . in the designs presented herein for a value of n = 512 , processor elements pe 1 through pe d − 1 , each process data in 2 k bit wide chunks . thus , in this example , w = 2 k , where w is the width of the data in each of the typical or generic forms of processing element , as illustrated in fig5 and 5a . it is noted that processor element pe 0 as shown in fig4 possesses an extra k bit processing capability , as is more particularly described below . thus , if each typical processing element pe 1 processes data in w bit wide chunks and if there are d + 1 processing elements with the rightmost processing element processing an extra k bits , then it is the preferred case that n = wd + k . thus , in general , the output of multiplexor 121 preferably comprises w + k bits . the leftmost third of these bits are supplied to multiplier 173 , the middle third of the bits in register bn ( reference numeral 198 ) are supplied to multiplier 172 , and the rightmost third bits are supplied to multiplier 171 . multipliers 171 , 172 , and 173 are thus each k bit by k bit multipliers . in this regard , it is noted that the original relatively large multiplier array 70 in fig1 employs an n by k multiplier . however , it is noted that the partitioning of the computation into a system employing a plurality of nearly identical processing elements results in the construction of circuits which now utilize multipliers which operate much more quickly since each multiplier now is typically only k bits by k bits . and clearly , since k is typically much less than n , processing takes place significantly faster . the leftmost of the 2 k bits output from multiplier 173 are supplied as a partial product out ( ppo ) to the next unit in the chain . in particular , it should be appreciated that in the discussions herein , that the natural order of processing is from the rightmost on through to the leftmost processing element in the chain ( see fig7 ). thus , data is passed from one processing element to the processing element on its immediate left . however , it should be noted that left and right are relative terms useful essentially only for descriptive and understanding purposes . the rightmost k bits from multiplier 173 are supplied as the leftmost k bits of a 2 k bit augend supplied to adder 175 . the rightmost k bits of this 2 k bit augend are supplied from the lower or rightmost k bits of multiplier 172 . thus , the rightmost k bits of multipliers 173 and 172 , respectively , are combined , as shown in fig4 , to supply a 2 k bit wide augend to adder 175 . adder 175 also has as its other input a 2 k bit augend which is supplied from the leftmost k bits of multiplier 172 and 171 , respectively , with multiplier 172 supplying the leftmost k bits of the 2 k bit augend and with multiplier 171 supplying the rightmost k bits of the 2 k bit augend supplied to adder 175 . thus , adder 175 is a 2 k bit wide adder . an equivalent but alternate connection arrangement is shown in fig4 a . multiplexor 152 operates to select , during the x - phase of computation , k bits from register r 0 ( reference numeral 190 ). during the z - phase , multiplexor 152 selects as its input the contents of temporary register 150 containing the variable x 0 . the output of multiplexor 152 is supplied to adder 165 which is k bits in width . adder 165 receives two augends , namely , the rightmost k bits from multiplier 171 and the k bits supplied from multiplexor 152 . the output of adder 165 is stored in temporary register 150 and is also supplied to multiplier 180 which is also a k bit by k bit multiplier . the other factor supplied to multiplier 180 is the contents of register 160 which contains the variable s . ( the calculation of s as − 1 / n 0 mod r is efficiently carried out in the circuit shown in fig1 which is discussed in detail below .) the output of multiplier 180 is supplied to register 130 which thus contains the value y as defined by the algorithm set out above . the output of register 130 is supplied to multiplexor 131 and is also supplied to the next processing element pe 1 ( see fig5 ). multiplexor 131 operates to select a portion of the variable a which is one of the factors in the multiplication operation . ( other k bit wide portions of variable a are selected by their respective processing elements .) in particular , register 110 contains the rightmost k bits of the variable a . thus , during the x - phase of operation , multiplexor 131 operates to select the contents of register 110 to be supplied to multipliers 173 , 172 , and 171 , as shown . likewise , during the z - phase of computation , multiplexor 131 operates to select the variable y from register 130 to be supplied to this same set of multipliers as the other factor . a carry - out signal line from adder 165 is also supplied as a carry input to the lowest order position in adder 185 , as shown . additionally , adder 175 supplies a first carry - out signal line to the next processing element in the chain ; similarly , adder 185 also supplies a second carry - out signal line to the next processing element in the chain . in particular , since fig4 illustrates processing element pe 0 , carry - out signal line 1 and carry - out signal line 2 are both provided to processing element pe 1 . the connections between pe 0 and pe 1 are readily apparent simply by placing fig4 to the right of fig5 . in particular , processing element pe 0 supplies the variable y , the partial product out , and the two carry - out signal lines to the inputs shown in pe 1 of fig5 . in particular , it is also noted that the variable y ( that is , the contents of register 130 ) is supplied to each one of the individual processing elements . and lastly , with respect to fig4 , it is noted that the output of adder 185 is supplied to registers r 0 and r 1 shown at the top of fig4 . as indicated above , it is the register set ( containing r 1 and r 0 on the right ) which ultimately contains the desired calculation result . accordingly , reference numeral 100 in fig4 describing processing element pe 0 does not include this register set . this register set is discussed separately below in terms of some of the other variations and structures that are employed in the present invention . attention is now directed to a discussion of fig5 which illustrates a more typical processor element and , in particular , which illustrates the form of a processor element which may be repeated in a circuit / system chain which is as long as is required to process factors which are n bits wide . with specific reference to fig5 , it is noted that it is similar to fig4 except that the part of the processing dealing with k bit wide operations involving s and n 0 need not be present in any processing elements except the rightmost one , namely , pe 0 . in particular , fig5 indicates that the generic form of a processing element pe p bearing reference numeral 200 specifically does include register bn ( reference numeral 298 ) but does not include the other registers shown . one of the significant differences between fig4 and 5 is that register 220 contains only a portion of the bits for the second factor b . in particular , register 220 contains 2 k bit wide chunks designated as b 2p + 2 and b 2p + 1 , where p ranges from 1 to d − 1 . again , as above , multiplexor 221 selects either the 2 k bits from register 220 or the 2 k bits from register 240 which has corresponding portions ( here 2 k bits chunks ) of the variable n . accordingly , register bn is 2 k bits wide . unlike register 198 in fig4 , register 298 ( bn ) in fig5 is only 2 k bits wide . in one preferred embodiment of the present invention when n = 512 , register bn is 64 bits wide . from an overall perspective , general processing element pe i ( reference numeral 200 as shown in fig5 ) accepts , as input from the right , the value of y , the partial product in , carry - in 1 and carry - in 2 . processor element pe 1 also has as an input the corresponding portion of the k bits of the multiplier factor a from register 210 . the register involvement for registers , 292 , 291 , and 290 is substantially as shown in fig4 except now shown in the generic version of a processor element . it is these registers that store intermediate values between phases and ultimately store the completed product , ab mod n . also , from an overall perspective , processor element 200 produces , as an output , a k bit partial product out which is supplied to the processor element on its left together with carryout signals 1 and 2 which are supplied to the corresponding adders 275 and 285 in the processor element on the left . the output of adder 285 is supplied back to registers r 2p + 1 and r 2p . accordingly , other than the connections to the register sets for r , b , n , and a , the processing elements are connected simply by matching partial products in and out and carries in and out 1 and 2 . accordingly , in systems constructed in accordance with those aspects of the present invention which employ a plurality of similar processing units , the overall system is constructed by starting with the circuit shown in fig4 or 4 a as a rightmost position and placing , in adjacent positions , processing elements similar to those shown in fig5 or 5 a . the overall configuration , therefore , is seen in fig7 . however , before proceeding , it is useful to consider the fact that the leftmost processor element pe d does not have to be as complicated as the processing elements to its right such as these shown in fig5 or 5 a . in particular , the leftmost processing element only needs to process k bits . in the x - phase of operation , the circuit shown in fig6 acts to add carry - in 1 to the partial product input to the leftmost processing element via increment - carry circuit 375 . likewise , adder 385 adds carry - in 2 to the other input to adder 385 to produce an output which is supplied to register r 2d in the immediate preceding processor element . in the z - phase of operation as controlled by and - gate 399 , the contents of register r 2i ( reference numeral 390 ) are added to the output of increment carry circuit 375 and this is also supplied to register r 2i in the feedback configuration as shown . accordingly , it is seen that in partitioned embodiments of the present invention , it is preferable to employ a leftmost processing element which is simpler than that which is generally required in one of the generic processing elements between the rightmost and leftmost elements . however , while preferable , this substitution is not mandatory . the partitioning of the computational problem as provided in one embodiment of the present invention into a solution having a plurality of nearly identical processing elements provides significant advantages in terms of design , efficiency , layout , and structure . concomitantly , these advantages also lead to advantages in circuit speed and throughput . however , it is also very important to note that the partitioning into a plurality of processing elements also provides significant advantages in terms of the fact that a pipelined operation is now possible . in particular , while pipelined operations generally introduce a small initial delay , the total throughput , as measured in terms of modulo n multiplications per time unit is significantly improved . accordingly , a significant portion of the description below is devoted to a discussion of the use of the described partitioned processing element structure in conjunction with a pipelined method for operating the circuits shown in fig4 , 5 , and 6 , and variations thereof . however , before embarking on a discussion regarding the pipelining aspects of the present invention , it is also useful to note that the circuits shown in fig4 - 7 are perfectly capable of operation in a non - pipelined fashion . such a mode of operation is illustrated in fig8 . in particular , it is noted that fig8 is a logical time - sequence diagram illustrating the use of the register set r 0 through r 33 as a final and temporary storage medium for passing information between the x - phase of computation and the z - phase of computation . fig8 also more particularly illustrates the distinction pointed out above between the register set and the individual processing elements . this figure also illustrates the unique positions for the rightmost and leftmost processing elements wherein the rightmost element is supplied with information from three registers and wherein the leftmost processing element receives direct information only from the leftmost portion of the register set , namely , r 33 since , in this particular case , n is assumed to be 1 , 024 and k is assumed to be 32 . not shown in fig8 are the signal connections between the processing elements . rather , fig8 is meant to be illustrative of time sequencing and the utilization of the register set . in particular , it should also be noted that , in fig8 , the processor elements in the upper half of the illustration are all operating in the x - phase at the same time , and likewise , all of the processing elements in the lower portion are operating in the z - phase . variations of this operational modality are more particularly described below with respect to fig9 and considerations relating to pipelining of the information into and out of the circuit . in the case of no pipelining , such as shown in fig8 , all of the processing elements start to process data at the same time and finish at the same time . in any given clock cycle , all of the processing elements are either all in the x - phase or are all in the z - phase of calculation . in this node , each processing element updates a fixed slice of the complete partial result register ( two r i registers ). since all of the partial product registers are updated at the same time , everything works smoothly in accordance with the algorithm described above . attention is now directed to that aspect of the present invention in which the processing elements are operated in a pipelined fashion . in order to achieve this result , certain hardware modifications are made to the circuits shown in fig4 and 5 . these modifications are more particularly illustrated in fig1 and 11 , respectively , to be discussed more particularly below . however , for purposes of better understanding the utilization of the processing elements in a pipelined fashion , attention is specifically directed to fig9 . in the pipelined approach , it is the case that , in a given clock cycle , any two adjacent processing elements are always in different phases with the processing element processing the less significant slice of data always being one clock cycle ahead . as seen by the circular arrows in fig9 , it is unfortunately the case that , while a given processing element is in the x - phase , it requires , as input , a 32 - bit value from the z - phase that is being calculated at the same time by the next processing element in the chain that is still in the previous z - phase . for example , as shown in fig8 , the rightmost processing element pe 0 on the top right is in the x - phase . this requires , as an input , the value in r 2 from processing element pe 1 which is one clock cycle behind in the z - phase . this problem is solved by adding a feedback paths from the next processing element in the chain , which links to a k - bit adder ( see reference numeral 235 in fig1 and reference numeral 135 in fig1 ). this solution creates additional delay due to the presence of a new k - bit adder . however , the maximum working frequency is not significantly affected since a k - bit adder is a relatively fast circuit . additionally , it is noted that the previous signal path , before this change , was not a critical path . the original critical path occurred in the rightmost processing element pe 0 due to the calculation of the constant y . the advantage to this particular solution is that there is no need to modify the formulas in the algorithm ; however , on the other hand , the maximum frequency is nonetheless slightly effected . additional variations , to be considered more particularly below , consider this minor problem and provide yet another solution which eliminates the delay introduced by adder 235 and 135 . in any event , either of the two pipelining solutions presented is an improved solution over that provided by the purely parallel approach illustrated in fig8 . as pointed out above , fig1 is similar to fig5 , but more particularly illustrates the inclusion of extra hardware elements that are used to achieve smooth operation in a pipelined fashion . in particular , latches 232 , 233 , and 234 are added as temporary storage mechanisms between processors elements for holding the k bit wide partial products out ( ppo ), and the single bit carry - out lines 1 ( from adder 275 ) and 2 ( from adder 285 ). additionally , it is noted that latch 231 stores either the selected k bit wide portion of multiplier factor a i or the constant y . this is provided in an alternating fashion from multiplexor 131 ( as shown in fig1 ). additionally , it is noted that the lower k bits from the output of adder 285 are supplied to the adjacent adder 235 which is actually present in the preceding processing element , namely the one to the right . in a similar fashion , the lower k bits from the next ( that is , the left ) processing element are supplied to adder 235 . additionally , there is a feedback connection ( not shown for reasons of drawing congestion ) from the output of adder 235 to the corresponding segment of the register “ set ,” namely , to r 2p + 1 . similar changes in the circuit are made to the rightmost processing element pe 0 , as shown in fig1 . in particular , latches 131 , 132 , 133 , and 134 are added to serve a function that is the same as that provided by latches 231 , 232 , 233 , and 234 in fig1 . and as in fig1 , adder 135 is now included to incorporate the extra addition step for pipelined operations . it is also noted that latch 131 ′ in fig1 is supplied from multiplexor 131 . it is from this latch that values of a i and y are supplied to subsequent processing elements in the chain . in this regard , it is also noted that register 110 containing the value a i is illustrated in fig1 as a k bit register , while in fact the preferred embodiment is the one illustrated in fig1 in which a long a register with n + 1 bits provides information to a multiplexor which selects subsequent k bit wide chunks from the contents of the a register . accordingly , register 110 in fig1 is preferably constructed as illustrated from register 10 and multiplexor 11 in fig1 . the simplification shown in fig1 is only for clarity and for ease of understanding . also , as is seen in the corresponding portion of fig4 , the output of multiplexor 121 is preferably w + k bits wide where w is the width of the data chunks processed by each of the generic processing elements . before proceeding to a discussion of yet another preferred embodiment of the present invention , it is worthwhile to consider the development described so far so in order to provide some overall perspective . in particular , a first preferred embodiment of the present invention provides a circuit such as that shown in fig1 which employs relatively large multiplier and adder arrays . in a second preferred embodiment , the adder and multiplier arrays are partitioned so as to be deployed in a chained sequence of individual processing elements with each one possessing the same structure and passing information from the rightmost to the leftmost processing elements in a system which efficiently carries out the same operations as shown in fig1 . in a third preferred embodiment of the present invention , the processing elements are further provided with an additional adder and latches which enable the processing elements to be operated in a pipelined fashion , such as illustrated in fig9 . in the next preferred embodiment of the present invention which is now considered in detail below , additional adders 135 and 235 are repositioned in the circuit so as not to negatively impact critical dataflow paths . it is now this embodiment which is described . in particular , in this embodiment , the processing elements and register sets are configured as shown in fig1 . in particular , it is noted that , in fig1 , the register connections to the individual processing elements are in fact different . this difference is due to the repositioning of the adder . in particular , fig1 illustrates the repositioning of adder 135 from fig1 and likewise , fig1 illustrates the repositioning of adder 235 from fig1 to the position shown as adder 435 ′ as shown in fig1 . accordingly , the design illustrated in fig1 and 11 for pipelined operations is improved even further by moving the indicated adder to the input stage of the processing elements which is facilitated by eliminating certain feedback paths between the processing elements , as shown . the adder is moved from the output of the processing element to the partial product input ( r register path ) and works in parallel with the slower multiplier function blocks . this eliminates an adder from a critical path . from fig9 , it can be seen that when processor element pe p is in the x - phase , it requires an input from both register portions r 2p + 2 and r 2p + 1 . the r 2p + 1 value is actually updated by the p th processor element during its previous clock cycle . the “ problem ” is that the value in r 2p + 2 , which is supposed to be contain the value of z 2p + 2 is updated in the same clock cycle by processor element p + 1 ( pe p + 1 ). it is noted that during the x - phase , processor element pe p adds the value z 2p + 2 contained in r 2p + 2 to the upper k bits of its output and loads the result into r 2p + 1 ( this is the x 2p + 1 value ). given that the contents of register r 2p + 1 are used and updated exclusively by pe p , one can proceed as follows : ( 1 ) during the x - phase , processor element pe p does not add the value of r 2p + 2 to its output before loading r 2p + 1 ; and ( 2 ) during the z - phase pe p receives as an extra input , the value in register r 2p + 2 ( which at this time has been updated by pe p + 1 with z 2p + 2 and adds this immediately to the r 2p + 1 input before any further processing ). the modifications to the circuit shown in fig1 , which are illustrated in the circuit of fig1 , are designed to accomplish these goals . the consequence of step ( 1 ) recited in the previous paragraph is that at this point the value generated by the processing elements during the x - phase is not any more the same as described in the algorithm set forth above . in order to compensate for this difference , another term is added during the z - phase . the benefit of this change is an increase in the maximum frequency of operation and a reduction in the power of the needed by the circuit . additionally , there are also advantages in terms of a reduced need for silicon area ( that is , chip “ real estate ”) together with advantages in having a more uniform and repeatable circuit design . accordingly , fig1 illustrates the new flow of data between the r register “ set ” and the processing elements . likewise , fig1 and 14 illustrate the presence of additional circuitry to accomplish the objectives stated above . the specific changes to the rightmost processing element for the improved pipelining version of the present invention are now specifically set forth . as above , a partial product out from multiplier 173 is latched up into k - bit wide register 432 . additionally , the variable m from multiplexor 131 is latched up into latch 437 . repositioned adder 435 is an adder having a width of 2 k bits . it also receives a carry input signal ( carry - in 3 ) and includes two input signal lines . a 2 k bit wide signal comes from a combination of the output from and - gate 402 which is supplied from register r 1 ( reference numeral 191 ). register 191 also supplies multiplexor 193 which has as its other input the k bit output signal from register r 0 ( reference numeral 190 ). the output of multiplexor 193 under the control of the “ x / z select ” signal line which causes the supply of either the output of register r 1 or register r 0 as the rightmost k bits for the right input to adder 435 . ( note though that adders and multipliers are symmetric with respect to the use of left and right inputs since the desired operations are commutative .) the first ( rightmost ) 2 k bit input to adder 435 is either ( r 1 , r 0 ) or ( 000 . . . 0 , r 1 ) depending on the “ x / z select ” signal being 1 or 0 , respectively . the “ x / z select ” signal configures the circuits for x - phase or for z - phase operation . during the x - phase , adder 435 executes the following operation : ( 00 . . . 0 , r 1 )+ 0 which result is sent to adder 135 . in comparison with fig1 , it is seen that adder circuit 185 in fig1 receives ( r 1 , r 0 ) but can also receive the additional signal input ( r 2 , 00 . . . 0 ). the reason for this option is based on pipelining operations because in such a mode the processing element ( pe ) on the left is always behind one clock cycle . for example , since pe 1 in fig1 is responsible for updating the r 2 register with the z value , this means that during the x - phase pe 0 needs the z value stored in r 2 in pe 1 which is still generating it . thus , in fig1 , adder 135 is used to transform the x - value in r 2 to the successive z value . however , in contrast in fig1 , the value in r 2 is added later in the next phase ( a z phase ) via adder 435 which is not in a critical path . the signal “ select r 2 ” is always ‘ zero ’ while the signal “ x / z select ” controls the x and z phase during modular multiplication . this signal , when set to ‘ one ’ provides the capability of performing regular multiplication as opposed to modular multiplication as needed , or as desired . for regular multiplication , the “ x / z select ” signal line is always “ zero ” while the “ select r 2 ” signal line is always “ one .” the other input to adder 435 is a 2 k bit wide signal whose rightmost k bits , driven by the and - gate 401 , are all zeros during a modular multiplication or equal to the register r 2 value during a standard multiplication as determined by the signal “ select r 2 ”. the output of and - gate 401 is connected now to the lower k bits of the leftmost 2 k bit input to adder 435 . the leftmost k bits of this second input comes from register r 2 ( reference numeral 192 ) under the control of the “ x / z select ” signal line which controls and - gate 403 . and - gate 403 is , like multiplexor 193 , also under control of the “ x / z select ” signal line , as shown . the reconfiguration of the adder &# 39 ; s input signals is necessitated by the repositioning of adder 135 to a position which is not in a time - critical path . the functioning of signal line “ select pe 0 ” is now more particularly described . the inclusion and functioning of this control line is not related to the repositioning of adder 435 . when signal line “ select pe 0 ” is “ one ” the hardware in the processing element becomes equivalent to the generic hardware processor element p i ( 1 ≦ i & lt ; d ). when the “ select pe 0 ” signal line is set to “ one ,” multiplier 406 selects the “ previous p ” input signal bus and provides it to adder 175 ( which is equivalent to adder 275 in pe i ). the output of and - gate 405 changes from “ zero ” ( in the case of pe 0 functioning ) to the value driven by the carry input signal line for adder 175 ( or 275 in pe i functioning ). multiplexor 404 selects the “ carry in 2 ” signal line and provides it as a carry input to adder 185 or 285 in pe i functioning ). accordingly , the “ select pe 0 ” signal line is used to “ disable ” the following devices so that the processing element operates as a generic pe i rather than as pe 0 : multiplier 171 , adder 165 , multiplexor 152 , multiplier 180 , register 150 and register 160 . there are two cases in which it is desired that the “ select pe 0 ” signal line should be driven into the “ one ” state . this means that the pe behaves specifically like a generic pe i as opposed to the rightmost pe 0 . the first case is when the system is designed comprising two separate chains of processing elements . for example , each of the two chains is made up of a concatenation of one pe 0 together with seven pe i &# 39 ; s ( that is , with eight processing elements per chain ). these two chains ( with eight pe &# 39 ; s each ) are particularly useful in carrying out operations of modular multiplication involving public key cryptography algorithms such as the rsa algorithm using the chinese remainder theorem ( crt ). in such cases , each of the two chains operates independently to perform two modular multiplications . in the case of modular multiplication as described above , there is thus provided a command which effectuates this operation together with an exponentiation function which is described in more detail below . in this case , the two chains of processing elements are concatenated to form a longer chain that is thus able to process more data in the same amount of time . in this case , the “ pe 0 ” on the rightmost position of the left chain behaves as a pe 1 and receives the inputs from pe 7 ( here “ 7 ” is used as an example which is in harmony with the exemplary chain size of eight , as recited above ) from the right chain . this is accomplished by setting the “ select pe 0 ” signal to “ one .” these two chains may be represented diagrammatically as follows : pe 7b pe 6b . . . pe 1b pe 0b ⇄ pe 7a pe 6a . . . pe 1a pe 0a in the event that the hardware herein is not being operated in the chinese remainder theorem mode ( to be discussed in more detail below ), pe 0b acts as a pe 1 and its “ select pe 0 ” signal input line is set to “ one .” there is also one other input control signal that is set to “ one ” in order to have pe 0b act as a pe i . in particular , this signal line is labeled “ auxiliary select ” in fig1 . more particularly , control line “ select pe 0 ” controls the operation of multiplexors 404 and 406 and and - gate 405 . in the pe 0 mode of operation , the carry - in 1 signal line is supplied to adder 175 together with the signal from the previous pe signal line coming in to the modified rightmost processing element shown in fig1 . if it is not in “ pe 0 mode ,” no carry input is supplied to adder 175 . likewise , based upon the state of the “ select pe 0 ” signal line , multiplexor 404 operates to select , as a carry input to the low order position of adder 175 , either the usual carry - out signal from adder 165 or , in the event of non - pe 0 mode operation , the signal supplied to the carry input of adder 185 is the carry - in 2 signal . apart from these variations , the rest of the circuits shown in fig1 operate in substantially the same manner as their counterparts in fig1 . fig1 also introduces several other signal lines for proper operation in various hardware modes . as described above the “ auxiliary select ” signal line is a 2 bit signal taking on the values “ 00 ,” “ 01 ,” or “ 10 .” the “ auxiliary select ” line has the value “ 10 ” to pe 0b above to concatenate pe 0b with pe 7a on its right in the case of non - crt operation . this is the only time that the “ auxiliary select ” signal bus is set to this value . in the other cases , this signal line is set to “ 01 ” during the z - phase ( select x / z = 1 ). the “ 00 ” value of “ auxiliary select ” selects the a i input used for the x - phase while the “ 01 ” value for this signal line selects the y input for the z - phase of operation . with respect to the other signal lines present in fig1 , the “ select r or x ” signal line is equivalent to “ select x / z ”; and the “ select r 2 ” signal line is driven independently when the processing elements are used to perform standard multiplication operations as opposed to modular multiplication . the “ select b or n ” signal line assumes the value given by “ select x / z ” during the next clock cycle ( that is , the anticipated version of “ select x / z ”). the reason for this is that the output of multiplexor 121 is used to select what is stored in bn register 198 which contains b during an x - phase and n during a z - phase . fig1 illustrates modifications made to the circuit shown in fig1 to accommodate repositioning adder 235 in fig1 to a position in the signal flow path which reduces time criticality with respect to addition operations . with respect to the specific differences between fig1 and 14 , it is noted that , in fig1 , it is no longer necessary to supply the low order k bit output from adder 285 to the processing element to the right . additionally , it is noted that instead of the signal line being labeled a i / y , the input signal line is labeled m to reflect the fact that multiplexor 131 in fig1 now has three possible inputs to select from rather than just a i or y . the third input of multiplexor 131 ( that is , the “ previous m ” signal line ) is used to concatenate pe 0b to pe 7a ( as per the example given above ) during non - crt operations . this allows on - the - fly construction of a long chain of processing elements ( sixteen in the example ) versus two independent chains of half as many ( that is , eight in the example ) processing elements . additionally , adder 435 ′ which is 2 k bits wide is now interposed between its corresponding register set segment and adder 285 . in particular , the output of adder 435 ′ is supplied as the second input to adder 285 and the carry out of adder 435 ′ is supplied to latch c 3 ( reference numeral 436 ) which supplies the carry - out 3 signal line . the contents of register r 2p + 2 ( reference numeral 292 ′) which is k bits in width is supplied as the lower k - bit portion of the left adder input under control of and - gate array 401 which is in turn controlled by the signal line “ select r 2p + 2 .” the contents of register r 2p + 2 are also supplied as the upper k - bit portion of the left adder input under control of and - gate array 403 which is in turn controlled by the “ x / z select ” signal line . the right input to adder 435 ′ is also 2 k bits in width and is supplied from and - gate array 402 and from multiplexor 493 . under control of the “ x / z select ” signal line , multiplexor 493 provides either the contents of register r 2p + 1 ( reference numeral 291 ′) or the contents of register r 2p from the processing element on the right . the 2 k - bit data portion supplied to the left input of adder 435 ′ is controlled by and - gate 401 and by and - gate 403 . the right 2 k - bit input to adder 435 ′ includes two portions one of which is a high order k bit wide portion which is either zero or the k - bit data portion coming from register r 2p + 2 ( reference numeral 292 ′) control of and - gate array 401 which is also under control of the “ select r 2 ” signal line . the lower order k bit wide portion of the right input to adder 435 ′ is selected by multiplexor 493 to be either the contents of register 291 ′ ( that is , r 2p + 1 ) or the contents of the 292 ′ register ( that is , r 2p ) in the processing element to the right . the operation of the circuits described produces the result that adder 285 ( fig1 ) accumulates the results of the multiplication operations performed by multipliers 272 and 273 together with the output of adder 275 . the left input of adder 285 is dependent on the phase of the operation for the processor element containing adder 285 . for example , during the x - phase , the result is ( 00 . . . 0 , r 2p + 1 ) while during the z - phase , the result is the binary sum ( r 2i + 1 , r 2i )+( r 2i + 2 , 00 . . . 0 ), where “ 00 . . . 0 ” is k bits wide . the term including r 2i + 1 is added only during the z - phase since , during the x - phase , this register value is still being updated by the processing element to the left . this aspect is best seen in fig1 . additionally , it is noted that if one desires to employ a simplified leftmost processing element such as one that is similar to that shown in fig6 , modifications are made to this circuit to accommodate the improved pipelining version associated with fig1 and 14 . in particular , this is accomplished by the inclusion of an increment - carry circuit 439 between previously employed and - gate array 399 and k bit wide adder 385 . the other signals supplied to increment carry circuit 439 is a carry input c in which comes from latch 436 in the processing element to the immediate right of the circuit shown in fig1 . in particular , this signal line is designated as carry - out 3 in fig1 . as above , the use of a simplified leftmost processing element ( pe d ) is optional but is clearly desired for purposes of circuit simplification , speed , and cost . the processing element pe end or pe d includes the function of adding the previous ppo ( partial product out ) from the pe to its right to the potential carryout signal from adder 435 ′ which signal is temporarily stored in latch c 3 ( 436 ). this result is stored in register r 2p . during the z - phase , the result of this operation is accumulated in register r 2p , as shown . it is noted that it is also possible to utilize the pipelined version of the present invention to process operands that are actually in fact wider than the hardware present in the processing element chain width ( n & gt ;& gt ; d or equivalently n & gt ;& gt ; mk ). the method for carrying out this extra wide operation processing is illustrated in fig1 . in particular , each horizontal line in fig1 represents a single clock cycle and each vertical column represents a slice of the data that is to be processed . assuming that each processing element processes 64 bits of data ( 2 k bits typically ), the first column indicates that the lower two k bits of the data are always processed by processing element pe 0 . during the first clock cycle , only processing element pe 0 is active . all of the other processing elements are activated sequentially , clock cycle after clock cycle . this provides sufficient time to the previous processor element to generate the pipelined data for the next processing element . in fact , it is possible that the width of the operand is larger than the processing element chain itself . for example , in the discussions herein , the situation in which n = 512 bits has been considered . however , in accordance with this aspect of the present invention , it is possible to process operands that are longer than 512 bits using a pipelined hardware structure which is designed for 512 bits . in such circumstances the clock cycle after the first processing element is activated , the entire processing element chain is shifted left by 2 k bits ( see fig1 ) leaving the lower two k bits unprocessed . this shifting continues until the upper processing element ( in this case , pe 8 ) is capable of processing the upper 2 k bits of the operand . following this , the processing element chain , instead of shifting back to the home position , stays in place with the exception of the rightmost processing element pe 0 . the lower processing element , after the others go into a home position , continues processing the lower two k - bit slice of the operand . when all of the processor elements are back in their home positions , the entire chain starts a shift left as before . this mechanism allows all of the processing elements to be busy all of the time and , accordingly , achieves a maximum performance level . additionally , a new operation can start before the previous operation is finished . the approach described herein provides maximal performance in the sense that all of the processing elements are always busy . additionally , the next operation can be started immediately without any delay and without idling any of the processor elements . furthermore , these operations are fully compatible with the pipelined approach as described above . as indicated very early above in the description for the present algorithm for computing ab mod n , it is desirable to begin the calculation with a value s which is equal to the negative inverse of the value n 0 where the inverse is now taken modulo r where r = 2 k . that is to say , in the initial presentation of the algorithm employed herein , the availability of the value s =− 1 / n 0 mod r was assumed . a circuit for carrying out this calculation is illustrated in fig1 which shows , in its upper portion , a circuit for calculating successive values of the variable q and correspondingly illustrates a circuit in its lower portion for calculating a companion variable s which ultimately becomes the desired s =− 1 / n 0 mod 2 k . in this regard , it is noted that the circuit shown in fig1 actually performs two operations . firstly , it computes a multiplicative inverse modulo , a number which is a power of 2 , and also at the same time computes the additive inverse of the multiplicative inverse . in ordinary , non - modular arithmetic , the computation of an additive inverse is a relatively simple operation requiring either the addition or change of a single bit at the leftmost portion of a representative number or at most the addition of a 1 to the low order position depending upon the format in which the numbers are stored . however , in the case of modular addition , it is noted that the operation cannot be carried out as simply as it is for ordinary , non - modular arithmetic . accordingly , it is noted that the circuit shown in fig1 actually carries out simultaneously two nontrivial operations modulo r . in particular , it computes a multiplicative inverse while at the same time ensures that the final result is the negative additive inverse modulo r = 2 k . in the context of the present invention , the algorithm set forth above for computing ab mod n employs the variable s =− 1 / n 0 modulo r . however , the circuit shown in fig1 is capable of generating the negative multiplicative inverse of any k - bit number a initially stored in the n 0 register ( reference numeral 501 ). the method employed for carrying out the formation of the desired negative multiplicative inverse is set forth below . the inputs to the process are the values k and the number whose negative multiplicative is desired , namely , a which is expressible as an ordered k - tuple of the form ( a k − 1 , . . . , a 1 , a 0 ). the desired output of this process is a variable s =− 1 / a modulo 2 k . in the process described below , the variable s is initially set equal to the value 2 k − 1 . the variable a is also initially loaded into the q register ( reference numeral 504 ) at the start of the process . accordingly , if the “ start ” signal line is “ 1 ,” then multiplexor 505 selects as its output the contents of register 501 which contain the value n 0 or , more generally , a variable a whose negative multiple inverse is to be generated . multiplexor 505 also receives as an input the output of k bit adder 503 . this adder has two inputs , namely , the leftmost k − 1 bits from q register 504 and a k bit input the value of a as stored in register 501 . adder 503 also effectively performs a shift right operation under circumstances to be described more particularly below , and accordingly , a zero high - order bit is added as appropriate to effect this shift operation with zeros being shifted into the high - order position . the process for carrying out the desired calculation resulting in the variable s being transformed to − 1 / a mod 2 k is set forth below : if rightmost bit of q , namely q 1 = 1 , then accordingly , it is seen that the process in this embodiment of the present invention occurs in k − 1 steps . at the last step , the contents of the s register are equal to the desired negative multiplicative inverse of a ( or n 0 for the specific purposes of the present invention ). it is also seen that the process for calculating the negative multiplicative inverse employs the concomitant calculation and updating of two variables , s and q . the upper portion of fig1 illustrates the updating and calculation of the variable q . in particular , it is noted that if the rightmost bit of q ( that is , q 1 ) is 1 then , via the utilization of and - gate array 502 , the contents of register 501 are added to the current value of q from q register 504 with the output being stored back in the q register via multiplexor 505 . it is noted that , at this stage of operation , the “ start ” signal line is not equal to “ 1 ” and , accordingly , multiplexor 505 selects as its input the output of adder 503 . otherwise , the initialization q = a is carried out . the circuit in the lower portion of fig1 calculates the companion variable s which is also the desired output at the end of the process . it is noted that in the updating of the variable s , in accordance with the process indicated above , one performs a subtraction from the current value of s by an amount which is equal to a power of 2 ( s = s − 2 i ). to effect the desired process , s register 560 is initially loaded with a value which is “ all ones ” representing the integer 2 k − 1 . and - gate array 561 controls the writing of particular bits into the s register . in particular as seen in fig1 , a k bit wide vector from and - gate array 561 is available for writing into register 560 . and - gate array 561 permits , during each clock cycle if necessary , the writing of a k bit vector into s register 560 . the selection of which vector is controlled by the current value in counter 563 which counts upwards from 0 to k − 1 , and then immediately back to zero again in a rollover fashion . in the examples of the present invention described above , k is typically equal to 32 bits . as such , counter 563 need contain only 5 bits . in general , counter 563 contains k ′= log 2 k . thus , decoder ring 562 receives k ′= 5 bits and produces as an output a k bit vector , only one of whose entries is 1 . this is the essential operational feature of a decoder circuit . counter 563 also supplies a signal line “ zerocount ” which is a “ 1 ” when the counter is all zeros . this signal line is also supplied to and - gate array 561 which triggers a write - enable bit when q ( 1 ) is “ 1 ” and the zerocount signal line is false and the start signal line is false . accordingly , under these circumstances , and - gate array 561 , in accordance with the algorithm described above , then permits the writing of a 0 bit into the corresponding portion of s register 560 as determined by the current value in register 563 which , in effect , contains the variable i recited in the algorithm listed above for negative multiplicative inverse calculation . it is in this fashion that the value of s is updated to s = s − 2 i . finally , at the end of the calculation , the value in the s register , which is initially set equal to all ones , is now equal to the negative multiplicative inverse modulo r of the value that was stored in the n 0 register 501 . if instead of (− 1 / a ) mod n , one wishes to calculate ( 1 / a ) mod n , one can employ the following algorithm : if rightmost bit of q , namely q 1 = 1 , then s = s + 2 i ( that is , set bit i to 1 ); accordingly , there is provided a circuit and a process for producing in a single set of operations not only the multiplicative inverse modulo r of a given number , but also , its arithmetic negative value modulo the same value r . for purposes of the multiplication algorithm of ab mod n described above , it is noted that it is the circuits shown in fig1 which are preferably employed for the calculation of the variable s =− 1 / n 0 mod r which is stored in registers 60 in fig1 , 160 in fig4 and 4a , 160 in fig1 , and 160 in fig1 . as discussed above , a primary purpose of the present invention is the multiplication of large integers modulo n for cryptographic purposes . since cryptography often involves the exponentiation operation , the use of the present hardware to perform exponentiation is now described . the relevant circuits and materials described above can be considered as implementing a specific function , f , with the following properties : if a & lt ; 2 n and b & lt ; 2 n , then ƒ ( a , b )& lt ; 2 n , and if a & lt ; 2 n and a ≠ n , then ƒ ( a , 1 )& lt ; n . in the above , the problem has been partitioned into m “ words ” of k bits each where mk ≧ n + 2 where n is the number of bits in the binary representation of n . and as above , n 0 is the least significant k bits of n . and n is , of course , odd . in the discussion above , it was pointed out that multiplication modulo n would normally be carried out in a two step process : step 1 : result 1 = ƒ ( a , b )= a b 2 − mk mod n step 2 : result 2 = ƒ ( result 1 , 2 2mk )= a b mod n . from the above properties of f , it is seen that premultiplication of either a or b by 2 mk produces the same result in one step : result = ƒ ( a 2 mk , b )= ƒ ( a , b 2 mk )= a b mod n . this is clearly the preferred approach for performing modular multiplication in one shot situation since premultiplication by 2 mk is easily performed via a shift operation . however , in the case of exponentiation , one uses the modular multiplication function , as implemented in the hardware described above , in a repeated fashion . in the present case then , exponentiation is carried out in a repeated fashion , but now one must deal with the fact hat there is a factor of 2 − mk present in the output of each iteration of the function , f , that is to say , ƒ ( a , b )= a b 2 − mk mod n . accordingly , in the present invention , the hardware implemented function f is used but with the factor 2 mk being “ preapplied ” to both of the multiplicands , a and b , as follows : ƒ ( a 2 mk , b 2 mk )= a b 2 + mk mod n . this way , since the function f introduces a factor of 2 − mk at each step , repeated iterations using preapplication of the 2 mk factor to both operands keeps a constant factor of 2 mk as part of the result . as a last step this factor is removed using the function f as implemented by the present hardware in the following manner : ƒ ( a 2 mk , 1 )= a mod n . therefore , at the last iteration in an exponentiation operation , a is the output from previous repeated applications of the function ƒ . in order to see that this value of a going into the f function hardware at this stage is constructed as an appropriate exponential , consider the general case of constructing the value a e mod n where e is an integer and in particular is an integer represented by the t + 1 bit binary value e t ⁢ 2 t + e t - 1 ⁢ 2 t - 1 + ⋯ + e 2 ⁢ 2 2 + e 0 = ∑ i = 0 t ⁢ ⁢ e i ⁢ 2 i , where e i is either “ 1 ” or “ 0 .” here , advantage is taken of the fact that a sum in an exponent becomes a product ( a x + y = a x a y ) so that : a e = ∏ i = 0 t ⁢ ⁢ a 2 i ⁢ e i = ⁢ ∏ i = 0 t ⁢ ⁢ ( a 2 i ) e i = ∏ i = 0 t ⁢ ⁢ ( a 2 ) ie i . based upon this expression for a e in terms of the binary integer e , it is seen that the following algorithm provides a method for using the hardware for the function f herein to produce the result a e mod n , a result which is very important for cryptographic operations and particularly important for public key cryptographic systems . here , n , k , m , n 0 and s (=− 1 / n 0 mod r where r = 2 k ) are as given above . the inputs to the method are the values a and e with e being a t + 1 bit binary integer . the method is summarized in the following outline : set c = 2 2mk mod n z 0 = f ( a , c ) z = z 0 for i = 1 to t z = f ( z , z ) if e t − i = 1 , then z = f ( z , z 0 ), else continue end for z = f ( 1 , z ) thus , at the end of this method the value stored in the z register is a e mod n , as desired . this procedure is also summarized in the flow chart shown as fig1 . a slightly different form of the exponentiation algorithm is implemented in fig1 . it is also described in the pseudo code provided below : set c = 2 2mk mod n z 0 = f ( a , c ) if e 0 = 0 , then set z = 1 , else set z = z 0 . for i = 1 to t z 0 = f ( z 0 , z 0 ) if e i = 1 , then z = f ( z , z 0 ) else continue end for z = f ( 1 , z ) in constructing circuits for implementing either of these methods for modular exponentiation , it should be noted that f is a symmetric function so that ƒ ( a , b )= ƒ ( b , a ). if ƒ is instead viewed as an operator , this condition is referred to as commutivity . thus , circuits implementing ƒ can have their inputs switched with no change in operation . one also notes in the algorithm set forth immediately above that e 0 is the lowest order bit in the binary representation for the exponent e . as such , for the cryptographic purposes described herein , one notes that n is an odd number . thus , it &# 39 ; s lowest order bit position is always 1 . thus , for cryptographic purposes the step which tests to see if e 0 = 0 can be eliminated . as an example , a circuit which can implement either one of the algorithms for exponentiation is shown in fig2 . the core of this exponentiation circuit is provided by an engine which implements the ƒ ( a , b )= a b 2 − mk mod n function . thus , engine 600 may be implemented by means of any of the hardware components described above which performs this function . the output from multiplication modulo n engine 600 is provided to decoder 603 which operates under control of finite state machine ( fsm ) 607 to store this output either in z register 604 or in z 0 register 605 , or in both ( to provide the z = z 0 step in the algorithm of fig1 ), as needed . thus , decoder 603 does not always function in accordance within the standard operational definition of a “ decoder ” which would normally have only one set of output lines carrying information . if the circuit of fig2 is intended to implement either of the exponentiation algorithms herein , then the outputs of registers 604 and 605 ( z and z 0 ) are both provided as inputs to multiplexors 601 ( for input a ) and 602 ( for input b ). these multiplexors are also provided with constants 1 and c = 2 + 2mk mod n . it is noted , however , that the constant “ 1 ” could also have been provided instead as an input to multiplexor 601 . however , the constant c and the input a ( which is used for computing a e mod n ) need to be provided to different ones of multiplexors 601 and 602 for the purpose of calculating the value z 0 = ƒ ( a , c ). multiplexors 601 and 602 and decoder 603 all operate under control of controller 607 which is preferably implemented as a finite state machine which can have as few as 6 states which depend only on the contents of index counter 608 ( which counts from 0 to t and then resets back to 0 ) and on the i th selected bit e 1 from register 606 which contains the exponent e in binary form . for example , in implementing the algorithm illustrated in fig1 , when counter 608 is at 0 , controller 607 selects the a input for multiplexor 601 and the c input for multiplexor 602 . it is also noted that , for both algorithms , the initialization and repetition aspects both involve two steps . accordingly , fsm 607 also includes one - bit register 609 ( step state register ) which is indicative of this step state . having used multiplexors 601 and 602 to select a and c as inputs to engine 600 , fsm 607 also controls decoder ( or router , if you will ) 603 to store the output ƒ ( a , c )= a c 2 − mk mod n into z 0 register 605 . the design of fsm &# 39 ; s for such purposes is standard and is well known and is , for example , described in the text “ digital logic and computer design ” by m . morris mano , copyright 1979 by prentice - hall . in the use of the crt as described above it is seen that one requires the constant c defined as 2 + 2mk mod n . while the constant 2 2mk is generally easy to determine and construct , the inclusion of the need for this to be modulo n is a complicating factor . note here too that it is the case that mk ≧ n + 2 where n is the number of bits in n and that m is picked to be the smallest integer satisfying this relationship . thus 2 + 2mk is always going to be greater than n and hence the modulo n form is needed . however , this constant is readily calculable using the ƒ engine described above . one first calculates t = 2 mk + t for a small value of t . the ƒ engine is then used repeatedly as follows : f ⁡ ( t , t ) = 2 mk + t ⁢ 2 mk + t ⁢ 2 - mk ⁢ mod ⁢ ⁢ n , = 2 mk + 2 ⁢ t ⁢ mod ⁢ ⁢ n this process is repeated until the first time that the result is greater than n . in public key cryptographic systems someone who wants to receive information picks two ( large ) prime numbers n p and n q and publishes only their product n = n p n q . the potential receiver then generates ( or otherwise creates , often randomly ) a public key e which is also published . before publication , however , the receiver - to - be checks to make sure that e is relatively prime with the respect to the product ( n p − 1 ) ( n q − 1 ). this is easily done since the receiver knows both n p and n q . with n and e thus known to the public , anyone wishing to transmit a message a destined for the receiver can form the encrypted version c of the message by computing c = a e mod n . thus , encryption is an exponentiation operation modulo n . it is the “ modulo n ” aspect which makes this a nonstandard arithmetic problem . however , the systems provided herein are particularly capable of performing the a e mod n operation . at the receiving end the message is decrypted as a = c d mod n , where , as above , c is the received / encrypted message and where d is a private key known only to the receiver and which is calculated as d = e − 1 mod [( n p − 1 ) ( n q − 1 )]. this is something which can be computed by the receiver since the receiver ( and only the receiver ) knows the values n q and n p . ( since n = n p n q is a large number , typically with thousands of bits , even though n be known , its factors , the prime numbers n q and n p are very hard to determine . this fact lies at the heart of public key cryptography .) the receiver also computes , actually precomputes , several other values that are useful in efficient decryption . in particular , the receiver computes two values u , d p and d q as follows : these values render it possible to more efficiently construct the desired result which is c d mod n . this process is more particularly illustrated in fig2 . ( coded message c is not to be confused with the constant c = 2 + 2mk used above .) advantage is now taken of the fact that the receiver , knowing n p and n q is able to calculate u , d p and d q so that advantage maybe taken of the chinese remainder theorem . the coded message c is an integer between 0 and n = n p n q where gcd ( n p , n q )= 1 end where “ gcd ” stands for “ greatest common denominator .” if c p = c mod n p and c q = c mod n q then the crt implies that c may be computed as follows : c = c q +( n q (( c p − c q ) mod n p ) u ) mod n p , where u is as defined above . this result is now more particularly applied to the computation of c d mod n , one first considers ( c d ) p which is defined as c d mod n p . likewise , one also considers ( c d ) q which is similarly defined as c d mod n q . note that ( c mod n p ) d mod n p =( c mod n p ) d p where d p = d mod ( n p − 1 ). similarly , ( c mod n q ) d mod n q =( c mod n q ) d q where , similarly d q = d mod ( n q − 1 ). thus , given c , d p , d q , n p , n q and u the exponential c d mod n can be calculated in three steps : step 1 . c p = c mod n p ; c q = c mod n q . step 2 . ( c p ) d =( c p ) d p mod n p ; ( c q ) d =( c q ) d q mod n q . step 3 . c d mod n =( c q ) d +[ n q ((( c p ) d −( c q ) d ) mod n p ) u ] mod n p . step 2 above is readily carried out using the methods set forth in fig1 and 19 . step 3 is a straightforward calculation not involving exponentiation . furthermore , as indicated above it is possible to split the sequence of processing elements into two chains which together calculate ( c p ) d and ( c q ) d simultaneously . attention is now directed to a method for further simplifying the computation shown in step 1 immediately above . since the input to the process is a relatively large number , perhaps being represented by as many as 2 , 048 bits , the calculation can be time consuming . however , the modular reduction is based on numbers n p and n q which are often roughly only half that size . suppose then that , phrased more generally , one wishes to compute a p = a mod n p and likewise a q = a mod n q . without loss in generality one may assume that n p & gt ; n q . suppose further that n p and n q are the number of bits in the binary representations for n p and n q , respectively . suppose even further that one picks values m p and m q such that these are the smallest integers for which : where k is the word size in the circuits described above for modular multiplication . with these parameters one may now write a in either of the two forms : depending on whether one wishes to compute either a p or a q , both of which are employable in the application of the crt as described above . if a is of the order of 2 , 048 bits , then : n p + n q ≦ 2048 ; and in general : 0 ≦ a 0p ≦ 2 m p k ; 0 ≦ a 0q ≦ 2 m q k ; 0 ≦ a 1p & lt ; n p ; and 0 ≦ a 1q & lt ; n p . one further defines two constants c p = 2 + 2m p k mod n p and c q = 2 + 2m q k mod n q . these constants have substantially the same role as the constant c = 2 + 2mk mod n discussed above , but now these new constants are employed to facilitate computation on a smaller scale problem in accordance with the representation of a as having two parts ( a 1p and a 0p for the mod n p calculation and a 1q and a 0q for the mod n q computation .) as indicated above the present inventors have provided circuits for construction of an engine which implements the function ƒ ( a , b )= a b 2 − mk mod n . this engine / circuit is also fully capable of implementing different functions in dependence on the m and n parameters . accordingly , the functions ƒ p and ƒ q are defined as follows : ƒ p ( a , b )= a b 2 − m p k mod n p , ƒ q ( a , b )= a b 2 − m q k mod n q . consider first the use of ƒ p in the calculation of a p based on the use of the two part representation of a as a 1p 2m p k + a 0p : a = ƒ p ( a 0p , 1 )= a 0p 2 − m p k mod n p b = ƒ p ( a 1p 2 m p k , 1 )= a 1p mod n p g = a + b = a 1p + a 0p 2 − m p k mod n p f p ⁡ ( g , c p ) = g ⁢ ⁢ 2 - m p ⁢ k ⁢ 2 + 2 ⁢ m p ⁢ k ⁢ mod ⁢ ⁢ n p , = g2 m p ⁢ k ⁢ mod ⁢ ⁢ n p , = a 1 ⁢ p ⁢ 2 m p ⁢ k + a 0 ⁢ p ⁢ mod ⁢ ⁢ n p = a ⁢ ⁢ mod ⁢ ⁢ n p = a p in the same manner one uses the circuits herein to compute a q using the parameters m q and n q to produced ƒ q as defined above . the overall structure for a preferred embodiment of cryptographic engine 700 employing the circuit and operational principles set forth above is shown in fig2 . the main feature of cryptographic engine 700 is the inclusion of modulo n multiplier 600 as described above . it is noted that , as implemented herein as a sequence of independent processing elements ( pe &# 39 ; s ), multiplier engine 600 is dividable into two pieces by the operation of electrically controlling a processing element so as to cause it to operate as a “ pe 0 ” element . this is particularly useful during decryption operations since in this circumstance the receiver knows both n p and n q , whereas during encryption the sender knows only the product n = n p n q . for the calculation of a b mod n , register set 658 contains registers for holding the following values : a , b p , b q , n p , n q and u , where b p = b mod ( n p − 1 ) and b q = b mod ( n q − 1 ). register set 658 also preferably includes at least two utility registers for holding temporary and / or intermediate results . in particular two such utility registers are preferably employed to contain the values a 1q and a 0q as described above , with a 0p and a 1p being thus stored in the ah and al registers respectively . clearly , the roles of these two utility registers are interchangeable . register set 658 also includes an output register which contains output results from multiplier engine 600 . cryptographic engine 700 also includes modular reduction unit 653 ( also described herein as auxiliary computation circuit in fig2 ) which performs addition and subtraction operations and performs single shot modular reductions . the flow of signals across databus 670 between register set 658 to and from multiplier engine 600 and modular reduction unit 653 is carried out under control of finite state machine ( fsm ) command control unit 660 in accordance with the methods , algorithms , and protocols set forth above for carrying out any or all of the following : modular multiplication , constant c generation , exponentiation and the use of the chinese remainder theorem ( crt ) for calculating modular numbers and for efficient exponentiation . i / o control unit 665 , besides implementing the decoding and control function necessary to supply values such as a , b , n , b p , b q , n p , n q and u to the registers set 658 through databus 670 , provides two important functions in the case of modular exponentiation with crt : the first important function is that it dynamically calculates the value of m or m p and m q and it also calculates the lengths of the exponents b or b p and b q . each value of the m &# 39 ; s is a function of the length of a modulus ( position of the leading 1 ) and is a key parameter used throughout the operations . the length of an exponent is simply used to determine when to stop the exponentiation process . the traditional solution is the use of a length detector that monitor the value of each bit in this large registers . this approach has disadvantages in terms of requiring more silicon area and also in terms of electrical loading on the output of the registers . the approach used in the i / o control logic is much less wasteful and is based on the detection of the leading ‘ 1 ’ in the k bit word being written and the associated address . every time a non - zero k bit word is written , a small piece of logic is used to calculate the location of the most significant ‘ 1 ’ which is being written , based on the address of the word itself , and is compared with a value stored in a register that is the result of the loading of the previous k bit word . if the new value calculated is larger than the value stored in the register , the register is updated accordingly . the calculation of the m parameter follows a similar approach and thus saves the need for a lookup table and another large leading ‘ 1 ’ detector . the second important function is that in preparation for performing modular exponentiation with the crt , the values of a 1p , a 0p , a 1q , and a 0q , as described previously , are calculated and loaded into separate registers under control of i / o control unit 665 . commands which externally govern the operation of engine 700 are also supplied via i / o control unit 665 . attention is now directed to a checking system and method which takes the fullest advantage of the modular multiplication circuits described above . in general , there are several ways to provide checking for the results of the hardware operations carried out by the system of the present invention . however , most of the standard approaches to checking are negatively impacted by size , economies of chip real estate and / or by the fact that the arithmetic operations carried out are modulo n operations . for example , result checking based on a straight forward duplication of hardware is very expensive in terms of “ silicon real estate .” error checking for the various function blocks employed ( multipliers , adders , controls , etc .) is also very expensive and complicated . lastly , the use of residue arithmetic check sum methods is not directly applicable to checksums for the modular multiplication hardware that implements the z = ƒ ( a , b )= ab 2 − mk mod n function described above . for example , if z ′, a ′, and b ′ are the check sums of z , a , and b , respectively , then it is still unfortunately the case that z ′ is not necessarily equal to ƒ ( a ′, b ′). accordingly , driven by the inappropriateness of standard approaches to hardware operation checking , there is provided herein a method and system which is closely tied to the architecture described above and which is particularly tied to the fact that the systems herein perform modulo n multiplication using x and z phases of operation and employ a plurality of processing elements based on the notion of partitioning the operands involved into a plurality , m , of k bit words . for an easier understanding of the checking method and system herein , one starts with an understanding of the process described above : n = number of bits in the binary representation of n k = number of bits in a word ( i . e ., in each chunk processed by one of the processing elements . m = smallest integer for which mk ≧ n + 2 n 0 = least significant k bits of n r = 2 k s =(− 1 / n 0 ) mod r a = ∑ i = 0 m - 1 ⁢ ⁢ a i ⁢ r i y i + 1 = s x i , 0 mod r ( where x i , 0 = least significant k bits of x l ) based on the above algorithm , structure , and process , the following equations lie at the heart of the model employed herein for checking the operation of the modulo n multiplication circuits : a = ∑ i = 0 m - 1 ⁢ ⁢ a i ⁢ r i b = ∑ i = 0 m - 1 ⁢ ⁢ b i ⁢ r i n = ∑ i = 0 m - 1 ⁢ ⁢ n i ⁢ r i z = ∑ i = 0 m - 1 ⁢ ⁢ z i ⁢ r i f ⁡ ( a , b ) = ( a , b ) / r m + n ⁢ ∑ i = 0 m - 1 ⁢ y i / r m - i ⁢ z ⁢ ⁢ mod ⁡ ( r - 1 ) = ∑ i = 0 m - 1 ⁢ z i ⁢ ⁢ mod ⁡ ( r - 1 ) = ab + n ⁢ ∑ i = 0 m - 1 ⁢ y i ⁢ mod ⁡ ( r - 1 ) = [ ( ∑ i = 0 m - 1 ⁢ a i ⁢ mod ⁡ ( r - 1 ) ) ⁢ ( ∑ i = 0 m - 1 ⁢ b i ⁢ mod ⁡ ( r - 1 ) ) + ⁢ ( ∑ i = 0 m - 1 ⁢ n i ⁢ mod ⁡ ( r - 1 ) ) ⁢ ( ∑ i = 0 m - 1 ⁢ y i ⁢ mod ⁡ ( r - 1 ) ] ⁢ mod ⁡ ( r - 1 ) the hardware which calculates the function ƒ ( a , b ) is therefore checkable through the use of the following relationship ( referred to below as equation ( 1 )): ∑ i = 0 m - 1 ⁢ z i ⁢ mod ⁡ ( r - 1 ) = [ ( ∑ i = 0 m - 1 ⁢ a i ⁢ mod ⁡ ( r - 1 ) ) ⁢ ( ∑ i = 0 m - 1 ⁢ b i ⁢ mod ⁡ ( r - 1 ) ) + ( ∑ i = 0 m - 1 ⁢ n i ⁢ mod ⁡ ( r - 1 ) ) ⁢ ( ∑ i = 0 m - 1 ⁢ y i ⁢ mod ⁡ ( r - 1 ) ) ] ⁢ mod ⁡ ( r - 1 ) ( 1 ) the fortunate part of this checksum calculation is that it is computed on the fly . for example , the circuitry necessary for the calculation of ∑ i = 0 m - 1 ⁢ y i ⁢ mod ⁡ ( r - 1 ) is shown in fig2 . it is noted , however , that the circuit ( s ) shown in fig2 are provided for the specific case of the use of the chinese remainder theorem where n p and n q are known and the processing elements are split into two independent chains , one for calculating multiplication modulo n p and the other for calculating multiplication modulo n q . in the case of modulo n p calculations , accumulating register y ( reference numeral 652 . 3 a ; not to be confused with the y l variable used above to describe the algorithm ) is initially set to zero with its output being used as an input to adder 652 . 2 a along with the input y l , p from the corresponding portion of register for the processing element partition which generates they , values . the input from register 652 . 1 a is added to the current y p value to produce a running accumulation which is stored between cycles in register y ( reference numeral 652 . 3 a ). at the end of m cycles the contents of this register is the value y p ′ = ∑ i = 0 m - 1 ⁢ y i , p ⁢ mod ⁡ ( r - 1 ) . likewise , the corresponding circuit shown in the lower portion of fig2 operates in an identical fashion to compute y q ′ = ∑ i = 0 m - 1 ⁢ y i , q ⁢ mod ⁡ ( r - 1 ) . in the case of both the y ′ p and the y ′ q computations , adders 652 . 2 a and 652 . 2 b respectively are each k bit integer binary adders with carries out of the high order position being fed back as carry inputs to the low order positions . in this way addition modulo ( r − 1 ) is carried out . thus , the circuits shown in fig2 supply check sum values y ′ p and y ′ q to check sum predictor circuit 800 of fig2 . it is noted that circuits ( not shown ) very similar to those of fig2 are likewise provided for the generation of checksum values a ′ p and a ′ q from accumulated sums ( modulo ( r − 1 )) of the values a i , p and a i , q respectively for i = 0 , 1 , . . . , m − 1 . similarly , checksum values b ′ p and b ′ p are generated from similar circuits ( also not shown ) similar circuits also generate the values n ′ p and n ′ q from the n i , p and n i , q values . since these circuits are identical in structure and operation and differ only in the naming of the signal components , like the circuits mentioned just above they are also not shown herein . the addition operation indicated in equation ( 1 ) is carried out by adder 820 which performs addition modulo ( r − 1 ) and accordingly , like the other adders in the checksum system , includes a high order carry out signal output which is fed back as a low order carry input , as shown . multiplexors 824 , 825 , 826 , and 827 are operated under control of two signal lines . a first signal control line ( p / q ) controls multiplexors 824 and 826 to select between the two independent processor element chains for n p and n q processing . a second signal control line ( select add ) controls multiplexors 825 and 827 to effect the cumulative addition operation indicated by the summation from i = 0 to ( m − 1 ) in equation ( 1 ). in order to calculate the intermediate checksum values a ′ p b ′ p and a ′ q and b ′ q a final addition operation is performed which adds together the contents of the p 0 and p 1 registers ( reference numerals 821 and 822 , respectively ) via operation of the select add control line . adder 820 is also responsible for the final addition which generates ( ab )′ p and ( ab )′ q by adding together the previous checksum values , stored in registers 831 and 832 , with the cumulative checksums ( ny )′ p and ( ny )′ q . this results in the generation of the p checksum and q checksum values from registers 831 and 832 respectively . these signal lines are supplied to main checksum generation block 670 ( in fig2 ). in particular , the p checksum and q checksum signal lines are supplied to comparators 657 a and 657 b , respectively , as shown in fig2 . accordingly , attention is now focused on the structure and operation of fig2 . the main function of block 670 is the calculation of the left hand side of equation ( 1 ). as above , this circuit has two parts devoted to split calculations based on n p and n q operations as when the processor elements in fig7 are split by controlling a middle processing element so as to force it into operating in the pe 0 mode . each processing element chain ( the n p chain or the n q chain ) outputs results of the modular multiplication operation 2 k bits at a time . accordingly , the circuit for generating the checksum value z ′ for the z variable is implemented as two adders with k bits each . additionally , because of the splitting , there are actually a total of four adders shown in fig2 . for the n p chain , for example , adder 656 a , processes the high order bits output from the multiplication operation that produces each high order k bit output from the chain working on the modulo n p multiplication . after all of the 2 k bit portions have been added together , multiplexor 656 a 2 is operated to add together the sums in the high order register z ′ p , h and the low order register z ′ p , l . this resulting sum is compared with the p checksum value by comparator 657 a to produce an error indication error 2a , if there is no match . it is also noted that the adders in fig2 all perform addition modulo ( r − 1 ) and include a carry feedback out of the high order position into the low order position . the bottom circuit shown in fig2 is structured and operates in the same way as the upper circuits . however , as is clearly evident the bottom circuit is associated with and operates on signals generated during calculations modulo n q based on the splitting of the processor element chain as described . accordingly , the lower circuit in fig2 generates the z ′ q checksum signal from the modulo n q calculations , which resultant value is compared in comparator 657 b to generate error signal error 2b , if there is no match . thus , the output of block 670 is describable as : error 2a or error 2b . thus , at the end of each modular multiplication operation , an error signal is available which functions to provide an indication that all hardware elements have worked as designed to produce the intended result . additionally , fig2 also shows the inclusion of auxiliary computation circuit 653 . this circuit is used to perform auxiliary operations such as z = j + k , z = j − k and z = j mod n . checksum operations for these calculations are optional but preferable . the calculations carried out by auxiliary computation circuit 653 are relatively simple in comparison with the modular multiplication features . residue checking for these calculations are also relatively simple . for the addition operation z = j + k , the checking mechanism is to make sure that the value of z mod ( r − 1 ) is the same as the value of the modulo ( r − 1 ) sum of ( jmod r − 1 ) and ( k mod r − 1 ), where r is an even integer . similarly , to check the operation of z = j − k , one is to check if the value of z mod ( r − 1 ) is the same as the value of the modulo ( r − 1 ) difference of ( j mod r − 1 ) and ( k mod r − 1 ). as for the operation of the modular reduction z = j mod n that is implemented by a long division , z is the remainder of j divided by n . one has the expression j = qn + z , where q is the quotient . the error checking for this modular reduction operation can be carried out by comparing the value of j mod ( r − 1 ) and the modulo sum of ( q mod ( r − 1 ))( n mod ( r − 1 )) and ( z mod ( r − 1 )). while many of the concepts presented above have been couched in terms of what are seemingly purely mathematical algorithms , the applications involved are really directed to the encryption , transmission and decryption of messages in whatever form these messages may be represented , as long as they are in digital form , or its equivalent ( octal , binary coded decimal or hexadecimal ). in these methods for encryption , transmission and decryption , messages are represented by large integers expressed in binary form so that for purposes explaining the theory , operation and value of the methods and devices presented herein , the description is necessarily of a mathematical nature . nonetheless , the devices and methods describes herein provide practical methods for ensuring secure communications . as such the devices and methods described herein represent practical implementations of mathematical concepts . it is also noted that the operation of the circuits described herein are meant to occur over a repeated number of cycles . the description herein sets forth the ideal number of cycles generally required for proper operation in the most general situations . however , neither the specification nor claims should be interpreted as being limited to the most general cases . in particular , it is noted that suboptimal control methods can sometimes lead to operation of the circuits for more cycles than is absolutely necessary , either by accident or by design . the scope of the claims herein should not be so narrowly construed as to forego this inclusion . likewise , for certain input situations , the full number of cycles normally required for the most general cases is not required . accordingly , some of the claims herein recite the operation for at most t cycles . clearly , for its intended use in encryption and decryption , the circuits herein have been designed to handle the most general cases . the claims , however , should not be construed to be so narrow as to exclude either the simpler cases or the cases of deliberate operation over more than the necessary number of cycles . accordingly , from the above , it is seen that all of the objectives indicated are achieved by the circuits and processes described herein . in particular , it is seen that there is provided a circuit and process for carrying out multiplication of relatively large numbers modulo n using either multiplier and adder arrays or a plurality of nearly identical processing elements . it is also seen that these same circuits can be used not only to implement modular exponentiation but can also be employed as part of hardware circuits for implementing solutions to problems based on the chinese remainder theorem . it is even further noted that the objective of providing pipelined operations for a series of connected processing elements is achieved in a manner in which all of the processing elements are functioning at all times to produce desired final or intermediate results . and it is also seen that circuits are provided for carrying out functions which are ancillary to the processes described above and , in particular , circuits and processes for producing negative multiplicative inverses . while such inverses are providable in a data processing system via software or by means of prior ( and perhaps separate ) computation , the processes and circuits shown herein are capable of providing this function in a short period of time with relatively simple hardware which takes advantage of already existing circuit registers and other elements . from the above , it is clear that the circuits shown in applicants &# 39 ; figures fulfill all of the objects indicated . additionally , it is noted that the circuit is easy to construct and takes full advantage of the parallelism brought about by structuring one of the operands in the multiplication process as m blocks of k bits each . in particular , it is seen that the circuit shown herein carries out a two - phase operation , one of which computes x i and y i , with the second phase computing a value for z i which eventually , at the last step , becomes a desired result . in particular , it is seen that the circuit shown in applicants &# 39 ; figures provides a desired trade off between multipliers which have to be n bits by n bits in size and between serial circuits which operate with only one bit of a factor being considered at each step . while the invention has been described in detail herein in accordance with certain preferred embodiments thereof , many modifications and changes therein may be effected by those skilled in the art . accordingly , it is intended by the appended claims to cover all such modifications and changes as fall within the true spirit and scope of the invention .