fig1 provides hardware that obtains novel control of the c / r method for correcting erroneous data requested from main storage ( ms ) 11 by a requestor , which may be a cpu ( central processing unit ), an i / 0 processor that is controlling one or more i / 0 devices , or a service processor ( sp ). each request for data sends an address to ms for accessing a line of data in ms dram arrays comprising a memory in a computer system . the invention may be applied to any memory , but the preferred embodiment uses the main storage ( ms ) in a computer system . each request provides the ms address of a requested data line in ms and the requestor &# 39 ; s identifier ( rid ), which is provided to the memory controller . each data line in ms 11 contains one or more data units ( dus ), of which each data unit is a group of data bits over which an error correcting code ( ecc ) is generated to provide a total group of bits indicated by the notation du + ecc group . the ecc bits in a group are commingled among the du bits , and the ecc bits enable sec / ded for its group during its readout and transmission . in the preferred embodiment each data line is comprised of sixteen du + ecc groups . the bits in a du + ecc group are readout and transmitted in parallel on a memory bus in the preferred embodiment , but they may be serially transmitted on a bus for the current data line . also , the preferred embodiment presumes each du is a double word of 64 data bits having 8 ecc bits providing sec / ded . hence , the 64 + 8 = 72 bits are transferred on the bus in parallel . if a serial bus were used , each du + ecc group would be assembled / disassembled into its parallel bit form to and from memory . in the hardware of fig1 each of the 16 du + ecc groups in a requested data line is transferred from ms 11 through inverter circuits 12 to an ecc logic circuit 13 . during an original fetch , each group passes through inverter 12 in its true ( non - inverted ) form to ecc logic circuit 13 . circuit 13 error checks each du + ecc group and passes it to its requestor , whether the ecc logic found it error - free or not . if a du + ecc group has only one erroneous bit , it is error corrected before being sent to the requestor . status information is sent with the data to the requestor to inform the requestor of the group &# 39 ; s error - free or particular error condition . if the requestor receives error - free data ( whether or not ecc corrected ), the c / r function is bypassed ( not done for the request ). a particular status signal identifies any detected error condition to the requestor for the sent du + ecc group , so that the requestor can determine what it wants done with the request , including whether the requestor will request the c / r method to be performed on the erroneous du + ecc group . the flow diagram of fig8 shows the steps in an original fetch operation for a data line request , in which step 1 represents the current request . step 2 represents when the fetch request obtains priority from the memory controller , which involves putting the request into memory request register 71 in fig4 from which addresses are generated for each du + ecc group in ms . step 3 is the generation of status information which is put into registers 73 and 74 in fig6 and 7 , which are located in the memory controller for ms 11 . register 73 in fig6 represents the status information sent to the requestor and has the following fields set by ecc circuits 13 : a requestor identifier ( rid ) of the processor which made the request , the 72 bits of the fetched du + ecc group , and the following single bit indicator fields : no error , 1 bit corrected error , excessive error , and a special ue ( uncorrected error ) indicator . the special ue is a unique character stored in a memory location to represent that the location had bad unrecoverable data due to an error . register 74 in fig7 represents the status information sent to a service processor ( sp ) which is also set by ecc circuits 13 with the same information as is put into register 73 , except that register 74 also has a field set with the ecc syndrome bits for the group . by providing the syndrome bits to the sp , the sp has the option of using the syndrome bits and other status information to verify the ecc operation , if required . for an original fetch , the fields h - h , h - s and s - s in registers 73 and 74 are not generated ( remain off in reset state ) in the status registers . in step 4 of fig8 the status information in register 73 is communicated to the requestor indicated in the rid field , which is the fetch request currently represented in register 71 in fig4 . the requestor may be a cpu , an i / o processor , or a service processor . each requestor has hardware for receiving and sensing the received status information and determining if further action is needed for continuing the storage request with the c / r method if an excessive error is reported in the status register information . in the preferred embodiment , if the requestor receives an excessive error indication in the status register , the requestor automatically makes a re - fetch request to ms , which is a request for invoking the c / r method to attempt a correction of the excessive error in that du + ecc group . status register 74 in fig7 has its contents transmitted to a service processor ( sp ) such as exists in the processor control element ( pce ) of an ibm 3090 system . the sp controls the error recovery operations for the system when required for an ms error condition , such as if an unrecoverable failure occurs in the hardware handling the request . for example if an error condition occurs in handling of the du + ecc group , the sp may cause a special ue character to be written into the location containing the erroneous group to prevent the bad data from being used . if a requestor ( receiving the status register information for an original fetch request ) finds the no error field is on , no response is provided and the requestor uses the received group . but if the excessive error indication is received , a re - fetch request ( sometimes called a redo request ) is the response provided to the ms controller by the requestor &# 39 ; s hardware / microcode . the re - fetch request invokes the c / r hardware in fig1 in an attempt to correct the erroneous du ( currently being addressed by register 71 ). no interruption is caused to the normal operation of ms 11 or to the requesting processor during the process of issuing a re - fetch request invoking the c / r method . the successful use of the c / r process without an interruption to the requesting processor provides significant novelty for the subject invention over the prior art . previously , an interruption to the requesting processor always occurred on sensing an excessive error condition ( 2 bit error with sec / ded ecc ) during which the sp was invoked to initiate and control the execution of the c / r method . a significant amount of processor time was lost in that prior process compared to the process of the subject invention . the following table represents the four states of the c / r sequencer shown in fig4 and some of their consequences including the restoration actions needed for restoring an erroneous du + ecc group to its original state in ms if a failure should occur in the c / r hardware before its completion of the c / r process . table______________________________________ du + du + ecc ecc du + ecc form in form in restoration action data buf ms at for retry during at end end of ( assures du + eccstate state of state state in original state______________________________________first ms to true true nonefetch data buffirst data buf true inverted data bufferstore to ms to main store ( without comp . ) second ms to true inverted if statusfetch inverter buffer error is to data buf recoverable , redo this second fetch , then do second storesecond data buf true true redo secondstore to ms store______________________________________ thus , the first fetch state of the c / r method is provided in response to a re - fetch request being handled by the memory controller , providing a c / r request from the requestor to sequencer 72 in fig5 . normally , the four states of the c / r method proceed in sequence and complete with the second store state , as long as the hardware used by the c / r method operates correctly . if a malfunction signal occurs during any state of the c / r method ( indicated by the output state signal of sequencer 72 ), the malfunction signal causes a suppression of any further steps in the c / r process and invokes a restoration operation to assure the restoration of the du + ecc group being processed to its original state in ms . this is because the du + ecc group may be stored in a complemented ( inverted ) form in its original ms location at the end of the 1st store and 2nd fetch states of the c / r process . the particular data restoration action depends on which step of the c / r process existed when suspension occurred . then the restored erroneous du + ecc group enables it to be retried again to a potential corrected state . without restoration , a retry of the c / r method may not be able to correct the erroneous du + ecc group , and would prohibit confidence in the correction ability of the c / r method . fig9 and 10 show detailed flow diagrams of the c / r method used in the preferred embodiment , and represent the c / r steps in the table in more detailed substeps . step 10 in fig9 represents a re - fetch request selected by the ms controller for accessing in register 71 , wherein requests are prioritized and may be pipeline delayed before becoming the current ms request in address register 71 . hence , many machine cycles may intervene between the time a fetch or re - fetch request is issued and the time its is performed by ms 11 , due to conventional priority selection being done for ms operations . that is , other fetch and store requests to ms 11 may be serviced during this intervening period . re - fetch requests usually get higher priority than fetch requests in the memory controller . step 10 in fig9 represents a re - fetch request being put into register 71 for activating the input &# 34 ; c / r request from requestor &# 34 ; to the c / r sequencer 72 in fig5 is set it to its 1st fetch output state . step 11 in fig9 represents the fetching of each du + ecc group from ms . step 12 represents the generation by circuits 13 of a &# 34 ; status bit &# 34 ;, s , and a parity bit , p , for each du + ecc group . bit s is generated as a copy of the &# 34 ; excessive error bit &# 34 ; field in the received status register information for the current du + ecc group . the status bit has a zero state if no excessive error is indicated , but it has a one state if an excessive error is indicated . and circuits 13 generate a parity bit , p , for each status bit . the parity bit may be generated with either even or odd parity . odd parity is used in the preferred embodiment . therefore , when the status bit is 1 , the parity bit is zero , and visa versa , in the embodiment . in step 14 the status bit and its parity bit ( s , p ) generated for each du + ecc group are copied into s and p fields in an inpointer addressed entry in each of two separate status buffers ( status buffer1 and status buffer2 ). the corresponding entries in buffers 1 and 2 receive identical status bit and parity bit states . the inpointers for the data buffer 21 and for the status buffers 1 and 2 all address corresponding entries in their respective buffers and all are incremented at the same time during the first fetch operation . the c / r method is only invoked if a status bit , s , is set to a 1 state ( to indicate an excessive error ) for at least one du + ecc group of the 16 du + ecc groups in the current ms data line being read into the data buffer . generally , most of the du + ecc groups in the data buffer will not be erroneous and their respective s bits will be set to zero state to indicate no error in the corresponding du + ecc group stored in data buffer . a 1 value of the s bit for any du + ecc group controls both inversions for the bits in that group in the c / r hardware of fig1 . thus a 0 value for the status bit ( indicating no error ) does not cause any inversion ( complementing ) of the group as it moves though the hardware in fig1 . see step 26 . step 15 represents the storing of each du + ecc group in data buffer 21 at the inpointer location . in step 16 , the inpointer is incremented and the next du + ecc group is read from ms into the next entry in data buffer 21 , until all 16 groups are written into the data buffer for the data line currently being addressed by the memory address register 71 in fig4 . step 18 tests if any error has been detected in the c / r processing hardware , and if an error is detected , the c / r process is suppressed and the du + ecc group in ms is restored to its original state existing before the start of the suppressed c / r processing . if step 18 finds no operational error , the c / r processing continues with step 19 incrementing the c / r state sequencer to its 1st store output state . in fig1 outpointers 3 , 2 and 1 are provided for the data buffer 21 and the two status buffers 2 and 1 to control the selection of the corresponding entries being outputted . during the 1st store state , the outpointers are incremented at the same time by step 25 to all have the same address in order to point to their corresponding entries in their respective stacks . steps 21 , 22 and 23 perform check operations on these pointers and on the contents of their accessed entries to detect any hardware error that might have occurred . initially , the inpointers and the outpointers address the first du + ecc group in the data buffer ( and its respective status buffer entries ) of the current data line . as soon as plural du + ecc groups are stored in plural entries in the data buffer ( along with their corresponding status and parity bits in corresponding entries in the status buffers 1 and 2 ), the inpointers will increment ahead of the outpointers , and the outpointer addressed entries can be outputted from the respective buffers as long as the inpointer value is ahead of the outpointer value . the outpointer addressed du + ecc group is outputted from the outpointer data stack entry to an inverter 32 in fig1 . the corresponding outputted value of the s bit from either status buffer 1 or 2 ( they are the same as long as they are not in error ) is used to control all inversion operations in fig1 upon the du + ecc group being outputted under the outpointer control . the value of the outputted s bit is registered in circuits 43 for the duration of the current c / r processing . if the registered s bit has a 1 value , it activates an inversion control signal on lines 44 to inverter 32 and inverter 12 ( which causes an inversion of the du + ecc bits on the first store and on the second fetch ). if the s bit is 0 for the currently outputted du + ecc group , no inversion is done for the respective du + ecc . step 26 cause an inversion ( complementing ) of the current outpointer group in inverter 32 if a 1 state exists for corresponding s bit . then step 27 disables and passes the du + ecc group through ecc logic circuits 33 and stores the group into the same ms location from which it was fetched . inverter 32 does not invert the du + ecc group if the corresponding s bit is 0 . ecc logic 33 does not operate on the group during the 1st store operation . the outpointer incrementing will control the storing of all du + ecc groups into the data line in ms , in which only the group ( s ) having an excessive error ( s = 1 ) are in inverted form in ms upon the completion of the first storing step of the c / r method . step 28 checks if the stores occurred without any failure in the hardware of the c / r processing for the 1st store operations . if a failure is detected , step 29 is entered for activate the restoration required for a failure during the 1st store state of the c / r processing , indicated in the above table . if the 1st store is found to have completed successfully , step 31 is executed to increment the c / r sequencer 71 to its 2nd - fetch state to initiate the 2nd fetch of the data line now stored in ms with one or more of its du + ecc groups being in complemented form . in the second fetch , the inpointer 3 operates the same as it did in the 1st fetch operations to access each du + ecc group in the data line being addressed by register 71 . inpointers 1 and 2 are not used in the second fetch operation . thus , step 51 accesses each du + ecc group in the current data line being addressed by register 71 . steps 54 , 55 and 56 perform check operations for the c / r hardware , which are discussed later . in the second fetch , the outpointers 1 and 2 operate differently from the first fetch , and instead address the status buffer entries having the s bit corresponding to the current du + ecc group being read from ms into the data buffer at the inpointer 3 location . in the second fetch , the outpointers 1 and 2 step together with inpointer 3 , although the incrementing of inpointer 3 may occur a cycle or two later when there are corresponding buffering delays in the ecc circuits 13 . outpointer 3 , on the other hand , controls the 2nd store operation for du + ecc groups in the data buffer earlier obtained by the 2nd fetch operation , so that the 2nd store operation can overlap the 2nd fetch operation . the outpointers 1 and 2 address the status buffer entries 1 and 2 to access the s bit for each du + ecc group being read from ms , in order to control the operation of inverter 12 while the respective group is passing through inverter 12 to execute step 57 in fig1 . the outpointers 1 and 2 are initially set to address the first du + ecc group to be readout to control the required inversion state of inverter 12 . then outpointers 1 and 2 are incremented for the next du + ecc group to be readout , etc . each accessed s bit in the status buffers ( which was generated during the first fetch ) is used again without change during the second fetch to control the second inversion of each erroneous du + ecc group to obtain correction of all hard errors in the group during the second fetch operation . thus , the order of the s bits in each status buffer is the order of the respective du + ecc groups readout of the data line put in ms by the 1 st store operation . step 58 in fig1 increments outpointers 1 and 2 just prior to each next du + ecc group being fetched in ms , so that the corresponding s bit is effective to control inverter 12 operation for the group being read from ms . in fig1 , the paths from step 58 to step 61 , and from step 58 to step 71 are simultaneously taken . in the first path , the sec / ded ecc circuits 13 detect for error conditions remaining in the current du + ecc group after the second inversion in the c / r method has corrected all existing hard errors . step 61 determines for the current group : 1 ) if an h - h condition exists because the ecc did not correct any error , or 2 ) if an h - s condition exists because the ecc corrected 1 error , or 3 ) if an s - s uncorrectable condition exists because the ecc could not corrected the existing error condition . step 63 sets the corresponding 1 bit field in registers 73 and 74 , which are required for use by the system error reporting process in fig1 . then , step 68 sends the status register contents to the requestor and to the sp , which includes sending to the requestor all 16 data units comprising the fetched data line . the parallel path continues with step 71 storing the current du + ecc group in the data buffer at the current inpointer 3 location , and then pointer 3 is incremented by step 72 . next step 73 tests whether the second fetch has completed without an error condition is the c / r hardware processing , which is a different type of error condition from the error conditions detected in the du + ecc group by step 61 . if a c / r processing error occurred , step 88 is entered to restore the current du + ecc group in ms for conditions existing at the end of the 2nd fetch . if no c / r processing error occurred , step 74 increments the c / r sequencer 72 to its last state , 2nd store . each group was written into the data buffer in its true state , since erroneous group ( s ) now has been double inverted and non - erroneous du + ecc groups were never inverted . then step 81 write each group into ms from the outpointer 3 location in the data buffer without any inversion . outpointer 3 ( unlike outpointers 1 and 2 ) operates in the same manner as it did for the first store in the c / r method , in which outpointer 3 is initially reset to the first entry in the data buffer , and is incremented after each du + ecc group is outputted from the entry . however , no s bit control is used in the 2nd store operation , so that there is no need for any s bit alignment with the data buffer entries as there was during the 1st store operation . and therefore none of the other pointers operates in synchronously with outpointer 3 . step 82 increments outpointer 3 after each group is outputted . accordingly , during the 2nd store operation , the entire data line exists in its true and original state in the data buffer , and after the 2nd store operation is completed , all groups in the data line remain in their true and original state in ms , except that any group only having a single soft error can be corrected by scrubbing . hence , the groups in ms will still have all hard errors , and all soft errors when more than one soft error existed in a group . accordingly , the c / r error correction process is completed , if no error occurred in the c / r processing hardware . to achieve a high degree of confidence in the fault - tolerance of the c / r hardware , novel means are provided to detect a failure in the operation of the c / r hardware . it is possible for an alpha particle to cause a soft error in any bit in any buffer entry , and in any pointer register . also it is possible to have a hard error in these same bit positions . a number of error checks are made in this embodiment while it is in operation to increase the fault tolerance of the c / r method . the status buffers and the data buffer each have an inpointer and an outpointer for use during writing and reading respectively . there are times when all inpointers must step in unison ( during the first fetch ) and all outpointers must step in unison ( during the first store ). at other times , only the two inpointers of the status buffers must step in unison ( during the second fetch when the outpointer of the data buffer is not in use ), and the two outpointers of the status buffers must step in unison . when one of the pointers is out of step , an attempt is made to recover the originally stored state of the du + ecc group and a retry of the c / r operation is made . the values of inpointers 1 and 2 are always supposed to be the same , which is check by comparator 41 . likewise the values of outpointers 1 and 2 are always supposed to be the same , and they are checked by comparator 42 . if comparator 41 or 42 ever finds an unequal condition , an error is detected , and the comparator then outputs an interruption signal to the requesting processor and to the sp . also the current erroneous du + ecc group is restored as indicated in the above table so the c / r method can be retried on that group . if the inpointers are out of step during the first fetch , there is no damage to the data in main storage . therefore , it is simply a matter of sending an interruption signal to the requestor for it to request a retry of the c / r method from its beginning . if the outpointers are out of step during the first store , an interruption signal will be generated to abort the first store to preserve the data in main storage . then the c / r method is retried in its entirety . if the outpointers of the two status buffers are out of step during the second fetch , an interruption signal is generated to abort the second fetch . since the reading of the status buffers and ms are non - destructive reads , the content of ms and the status buffers are assumed to be un - changed . therefore , recovery is possible by a retry of the second fetch or second store c / r sequence . when these out - of - step interruptions frequently occur within a given time interval , the hardware involved in the c / r method is assumed to be unreliable and must be replaced immediately . on each access to the status buffers 24 and 27 by their inpointers and by their outpointers , the accessed status and parity bits ( s , p ) are suppose to be the same , and they are also compared for equality in a comparator in circuits 43 . if the compared s , p values are ever different , an error is indicated and an interruption signal is sent to the requesting processor and to the sp . also circuits 43 do a parity - check of the s , p content of each accessed status buffer entry for detecting any parity error condition . if the parity check is bad in one of the status buffer entries , the s bit in the other corresponding status buffer entry is used for the inversion control explained above if its parity is correct . the redundancy of the status buffer allows the c / r operation to proceed in case the accessed entry of one status buffer has a parity error and the accessed entry of the other status buffer has good parity . however , when parity errors are detected in the accessed entries of both status buffers , the c / r operation must be halted as soon as possible and an interrupt is sent to the sp for assistance . if this interrupt occurs during the first store , the store operation is aborted immediately to preserve the original data in ms . at this point , the content of the status buffers and data buffers can be reloaded by re - executing the c / r operation in its entirety . if this interrupt occurs during the second fetch , the c / r operation suffers an unrecoverable failure because the status bits cannot indicate , due to parity errors , whether the du + ecc in ms has been complemented or not . as a result , a special ue character will be stored in ms at the address involved with the c / r operation to indicate a bad , unrecoverable block of data . before storing the status bits , each status buffers checks the status bits for good parity . the status bits that have a bad parity will be written into the status buffer with a default value of ` 0 ` and its parity of ` 1 `. this action is taken to ensure that all entries in the status buffers have good parity at the end of the first fetch . the default s bit does not cause any inversion and prevents the c / r method from operating on that group . in more detail during the first fetch , the outpointers 1 , 2 and 3 are compared to ensure that the outpointers always step in unison . any discrepancy among the outpointers will cause an error signal to be generated noting failure of operation . however during the second fetch , only the outpointers 1 and 2 of the two status buffers are compared since they do not step in unison with outpointer 3 . this is done in fig9 by steps 21 , 22 and 23 , and in fig1 by steps 54 , 55 and 56 . the completed results of the c / r method are passed to the requestor as corrected data or as uncorrected data ( such as the detection of two soft errors , or of a special ue ). the reporting process in fig1 greatly reduces the amount and frequency of reporting excessive errors to operating system software ( os ), and eliminates all interruptions for a hard error in a memory unit , e . g . a 4 kb page , that was previously reported . the reporting process in fig1 is invoked when the requestor receives status information ( shown in fig6 ) indicating an excessive error exists in the requested data line . this embodiment provides a novel table called an ltr ( logical track record ), which is located in a storage area only accessible to microcode . the ltr includes a set of reporting bits , one for each ms data unit ( e . g . 4kb page ). microcode in the requesting processor accesses the ltr to determine if reporting is needed for the currently detected excessive error condition provided by status information after the second fetch in the c / r method . three different monitoring processes are represented in fig1 , and their selection is dependent on which type of excessive error is being reported , which can be any one of the s - s , h - h , h - s and special ue cases , which represent different cases of hard and soft error detection by the c / r method . the h - h and h - s cases each indicate the addressed page is stored in bad ms hardware . then a bit in the ltr is accessed using the page address of the data line having the currently detected excessive error . if the accessed ltr bit is set on , the yes path 91 is taken which indicates an excessive error was previously reported for that page , and that no communication with os is needed for the currently detected excessive error , so that no processor interruption is generated . but if no error has been reported for this page , then the no path is taken which sets the ltr bit and causes an mc interruption that sets bit 17 in the machine check interrupt code ( mcic ) to communicate to os the first excessive hard error in the page . the s - s case does not indicate any bad hardware in the addressed page , but that soft errors were detected in it . soft errors indicate bad data ( which may be in good hardware ). an excessive soft error must be reported each time it occurs , which is done by causing a machine check interruption that sets bit 16 and resets bit 32 in the mcic to communicate the soft error to os . if the ltr bit is set on in the s - s path and later a hard error is detected in the same page causing an entry into the h - h or h - s path in fig1 , the ltr bit for that page will have been set on so that path 91 is taken which avoids any interruption to the requesting processor due to the c / r processing . thus , when the process on path 91 in fig1 is taken , it eliminates the two clock - stopping interruptions ( to the processor and to the memory ) which occurred in the prior art operation of the c / r method . the first interruption occurred on the invocation of the c / r method , and the second interruption occurred on the determination of the type of excessive error being detected . this invention eliminates the first type of interruption and greatly reduces the second type of interruption . the special ue ( uncorrectable error character ) indicates that bad data was put into its location , which was stored as a special ue data pattern . the special ue ( when fetched ) causes a machine check interruption which sets bits 16 and 32 in the mcic to communicate the special ue to os . although the preferred embodiment is disclosed in connection with the main storage , it is understood the present invention may be used with other storages such as expanded storage or key storage and by other requestors such as vector processors . where we have illustrated and described the preferred embodiment of our invention , it is to be understood that we do not limit ourselves to the precise construction herein disclosed , and the right is reserved to all changes and modifications coming within the scope of the invention as defined in the appended claim .