a storage device and an alternate processing method for defective sectors of a storage device according to first and second preferred embodiments of the present invention will hereinafter be described in detail with reference to the accompanying drawings . fig2 is a plane - view showing a damascene interconnection structure according to a first preferred embodiment of a present invention . fig3 is a cross - sectional view showing damascene interconnection structure according to the first preferred embodiment of the present invention . as shown in fig2 and fig3 , a first damascene interconnection structure is preferably made up of a first insulating layer , as a first sio 2 12 , having a first through hole , and a first interconnection 18 that is buried in the first through hole . the first interconnection 18 is preferably made up of a first conductive layer such as a first tin film 16 a , a first barrier layer such as a first ti film 17 a , and a first main interconnection 19 . the first tin film 16 a is formed on the first sio 2 12 in the first through hole . the first ti film 17 a is formed on the first tin film 16 a . the first main interconnection is formed on the ti film 17 a so as to bury the first through hole . the first through hole has a first extending direction and a second extending direction which is longer than the first extending direction , and is formed so that the second extending direction corresponds to the flow of electrons in the first interconnection 18 which is formed in the first through hole . a second damascene interconnection structure is preferably made up of a second insulating layer , as a second sio 2 22 , having a second through hole , and a second interconnection 28 which is buried in the second through hole . the second interconnection 28 is preferably made up of a second conductive layer such as a second tin film 26 , a second barrier layer such as a second ti film 27 , and a second main interconnection 29 . the second tin film 26 is formed on the second sio 2 22 in the second through hole . the second ti film 27 is formed on the second tin film 26 . the second main interconnection 29 is formed on the second ti film 27 so as to bury the second through hole . the second interconnection 28 is connected to one of the first tin film 16 and the first ti film 17 of the first interconnection 18 . the second interconnection 28 is connected to one of the second tin film 16 a and the second ti film 17 a . the second interconnection 28 has a protrusion portion where the second interconnection 28 is connected to the first interconnection 18 . the protrusion portion of the second interconnection 28 is connected to the first interconnection 18 via the first through hole . in the structure mentioned above , when a voltage so as to become a high voltage is applied to the first interconnection 18 and a voltage so as to become a low voltage is applied to the second interconnection 28 , electrons flow from the second interconnection 28 to the first interconnection 18 . the cu atoms in the first main interconnection 19 of the first interconnection 18 move to opposite direction of electron flow because of electromigration . as a result , voids are formed in the first main interconnection 19 of the first interconnection 18 . however , since the second interconnection is connected to the first ti 17 a , the first ti 17 a can maintain electrical connection between the first and second interconnections . fig4 a – 4f are cross - sectional views showing a method for forming damascene interconnections structure according to the first preferred embodiment of the present invention . as shown in fig4 a , a first sio2 film 12 insulating film , a thickness of 1 μm , is formed on a semiconductor substrate 10 . first interconnections recesses 14 , a depth of 500 nm are formed in regions which first interconnections are formed , using photolithography technique and plasma etching with a mixed gas of c2f8 and o2 . as shown in fig4 b , tin films 16 , 16 a , a thickness of 30 nm are selectively formed on the first sio 2 film 12 in the first interconnection recesses 14 . ti films 17 , 17 a , a thickness of 5 nm , are formed on the tin films 16 , 16 a . cvd ( chemical vapor deposition ) method and cmp ( chemical mechanical polishing ) method are used for forming the tin films 16 , 16 a and the ti films 17 , 17 a . then , cu is buried in the first interconnection recesses 14 and then is polished until the first sio 2 film 12 is exposed , using the cmp method . as a result , a first main interconnection 19 is formed in the first interconnection recesses 14 . therefore , a first interconnection 18 which is made up of the tin films 16 , 16 a , the ti films 17 , 17 a , and the first main interconnection 19 , are formed in the first interconnections recesses 14 . as shown in fig4 c , a second sio 2 film as a second insulating film , a thickness of 1 μm , is formed on the entire surface . a first through hole 50 is formed so as to expose the first sio 2 film 12 a surface , a portion of the tin films 16 a , and a portion of the ti films 17 a in the second sio 2 film . a portion of the first sio 2 film 12 a is removed . as a result , a portion of the tin films 16 a sidewalls is exposed . here , an etching depth is about the half thickness of the first main interconnection 19 . as shown in fig4 d , a second interconnection recess 24 , a thickness of 500 nm , is formed in the second sio2 film 22 using plasma etching with c2f8 gas and o2 gas . as shown in fig4 e , a second tin film 26 and a second ti film 27 are successively formed on the second sio2 film in the second interconnection recess 24 using the same manner of the forming steps for the first interconnection 18 . as shown in fig4 f , cu is buried in the second interconnection recess 24 using sputtering method or cvd method . after then , the cu is polished until the second sio 2 film 22 surface is exposed . a second interconnection 28 which is made up of the cu as a second main interconnection , the second tin film 26 , and the second ti film 27 , are formed in the second interconnection recess 24 . thus , the second interconnection 28 is connected to the first tin film 16 a and the first ti film 17 a . fig5 a – 5f are cross - sectional views showing a method for forming damascene interconnection structure according to the second preferred embodiment of the present invention . as shown in fig5 a , a first insulating film 12 is preferably made up of a sio2 film 34 , a sin film 32 , and a sio2 film 30 . the sio2 film 34 , thickness of 500 nm , is formed on a semiconductor substrate 10 . the sin film 32 as etching stop layer , thickness of 50 nm , is formed on the sio2 film 34 . the sio2 film 30 , thickness of 500 nm , is formed on the sin film 32 . then , the sio2 film 30 is etched using photolithography technique and plasma etching with c2f8 gas and o2 gas . in this time , sin film 32 serves as the etching stop layer again st the sio2 film 30 . as a result , the sio2 film patterns 12 a , 30 and a first interconnection recess 14 are formed , respectively . as shown in fig5 b , tin films 16 , 16 a , ti films 17 , 17 a , and first main interconnections 19 are respectively formed in the first interconnection recess 14 using the same manner for forming steps of the first preferred embodiment . here , a first interconnection 18 is made up of the tin films 16 , 16 a , the ti films 17 , 17 a , and the first main interconnections 19 . as shown in fig5 c , a second insulating film 22 is preferably made up of a sio2 film 44 , a sin film 42 , and a sio2 film 40 . the sio2 film 44 , thickness of 500 nm , is formed on the entire surface . the sin film 42 as etching stop layer , thickness of 50 nm , is formed on the sio2 film 44 . the sio2 film 40 , thickness of 500 nm , is formed on the sin film 42 . the sio 2 film 40 is etched using photolithography technique and plasma etching with c2f8 gas and o2 gas until the sin film 42 is exposed . then , the sin film 42 is etched using plasma etching with sf6 gas and o2 gas . then , the si 0 2 films 12 , 44 are etched using photolithography technique and plasma etching with c2f8 gas and o2 gas until the sin film 32 is exposed . as a result , a through hole 50 is formed , and a sidewall of the tin film 16 a , edge of the ti films 17 a , and a part of the first main interconnections 19 are exposed in the through hole 50 . as shown in fig5 d , a second interconnection recess 24 which is wider than the through hole 50 , is formed by etching the sio 2 film 40 using photolithography technique and plasma etching with c2f8 gas and o2 gas . as shown in fig5 e , a second tin film 26 and a second ti film 27 are successively formed in the second interconnection recess 24 and the through hole 50 using the same manner of the forming steps for the first interconnection 18 . here , before forming the second tin film 26 and the second ti film 27 , another ti film may be formed in the second interconnection recess 24 and the through hole 50 . the first main interconnections 19 are subjected to nh3 used for forming the second tin film 26 . as a result , the first main interconnections 19 nitrides , and it is difficult to electrically connect the first interconnection 18 and the second interconnection 28 . as shown in fig5 f , cu is buried in the second interconnection recess 24 using sputtering method or cvd method . then , the cu is polished until the second sio 2 film 22 surface is exposed . a second interconnection 28 which is made up of the cu as a second main interconnection , the second tin film 26 , and the second ti film 27 , are formed in the second interconnection recess 24 . thus , the second interconnection 28 is connected to the first tin film 16 a and the first ti film 17 a . fig6 is a plan - view showing a damascene interconnection structure according to a third preferred embodiment of the invention . fig7 is a cross - sectional view showing a damascene interconnection structure according to a third preferred embodiment of the invention . as shown in fig6 and fig7 , a first interconnection 38 is preferably made up of a tin film 16 as a barrier layer , a ti film 17 as a conductive layer , and a first main interconnection 19 comprising cu . the first interconnection 38 is formed in a first sio 2 film 12 . a second interconnection 48 is preferably made up of a tin film 26 as a barrier layer , a ti film 27 as a conductive layer , and a first main interconnection 29 comprising cu . the second interconnection 48 is formed so as to cover an upper surface of and a sidewall of the first interconnection 38 . since a connecting area is wider than the conventional art , a contact resistance is low and a current flow is easy . therefore , it can avoid the electromigration . in the structure mentioned above , when a voltage so as to become a high voltage is applied to the first interconnection 38 and a voltage so as to become a low voltage is applied to the second interconnection 48 , electrons flow from the second interconnection 48 to the first interconnection 38 . the cu atoms in the first main interconnection 19 of the first interconnection 38 move in opposite direction of electron flow because of electromigration . as a result , voids are formed in the first main interconnection 19 of the first interconnection 38 . however , since the second interconnection 48 is connected to the first ti 17 a , the first ti 17 a can maintain electrical connection between the first and second interconnections . while the present invention has been described with reference to the illustrative embodiments , this description is not intended to be construed in a limiting sense . various modifications of the illustrative embodiments , as well as other embodiments of the invention , will be apparent to those skilled in the art on reference to this description . it is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention .