please refer to fig1 . fig1 is a diagram of a programming system 100 according to an embodiment of the present invention . the programming system 100 is used to perform code programming for a plurality of controller chips 160 , 170 . as shown in fig1 , the programming system 100 comprises a main printed circuit board ( pcb ) 110 , having a micro - controller unit ( mcu ) 130 , and a plurality of sub - pcbs 140 and 150 mounted on the main pcb 110 . in this embodiment the two sub - pcbs are pcbs that have at least a controller mounted on them and are installed into the display device . sub - pcbs 140 and 150 comprise controller chips 160 and 170 respectively , which are integrated circuits ( ics ) in this embodiment . the sub - pcbs 140 and 150 have interfaces 180 and 190 respectively that are connected to the controller chips 160 and 170 . please note that in this diagram , only one display controller chip is illustrated as being mounted on each sub - pcb ; however , this number is not a limitation of the present invention , and more than one display controller chip can be mounted on a single sub - pcb . the mcu 130 is utilized for controlling validation and program operations , and storing program codes into the controller chips 160 , 170 . the main pcb 110 further comprises an interface 120 for receiving program code data and data request instructions . in addition , the main pcb 110 is further capable of programming at least one external display controller chip ( not shown ) through the interface 120 . in an embodiment , the interface 120 can be implemented by a vga or a dvi interface . these implementations are not limitations of the present invention . in this embodiment , the combination of the mcu 130 , main pcb 110 and interfaces 120 , 180 , 190 serve as a programming apparatus . the sub - pcbs 140 , 150 having controller chips 160 and 170 mounted thereon act as programmable devices that are to be installed into display devices after the code programming is completed . in other words , once the controller chips 160 , 170 have been programmed , the entire sub - pcbs 140 , 150 can be removed from the main pcb 110 and placed in the display device , so the connecting pins of the controller chips 160 , 170 are prevented from being damaged . similarly , when the controller chips 160 , 170 require re - programming , the sub - pcbs 140 , 150 can be removed and placed back on the main pcb 110 for code programming , so there is no need for the chip to be removed individually and no damage will be applied to connecting pins of the chip . in short , the use of the sub - pcbs 140 , 150 prevents pin damage due to constant wear and tear . please refer to fig2 . fig2 is a block diagram of the display controller chip 160 shown in fig1 according to an embodiment of the present invention . only the display controller chip 160 is detailed in fig2 for brevity . the display controller chip 160 comprises an mcu 210 for executing normal operation of the display controller chip 160 . when data request instructions are received through an interface 230 ( in this embodiment the interface is realized by a dvi / vga interface ), an auxiliary controller 220 disables the mcu 210 during the code programming process . for example , the auxiliary controller 220 disables the mcu 210 , and program codes , such as firmware data , are received from the dvi / vga interface 230 and then sent to the write control circuit 260 . the present invention improves over the related art , however , by first sending requested data to a write buffer 270 , and then sending it to the flash memory 280 . this utilization of the write buffer 270 enables both the mcu 210 and the flash memory 280 to operate at maximum speed , as the write buffer 270 has a faster operating speed than the flash memory 280 , so data ( program codes ) can be written to the display controller chip 160 faster than if no write buffer were present . the evaluation circuit 240 is used to evaluate the data stored into the flash memory 280 to check validity of the programmed data . the read control circuit 250 controls the data reading of the flash memory 280 . when the display controller chip 160 is a display controller , the display controller chip 160 further comprises an image processing unit ( not shown in fig2 ), such as a scaler , or a de - interlacing module . please refer to fig3 . fig3 is a flowchart of a code programming process of the display controller chip 160 shown in fig2 . the steps are as follows : step 300 : receive an instruction through the dvi / vga interface 230 . step 302 : disable the normal operation of the internal mcu 210 . step 304 : assign a write address , and receive related data through the dvi / vga interface 230 . in one embodiment , the write control circuit 260 assigns a write address for programming the flash memory 280 and receives data ( program codes ) from the dvi / vga interface 230 . in another embodiment , the program codes to be programmed into the flash memory 280 are provided by the external programming apparatus and transmitted to the display controller chip 160 through the interfaces 180 and 230 . step 306 : buffer the received data in the write buffer 270 . step 308 : send data to the flash memory 280 once the write buffer 270 has reached capacity . step 310 : has all data requested been sent to the flash memory 280 ? if yes , go to step 312 ; otherwise , go to step 304 . step 312 : enable the normal operation of the internal mcu 210 . in a preferred embodiment , the utilization of the write buffer 270 enables the write process to continue without waiting for a write to go to the flash memory 280 . in other words , the implementation of the write buffer 270 offers a sequential data writing scheme to improve the code programming performance . moreover , it should be noted that the aforementioned data buffering scheme is only meant to be an example , and other data buffering schemes could be implemented in other embodiments of the present invention . the invention further provides an evaluation process , integrated in the code programming process , for determining whether data written to the display controller chip is correct . please refer to fig4 . fig4 is a flowchart of a code programming process of the controller 160 shown in fig2 according to the present invention . the steps are as follows : step 400 : receive an instruction through the dvi / vga interface 230 . step 402 : disable the normal operation of the internal mcu 210 . step 404 : write data to the flash memory 280 . step 406 : auto - read data back from the flash memory 280 once all data has been written to the flash memory 280 . step 407 : perform a crc check on each byte of data . step 408 : is an internal value stored in the mcu 130 equal to a value obtained by the crc operation ? if yes , go to step 410 ; otherwise , go to step 412 . step 410 : evaluation is successful . go to step 414 . step 414 : enable the normal operation of the internal mcu 210 . for code programming , the mcu 130 on the main pcb 110 will disable the operation of the mcu 210 in the display controller chip 160 through the auxiliary controller 220 via issuing an instruction to the dvi / vga interface 230 ( steps 400 and 402 ). then , the write control circuit 260 inside the display controller chip 160 writes received data ( program codes ) to the flash memory 280 ( step 404 ). in this embodiment , the method assigns a predetermined amount of data to be evaluated , by assigning a start and end address in the flash memory 280 . for example , the start address and the end address in the flash memory 280 define a data length corresponding to the whole program codes needed to be programmed into the flash memory 280 . therefore , once it is determined all data ( all program codes ) have been written to the flash memory 280 , the programmed data will be automatically read back to the evaluation circuit 240 , where a crc check will be performed on each byte of programmed data ( step 407 ). through evaluating the programmed data , the evaluation circuit 240 computes a crc value . then , the evaluation circuit 240 compares the computed crc value with a value stored in the mcu 130 mounted on the main pcb 110 ; if the computed crc value is determined to be correct , the mcu 130 will re - activate the mcu 210 of the display controller chip 160 by instructing the auxiliary controller 220 ( steps 408 , 410 and 414 ). if the computed crc value is not correct , however , the display controller chip 160 will be programmed again or deemed to be a bad chip . in a preferred embodiment , step 404 adopts the aforementioned data writing scheme shown in fig3 to optimize code programming efficiency . that is , the write buffer 270 is utilized to buffer the received data ( program codes ) when the write control circuit 260 writes the received data ( program codes ) into the flash memory 280 . however , the evaluation process of the present invention is not limited to be combined with the data writing scheme shown in fig3 . for other embodiments not using the data writing scheme shown in fig3 , the same objective of obtaining faster data evaluation speed is still achieved by performing the crc check only after all data to be evaluated has been written to the non - volatile memory . the mounting of the controller chips on sub - pcbs prevents damage occurring to the connecting pins through removal and wear . the write buffer in the controller chips allows write information to be buffered before being passed to the non - volatile memory ( e . g . flash memory ), therefore enabling both the mcu and the non - volatile memory to operate at maximum speed for code programming . the evaluation process allows faster evaluation of data by performing the crc check only after all data to be evaluated has been written to the non - volatile memory . those skilled in the art will readily observe that numerous modifications and alterations of the device and method may be made while retaining the teachings of the invention . accordingly , the above disclosure should be construed as limited only by the metes and bounds of the appended claims .