the present invention originates from the following facts : many cases must be considered in determining the clock cycle ; most of the cases are away from the worst case by considerable distance , especially in the low - voltage environment ; while few worst cases appear , one or more cycles are spent to complete calculation lest all the calculations be decelerated by few worst cases . the device of the present invention is similar to the non - synchronous circuit in operation but similar to the synchronous circuit in verifying the design . the device of the present invention can be designed with the standard eda tool and the standard cell - based design flow . the present invention can promote the overall performance of the circuit . the variable - latency datapath of the present invention effectively compresses the clock cycle of the circuit to be within the critical path delay of the worst case and thus promotes the overall performance of the circuit . refer to fig7 for latency distributions of a 17 × 17 - bit multiplier in a conventional technology . in fig7 , the critical path delay is 42 ns , which is almost unlikely to occur in practice . therefore , the clock cycle is set to be 25 ns , and two clock cycles ( 50 ns ) are spent in undertaking few multiplication calculations needing a calculation time of over 25 ns . if the proportion of the abovementioned few multiplication calculations consuming 2 clock cycles is 5 %, the average time of completing a multiplication calculation is only 26 . 25 ns . thus , the performance is 1 . 6 times enhanced . if sta ( static timing analysis ) is used to analyze latency , overproof design is required to deal with dynamic variations of the fabrication process , voltage and temperature . thus , the present invention is proved to have higher efficiency than the conventional design . refer to fig8 a diagram schematically showing the circuit of a speculative lookahead processing device according to one embodiment of the present invention . the device of the present invention comprises n pieces of datapath units 18 . each datapath unit 18 receives and calculates an input signal x to generate a correct value and a speculation value . n is a natural number greater than or equal to 2 . the output terminal of each datapath unit 18 is connected with at least one first multiplexer 20 and a second multiplexer 24 . in the embodiment shown in fig8 , the device of the present invention has a plurality of datapath units 18 , a plurality of speculation values and a plurality of first multiplexers 20 . let n be a natural number greater than or equal to 3 . the device of the present invention has ( n − 1 ) pieces of first multiplexers 20 and generates ( n − 1 ) pieces of speculation values . according to the input signal x , the datapath unit 18 generates a correct value y n and transmits y n to the second multiplexer 24 . the second multiplexer 24 outputs the correct value at the nth cycle of the datapath unit 18 . the speculation values are symbolized by y ( n − 1 ) , y ( n − 2 ) , . . . , y ( 1 ) , which respectively represent the speculation values output by the datapath units 18 at the ends of the ( n − 1 ) th cycle , the ( n − 2 ) th cycle , . . . , the first cycle . the first multiplexer 20 receives the abovementioned speculation values y ( n − 1 ) , y ( n − 2 ) , . . . , y ( 1 ) , and sequentially outputs the abovementioned speculation values y ( 1 ) , . . . , y ( n − 2 ) , y ( n − 1 ) during the first m cycles , wherein m is a natural number smaller than n . a timing controller 28 is connected with the second multiplexer 24 and the first multiplexers 20 and controls the timing when the second multiplexer 24 outputs the correction value y n and the timing when the first multiplexers 20 output y ( 1 ) , . . . , y ( n − 2 ) , y ( n − 1 ) . each datapath unit 18 is connected with a demultiplexer 30 . the demultiplexer 30 is connected with the timing controller 28 and receives a clock signal clk from the timing controller 28 . the timing controller 28 uses the clock signal clk and cooperates with all the demultiplexers 30 to control all the datapath units 18 to receive the input signal x 18 in a round - robin way . in other words , the datapath units 18 receive the input signal x in sequence from top to bottom . a comparator 26 is connected with the second multiplexer 24 and the datapath units 18 , receiving the stored speculation values y ( 1 ) , . . . , y ( n − 2 ) , y ( n − 1 ) and the correct value y n and comparing the correct value with each speculation value . while the speculation value is identical to the correct value , the comparator 26 drives the datapath unit 18 to continue to execute the instruction corresponding to the speculation value . while the speculation value is different from the correct value , the comparator 26 drives the datapath unit 10 to stall the pipeline for a period of time , such as a period of one cycle , to allow the second multiplexer 24 to output the correct value . below is described the process of a speculative lookahead processing method of the present invention . firstly , the timing controller 28 uses the clock signal clk and cooperates with all the demultiplexers 30 to control all the datapath units 18 to receive the input signal x 18 in the round - robin way ; the datapath units 18 calculates the input signal x , generating ( n − 1 ) pieces of speculation values and storing these speculation values , wherein n is a natural number equal to or greater than 2 . next , the datapath units 18 output the abovementioned speculation values y ( 1 ) , . . . , y ( n − 2 ) , y ( n − 1 ) in sequence before executing the nth cycle ; the timing controller 28 controls the first multiplexers 20 to receive the speculation values y ( 1 ) , . . . , y ( n − 2 ) , y ( n − 1 ) in sequence and output the abovementioned speculation values y ( 1 ) , . . . , y ( n − 2 ) , y ( n − 1 ) in sequence during the first m cycles . while the datapath unit 18 is executing the nth cycle , the timer controller 28 controls the second multiplexer 24 to output the correct value y n generated by the datapath unit 18 according to the input signal x . then , the comparator 26 receives the correct value y n and the speculation values y ( 1 ) , . . . , y ( n − 2 ) , y ( n − 1 ) and compares the correct value with each speculation value ; if the speculation value is identical to the correct value , the comparator 26 drives the datapath unit 18 to continue to execute the instruction corresponding to the speculation value ; if the speculation value is different from the correct value , the comparator 26 drives the datapath unit 18 to stall the pipeline for a period of time , such as a period of one cycle , to allow the second multiplexer 24 to output the correct value . the present invention is characterized in synchronously calculating the speculation values and the correct value ; using multiplexers to undertake selection ; and promoting the performance and efficiency of the system via constraining the hold time without using extra transistors . refer to fig9 ( a ) and fig9 ( b ) respectively showing the circuit and timing diagram of an accumulator according to one embodiment of the present invention , wherein an adder 31 inside the accumulator takes a cycle to undertake addition , and a register 32 receives the output of the adder 31 . an external input enters the adder 31 via an input terminal a , and the output of the register 32 enters the adder 31 via an input terminal b at the same time . as shown in fig9 ( a ) and fig9 ( b ), the input terminal a respectively receives external inputs x0 , x1 and x2 during different cycles , and the register 32 outputs ( y − 1 ) during the first cycle . thus , the adder 31 adds x0 to ( y − 1 ) and gets y0 . y0 is stored in the register 32 . in the second cycle , the input terminal a receives the external input x1 , and the input terminal b receives the output of the register 32 , i . e . the calculation result of the preceding cycle y0 . the adder 31 adds x1 to y0 to get y1 and stores y1 to the register 32 . in the succeeding cycle , the adder 31 will add x2 to y1 to get a new value . refer to fig1 ( a ) and fig1 ( b ) respectively diagrams schematically showing the applications of a speculative lookahead processing device to the first cycle and the second cycle of an accumulator according to one embodiment of the present invention . the timing diagrams corresponding to fig1 ( a ) and fig1 ( b ) are shown in fig1 - 14 . in each of fig1 ( a ) and fig1 ( b ), there are two datapaths , which are accumulators . the datapath outputs the correct value at the second cycle and outputs the speculation value at the first cycle . both the correct value and the speculation value are received by the registers . the external input is transmitted to the input terminal a and the input terminal a ′ in a round - robin way . the datapaths also undertake calculations in a round - robin way corresponding to the round - robin inputs . the input of the input terminal b is the output of the lower register 32 ′— the sum of a ′ and b ′, which is the result of addition undertaken in the preceding cycle . the input of the input terminal b ′ is the output of the upper register 32 — the sum of a and b , which is the result of addition undertaken in the preceding cycle . the timing diagrams of the abovementioned operations are described below . refer to fig1 a timing diagram of a case wherein all speculations are successful while the speculative lookahead processing device of the present invention is applied to an accumulator . the accumulator receives external inputs x0 , x1 and x2 in sequence at different cycles . the input x0 is executed by the upper datapath . the input x1 is executed by the lower datapath alternatively . then , the input x2 is executed by the upper datapath again . in the first cycle , the upper datapath calculates the addition of x0 and y − 1 . as only a cycle is spent in the calculation , the result is speculative . y0 ′ is used to symbolize the speculation value . the speculation value y0 is stored in the upper register 32 . in the second cycle , the upper datapath mainly undertakes two things : the first thing is continuing to calculate to obtain the correct value ; the second thing is undertaking comparison to examine whether the correct value is identical to the speculation value . the correct value is transmitted to and stored in the upper register 32 . in the case shown in fig1 , the speculation is successful , i . e . the speculation value is identical to the correct value . therefore , both the inputs of the input terminal a ′ and the input terminal b ′ of the lower datapath are correct , and the lower datapath is not influenced . in the third cycle , the upper datapath receives the input x2 and the speculation value of the lower datapath . the operation of the third cycle is the same as the operation of the preceding cycle : the lower datapath speculates successfully , and the upper datapath works normally . refer to fig1 a timing diagram of a case wherein only the speculation of the first input fails while the speculative lookahead processing device of the present invention is applied to an accumulator . the failure of speculation occurs in the second cycle , i . e . the speculation value is not identical to the correct value . thus , the system stalls the pipeline and interrupts inputting for a cycle . then , the third input x2 does not enter the datapath until the fourth cycle . during the stall of the pipeline , the timing controller sends a gating signal to the input terminals of the upper datapath to keep the input values for an additional cycle and guarantee that the inputs to the lower datapath can be maintained for two full cycles . in this case , the datapath spends two cycles in calculation . in the second cycle , the lower datapath receives and calculates the incorrect speculation value y0 ′ and outputs an incorrect value . therefore , the system transmits the correct value y0 to the datapath and resumes calculation in the third cycle . in order to deal with the resumed calculation and enable the datapath to calculate for two full cycles , the system sends a gating signal to the input terminals a ′ and b ′ in the fourth cycle , keeping the input for a cycle until the input x2 enters the datapath . refer to fig1 a timing diagram of a case wherein only the speculation of the second input fails while the speculative lookahead processing device of the present invention is applied to an accumulator . in this case , a speculation fails in the fourth cycle . thus , the system interrupts inputting for a cycle and sends a gating signal to the lower datapath for keeping the input for a cycle . in the next cycle , the system sends a gating signal to the upper datapath for keeping the input for one more cycle . refer to fig1 a timing diagram of a case wherein the speculations of the front two inputs fail while the speculative lookahead processing device of the present invention is applied to an accumulator . the front three cycles in fig1 are the same as fig1 . however , a speculation fails in the fourth cycle in fig1 . thus , the system interrupts inputting for a cycle and sends a gating signal to the lower datapath for keeping the input for a cycle . in the next cycle , the system sends a gating signal to the upper datapath for keeping the input for one more cycle . in conclusion , the present invention proposes a speculative lookahead processing device and method characterized in synchronously calculating the speculation value and the correct value , and using multiplexers to determine whether to output the speculation value or the correct value , whereby the latency is effectively shortened and the system performance is obviously enhanced . the embodiments described above are only to exemplify the present invention but not to limit the scope of the present invention . therefore , any equivalent modification or variation according to the shapes , structures , features , or spirit disclosed by the present invention is to be also included within the scope of the present invention .