while the present technology will be described more fully hereinafter with reference to the accompanying drawings , in which a preferred embodiment of the present technology is shown , it is to be understood at the outset of the description which follows that persons of skill in the appropriate arts may modify what is here described while still achieving the favorable results desired . accordingly , the description which follows is to be understood as being a broad , teaching disclosure directed to persons of skill in the appropriate arts , and not as limiting upon the protection sought . the term “ circuit ” or “ circuitry ” may be used in the summary , description , and / or claims . as is well known in the art , the term “ circuitry ” includes all levels of available integration , e . g ., from discrete logic circuits to the highest level of circuit integration such as vlsi , and includes programmable logic components programmed to perform the functions of an embodiment as well as general - purpose or special - purpose processors programmed with instructions to perform those functions . while various exemplary circuits or circuitry are discussed , fig1 depicts a block diagram of an illustrative exemplary computer system 100 . the system 100 may be a desktop computer system , such as one of the thinkcentre ® or thinkpad ® series of personal computers sold by lenovo ( us ) inc . of morrisville , n . c ., or a workstation computer , such as the thinkstation ®, which are sold by lenovo ( us ) inc . of morrisville , n . c . ; however , as apparent from the description herein , a client device , a server or other machine may include other features or only some of the features of the system 100 . the computer system 100 , when configured as a portable system of the types known as a notebook or netbook computer , will accommodate being powered either by a line voltage as derived from an electric utility or by a battery . further , the system will exchange electrical power with the battery either by drawing power from the battery , charging the battery while connected to line voltage , or both . the system 100 of fig1 includes a so - called chipset 110 ( a group of integrated circuits , or chips , that work together , chipsets ) with an architecture that may vary depending on manufacturer ( e . g ., intel ®, amd ®, etc .). the architecture of the chipset 110 includes a core and memory control group 120 and an i / o controller hub 150 that exchange information ( e . g ., data , signals , commands , etc .) via a direct management interface ( dmi ) 142 or a link controller 144 . in fig1 , the dmi 142 is a chip - to - chip interface ( sometimes referred to as being a link between a “ northbridge ” and a “ southbridge ”). the core and memory control group 120 include one or more processors 122 ( e . g ., single or multi - core ) and a memory controller hub 126 that exchange information via a front side bus ( fsb ) 124 ; noting that components of the group 120 may be integrated in a chip that supplants the conventional “ northbridge ” style architecture . in fig1 , the memory controller hub 126 interfaces with memory 140 ( e . g ., to provide support for a type of ram that may be referred to as “ system memory ”). the memory controller hub 126 further includes a lvds interface 132 for a display device 192 ( e . g ., a crt , a flat panel , a projector , etc .). a block 138 includes some technologies that may be supported via the lvds interface 132 ( e . g ., serial digital video , hdmi / dvi , display port ). the memory controller hub 126 also includes a pci - express interface ( pci - e ) 134 that may support discrete graphics 136 . in fig1 , the i / o hub controller 150 includes a sata interface 151 ( e . g ., for hdds , sdds , etc . ), a pci - e interface 152 ( e . g ., for wireless connections 182 ), a usb interface 153 ( e . g ., for input devices 184 such as keyboard , mice , cameras , phones , storage , etc . ), a network interface 154 ( e . g ., lan ), a gpio interface 155 , a lpc interface 170 ( for asics 171 , a tpm 172 , a super i / o 173 , a firmware hub 174 , bios support 175 as well as various types of memory 176 such as rom 177 , flash 178 , and nvram 179 ), a power management interface 161 , a clock generator interface 162 , an audio interface 163 ( e . g ., for speakers 194 ), a tco interface 164 , a system management bus interface 165 , and spi flash 166 , which can include bios 168 and boot code 190 . the i / o hub controller 150 may include gigabit ethernet support . the system 100 , upon power on , may be configured to execute boot code 190 for the bios 168 , as stored within the spi flash 166 , and thereafter processes data under the control of one or more operating systems and application software ( e . g ., stored in system memory 140 ). an operating system may be stored in any of a variety of locations and accessed , for example , according to instructions of the bios 168 . as described herein , a device may include fewer or more features than shown in the system 100 of fig1 . it is known that a computer system as illustrated in fig1 may support a plurality of states of power management through the power management interface 161 . such a system ( or other electronic device ) may have four states of power management : a normal operating state , a standby state , a hibernation state , and an off state . the standby state is characterized by devices , such as a video controller and a hard drive , being placed into a low - power mode transparent to the operating system and the applications executing on the computer system . the hibernation state is characterized by executing code being interrupted and the state of the computer system being saved to a file on the hard drive in such a manner that system power may be removed after the state of the computer system is saved to the hard drive . later , after system power is restored , the state of the computer system is resumed by reading from the hard drive and loading it in such a manner that the operating system and application programs are not adversely affected . the normal operating state and the off state correspond to the typical on and off states of computer systems lacking such multiple state of power management . transition from one state to another is variously controlled by passage of time or manipulation of manual switches or by remote actuation through a network adapter . in some known systems , the hibernate state is known as s3 ; hibernation as s4 ; and power off as s5 . transitions among the various power states can and will occur when the system is powered by line voltage and by a battery . the technology which is the focus of this description contemplates operation of the computer system in accordance with a process in which the system accommodates line and battery power , has a first cryptographic element and stores a plurality of digitally encoded number strings . as will be made more clear hereinafter , these number strings are stored within memory of the system accessible to the system processor and code stored in the system which manipulates the number string in a particular manner . the technology anticipates the coupling to the computer system of a battery which has a second cryptographic element . while the battery is coupled , there is an exchange of encrypted messages derived from one of the number strings between cooperating first and second cryptographic elements wherein a matched exchange enables the computer system to recognize the battery and exchange electrical power with the recognized battery . as used herein , the phrase “ matched exchange ” has a particular meaning . a matched exchange occurs when a number string originating from one of the system and the battery is transmitted to the other in an encrypted form , decrypted where received and compared to a previously established number string , encrypted for return transmission , and when decrypted matches the originating number string . such encryption is asymmetrical , using paired public and private keys . public - key cryptography refers to a method for transforming a message , including a number string , into a form that can be read only by an intended recipient . this cryptographic approach involves the use of asymmetric key algorithms . the non - message information ( the public key ) needed to transform the message to a secure form is different from the information needed to reverse the process ( the private key ). preferably , a public key is stored in the computer system and a private key is stored in a battery which can be coupled to the computer system , about which more will be said later . the plurality of number strings stored in the computer system are encrypted using the public key and may be communicated to the battery as an encrypted number string . the encrypted number string is then decrypted in the battery using the private key and the unencrypted number string returned to the system . if the returned number matches a number string stored in the system , then a matched exchange has occurred and the battery is recognized . in the event that there is no returned string or the returned string does not match , then the matched exchange fails and the electronic device will block the exchange of power with the unrecognized battery . the electronic device responds to a transition from one power state to another power state by initiating an exchange of encrypted messages and selects from among a plurality of stored encrypted number strings differing ones of the encrypted number strings to be used in exchanges initiated on successive transitions from one power state to another power state . referring now to fig1 and 2 , the drawings represent the elements involved in the exchange . a list of a plurality of digitally encoded number strings is maintained in or accessibly to the bios 200 which identify batteries to be recognized for the system . a public encryption key is also maintained . on each power state transition , each of the number strings is encrypted using the public key to create a list of challenges ( the encrypted number strings ) and responses ( the original number strings , as decrypted using the paired private key ) and store the challenge / response strings accessibly to the system management bus controller 201 . an encrypted number string to be used as a challenge becomes a number used once , also known as a nonce . because the number strings are stored in the controller 201 , the numbers are available for a challenge / response on any change of batteries in addition to power state transitions . the advantage of the cached numbers is that the controller 201 may manage new battery insertions while system operation continues . a battery 203 to be coupled to the system has cells 204 , a battery management unit 205 and a semiconductor component 207 which stores the private key . when a challenge arrives at the battery , the semiconductor component supplies the private key used to decrypt the challenge . the challenge is communicated to the battery management unit 205 through the system management bus 208 , the response ( the decrypted original number string ) is generated using the private key stored in the semiconductor component 207 , and returned through the bus 208 . in the event that the response matches the original number string , the battery is recognized and enabled for power exchange , discharging , charging or both . in the event there is no response or the response fails to match the original number string , the match fails , the battery is not recognized , and the exchange of power with the battery is blocked . the sequences are illustrated in fig3 . to restate , a list of number strings identifying batteries to be recognized is maintained as at 301 . on a power state transition , those numbers are encrypted with the public key at 302 and communicated to a battery at 304 ( the “ challenge ”). this can occur , for example , should a battery be changed during operation of the system or should a second battery be coupled to a system which accommodates such connections or should a change be made at a docking station . at the battery , the encrypted number is decrypted using the private key at 305 and returned to the system ( the “ response ”) at 306 . the system then checks for a match ( 308 ) and either enables or blocks the battery depending upon whether the match succeeds or fails ( 309 ). in this process , the public key stored in the system functions as a first encryption element , with the private key stored in the semiconductor device 207 functions as a second encryption element . the first encryption element is exercised by code stored in the system accessibly to the processor and causing the processor when executing the code to perform the encryption and storing described . in the drawings and specifications there has been set forth a preferred embodiment of the technology and , although specific terms are used , the description thus given uses terminology in a generic and descriptive sense only and not for purposes of limitation .