various embodiments of the present invention will be hereinafter described with reference to the accompanying drawings . fig1 is a block diagram showing the configuration of a content data recording apparatus according to a first embodiment of the present invention . in fig1 , input and output are independently shown to easily understand an operation inclusive of the case where a bus of this embodiment is a bidirectional bus . content data is video and audio having a frame format . when recording is started , the content data is supplied to a write buffer 10 . the write buffer 10 temporarily holds the content data to take time matching with an error correction code addition unit 20 . the error correction code addition unit 20 adds an error correction code to the content data output from the buffer 10 . the content data added with the error correction code is distributed to two signals by a distributor 30 . one of two signals is supplied to a write buffer 40 while the other thereof is supplied to a write buffer 50 . the write buffer 40 has a capacity equivalent to two pages . the buffer 40 outputs content data equivalent to one page when the content data remains more than one page . the write buffer 50 has a capacity equivalent to two pages . the buffer 50 holds the same content data as the buffer 40 . when the capacity equivalent to two pages becomes full , both buffers 40 and 50 overwrite new data in the order from data held at first . the buffer 50 holds content data equivalent to one page therein according to hold instructions from a central processing unit ( cpu ) 60 , and then , inhibits an overwrite operation . when receiving output instructions from the cpu 60 , the buffer 50 outputs the held content data equivalent to one page . a switching unit 70 receives content data output from the buffers 40 and 50 , and selectively outputs one content data of the buffers 40 and 50 to a storage device 80 . usually , the switching unit 70 outputs the content data from the buffer 40 . the storage device 80 includes a flash memory 81 , an address generator 82 , a state notification unit 83 and an error detector . the flash memory 81 can store content data written in units of pages . the address generator 82 generates write / read address in the flash memory 81 . the storage device 80 writes the output content data to the flash memory 81 according to a write address generated by the address generator 82 . when write to the flash memory 81 is started , the state notification unit 83 gives notification that the flash memory 81 is in a busy state to the cpu 60 . when write to the flash memory 81 is completed , the state notification unit 83 gives notification that the busy state ends to the cpu 60 . the error detector 84 detects an error in a write operation of content data to the flash memory 81 . when detecting a write error , the error detector 84 notifies the cpu 60 that the write error occurs . the content data written to the flash memory 81 is read according to instructions from the cpu 60 . a read buffer 90 temporarily holds the read content data to take time matching with an error correction unit 100 , and thereafter , outputs the read content data to the error correction unit 100 . the error correction unit 100 intactly passes the content data based on the error correction code added to the content data if no error occurs in a write operation . the error correction unit 100 corrects an error of the content data if an error occurs in a write operation . if the foregoing error is correctable by the error correction code , the error correction unit 100 outputs the corrected content data to a read buffer 110 . conversely , if the error of the read content data is not correctable , the error correction unit 100 gives correction impossible notification to the cpu 60 . the content data output to the buffer 110 is temporarily held , and thereafter , output outside as reproduction data . fig2 is a schematic view to explain the relationship between processing time of a storage device 80 and an error correction unit 100 according to a first embodiment of the present invention and processing time of processing continuously input content data every frame . in fig2 , the case where content data equivalent to one frame ranges a plurality of pages is given as one example . in order to realize the foregoing processing , a content data recording apparatus must be designed sufficiently considering write / read time to the flash memory 81 and error correction time in the error correction unit 100 . specifically , the storage device 80 and the error correction unit 100 must be designed to satisfy the following condition so that time of rewriting content data having an error to the flash memory 81 is secured . according to the condition , the total time of write time , read time and error correction time of the content data is shortened more than time of processing content data equivalent to one page with respect to time of inputting one frame content data . the cpu 60 completes rewrite of the content data within a free time thus produced . the cpu 60 controls write / read of content data to the storage device 80 so that normal content data is stored in the storage device 80 . fig3 is a flowchart to explain the content data rewrite procedure by the cpu 60 according to the first embodiment of the present invention . the content data from the buffer 40 is supplied to the storage device 80 , and then , written to the flash memory 81 according to a write address generated by the address generator 82 . when write is started , the state notification unit 83 gives notification that the flash memory 81 is in a busy state to the cpu 60 ( block b 1 ). the cpu 60 determines whether or not notification that the busy state ends is given when the flash memory 81 is in the busy state ( block b 2 ). if the notification that the busy state ends is given ( yes in block b 2 ), the cpu 60 determines whether or not notification that a write error is detected is supplied from the error detector 84 ( block b 3 ). if there exist no notification that the write error is detected ( no in block b 3 ), the cpu 60 determines that write to the flash memory 81 ends safely . then , the cpu 60 reads the written content data ( block b 4 ). the cpu 60 determines whether or not correction impossible notification from the error correction unit 100 is given ( block b 5 ). if the notification is not given ( no in block b 5 ), the cpu 60 ends the procedure because the content data is normally stored in the storage device 80 . conversely , if the correction impossible notification from the error correction unit 100 is given ( yes in block b 5 ), the cpu 60 outputs save command to the buffer 50 , and holds the write address of the content data ( block b 6 ). in this way , the same content data as the content data output to the storage device 80 from the buffer 40 is stored in the buffer 50 . then , the cpu 60 determines whether or not the one - frame content data procedure ends ( block b 7 ). if the one - frame content data procedure ends ( yes in block b 7 ), the cpu 60 gives instructions to the address generator 82 to generate a new address different from the write address of the flash memory 81 having an error ( block b 8 ). when the new address is generated , the cpu 60 controls the switching unit 70 so that the switching unit 70 outputs the content data from the buffer 50 ( block b 9 ), and thus , gives output instructions to the buffer 50 ( block b 1 ). the content data output from the buffer 50 is stored in the storage device 80 . the cpu 60 transfers the procedure to the block 82 to confirm whether or not the content data is normally stored in the storage device 80 . in block b 2 , if there exists notification that the busy state is completed is not given ( no in block b 2 ), the cpu 60 determines whether or not a state that the notification is not given continues for a predetermined time ( block b 11 ). if the notification is not given after the predetermined time elapses ( yes in block b 11 ), the cpu 60 transfers the procedure to block b 6 . if the predetermined time does not elapse ( no in block 811 ), the cpu 60 transfers the procedure to block b 2 . in block b 3 , if a write error occurs ( yes in block b 3 ), the cpu 60 transfers the procedure to the block b 6 . in this case , the cpu 60 completes a series of procedures ( from block b 8 to block b 10 ) of outputting the content data from the buffer 50 and writing it to the flash memory 81 within a free time shown in fig2 . if the rewrite procedure is not completed from the reason why a write error again occurs in the content data from the buffer 50 , the cpu 60 takes the foregoing series of procedures within a free time generated after the next frame ends . in this case , there is a possibility that the capacity of the buffer 50 is short ; therefore , preferably , the buffer capacity has two pages or more . although no illustration in fig3 , when the rewrite procedure of fig3 ends , the cpu 60 controls the switching unit 70 so that the switching unit 70 selects the content data from the buffer 40 . in other words , usually , the content data from the buffer 40 is output via the switching unit 70 , and in a rewrite operation only , the content data from the buffer 50 is output via the switching unit 70 . according to the foregoing first embodiment , if the predetermined time elapses in a state that the cpu 60 does not receive the notification that the busy state ends from the state notification unit 83 , the cpu 60 determines that write of content data fails . then , the cpu 60 gives instructions to save the same content data as the write - failed content data to the buffer 50 . further , the cpu 60 saves the write address of the write - failed content data together with the save instructions . the cpu 60 controls the address generator 82 so that the address generator 82 generates a write address different from the write address of the flash memory having an error . then , the buffer 50 outputs the saved content data , and rewrites the content data to the flash memory based on a new write address . in this way , even if content data write to the flash memory 81 is not completed , the content data recording apparatus can rewrite the content data to the flash memory 81 , and therefore , can record the content data to the flash memory 81 normally . if write to the flash memory 81 is completed , and there exists notification that a write error is detected output from the error detector 84 , the cpu 60 determines that write of the content data fails . then , the cpu 60 saves the write - failed content data in the buffer 50 to rewrite the content data to the flash memory 81 . in this way , even if an error occurs in a write operation to the flash memory 81 , the content data recording apparatus can rewrite the content data to the flash memory 81 , and therefore , can record the content data to the flash memory 81 normally . if write to the flash memory 81 is completed , and there exists no notification that a write error is detected , the cpu 60 reads the data at the same time as the write completion . the error correction unit 100 corrects the read content data based on an error correction code added to the data . if correction is impossible , the error correction unit 100 gives correction impossible notification to the cpu 60 . when receiving the correction impossible notification , the cpu 60 saves the content data that is impossible to correct in the buffer 50 to rewrite the content data to the flash memory 81 . in this way , even if write to the flash memory 81 is completed , and a write error is not detected , it is possible to automatically confirm whether or not the content data is normally written . if write to the flash memory 81 fails , the content data is rewritten to the flash memory 81 . therefore , it is possible to compensate for content data loss . the cpu 60 executes rewrite of the write - failed content data within a free time between one - frame transfer time of the content data and processing time of one - frame content data . this serves to execute rewrite without hindering write of continuously input content data to the flash memory 81 . the flash memory is generally capable of erasing data in units of blocks . thus , the new write address of the flash memory is generated based on the units of blocks when the error that is impossible to correct occurs . a method to manage a continuity of the content data is adopted in generation of the new write address . as this method does not relate to this invention , the procedure of the generation of the new write address is omitted . according to the present invention , the content data recording apparatus securely detects a write error without hindering normal write of content data to the flash memory , and records the content data . the present invention is not limited to the foregoing first embodiment . for example , the content data recording apparatus is provided with two write buffers , and each capacity of the buffers 40 and 50 is two pages . however , the number of write buffers is not limited to two , and the capacity is not limited to two pages . fig4 is a block diagram showing the configuration of a content data recording apparatus according to a second embodiment of the present invention . the same reference numbers are used to designate the same portions as fig1 , and the overlapping explanation is omitted . content data output from an error correction code addition unit 20 is temporarily held in a ring buffer 120 , and then , output to a storage device 80 . the ring buffer 120 has a capacity equivalent to 16 pages . the ring buffer 120 successively writes input content data from the header address to the final address . when the content data is written to the final address of ring buffer 120 , the ring buffer 120 writes new content data to its header - address . when content data equivalent to one page is collected , the ring buffer 120 outputs the content data equivalent to one page . when determining that an error requiring rewrite occurs , a cpu 60 stores an address on the ring buffer 120 of data to be rewritten . when the ring buffer 120 receives instructions to output rewrite data from the cpu 60 , the ring buffer 120 outputs the stored content data equivalent to one page . according to the foregoing second embodiment , if write to a flash memory 81 of the storage device 80 fails , the write filed content data stored in the ring buffer 120 is again output to the storage device 80 . thereafter , the content data is rewritten to the flash memory 81 . in this way , even if the ring buffer 120 is used , it is possible to automatically determine whether or not content data is normally written . in addition , it is possible to compensate for the loss of the write - failed content data . therefore , the content data recording apparatus according to the present invention securely detects a write error without hindering normal write of content data to the flash memory , and records the content data . additional advantages and modifications will readily occur to those skilled in the art . therefore , the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described herein . accordingly , various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents .