fig1 shows the first embodiment of the code generator according to the present invention , in which lat1 and lat2 are latch circuits , which receive code pattern data pt 2 to pt n and code phase data ph 1 to ph n in time sharing from data lines dat1 to n , respectively , and hold them ; trs1 and trs2 are bit inverting circuits , each of which outputs the input as it is , when a control signal trc is at the &# 34 ; h &# 34 ; level , and a signal inverted so that the lsb ( least significant bit ) and the msb ( most significant bit ) are replaced by each other , when it is at the &# 34 ; l &# 34 ; level . further dec1 is a decoder circuit for controlling the data input to the latch circuit , responding to a latch select signal sel and a latch enable signal le and msrg1 is a modular type shift register circuit having a structure of n stages . still further lat3 is a latch circuit disposed in order that the bit inverting operation is performed in synchronism with a stb signal . fig2 and 3 show concrete examples of the bit inverting circuit and the modular type shift register circuit , respectively . in fig2 ds 1 to ds n are data select circuits . in fig3 an 2 to an n are and circuits ; sr1 to srn are flipflops constituting the shift register ; and e 2 to e n are exclusive logic sum circuits . in the case where code generators , whose structure is indicated in fig6 are used in the transmission and reception , when mirror image codes are generated in the transmission and the reception , the relation between the two sets of code data will be described . however , in the case where the two codes are in a mirror image relation to each other , since it is clear that the code periods of them are equal to each other , it can be supposed that the number of stages of the two modular type shift registers is n . further , for the purpose of explanation the code pattern data a 2 to a n are defined by a vector [ a 2 a 3 . . . a n - 1 a n ] and the code phase data b 1 to b n by [ b 1 b 2 . . . b n - 1 b n ]. then the code data given in the transmission and the reception can be expressed as follows ; ______________________________________on the transmission side ; code pattern data ; [ ta . sub . 2 ta . sub . 3 . . . ta . sub . n - 1 ta . sub . n ] code phase data ; [ tb . sub . 1 tb . sub . 2 . . . tb . sub . n - 1 tb . sub . n ] on the reception side ; code pattern data ; [ ra . sub . 2 ra . sub . 3 . . . ra . sub . n - 1 ra . sub . n ] code phase data [ rb . sub . 1 rb . sub . 2 . . . rb . sub . n - 1 rb . sub . n ] ______________________________________ as described in the explanation of the prior art system , the code data are data indicating the feedback wiring method and the code phase data are data indicating the initial state of the modular type shift register . at first , concerning the feedback wiring method for obtaining the mirror image code , according to r . c . dixon , spread spectrum systems , pp . 86 - 92 , john wiley & amp ; sons ( 1984 ) it is known that a feedback wiring method , [ n , n - r , . . . n - p ] m for [ n , r , . . . p ] m , may be used . consequently it can be known that the code pattern data on the reception side may be set as equation ( 1 ); [ ra . sub . 2 ra . sub . 3 . . . ra . sub . n - 1 ra . sub . n ]=[ ta . sub . n ta . sub . n - 1 . . . ta . sub . 3 ta . sub . 2 ] ( 1 ) next the method for determining the initial state of the modular type shift register for obtaining the mirror image code is disclosed in hamatsu , et al ., national meeting of the electric communication society 48 , ( 1986 ) ( in japanese ) and jp - a - 63 - 95744 . in particular , in the case where the code output is taken out from the last stage of the modular type shift register , according to japanese patent application no . 63 - 255396 , it is known that the code phase data may be set , as given by equation ( 2 ). [ rb . sub . 1 rb . sub . 2 . . . rb . sub . n - 1 rb . sub . n ]=[ tb . sub . n tb . sub . n - 1 . . . tb . sub . 2 tb . sub . 1 ) ( 2 ) consequently , according to equations ( 1 ) and ( 2 ), it is known that same code data can be utilized in common in the transmission and the reception by means of a bit inverting circuit , which replaces the lsb and the msb by each other . as explained above , according to the first embodiment of the present invention it is possible to obtain two codes , which are in the mirror image relation , starting from same code data , and thus an advantage is obtained in that the same code data can be used in the transmission and the reception in the case where a same code is used in the transmission and the reception , and even in the case where the mirror image code is used . fig4 shows a second embodiment of the code generator according to the present invention . in fig4 msrg1 , msrg2 and msrg3 are modular type shift register circuits having a structure consisting of n stages , whose concrete example is indicated in fig3 ; ptn1 and ptn2 are memory circuits holding code pattern data specifying the feedback wiring method for the modular type shift register circuits msrg1 and msrg2 as well as msrg3 ; and lat1 is a latch circuit , which receives data of n - 1 bits in the initial state of n bits for the shift register circuits msrg2 as well as msrg3 from the exterior to hold them . further , e1 and e2 are exclusive logic sum gates for adding the code outputs of the shift register circuits msrg1 and msrg2 and the code outputs of the shift registers msrg1 and msrg3 , respectively , mod . 2 ; ff1 , ff2 and ff3 are flipflops disposed for removing hazards produced in the exclusive logic sum gates and for obtaining a code output in synchronism with a clock signal ; and ds1 is a data select circuit , which selects either one of the gold code generated by the gate e1 and the gold code generated by the gate e2 , responding to the state of a cski signal given from the exterior and outputs it to the flipflop ff3 . in fig4 by giving the memory circuits ptn1 and ptn2 different code pattern data , it is possible to obtain two sorts of m sequence codes in the shift register circuits msrg1 and msrg2 as well as msrg3 . further , since same code pattern data are given to the shift register circuits msrg2 and msrg3 , a same sort of am sequence codes are obtained there . however , concerning the initial stage , since the n - 1 bits at the terminals b2 to bn are common to the two shift register circuits and the remaining one bit at the terminal b1 is fixed at the &# 34 ; h &# 34 ; level for the msrg2 and at the &# 34 ; l &# 34 ; level for the msrg3 , codes having different phases are produced . consequently the gold codes generated at the gates e1 and e2 are always different . further , since all the initial states of the shift register circuit msrg1 are fixed at the &# 34 ; h &# 34 ; level , in the case where the initial state of n - 1 bits at the terminals b2 to bn of the shift register circuits msrg2 and msrg3 are changed , it is possible to obtain a pair of gold codes having patterns , which are not overlapped but are different from each other . although there are 2 n - 1 sorts of data , i . e . from 0 to 2 n - 1 - 1 ( decimal ), which can be inputted from data lines of n - 1 bits , dat1 to n - 1 , since for 0 ( decimal ) all the initial states of the shift register circuit msrg3 are set at the &# 34 ; l &# 34 ; level , no m sequence code output can be obtained from the shift register circuit msrg3 . consequently there are 2 n - 1 - 1 sorts of code data , which can be used for the csk in reality . it is possible for the user to eliminate the necessity of control by means of a microcomputer or complicated driver circuits by assigning the code data from 1 to 2 n - 1 - 1 ( decimal ) to the channel number , as they are . although a code generator having the modular type shift register structure has been taken as an example in the above , it is true also in the case of the simple typ shift register structure that different kinds of gold codes can be obtained by varying the initial state and thus it is a matter of course that the present invention can be applied to a code generator having the simple type shift register structure . as explained above , according to the second embodiment of the present invention , it is possible to obtain a code generator for the csk , in which the code data can be assigned to the channel number , as they are . fig5 shows the third embodiment of the code generator according to the present invention . in fig5 msrg1 and msrg2 are modular type shift register circuits . a concrete example of the circuits is indicated in fig3 . the difference thereof from the modular type shift register portion indicated in fig4 is that the number of stages is fixed at n . further e1 is an exclusive logic sum gate for adding two m sequence codes mod . 2 . ff1 is a flipflop disposed for removing hazards . since the input signal to the flipflop of the n - th stage is taken out through the terminal sr n of the modular type shift register circuits , at a terminal gold , a gold code having a phase completely identical to that of the m sequence codes outputted through terminals code1 and code2 is obtained . further , in the figure , ptn1 and ptn2 are memory circuits , in which the code pattern data of the shift register circuits msrg1 and msrg2 are stored , and lat1 is a latch circuit , which receives the code phase data of the shift register circuit msrg2 from the exterior to hold them . trs1 , trs2 and trs3 are bit inverting circuits capable of generating two codes , which are in a mirror image relation to each other , starting from same code data . a concrete example of the circuits is indicated in fig2 . it is known that 2 n - 1 gold codes can be obtained , starting from two m sequence codes having a period of 2 n - 1 , by varying the phase difference therebetween ( r . c . dixon , spread spectrum systems , pp . 53 - 92 , john wiley & amp ; sons ( 1984 )). consequently , according to the system of the present invention , the number of stages and the code pattern data of the two shift register circuits are fixed and only the code phase data are set from the exterior . in fig5 since all the initial states of the shift register circuit msrg1 are fixed at the &# 34 ; h &# 34 ; level , the phase difference between two m sequence codes can be varied by varying the initial state of the shift register circuit msrg2 . the states , which the modular type shift register having a structure consisting of n stages can take , are all the binary values of n bits except for the initial state , in which all the bits are 0 . that is , it can be understood that , in the code data given from the exterior there are 2 n - 1 sorts from 1 to 2 n - 1 ( decimal ) and that different gold code outputs are obtained for different sorts . the user can set the code only by specifying the channel number , without knowing the structure of the code generator as in the prior art system , by assigning the code data from 1 to 2 n - 1 ( decimal ) corresponding to the initial states of the shift register circuit msrg2 to the channel number . further , in the circuit indicated in fig1 , since it comprises bit inverting circuits , also in the ssc using mirror image codes in the transmission and reception such as the convolver system , communication can be simply effected by specifying a same channel number both for the transmission and for the reception and switching over the transmission and the reception by a t / r signal . further it is possible to increase the number of channels by using ram , eprom or latch circuits for the memory circuits ptn1 and ptn2 in fig1 so that the code pattern data can be rewritten . although a code generator having the modular type shift register structure has been taken as an example , it is a matter of course that the present invention can be applied also to a code generator having simple type shift register structure . as explained above , according to the third embodiment of the present invention no only the selection of the channel , i . e . the method for setting the code , is simplified , but also another advantage is obtained that it is possible to use the channel number as code data , as it is . while particular embodiments of the invention have been shown and described , it will be obvious to those skilled in the art that various changes and modifications may be made without departing from the present invention in its broader aspect .