in an illustrative embodiment of the present invention , referring to fig1 , an integrated optoelectric ( oe ) package or assembly 10 is depicted and may be fabricated using standard complementary metal - oxide - semiconductor ( cmos ) processes . the oe assembly 10 includes a silicon substrate 14 that contains wiring layers 18 of fine wiring and , in an alternative embodiment , electrical circuitry . the fine wiring 18 interconnects oe arrays 22 which in the embodiment of fig1 is an array of vertical cavity surface emitting lasers ( vcsel ) or photo diode ( pd ) arrays , herein collectively referred to as the oe arrays 22 . the oe arrays 22 communicate with laser diode drivers ( ldd ) and transimpedance amplifiers ( tias ) collectively referred to with reference numeral 26 . dedicated wiring of the fine wiring 18 route signals from the ldds and tias 26 to pads 30 have c4 bumps 34 or other interconnect elements . a through hole 40 ( or optical via ) is fabricated in the substrate . the hole 40 enables light 42 to pass from the oe device to a microlens array 44 on the substrate 14 . the through hole 40 is , for example , 50 to 200 microns in diameter , however smaller or larger hole sizes are possible and may be fabricated using an etch process such as , bosch ™® etch . as an alternative to individual holes ( one hole / oe source or detector region ), a through slot which spans all oe source / detector regions of a particular oe array may be fabricated . the microlens array 44 functions to collimate or focus the light to and from the oe arrays 22 . the glass microlens array 44 wafer may have a thickness of 100 to 1000 microns in the embodiment of the present invention depicted in fig1 , a method for manufacturing the integrated optoelectric ( oe ) package or assembly 10 includes the steps below ( which are not shown in the drawings ). after silicon wiring layers ( resulting in wiring layers 18 in the substrate 14 ) have been fabricated on a silicon wafer , a through hole ( or optical via ) is fabricated ( shown as hole 40 on the substrate 14 ). the hole 40 enables light to pass from the oe device to a microlens array ( shown as lens array 44 on the substrate 14 ). the through hole 40 is for example , 50 to 200 microns in diameter however smaller and larger sizes are possible and may be fabricated using an etch process such as , bosch ™® etch . the silicon wafer is then attached to a temporary handling wafer , and is ground and polished to a thickness of between about 10 to 200 microns . after polishing , the silicon wafer may be further thinned by chemical etch ( for example , using si anisotropic etching , for example , tmah ( tetramethylammonium hydroxide ) or koh ( potassium hydroxide ) etching ), leaving the si wiring and si circuitry on the glass handler . when the si wiring is left on the glass , the high speed electrical performance of the wiring is improved . also , by leaving the si wiring and circuitry on the glass handler , there is no need to fabricate the optical via or optical window since all bulk si ( other than the wiring and circuitry ) is removed . the silicon wafer is then transferred and attached to a glass wafer which contains microlenses . the glass wafer could contain microlenses of spherical or aspherical shapes . the microlenses could be refractive or diffractive or a combination . instead of glass other optically transparent materials could be used such as inp or gaas ( indium phosphorus or gallium arsenide ), or transparent plastic . a microlens array functions to collimate or focus the light to and from oe elements ( oe arrays 22 ). the temporary handling wafer is then removed exposing the silicon wiring and pads . the wafer may then be bumped by attaching c4 balls ( shown as solder balls 34 on the substrate 14 ), or other interconnect elements ( for example , pins , or columns ) may be attached , resulting in the silicon substrate 14 . the next step in the fabrication process is to attach oe devices to the substrate 14 . a vcsel array ( vertical cavity surface emitting laser diode array ) or a pd array ( photodiode array ) is bonded to the silicon substrate using standard flip chip bonding tools ( such as suss ® microtech flip chip bonder ). the oe to silicon chip join may consist of micro c4s solder balls , compression bonds , or other interconnects . the ldd , tia , and the oe may be underfilled to protect and secure the chip joins to complete the fabrication of the oe assembly 10 . other processing / manufacturing sequences of the above individual steps may be used to generate the oe assembly 10 which are within the scope and spirit of the present invention . the silicon wafer may be fabricated using standard cmos processes . alternatively other device substrates could be used such as sige , gaas , or silicon on insulator ( soi ). the bonding of the glass lens wafer to the silicon is performed using standard wafer to wafer bonding tools . an alignment accuracy of +/− 1 micron is obtained . referring to fig2 a , the oe assembly 10 includes a 2 × 12 array of microlenses . it is understood that other lens arrangements are possible , such as a 1 × 12 array , a 4 × 12 array or larger two dimensional arrays of lenses . fig2 b shows a bottom view of the oe assembly 10 with the ldd / tia elements 26 removed . the interconnect pads 30 are bumped with c4 balls 34 as shown in fig1 . the interconnect pads 30 provide the connection between the oe assembly 10 and a next level of packaging . high density wiring 18 connects the pads to the ldds and tias chips 48 . the ldd and tias chips 48 are connected to pads 30 on which the oe device 10 is mounted . the through hole optical via 40 allows light to pass to the microlenses 44 . alternatively , it may be desirable , in view of high frequency electrical signal integrity , to control the electrical impedance and balance the timing skew between different channels between the pads 30 of the circuitry on the ldd or tia chip 48 ( input / interconnect pads ), and the pads 30 connecting the oe 10 to another device ( oe ouput pads ). one way to control the electrical impedance and balance the trimming skew is by minimizing the electrical signal lines length difference between the channels in a layout circuit wiring . another optimization includes minimizing the area of the ldd and tia circuitry layout on the chip 48 , which may involve placing the individual ldd / tia channel circuitry on the same pitch as the oe pads 30 or oe diodes . referring to fig2 c , a vcsel array 22 is shown having the oe 10 with a source region 52 which emits light . the pads 30 interconnect the source region 52 to silicon drive circuitry . the arrangement of pads may be similar for the photodiode ( pd ) arrays 22 . it is understood that the oe lens array 44 ( and oe devices ) may be multidimensional , for example a 2 × 12 , 4 × 12 or a larger array of active elements . referring to fig3 , in another embodiment of the invention , a package 70 includes the oe assembly 10 mounted on a carrier 60 . the carrier 60 may be , for example , an organic laminate , ceramic , silicon , or other substrate material . the device drivers , i . e ., the ldd drivers / tia and oe arrays 22 , on the oe assembly 10 protrude into a cavity 64 on the carrier 60 . c4 balls 34 interconnect the oe assembly 10 to the carrier 60 . the c4 interconnects 34 may be underfilled to strengthen and protect the integrity of the join . a heat spreader 68 is positioned at the bottom of the cavity 64 . the heat spreader 68 may be used to transfer heat from the oe 10 and for example , cmos devices , to the side of the package 70 for removal by , for example , an air cooled heat sink , a water cooled heat sink , or by other standard heat removal means . the carrier 60 may be further attached to a printed circuit board ( pcb ) 72 by means of a ball grid array ( bga ) or land grid array ( lga ) interconnect 76 . the carrier 60 also serves as an electrical and mechanical interposer . the oe assembly 10 is used to form a custom number of optical channels , with the carrier 60 serving as an electrical and mechanical interposer between the oe assembly 10 and the pcb 72 . referring to fig4 , another embodiment of the invention includes a package 80 including an embodiment of an oe assembly 100 wherein features consistent with the oe assembly 10 shown in fig1 have the same reference numerals . the oe assembly 100 includes the silicon substrate 14 , oe arrays 22 , and an attached lens array 44 . in this case the ldd and tia devices 26 are attached to the carrier 60 . it is understood the carrier may be organic , ceramic , silicon , or other suitable material . it is understood that a number of oe arrays 22 may be extended beyond two arrays . it is also understood that a combination vcsel and photodiode arrays 22 may be used on the oe assembly 100 to provide a transceiver function . referring to fig5 , in another embodiment of the invention , a package 90 includes the oe assembly 10 ( shown in fig1 and 3 ) and an additional device attached to the carrier substrate 60 . the additional device may be a processor or asic ( application specific integrated circuit ) chip 78 , or another component . in some cases , it is highly desirable to place the additional device 78 as close as possible to the oe assembly 10 to minimize the electrical power and cost by incorporating some or all of the ldd circuitry 26 within the additional device 78 . in alternative cases , it may be desirable to use standard ( non - custom ) additional device ( s ) where the needed ldd / tia 26 circuitry requirements are in the oe assembly 10 . referring to fig6 , another embodiment of a package 120 includes the oe assembly 10 rotated one hundred and eighty degrees and attached to a carrier substrate 104 . in the embodiment of fig6 , the carrier substrate includes an optional recessed region , including an electrical interconnection in the recessed region to connect the oe assembly to the carrier 104 . alternatively ( not shown ), the carrier could have only a hole or rectangular opening and no recessed region , in this case , electrical interconnect is done on the bottom side of the carrier . also , an additional interposer ( not shown ) could be used to create a larger gap between the pcb and the oe assembly . the light 42 is orientated downward towards the printed circuit board ( pcb ) 72 . optical waveguides 106 are attached to the top surface of the pcb 72 . a lens array 112 is positioned on top of the waveguides 106 which couples the light from the oe assembly 10 to the waveguide cores . also , waveguide turning mirrors 108 reflect the light 42 ninety degrees . the light 42 within the optical waveguides 106 may be conveyed across the pcb 72 to other optical assemblies or to an edge of the printed circuit board for interconnection with an optical backplane or optical fiber cables . a heat spreader 116 in positioned on the top of the carrier 104 . the thermal interface material 69 is used to connect the heat spreader 116 to the ldds / tias 22 , and oe arrays 22 . the heat spreader 116 may be connected to a top side heat sink to remove heat from the package 120 . referring to fig7 a , 7 b , and 7 c , the oe assembly 10 is attached to the carrier 60 and a mating waveguide / optical connector 124 . referring to fig7 a , an optical cable 126 is connected to the waveguide / optical connector 124 . the waveguide cable 126 may be a polymer and incorporates turning mirror elements 128 , a lens array 44 , and a connector housing 132 . referring to fig7 b , an oe assembly 130 on the carrier 60 incorporates an alignment frame 134 . the alignment frame 134 is passively aligned to the lens oe assembly 130 lens array 144 , and then glued into place . during fabrication of the lens array 144 , additional features may be formed which can be used to accurately position the alignment frame 134 . for example , a step 136 is formed in the lens array 144 , for the alignment frame 134 to reference . thereby , after assembly the alignment frame 134 is accurately referenced to the lens array 144 and the devices 26 to specified semiconductor tool tolerances , such as , within a 1 or 2 micron alignment tolerance . the oe assembly 130 is mated to the optical connector 124 as shown in fig7 c forming a package 140 . the optical connector 124 seals the optical elements , i . e ., the turning mirrors 128 , the waveguide cable 126 and connector 132 from dust or other contaminates . referring to fig8 , an alternate oe assembly 150 according to the invention includes wiring or circuitry 18 on top of the silicon substrate 14 interconnecting the vcsel / pds 22 , and ldd / tia 26 devices . the lens array 44 is aligned and attached to the silicon substrate or carrier 14 . the silicon substrate / carrier 14 contains through silicon vias 152 which connect the top side wiring 14 to bottom side pads 30 . c4 bumps 34 are attached to the pads 30 . a stiffener frame 154 and a heat spreader 156 are positioned on top of one another . the head spreader 156 conducts heat from the ldd / tia 26 , and pds 22 and spreads it laterally . a conventional heat sink may be attached to the top to cool the assembly 150 . referring to fig9 , where like features have the same reference numerals as the embodiments of the invention shown in fig1 , 3 - 8 , another embodiment of an oe package 160 includes through silicon vias 152 in the embodiment of the oe assembly 150 shown in fig8 . the oe assembly 150 is attached to a carrier substrate 162 . in the oe package 160 , shown in fig9 , the light 42 is directed downward towards the pcb 72 . referring to fig1 , where like features have the same reference numerals as the embodiments of the invention shown in fig1 , 3 - 9 , another embodiment of an oe package 170 includes the ldds / tias 26 , and oe arrays 22 a are attached to a first silicon substrate / carrier 174 a which is thicker ( e . g ., between 100 to 800 microns thick ) than in the previous embodiments shown in fig3 - 6 . an optical coupling glass wafer is reversed and the microlens 176 surface faces the oe arrays 22 . the glass lens array 176 may be thicker than in previous embodiments , since the light 42 passes through the glass substrate 176 in a collimated manner . a second silicon substrate 174 b includes wiring 18 and through silicon vias 152 as shown in fig8 and 9 . the second silicon substrate 174 b is used to redistribute the signals from fine interconnect pads on the first silicon substrate 174 a to larger pads 30 ( and larger pitch ) on the second silicon substrate 174 b . further , the second silicon substrate 174 b conducts heat from the first silicon substrate 174 a laterally to a heat spreader / alignment frame 172 . the heat spreader / alignment frame 172 is bonded to the second silicon substrate 174 b . a heat sink may be attached to the heat spreader / alignment frame 172 to cool the oe assembly 180 . the heat spreader / alignment frame 172 may also serve as an alignment frame for mating with an optical connector . the components on the oe assembly 180 may be underfilled or sealed 178 as shown in fig1 . the sealing 178 serves to strengthen the components and protect the internal bond pads from the environment . referring to fig1 , another embodiment of an oe assembly 200 in an oe package 210 is similar to the embodiment shown in fig1 , however , the oe assembly 200 includes ldd and tia circuitry imbedded in the first silicon substrate 174 a . in some cases , it is desirable to place the ldd and tia devices as close as possible to the oe devices 22 to minimize the electrical power and cost by incorporating the circuitry in the first silicon substrate 174 a . in an alternative embodiment , the ldd / tia circuitry is attached to the first silicon substrate . other embodiments may also include oe devices being two dimensional , e . g ., containing 2 × 12 arrays , 4 × 12 arrays or more devices per oe substrate . fig1 shows an oe assembly 220 of an oe package 230 with a thicker silicon substrate 224 . a lens array 232 is shortened in comparison to previous embodiments , thereby exposing a top portion of the silicon substrate 224 . the exposed top portion of the silicon substrate 224 enables a heat spreader 234 to be directly attached to the top of the silicon substrate 224 , and to be referenced laterally by reference features 233 in the lens array 232 . by attaching the heat spreader 234 to the top of the silicon substrate 224 , heat may be conducted away from active devices , for example , oe arrays 22 and drivers / tias 26 , and distributed to a top side heat sink / spreader 234 . referring to fig1 , another embodiment of an oe package 240 includes the oe assembly shown in fig1 , however , in the oe package 240 , a second silicon spacer 242 ( or silicon frame ) having silicon vias there through is attached to the first silicon substrate 224 . in this case a cavity is not required in the organic or ceramic carrier and the oe assembly may be attached to a flat carrier as shown . thereby , the oe packages and oe assemblies shown in the embodiments of the invention , integrate the oe transceiver elements in a compact space . thereby , the present invention provides a system and assembly of integrated packaging , and a method of integrated packaging for reducing the size and lowering the cost of optical transceivers . more specifically , the optoelectronic drivers and receivers are processed and packaged with optical coupling elements , and oe ( vcsel and pd ) elements using a wafer scale packaging technology , together with 3d stacking , for integrating the elements in a compact space , resulting in improved density of components and lower cost manufacturing or fabrication . while the present invention has been particularly shown and described with respect to preferred embodiments thereof , it will be understood by those skilled in the art that changes in forms and details may be made without departing from the spirit and scope of the present application . it is therefore intended that the present invention not be limited to the exact forms and details described and illustrated herein , but falls within the scope of the appended claims .