a method and associated apparatus are described herein that provide for sensing the data stored by an entire wordline of a memory device in parallel without the excessive consumption of current . the advantages of the present described method and apparatus are provided , in part , by performing read operations of the memory cells without requiring an active cell current i d ( i . e . approximately zero dc cell current ). because no cell current is required to sense the data stored by the nonvolatile memory , the amount of power required to read each cell is reduced sufficiently to allow for an entire selected wordline of memory cells to be read simultaneously . wherein the amount of time required to form a single read operation using the described methods may , under some circumstances , be longer than the amount of time required to read a memory cell using some prior at schemes , the fact that many more memory cells can be sensed in parallel allows the sensing time to be amortized over many more cells so that the average amount of time to read each cell is significantly reduced and performance is increased . the sensing system that operates according to present embodiments , as described with respect to fig2 - 10 , does not require the drain bias circuit , a differential sense amplifier , or an active cell current in order to accurately sense the amount of charge stored on the floating gate of a memory cell . instead , the sensing system and method described herein uses a source bias and an analog - to - digital converter ( adc ) to detect the state of a cell in a manner that will be described below . fig2 - 5 diagramatically illustrate the manner in which the state of a memory cell may be sensed according to the present embodiments . fig2 shows a memory cell 35 having its select gate sg coupled to a wordline 40 , its &# 34 ; drain &# 34 ; d coupled to a bitline 45 , and its source s floating . the process of sensing the state of memory cell 35 is begun in fig2 by setting the voltage of bitline 45 , and therefore the &# 34 ; drain &# 34 ; d of memory cell 35 , to system ground v ss . alternatively , the drain d of memory cell 35 may not first be set to v ss . as shown in fig3 the ground potential v ss is removed from bitline 45 such that both the &# 34 ; drain &# 34 ; d and &# 34 ; source &# 34 ; s of memory cell 35 are floating . as shown in fig4 a read voltage v g is then applied to wordline 40 while a bitline 45 and the source of memory cell 35 remain floating . in fig5 a source voltage v s is applied to the &# 34 ; source &# 34 ; s of memory cell 35 , which results in the &# 34 ; drain &# 34 ; d of memory cell 35 being pulled up to a voltage proportional to ( v g - v t ). the value of the voltage of the bitline 45 may be sensed , for example , using an analog to digital converter . applying the source voltage v s to memory cell 35 actually results in the functions of the &# 34 ; drain &# 34 ; and &# 34 ; source &# 34 ; of memory cell 35 reversing such that what was formerly the &# 34 ; drain &# 34 ; of memory cell 35 now operates as the &# 34 ; source &# 34 ; of memory cell 35 , and vice versa . the method and system shown in fig2 - 5 enables the actual cell threshold voltage vt of memory cell 35 to be sensed . many prior schemes sense the cell current i d and not the cell threshold voltage vt of a memory cell . the cell current i d is a function of many parameters that can lead to sources of variation in the cell current i d from memory cell to memory cell . when memory cell 35 is a flash memory cell , the cell threshold voltage vt determines the cell current i d . therefore , in order to reduce the variability of the sensed data stored in memory cells , it is preferable to sense the cell threshold voltage vt rather than the cell current i d . additionally , many of a flash memory cell &# 39 ; s parameters rely on the cell threshold voltage vt , not the cell current i d . for instance , the programming of a flash memory cell is directly proportional to the cell threshold voltage vt , not the cell current i d . in addition , disturb mechanisms ( charge loss and charge gain ) are related to the cell threshold voltage vt . therefore , it is preferable to sense the cell threshold voltage vt rather than the cell current i d . the scheme illustrated in fig2 - 5 does not require an active cell current i d , the use of a drain bias circuit , or a differential sense amplifier . therefore , substantially less power is required to sense data stored by memory cell 35 as opposed to prior memory cells ( e . g . memory cell 10 of fig1 ). the reduced power required to sense data stored in memory cell 35 enables more memory cells to be sensed or read in parallel than previous schemes would allow . for one embodiment , an entire wordline of memory cells ( e . g . 1024 ) may be sensed in parallel . according to the present embodiments , both the read voltage v g applied to the wordline 40 and the source voltage v s are selected in view of the operating characteristics of the memory cell 35 . specifically , for the example wherein memory cell 35 is a flash memory cell , the range of possible cell threshold voltages vt provides a programming window that may be subdivided into a number of distinct states . the number of states into which the programming window is divided determines the number of bits stored by the memory cell 35 . for example , if a programming window is subdivided into only two states , memory cell 35 is capable of storing only one bit of data . alternatively , if a programming window is subdivided into eight distinct states , memory cell 35 is capable of storing 3 bits of data . fig6 shows a programming window 50 as a function of the threshold voltage v t . as shown , a minimum threshold voltage v t , min defines a lower boundary of the programming window 50 , and a maximum threshold voltage v t , max defines an upper bound of the programming window 50 . the lower bound of programming window 50 is determined primarily by over - erased conditions of the flash memory cell , and the upper bound of programming window 50 is determined primarily by maximum programming voltages and cell disturbs . according to the present embodiments , the read voltage v g is selected to be greater than the maximum threshold voltage v t , max . the source voltage v s is selected to be equal to ( v t , max - v t , min ), which is the maximum possible swing of the bitline . when these constant voltages are applied to wordline 40 and the source s of a memory cell 35 , bitline 45 coupled to the drain d of memory cell 35 will eventually achieve a dc value proportional to ( v g - v t ). for one embodiment , the read voltage v g is approximately 5 . 5 volts and the source voltage v s is approximately 3 . 0 volts . fig7 shows one embodiment of a memory device 70 that includes a memory cell array 75 and periphery circuitry 80 . memory cell array 75 comprises a multiplicity of memory cells arranged in rows ( wordlines ) and columns ( bitlines ) such as those shown in fig8 . periphery circuitry 80 includes circuitry for reading and writing of data to the memory cell array 75 and an interface to the data bus 85 . periphery circuitry 80 is shown as including power supply inputs v cc and v ss , programming voltage v pp , control inputs ctl ( including chip enable , output enable , etc . ), address inputs addr , and an i / o path to data bus 85 . fig8 shows one embodiment of memory cell array 75 . depending upon the storage capacity of memory device 70 , memory cell array 75 may include several hundreds of bitlines and several hundreds of wordlines . fig8 shows a sub - section of memory cell array 75 that includes a plurality of memory cells 101 - 103 , all of which are coupled to wordline 100 , and another plurality of memory cells 111 - 113 , all of which are coupled to wordline 110 . bitline 120 is shown as being coupled to the drains of memory cells 101 and 111 , bitline 121 is shown as being coupled to the drains of memory cells 102 and 112 , bitline 122 is shown as being coupled to the drains of memory cells 103 and 113 . each of the memory cells 101 - 103 and 111 - 113 are shown as having their sources coupled to a source diffusion 130 that is coupled to a source strap 131 . additional bitlines , wordlines , source diffusions , source straps , and memory cells are implied by fig8 . memory cell array 75 of fig8 may be manipulated in the manner shown in fig2 - 5 by appropriately applying voltages to bitlines 120 - 122 , source straps 131 - 132 , and wordlines 100 and 110 . as may be seen , a voltage applied to a particular wordline will be applied to the select gates of all of the memory cells coupled to that wordline . for example , applying a voltage to wordline 100 will result in each of the memory cells 101 - 103 having that voltage applied to their select gates . as will be discussed with respect to fig1 , the manipulation of wordlines 100 and 110 , bitlines 120 - 122 , and source straps 131 - 132 may be done using conventional circuitry . fig9 summarizes a method for reading all of the memory cells coupled to a single wordline ( e . g . wordline 100 of fig8 ). the process begins at process block 150 typically in response to receiving a read request as decoded from the control signals of memory device 70 . at process block 155 , all bitlines of the memory cell array 75 are grounded , and the bitlines are floated at process block 160 . the actions of process blocks 155 and 160 may be performed concurrently with the decoding of an address by the row and column decoders of memory device 70 ( shown in fig1 ). given that all of the memory cells coupled to a wordline may be simultaneously sensed , the use of a column decoder may not be required . at process block 165 , the read voltage v g is applied to the selected wordline , and deselected wordlines are grounded to prevent the switching on of the memory cells attached to the deselected wordlines . again , the read voltage v g that is applied to the selected wordline is selected to be greater than the maximum threshold voltage v t , max obtainable by a memory cell of memory cell array 75 . at process block 170 , a source voltage v s is applied to all the sources of all the memory cells in memory array 75 by coupling the source voltage v s to the source straps of the memory cell array . for other layouts of memory cell array 75 , the source voltage v s may not necessarily be applied to all the sources of the memory cells ; however , the present scheme will work so long as all of the memory cells of the memory cell array 75 that are to be read have their sources set to the appropriate source voltage v s . a predetermined period of time is allowed to elapse so that the bitlines coupled to the selected memory cells are allowed to achieve a steady state voltage proportional to ( v g - v t ). each of bitlines 120 - 122 may have a different voltage as determined by the threshold voltages v t of each of memory cells 101 - 103 . at process block 175 bitline voltages for each of bitlines 120 - 122 of the memory cell array 75 are sensed . the bitlines may be sensed in parallel or subsets of the bitlines may be sensed sequentially . for example , given 1024 bitlines , the periphery circuitry 80 of the memory device 70 may be configured to sense the voltages of all the bitlines in parallel or to sense a subset of the bitlines at a time ( e . g . sixteen ). so long as the read voltage v g and the source voltage v s are applied to the memory cells of the selected wordline , the bitline voltages on bitlines 120 - 122 will maintain a dc value proportional to ( v g - v t ). providing sufficient time to allow bitlines 120 - 122 to achieve a dc voltage may require a longer period of time than normally required by prior art sensing schemes ; however , the fact that all of the memory cells of an entire wordline may be sensed in parallel allows the time to be amortized over all of the memory cells of a wordline such that the average time to access the data of each memory cell is significantly reduced over the prior art . under this scheme no drain bias circuit is required because no cell current is required . similarly , a differential sense amplifier is also not required . because , the value of the read voltage v g and the maximum swing of the threshold voltage v t are known , an analog to digital converter may be used to convert the voltage of a bitline into a digital value , therefore not requiring a sense amplifier . fig1 shows the periphery circuitry 80 of the memory device 70 for one embodiment . periphery circuitry 80 generally comprises voltage regulation circuitry 205 , voltage switches 210 , row and column decoders 215 , and sensing circuitry 220 . periphery circuitry 80 is also shown as including an optional control engine 200 that includes a read algorithm &# 34 ; r &# 34 ; 201 and a write algorithm &# 34 ; w &# 34 ; 202 that control engine 200 uses to control the periphery circuitry 80 for accessing the memory cell array 75 . control engine 200 may alternatively be provided externally to the memory device 70 . control engine 200 is coupled to receive the address and control signals such that it can appropriately control the voltage regulation circuitry 205 , voltage switches 210 , and the row and column decoders 215 . the voltage regulation circuitry 205 is coupled to receive the external supply voltages v cc , v pp , and v ss . typically , values of v cc and vpp are 5 volts and 12 volts , respectively . however , for some embodiments v cc and v pp may be the same voltage , ( e . g . 5 . 0 volts or 3 . 3 volts ). the voltage regulation circuitry 205 may include charge pumps , dc - to - dc converters , and / or voltage dividers for producing the read voltage v g and the source voltage v s . the voltage switches 210 are coupled to the voltage regulation circuitry 205 and to the wordlines , bitlines , and source straps of memory cell array 75 . voltage switches 210 selectively provides the desired voltages ( e . g . source voltage v s ) to the memory cell array in response to control signals provided by the control engine 200 . the row decoders of row and column decoders 215 are coupled to the voltage switches 210 for receiving the read voltage v g and supplying the read voltage v g to a wordline of memory cell array 75 indicated by the address transmitted received from the address lines addr . as previously mentioned , column decoders are optional and may be used merely to multiplex sensing circuitry 220 to sense specific subsets of bitlines 120 - 122 of the memory cell array 75 . if no column decoders are provided , sensing circuitry 220 will sense all of the bitlines of the memory cell array 75 in parallel . sensing circuitry 220 is shown as including analog to digital converter &# 34 ; adc &# 34 ; 221 that translates the voltages sensed at bitlines 120 - 122 to digital values . sensing circuitry 220 may include latches for storing the sensed voltages such that all of the voltages on bitlines 120 - 122 may be dumped into the latches and sequentially output in smaller subsets to data bus 85 . the memory device architecture shown in fig7 - 10 illustrate a nonvolatile memory device having a page mode read operation . if latches or another form of memory are provided in sensing circuitry 220 , an entire wordline of memory cells may be stored in a cache - like fashion wherein a wordline of data is fetched at a time from memory cell array 75 . subsequent accesses to memory cell array 75 are done entirely within a buffer memory of sensing circuitry 220 ( not shown ) using row and column decoders 215 . subsequent accesses will continue to be made to the buffer memory of sensing circuitry 220 instead of memory cell array 75 until data is attempted to be fetched from memory cell array 75 that is not stored in sensing circuitry 220 . in the foregoing specification the invention has been described with reference to specific exemplary embodiments thereof . it will , however , be evident that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention . the specification and drawings are , accordingly , to be regarded in an illustrative rather than restrictive sense .