the technical solution of the present invention will be described by referring to specific embodiments . in the following description , some specific details are provided in order to provide a detailed explanation to the embodiments of the present invention . however , one skilled in the art knows that the present invention can also be implemented without these details . further , there is no detailed description on the known structures relating to computers , processors and so on , in order to prevent from unnecessarily obscuring the description of the present invention &# 39 ; s embodiments . it should be noted that , the sections for performing predetermined processing in the following embodiments may be implemented in hardware and / or software . for example , a specific processing may be performed using software and / or firmware executed on one or more processing modules . in general , a system for performing processing may include a more generic processing module and memory . the processing module can be a single processing device or a plurality of processing devices . such a processing device may be a microprocessor , micro - controller , digital processor , microcomputer , a portion of the central processing unit , a state machine , logic circuitry , and / or any device that manipulates the signal . the memory may be a single memory device or a plurality of memory devices . such a memory device may be a read only memory , a random access memory , a floppy disk memory , magnetic tape memory , erasable memory , a portion of a system memory , and / or any device that stores operational instructions in a digital format . note that when the processing module implements one or more of its functions to be a state machine or logic circuitry , the memory storing in the corresponding operational instructions is embedded within the circuitry comprising the state machine and / or other logic circuitry . for example , such a system may be a circuit design tool having a compilable memory unit to facilitate implementation of memories as described herein . unless the context requires otherwise , throughout the specification and claims which follow , the word “ comprise ” and variations thereof , such as , “ comprises ” and “ comprising ” are to be construed in an open , inclusive sense , that is as “ including , but not limited to .” fig3 is a block diagram showing an example of general functional structure of a simulating system according to an embodiment of the present invention . as shown in fig3 , a simulating system 50 comprises a function simulator 10 ′, a cycle - accurate simulator 20 ′ and a synchronization control system 40 based on threads . fig4 is a flow chart showing general procedure of a simulation method according to an embodiment of the present invention . as shown in fig3 , the function simulator 10 ′ comprises a fetch module 11 , a decoding module 12 , an execution module 13 , a committing module 14 , a mmu 15 ′ and a memory hierarchy structure 16 . the fetch module 11 is used to fetch an instruction to be executed and provide the instruction to the decoding module 12 . the decoding module 12 understands the semantic of the obtained instruction and transmits it to the execution module 13 . the execution module 13 executes the decoded instruction according to its semantic and writes back the new value of the modified memory unit through the mmu 15 ′, or writes back the new value of the modified register through the committing module 14 . the committing module 14 writes back the new value of the modified register and updates a program counter in order to make the fetch module 11 to fetch the next instruction . mmu 15 ′ maps the target virtual memory space to the target physical memory space , and this is necessary for all the memory - related instructions . the memory hierarchy structure 16 simulates the memory hierarchy structure of the target system , for example , a dedicated l1 cache and a shared l2 cache , and maps the target physical space to the main memory space of the simulator . as compared to the prior art function simulator , the function simulator in the present invention &# 39 ; s embodiment comprises an access record extracting module for obtaining memory access records of instructions . in the following discussion about an example , the module is set in the mmu 15 ′. when the execution module 13 is executing the semantic of an instruction , if the semantic involves accessing the memory hierarchy structure 16 , the memory access is performed through the mmu 15 ′. in response to this , the access record extracting module associated with the mmu 15 ′ extracts information relating to the instruction , i . e ., the memory access record , including an identification of the cpu for executing the instruction , an identification of the instruction , and the address of the accessed memory location . according to the types of the hardware / software architectures and operation systems which the function simulator implementation is based on , various ways may be adopted to implement the function of the above access record extracting module . for example , in case of adopting windows operation system , it is possible to utilize the hook mechanism to intercept events resulted from the memory access by the mmu 15 ′, thus obtaining the information of the memory access records . this module may also be set outside the mmu 15 ′. as shown in fig4 , the method of the present invention begins at step s 1 , where the execution of a program is simulated by the function simulator 10 ′, and the memory access records are obtained by the access record extracting module . as shown in fig3 , the synchronization control system 40 based on threads comprises a thread generator 41 , a thread database 42 and a synchronizing device 43 . the synchronization control system 40 may be implemented based on a computer . as shown in fig4 , when the function simulator 10 ′ completes the simulated execution of the executable program , then at step s 2 , the thread generator 41 of the synchronization control system 40 obtains the memory access records extracted by the function simulator 10 ′. the transmission of memory access records between the synchronization control system 40 and the function simulator 10 ′ may be implemented through direct communication or intermediate storage . then at step s 3 , the thread generator 41 analyses the accumulated memory access records , wherein in view of the address of each accessed memory unit present in the memory access records , sets of instructions are found from the accumulated memory access records , where each set includes instructions involved the accesses from different processors to the same memory unit address . i . e ., for that address , it is determined whether the accumulated memory access records show that different processors have accesses the memory unit indicated by that address . if so , all the memory access records including said different processors and the address are found out , and the instructions identified by these memory access records form one of such sets . there are various possible variations of the method for finding such sets . then at step s 4 , the thread generator 41 stores the found sets in the thread database 42 . as shown in fig3 , the cycle - accurate simulator 20 ′ comprises several parallel simulation units 20 - 1 to 20 - n . each parallel simulation unit simulates one processor , and its work flow is similar to one serial cycle - accurate simulator . each parallel simulation unit maintains its own present simulation time . each parallel simulation unit comprises a fetching module 21 , a decoding module 22 , an issuing module 23 , a functional unit 24 , a writing back module 25 , a committing module 26 , a mmu 27 ′ and a memory hierarchical structure 28 . the fetching module 21 is used to fetch an instruction to be executed and provide the instruction to the decoding module 22 . the decoding module 22 understands the semantic of the obtained instruction and transmits it to the issuing module 23 . the issuing module 23 allocates a temporary register , i . e ., renamed register for the instruction , and allocates the register to a respective functional unit 24 . the functional unit 24 executes the instruction to be executed according to its semantic and writes back the new value of the modified memory unit through the mmu 27 ′, or writes back the new value of the modified register through the writing back module 25 and the committing module 26 . the writing back module 25 writes back the modified temporary register , i . e ., the new value of the renamed register . the committing module 26 writes back the new value of the modified register modified by the instruction and updates a program counter in order to make the fetching module 21 to fetch the next instruction . mmu 27 ′ maps the target virtual memory space to the target physical memory space , and this is necessary for all the memory - related instructions . the memory hierarchical structure 28 simulates the memory hierarchy structure of the target system , for example , a dedicated l1 cache and a shared l2 cache , and maps the target physical space to the main memory space of the present simulating unit . as compared to the execution module in the function simulator , the issuing modules , functional units and writing back modules in the parallel simulation units in the cycle - accurate simulator may be considered as a more complicated pipeline 30 . as shown in fig4 , after step s 4 , at step s 5 , the above executable program is executed by respective parallel simulation units of the cycle - accurate simulator 20 ′. fig5 is a flow chart specifically showing a control procedure of memory access synchronization in step s 5 of fig4 . as compared to the prior art parallel cycle - accurate simulator , the parallel simulation units of the cycle - accurate simulator 20 ′ according to the embodiment of the present invention may comprise a memory access control module . in the following discussion about an example , the module is implemented in the mmu 27 ′. as shown in fig5 , at step s 10 , the synchronizing device 43 obtains information for identifying the instruction causing access to the memory hierarchical structure 28 from the mmu 27 ′ ( i . e ., memory access control module ). when the functional unit 24 is executing the semantic of an instruction , if the semantic involves accessing the memory hierarchy structure 28 , the memory access is performed through the mmu 27 ′. in response to this , the information on the instruction , i . e ., the identification of the instruction is provided from the mmu 27 ′ by the memory access control module associated with the mmu 27 ′. according to the types of the hardware / software architectures and operation systems which the cycle - accurate simulator implementation is based on , various ways may be adopted to collect and provide the identification information on the instructions . for example , in case of adopting windows operation system , it is possible to utilize the hook mechanism to intercept events resulted from the memory access by the mmu 27 ′, thus obtaining the identification information of the instruction which the memory access is based on . this memory access control module may also be implemented outside the mmu 27 ′. alternatively , the above information for identifying instructions provided by the mmu 15 ′ and mmu 27 ′ may be based on instruction addresses in the executable program image . it should be noted that , the instruction identification information is provided to the synchronizing device 43 before the mmu 27 ′ actually performs the memory access . at this time , the memory access control module makes the actual memory access of the mmu 27 ′ being hung up , until the synchronizing device 43 completes synchronization processing at step s 11 . at step s 11 , when the synchronizing device 43 receives the instruction identification information from the mmu of a parallel simulation unit , compares it with the instruction identification information in respective sets stored in the thread database 42 , and if it matches with the instruction identification information in a set , identifies that the memory access to be performed by the mmu needs synchronization and performs synchronization control on the memory access . the synchronizing device 43 is in charge of maintaining a global simulation time of the parallel cycle - accurate simulator . the global simulation time equals to the minimum value among all the parallel simulation unit simulation times . the synchronizing device 43 may obtain the global simulation time by checking the present simulation times of all the parallel simulation units and finding the minimum value by comparison . as an example , when the synchronizing device 43 receives the instruction identification information from the mmu of a parallel simulation unit and determines that the execution of the corresponding instruction needs synchronization , the synchronizing device 43 firstly blocks the simulation work of the mmu for the present processor , waits for the virtual time of the processor to be equal to the global virtual time , and then notifies its mmu to resume the simulation . in the present parallel simulating system , the simulation work flow of the mmu is the same as that of the mmu in a serial simulator . thus the synchronizing device has a function of adjusting the occurrence times of the mmu &# 39 ; s simulation actions , but not altering the mmu &# 39 ; s internal mechanism . for example , assume that a parallel simulator has three parallel simulation units , processors p 0 , p 1 and p 2 . the simulation time of p 0 is 100 seconds , the simulation time of p 1 is 101 seconds , the simulation time of p 2 is 102 seconds , and then the present global simulation time is 100 seconds . assuming that the instructions executed by p 0 , p 1 and p 2 at this time are marked as needing synchronization in the thread database , their executions are hung up in the synchronizing device 43 . at this time , the synchronizing device 43 determines that p 1 and p 2 must wait because the simulation times of them are greater than the global simulation time , and p 0 may start its simulated actions by the mmu because its simulation time is equal to the global simulation time . assuming that the time is 103 seconds when p 0 completes its simulated action by the mmu , the global simulation time increases at 101 seconds and the synchronizing device 43 determines that p 1 may also start its simulated action by the mmu , and p 2 still needs waiting . further assuming that the time is 104 seconds when p 1 completes its simulated action by the mmu , the global simulation time becomes 102 seconds and the synchronizing device 43 determines that p 2 may also start its simulated action by the mmu . as an alternative way , when the mmu of a parallel simulation unit executes an instruction , the memory access control module firstly queries the thread database to see if the instruction needs synchronization . if its needs no synchronization , it is possible to directly perform the corresponding simulation operation by the mmu , and if otherwise , the memory access control module performs control so that the mmu of the parallel simulation unit autonomously blocks the execution of the instruction , and waits for its simulation time to be equal to the global simulation time so as to resume its corresponding operations . this manner is the so - called autonomous manner . in this situation , the synchronizing device only needs to maintaining the global simulation time , or the synchronizing device may be omitted , and the memory access control module of the mmu may autonomously obtain the global simulation time ( for example , taking the minimum value among the present simulation times of all the mmus as the global simulation time ). although the device for storing the sets is described as the thread database in the above , it is also possible to adopt other means known in the art for storing , and the storage function may be independent , or may also be integrated in the function simulator or cycle - accurate simulator . similarly , the thread generator may also be integrated in the function simulator , and the synchronizing device may be integrated in the cycle - accurate simulator . further , although in the above embodiments the function simulator , the cycle - accurate simulator and the synchronization control system are described as separated portions , one skilled in the art knows that they can be combined arbitrarily in specific implementations . although in the above embodiments the parallel simulation units are described as separated portions , they can be implemented by using centralized or distributed parallel computing techniques in specific implementations . in addition , communications between respective units in the above embodiments may adopt wired or wireless communication techniques such as bus , network , shared memory , dma , interruption , message , pipe , event , dedicated connection and so on . although the criteria for identifying the set are determined as access to the same memory address by different processors in the embodiments , it is possible to design other identifying criteria according to specific implementations . preferably , the identified sets should comprise at least one instruction that at least causes a write access . the above - disclosed subject matter is to be considered illustrative , and not restrictive , and the appended claims are intended to cover all such modifications , enhancements , and other embodiments that fall within the true spirit and scope of the present invention . thus , to the maximum extent allowed by law , the scope of the present invention is to be determined by the broadest permissible interpretation of the following claims and their equivalents , and shall not be restricted or limited by the foregoing detailed description .