the following is a detailed description of a preferred embodiment of the invention . note that the embodiment described below is not intended to unduly limit the content of the invention recited in the claims , and all of the constituent elements described in the embodiment are not necessarily essential as solutions provided by the invention . fig1 shows an example of a configuration of a circuit device . a circuit device 200 includes a bridge circuit 210 , a register unit 235 , a control circuit 240 , a delay unit 250 , and a pre - driver unit 260 . hereinafter , an example will be described in which the circuit device 200 is used in a motor driver apparatus , but the circuit device 200 of the present embodiment is applicable to any apparatus that drives an external circuit by using the bridge circuit 210 . the bridge circuit 210 is a circuit that outputs driving current to a motor 280 ( direct current motor ) via terminals out 1 and out 2 . to be specific , the bridge circuit 210 includes first to fourth transistors q 1 to q 4 configured as an h bridge , and diodes d 1 to d 4 that are respectively connected in parallel to the transistors q 1 to q 4 . the transistors q 1 and q 3 have source nodes connected to a node of power supply voltage vcc , and the transistors q 2 and q 4 have source nodes connected to a node of ground voltage . the transistors q 1 and q 2 have drain nodes connected to the terminal out 1 , and the transistors q 3 and q 4 have drain nodes connected to the terminal out 2 . the control circuit 240 is a circuit that controls the transistors q 1 to q 4 between on and off , and outputs first to fourth driving pulse signals s 1 to s 4 for controlling the transistors between on and off . fig2 a shows examples of waveforms of the driving pulse signals s 1 to s 4 . in this example , the driving pulse signals s 1 to s 4 are low active signals . in other words , during a charge period , the driving pulse signals s 1 and s 4 are at a low level , and the driving pulse signals s 2 and s 3 are at a high level . during the charge period , as shown in fig3 , the transistors q 1 and q 4 are turned on , and the transistors q 2 and q 3 are turned off , causing driving current id to flow from the power supply to the ground . on the other hand , during a decay period , the driving pulse signals s 1 and s 4 are at a high level , and the driving pulse signals s 2 and s 3 are at a low level . during this period , as shown in fig4 , the transistors q 1 and q 4 are turned off , and the transistors q 2 and q 3 are turned on , causing the driving current id to flow from the ground back to the power supply . as will be described later with reference to fig1 , the driving current id of the motor 280 increases during the charge period and decreases during the decay period . the control circuit 240 repeats these periods , and controls the driving current id ( i . e ., the number of revolutions of the motor ) by controlling the length of the periods . the delay unit 250 includes first to fourth delay circuits 251 to 254 that delay the driving pulse signals s 1 to s 4 . to be specific , the register unit 235 includes a delay setting register 237 in which first to fourth delay time information are variably set . the delay circuits 251 to 254 respectively delay the driving pulse signals s 1 to s 4 based on the first to fourth delay time information , and outputs delayed driving pulse signals sd 1 to sd 4 . the first to fourth delay time information may be any type of information as long as they are information regarding delay time . for example , in an embodiment that will be described later , a delay is caused by using a clock , and the number of clocks by which the delay is caused may be defined as the delay time information . alternatively , the delay time information may be a delay time itself , information obtained by encoding the delay time , or the like . the pre - driver unit 260 includes first to fourth pre - drivers 261 to 264 that drive the first to fourth transistors q 1 to q 4 . the pre - drivers 261 to 264 buffer the delayed driving pulse signals sd 1 to sd 4 , and output the buffered signals to the gates of the transistors q 1 to q 4 as driving signals g 1 to g 4 . a comparative example will now be described using a circuit device 200 that does not include the delay unit 250 . in this comparative example , the driving pulse signals s 1 to s 4 output from the control circuit 240 are buffered directly by the pre - drivers 261 to 264 , and then output as driving signals g 1 to g 4 . as shown in fig2 a , the driving pulse signals s 1 to s 4 have the same timing of switching between on and off . if these driving pulse signals are applied to the transistors q 1 to q 4 while maintaining the ideal timing , then , as shown in fig3 and 4 , the transistors q 1 and q 2 ( or q 3 and q 4 ) that are connected in series are turned on and off in a mutually exclusive manner . in this case , the through current flowing from the power supply voltage vcc to the ground voltage via the transistors q 1 and q 2 ( or q 3 and q 4 ) does not occur . however , the actual timing of switching between on and off of the transistors q 1 to q 4 is different from the timing of switching between on and off of the driving pulse signals s 1 to s 4 depending on , for example , the drive capability of the pre - drivers 261 to 264 , the gate size of the transistors q 1 to q 4 , the characteristics of the motor 280 serving as a load , and the like . fig2 shows examples of waveforms of the driving signals g 1 to g 4 according to the comparative example . in this example , the driving signals g 1 and g 3 that drive the high - side transistors q 1 and q 3 and the driving signals g 2 and g 4 that drive the low - side transistors q 2 and q 4 have different edge slopes ( rising time and falling time ). the edge slopes cause the timing of switching between on and off to be delayed , which causes a timing difference between the high - side transistors and the low - side transistors . as a result , a period tt occurs during which the transistors q 1 and q 2 ( or q 3 and q 4 ) are simultaneously on . during the period tt , the power supply and the ground are short circuited , and thus through current is generated . to address this , in the present embodiment , the delay circuits 251 to 254 delay the driving pulse signals s 1 to s 4 by first to fourth delay times td1 to td4 corresponding to the first to fourth delay time information set in the delay setting register 237 . fig5 shows examples of waveforms of driving pulse signals sd 1 to sd 4 that are output by the delay circuits 251 to 254 , and examples of waveforms of driving signals g 1 to g 4 that are output by the pre - drivers 261 to 264 based on the driving pulse signals sd 1 to sd 4 . as shown in fig5 , the delay circuits 251 to 254 delay the driving pulse signals s 1 to s 4 used to turn the transistors q 1 to q 4 from off to on by the delay times td1 to td4 . in the case of low active driving signals , falling edges at which the driving pulse signals drop from a high level to a low level are delayed . in other words , during transition from the charge period to the decay period , the falling edges of the driving pulse signals sd 2 and sd 3 are delayed with respect to the rising edges of the driving pulse signals sd 1 and sd 4 . on the other hand , during transition from the decay period to the charge period , the falling edges of the driving pulse signals sd 1 and sd 4 are delayed with respect to the rising edges of the driving pulse signals sd 2 and sd 3 . due to the delay of the driving pulse signals sd 1 to sd 4 , the timing of when , for example , the transistor q 2 is turned from off to on is delayed by the delay time td2 . by causing a delay in the timing of turning the transistor q 2 from off to on in this way , it is possible to turn on the transistor q 2 after the transistor q 1 has been turned off . in other words , a period is generated during which the transistors q 1 and q 2 connected in series are simultaneously turned off , and it is thereby possible to eliminate the period tt during which the transistors q 1 and q 2 are turned on simultaneously , which was described with reference to fig2 b , and avoid through current . next , a second comparative example will be described in which a fixed period is provided during which all of the transistors q 1 to q 4 are turned off . fig6 shows examples of waveforms according to the second comparative example . the driving pulse signals sd 1 to sd 4 are provided with a fixed period during which all of them are set to high levels . due to the fixed period , with the driving signals g 1 to g 4 , a period occurs during which the transistors q 1 to q 4 are all turned off . the actual timing of switching between on and off of the transistors q 1 to q 4 differs according to various factors described above . it is therefore necessary to set the fixed period during which all of the driving pulse signals sd 1 to sd 4 are set to high levels in consideration of the worst case caused by the timing difference . accordingly , a problem arises in that the period during which all of the transistors q 1 to q 4 are turned off increases to reduce the period during which they are turned on , resulting in , for example , reduction of power efficiency , torque reduction of the motor 280 , and the like . according to jp - a - 2008 - 289143 mentioned above , the timing of switching between on and off of the transistors is controlled based on the result obtained by monitoring the driving signals , and thus the dead time is not fixed . however , because the timing of switching between on and off of the transistors cannot be set freely , the dead time cannot be optimized . in contrast , according to the present embodiment , the delay times td1 to td4 corresponding to the transistors q 1 to q 4 can be independently adjusted by the delay setting register 237 . for example , a configuration is possible in which the circuit device 200 and the motor 280 are combined at the time of manufacturing , minimum delay times td1 to td4 that do not generate through current are measured , and delay time information corresponding to the minimum delay times td1 to td4 are set in the delay setting register 237 . this operation may be performed by the user . with this configuration , the minimum required delay times td1 to td4 can be set , and thus the optimal dead time is set , and the reduction of power efficiency , the torque reduction of the motor 280 , and the like can be suppressed . it is basically sufficient to not simultaneously turn on the transistors q 1 and q 2 ( or q 3 and q 4 ) that are connected in series , and it is therefore unnecessary to simultaneously turn off all of the transistors q 1 to q 4 . in the present embodiment , for example , the delay times td2 and td3 of the driving signals g 2 and g 3 shown in fig5 can be individually adjusted , and thus the relationship between the transistors q 1 and q 2 , and the relationship between the transistors q 3 and q 4 can be individually adjusted . in other words , because the present embodiment does not have a requirement that all of the transistors are turned off simultaneously , the dead time can be reduced as much as possible to increase the time period during which the transistors are turned on . in the embodiment given above , an example was described in which the bridge circuit 210 is constituted by the first to fourth transistors q 1 to q 4 ( h bridge ), but it is sufficient that the bridge circuit 210 is constituted by first to n - th transistors ( where n is 2 or greater ). for example , the bridge circuit 210 may be constituted by a half bridge . in this case , for example , the bridge circuit 210 is constituted by the transistors q 1 and q 2 , and the terminal out 2 is connected to the ground voltage . next is a description of a method for setting the delay times td1 to td4 in the bridge circuit 210 having a specific configuration . in the bridge circuit 210 according to the configuration example shown in fig1 , the high - side transistors q 1 and q 3 are p - type transistors , and the low - side transistors q 2 and q 4 are n - type transistors . as used herein , the high - side transistors refer to transistors that are connected to a higher potential power supply side than the low - side transistors , and the low - side transistors refer to transistors that are connected to a lower potential power supply side than the high - side transistors . the bridge circuit 210 is operated by high power supply voltage vcc ( for example , 42 v ). on the other hand , the control circuit 240 and the delay unit 250 are operated by low power supply voltage ( for example , 5 v ). accordingly , the pre - drivers 261 to 264 are constituted by level shifters that convert the signal levels of the driving pulse signals sd 1 to sd 4 . because the high - side transistors are p - type transistors , and the low - side transistors are n - type transistors , the pre - drivers 261 and 263 output input signals ( sd 1 and sd 3 ) by using a non - inverse logic , and the pre - drivers 262 and 264 output input signals ( sd 2 and sd 4 ) by using an inverse logic . with the configuration described above , as shown in fig5 , it is possible to supply low active driving signals g 1 and g 3 to the p - type transistors q 1 and q 3 , and high active driving signals g 2 and g 4 to the n - type transistors q 2 and q 4 . at the same time , the driving pulse signals sd 1 to sd 4 are uniformly set to be low active , and thus the delay circuits 251 to 254 can have the same circuit configuration . this enables simplification of the design of , for example , the delay circuits 251 to 254 . the configuration of the delay circuits 251 to 254 will be described later in detail . as shown in fig5 , in the delay setting register 237 , first delay time information and second delay time information are set such that the second delay time td2 used to turn the low - side n - type transistor q 2 from off to on is longer than the first delay time td1 used to turn the high - side p - type transistor q 1 from off to on ( i . e ., td2 & gt ; td1 ). this will be described with reference to fig7 a to 8b . fig7 a and 7b show examples of waveforms in the high - side p - type transistor q 1 . the examples of waveforms shown in fig7 a and 7b were obtained by connecting a resistive element serving as a load between the ground and the terminal out 1 , and measuring the driving pulse signal sd 1 and the voltage of the terminal out 1 . fig8 a and 8b show examples of waveforms in the low - side n - type transistor q 2 . the examples of waveforms shown in fig8 a and 8b were obtained by connecting a resistive element serving as a load between the power supply and the terminal out 1 , and measuring the driving pulse signal s 22 and the voltage of the terminal out 1 . the p - type transistor q 3 and the n - type transistor q 4 also have similar waveforms . the time ( trp ) it takes from the falling edge of the driving pulse signal sd 1 to the rising edge of the output of the p - type transistor q 1 ( i . e ., when the transistor is turned on ) is 744 nanoseconds ( trp = 744 ns ), and the time ( tfp ) it takes from the rising edge of the driving pulse signal sd 1 to the falling edge of the output of the p - type transistor q 1 ( i . e ., when the transistor is turned off ) is 688 nanoseconds ( tfp = 688 ns ). also , the time ( tfn ) it takes from the failing edge of the driving pulse signal sd 2 to the falling edge of the output of the n - type transistor q 2 ( i . e ., when the transistor is turned on ) is 464 nanoseconds ( tfn = 464 ns ), and the time ( trn ) it takes from the rising edge of the driving pulse signal sd 2 to the rising edge of the output of the n - type transistor q 2 ( i . e ., when the transistor is turned off ) is 688 nanoseconds ( trn = 688 ns ). the above - described rising and falling times have the following relationship : trp & gt ; trn , and tfp & gt ; tfn . in the bridge circuit 210 , the on resistance of the transistors q 1 to q 4 affects the power efficiency , and it is therefore desirable to increase the transistor size and reduce the on resistance . generally , p - type transistors have a higher on resistance than n - type transistors , and thus trp & gt ; trn and tfp & gt ; tfn . as shown in fig5 , during transition from the decay period to the charge period , due to trp & gt ; trn , the time ( trp ) it takes for the transistor q 1 to switch from off to on is longer than the time ( trn ) it takes for the transistor q 2 to switch from on to off . in other words , the possibility that the transistors are turned on simultaneously is low even if the delay time is not provided . in this case , the delay time td1 may be set to , for example , zero , or may be set to a small value just to be sure . on the other hand , during transition from the charge period to the decay period , due to tfp & gt ; tfn , the time ( tfn ) it takes for the transistor q 2 to switch from off to on is shorter than the time ( tfp ) it takes for the transistor q 1 to switch from on to off . in other words , the possibility that the transistors are turned on simultaneously is high unless the delay time is provided . for this reason , it is necessary to set the delay time td2 so as to be longer than the delay time td1 . by setting the delay times td1 and td2 in the manner described above , it is possible to set appropriate delay times td1 and td2 in the bridge circuit 210 including p - type transistors as high - side transistors and n - type transistors as low - side transistors . in other words , the delay times td1 and td2 can be individually set in a programmable manner , and thus the minimum required dead time that can avoid through current can be achieved in the bridge circuit 210 having the above - described specific configuration . although the foregoing has been described by using the transistors q 1 and q 2 , the same applies to the transistors q 3 and q 4 . to be specific , in the delay setting register 237 , third delay time information and fourth delay time information are set such that the fourth delay time td4 used to turn the low - side n - type transistor q 4 from off to on is longer than the third delay time td3 used to turn the high - side p - type transistor q 3 from off to on ( i . e ., td4 & gt ; td3 ). for example , it is assumed that td3 = td1 , and td4 = td2 . the only difference between the transistors q 1 and q 2 and the transistors q 3 and q 4 is that the charge period and the decay period are replaced with each other , and thus the description given above by taking the transistors q 1 and q 2 as an example is equally applicable to the transistors q 3 and q 4 . next is a detailed description of the delay circuits 251 to 254 . in the delay setting register 237 , first to fourth numbers of clocks are set as the first to fourth delay time information . in other words , time periods corresponding to the first to fourth numbers of clocks are the delay times td1 to td4 . the delay circuits 251 to 254 delay the driving pulse signals s 1 to s 4 used to turn the transistors q 1 to q 4 from off to on by the first to fourth numbers of clocks set in the delay setting register 237 , and output the delayed driving pulse signals sd 1 to sd 4 . the clock signals used to cause delays may be , for example , system clock signals supplied from an external host controller , or clock signals generated by a clock generation circuit provided in the circuit device 200 . with this configuration , the delay times td1 to td4 can be defined by the number of clocks , and thus delay times td1 to td4 can be consistently set , and the minimum dead time can be accurately set . also , it is only necessary to delay the edges of the driving pulse signals s 1 to s 4 , and thus the configuration of the delay circuits can be simplified as compared to the configuration that requires , for example , additional edges to be provided before the edges of input signals . fig9 shows a detailed configuration example of the delay circuit 251 . fig1 shows a timing chart in the delay circuit 251 according to the detailed configuration example . the following will be described by taking the first delay circuit 251 as the i - th delay circuit ( where i is a natural number less than or equal to 4 ), but the second to fourth delay circuits 252 to 254 can also have the same configuration . the delay circuit 251 includes first to fourth flip - flop circuits ff 1 to ff 4 ( first to k - th flip - flop circuits in a broad sense ), a selector sell , and an or circuit or 1 ( logic circuit in a broad sense ). the flip - flop circuits ff 1 to ff 4 are cascade - connected , and a clock signal clk is input into the flip - flop circuits ff 1 to ff 4 . to be specific , a driving pulse signal s 1 is input into the flip - flop circuit ff 1 . as shown in fig1 , the flip - flop circuit ff 1 outputs a delayed pulse signal qf 1 obtained by delaying the driving pulse signal s 1 by one cycle ( one period ) of the clock signal clk . the delayed pulse signal qf 1 is input into the flip - flop circuit ff 2 . as shown in fig1 , the flip - flop circuit ff 2 outputs a delayed pulse signal qf 2 obtained by further delaying the delayed pulse signal qf 1 by one cycle of the clock signal clk . after that , the flip - flop circuits ff 3 and ff 4 are also cascade - connected in the same manner . in this way , the flip - flop circuits ff 1 to ff 4 output the delayed pulse signals qf 1 to qf 4 obtained by delaying the driving pulse signal s 1 by one to four cycles , respectively . the delayed pulse signals qf 1 to qf 4 and a select signal sel are input into the selector sel 1 the select signal sel is the first delay time information set in the delay setting register 237 , and is the number of clocks corresponding to the first delay time td1 . as shown in fig1 , it is assumed that , for example , sel = 3 is set as the number of clocks . in this case , the selector sel 1 selects the delayed pulse signal qf 3 , and outputs the selected signal as a signal qs 1 . the driving pulse signal s 1 and the signal qs 1 are input into the or circuit or 1 , and the or circuit or 1 logically ors these signals , and outputs the resultant as a delayed driving pulse signal sd 1 . at this time , the or circuit or 1 outputs an edge of the delayed pulse signal qs 1 selected by the selector sel 1 as an edge used to turn the transistor q 1 from off to on . to be specific , as shown in fig1 , when the driving pulse signal s 1 drops from a high level to a low level , the driving pulse signal sd 1 drops from a high level to a low level at the timing at which the signal qs 1 drops from a high level to a low level . when , on the other hand , the driving pulse signal s 1 rises from a low level to a high level , the driving pulse signal sd 1 rises from a low level to a high level at the timing at which the driving pulse signal s 1 rises from a low level to a high level . in this way , the falling edge of the driving pulse signal sd 1 is delayed in the same manner as the signal qs 1 , but the rising edge of the same is not delayed . by configuring the delay circuits 251 to 254 in the manner described above , the first to fourth driving pulse signals s 1 to s 4 used to turn the transistors q 1 to q 4 from off to on can be delayed by the first to fourth numbers of clocks set in the delay setting register 237 . in other words , any one of the delayed pulse signals qf 1 to qf 4 can be selected individually for each delay circuit by the selector sel 1 according to the number of clocks . then , only the falling edges of the selected signal qs 1 can be reflected in the driving pulse signals sd 1 to sd 4 by the or circuit or 1 . the above embodiment has been described by taking , as an example , the case where the driving pulse signals s 1 to s 4 and the driving pulse signals sd 1 to sd 4 are low active signals , but these signals may be high active signals . in this case , for example , the or circuits or 1 of the delay circuits 251 to 254 are replaced by and circuits , the pre - drivers 261 and 263 are constituted by inverse logic level shifters , and the pre - drivers 262 and 264 are constituted by non - inverse logic level shifters . fig1 shows a detailed configuration example of the circuit device 200 . fig1 is a diagram illustrating an operation performed by the circuit device 200 according to the detailed configuration example . the circuit device 200 shown in fig1 includes the bridge circuit 210 , a comparator 221 ( detection circuit ), a reference voltage generation circuit 230 , the register unit 235 , the control circuit 240 , the delay unit 250 , the pre - driver unit 260 , and a clock generation circuit 270 . the constituent elements that are the same as those described above are given the same reference numerals , and a description thereof is not given here . the clock generation circuit 270 generates a clock signal clk , and supplies the clock signal clk to each unit of the circuit device 200 . the delay circuits 251 to 254 receive the clock signal clk , and generate delayed driving pulse signals sd 1 to sd 4 . in the bridge circuit 210 , the source nodes of the low - side transistors q 2 and q 4 are connected to a node n 1 that is connected to a terminal rnf . one end of a sense resistor 290 is connected to the terminal rnf . the other end of the sense resistor 290 is connected to the node of the ground voltage . the register unit 235 includes the aforementioned delay setting register 237 , a period setting register 236 in which the length of the decay period is set , and an upper limit setting register 238 in which the upper limit of the charge current ( driving current id ) is set . a register value is variably written in the register unit 235 by , for example , a host controller ( for example , cpu ), and thereby the host controller controls the number of revolutions , torque and the like of the motor 280 . the reference voltage generation circuit 230 generates a reference voltage vr for detecting the upper limit imax of the charge current . to be specific , the reference voltage generation circuit 230 is constituted by a d / a conversion circuit . the d / a conversion circuit generates a plurality of voltages based on a reference voltage vref , selects a voltage corresponding to the register value set in the upper limit setting register 238 from among the plurality of voltages , and outputs the selected voltage as the reference voltage vr . the comparator 221 detects the charge current during the charge period by detecting a voltage vs of the node n 1 . as shown in fig3 , the driving current id flows from the power supply voltage vcc to the transistor q 1 , the motor 280 and the transistor q 4 . in the configuration example shown in fig1 , the driving current id further flows through the sense resistor 290 to the ground voltage . the driving current id during this charge period is called “ charge current ”. as shown in fig1 , during a charge period tc , the charge current increases , and the voltage vs of the node n 1 rises along with the increase of the charge current . the comparator 221 detects that the charge current has reached the upper limit imax by detecting that the voltage vs has reached the reference voltage vr . the control circuit 240 switches from the charge period tc to a decay period td if the comparator 221 detects the upper limit imax of the charge current during the charge period tc . the driving current id during the decay period td is called “ decay current ”, and as shown in fig1 , the decay current decreases during the decay period td . after the decay period set in the period setting register 236 elapses after switching to the decay period td by the control circuit 240 , the control circuit 240 switches from the decay period id to the charge period tc . in this way , the charge period tc and the decay period td are repeated , and the driving current id of the motor 280 is controlled such that the upper limit does not exceed imax . fig1 shows an example of a configuration of an electronic device in which the circuit device 200 of the present embodiment is used . the electronic device includes a processing unit 300 , a storage unit 310 , an operation unit 320 , an input / output unit 330 , the circuit device 200 , a bus 340 that connects these units , and the motor 280 . the circuit device 200 can be implemented by , for example , an integrated circuit device . the following will be described using , as an example , a printer in which its head and paper feed are controlled by motor driving , but the present embodiment is not limited thereto , and is applicable to any type of electronic devices . the input / output unit 330 can be , for example , a use connector , or an interface such as a wireless lan , and receives input of image data and document data . the input data is stored in the storage unit 310 , which is , for example , an internal storage device such as a dram . upon receiving a print instruction via the operation unit 320 , the processing unit 300 starts an operation to print the data stored in the storage unit 310 . the processing unit 300 sends an instruction according to the print layout of the data to the circuit device 200 , and the circuit device 200 rotates the motor 280 based on the instruction so as to move the head or feed paper . while the present embodiment has been described in detail above , it will be readily understood by those skilled in the art that numerous modifications are possible without substantially departing from the novel features and advantageous effects of the invention . accordingly , all such modifications also fall within the scope of the invention . for example , a term used with a broader or similar but different term at least once in the specification or the drawings can be replaced by the different term in anywhere in the specification or the drawings . all combinations of the present embodiment and variations also fall within the scope of the invention . also , the configurations and operations of the delay circuits , the bridge circuit , the circuit device and the electronic device , the method for setting the delay times , the method for controlling the bridge circuit , and the like are not limited to those described in the present embodiment , and various other modifications are possible . the entire disclosure of japanese patent application no . 2013 - 208887 , filed oct . 4 , 2013 is expressly incorporated by reference herein .