the present invention is directed to a folded r - 2r ladder current steering digital - to - analog converter . detailed steps and constituents are given below to assist in the understanding the present invention . obviously , the implementations of the present invention are not limited to the specific details known by those skilled in the art . on the other hand , well - known steps or constituents are not described in details in order not to unnecessarily limit the present invention . detailed embodiments of the present invention will be provided as follow . however , apart from these detailed descriptions , the present invention may be generally applied to other embodiments , and the scope of the present invention is thus limited only by the appended claims . a folded r - 2r ladder current steering digital - to - analog converter according to a first embodiment of the present invention is shown in fig2 , which employs n / 2 first weighted current sources and n / 2 second weighted current sources to convert n - bit digital information into an analog output . the current steering digital - to - analog converter includes n / 2 - bit most - significant - bit group to control the n / 2 first weighted current source , respectively . the current steering digital - to - analog converter further includes n / 2 - bit lower — significant - bit group to control the n / 2 second weighted current source , respectively . the current steering digital - to - analog converter also includes a r - 2r ladder . the folded r - 2r ladder of the present invention implies that the first weighted current source and the second weighted current source can simultaneously flow into the r - 2r ladder , such that each node in the r - 2r ladder includes a first weighed current source and a second weighted current source . the difference between the folded r - 2r ladder digital - to - analog converter of the present invention and a conventional r - 2r ladder digital - to - analog converter in structure is that more than one differently weighted input currents correspond to a r - 2r set . if a r - 2r set has two input current sources : the first weighted current source and the second weighted current source , then there is h times different in weights between them , wherein in this way , there is a 2 m difference between the groups of current sources controlled by the lower - significant - bit group ( d 0 , d 1 , . . . , d m − 1 ) and the most - significant - bit group ( d m , . . . , d n − 1 ) in the same r - 2r ladder network , which enables the operation of the current - steering digital - to - analog converter . in the case that the current - steering digital - to - analog converter has two input current sources in each node of the r - 2r ladder network , the output voltage can be given as : accordingly , compared to the conventional r - 2r ladder current - steering digital - to - analog converter which provides only one input current source per r - 2r set , the folded r - 2r ladder current - steering digital - to - analog converter is able to reduce the number of passive components by half , as well as the power consumption . if there are two input current sources in each node , m equals to n / 2 ; if three input current sources are in each node , m equals to n / 3 ; if four input current sources are in each node , m equals to n / 4 , and so on . in other words , for two adjacent current sources sequentially arranged in the same r - 2r set , there is a m bit ( s ) difference between signals them , and the inner current values thereof differ by 2 m times . referring to fig2 , the first embodiment of the present invention is a folded r - 2r current - steering digital - to - analog converter , including an end current - steering circuit 30 and a plurality of sequentially arranged r - 2r current - steering circuits 40 . the end current - steering circuit 30 includes : a first electrical contact c 1 ; a first two - ended circuit element r 1 ; a second electrical contact c 2 and a plurality of current sources a . the two ends of the first two - ended circuit element r 1 electrically couple between the first contact c 1 and the second contact c 2 . the resistance of the first two - ended circuit element r 1 between the first contact c 1 and the second contact c 2 is a first resistance value . additionally , each current source has a switching element s electrically coupled to the second contact c 2 , wherein the switching element s controls the current flowing / not flowing through current source a by turning on / off , respectively . each of the r - 2r current - steering circuits includes : a first contact c 1 , all first contacts are electrically coupled together ( in parallel ); a first two - ended circuit element r 1 ; a second contact c 2 ; a second two - ended circuit element r 2 ; a third contact c 3 , wherein the two ends of the second two - ended circuit element r 2 are electrically coupled between the second contact c 2 and the third contact c 3 ; and a plurality of current sources a . the resistance of the second two - ended circuit element r 2 between the second contact c 2 and the third contact c 3 is a second resistance value . in the r - 2r current - steering circuit , the first resistance value is two times the second resistance value . the first resistance value in a r - 2r current - steering circuit is two times the first resistance value in the end current - steering circuit . prior to arranging with the end current - steering circuit 30 , the plurality of sequential r - 2r current - steering circuits 40 form a sequential r - 2r circuit network , wherein the third contact c 3 of each current - steering circuit electrically couples to the second contact c 2 of the following current - steering circuit . the switching element s in each current - steering circuit electrically couples to an input signal ( e . g . one of d 0 , d 1 , . . . , d m − 1 , d m , d m + 1 , . . . , d n − 1 ), respectively , and are switched according to the bit input signals . these bit input signals constitute a plurality - bit binary input value . thus , the voltage value outputted at the second contact c 2 of the first current - steering circuit is an analog output value converted according to the binary input value . for any arbitrary two current - steering circuits above , for example , the first and second current - steering circuits , the above bit input signals include : a first bit input signal providing a binary value of a first bit to the switch s of a first current source , when the switch s of the first current source is turned on , the inner current of the first current source is a first current value , wherein the first current source resides in the first current - steering circuit ; a second bit input signal providing a binary value of a second bit to the switch s of a second current source , when the switch s of the second current source is turned on , the inner current of the second current source is a second current value , wherein the second current source resides in the first current - steering circuit ; a third bit input signal providing a binary value of a third bit to the switch s of a third current source , when the switch s of the third current source is turned on , the inner current of the third current source is a third current value , wherein the third current source resides in the second current - steering circuit ; and a fourth bit input signal providing a binary value of a fourth bit to the switch s of a fourth current source , when the switch s of the fourth current source is turned on , the inner current of the fourth current source is a fourth current value , wherein the fourth current source resides in the second current - steering circuit . in other words , the first and second current sources can be arbitrary two current sources in the first current - steering circuit , and the third and fourth current sources can be two current sources in the second current - steering circuit corresponding to the first and second current sources . thus , there can be additional current source ( s ) electrically coupled ( either at the front or back ) to the same contact c 2 of the above two current sources . accordingly , in a preferred embodiment of the present invention , the first current value is equal to the third current value ; the second current value equals to the fourth current value ; and the first and second current - steering circuits are adjacent circuits arranged next to each other . thus , the first bit and third bit can be two adjacent bits in a binary input value , while the second bit and fourth bit can be two adjacent bits in the binary input value . thus , the first bit and the second bit can be the first bit position and the second bit position in the binary input value , respectively . the distance between the first bit position and the second bit position is offset by m . moreover , the first current value is 2 m times the second current value . as mentioned before , additional current sources can be electrically coupled to , at the front / back , the same second contact c 2 of the above two current sources . in a preferred embodiment of the present invention , the plurality of bit input signals further include : a fifth bit input signal providing a binary value of a fifth bit to the switch s of a fifth current source , when the switch s of the fifth current source is turned on , the inner current of the fifth current source is a fifth current value , wherein the fifth current source resides in the first current - steering circuit . the fifth bit is a third bit position in the binary input value . the distance between the first bit position and the third bit position is offset by m . moreover , the fifth current value is 2 m times the second current value . conversely , the plurality of bit input signals further include : a sixth bit input signal providing a binary value of a sixth bit to the switch s of a sixth current source , when the switch s of the sixth current source is turned on , the inner current of the sixth current source is a sixth current value , wherein the sixth current source also resides in the first current - steering circuit . the sixth bit is a fourth bit position in the binary input value . the distance between the second bit position and the fourth bit position is offset by m . moreover , the second current value is 2 m times the sixth current value . a second embodiment of the present invention is a virtual binary folded r - 2r current - steering digital - to - analog converter . as shown in fig3 , the circuit uses the “ folded ” concept as the basis for the inventive circuit herein , that is , one set of the r - 2r ladder network has more than one differently weighted input current sources . however , the difference between the first and the second embodiments is in the way the inputs bits are arranged and the current weighted values . in the virtual binary folded r - 2r current - steering digital - to - analog converter , the highest weighted bit is arranged in the r - 2r set closest to the output end ; the second highest weighted bit is arranged also in the same r - 2r set ; and the third and fourth highest weighted value are arranged in the second r - 2r set . the bits are arranged in this way from the highest to the lowest weighted value . as known from prior r - 2r ladder current - steering digital - to - analog converter , it exhibits binary characteristic as long as the current sources in two adjacent r - 2r sets have the same weight . thus , it can be understood that in the virtual binary folded r - 2r current - steering digital - to - analog converter , current sources in adjacent r - 2r sets must have the same weight , while the current source of a different weighted bit in the same r - 2r set must obviously have a two - bit weight in order to exhibit the binary characteristic . in other words , each of the two adjacent r - 2r sets will have a current source with the same weight and another with a different weight . in addition , more than two differently weighted current sources can be inputted into the same r - 2r set . referring to fig3 , the second embodiment of the present invention is a folded r - 2r current - steering digital - to - analog converter , including an end current - steering circuit 50 and a plurality of sequentially arranged r - 2r current - steering circuits 60 . the end current - steering circuit 50 includes : a first electrical contact c 1 ; a first two - ended circuit element r 1 ; a second electrical contact c 2 and a plurality of current sources a . the two ends of the first two - ended circuit element r 1 electrically couple between the first contact c 1 and the second contact c 2 . the resistance of the first two - ended circuit element r 1 between the first contact c 1 and the second contact c 2 is a first resistance value . additionally , each current source has a switching element s electrically coupled to the second contact c 2 , wherein the switching element s controls the current flowing / not flowing through current source a by turning on / off , respectively . each of the r - 2r current - steering circuits 60 includes : a first contact c 1 , all first contacts are electrically coupled together ( in parallel ); a first two - ended circuit element r 1 ; a second contact c 2 ; a second two - ended circuit element r 2 ; a third contact c 3 , wherein the two ends of the second two - ended circuit element r 2 are electrically coupled between the second contact c 2 and the third contact c 3 ; and a plurality of current sources a . the resistance of the second two - ended circuit element r 2 between the second contact c 2 and the third contact c 3 is a second resistance value . in the r - 2r current - steering circuit , the first resistance value is two times the second resistance value . the first resistance value in a r - 2r current - steering circuit is two times the first resistance value in the end current - steering circuit . furthermore , each current - steering circuit and its following current - steering circuit respectively has a current source with the same weight , and each current - steering circuit has at least one current source a with a weight different from any of the weights of all the current sources a in the following current - steering circuit . prior to arranging with the end current - steering circuit 50 , the plurality of sequential r - 2r current - steering circuits 60 form a sequential r - 2r circuit network , wherein the third contact c 3 of each current - steering circuit electrically couples to the second contact c 2 of the following current - steering circuit . the switching element s in each current - steering circuit electrically couples to an input signal ( e . g . one of d 0 , d 1 , . . . , d n − 2 , d n − 1 ), respectively , and are switched according to the bit input signals . these bit input signals constitute a plurality - bit binary input value . thus , the voltage value outputted at the second contact c 2 of the first current - steering circuit is an analog output value converted according to the binary input value . in a preferred embodiment of the present invention , referring to fig2 and 3 , the plurality of current - steering circuits are arranged from left to right ; the first current - steering circuit is the lest most current - steering circuit . for any arbitrary two current - steering circuits above , for example , the first and second current - steering circuits , the above bit input signals include : a first bit input signal providing a binary value of a first bit to the switch s of a first current source , when the switch s of the first current source is turned on , the inner current of the first current source is a first current value , wherein the first current source resides in the first current - steering circuit ; a second bit input signal providing a binary value of a second bit to the switch s of a second current source , when the switch s of the second current source is turned on , the inner current of the second current source is a second current value , wherein the second current source resides in the first current - steering circuit ; a third bit input signal providing a binary value of a third bit to the switch s of a third current source , when the switch s of the third current source is turned on , the inner current of the third current source is a third current value , wherein the third current source resides in the second current - steering circuit ; and a fourth bit input signal providing a binary value of a fourth bit to the switch s of a fourth current source , when the switch s of the fourth current source is turned on , the inner current of the fourth current source is a fourth current value , wherein the fourth current source resides in the second current - steering circuit . in other words , the first and second current sources can be any arbitrary two current sources in the first current - steering circuit , and the third and fourth current sources can be two current sources in the second current - steering circuit corresponding to the first and second current sources . thus , there can be additional current source ( s ) electrically coupled ( either at the front or back ) to the same contact c 2 of the above two current sources . the second current value is the same as the third current value ; while the first and fourth current values are different from the second and third current values . the first and second current - steering circuits are two current - steering circuits arranged next to each other . moreover , the first , second , third and fourth bits are four consecutive bits in the binary input value . the first current value is two times the second current value and the third current value is two times the fourth current value . in other words , the main difference between the first and second embodiments of the present invention is that , in the second embodiment , the switches receive consecutive bits of a binary input value are disposed consecutively ; whereas in the first embodiment , the switches receiving two consecutive bits are interlaced . as such , the inner currents of the corresponding current sources are different . furthermore , if the second current - steering circuit is the end current - steering circuit , and the second current value is the smallest among the inner currents of all the current sources , the fourth bit is the least significant bit of the binary input value . in addition , if the first bit is the most significant bit of the binary input value , then the second contact c 2 of the first current - steering circuit outputs an output signal , which is an analog output signal converted from the binary input value , wherein the first current value is the largest of all . in addition , the first and second two - ended circuit elements can be of any circuit forms that provide impedance . in a preferred embodiment of the present invention , the first and second two - ended circuit elements are resistors or capacitors . the foregoing description is not intended to be exhaustive or to limit the invention to the precise forms disclosed . obvious modifications or variations are possible in light of the above teachings . in this regard , the embodiment or embodiments discussed were chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated . all such modifications and variations are within the scope of the inventions as determined by the appended claims when interpreted in accordance with the breath to which they are fairly and legally entitled . it is understood that several modifications , changes , and substitutions are intended in the foregoing disclosure and in some instances some features of the invention will be employed without a corresponding use of other features . accordingly , it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention .