in accordance with features of the invention , the sense amplifier of an efuse is effectively tested without having to blow the efuse . electronic fuses or efuses use a sense amplifier to determine if the efuse is a logical “ 0 ” or logical “ 1 ”. the fuse stores information by electrically changing the resistance of a polysilicon resistor . the testing of the present invention effectively tests the states of the sense amplifier that result from both the blown and not blown conditions of the efuse . having reference now to the drawings , in fig1 , there is shown an exemplary sense amplifier generally designated by the reference character 100 for implementing efuse sense amplifier testing in accordance with the preferred embodiment . sense amplifier 100 is used for an electronic fuse , or efuse 102 to determine if the fuse 102 is a logical “ 0 ” or logical “ 1 ”. the fuse 102 stores information by electrically changing the resistance of a polysilicon resistor . sense amplifier 100 includes true and complement sensing nodes respectively labeled s_t and s_c . a first precharge p - channel field effect transistor ( pfet ) 104 is connected between a positive voltage supply rail vdd and the true sensing node s_t that is connected via a pair of series connected n - channel field effect transistor ( nfets ) 106 , 108 to the efuse 102 . a second precharge p - channel field effect transistor ( pfet ) 110 is connected between the positive voltage supply rail vdd and the complement sensing node s_c that is connected via a pair of series connected n - channel field effect transistor ( nfets ) 112 , 114 to a reference resistor 116 . sense amplifier 100 includes a pair of cross - coupled inverters connected to the true and complement sensing nodes s_t and s_c , as shown . a pfet 120 and an nfet 122 , and a pfet 124 and an nfet 126 respectively form the cross - coupled inverters . a pull - up pfet 128 connects pfets 120 , 124 to the positive voltage supply rail vdd and a pull - down nfet 130 connects nfets 122 , 126 to ground . the efuse 102 and reference resistor 116 are connected to a common node labeled fsource and a connected via a pair of series connected n - channel field effect transistor ( nfets ) 140 , 142 to ground . a fuse programming circuit coupled to the efuse 102 includes a nand gate 150 receiving two inputs , blow_fuse , fuse_solution and providing an output applied to an inverter 152 , and a pair of series connected n - channel field effect transistor ( nfets ) 154 , 156 connected between the efuse 102 to ground . the reference resistor 116 is , for example , about ½ the difference between a “ 0 ” and “ 1 ” resistance of fuse 102 . the fuse 102 and the reference resistor 116 are used to generate signal for the sense amplifier , that converts them to a digital “ 0 ” or “ 1 ” value . a sense amplifier signal control 160 generates signals sigdev , fset , and precharge that are applied to the sense amplifier 100 in normal operation as illustrated in fig2 a and 2b . the sense amplifier signal control 160 generates signals sigdev , fset , and two separate precharge control signals pc_tru , pc_cmp that are applied to the sense amplifier 100 during testing operation as illustrated in fig3 a and 3b in accordance with features of the invention . referring to fig2 a and 2b , the sense amplifier 100 initializes by precharging both sides of the sense nodes s_c , s_t to a high voltage with a low precharge signal applied to both pfets 104 , 110 . the fset signal is inverted by an inverter 210 and applied to pfet 128 and the fset signal is directly applied to nfet 130 . the sensing signals sigdev are applied to nfets 106 , 112 on the two sides of the amplifier 100 and the amplification process commences . however , after initial processing of the silicon , it is desirable to test whether the sense amplifier 100 can generate a valid “ 0 ” and “ 1 ” before blowing or programming the fuse 102 . with the efuse 102 not blown the sense amplifier 100 will result in an output “ 0 ” at the output true of inverter 134 of fig1 , with s_c high and s_t low , as shown in fig2 b . as shown in fig2 b , reading the efuse 102 includes normal control signals as follows : 1 ) initially , precharge on , ( pfets 104 , 110 turned on ) sigdev off ( nfets 106 , 112 turned off ), fset off ( pfet 128 off , nfet 130 off ) 2 ) sigdev on ( nfets 106 , 112 turned on ) 3 ) fset on ( pfet 128 turned on , nfet 130 turned on ) 4 ) precharge off ( pfets 104 , 110 turned off ) 5 ) sigdev off ( data can be read ) ( nfets 106 , 112 turned off ) 6 ) fset off ( pfet 128 off , nfet 130 off ) 7 ) precharge on ( pfets 104 , 110 turned on ) in accordance with features of the invention , after initial processing of the silicon defining sense amplifier 100 , the sense amplifier 100 is tested to determine whether the sense amplifier 100 can generate a valid “ 0 ” and “ 1 ” outputs before programming or blowing efuse 102 . when the efuse 102 is not blown the sense amplifier 100 will result in an output “ 0 ”. when the fuse is blown the sense amplifier 100 will result in an output “ 1 ”. testing of the sense amplifier 100 includes both states of the sense amplifier 100 that result from both the blown and not blown conditions of the efuse 102 without requiring that the efuse be programmed or blown . referring to fig3 a and 3b in accordance with features of the invention testing of the sense amplifier 100 is provided without requiring any additional devices to be added to the sense amplifier . the fset signal is inverted by an inverter 210 and applied to pfet 128 and the fset signal is directly applied to nfet 130 . the sensing signals sigdev are applied to sensing node nfets 106 , 112 on the two sides of the amplifier 100 . as shown in fig3 b , the method to read 0 with an unblown fuse 102 is illustrated near the bottom of fig3 b , with signal pc_cmp is held low keeping pfet 110 on , and pc_tru switched off early turning pfet 104 off . since the efuse 102 is unblown , the fuse can be read normally as shown in fig2 b , however , pc_tru can be switched off early as shown in fig3 b , while it should be understood that this is unnecessary . as shown in fig3 b , reading 0 with the unblown efuse 102 includes testing control signal as follows : 1 ) initially , pc_tru on , and pc_cmp on , ( pfets 104 , 110 turned on ) sigdev off ( nfets 106 , 112 turned off ), fset off ( pfet 128 off , nfet 130 off ) 2 ) sigdev on ( nfets 106 , 112 turned on ) 3 ) fset on ( pfet 128 turned on , nfet 130 turned on ) 4 ) pc_tru off , pc_cmp on ( pfet 104 turned on , pfet 110 turned off ) 5 ) sigdev off ( data can be read ) ( nfets 106 , 112 turned off ) 6 ) fset off ( pfet 128 off , nfet 130 off ) 7 ) pc_tru on , pc_cmp on ( pfet 104 turned on , pfet 110 turned on ) the method to read 1 with an unblown efuse 102 is illustrated near the bottom of fig3 b starting with signal pc_tru that is held low keeping pfet 104 on , and pc_cmp switched off early turning pfet 110 off . as shown in fig3 b , reading 1 with the unblown efuse 102 includes testing control signal as follows : 1 ) initially , pc_tru on , and pc_cmp on , ( both low with pfets 104 , 110 turned on ) sigdev off ( nfets 106 , 112 turned off ), fset off ( pfet 128 off , nfet 130 off ) 2 ) sigdev on ( nfets 106 , 112 turned on ) 3 ) fset on ( pfet 128 turned on , nfet 130 turned on ) 4 ) pc_tru on , pc_cmp off ( pfet 104 turned on , pfet 110 turned off ) 5 ) sigdev off ( data can be read ) ( nfets 106 , 112 turned off ) 6 ) fset off ( pfet 128 off , nfet 130 off ) 7 ) pc_tru on , pc_cmp on ( pfet 104 turned on , pfet 110 turned on ) while the present invention has been described with reference to the details of the embodiments of the invention shown in the drawing , these details are not intended to limit the scope of the invention as claimed in the appended claims .