referring to fig1 and 2 , an example of a device in accordance with the invention is shown which makes use of two coupled asymmetric quantum point contacts ( caqpcs ). the structure is fabricated on a semiconductor wafer , shown in section in fig2 that contains a two - dimensional electron gas ( 2 deg ) at a heterojunction interface . in this embodiment , two 2 deg layers are used in order to increase charge carrier transport . referring to fig1 electrons are constrained to flow through two essentially one - dimensional constrictions between ohmic contacts a - d and b - c respectively , the constrictions being referenced 1 , 2 in fig1 . the constrictions are defined by electrodes g1 , g2 which overlie the substrate , and electrodes g t1 and g t2 , which form a barrier between the constrictions 1 , 2 except in a central region of width l t . referring to fig2 in which the device is shown in cross section , the device is conveniently fabricated on a gaas substrate 3 , on which is formed a relatively insulating low temperature ( lt ) gaas layer 4 , which is overlaid by a series of gaalas layers 5 , 6 , 7 , with thicknesses as shown in the drawing . a gaas layer 8 forms a heterojunction with layer 7 on its underside . its upperside forms a heterojunction with an overlaid gaalas layer 10 , which is overlaid by another such layer 11 and a gaas passivation layer 12 . as well known in the art , such a configuration produces an essentially two - dimensional electron gas at each heterojunction interface , referenced 9a and 9b , the lateral extent of which is controlled by depletion regions 13 , 14 produced by control potentials supplied to electrodes g1 , g2 . referring again to fig1 the ohmic contacts a - d make contact with both of the 2 deg regions 9a , 9b . as a result , a first conduction path is provided between terminals a and d , and a second path is provided between terminals b and c , the paths extending through the constrictions 1 , 2 respectively . as previously stated , these constrictions constitute quantum point contacts ( qpcs ) of width and longitudinal extent w 1 , l 1 ; w 2 , l 2 . the qpcs are separated by inversion layers produced by gate electrodes g t1 , g t2 but an asymmetrical coupling occurs in a region of dimensions l t , w t between the electrodes . the device is constructed on a nanometer scale and as a result , the quantum properties of wavefunctions dominate electron transport . electrical conductance is limited by the transmission rate of electrons through each qpc and the quantum mechanical wavefunction profile in the device plays a significant role in the transmission rate . in accordance with the invention , the wavefunction is configured to have an asymmetrical profile and as a result , the transmission probability for each constriction 1 , 2 depends upon the energy levels set in the device . as will be explained hereinafter , at different energy levels , electrons preferentially travel along either constriction 1 or constriction 2 since the transmission probability oscillates between the constrictions as a function of the quantum number of the energy level and this permits electron transport to be switched between the constrictions 1 and 2 . also , since a large number of quantum states are available , the device can be used as a multiple - state logic device . in order to achieve a symmetry of the quantum mechanical wavefunction in the region of the qpcs 1 , 2 , the widths of the constrictions w1 , w2 are given different values . typical dimensions for example shown in fig1 are w 1 + w t + w 2 = 800 nm , w t = 100 nm , l t = 200 nm . l 1 and l 2 are each of the order of 1 μm . a 20 % difference in w 1 and w 2 is typically provided to provide the asymmetry , such that w 1 = 385 nm and w 2 = 315 nm . referring now to fig3 ( a ), this shows a profile for the lateral electron confinement potential in the direction x -- x &# 39 ; indicated in fig1 . the potential consists of an asymmetrical well configuration comprising wells 15 , 16 associated with qpc1 and 2 respectively , the well 15 being slightly narrower due to the asymmetry of the widths w 1 , w 2 . the well configuration includes a twin - asymmetric trough portion , shown within dotted outline 17 . an enlarged view of the trough portion 16 is shown in fig3 ( b ). stable energy states n = 1 to 18 are shown . these have been computed by solving the schrodinger wave equation for the potential well shown in fig3 ( a ), for energy levels of electrons up to the 18th quantum number , as shown in fig3 ( c ). referring to fig3 ( b ), in the twin - trough region it can be seen that for eigenstates that lie within the twin - trough region , the stable state falls either in a region associated with qpc1 or qpc2 , but not both . for example when the energy level is such that n = 4 , the wavefunction localises in qpc1 whereas when n = 5 , the wavefunction localises in qpc2 . this selective action occurs for a range of energy states , in this example from n = 2 to 12 . at higher electron states , the wave function extends across both of the qpcs so that dual channel conduction will occur , i . e . electron transport can occur in both qpcs simultaneously . thus , by selecting the energy level for example , to lie within the range n = 2 to 12 , multiple state logic can be achieved . switching between successive energy levels can be achieved by changing the applied voltage to the device . as a result , the conductance difference between qpc1 and qpc2 can be made to switch back and forth as a function of applied voltage . fig4 ( a ) shows the conductance difference as a function of voltage or equivalently as a function of energy . in this figure the voltage in the horizontal axis represents a gate voltage applied to gates gt1 and gt2 of fig1 . the amplititude of the oscillation in the value of the conductance difference is less than the quantised conductance 2e 2 / h per 2 deg layer . v n indicates the voltage where the fermi level coincides with the nth energy level . thus , by changing the gate voltage , different resonant conditions with different energy levels are achieved and result in the energy levels switching back and forth between the different maxima and minima shown on the graph . referring now to fig4 ( b ), this illustrates four - state logic operation using the device , when connected to a series resistor r l . for example , the resistor r l may be connected to terminal d shown in fig1 . the resistance is loaded with a voltage v l ( as will be explained in more detail hereinafter ). the graph shown in fig4 ( b ) illustrates how the device can be used for four - state logic operation with four stable operation voltage points v0 to v1 . with the application of a positive or negative voltage pulse having an absolute value higher than ( v n - v n - 1 )/ 2 , the circuit is switched between v n - 1 and v n . whilst a four - state device is described , it will be appreciated that a different degree of multiplicity can be set by appropriately choosing v l and r l . referring now to fig5 this shows a 4 - voltage state device used for logic operation . the capc corresponds to that shown in fig1 and 2 , and corresponding parts are marked with the same reference numerals . voltage sources v a , v g1 , v g2 , v t are connected as shown to the terminals a , g 2 , c , g 1 , and g t1 , g t2 respectively . an input to the device is v i ( t ) is applied at terminal 17 through a capacitor c1 to the gates g t1 , g t2 . an output from the device is taken through a load resistor r l that is biased by a load voltage v l , the output being derived at terminal 18 . in a typical example of operation of the device to provide 4 - voltage - state logic , the gate voltages v g1 and v g2 applied to g 1 and g 2 are - 0 . 9 v and that applied to g t1 and g t2 is - 0 . 5 v . a voltage pulse v i ( t ) is superimposed on v t through the input terminal 17 so as to trigger a change between the stable voltage states v n and v n - 1 . in this example the four - stable states v 0 , v 1 , v 2 and v 3 are 6 mv , 7 mv , 8 mv and 9 mv with equal spacing v n - v n - 1 = 1 mv . in order to achieve the 4 - state condition illustrated in fig4 ( b ), special consideration needs to be given to the relative values of v a , v l and v c and the following condition needs to be establish generally , under these conditions , the device operates such that current flows from terminal a to either terminal d or terminal c . the characteristics to current flow for the two paths is substantially the same . a typical current flowing through terminal d is about 1 μa with r l = 25 kω , v a =- 20 mv , v l =- 10 mv and v c = 0 mv . four - state flip - flop - like digital operation of this device is demonstrated in fig7 ( a ). in the upper part of the figure a typical input wave form v i ( t ) is shown , which consists of a number of trigger pulses that , as previously described , trigger the circuit between four different stable states . the input waveform can switch from a median operating level v op to an upper level v u or a lower level v d . thus , in fig7 ( a ), the input voltage includes three successive positive going pulses 19 , 20 , 21 followed by three negative going pulses 22 , 23 , 24 . the effect of these pulses on the output at terminal 18 ( fig5 ) is shown in the lower part of fig7 ( a ). pulse 19 causes the output 18 to flip from voltage v 0 to v 1 . similarly , pulse 20 causes the output voltage to flip from stable state v 1 to v 2 . similarly , pulse 21 causes a change to stable state v 3 . the negative going pulses 22 , 23 , 24 produce an inverse effect , so as to switch the stable state of the output 18 downwardly between the stable voltage levels . the input voltage need not necessarily be applied to the gates g t1 and g t2 . instead , it could be superimposed on the voltage at terminal d . it will be appreciated that electron flow through the device is essentially ballistic , controlled by the quantum mechanical wavefunction in the regions 1 , 2 . accordingly , the operation time scale for the device needs to be longer than the electron time of flight from terminals a to c or d . this will be of the order to a few ps and so the operation time scale can be of the order of 10 ps . the invention can also be used as a memory device and an example is illustrated in fig6 . the nomenclature of fig6 corresponds to that of fig5 and the device conditions and structures are all the same except that the input v i ( t ) is applied directly to terminal d and the current flowing in the output resistor r l is converted into an output voltage for example by means of a comparator a1 . the result of memory operation for this device is shown in fig7 b . the input voltage v i ( t ) is switched from an operating level vop to either an upper &# 34 ; on &# 34 ; voltage v on or a lower &# 34 ; off &# 34 ; voltage v off . the operating voltage v op coincides with one of the four stable voltage points v n . the on - off voltage should lie between 0 . 5 ( v n - v n - 1 ) and 1 . 0 ( v n - v n - 1 ). as shown in the lower part of fig7 ( b ), a pulse from v op to v on switches the current flowing in resistor r l from a current i on to i off , whereas the corresponding pulse from v op to v off produces a reverse switching of the output load current from the i off to i on , thereby producing a memory operation . the memory operation can take place at the four stable voltage levels v n shown in fig4 ( b ). thus , by combining the four state logic device of fig5 with the memory configuration shown in fig6 two different degrees of freedom are realised for logic operation . thus , by means of the device of fig5 a first input can be used to switch between four different stable logic states and , by means of the input of fig6 a memory function with each of those states can be provided . thus , complicated multiple - state logic operations can be achieved by means of such a two - input device , with a single circuit element , thus providing a much more sophisticated logic element than a conventional two - state logic device . as previously explained , the invention also has other uses and fig8 illustrates a signal processing device . in the circuit of fig8 the same nomenclature is used as in the preceding figures . two input voltage pulse trains v ia ( t ) and v it ( t ) are superimposed respectively on dc voltage v a and v t , at input terminals 17a , 17t . outputs are taken from terminals d and c , amplified by amplifiers a d and a c , the outputs of which are combined by output amplifier a o to provide an output at terminal 18 . if the signal is applied to input 17a or b with no signal applied to the other , the device works as an amplifier . a small change to the input produces a large change at the output 18 according to the conductance characteristics shown in fig4 ( a ). thus , in this example , the slope of the curve shown in fig4 ( a ), in the region of one of the stable voltage levels vn , is used as the transfer function for the amplifier . an input signal applied to terminal 17a undergoes amplitude modulation through conductance modulation produced by a modulation voltage applied to input 17t . using the negative - differential resistance regions in the conductance characteristics shown in fig4 ( a ), an oscillator can be constructed . reference is directed to s . m . sze , physics of semiconductor devices ( john wiley & amp ; sons , n . y ., 1981 ) chap . 9 . micro - wave emission phenomena based on negative - differential resistance is discussed . with such an arrangement , if the voltage v t is controlled , for example by an appropriate input at terminal 17t , the oscillation can be switched on and off and hence an oscillator including an amplitude modulator is fabricated . the voltage v t can be alternately biased on and off or , if an input is applied at 17t , it can be made to alternate between adjacent conductance peak and valleys shown in fig4 ( a ) in order to achieve appropriate modulation . referring now to fig9 ( a ) and ( b ), yet another embodiment of the invention is shown wherein the device is integrated into a high - speed photoconductive switch . the device is formed in a substrate which has the same general structure as that shown in fig2 with a caqpc device , referenced generally at 20 , which is of the same construction as described with reference to fig1 with electrical connections ( not shown ) corresponding to those described with reference to fig5 . the substrate additionally includes overlying electrodes 21 , 22 , 23 , 24 , 25 , formed in the same way as electrodes g 1 and g 2 , spaced by non - conductive gaps 26 , 27 . a further pair of non - conductive gaps 28 , 29 are similarly formed , on either side of electrode 24 . an ultra - fast photoconductive switch ( pcs ) 30 is formed at the junction of electrodes 22 and 24 . the pcs 30 is shown in more detail in fig9 ( b ) and consists of two sets of interdigitated fingers 31a , 31b formed from the electrode material 22 , 24 overlying lt gaas so as to provide an interdigitated metal - semiconductor - metal switch . an example of such an arrangement is described in more detail in j . allam , k . ogawa , j . white , n . deb . baynes j . r . a . cleaver , i . ohbu , t . tanoue and t . mishima , ultrafast electronics and optoelectronics conf ., 1993 . reference is also directed to copending british patent application no . 9322246 . 1 filed on oct . 28 , 1993 , entitled interdigitated photodetectors . briefly , the recombination centers in the ltgaas accelerate decay of photo - injected carriers and a high speed response of the switch is thereby realised . in fig9 ( a ), the result of incident photons is to produce a modulation on the electrode 22 , which thereby modulates the voltage applied to gate g t2 of the caqpc 20 , which produces switching or alteration of the asymmetric wave function , in the manner previously described . thus , the pcs switch 30 can be used to produce logical switching between multiple voltage levels as previously described or alternatively , the device can be used to produce modulation in a manner generally described with reference to fig8 . all of the devices disclosed herein can be integrated with such high - speed photo - conductive switches and operated in the picosecond time domain . such devices can be utilised as optoelectronic logical modulation devices within a network of such optically interconnected systems . a more sophisticated optical switching arrangement will now be described with reference to fig1 ( a ) to ( c ) and 11 ( a ) to ( c ). referring to fig1 ( a ), the device is fabricated in the same general way as described with reference to fig9 and the device includes an array of pcs &# 39 ; s 30a - h , each connected to one of the terminals of the caqpc 20 by a respective transmission line 32 . referring to the pcs 30h in more detail , it consists of two sets of interdigitated electrodes as described with reference to fig9 . the transmission line 32 , formed in the same manner as transmission line 22 of fig9 extends from the gate region g t2 of the device 20 , to a contact pad 33 at the edge of the substrate . at the location of pcs 30h , the transmission line 32h is provided with a first set of interdigitated electrodes , in the manner shown in fig9 and the other interdigitated electrode set is coupled to transmission line 34 that extends to contact pad 35 at the edge of the substrate . referring to fig1 ( b ), the transmission line 32 is formed by selective etching of a conductive ground plane 36 to form parallel non - conducting gaps 37 , 38 on opposite sides of the transmission line . transmission line 34 is formed in a similar way . in use , a potential difference is applied to the contacts 33 , 35 , and when photons are incident upon the pcs 30h , an ultrafast electrical pulse is induced , which travels along the transmission line 32 to the gate g t2 of the caqpc 20 . each of the other pcs &# 39 ; s 30 is coupled in a similar manner to one of the inputs of the device 20 , as can be seen in more detail in fig1 ( a ). in fig1 ( a ), the connections to the device 20 are shown in more detail , in plan view . the device 20 , shown in fig1 ( b ) is essentially the same as that shown in fig1 and has its corresponding connections a - d , g t1 , g t2 , g 1 , g 2 connected to a respective one of the transmission lines 32a - 32h shown in fig1 ( a ). two of the connections are shown in more detail in fig1 ( a ), for gate electrode g t2 and connection c respectively . considering the transmission line 32h , it is connected to a tapered conductive portion 39 which connects to the gate electrode g t2 shown in fig1 ( b ). considering the waveguide 32c , this is connected to an ohmic contact 40 which is connected to the 2 deg regions 9 ( fig2 ) in qpc2 ( fig1 ). from fig1 ( c ), it will be seen that the layers 5 - 12 ( fig2 ) are configured as a mesa , shown by outline 41 in fig1 ( a ), which overlies the ltgaas photoconductive layer 4 on the substrate 3 . corresponding connections are made to the other gates and channels of the device 20 . thus , in use , photons incident on the pcs &# 39 ; s 30a - h can be used to trigger the multiple logic levels exhibited by the device 20 so that the device is switched between a number of multiple voltage output levels , dependent upon the number of trigger pulses produced by the various photoconductive switches 30 . the output of the device can be detected as described previously with reference to fig5 so as to provide a highly integrated , multiple level logic output system with a high degree of integration . referring now to fig1 , as an alternative to using a caqpc , coupled asymmetric quantum dots ( caqds ) can be employed . as known in the art , quantum dots tend to constrain small numbers of electrons in a quantum well ( in theory , single electrons can be constrained in this way ) and as a result , caqds demonstrate a higher peak to valley ratio in their conductance or current - voltage characteristics ( see fig4 ) but a lower current level because of the higher degree of wavefunction confinement in the quantum dots . fig1 illustrates a caqd manufactured by the same techniques described with reference to fig1 and 2 . the electrodes g 1 and g 2 are however each shaped in such a way as to provide an electron confinement region 42 , 43 defining quatum dots qd1 , qd2 . each qd has narrow conduction channels at both ends ( cw 1 for example ), which channels act as tunnelling barriers and confine strongly electron wave functions into the qds . the sizes of caqds in fig1 are as follows : w 1 = 385 nm , w 2 = 315 nm , l 1 = l 2 = 500 nm , cw 1 = cw 2 = 100 nm , w t = 100 nm and l t = 200 nm . many modifications and variations fall within the scope of the invention will be apparent to those skilled in the art . for example , although the devices have been described using two 2deg conductive regions , it will be appreciated that in order to increase current flow , it would be possible to produce further heterojunctions and hence further conductive layers in a multiple layer structure . also , it is possible to fabricate the devices with materials other than gaas as previously described . two dimensional electron gas and the electrode structures are also available in in 1 - x ga x as y p 1 - y / inp and si 1 - x ge x / si 1 - y ge y heterojunction interface layers and in si / sio 2 inversion layer . the caqpcs and caqds described hereinbefore are fabricated by means of split - gate processing with electron - beam lithography and metalisation . however , other methods could be used . for example focussed ion - beam implantation can be used to form the electrode structure shown in fig1 and 12 . also , a side - gate formation process can be used in which electron beam lithography , followed by chemical etching , can realise side - gate electrode structures for defining the region with an asymmetric quantum mechanical wave function .