in fig1 of the drawings , a conventionally formatted yuv digital signal 10 is received by an interlaced to progressive ( non - interlaced ) scan conversion module 12 for conversion into a non - interlaced yuv formatted signal 14 . the converter 12 performs the conversion from interlaced to non - interlaced in accordance with a spatial line doubling by interpolation technique , such as the bob technique specified by microsoft corporation . the signal 14 can take a variety of formats and is not limited to a yuv format . for example the signal 14 can take a ycrcb , yiq or rgb format . adaptive artifact removal module 16 operates in accordance with the principles of the present invention to remove artifacts , most notably , jagged or staircase like diagonal lines and edges in images embodied in signal 14 . it should be noted that adaptive artifact removal module 16 is most effective when operating on a non - interlaced signal generated from an interlaced signal by a bob type converter . however , the module 16 is also effective in removing , from other signals , artifacts that are of the type generated by a bob type converter . delay compensation modules 18 and 20 insert a delay into the u and v components , respectively , of signal 14 . the amount by which the u and v components are delayed by modules 18 and 20 is equal to an amount by which the y component is delayed by module 16 . modules 18 and 20 essentially operate to equalize the delay between the three components of the signal 14 and therefore to ensure that all three components of the signal 14 are time synchronized . fig2 of the drawings illustrates delay compensation modules 18 and 20 in further detail . the adaptive artifact removal module 16 in the embodiment described herein introduces a time delay into the y component of signal 114 of one scan line , and three pixels . the delay compensation modules 18 and 20 therefore include a line delay module 22 to introduce into the u and v components of signal 14 , a line delay equal to the line delay introduced by adaptive artifact removal module 16 . pixel delay modules 24 , 26 and 28 together introduce into the u and v components of signal 14 , a pixel delay equal to the pixel delay introduced by adaptive artifact removal module 16 . the line delay module 22 and the pixel delay modules 24 , 26 and 28 take the form of conventional storage devices that buffer the incoming component of the signal 14 for an amount of time equal to the desired delay . the exact implementation of the delay compensation modules 18 and 20 is not critical and can take any form that provides the required delay . the chrominance ( u , v ) components of the signal 14 exhibit a lower horizontal bandwidth than the luminance ( y ) component of the signal 14 . additional horizontal low - pass filtering therefore has less influence on the signal quality . thus , it is generally sufficient to apply the adaptive interpolation provided by module 16 to only the luminance component . however , if enhancement of the chrominance components is desired , either one or both of the delay modules 18 and 20 can be replaced with the adaptive interpolation module 16 . if the signal 14 is in a rgb ( red , green , blue ) format , then each component of the signal 14 , which contains both luminance and chrominance components , will have equal resolution and each component should be operated upon by adaptive interpolation module 16 . fig3 of the drawings illustrates adaptive artifact removal module 16 in further detail . the module 16 comprises three sub - modules 30 , 32 and 34 , arranged in parallel to each receive the y component of signal 14 . sub - module 32 performs filtering , as described in further detail below , on the y component of signal 14 to reduce the resolution of the received component of signal 14 . sub - module 34 inserts a time delay into the y component of signal 14 that is equal to the time delay imposed by sub - module 32 . sub - module 30 performs a binary edge detection operation on the y component of signal 14 to generate a selection signal 36 that selects , by way of selector 38 , either the output of sub - module 32 ( signal 40 ) or the output of sub - module 34 ( signal 42 ). the output signal 15 is a time delayed version of signal 14 that is otherwise either the same as the signal 14 or filtered to reduce the resolution of the signal 14 . selection of the filtered signal 40 or the purely time delayed signal 42 is performed as a function of non - horizontal transitions contained in images represented by signal 14 . the sub - modules 30 , 32 and 34 are now described in further detail . sub - module 30 , shown in further detail in fig4 includes a 3 × 3 sobel operator 44 that takes the form of a square convolution mask or matrix for vertical ( non - horizontal ) edge detection . the sobel operator 44 is preferred for edge detection but can be replaced with a vertical high - pass type filter with acceptable results . use of various high - pass filters may require proper tuning of the threshold level 50 . the output of the sobel operator 44 is received by an absolute value module 46 that generates the absolute value ( magnitude ) of the input . selector 38 compares the output of the module 46 with a stored threshold value 48 . the selector 38 generates an output that is a logical “ one ” if the input value to the selector 38 is greater than the stored threshold value 48 , and a logical “ zero ” otherwise . the stored threshold value 48 is preferably stored in a programmable register 50 to allow the value to be changed . for ease of understanding , it should be noted that a vertical edge in an image , such as created by a doorway or the side of a building , generates an abrupt horizontal transition . a horizontal edge in an image , such as created by a top of a doorway or flat top of an object , generates an abrupt vertical transition . as used herein , the term “ vertical edge detection ,” or variants thereof , refers to detection of a vertical transition . the term “ horizontal edge detection ,” or variants thereof , refers to detection of a horizontal transition . the impulse response of the sobel operator 44 is a two - dimensional sequence which can be realized as a cascade , or convolution , of two one - dimensional filters , such as the vertical high - pass filter ( vhpf ) 52 and the horizontal low - pass filter ( hlpf ) 54 shown in fig4 . the sequence in which the signal 14 is operated on by the filters 52 and 54 is not important and can be reversed so that the signal 14 is operated on first by hlpf 54 and then by vhpf 52 . edge detection is performed by the vhpf 52 which detects vertical type transitions in images represented by signal 14 . more specifically , the vhpf 52 detects the vertical component of transitions , which means that it detects transitions that have a vertical transition component , in other words , transitions that are not purely horizontal . as used herein , the term vertical edge detection is understood to be synonymous with non - horizontal edge detection , in other words , detection of transitions that have some vertical transition . hlpf 54 performs low - pass noise removal to filter out minor variations in vertical transitions . in alternative embodiments , the noise removal function performed by the hlpf 54 can be eliminated , leaving only the vertical edge detection performed by vhpf 52 . if the horizontal low - pass filter 54 is applied with the values [ 1 2 1 ] across each row of the matrix provided by the vertical high - pass filter 52 , then the first row of the resulting matrix contains the values [− 1 , − 2 , − 1 ], the second row contains the values [ 0 , 0 , 0 ] and the third row contains the values [ 1 , 2 , 1 ]. the vertical high - pass filter 52 , shown in further detail in fig5 takes the form of a 3 - tap filter with coefficients { 1 , 0 , − 1 }. since the central tap 57 is zero , the delayed input line corresponding to the central tap is not used in the computations . two line delay elements 56 and 58 operate to generate the second ( central ) and third taps , respectively , of the filter . the output of delay element 58 is summed by summing element 60 with the input to the filter 52 to generate the filter output operated on by hlpf 54 . the hlpf 54 , shown in further detail in fig6 receives the output of the vertical high - pass filter 52 and generates second and third taps of the filter with pixel delay elements 62 and 64 respectively . the first and third taps 61 and 63 are summed by summing element 66 and then normalized by summing element 68 . the normalization is performed by shifting , with shifter 65 , the output of the second tap 63 to the left one - bit to implement a multiply by two and then adding the result at summing element 68 with the result generated by summing element 66 . the absolute value module 46 generates the magnitude of the output of module 54 in a conventional manner . comparator 38 operates conventionally to compare the output of the module 46 with a stored threshold value 48 and to generate a single bit single indicating the results of the comparison . sub - module 32 is now described in further detail . vertical low - pass filter ( vlpf3 ) 70 operates to generate a signal that blurs vertical transitions in the y component of signal 14 . in an exemplary embodiment , the filter 70 takes the form of a 3 - tap vertical low pass filter , shown in further detail in fig7 . the output of the vlpf3 70 is further filtered by horizontal low - pass filter ( hlpf7 ) 72 . in an exemplary embodiment , hlpf7 72 takes the form of a 7 - tap horizontal low pass filter . the processing of the y component of signal 14 by the filters 70 and 72 limits the horizontal resolution of the y component of signal 14 to one - quarter of the sampling clock frequency . this results in a smoothing of the luminance ( y ) component of the signal 14 so that previously introduced interpolation artifacts ( such as by module 12 ) are no longer visible . the vertical low - pass filter 70 takes the form of a simple 3 - tap raised cosine filter with coefficient values of { ¼ , ½ , ¼ }. the implementation of the filter 70 , shown in fig7 includes line delay elements 74 and 76 which take the form of line delay memories to generate the second 75 and third 77 taps , respectively , of the filter 70 . the three taps of the filter 70 are multiplied by multipliers 78 , 80 and 82 with the coefficient values { ¼ , ½ , ¼ }, respectively . the outputs of multipliers 78 and 80 are summed by summing element 84 and the output of summing element 84 is summed with the output of multiplier 82 by summing element 86 to generate the output of the filter 70 . an alternative embodiment of the filter 70 is shown in fig8 . advantageously , the structure shown in fig8 provides an efficient implementation that avoids the multipliers required by the embodiment of fig7 . as can be seen in fig8 the multipliers 78 , 80 and 82 have been eliminated . multiplier 80 is replaced by shifter 88 which shifts the output of line delay element 74 to the left one - bit to achieve a multiplication by the coefficient value of ½ . multipliers 78 and 80 are replaced by shifter 90 with a corresponding change in the order in which the taps of the filter are summed together . the hlpf7 72 operates , in response to the output of vlpf3 70 , to reduce the horizontal resolution of the y component of signal 14 by an amount that is sufficient to mask any interpolation artifacts in a bob up - converted progressive scan video signal . in certain embodiments , a reduction of resolution by a factor of four may be sufficient . the hlpf7 72 rejects horizontal frequency components with frequencies greater than a user - specified cutoff frequency , which is a fraction of the horizontal sampling frequency . the filter 72 delays the input by a time delay equal to three pixels . the frequency response of the filter 72 is shown in fig9 . an exemplary embodiment of the filter 72 is shown in fig1 . by way of example , sufficient attenuation can be achieved with a seven - tap filter and the following filter coefficient values : { 20 / 256 , 34 / 256 , 47 / 256 , 54 / 256 , 47 / 256 , 34 / 256 , 20 / 256 }. notice that the filter coefficients have been normalized to add up to one . pixel delay elements 92 - 97 each generate a time delay of one pixel to generate taps 2 - 7 of the filter 72 . multipliers 98 - 104 multiply the corresponding tap ( 1 - 7 respectively ) with the respective coefficient . the output of multipliers 98 and 99 are summed by summing element 105 . summing elements 106 - 110 sum the output of the prior summing element with the output of the corresponding multiplier ( 100 - 104 ) to generate the output of the filter 72 . the coefficients in the filter shown in fig1 are symmetrical , and therefore three of the multipliers can be eliminated . also , the multiplication by rational values can be replaced by multiplication by the numerators only with a 8 - bit shift left operation at the output of the filter . a hardware implementation of the filter 72 operating in accordance with such principles is shown in fig1 . the implementation shown in fig1 takes advantage of the fact that the filter 72 is symmetrical and of odd length . the pixel delay elements 92 - 97 are the same . multipliers 111 , 112 , 113 and 114 and summing elements 115 - 120 perform the functions performed by multipliers 98 - 104 and summing elements 105 - 110 . effectively , the sequence of multiplication followed by summation in the embodiment of fig1 is replaced by summation , multiplication and summation to reduce the number of required multipliers . complexity of the filter shown in fig1 can be further reduced by replacing the multipliers 111 - 114 with a number of shifts and add or subtract operations . fig1 shows a rounding and clipping function 122 that performs rounding and clipping of values generated in an embodiment that employs integer arithmetic . if the embodiment of fig1 is implemented with integer arithmetic then rounding and clipping of the values generated therein would also be required to achieve the desired results . module 34 provides a delay compensated version of the full resolution y component of signal 14 . module 34 operates to generate the same amount of delay as delay compensation modules 18 and 20 shown in fig2 and described in the accompanying description . it is to be understood that the specific mechanisms and techniques which have been described are merely illustrative of one application of the principals of the invention . for example , many of the functions disclosed herein can be implemented equally well with dedicated hardware , or with programmable circuitry . numerous additional modifications may be made to the methods and apparatus described without departing from the true spirit of the invention .