fig1 shows a first embodiment which is formed by a more standard cmos fabrication process . there is a relatively large floating diffusion capacitance , which can tend to reduce the charge conversion gain . however , this system may be easier to make due to its use of a standard cmos process , with the floating diffusion being on the surface . an n - type well 100 is formed in the p - type substrate 105 . a first floating diffusion region 110 is a p - type floating diffusion region formed on the surface , i . e ., its top surface close to or touching the active oxide region 102 . the p - type floating diffusion region 110 is connected to a p - type output transistor 115 and a p - type reset transistor 120 . the reset transistor 120 connects to a p +- type diffusion region 125 which is biased , for example , to the voltage level of the drain voltage . the second floating diffusion region 130 is an n - type floating diffusion region . note that the second floating diffusion region 120 takes up a much smaller area then the first floating diffusion region , e . g . one fifth as much area . the second floating diffusion region is n - type , and is connected to an n - type output transistor 135 . an nmos reset transistor 140 connects the floating diffusion region to n + diffusion region 145 , which can be connected to a supply voltage level . in this way , a p - type region is formed extending from the edge of the p - type floating diffusion 110 to the edge of the p - type diffusion 125 . the n - type region , starting at floating diffusion 130 , is separate from the p - type region . in addition , the n - type region can surround virtually the entire active p type region , and all of the p + region . this new pixel design needs two separate reset control lines , one for the nmos reset transistor 140 and the other for the pmos reset transistor 120 . one column can be used for both output signals , e . g . with two select control lines . alternately , two output columns can be used with one select line . note that since the size of the two different floating diffusion regions is different , they will store different amounts of charge . therefore , the floating diffusion 110 can store more charge then the floating diffusion 135 . different integration periods for these two diffusion floating regions allow a flexible saturation exposure for each element . it also facilitates obtaining a highlighted compression knee sloped light transfer curve . a second embodiment is shown in fig2 . in this embodiment , the p type diffusion region 200 is formed below the surface of the n - well 202 . an overlying n region 215 is formed above the floating diffusion , covered by the active oxide . the n - well 202 , in this embodiment , is arranged to be fully depleted . a second smaller floating diffusion region 205 is connected to the buried floating diffusion 200 , and is connected to output transistor 115 . in this way , there are three superimposed pn junctions : a first junction between the overlying n region area 215 and the buried floating diffusion 200 . another pn junction is formed between the bottom of the floating diffusion 215 and the n region 202 . the third pn junction is between the fully depleted n region 202 , and the p type substrate 105 . the capacitance for the floating n type diffusion can be reduced by this structure . although only a few embodiments have been disclosed and detailed above , other modifications are possible . all such modifications are intended to be encompassed within the following claims , in which :