fig2 a shows a schematic of a power converter 10 embodying aspects of the present invention . power converter 10 includes a primary section 20 and a secondary section 30 electromagnetically coupled to one another through a transformer t including respective primary and secondary windings , 12 and 16 . a dc voltage input vin is connected to the primary winding 12 of the power transformer by a switch q 1 . in one exemplary embodiment , switch q 1 comprises a main power switch , such as an n - channel mosfet ( metal oxide semiconductor field effect transistor ) switch . it will be understood , however , that the principles of the present invention are not limited to mosfet switches since other types of power transistor switches , such as bjts ( bipolar junction transistors ), sits ( static induction transistors ), igbts ( insulated - gate biploar transistors ), and the like could be used , depending on the requirements in any given application . a clamp circuit arrangement is also provided to limit the reset voltage . the switch q 1 is shunted by a series connection of a clamp capacitor creset and a switch device q 2 . the conducting intervals of q 1 and q 2 are generally mutually exclusive . the voltage inertia of the capacitor creset limits the amplitude of the reset voltage appearing across the magnetizing inductance during the non - conducting interval of power switch q 1 . generally , the present invention fulfills the foregoing needs by providing in one aspect thereof a power distribution system including a plurality of power converter modules each having a current sharing signal terminal on an input side and power output terminals on an output side , the corresponding power output terminals of the several modules being connected together and adapted to power a common load ; an interconnecting signal bus coupled across the current sharing signal terminals on the input side ; a plurality of feedback circuits , each of which is associated with one of said modules , each feedback circuit including a comparator ( output error amplifier ) for comparing a feedback voltage on the output side with a reference voltage to provide an error signal to the input side ; the error signal conditioned to provide a current command signal to said signal bus , wherein the signal bus provides a control signal to drive the power converter modules . the secondary winding 16 is connected to an output lead through a synchronous rectifier 14 including rectifying devices sr 1 and sr 2 . in one aspect of the invention , each rectifying device comprises a mosfet rectifier device including a body diode . other types of switches could be used , depending on the requirements in any given application . with the power switch q 1 conducting , the input voltage vin is applied across the primary winding 12 . the secondary winding 16 is oriented in polarity to respond to the primary voltage with a current flow through inductor lo , the load connected to the output lead and back through the mosfet rectifier device sr 1 to the secondary winding 16 . continuity of the current flow in the inductor lo when the power switch q 1 is non - conducting is maintained by the current path provided by the conduction of the freewheeling rectifier device sr 2 ( e . g ., mosfet ). an output filter capacitor co shunts the output of the converter . gate control circuitry 18 is provided to apply the gate signal to freewheeling rectifier device sr 2 in accordance with the invention . in one aspect of the invention , gate control circuitry 18 is designed to gradually apply the gate signal to the synchronous rectifier sr 2 through gradually releasing either the amplitude or the pulse - width of the gate signal to sr 2 . the speed of releasing the gate signal to sr 2 is a parameter determined in accordance with the design requirements of the circuit . design considerations include the following factors : an abrupt release of the gate signal may introduce a strong disturbance to the converter and cause an unacceptable output voltage transient . a very slow release may cause a few unfavorable problems as well , such as the output voltage may over - shoot under no - load and lose pwm action which could further cause a loss of bias power depending on the detail design . fig2 b - d show exemplary gate drive signals in which the duty cycle , or amplitude , or both duty cycle and amplitude , are shown to be variably used in the clamping action and soft start of sr 2 . fig3 illustrates an exemplary embodiment of the gate control circuitry 18 . the control circuitry 18 is coupled to the drive terminal ( gate ) of the switch sr 2 . in this example scheme , the gate control circuitry 18 provides clamping by including a diode and a resistor paralleled to a capacitor ( resistor - capacitor - diode ( rcd ) snubber ) which acts as a voltage clamp . the voltage across the capacitor and resistor sets the clamp voltage . specifically , diode dg has its anode coupled to the gate of sr 2 and its cathode coupled in series to a clamping capacitor cg and resistor rg in parallel . this scheme calls for the gate drive circuit be tolerable to a “ shorting ” of the gate of the synchronous rectifier . in another implementation , as shown in fig4 to magnify the clamping effect of the capacitor cg , a transistor qg replaces the diode dg of fig3 . in one aspect of the invention , transistor qg comprises a pnp transistor with its emitter coupled to the gate of sr 2 , its base coupled in series to a capacitor cg and resistor rg in parallel . in the event the base - to - emitter reverse blocking voltage of qg is not sufficient , a diode ( not shown ) can be added in series with the emitter or the base of qg to block the voltage when sr 2 is off ( gated low ). the capacitance of cg , which controls the properties of the clamping effect is selected to obtain desired results . as the gate threshold voltage of the transistor qg is moving lower , the emitter - to - base ( also the extra diode that may be included ) voltage drop could become too large to clamp the gate of sr 2 to a sufficiently low level . in that situation , the common of the clamping circuit 18 is moved to a negative voltage potential with reference to the point shown in the figures . as is apparent to those skilled in the art , the other part of the drive circuits to sr 1 and sr 2 not shown in the figures can take on various forms . a condition is that the drive circuit for sr 2 should be capable of working properly when the gate of sr 2 is almost “ shorted ” to sr 2 source for some time during the start - up process . for example , it may include certain impedance , such as a resistor ( not shown ) or a capacitor ( not shown ), in its main current path . while the preferred embodiments of the present invention have been shown and described herein , it will be obvious that such embodiments are provided by way of example only . the overall topology encompasses any topology suitable for synchronous rectification , and is not limited to the topology shown in the illustrated embodiment . numerous variations , changes and substitutions will occur to those of skill in the art without departing from the invention herein . accordingly , it is intended that the invention be limited only by the spirit and scope of the appended claims .