fig2 shows an exemplary embodiment of a frequency compensation circuit 100 in accordance with the present invention . referring to fig2 , the frequency compensation circuit 100 comprises a transconductance amplifier 30 which is a voltage controlled current source , a voltage source 1 , a current source 2 and a reference voltage 4 . the voltage source 1 is coupled to a negative input 32 of the transconductance amplifier 30 through a resistance 3 and the current source 2 is also coupled to the negative input 32 of the transconductance amplifier 30 . the reference voltage 4 is coupled to a positive input 31 of the transconductance amplifier 30 . the primary output of the transconductance amplifier 30 is coupled to the negative input 32 through a feedback connection . the first output of the transconductance amplifier 30 is coupled to a first compensation network 10 comprising a resistance 7 and a capacitance 8 . a second output of the transconductance amplifier 30 can be coupled to additional compensation impedance 9 or other circuits . the transconductance amplifier 30 in the given embodiment has a differential voltage input comprising a positive input 31 and a negative input 32 , and a first current source output 33 with a gain g m . further , the transconductance amplifier 30 in the given embodiment has one or more secondary independent current outputs 34 , 35 with matched but magnitude scaled gains k 1 × g m , . . . , k n × g m , where k n ( n = 1 , 2 , . . . ) are predetermined scaling factors that may be less than , equal to or more than 1 . the primary current output 33 is connected to the negative input 32 to provide a feedback function . thus , the negative input 32 is driven to the same potential as the positive input by the large value of g m and the feedback connection . the negative input 32 is also coupled to the voltage source 1 via the resistance 3 and to the current source 2 , while the positive input 31 is coupled to the reference voltage 4 . the first current output 34 is coupled to a first compensation network 10 comprising a resistance 7 and a capacitance 8 . it is noted that one of the terminals of the capacitance 8 is connected to ground or other suitable reference potential . alternatively , the compensation network comprising capacitance 8 may be indirectly connected to ground or other reference potential via the series resistance 7 . since the capacitance 8 is connected to ground or the reference potential , it is easy to control an initial voltage of the capacitance 8 ( for example , to initialize or reset the circuit ). the transconductance amplifier 30 may have additional independent outputs 35 connected to separate impedances 9 having an impedance value of z n to provide different transfer functions or to drive other circuits . assuming the input impedance of the transconductance amplifier 30 is large enough and initial conditions are ignored , the voltage transfer function for the output of this circuit taken at 34 is : - v out ( v 1 - v ref + v out k 1 ⁢ g m ⁡ ( r f + 1 s ⁢ ⁢ c f ) r s ) - i 2 = s ⁢ ⁢ r f ⁢ c f + 1 s ⁣ c f k 1 ( 2 ) similarly , assuming k 1 r f g m & gt ;& gt ; 1 , the transfer function for the secondary current output 35 is : it is noted that with the advantages of multiple independent outputs , the capacitor size c f ( or z n ) can be easily scaled with the factor k 1 ( or k n ). in addition , the secondary current outputs which have scaled but proportional outputs related to the same inputs may have different filter functions , for example proportional and integral outputs , different filter types or bandwidths , comparator or window functions and etc . the transconductance amplifier 30 in the given embodiment has an input circuit block 40 and an output circuit block 50 . examples of the configuration of the input circuit block 40 are shown in fig3 and 4 . the input circuit block 40 further comprises a differential voltage input stage 41 and a level shift and / or additional current gain stage 42 . the input circuit block may output a high side signal x h or a low side signal x l . examples of the detailed configuration of the input circuit block 40 are shown in fig4 a - 4 d . as shown for example in fig4 a , the differential voltage input stage 41 may comprise two nmos transistors 43 and 44 and a bias current sink 45 a . a level shift stage 42 may comprise a pmos current mirror 46 . in fig4 b , the differential voltage input stage 41 may comprise two pmos transistors 47 and 48 and a bias current source 45 b . the level shift stage 42 may comprise a nmos mirror 49 . in fig4 c and 4 d , the mos transistors are replaced with bipolar transistors . the input circuit comprises the differential voltage input stage with complementary current outputs x h and x l , where x h is a sink current and x l is a source current . | x h |+| x l |=| bias current | or if additional gain is needed , | x h |+| x l |= k ×| bias current |, where k is a factor greater than 1 . the current mirror is needed to provide the correct polarity currents to drive the output stages . in function , this circuit converts a differential input voltage into complementary currents for driving on output stage . examples of the configuration of the output circuit block 50 are shown in fig5 a and 5 b . in the given embodiment , cmos transistors ( fig5 a ) or bipolar transistors ( fig5 b ) may be employed . the output circuit block 50 may comprise n additional stages ( n = 1 , 2 , . . . ), each having a complementary pair of transistors ( nmos and pmos or npn and pnp ). as shown for example in fig5 a , in each stage , the sources of the pmos transistors are coupled to vcc and the sources of the nmos transistors are coupled to ground . the complementary signals from the input circuit block 40 , x h and x l shown in fig5 a and 5 b , are connected to the gate ( or base ) terminal of the pmos ( pnp ) transistors and the nmos ( npn ) transistors , respectively , in each stage . here , w / l indicate the relative dimensions of the mos transistors and a indicate the relative emitter areas ( sizes ) of the bipolar transistors . subscripts h and l indicate high side and low side . complementary driving signals from the input stage are connected to the output stage at x . the output from the first stage 51 , which is taken at the drain terminals of the transistors in the first output stage , may constitute the current output used for feedback to the input and the outputs from n th stages ( n = 2 , 3 , . . . ) may constitute the secondary current outputs , where n = 1 is for the primary compensator and n = 2 , 3 , . . . are secondary current outputs for other uses . it is noted that only one input circuit block 40 is required even for multiple outputs . the input referred offsets for ratio scaled and matched ( proportional to w / l or a ) outputs scale by the same factors ( k n ). also , g m has to be only sufficiently large for equation ( 3 ) to be valid without any requirement for a specific value or temperature dependence . in this point , the present invention differs from classic “ g m - c ” filters , and large g m is usually as easy to achieve as large a . in classical “ g m - c ” filters , the response is a function of the actual value of the parameter g m , so g m must be a value independent of process variation and temperature and changing only with the value of a prescribed additional ( control ) signal ( e . g . for a tuning frequency control ). in general , the g m of a differential voltage input stage to output current depends on process parameters , transistor sizes , die temperature and etc , as well as the bias current . here , the circuit output is set by r s and z n and not by actual g m &# 39 ; s but only g m ratios ( factor k &# 39 ; s ). one of the advantages associated with the present invention is the use of the transconductance amplifier 30 . with the scaling factors k n , the capacitance value c f in the compensation network 10 can be easily modified . in addition , since the capacitor 8 in the compensation network 10 is connected to ground ( or other reference potential ), the circuit of the present invention allows easy initialization or reset of the voltage of the capacitor 8 . another advantage associated with the present invention is that it can also provide multiple outputs all accurately proportional to each other and having the same input referenced voltage offset and variation with bias current . although certain specific embodiments of the present invention have been disclosed , it is noted that the present invention may be embodied in other forms without departing from the spirit or essential characteristics thereof . thus , the present embodiments are therefore to be considered in all respects as illustrative and not restrictive , the scope of the invention being indicated by the appended claims , and all changes that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein .