in accordance with the present invention , a semiconductor device comprising metal oxide semiconductor ( mos ) transistors and mosi 2 interconnections is fabricated . referring to fig1 a mos transistor is formed in and on a p - type silicon substrate 1 . a p + - type channel cut region 2 is selectively formed in and adjacent to the surface of the substrate 1 and the surface of the channel cut region 2 is then oxidized to form a field oxide layer 3 , for element separation . a thin layer of the exposed surface of the substrate 1 , i . e ., that surface not covered by the field oxide layer 3 , is oxidized to form a gate insulating film 4 of silicon dioxide . a gate 5 of polysilicon is formed on the silicon dioxide layer 4 . an n + - type drain region 6 and an n + - type source region ( not shown in the figs .) are formed by ion implantation using the gate 5 and the field oxide layer 3 as masks . the exposed surfaces of the gate 5 are then oxidized , and the silicon dioxide layer 4 on the source region ( not shown ) and the drain region 6 is selectively etched off to form electrode contact windows 8 . the above description is of a conventional process . referring to fig2 a non - doped polysilicon layer 9 is deposited to a thickness of , e . g ., 300 nm to 400 nm by a chemical vapor deposition ( cvd ) technique and a molybdenum ( mo ) layer 10 is then deposited on the polysilicon layer 9 to a thickness of , e . g ., 80 nm to 100 nm by an electron beam evaporation technique , or the like . referring to fig3 a , the mo layer 10 is patterned by forming a resist layer 11 on the mo layer 10 , patterning the resist layer 11 , and selectively etching the mo layer 10 with a heated etchant of , e . g ., phosphoric acid with 4 wt %- nitric acid , and the resist layer 11 acting as a mask . the resist layer 11 is then removed and heat treatment is effected at a temperature of approximately 550 ° c . for a period of , e . g ., 20 minutes , to change the mo layer 10 to an mosi 2 layer 12 . this mosi 2 layer 12 is formed by the reaction between the molybdenum in the mo layer 11 and the silicon in the polysilicon layer 9 and includes an upper part protruding from the surface of the original polysilicon layer 9 , approximately 80 nm to 100 nm thick , and a lower part buried in the polysilicon layer 9 , approximately 160 nm to 200 nm thick ( see fig4 ). in general , the heat treatment mentioned above is conducted at a temperature of above approximately 500 ° c ., preferably above 550 ° c ., since the reaction for forming mosi 2 occurs most frequently at such a temperature . further , the temperature is preferably below approximately 1300 ° c . since the resultant surface of the mosi 2 layer 12 is disturbed at a temperature near to the melting point of the polysilicon . selectively , the mosi 2 layer 12 shown in fig4 may be formed in a different way , as described below : referring to fig3 b , the mo layer 10 mentioned before and shown in fig2 is subjected to selective scanning with an energy beam , for example , a continuous wave laser beam , of a required intensity , to form a mosi layer 12 at the interface of the mo layer 10 and the polysilicon layer 9 . when beam scanning by a continuous wave argon ( cw - ar ) laser having a beam spot diameter of approximately 3 . 5 μ and an output of approximately 1 . 5 w is effected at a scanning speed of approximately 10 cm / sec , the resultant mosi 2 layer 12 has a thickness of approximately 100 nm . therefore , a plurality of scannings are needed to obtain an mosi 2 layer having a larger thickness , for example , 300 nm . in such a case , it is preferable to heat a supporter on which the silicon wafer , i . e ., the substrate 1 , is mounted for beam scanning to a temperature of approximately 400 ° c . to 450 ° c . lowering the scanning speed or increasing the output power of the laser may be done to decrease the number of scannings , but precautions should be taken that the melting point of the silicon is not exceeded . by this process an mosi 2 layer 12 having a thickness of approximately 240 nm to 300 nm is formed . a portion of the mosi 2 layer 12 is buried in the silicon layer , to a depth of approximately two - thirds of the thickness of the mosi 2 layer 12 itself . electron beams , ion beams , or other high energy beams may be used for selectively forming the mosi 2 layer 12 in place of the above laser beam . after the mosi 2 layer 12 is formed , the remainder of the mo layer 10 is removed by etching with a heated etchant of , e . g ., phosphoric acid mixed with 4 wt %- nitric acid , resulting in exposure of the mosi 2 layer 12 and the polysilicon layer 9 ( see fig4 ). referring to fig5 following the selective formation of the mosi 2 layer 12 , oxidation of the mosi 2 layer 12 and the polysilicon layer 9 is effected in a wet oxygen gas atmosphere at a temperature of , e . g ., approximately 900 ° c . to 1000 ° c . for a required period , until the polysilicon layer 9 is oxidized from top to bottom . this oxidation procedure forces the mosi 2 layer 12 to go down and reach the top surfaces of the field oxide layer 3 and the source region ( not shown ) and the drain region 6 , the mosi 2 layer 12 making contact with the source region and the drain region 6 , the mechanism of this phenomenon having been described before . after this oxidation , the polysilicon layer 9 is changed to a silicon dioxide ( sio 2 ) layer 13 , which is approximately twice as thick as the original polysilicon layer 9 . where the original polysilicon layer 9 shown in fig2 and the mosi 2 layer 12 have a thickness of 300 nm and 240 nm , respectively , the resultant thickness of the sio 2 layer 13 where the mosi 2 layer 12 does not exist is approximately 600 nm , and the resultant total thickness of the sio 2 layer 13 and the mosi 2 layer 12 where the mosi 2 layer 12 exists is approximately 520 nm . the difference in these two thicknesses is only 80 nm . where the polysilicon layer 9 and the mosi 2 layer 12 are 400 nm and 300 nm thick respectively , the resultant former and latter thicknesses are 800 nm and 700 nm , respectively , the difference being 100 nm . thus , the resultant layer consisting of the sio 2 layer 13 and the mosi 2 layer 12 has a substantially uniform thickness and , therefore , a substantially even top surface . selective etching of the polysilicon layer 9 to a certain thickness by using the mosi 2 layer 12 as a mask may be effected after the mosi 2 layer 12 is selectively formed on the polysilicon layer 9 , so that the resultant layer consisting of the sio 2 layer 13 and the mosi 2 layer 12 after oxidation has a theoretically uniform thickness , resulting in an even top surface . the thus obtainable even top surface of the sio 2 layer 13 , i . e ., an insulating layer , is extremely advantageous in that an excellent conductive layer can be easily formed on the insulating layer . further , the resultant sio 2 layer 13 is an excellent insulating layer since it is not formed onto an mosi 2 layer 12 originally having steps , as in the prior art . in a process according to the present invention , an active region such as the source or drain region in the above - described example is not damaged from sputtering , as in a conventional process . in addition , patterning of a layer of metal silicide such as mosi 2 is simple if it is effected by a high energy beam . it should be noted that the above description is made with reference to examples , and the present invention is not limited to these examples . for example , the mosi 2 layer 12 may be formed onto a phospho - silicate - glass ( psg ) layer , or the like other than a field oxide layer . the polysilicon layer on which a metal silicide layer is formed , and which should be oxidized , may be replaced by a single crystalline silicon layer . a process according to the present invention may also apply to other metal silicides such as wsi 2 , tisi 2 , tasi 2 , and ptsi .