embodiments of the present invention will be described in detail with the following drawings in order to clarify the above described and the other objects , property and advantages of the present invention . fig1 to fig2 are drawings illustrating a semiconductor apparatus of a first embodiment of the present invention . fig1 is a sectional view of a semiconductor apparatus in the first embodiment of the present invention ; and fig2 is a plan perspective view of the sectional view in fig1 looked at from the above . in fig1 , a bump 1 is embedded at an opening of an insulating resin layer 8 . the bump described above sits on the stand made of ubm ( under bump metal ) 2 . the lower layer of the ubm comprises a ubm via 3 for conduction from the bump to the upper layer wiring 4 . the upper layer wiring 4 is connected to a lower layer wiring 6 through a via plug 5 . these upper layer wiring 4 , lower layer wiring 6 and via plug 5 are also referred to collectively as an lsi layer wiring 9 . as apparent from this drawing , with the bump center line as a boundary line , a via plug 5 is arranged toward the chip inner side and compressive stress material 7 is arranged toward chip outer side . fig2 illustrates a plan perspective view of the same site , for the sectional view in fig1 . here , a semiconductor ship is looked up from the lower direction . with the center line of a solder bump as a boundary line , a via plug 5 is arranged toward the chip inner side and compressive stress material 7 is arranged toward chip outer side . moreover , the via plug 5 and the compressive stress material 7 are arranged immediately under an edge of the ubm 2 and the ubm via 3 . in addition , with fig3 , an entire image of the lsi chip will be described . here , in a simple manner , the case where the chip 101 has eight bumps in the outermost periphery is illustrated . however , actually , the number of bumps is greater so that those bumps form a matrix vertically and horizontally . the stress occurring immediately under these bumps in the outermost periphery is larger than the bumps in the inner periphery . a centripetal line l 1 connecting a center point c 1 of the lsi chip with a center point c 2 between the bumps 102 and 103 is presupposed . a line crossing the centripetal line l 1 perpendicularly on the lsi chip surface and passing the center c 2 of the bump is presupposed as a stress boundary line l 2 . fig4 illustrates an enlarged view of an attention bump 103 in fig3 . this diagram is a wiring layout of the bump and immediately under the bump likewise fig1 and 2 . the diagram illustrates relative relationship among the chip center , the chip end and the wiring under the bump . back to fig3 , corresponding to the bump position , the position of the stress boundary line is changed . with those stress boundary lines as boundaries , an example where compressive stress occurs on the chip center side and tensile stress occurs on the chip end side was adopted . a result of device simulation carried out by the inventor for supporting the distribution state of stress described above is illustrated in fig5 . the x axis / y axis respectively represent distance / stress from the bump center for the point of origin . the positive direction toward the upper side of the y axis from the point of origin represents tensile stress . the opposite negative direction represents compressive stress . in addition , the present simulation conditions will be briefly described with fig7 . at first , the case where an lsi chip 11 to become an object undergoes mounting on a mounting substrate 10 is imagined . the environment in the case of arranging the bump 1 , the ubm 2 , the ubm via 3 on the lsi chip side , applying heat of 220 ° c . to the both parties and cooling to 25 ° c . was reproduced . stress occurring on the wiring layer beneath the bump of the lsi chip was plotted . that simulation result can overlap on an a - a sectional diagram in fig4 . the point of origin in fig5 is taken as the position c 2 in fig4 . the via plug and the compressive stress material are arranged in fig4 but are not arranged under the simulation conditions in fig5 . as apparent from fig5 , the stress will enter complementary relation between the inner side and the outer side of the chip with the point of origin as the center . the stress will become compressive stress inside the chip , that is , in the chip center direction . in addition , the stress will become tensile stress outside the chip , that is , in the chip end direction . in further detail , the size of the stress apparently has four peaks in total at two sites each for inside and outside the chip . an edge of the ubm and an edge of the ubm via are present on the x axis where a peak goes , that is , in the position from the bump center . that is , width of the ubm is indicated by + a to − a points and width of the ubm via is indicated by + b to − b points on the x axis in the drawing . in other words , an edge of the ubm is present on the + a and − a points and an edge of the ubm via is present on the + b and − b points . a simulation result of arranging stress alleviating material only under the ubm on the chip end side with the stress boundary line as the boundary under the stress conditions as in fig5 is illustrated in fig6 . here , alleviation of tensile stress outside the chip compared with the prior arts indicated by dotted lines corresponding to fig5 can be interpreted . in addition , coupled alleviation of compressive stress inside the chip in complementary relation can be also interpreted . that is , stress outside the chip under the bump is alleviated by arranging compressive stress material against tensile stress being present outside the chip . alleviation of that tensile stress allowed alleviation of the compressive stress being present inside the chip to establish symmetrical relation . here , description on the simulation result will be omitted . however , the advantage likewise the result described above is obtained also in the case of arranging a via plug providing tensile stress immediately under the bump on the chip inner side providing compressive stress . here , an example of bringing an lsi chip and a mounting substrate has been described for the present embodiment , as illustrated in fig7 . the case where the lsi chip bends upward with the mounting substrate as illustrated with dotted line in fig7 is assumed . the drawing is two dimensional . however , actually , the four corners of the lsi chip bends upward against the mounting substrate . however , the case where the lsi chip bends in the opposite direction unlike the present embodiment can occur according to the respective conditions such as the mounting method and conditions of the lsi chip or the type of the mounting substrate . that is , the case of bending downward against the mounting substrate is naturally present . in such a case , the direction of stress will be opposite from the direction in the present embodiment . it goes without saying that the arrangement of material for alleviating that stress is also desired to be opposite from the arrangement in the present embodiment . in addition , this embodiment was exemplified only a tensile stress material being provided in inside of a chip under a bump , but it was not limited to this . for example , it is possible to provide a tensile stress material in the outside of a chip under a bump . and a density of tensile stress materials in an inside of chip under a bump may come to have thicker than the outside of chip under a bump . of course a size of tensile material in an inside of chip under bump may come to have larger than an outside of chip under a bump . so far , an example of a ubm and a ubm via corresponding to each bump respectively is illustrated in fig1 and 2 . here , an example of ubm via being present in plurality for a bump and ubm will be illustrated in fig8 . likewise fig1 and 2 , there are chip inner side and chip outer side on left and right direction on the sheet respectively . in addition , one ubm corresponds to one solder bump 1 and four ubm vias 3 correspond to that one ubm . a via plug 5 is arranged in a edge part of the ubm via toward the chip inner side with a predetermined boundary line 10 as a boundary also in fig8 , likewise fig1 and 2 . compressive stress material 7 is arranged symmetrically toward the chip outer side . here , the present invention will not be limited to each of embodiments described above . each embodiment apparently can be altered appropriately within the range of technological thoughts of the present invention . for example , the present embodiment was exemplified by line bisecting a predetermined region immediately under the bump . however , bisection is not required according to stress to occur . for example , in the case where the aspect ratio of the lsi chip is special , attention is required to the longitudinal side which is strongly influenced by stress . that is , the longitudinal side occasionally requires measures not only for the outermost peripheral bump but also for the peripheral bump being inner than the outermost peripheral bump . in addition , once again , it goes without saying that the stress can be coped with by appropriately changing material to be arranged in the case where the occurring stress is reversed between the vicinity of the chip center and the vicinity of the chip end . in addition , it is also possible to interpret the bump with bonding wire and the ubm with bonding pad .