fig4 illustrates a signal router 50 constructed in accordance with an embodiment of the invention . the signal router 50 includes a register bank 52 . in this embodiment , the register bank 52 loads eight data signals in parallel . a phase controlled read circuit 54 sequentially routes the signals to a lvds buffer 58 , which subsequently applies the signals to a differential signaling channel 59 . the phase controlled read circuit 54 is controlled by a delay locked loop 56 . the delay locked loop 56 receives an input clock signal and generates a set of eight phase displaced signals that are applied to the phase controlled read circuit 54 . the delay locked loop 56 routes the input signal to a clock output buffer 60 , which produces a differential output signal on differential signal lines 61 . fig5 illustrates the delay locked loop 56 generating a set of phase displaced signals 70 . each phase displaced signal is displaced from an adjacent phase displaced signal by ⅛ of a cycle . the eight output clocks from the delay locked loop 56 are used to route the eight signals from the register bank 52 . in other words , one clock signal from the delay locked loop 56 is assigned to each register of the register bank 52 . thus , a signal in a register bank is driven from the register bank 52 to the buffer 58 in response to its delay locked loop signal , resulting in the register bank driving a signal to the buffer 58 every ⅛ of a clock cycle . fig6 illustrates a phase controlled read circuit 54 that may be used to accomplish this functionality . in fig6 , q 1 through q 8 are the outputs from the register bank 52 , while φ 1 through φ 8 are the outputs of the delay locked loop 56 . the operation of the read circuit 54 is appreciated with reference to a single column of transistors . for example , consider the first column of transistors on the left side of the circuit 54 . initially , the φ 1 signal is high and the φ 2 signal is low . the digital high φ 1 signal is inverted and therefore turns - on pmos transistor 74 , the digital low φ 2 signal turns - on pmos transistor 76 , the digital high φ 1 signal causes the nmos transistor 78 to turn - on , while the inverted φ 2 signal has a digital high value and thereby causes the nmos transistor 80 to turn - on . in sum , transistors 74 , 76 , 78 and 80 are turned - on . the output of node 90 will now be determined by the states of transistors 82 and 84 , which receive the input signal q 1 . if q 1 is a digital low value , then transistor 82 turns - on and transistor 84 remains off . transistors 74 , 76 and 82 drive a digital high signal onto the output node 90 . thus , transistors 74 , 76 and 82 operate as a set of pull - up transistors . alternately , if q 1 has a digital high value , then transistor 82 is off and transistor 84 turns - on . transistors 84 , 78 , and 80 pull the output node 90 to a digital low value . thus , transistors 84 , 78 , and 80 operate as a set of pull - down transistors . observe that this operation occurs in the ⅛ of a cycle while the φ 1 signal is high and the φ 2 signal is low . when φ 1 and φ 2 are both high , transistors 76 and 80 will be turned - off , thereby preventing the column of transistors from driving a signal on the output node 90 . however , at this point , the next column of transistors is operative . this cascaded operation is repeated for each signal phase . the output node 90 , which is connected to each column of transistors , operates as a hardwired logical or circuit . observe that each register in the register bank 52 operates at the standard clock rate , not a multiple of the clock rate . thus , the simplified clock scheme does not have to generate high clock speeds . this results in low power consumption . in addition , concerns regarding whether a process technology can support high frequency clock signals no longer apply . only the lvds buffer 58 is required to operate at the higher clock speed ( e . g ., 8 times the clock speed ). the lvds buffer may be implemented using a standard lvds configuration , such as drivers 42 in fig3 . a multiplexer or de - multiplexer configuration is established by selecting the size of the register bank 52 and the corresponding delay locked loop 56 . this flexible scheme is highly extendible to conform to the number of lvds channels . the router 50 may be used in any number of architectures . for example , the router 50 may be a discrete circuit embedded in a programmable logic device . alternately , the router 50 may be implemented into the logical blocks of a programmable logic device . fig7 illustrates a programmable logic device 100 . plds ( sometimes referred to as pals , plas , fplas , plds , eplds , eeplds , lcas , or fpgas ) are well - known integrated circuits that provide the advantages of fixed integrated circuits with the flexibility of custom integrated circuits . such devices allow a user to electrically program standard , off - the - shelf logic elements to meet a user &# 39 ; s specific needs . see , for example , u . s . pat . no . 4 , 617 , 479 , incorporated herein by reference for all purposes . such devices are currently represented by , for example , altera &# 39 ; s max ® series of plds and flex ® series of plds . the former are described in , for example , u . s . pat . nos . 5 , 241 , 224 and 4 , 871 , 930 , and the altera data book , june 1999 , all incorporated herein by reference . the latter are described in , for example , u . s . pat . nos . 5 , 258 , 668 ; 5 , 260 , 610 ; 5 , 260 , 611 ; and 5 , 436 , 575 , and the altera data book , june 1999 , all incorporated herein by reference . the programmable logic device 100 includes a set of logic array blocks 102 . row interconnect circuitry 104 and column interconnect circuitry 106 link the various logic array blocks 102 . input / output elements 110 positioned at the ends of the row interconnect circuitry 104 and column interconnect circuitry 106 are used for input / output connections with external devices . fig8 illustrates a programmable logic device 114 configured for lvds transmission . the figure also illustrates a programmable logic device 116 configured for lvds reception . a differential signal channel 115 connects the two devices . each device may also receive transistor - transistor logic ( ttl ) signals at signal pins that are not connected to the differential signal channel 115 . the plds 114 and 116 of fig8 may be incorporated into a larger digital system , as shown in fig9 . fig9 illustrates a data processing system 120 . the data processing system 120 may include one or more of the following components : a processor 124 , a memory 126 , input / output circuitry 128 , and peripheral devices 130 . these components are coupled together by a system bus 132 and are populated on a circuit board 134 , which is contained in an end - user system 136 . the system 120 can be used in a wide variety of applications , such as computer networking , data networking , instrumentation , video processing , digital signal processing , or any other application where the advantage of using re - programmable logic is desirable . the plds 114 and 116 can be used to perform a variety of logic functions . for example , they can be configured as a processor or controller that works in cooperation with processor 124 . the plds 114 and 116 may also be used as an arbiter for arbitrating access to a shared resource in the system 120 . in yet another example , the plds 114 and 116 can be configured as an interface between the processor 124 and one of the other components in the system 120 . the plds 114 and 116 may communicate with the other elements of the system 120 using either ttl signaling or differential signaling . the invention was described in the context of a transmitting device in which the contents of a register bank 52 are sequentially read in response to the phase delayed signals . those skilled in the art will appreciate that the technique of the invention can also be used at a receiving device . in particular , the phase delayed signals can be used to sequentially latch a set of received signals into a register bank . after all of the signals are received , the received signals can be loaded in parallel to an adjacent register bank and then be processed in a standard manner . fig1 illustrates such a system . the receiving device 150 includes an lvds buffer 152 to convert each received differential signal into a single ended signal , which is applied to the phase controlled write circuit 154 . the phase controlled write circuit 154 is a set of registers that sequentially loads received signals in response to the phase delayed signals from the dll 156 . once the phase controlled write circuit is loaded , its contents can be written in parallel to the register bank 160 . the foregoing description , for purposes of explanation , used specific nomenclature to provide a thorough understanding of the invention . however , it will be apparent to one skilled in the art that the specific details are not required in order to practice the invention . in other instances , well known circuits and devices are shown in block diagram form in order to avoid unnecessary distraction from the underlying invention . thus , the foregoing descriptions of specific embodiments of the present invention are presented for purposes of illustration and description . they are not intended to be exhaustive or to limit the invention to the precise forms disclosed , obviously many modifications and variations are possible in view of the above teachings . the embodiments were chosen and described in order to best explain the principles of the invention and its practical applications , to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated . it is intended that the scope of the invention be defined by the following claims and their equivalents .