various embodiments are described more fully below with reference to the accompanying drawings , which form a part hereof , and which show specific exemplary embodiments . however , embodiments may be implemented in many different forms and should not be construed as limited to the embodiments set forth herein ; rather , these embodiments are provided so that this disclosure will be thorough and complete , and will fully convey the scope of the embodiments to those skilled in the art . embodiments may be practiced as methods , systems or devices . accordingly , embodiments may take the form of a hardware implementation , an entirely software implementation or an implementation combining software and hardware aspects . the following detailed description is , therefore , not to be taken in a limiting sense . reference in the specification to “ one embodiment ” or to “ an embodiment ” means that a particular feature , structure , or characteristic described in connection with the embodiments is included in at least one embodiment of the invention . the appearances of the phrase “ in one embodiment ” in various places in the specification are not necessarily all referring to the same embodiment . unless specifically stated otherwise as apparent from the following discussion , it is appreciated that throughout the description , discussions utilizing terms such as “ processing ” or “ computing ” or “ calculating ” or “ determining ” or “ displaying ” or the like , refer to the action and processes of a computer system , or similar electronic computing device , that manipulates and transforms data represented as physical ( electronic ) quantities within the computer system memories or registers or other such information storage , transmission or display devices . certain aspects of the present invention include process steps and instructions that could be embodied in software , firmware or hardware , and when embodied in software , could be downloaded to reside on and be operated from different platforms used by a variety of operating systems . the language used in the specification has been principally selected for readability and instructional purposes , and may not have been selected to delineate or circumscribe the inventive subject matter . accordingly , the disclosure of the present invention is intended to be illustrative , but not limiting , of the scope of the invention , which is set forth in the claims . traditionally dram is used as a fast - access temporary storage system when moving data between the disk and processor is time sensitive . the following is the traditional hierarchy of memory within a computer system in which the first levels have the least amount of storage space , cost the most , and have the fastest performance while the later levels have the most storage space , cost the least , and have slower performance . performance in this case can be defined as the read speed ( time to read the memory ) and the write speed ( time to program to the memory ). the first level of memory , known as the instruction cache , is composed of registers inside the actual processor . the second level is usually also a part of the processor and is referred to as the data cache 130 . the data cache can be further segmented into levels ( l1 , l2 , l3 , etc .) in the same relationship as described with memory ( most modern cpus have at least 2 levels of data cache ). subsequently , the memory used is a random access memory 140 . these memories can be static or dynamic depending on the function of the system . next , the memory is usually referred to as disk and refers to a nonvolatile memory product 150 that can store data longer ( and without power ). finally , there is a class of memory called tertiary storage , which refers to removable media such as dvds , cds , tape , and disks . in the traditional architecture , all levels before the disk level are traditionally thought of as volatile memories , meaning power is required to retain the data . subsequent levels are referred to as nonvolatile . additionally in the current state of the art , the performance characteristics of each type of memory remain relatively constant and are well - defined . performance characteristics for memory include but are not limited to read speed , write speed , read energy , write energy , data retention , endurance , and size . this memory system is also primarily considered to exist across the entire cpu , but in the current state of the art , the same system applies to most graphics cards , which include their own dedicated dynamic random access memory ( dram ). dram is a volatile memory , which means if the data is not refreshed within a certain time interval , the stored value can no longer be guaranteed to be accurate . the interval for the current state of the art dram is typically 64 ms . fefet memory is a dram product that has the flexibility for certain performance characteristics to change depending on how data is written to the memory . at the simplest level , this means that depending on the type of operation ( s ) being executed , fefet memory can provide more favorable characteristics than current state of the art dram . these benefits include lower power utilization , longer retention , higher density , and lower heat . for example when rendering a video , if the resolution is 1000 × 800 , at least 800 , 000 bytes of dram are programmed with the values of the pixels on the screen and must be refreshed at least every 64 ms . however in most video operation , less than 5 % of the screen actually changes every 64 ms . therefore , by programming an fefet memory cell in a certain way , it would be possible to have a longer retention on the cell and access it less , which improves both power utilization and heat generation . in terms of types of operations , the current state of the art has well - defined characteristics for how often dram is used during normal operation . knowing the types of instructions being executed and programming an fefet memory effectively can achieve tremendous savings and ultimately lead to lower cost . fig1 is a simplified block diagram of the processing and data storage functions of a typical computer utilizing fefet memory in accord with the present invention . three broad tiers of the memory hierarchy that the cpu 110 accesses through bi - directional data communication are described as follows : ( 1 ) the cache 130 within the cpu provides fast memory access ; ( 2 ) dram 140 provides volatile data storage ; and ( 3 ) storage 150 , typically accessed through i / o circuitry or other control logic , provides non - volatile data storage . instruction logic 120 refers to the components of the von neumann architecture of the processer and arithmetic logic unit and also includes the instruction cache . the instruction cache is the fastest level of temporary storage that can be used by the processor to store calculations . instruction cache memory is volatile in nature . cache 130 refers to the data cache component which can be broken down into several levels of cache , each level progressively larger in size , but slower in data access performance . most modern architectures include at least two levels of cache in the data cache . the data cache is volatile in nature , and one embodiment of the invention would be implemented in the data cache . any or all of these memories may utilize fefet memory in lieu of current dram technologies in accord with the present invention . for example , in one embodiment , fefet memory is used as a standalone volatile memory 140 . some embodiments of data storage 150 may include a volatile memory cache for faster access ; this cache could also utilize fefet memory . fig2 is a simplified block diagram of a soc 210 with on - chip fefet memory . the embedded fefet memory 241 provides memory support to the core logic function of the cpu 120 . note that , as previously mentioned , cache 130 and storage 150 can also be implemented as fefet memory . in certain embodiments , storage 150 can also be integrated in the soc 210 . as shown in fig3 , a computing device such as a laptop 310 can utilize embodiments of the present invention , such as the conventional memory architecture of fig1 or the soc of fig2 , each embodiment utilizing fefet memory in lieu of dram in one or more of its various components as discussed above . fig4 illustrates the single - transistor architecture of an fefet memory cell . the fundamental storage unit of the cell is a ferroelectric field - effect transistor ( fefet ) 410 . the makeup of the fefet may be , as a non - limiting example , metal layer 411 , silicon layer 412 , and the ferroelectric layer 413 . other structures are possible . fefets differ from traditional fets by storing information in their ferroelectric layer . in one embodiment , such as that discussed in ma &# 39 ; 244 ( incorporated by reference as if set forth in its entirety herein ), the ferroelectric layer is made of doped hafnium oxide . fig5 a depicts the data retention time of the fefet memory cell based on different types of metal electrodes . as depicted in fig5 a , the use of different gate and drain current magnitudes to program to the cell results in varying data retention characteristics . fig5 b depicts the hysteresis of an fefet memory cell varying by the composition of the ferroelectric materials and the cohesive voltage needed to program to an fefet memory cell , i . e ., at least that amount of voltage within the memory window of the hysteresis is required in order to successfully program an fefet memory cell . fig5 c ( left ) the relationship of the programming window and programming time of an fefet memory cell . fig5 c ( right ) depicts the extent of the memory window erased as a function of erase voltage in a fefet memory cell . these windows depict the values for the threshold voltage required to either set or reset an fefet memory cell . fig5 d depicts the data retention of an exemplary ferroelectric hafnium oxide fefet memory cell . fig5 d shows how long data is retained in the cell , effectively defining the interval between refreshes to ensure the data stored in the cell is considered reliable . fig5 e shows the endurance of an exemplary ferroelectric hafnium oxide fefet memory cell . fig5 e illustrates the number of times an fefet memory cell can be written to and still have a discernable memory window . fig5 f juxtaposes the data of fig5 g and 5h to show that an exemplary hafnium oxide fefet memory cell can have high endurance with decreased retention by reducing the programming pulse strength . fig5 g is a version of fig5 d depicting the same . fig5 h is a version of fig5 e depicting the same . fig5 depict several non - limiting examples of embodiments for programming fefet memories in accord with the present invention . as is evident from these examples , retention time is increased when a stronger programming pulse is used . one who is skilled in the art will appreciate that there is an inherent power relationship between current and voltage . accordingly , one can achieve longer data retention in an fefet memory by differing durations by varying the power characteristics used to program data to the fefet memory . one can analogously achieve higher endurance in a fefet memory by differing durations by varying the power characteristics used to program data to the fefet memory . finally , one can take as a whole both retention and endurance together in programming fefet memory by differing durations by varying the power characteristics used to program data to the fefet memory . varying data retention can be useful to various applications and offer improved thermal and power characteristics . one benefit to a longer data retention is that since there will be a longer interval between refreshes , the fefet memory will use less energy to operate . another benefit to a longer retention is that the fefet memory itself will produce less heat due to longer intervals between refresh cycles , which in turn can result in a reduction in cooling costs and overall energy used for cooling . another benefit to longer retention is that more of the memory will be accessible at any given time , reducing the average access time . one of ordinary skill in the art will note that the optimal operating parameters are not necessarily those that would program the fefet memory cell for the longest retention every time . such parameters would result in a higher - than - necessary current being applied if , for example , subsequent operations were expected to reprogram the fefet memory cell contents . thus it is necessary to determine how much power is actually required depending on , e . g ., the nature of the operations using fefet memory . another dimension of fefet memory programming is duration of the voltage being applied . by applying voltages for different durations as illustrated in fig5 c , a different relationship between endurance ( i . e ., device life ) and data retention is achieved in the fefet memory cell . one of ordinary skill in the art will appreciate that endurance and retention characteristics are related to acceptable error rate , which in turn may be a consideration in defining optimal operating parameters . soft error mitigation may be a consideration in choosing programming characteristics . one of ordinary skill in the art will appreciate that given the exemplary properties shown in fig5 a - 5f , there is a very large range of combinations of voltage and duration that will achieve different combinations of data retention and endurance . because of this flexibility , there can be tremendous benefits from varying the voltage applied or the duration of the charge in certain situations . for example , while traditional longer - duration higher - voltage programming may be suitable for traditional longer storage applications , lower - voltage shorter - duration programming may be preferable low power program operations . for completeness , shorter - duration higher - voltage and longer - duration lower - voltage programming can be used for various other applications and are just as desirable for optimization of power characteristics . as a non - limiting example , these can be used in sensor networks where high performance is required after long periods of standby . fig6 depicts a logical diagram for one embodiment of an fefet memory circuit , which can be used in either non - volatile or volatile applications . circuit 600 can include any combination of fefet arrays 610 , word line selector and driver 630 , bit line selector 635 , source line selector 640 , refresh circuitry 645 , sense amplifiers 650 , error checking and correcting units 655 , and read / program control circuitry 665 . in the embodiment illustrated , there is one of each of these units . however , other embodiments may contain zero or multiples of any of these elements . for more information , please refer to the patent application filed on jul . 2 , 2014 , entitled , “ circuitry for ferroelectric fet - based dynamic random access memory and non - volatile memory ,” having attorney docket number 98199 . 00083 and naming xiao sun and tso - ping ma as inventors , the disclosure of which is hereby incorporated by reference in its entirety . furthermore one of ordinary skill in the art would note that a full fefet memory product may contain one or more of circuit 600 and that each circuit 600 may include different combinations or numbers of the illustrated elements . for example one circuit 600 ′ may contain error checking and correcting units 655 while another circuit 600 ″ does not . however , circuit 600 ′ may be in electrical contact with 600 ″ so that the units 655 within circuit 600 ′ communicate with circuit 600 ″, etc . in order to implement the different levels of data retention as previously described , read / program control circuitry 665 may be enhanced beyond the standard read / program circuitry . in addition to the standard circuitry , an optional input can be added that overrides the “ normal ” operating parameters . this additional input can be specified in many ways and is depicted in fig7 by read / program controller 766 . note that read / program controller 766 is an optional component of fefet memory and that other circuitry normally included as part of read / program controller 665 is not otherwise depicted in figure . one exemplary embodiment of read / program controller 766 is a multiplexer that selects a different current , voltage , or programming time depending on the type of operational instruction that is currently being executed . this operation type may be communicated to the read / program controller 766 through an external source as part of the instruction set . another embodiment of read / program controller 766 would measure the interval between successive programming to memory cells of read / program control circuitry 665 . if the average interval between successive programs is short , it means the memory is being changed constantly and a lower current and voltage combination could be utilized . if the average interval between programs is long , then a higher voltage and current combination may be utilized . one of ordinary skill in the art would note that the embodiments described for read / program controller 766 need not be implemented physically on an fefet memory . the read / program controller function 766 could come from an external source such as , e . g ., the processor itself 120 . fig8 depicts one embodiment of the present invention that utilizes virtual segmentation in connection with the fefet memory cells . the fefet memory array 800 includes a plurality of segmentations 811 , 812 , etc . each segmentation 811 , 812 , etc . corresponds to a range of fefet memory cells that are being written to using certain electrical characteristics for a particular data retention . for the following example , segmentation 811 refers to a lower power , shorter data retention range while the segmentation 812 refers to a higher power , longer duration data retention range . while it is possible to program each fefet memory cell specifically , the management of such operations may result in an impractical amount of overhead . by creating segmentations within the fefet memory itself , the dram layer of the memory tree utilizing fefet memory more closely resembles the data cache layer ( l1 cache , l2 cache , l3 cache , etc .). in an analog as to how cache operations are executed on the data cache of a processor , the different segments within fefet memory could have different settings of normalized operations that would approximate the optimal configuration of programming voltage and current for the particular desired refresh characteristics for that segment . for example in a computer that has multiple operations occurring at the same time , a web browser session with a streaming video may be loaded . in this instance , the data for the browser session and the thumbnail placeholder for the video itself would be loaded into segmentation 812 because they correspond to an operation that is less likely to require reprogramming of the contents in segmentation 812 . however , if the video began playback , the memory operations resulting from the display of the video would get saved into segmentation 811 because while the video is playing , the memory contents are more likely to change rapidly . one of ordinary skill in the art will appreciate that while only two segmentations 811 and 812 are shown , there can be any number of segmentations within an array of fefet memory . furthermore , one can appreciate that the number of segmentations could dynamically change during operation . during the dynamic process , different segmentations could be added that have either a shorter retention or a longer retention depending on the characteristics of the data set that need to be stored within the fefet memory . fig8 a depicts the architecture of an exemplary fefet memory . each fefet memory includes a plurality of physical units 840 a , 840 b , etc . physical units are memories in physically separate packages . these separately packaged units may be mounted in two dimensions as on a printed circuit board ( pcb ) and / or stacked in three dimensions as in package on package ( pop ) configurations . each physical unit 840 includes a plurality of sets 830 a , 830 b , etc . these sets need not be of equal size or function . any plurality of sets 830 may be combined to form a larger set . sets 830 may include any grouping of memory elements that are housed in the same package 840 , including three dimensional stacking of fefet memory on the same die , and stacked chips within the same package 840 . each set 830 comprises one or more minimal addressable memory elements 820 a , 820 b , etc . these elements are the smallest addressable unit within the fefet memory . sets 830 may also comprise other sets 830 , with an arbitrary number of levels of sets 830 possible . fig8 b depicts an exemplary segmentation of an fefet memory . physical array 840 a comprises multiple segments . segments 851 a , 851 b etc . comprise memory elements within set 830 a , arranged in a certain way . segments 852 a , 852 b , etc . comprise memory elements within set 830 b , arranged in a certain way which is distinct from that of segments 851 a , 851 b etc . segments 851 may include elements of multiple sets 830 , as 853 a comprises minimal addressable memory elements 820 a within sets 830 c , 830 d , etc . similarly segment 853 b comprises minimal addressable memory elements 820 b within sets 830 c , 830 d , etc . without limitation , groupings such as 853 a and 853 can occur across any number of sets 830 or packages 840 . segment 861 includes an arrangement of elements 820 c , 820 d , etc . across multiple sets 830 c , 830 d , etc . segment numbering above 850 is meant to correspond to segments previously described in segmentations 811 and 812 . different numbering patterns are used to distinguish how the segments are grouped together based on the different combinations of possible segments . not all exhaustive embodiments are depicted , but should be assumed to be covered . physical array 840 c comprises multiple segments arranged differently from those of 840 a . segment 862 comprises elements 820 a , 820 c , etc . across multiple sets 830 a , 830 c etc . where said sets are arranged differently from those of set 861 . segments 863 , 864 a , and 864 b comprise elements of multiple sets . fig8 c depicts an exemplary segmentation of an fefet memory . segment 871 comprises a plurality of sets 830 a , 830 c , etc . and 830 b , 830 d etc . arranged in a certain way . segment 872 is similarly comprised of a plurality of sets 830 a , 830 b etc . and 830 c , 830 d etc ., arranged in a certain way which is distinct from the arrangement of 871 . segment 873 a comprises sets 830 a in a plurality of physical arrays 840 b , 840 d , etc . segment 873 b comprises a plurality of sets 830 b , 830 c etc . across a plurality of physical arrays 840 b , 840 d etc . fig8 d depicts an exemplary segmentation of an fefet memory . segment 881 comprises a plurality of physical arrays 840 a , 840 aa , etc . arranged in a certain way . segment 882 comprises a plurality of physical arrays 840 aaa , 840 ccc , etc ., arranged in a certain way which is distinct from that of segment 881 . segment 883 a comprises a plurality of physical arrays 840 b , 840 cc etc . arranged in a certain way . segment 883 b comprises a plurality of physical arrays 840 c , 840 d etc ., arranged in a certain way which is distinct from that of 883 a . the implementation of the segmentation behavior may vary depending on the product using the fefet memory . for example , a graphics card driving displays is likely to have different segmentations than , e . g ., an fefet memory used with the main central processor ( s ). in fact , segmentation may be implemented using , e . g ., physically separate instances of fefet memory that correspond to different types of operations . within a graphics card , certain parts of the screen may be allocated to a lower power segmentation because they are less likely to change from frame - to - frame . in contrast , memory used for computations to represent objects and 3 - dimensional physics would be allocated to a higher power segmentation to address their likely need to change due to the constantly changing nature of the computations . it is important to note that within the virtual segmentation , not all cells need to remain mapped to the same segmentation . in fact , the mapping of individual fefet memory cells may change due to the endurance of the cells , i . e ., the number of times the memory cell can be written to before it is no longer expected to function reliably . by varying the virtual mapping of cells among segments , it is possible to equalize the endurance of individual cells and prevent , e . g ., a failure of one overused cell while other underused cells continue to operate . one embodiment of an approach to achieve such a mapping is to simply randomly assign the cells each time a segmentation occurs , such as when the computer changes from a powered off state to a powered on state . as referenced in fig2 , one embodiment of the invention could be a scenario in which data cache 130 and volatile memory 241 are combined in a single physical fefet memory . in this embodiment , some number of virtual segmentations 811 , 812 , etc . could be implemented to accomplish the same functionality as both the data cache and volatile memory in an embedded application . embodiments of the present disclosure , for example , are described above with reference to block diagrams and / or operational illustrations of methods , systems , and computer program products according to embodiments of the present disclosure . the functions / acts noted in the blocks may occur out of the order as shown in any flowchart . for example , two blocks shown in succession may in fact be executed substantially concurrent or the blocks may sometimes be executed in the reverse order , depending upon the functionality / acts involved . additionally , not all of the blocks shown in any flowchart need to be performed and / or executed . for example , if a given flowchart has five blocks containing functions / acts , it may be the case that only three of the five blocks are performed and / or executed . in this example , any of the three of the five blocks may be performed and / or executed . the description and illustration of one or more embodiments provided in this application are not intended to limit or restrict the scope of the present disclosure as claimed in any way . the embodiments , examples , and details provided in this application are considered sufficient to convey possession and enable others to make and use the best mode of the claimed embodiments . the claimed embodiments should not be construed as being limited to any embodiment , example , or detail provided in this application . regardless of whether shown and described in combination or separately , the various features ( both structural and methodological ) are intended to be selectively included or omitted to produce an embodiment with a particular set of features . having been provided with the description and illustration of the present application , one skilled in the art may envision variations , modifications , and alternate embodiments falling within the spirit of the broader aspects of the general inventive concept embodied in this application that do not depart from the broader scope of the claimed embodiments .