the method proposed by the present invention addresses the problem of testing integrated intellectual property ( ip ) cores through the proper use of insertion of test circuitry and automatic test pattern generation ( atpg ) tools , when used in the context of core based , or core dominated , digital circuit designs . this leads to significant fault coverage improvements , while at the same time , maintaining protection of the proprietary ip core . one technique by which this may be achieved is as follows . an internal scan chain only , partial netlist version of the embedded core in question is first extracted or developed , including only the key input and output logic cones associated with the scan flip - flops which are fed from primary inputs , and including the scan flip - flops which are driving primary output ports or pins of the core extracted . this applies as well to cores without any direct boundary scan implementations . this task may be wholly or partially performed using known software . next , the cells of the netlist are renamed using a generic notation , to eliminate any remnants of functionality to assist in further removing the possibility for reverse engineering of the specific contents of the embedded core . test pattern creation / generation is then performed , first by replacing the existing core with its partial netlist version equivalent ( the scan only “ model ”) in the netlist hierarchy of the design . additionally required top level input pins are introduced for proper scan mode control of the scan only model . the automatic test pattern generation ( atpg ) software is then run , taking advantage of the core visibility available through the scan only model and the added test control it provides . the corresponding appropriate format test pattern files are then generated , and the test pattern files are edited to remove the additional scan only model inputs . according to an alternative embodiment of the invention that is used exclusively with respect to atpg a “ reset or fixed state ” only atpg model of the embedded core is used . this technique is relatively similar to the above , except the focus is not so much ip protection , but rather the controllability of the embedded core output signal . this technique is particularly useful when support for the scan only model ( partial netlist ) extraction is not available for a particular embedded core . according to the alternative embodiment , there is no extraction of any kind from the actual core netlist other than determining the state of the outputs of the embedded core at a know “ reset ” or specific “ fixed ” state ; therefore , no if issues are involved . however , the alternative technique provides a much less desired level of controllability than the “ scan only model / partial netlist ” approach . the alternative embodiment does , however , provide significant improvement over using just the embedded core in a “ black box ” context . the alternative technique first determines the state of the outputs of the embedded core at a known “ reset ” or specific “ fixed ” state through simulation or some other available means , such as device specific documentation . from this information , an atpg model representing this derived “ fixed ” state of the embedded core is constructed . along with this model , just like in the “ scan only model ” case , a corresponding atpg setup sequence , using only the actual top level pins of the design , ( i . e . : no pseudo pins needed ) may be derived as well . the test pattern creation / generation is then performed by running the atpg software on the overall embedded core based design using the newly derived atpg model and test setup sequence . generate corresponding appropriate format test pattern files are generated . since , the design netlist is not changed the resulting pattern files are ready for use as is , without requiring post atpg editing . more particularly , fastscan .™. is one popular automatic test pattern generation ( atpg ) program that is available from mentor graphics corp , wilsonville , oreg ., usa . other programs are available as well . in operation , setup files are provided for the program , and the program automatically generates a set of test vectors that can be applied to test the circuit . the setup files contain a number of things needed for the program to run , which may include , for example , a list of initialization states that may be applied to the circuitry to produce known output results . this enables a circuit designer to append or attach his circuitry to the netlisted circuitry to accomplish his desired customized circuitry . as described above , the netlist of the core circuitry may be a flattened or abbreviated netlist , so that the ip content of the core is not revealed to the user . however , as mentioned , much of the circuitry that will be included in the final circuit design is provided by the core vendor , but is not necessary for design verification / simulation by the custom circuit designer . an example of such additional circuitry is the jtag interface circuitry that may be provided with a dsp , or other similar product . although the atpg software may well develop appropriate test patterns for the jtag circuitry , the test vectors are unnecessary , and , moreover , may be very complicated . as a result , and in accordance with a preferred embodiment of the invention , “ pseudo - pins ” are provided as a part of the setup files provided to the atpg software . pseudo - pins have no circuitry associated with them , and , in fact , do not exist in the physical circuitry . they stand - in for actual circuitry pins for the atpg software . more particularly , the pseudo - pins provide a placeholder to which the test patterns applied to the circuitry may be applied , but without the actual accompanying hardware circuitry , they do not result in the generation of a large number of test vectors by the software . since no physical circuitry is represented by the pseudo - pins , no test vectors are generated , except those that generate the pre - established responses that may be provided in the set - up files . that is , the set - up files may contain the logic states to be applied to the pseudo - pins to produce the desired output states in the actual circuit operation . thus , the pseudo - pins may be used to emulate the expected response by the core circuit , without including the possibly complex circuit netlist . this is particularly useful in the case of an ip core ; that is , a core that has content that is desired to be maintained in secrecy . when the set - up files are delivered to the user they may include only the initial state or setup sequences that emulate the nonproprietary circuitry that the pseudo pins replace . as a result , not only is the test vector generation greatly simplified , but the ip content of the core is maintained , as well . of course , once the atpg software has generated the test vectors to test the actual physical circuitry that is represented by the netlist and other set - up files , the pseudo - pin references must be removed from the test vector files . therefore , when the test vectors are applied to the actual circuitry in its test , the test vectors can be applied to the correct circuitry inputs . as mentioned , the test vectors for the vendor core circuitry ideally would have been already generated by the core vendor . as a result , the final combined circuitry test vectors may be somewhat redundant and unnecessary . with reference first to fig1 , a block diagram of a circuit 10 is shown illustrating one environment in which the invention may be practiced . the circuit 10 includes both vendor embedded circuitry 12 and customer designed circuitry 14 that are integrated onto a single integrated circuit chip 16 . in the embodiment illustrated , the vendor circuitry 12 is a digital signal processor ( dsp ); however , it should be understood that other circuitry may be equally advantageously employed . the vendor embedded circuitry 12 includes both proprietary circuit portions 18 and nonproprietary circuit portions 20 , which are tested in known manner by signals applied via a chain of scan flip - flops 22 . the test signals normally are conducted to the chain of scan flip - flops 22 from a jtag interface circuit 24 , and , after traversing the scan chain 22 are returned through the jtag circuitry via a multiplexer 26 for analysis . the jtag interface circuit 24 , for example , generates test signals according to ieee standard 1149 . 1 , and is shown for convenience as being included within the nonproprietary circuitry 20 . the embedded vendor circuitry 12 is intended to be used by the customer as the core around which the customer desires to design its own circuitry that can take advantage of the capabilities of the core circuitry . however , in order to enable the customer to design its circuitry , sufficient details of the embedded vendor core must be provided to the customer , as described above . the customer designed circuitry 14 includes the core of customer circuitry 28 and a chain of scan flip - flops 30 . at least one output from the embedded vendor dsp 12 is applied as an input to the customer designed circuitry 14 , as denoted by the dotted line 31 . the customer circuitry 28 is tested by signals applied via the chain of scan flip - flops 30 , separately from the test signals applied to the embedded vendor circuitry 12 . the application of the test signals to the scan chain 30 of the customer circuitry 28 may also be sourced from the jtag interface circuit 24 and returned therethrough via the multiplexer 26 . it should be noted , however , that typically the circuitry of the jtag interface circuit 24 is relatively complex , and is mostly , if not entirely , nonproprietary . moreover , in some cases the jtag interface circuit 24 is mostly , if not entirely , used in the testing of the embedded vendor circuitry 12 , rather than the customer designed circuitry 14 . as a result , the inclusion of the circuitry of the jtag interface circuit 24 in the netlist that is provided to the customer to enable the customer to develop its circuitry may unduly complicate the design and test of the customer designed circuitry 14 , and specifically the atpg software development of the test vectors for testing the customer circuitry 28 . for example , when the atpg software is applied to the entire circuit including both the embedded vendor dsp and customer designed circuitry 14 , it must contend with the signal modifications made by the circuitry of the jtag interface 14 . this may add significant time to the generation of the test vectors for testing the final circuits . therefore , according to the invention , some or all of the circuitry of the vendor core may be represented by the “ pseudo pins ” described above in the netlist provided to the customer to enable the customer to use the atpg software to generate its text vectors for the customer circuitry . for example , pseudo input or pseudo pin 25 is shown providing an input to the embedded vendor dsp 12 . since the generation of the test vectors for the customer circuitry is not affected by the operation of the jtag interface circuitry , the pseudo pin approach greatly simplifies and shortens the test vector generation by the atpg . an example of a test netlist that may be furnished to a customer is attached hereto as “ appendix a ”. also shown is a second pseudo input or pseudo pin 27 that may be used , if desired , to emulate other portions of the non - proprietary circuit 20 . it should be noted that the supplied embedded vendor dsp core model and its accompanying jtag interface circuitry in most cases have already been verified by the vendor at the time they are provided to the customer . consequently , when the customer runs an atpg program to generate the test vectors of its own circuitry , it may at least partially duplicate the testing of the previously verified embedded vendor dsp core . after the atpg test vectors have been generated , a removal program may be applied to the vendor supplied netlist to remove the references to the pseudo pins from the netlist . an example of such program is attached as “ appendix b ”. with reference additionally now to fig2 , a block diagram of another circuit 35 is shown illustrating another environment in which the invention may be practiced . the circuit 35 includes both vendor embedded circuitry 36 and customer designed circuitry 38 that are integrated onto a single integrated circuit chip 40 . in the embodiment illustrated , the vendor circuitry 36 again is a digital signal processor ( dsp ); however , it should be understood that other circuitry may be equally advantageously employed . the vendor embedded circuitry 36 includes both proprietary circuit portions 42 and nonproprietary circuit elements 44 , which are tested in known manner by signals applied via a chain of scan flip - flops 46 . the test signals are conducted to the chain of scan flip - flops 46 directly from a jtag interface circuit 48 . in some cases , the jtag interface circuit 48 , for example , generates test signals according to ieee standard 1149 . 1 . in the embodiment of circuitry 35 , it is clear that the jtag interface circuit 48 affects only the embedded vendor dsp 36 , and not the customer designed circuitry 38 . the customer designed circuitry 38 includes circuitry 39 and 41 , which receive outputs 43 from the embedded vendor core circuitry 36 , and two or more chains of scan flip - flops 50 and 52 . at least one output from the embedded vendor dsp or core 36 is applied as an input to the customer designed circuitry 39 and 41 , as denoted by the dotted line 53 . the customer circuitry 38 is tested by signals applied via the chains of scan flip - flops 50 and 52 , separately from the test signals applied to the embedded vendor circuitry 36 ; however , it is noted that some of the inputs to the scan flip - flops 50 are derived from outputs from the embedded vendor dsp 36 . in the embodiment of fig2 , at least some of the functions of the jtag interface circuit 48 are emulated or replaced by one or more pseudo - pins 47 , as shown . also , if desired , other portions of the nonproprietary circuitry 44 may be emulated or replaced by pseudo - pins 49 , as shown . since the functions of the jtag interface circuit 48 and optionally other functions of the nonproprietary circuit 44 are emulated or replaced by the use of the pseudo pins 47 and 49 in combination with the setup states in the set up files , the pseudo - pins and setup files may be used to enable the customer to utilize the atpg software tools to test the customer circuitry in the chip . thus , the pseudo pin approach greatly simplifies and shortens the test vector generation by the use of such atpg tool . again , after the atpg test vectors have been generated , a removal program may be applied to the netlist to remove the references to the pseudo pins . an example of such program is attached as “ appendix b ”. thus , in accordance with a preferred embodiment of the invention , a method is presented for testing a circuit having both an embedded circuit core and appended user circuitry , using atpg software to generate test vectors therefor . the steps of the method are illustrated in fig3 , to which reference is now made . the steps are broken up into two phases , the first performed by the vendor , the second performed by the customer . the process begins with the vendor steps , in which the vendor first generates a partial netlist of the entire embedded vendor core 60 . at least one pseudo pin input is defined for at least some of the circuitry in the partial netlist 62 . also , an output node of the vendor circuit to which the customer circuitry will be connected is identified 64 . thus , it can be seen that according to one aspect of the invention , pseudo - pin inputs may be substituted into the core netlist for at least some of the circuitry , for example the jtag interface circuitry of fig1 and 2 . with this substitution , an abbreviated core netlist of the vendor circuit that includes the pseudo pins and the output node is generated 66 . the abbreviated netlist is then delivered to the customer to enable the customer to develop and append its own custom circuit to the embedded vendor circuit . during the second phase of circuit development , the customer develops its own circuit 68 in the form of a customer netlist . the customer netlist is appended or attached to said abbreviated core netlist with substituted pseudo - pins to produce an abbreviated total circuit 70 . the atpg software is then applied to the abbreviated total circuit to produce a number of circuit test vectors 72 . thereafter , references to the pseudo - pin inputs are removed from the total circuit 74 and the removed original circuitry is substituted back thereinto 76 . finally , the test vectors are applied to the original circuitry . although the invention has been described and illustrated with a certain degree of particularity , it is understood that the present disclosure has been made only by way of example , and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention , as hereinafter claimed .