in conjunction with the description of the preferred embodiment , a web offset printing press will be described . it should be noted , however , that the invention can be utilized on printing presses other than web offset presses . referring to fig1 , a color registration control system 100 is shown and includes a scanning unit or camera assembly 102 and an associated transport system 104 . the transport system 104 can be of a manual or automated design . preferably , an automated design is used such as is known in the art . generally , an automated transport system can include a linear actuator and a motor with a motor controller . the actuator consists of a bar , carriage , coupling mechanism , transport mechanism ( e . g . screw or belt ), and position encoder . optionally , the transport system 104 may also include limit switches , jog buttons ( to allow the operator to move the carriage ), and indicators such as the direction it is moving and whether or not the camera assembly 102 is tracking the register marks . however , it should be noted that other suitable transport mechanisms can also be employed to provide mobility to the camera assembly 102 . the camera assembly 102 takes an acquisition - on - demand image of a web 106 of a printing press 108 and processes the image within the camera assembly 102 . the camera assembly 102 will be described hereafter in operation in conjunction with a color registration control system 100 and color registration controller 110 of a web offset printing press . however , it should be noted that the camera assembly 102 can be utilized on other types of printing presses and in other printing press control systems wherein an image of the moving web is needed such as in ink density color control , cutoff control , ribbon or sidelay control , fanout and cocking control , and web inspection . referring now to fig2 , the camera assembly 102 is shown in detail . the camera assembly 102 includes an outer housing or case 204 . ribs 206 on the housing are utilized to dissipate heat . the camera assembly 102 defines a self - contained package for processing images of the web in a small footprint , in contrast to the scanning function being in one location and the processing in another remote location with a video cable connection therebetween . by including the scanning and processing components all within a single housing or package , the difficulty of transmitting the image data is eliminated and distortion and degradation problems of the image data are significantly reduced . preferably , the housing has width dimension of 4 ″ or smaller . the components contained within the housing 204 of the camera assembly include a light source 208 , an optics assembly 210 , a power supply and interface board 212 , an image sensor 214 on a sensor board 216 , and a main board 218 . with respect to the light source 208 , preferably the light source is a single source and more preferably a strobe light source . a strobe light source freezes the motion of the moving web by firing with a short duration . it should be noted , however , that other light sources such as a strobed set of leds could also be employed . in the preferred embodiment , a strobe illumination assembly 208 is utilized . the assembly 208 includes a strobe bulb 220 , such as a xenon strobe bulb , a high voltage power supply 222 , and a strobe trigger 223 ( fig9 ). when the strobe bulb 220 is fired , the energy in a capacitor is controllable and is transferred into the bulb 220 . the strobe power supply 222 used in the preferred embodiment has a low - voltage trim input that is used to set the capacitor voltage . the low - voltage trim input is further controlled with a d / a converter . with respect to the optics assembly 210 , preferably the assembly 210 includes a lens 224 and a mirror assembly 226 . the lens 224 is for example a f 7 adjustable focus lens having a focal length of approximately 21 mm . as best shown in fig3 and 4 , the mirror assembly 226 includes two flat mirrors 228 , 230 positioned as shown . it should be noted that the mirrors 228 , 230 could have other configurations other than flat such as , for example , concave mirrors . the mirrors are front silvered to eliminate the problem of ghost images and are attached to a mounting housing with an adhesive such as glue or preferably a double - sided adhesive tape . the mounting housing includes stops to aid in the location of the mirrors upon assembly . as best shown in fig5 a and 5b , the mirrors redirect light from the strobe bulb 220 located in - between and , preferably , above the mirrors so that the light is in the same plane as the imaging axis ( lens axis ), that plane being normal to the curved surface of the idler and intersecting the rotational axis of the idler . the mirrors are spaced far enough apart so that no specularly reflected incident light ray will enter the lens 224 and cause glare . the lens 224 is symmetrical about a vertical plane that is orthogonal to the plane in which the incident light and lens axis occur , the intersection of these two planes being a line that is coincident with the lens axis . this symmetry provides uniformity of illumination from each mirror 228 , 230 as such , the mirrors 228 , 230 are designed to receive light from the single light source and create dual light paths of substantially uniform illumination directed toward the web 106 of the printing press 108 as is shown fig5 a and 5b . with the use of a single light source , light source illumination characteristics do not have to be matched to approximate uniform illumination . further , the cost of supply and replacement of a single light source , as compared to a dual light source implementation , is reduced by half . the mirror assembly 226 enables a dual light path to be created with each path being at substantially the same illumination level . the single source / mirror combination also enables the housing 204 of the camera assembly 102 to be of a reduced width dimension enabling the camera assembly 102 to be positioned in locations not otherwise accessible , such as at the web extremities . the smaller profile camera assembly 102 can be positioned at the extremity of the web 106 and not be interfered with by the sideframe of the printing press 108 . referring now to the power supply and interface board 212 within the housing 204 of the camera assembly 102 , it includes a conventional low voltage power supply and conventional communication interfaces . with respect to the image sensor 214 , preferably a ccd area scanner is utilized such as an image sensing device available from texas instruments as model ti tc237b . it would be apparent to those of ordinary skill in the art that other devices such as a cmos image sensor may also be used . the sensor board 216 includes drivers , the image sensor 214 and a ccd signal processor ( csp ) 516 as shown in fig9 as will be described hereafter . in general operation and with reference back to fig1 , the camera assembly 102 functions as follows . upon receipt of an activation signal , the strobe illumination assembly 208 is activated and illuminates the web 106 as shown by arrow a . the reflected light off the web 106 , as shown by arrow b , is received by the image sensor 214 and the resulting image data is processed within the camera assembly 102 . after processing , if it is determined that the camera assembly 102 should be positioned in a different location , such as when searching for color register marks , a move request and a web position are sent to the transport system 104 . the transport system 104 then re - positions the camera assembly 102 either manually or automatically . for example , if automated , the transport system 104 allows an automatic , controlled side - to - side movement . if , however , the transport system 104 is to be operated manually , a status indicator can be activated to indicate to an operator a direction in which to move the camera assembly 102 . the register error , even if zero , will be reported to the color registration controller 110 . an operator can then access the register error and other information such as the system configuration and setup , troubleshoot , or track system operation through an operator control station 112 . referring now to fig6 , typical predefined color register marks 300 , 302 and 304 are shown in a 50 : 1 scale . the mark 304 is preferably used with the present invention and is 0 . 010 ″ to scale . however , it should be noted that other predefined and programmable register marks can be used as will be explained in detail hereafter . fig7 illustrates an exemplary predefined register mark pattern 306 . specifically , in order to control color register , the control system 100 needs to measure the position of the printed color register marks relative to each other , and to correct for any erroneous positions . to measure the positions of color register marks , a plurality of register marks in a register mark pattern 306 are printed on the web 106 such as the exemplary pattern 306 shown in fig7 . the pattern 306 includes four marks of one ink color and one mark of each of the other three ink colors , however , other patterns can also be utilized . ideally , if the printed color register marks match the predefined pattern 306 , color is in register . the camera assembly 102 locates and measures the relationship of the printed marks of each color relative to each other and relative to the predefined pattern 306 . the difference between the locations measured by the camera assembly 102 and the predefined pattern 306 is considered a register error . the procedure then includes sampling the printed marks at a mark sampling rate , e . g . five shots per second , filtering the resulting register error samples , and feeding the register error samples to a control algorithm . the control algorithm then decides how to correct the error . the printing press 108 includes a plurality of register motors that allow small lateral and circumferential adjustments of the printing cylinder relative to the rest of the printing press . the color registration controller 110 performs the error adjustments as is known in the art . even if the printed mark pattern perfectly matches the predefined format 306 , there still might be a residual error . residual error is often generated as a result of plate mounting errors or plate errors introduced in the manufacturing process . an operator measures that error manually and enters an offset into the controller 110 to compensate for the error . thereafter , the controller 110 is enabled to control the corrected ( offset ) pattern . turning now to fig8 , the main circuit board 218 of the camera assembly 102 is shown schematically . the main board 218 includes a processor 400 , preferably an embedded microprocessor such as the 32 - bit motorola coldfire mcf5307 , and a memory module 402 for data and instruction storage . the memory module 402 is operatively coupled to the processor 400 and it further includes a sdram module 404 such as two micron manufacturing mt48lc4m16atg - 75 sdrams , and a field - re - programmable nonvolatile storage / flash memory module 406 such as an intel te28f160c3ba90 flash memory . the sdram module 404 provides , in general , run - time storage of all software instructions and data , whereas the flash memory module 406 stores an operating system , a plurality of fpga bit files , a plurality of configuration parameters , a plurality of diagnostic logs and application executables . it would be apparent to those of ordinary skill in the art that other memory devices such as a dram , a ddr sdram ( double data rate sdram ), a rambus dram , a high speed sram , or the like may also be used . the processor 400 is also operatively coupled to a hardware image processing ( hip ) fpga module 410 such as a xilinx xcv100e fpga , and a video head subsystem ( vhs ) fpga module 412 such as a xilinx xcs30xl fpga which interfaces between the processor 400 and the sensor board 216 . it would be apparent to those of ordinary skill in the art that other devices such as an asic , a cpld , a pld , a dedicated image processing hardware offered by sumitomo metals , a processor with fpga or cpld structure built in , or the like may be used in instead of the fpgas . the processor 400 includes a dma controller 422 as will be explained in more detail below . the main board 218 also includes a lan interface module 414 . the lan interface module 414 includes an ethernet lan controller 416 such as a crystal / cirrus cs8900a isa bus ethernet lan controller ( which provides 10baset connectivity for the camera assembly ) and a lan controller interface ( cpld ) 418 such as a xilinx xc95144xl - 10tq144i . turning now to fig9 , the vhs fpga module 412 and the main components of the sensor board 216 are illustrated . the vhs fpga module 412 includes a plurality of controls and interfaces , such as an encoder interface 502 , a processor interface 504 , an image acquisition control 506 , and a video dma interface 508 . the vhs fpga module 412 generates all of the signals that the sensor board 216 needs in order to operate . the vhs fpga module 412 also functions to interface to an optical rotary encoder 114 ( fig1 ) on the printing press 108 and take an image of the web 106 at a specified location . specifically , the encoder 114 is operatively coupled to the printing press as is known in the art . the encoder 114 provides an indication of the circumferential position of a printing plate and provides high resolution rotational position information directly to or via a position input multiplexer 116 ( fig1 ) to the camera assembly 102 . images of the web 106 are then taken at different circumferential positions by choosing different encoder pulse counts at which the images are taken . based on demand , the processor 400 initiates an image acquisition process , and specifies an encoder pulse count at which an image of the web 106 is taken that corresponds to the desired image . the encoder interface 502 then generates a trigger signal at the encoder pulse count specified by the processor 400 . the encoder interface 502 then signals the image acquisition control 506 to activate the strobe illumination assembly 208 . when the web 106 is illuminated , the reflected light from the web 106 is detected by the lens 224 and the image sensor 214 . in the preferred embodiment , the image sensor 214 is driven by a driver circuit 514 with drivers such as elantec el7202 high speed dual channel power mosfet drivers . the image sensor 214 , located on the sensor board 216 and controlled by the image acquisition control 506 , retains the image in analog form and provides the image as a serial stream of pixels to a ccd signal processor ( csp ) 516 or an image digitizer such as a exar xr98l55 , also located on the sensor board 216 . the csp 516 subsequently converts each pixel to a 8 - bit digital output at a 12 . 5 mhz rate . particularly , the vhs fpga module 412 buffers up the image data ( typically a stream of 8 - bit pixels ) coming back from the sensor board 216 in the video dma interface 508 . when the dma interface 508 has 16 bytes , it issues a dma request to the processor 400 . the dma controller 422 of the processor 400 services the dma request and conducts a burst read of the image data off the vhs fpga module 412 followed by a burst write to the sdram 404 , in either a single address access mode or a dual address access mode , where the single address mode is preferred . the vhs fpga module 412 keeps requesting dma transfers until eventually a full image has been read out and transferred into the sdram 404 via the video dma interface 508 . to solve the problems of synchronization , the vhs fpga module 412 takes direct control of the scanning function by providing an image acquisition - on - demand ability while keeping the image sensor 214 relatively free of charge . if the scanner is allowed to remain idle without being read out , the image sensor 214 would slowly integrate the ambient light and dark current until becoming saturated . in the preferred embodiment , the vhs fpga module 412 includes the auto - clearing mode referring to the period when the vhs fpga module 412 is waiting to be notified to take an image . depending upon the specific image sensor 214 used , pulses should be provided to keep the image areas and storage area clear . depending upon the type of csp 516 used , a steady stream of dark pixels should be provided to maintain a plurality of biases . the auto - clearing mode can be interrupted at any time when an image needs to be taken . when a signal is received to take an image , the auto - clearing mode is stopped , and an integration mode / period is entered . after the integration period is entered , the strobe trigger 223 and the strobe bulb 220 are activated . after the integration period , the vhs fpga module 412 transfers the frame image data from the image area to its storage area , and the data is read out one line at a time . the vhs fpga module 412 also provides the high - speed dma interface 508 to the processor 400 with the processor 400 including the dma controller 422 with a plurality of channels . the dma channels are run in a cycle - stealing mode in which each dma request executes a single transfer of data , e . g . 16 bytes . in traditional non - cycle - stealing - dma , the dma controller 422 is programmed with a source address , a destination address , a count of the bytes in the overall transfer , and a size of each cycle in the transfer . when a dma transfer occurs , the dma controller 422 executes as many cycles as it needs to contiguously complete the entire transfer . when the dma executes the entire transfer at once , a buffer as large as the entire image is required until the image is completely read out of the image sensor 214 , and buffers of such size can increase cost of the system . cycle - stealing dma , in contrast , executes only a single cycle of sixteen bytes every time a dma request is serviced . the vhs fpga module 412 buffers only 16 bytes before it asserts the dma request and then the dma controller 422 steals a bus cycle in order to perform the transfer of data . saving a full image before executing the dma transfer would require an external ram . instead , the preferred embodiment uses a small first - in - first - out ( fifo ) module that can store enough bytes in order to buffer the bytes that are acquired while waiting for the dma controller 422 to respond to a previous request . in one embodiment as an example , the vhs fpga module 412 reads pixels out of the image sensor 214 at 12 . 5 mhz , approximately one pixel every 80 ns , and therefore , sixteen pixels are ready every 1280 ns . executing the dma cycle takes about 7 bus clocks meaning that the vhs fpga module 412 will need about 7 bus clocks × 22 ns = 154 ns of the bus every 1280 ns which is about 12 % of the processor bus bandwidth . in the preferred embodiment , and because the vhs fpga module 412 is basically re - programmable , the fpga design can be adapted or changed very easily to match up with different image sensors . for example , if a cmos image sensor technology is utilized , program changes are necessary at the vhs fpga module 412 in order that it is able to interface to the cmos devices without changing the main board 218 layout . referring now to fig1 , the hip fpga module 410 is shown and includes a dma interface 602 , a pixel histogrammer 604 , a binary correlator 606 , a correlation value histogrammer 608 , a binarizer 610 , a processor interface 612 , and a dma request arbiter 614 . the dma interface 602 is responsible for getting data from the bus . dma data is transferred via high - speed cycle - stealing burst transfers . details of the dma interface 602 are discussed hereinafter . the pixel histogrammer 604 runs on the vhs dma channel and calculates a gray scale histogram each time that the vhs fpga module 412 transfers an image into sdram 404 . the gray scale histogram is used to set the binarization level or the initial conditions of the binarizer 610 , which binarizes the image pixel value to 0 or 1 . the binary correlator 606 includes a correlator and all the logic used to run it and store its results . it can be run on the vhs dma channel or its own dma channel , depending upon how it is programmed . the correlation value histogrammer 608 creates a histogram of the correlation values when the binary correlator 606 is run . the correlation value histogrammer 608 is also used in the event that the correlator 606 produces no or few results , or if the correlator 606 results overflow . it can then be used to calculate an appropriate correlation threshold that could be used on a recorrelation to get a satisfactory number of correlation results . the processor interface 612 is preferably responsible for decoding the processor read , write , and interrupt acknowledge bus cycles , and for recognizing and handling an overall timing of these cycles . part of the address decoding of write cycles occurs within the processor interface 612 . additional decoding is also performed , where appropriate , within other blocks in the hip fpga module 410 , and when the other block has more than one register or a ram with more than one address location . specifically , the dma interface 602 further includes a dma cycle decoder 618 , a histogrammer dma interface 620 , and a correlator dma interface 622 . in an alternative embodiment , the interfaces are dma channel - centric instead of image processing tool - centric . this would approach the histogrammer dma interface 620 and the correlator dma interface 622 with both the first dma channel interface and a dma second channel interface . the main goal of the dma cycle decoder 618 is to look at input signals that indicate whether a dma cycle is occurring and then generate output signals that bracket when the sdram data is valid on the internal data bus so that it can be saved into fifos in the histogrammer and the correlator dma interfaces 620 , 622 respectively . the interface 602 also generates an additional signal for the correlator dma interface 622 to indicate the end of a dma transfer intended for the correlator . common features of the histogrammer and correlator dma interfaces 620 , 622 are a dma fifo with status indication , a fifo read control state machine , and a means to convert from a 4 pixel wide data stream to a 1 pixel wide data stream . the dma fifo is preferably a 64 bit deep by 32 bit wide ( four pixel ) fifo that is operatively coupled to the synchronized internal copy of the processor data bus . the write enable of each dma fifo is fed by the dma cycle decoder data detector 618 . when a dma cycle occurs , the sixteen pixels ( 4 clocks of 4 pixels each ) are saved in the dma fifo . the dma fifo has status outputs that indicate whether it is empty or full . in this case , the dma fifo is considered full if it cannot accept another full dma transfer of sixteen pixels . thus , the dma fifo is considered full if it has more than 48 pixels in it . whenever the dma fifo is not empty , the fifo read control state machine reads out an entry ( e . g . 32 bits , or 4 pixels ) from the dma fifo and generates the proper select signals to conversion means . working together the fifo read control state machine and the conversion means serialize the four packed pixels into a stream of single pixels . this stream of signal pixels can be fed as the input to either the correlator 606 or the histogrammer 604 . the fifo read control state machine also generates a “ valid data ” output that indicates when the stream of single pixels is active . this signal is intended as an enable for the correlator 606 or histogrammer 604 . finally , the dma interface 602 provides a signal that indicates when it is empty , an indicator that it has no more data in its dma fifo being serialized by the fifo read control state machine and the multiplexer . other additional features of the correlator dma interface 622 includes a dma counter and a dma request state machine . the dma counter is preferably programmed with the number of transfers that will occur in the overall dma transfer ( typically a full image ). when the binary correlator 606 is running on its own dma channel , the dma request state machine will generate a dma request to the processor whenever the correlator dma fifo is not full . the dma counter indicates there are more transfers required , and there are no outstanding dma requests , its previous requests have been acknowledged . additionally , the dma interface empty signal for the correlator dma interface 622 will not be asserted unless the dma counter indicates there are no more transfers required . the pixel histogrammer 604 further includes an input multiplexer 624 , a dual - port block ram 626 ( preferably of size 256 × 19 bit ), an incrementer 628 , and a plurality of flip - flops to delay key signals . the input multiplexer 624 decides whether the histogram pixel input or the processor address should access the block ram 626 . when the histogrammer 604 is enabled , the pixel input addresses the block ram 626 . however , when the histogrammer 604 is disabled , the processor 400 can address the block ram 626 in order to read and write from the ram 626 . prior to starting a histogram , all of the locations in the block ram 626 are preferably cleared . when the histogrammer 604 is enabled , each pixel addresses the block ram 626 . this causes the ram entry for that pixel to be read out . that value is then incremented and stored back into the block ram 626 on the other port . the timing is designed to make sure that the incremented value is saved before the next pixel arrives . that allows for two pixels in a row to be the same without causing a problem . turning to the binary correlator 606 , it preferably includes a row storage element 632 , a 16 × 16 pixel binary correlator 634 , a correlator location tracker and decoder module 636 , a correlation thresholder 638 , a correlation peak ram address counter 640 and a correlation peak ram 642 . generally , the binary correlator 606 provides a high - speed hardware - based means of searching for register marks in an image . the binary correlator 606 uses a 16 × 16 kernel which contains a binary image of the register mark . the correlator 606 binarizes the image and , in effect , passes a template over the entire image . for each possible template location within the image , the correlator 606 computes the correlation between the template and the image . locations with a correlation value higher than a programmable threshold are saved . turning now to fig1 , the binary correlator is shown in more detail . the binary correlator receives 8 - bit image data from the dma interface at arrow a . the hip fpga module 410 binarizes the image with the binarizer 610 , and passes that data into a 16 × 16 correlator 634 . the data enters the lower right comer of the correlator 634 . with each new pixel , the data in the correlator 634 is shifted to the left , effectively moving the template to the right within the image . as data passes out of the left edge of the template , it is sent to the row - storage memory element 632 . the row - storage size is fixed at 15 × 640 , which limits the operation of the correlator 634 to images that are 656 pixels wide . in an alternative embodiment , the row - storage size is made variable . the correlation value is calculated at each template location . if the correlation value meets or exceeds the correlation threshold stored in the correlation thresholder 638 and the template is within the area of interest in the image , the correlation and template location are saved in the correlation peak ram 642 . the template position tracker 636 contains a row and column counter to track the position of the lower right corner of the template . it also contains registers that define the area of interest . the correlation peak ram address counter 640 increments when each peak is stored in ram 642 . the correlation peak ram 642 preferably stores 1024 entries . the correlator 634 uses a kernel , the image data , and a kernel mask to calculate the binary correlation . for example , the kernel is a 16 × 16 square that contains a binary representation of a golden template mark . the mask is used to specify which pixels within the 16 × 16 square will be used for correlation and which pixels will be ignored . the image data is a 16 × 16 section of the image that is being correlated upon . in general , binary correlation is simply counting the number of bits within the image data that match the bits in the template . bits that are masked out are ignored . on a pixel by pixel basis , the logic function is : one way to implement the correlation function is to build the mask and kernel each out of sixteen 16 - bit registers , one register for each row . the image data is held in sixteen 16 - bit shift registers to facilitate moving the kernel across the image . in each kernel location , the correlation logic function is applied combinatorially on a per - pixel basis to all pixels in the template . the number of matching bits is added with some type of adder tree . with this implementation , the mask and kernel will each be programmed with a binary bitmap . the preferred embodiment uses look up tables storing the image data in sixteen 16 - bit shift registers , one for each row of the kernel . one row , and the associated logic , is shown in fig1 . each 4 - bit nibble of each shift register feeds a 16 × 3 look up table . each nibble represents one 4 - bit segment of the overall kernel . the shape , correlation function , and mask appropriate for each nibble must be programmed into the look up table . the outputs of all nibble look up tables are added together within rows to compute row correlations . the partial sums for all kernel - row correlators are added together for one overall correlation result . with the look - up - table implementation , the shape of the template mark , the mask , even the correlation function , are all programmed within the look - up - tables . in essence , the preferred binary correlator is a look - up - table based image processor that sums up its look - up - table results . turning back to fig6 and 7 , predefined color register marks 304 and pattern 306 are illustrated . however , as earlier noted , the invention supports the use of programmable color register marks . these marks and patterns can therefore be defined and designed by the used to suit individual application , and allow flexibility . referring now to fig1 , a state diagram of the registration control system 100 according to the present invention . as long as a transport system 146 ( 104 of fig1 ) is not moving , and the press 108 ( fig1 ) is above a minimum speed , an acquisition manager 150 starts to request a plurality of search areas from the search controller 152 , and starts to examine one search area at a time . the search controller 152 then uses the present encoder position , and the press speed ( along with a list of search areas that have been searched ) to pick the next desired area ( out of the list the search areas that have not been searched ) at which the camera assembly 102 is to take a picture . the acquisition manager 150 simultaneously programs an image acquisition at the search area by a plurality of programming steps . these steps include programming the vhs 154 ( 412 of fig8 ) with an acquisition request that provides the encoder count for the picture , programming a hip pixel histogrammer 156 ( 410 of fig8 ) to run on the image as it is unloaded from the vhs 154 , and programming a dma controller 158 ( 422 of fig8 ) to conduct the data transfer for acquisition . the vhs 154 then waits for the encoder 148 to reach the proper area by counting a series of encoder pulses . the vhs 154 sends a pulse to the strobe trigger 223 ( fig9 ), and the strobe bulb 220 is then activated to illuminate the web 106 . the reflected image of the illuminated web is detected by the sensor 214 . the vhs 154 in conjunction with the dma controller 158 then begin the transfer of image to memory , while a histogram is computed on the image by the hip 156 . the dma controller 158 signals the acquisition manager 150 when the full image is acquired and stored in memory . the acquisition manager 150 then signals a software image processor 160 that a new image has been acquired . meanwhile the acquisition manager 150 repeats the step of requesting the next desired search area discussed earlier . the software image processor 160 obtains the results from the hip histogrammer , and calculates a plurality of initial conditions for a hip binarizer 162 ( 610 fig1 ) based upon the histogram obtained . the software image processor 160 then programs the hip binary correlator 164 with data needed to run the correlation , the binarizer 162 with the initial conditions , and the dma controller 158 to conduct the data transfer for the hip 156 . the software image processor 160 then waits for the binary correlator 164 to be complete . once the hip binary correlator 164 completes the binary correlation 164 , it then notifies the software image processor 160 . the software image processor 160 then obtains the correlation results from the hip binary correlator 164 , and releases the hip to process the next image . the software image processor 160 also uses the correlation results and grayscale image data to search for the marks . the software image processor 160 notifies the search controller 152 of image processing results based on a plurality of pattern recognition results . if a partial pattern is found , the search controller 152 moves the transport system 146 to determine if a full pattern is found . if a full pattern is found , the search controller 152 stops searching circumferentially and starts tracking on it . if no pattern is found , the search controller 152 continues the circumferential search .