hereinafter , preferred embodiments of the present invention are described in detail with reference to the drawings , so that those skilled in the art can easily understand the technical idea of the present invention . [ 0024 ] fig8 is a schematic of a 2 - stage amplifying circuit according to an embodiment of the present invention . in fig8 the 2 - stage amplifying circuit according to this embodiment is provided with an amplifying means ( 100 ) for outputting received input signals ( in ) to the output stage ( out ) without change , a detecting means ( 200 ) for generating detection signals as it detects voltage levels in the input signals ( out 1 , out 2 ) to the output transistors of pmos type ( p 5 ) and nmos type ( n 5 ) of the amplifying means ( 100 ), and a load drivability control means ( 300 ) for changing the load drivability of the amplifying means ( 100 ) in response to the detection signals from the detection means ( 200 ). the amplifying means ( 100 ) is a 2 - stage amplifying circuit that first amplifies input signals ( in ), outputs them as stage - 1 amplified signals ( out 1 , out 2 ) through the pmos transistor ( p 4 ) and the nmos transistor ( n 4 ), and amplifies them once again through another pmos transistor ( p 5 ) and another nmos transistor ( n 5 ), and outputs them through the output stage ( out ). its configuration and operation is the same as that of the 2 - stage amplifying circuit shown on fig1 . the detecting means ( 200 ) comprises two schmitt - trigger means ( 31 , 32 ) that detect voltage level changes in the input signals ( out 1 , out 2 ) to the output transistors of the amplifying means ( 100 ) ( nmos transistor ( n 5 ) and the pmos transistor ( p 5 )), and an exclusive or gate ( 33 ) and an inverter ( 34 ) that receive the outputs from the schmitt - trigger means ( 31 , 32 ) and output detection signals ( bstx , bst ) to control the load drivability control means ( 300 ). the first and second schmitt - trigger means ( 31 , 32 ) output a low level signal ( ground level ) when the input signals ( out 1 , out 2 ) become the same level as that of the gate signal ( t 2 ), i . e . the input signal to the pmos transistor ( p 4 ) that outputs amplified signal ( out 2 ). the first and second schmitt - trigger means ( 31 , 32 ) output a high level signal ( source voltage level ) when the input signals ( out 1 , out 2 ) become the same level as that of the gate signal ( t 1 ), i . e . the input signal to the nmos transistor ( n 4 ) that outputs amplified signal ( out 1 ). the load drivability control means ( 300 ) comprises a first control means ( 310 ) that is driven by the detection signal ( bst ) of the detection means ( 200 ) and increases the drivability of the output transistor ( p 5 ) of the amplifying circuit , and a second control means ( 320 ) that is driven by the detection signal ( bstx ) of the detection means ( 200 ) and increases the drivability of the output transistor ( n 5 ) of the amplifying means ( 100 ). the first control means ( 310 ) comprises an nmos transistor ( n 6 ) and a pmos transistor ( p 7 ) that function as switches , and a pmos transistor ( p 8 ) that increases the load drivability in cooperation with the output transistor ( p 5 ) of the amplifying means ( 100 ) using the first amplified signal ( out 1 ) as the gate input . the second control means ( 320 ) comprises an nmos transistor ( n 7 ) and a pmos transistor ( p 6 ) that function as switches , and an nmos transistor ( n 8 ) that changes the load drivability in cooperation with the output transistor ( n 5 ) of the amplifying means ( 100 ) using the second amplified signal ( out 2 ) as the gate input . the output transistors of the load drivability control means ( 300 ), i . e . pmos transistor ( p 8 ) and the nmos transistor ( n 8 ), have a size not less than four times that of output transistors of the amplifying means ( 100 ), i . e . the pmos transistor ( p 5 ) and the nmos transistor ( n 5 ). the operation of the amplifying circuit with variable load drivability is described in the following , with reference to the input / output waveform diagram in fig9 fig1 a and fig1 b , and the operational waveform diagram in fig1 . first , when the input signal level ( in ) to the amplifying circuit does not change , as in the settled region a , the amplified signal ( out 2 ) outputted from the pmos transistor ( p 4 ) stays at the level of the gate signal ( t 2 ) of the pmos transistor ( p 4 ), and the amplified signal ( out 1 ) outputted from the nmos transistor ( n 4 ) stays at the voltage level of the gate signal ( t 1 ). therefore , the two schmitt - trigger means ( 31 , 32 ) respectively output high level signals of source voltage ( vdd ) level and low level signals of ground level . therefore , the detecting means ( 200 ) generates a high level detection signal ( bstx ) and a low level detection signal ( bst ) respectively , through an exclusive or gate ( 33 ) and an inverter ( 34 ), and provides them to the load drivability control means ( 300 ) at the load drivability control means ( 300 ), the first control means ( 310 ) disables the pmos transistor ( p 8 ) by turning on the pmos transistor ( p 7 ) in response to the low level detection signal ( bst ), and the second control means ( 320 ) disables the nmos transistor ( n 8 ) by turning on the nmos transistor ( n 7 ) in response to the high level detection signal ( bstx ). also , because the amplified signals ( out 1 , out 2 ) are no longer delivered to the gate inputs of the pmos transistor ( p 8 ) and the nmos transistor ( n 8 ) when the nmos transistor ( n 6 ) and the pmos transistor ( p 6 ) are turned off , the amplified signal from the pmos transistor ( p 5 ) and the nmos transistor ( n 5 ) of the amplifying means ( 100 ) are output through the output stage ( out ). next , when the input level of the amplifying circuit ( in ) is greatly increased and fast operation of the output stage of the amplifying circuit is required , if the voltage at the output ( out ) is smaller than the voltage at - the input ( in ), as in region b of fig1 , the amplified signals ( out 1 , out 2 ) are lowered to the ground level ( vss ). therefore , the schmitt - trigger means ( 31 ) maintains the high level signal of source voltage ( vdd ) and the schmitt - trigger means ( 32 ) generates the high level signal of source voltage ( vdd ). and the exclusive or gate ( 33 ) and the inverter ( 34 ) respectively generates a low level detection signal ( bstx ) and a high level detection signal ( bst ). at the first control means ( 310 ) of the load drivability control means ( 300 ), the pmos transistor ( p 6 ) is turned on by the low level detection signal ( bstx ), and the amplified signal ( out 1 ) is delivered to the gate input of the nmos transistor ( n 8 ). at the second control means ( 320 ) of the load drivability control means ( 300 ), the nmos transistor ( n 6 ) is turned on by the high level detection signal ( bst ), and the amplified signal ( out 2 ) is delivered to the gate input of the pmos transistor ( p 8 ). therefore , the size of the output stage transistors of the amplifying circuit becomes the sum of the sizes of all the pmos transistors ( p 5 , p 8 ) and the nmos transistors ( n 5 , n 8 ), which greatly increases the load drivability of the amplifying circuit , and greatly reduces the settling time compared with the conventional amplifying circuit , as shown on fig0 . 9 , fig1 a and fig1 b . the pmos transistor ( p 7 ) and the nmos transistor ( n 7 ) of the load drivability control means ( 300 ) are turned off by the detection signals ( bst , bstx ). when the load capacitor is charged , and the output ( out ) of the amplifying circuit approaches the level of the input signal ( in ), and the output signal ( out ) settles at the input signal level ( in ), the amplified signal ( out 2 ) returns to the voltage level of the node ( t 2 ) from the ground level ( vss ). therefore , when the level of the input signal ( in ) does not change ( region a ) as described above , the output signal of the schmitt - trigger ( 32 ) changes to a low level signal of ground level ( vss ). this turns off the pmos transistor ( p 8 ) and the nmos transistor ( n 8 ) of the load drivability control means ( 300 ) and reduces power consumption greatly . next , when the input signal level ( in ) is lowered , like the region d in fig1 where the output signal level ( out ) is greater than the input signal level ( in ), the amplified signal ( out 1 ) approaches the source voltage level ( vdd ), and the schmitt - trigger means ( 31 , 32 ) output high level signals of source voltage ( vdd ). accordingly , the exclusive or gate ( 33 ) and the inverter ( 34 ) respectively output a low level detection signal ( bstx ) and a high level detection signal ( bst ), and the pmos transistor ( p 6 ) and the nmos transistor ( n 6 ) of the load drivability control means ( 300 ) are turned on . therefore , the size of the output stage transistor of the amplifying circuit becomes the sum of the sizes of all the pmos transistors ( p 5 , p 8 ) and all the nmos transistors ( n 5 , n 8 ), which greatly increases the load drivability of the amplifying circuit , and greatly reduces the settling time compared with the conventional amplifying circuit , as shown on fig9 fig1 a and fig1 b . when the load capacitor is discharged fast , the output signal level ( out ) of the amplifying circuit approaches the input signal - level ( in ), and the output signal ( out ) settles at the level of input signal ( in ) as in region e in fig1 , the amplified signal ( out 1 ) returns to the level of node ( t 1 ) from the source voltage level ( vdd ). therefore , when the level of the input signal ( in ) does not change ( as in region e ), the output signal of the schmitt - trigger ( 31 ) changes to a high level signal of ground level ( vdd ). this turns off the pmos transistor ( p 8 ) and the nmos transistor ( n 8 ) of the load drivability control means ( 300 ) and reduces the power consumption greatly . in this embodiment of the present invention , the maximum current through the transistors ( p 5 , n 5 , p 8 , n 8 ) is decided by the w / l size of these transistors , which means that the settling time is decided by these transistors . therefore , when the signal level of the amplified signal ( out 2 ) drops to the ground level ( vss ), it is detected by the detecting means ( 200 ), which increases the drivability through the load drivability control means . when the amplifying circuit is almost settled and the amplified signal level ( out 2 ) returns to the signal level of the node ( t 2 ), this is detected by the detecting means ( 200 ) and causes the load drivability control means ( 300 ) to be disabled . when the amplified signal level ( out 1 ) rises to the source voltage level ( vdd ), it is detected by the detecting means ( 200 ), which increases the drivability through the load drivability control means ( 300 ). when the amplifier circuit is almost settled and the amplified signal level ( out 1 ) returns to the source voltage level , this is detected by the detecting means ( 200 ) and disables the load drivability control means ( 300 ). therefore , when the input signal ( in ) changes , the load drivability is increased to reduce the settling time , and when the input signal ( in ) does not change , the power consumption is minimized . as described above , according to the present invention , when there are changes in input signal level ( in ), it is detected , and causes the load drivability control means to increase the load drivability and to reduce the settling time , and when there is no change in the input signal level , it is also detected and causes the load drivability control means to be disabled , resulting in smaller power consumption . although the technical idea of the present invention has been described in detail in connection with preferred embodiments , it should be obvious that various modifications , additions and alterations may be made to the invention by those skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims .