the present invention is illustrated and described in terms of a particular circuit implementation of an automatic gain control . while the present invention will typically be implemented as a part of an integrated circuit ( ic ), it is contemplated that the present invention may be implemented as discrete component , as a stand - alone ic , or as part of a system on chip ( soc ) or multi - chip system . fig2 illustrates an exemplary implementation in which the agc control voltage ( v agc ) is generated by a charge pump 201 that is driven by a timing controller 203 . clock generator 221 generates a clock pulse t 1 that is synchronized with the frequency of the v out signal . charge pump 201 charges capacitor 211 by applying pulses t 2 and discharges capacitor 211 by applying pulses t 3 . in general , the operating time of the charge pump 201 is relatively short and so the capacitor 211 can be small as compared to capacitor 111 shown in fig1 . this allows capacitor 211 to be implemented as an integrated device in some instances . the instantaneous gain of variable gain amplifier 101 is determined by the v agc signal as applied through buffer 109 . charge pump behavior is determined by the reference voltage values v ref1 , v ref2 and v ref3 . rectifier 217 rectifies the v out signal to produce a signal named v a in the illustrations . in the particular examples , v a is coupled to the inverting input of comparator 207 and 209 , and coupled to the non - inverting input of comparator 205 . v ref1 is coupled to the inverting input of comparator 205 , v ref2 is coupled to the non - inverting input of comparator 207 and v ref3 is coupled to the non - inverting input of comparator 209 . v a is compared to v ref1 by comparator 205 , v ref2 by comparator 207 and v ref3 by comparator 209 . while v a is between v ref1 and v ref3 , the output voltage v out is close to the desired value and so no gain adjustment is required . in this state , the charge pump 201 does not operate . timing controller 203 produces signals t 2 and t 3 so as to keep switches 219 and 221 in an open state . accordingly , capacitor 211 is neither charged nor discharged and v agc remains substantially constant . consequently , the agc loop gain remains substantially constant . when v a goes to a level outside of the “ dead zone ” defined by v ref1 and v ref3 , the output voltage v out has deviated from the desired value and so gain adjustment is required . in the particular example , an increase in v a above v ref1 causes the output of comparator 205 to transition from a logic low to a logic high , and a decrease in v a below v ref3 will cause the output of comparator 209 to transition from a logic low a logic high . timing controller 203 is then enabled to generate pulses t 2 or t 3 that close switches 219 or 221 . during charging , magnitude of the current supplied to capacitor 211 with each pulse of t 2 is determined by variable current source 213 . during discharging , magnitude of the current removed from capacitor 211 with each pulse of t 3 is determined by variable current source 215 . in the particular example , variable current sources 213 and 215 are under control of the output of comparator 207 . preferably , as the magnitude of the difference between v a and v ref2 becomes larger , current sources 213 / 215 are controlled so as to increase the rate at which capacitor 211 is charged / discharged . in this manner the charge pump intervention is proportional to the difference between v a and v ref2 . when v a is close to v ref2 , charge pump current is small and the variation ( increment or decrement ) of v agc is small as well . when v a differs significantly from v ref2 , the charge pump current is high and the increments of increase and decrease in v agc are large as well . in a particular example , when charge pump 201 is operating it charges with a pulse of t 2 or discharges with a pulse of t 3 twice in each cycle of t 1 . the change in v agc with each pulse of t 2 / t 3 is described by : where t is the t 2 / t 3 pulse width , i is the current magnitude of current source 213 / 215 , and c is the value of capacitor 211 . unlike the prior circuit shown in fig1 , the operating time or pulse width of the t 2 / t 3 pulses is fixed by the clock generator 221 and timing controller 203 . hence , each pulse will result in a substantially equal change in v agc , irrespective of the frequency of the input signal . however , t 2 / t 3 may pulse at a wide range of rates and pulse widths to meet the needs of a particular application . the pulse width should be long enough to provide sufficiently rapid charge / discharge of capacitor 211 but at the same time short enough to provide adequately small steps each time t 2 / t 3 are pulsed . smaller steps provide greater granularity in the control of v agc . in a particular example , the charge time t 2 is set to near the discharge time t 3 . as a result , the attack time is substantially equal to the release time . in the example of fig2 , the attack time and decay time ( also referred to as a release time ) that are substantially equal is provided . the measured attack / decay time achieved by a particular implementation is dependent on the input magnitude because the system undergoes a continuous control action and the charge / discharge time of charge pump 211 is regulated to the same value even though the input signal frequency may vary . it will be recalled that in the prior art fig1 , when the input frequency was low , the quantity of charging current added to capacitor 111 each cycle was much larger than is the quantity added during each cycle of a higher frequency input signal . as a result , in order to achieve sufficiently small voltage increments in v agc , a large external capacitor was required for low frequency operation . in accordance with the present invention , since the pulse width of each t 2 / t 3 pulse can be made very short and is independent of the input signal frequency , capacitor 211 ( shown in fig2 ) can be made quite small as compared to capacitor 111 in fig1 . for a case in which there are two t 2 / t 3 pulses per clock , and therefore two incremental steps in the change of v agc each clock pulse , for a given change in v agc ( i . e ., a v agc change from v agc1 to v agc2 ) the attack time ( or decay time ) can be determined from : t attack = t decay =  v agc ⁢ ⁢ 2 - ⁢ ⁢ v agc ⁢ ⁢ 1  2 ⁢ ⁢ δ ⁢ ⁢ v agc ⁢ ( ts ) where ts is the signal cycle ( i . e ., the period for t 2 / t 3 ). from the above equation it is apparent that the decay time can be made substantially equal to the attack time for a given input signal because the current is determined by the input signal amplitude , not the input signal frequency . moreover , the charge pump solution of the present invention allows control over both the rate of increase in v agc as well as the rate of decrease in v agc . the above equation also shows that the attack or decay time is a multiple “ n ” of the signal cycle where “ n ” is an integer indicating the number of t 2 / t 3 pulses . in other words , the v agc naturally increases or decrease in a step - wise linear fashion rather than prior solutions in which it was difficult or impossible to cause each increment to change v agc by a uniform amount . fig3 shows waveforms illustrating the operation of a timing controller 203 . the three waveforms shown in fig3 are aligned in time which is represented on the horizontal axis . the vertical axes represent voltage with exemplary voltage levels indicated on the axes for relative comparisons . fig3 illustrates a situation in which the magnitude of v in increases from a peak - to - peak value of about 2 . 5 mv to a peak to peak value of about 30 mv as shown at time point 301 . charging pump 201 functions to quickly and accurately change the gain of vga 101 so that v out experiences little amplitude variance . the waveform labeled v a shows the rectified v out , the waveform labeled t 1 is illustrated as a square - wave superimposed over the v a waveform . it can be seen that t 2 / t 3 pulses are synchronized with the v a waveform . after time point 301 , v a increases or decrease in magnitude such that it is outside of the window defined by v ref1 and v ref3 . consequently , current source 213 or 215 is activated , and timing controller 203 begins to generate t 2 or t 3 pulses . the determination of whether a t 2 or t 3 pulse is generated is determined by whether v a is larger than desired , indicating a need to reduce gain , or v a is smaller than desired , which indicates a need to increase gain . at about time point 302 timing controller 203 beings to generate t 2 or t 3 pulses at times 302 - 313 as shown in the lower waveform of fig3 . in fig3 the t 2 / t 3 pulses are generated on the falling edge of the t 1 clock , however , any convenient arrangement for generating one ore more t 2 / t 3 pulses each clock cycle may be used . fig3 illustrates that v a increases in magnitude immediately after v in increases in magnitude to the point of clipping at the power supply limits . with in a few cycles , however , v a decreases in magnitude as the gain of vga 101 is incrementally reduced over time periods 302 - 313 . after time point 313 v a has been reduced to the point that it is within the upper and lower limits set by v ref1 and v ref3 , at which time timing controller ceases generating t 2 or t 3 pulses . fig4 shows simulated waveforms illustrating attack time response of an automatic gain control circuit in accordance with the present invention with a v in frequency of 1 kilohertz in an “ attack ” example where v in increases from a peak value of about 2 . 5 mv to a peak value of about 30 mv as in the example of fig3 . in fig4 , v out is illustrated rather than v a . in fig4 , v agc generated is illustrated demonstrating how it increases in a step - wise linear fashion with two increments per clock cycle in the specific implementation . each increment is substantially equal in magnitude to each other increment , and there is no discernable non - linear decay or discharge that affects the v agc level . once the timing controller 203 is deactivated v agc remains at a substantially steady level . fig5 shows simulated waveforms illustrating decay time response of an automatic gain control circuit in accordance with the present invention with a v in frequency of 1 kilohertz in an “ release ” or “ decay ” example where v in decreases from a peak value of about 30 mv to a peak value of about 2 . 5 mv . in fig5 , v agc generated is illustrated demonstrating how it decreases in a step - wise linear fashion with two increments per clock cycle in the specific implementation . each increment is substantially equal in magnitude to each other increment , and there is no discernable non - linear decay or discharge that affects the v agc level . once the timing controller 203 is deactivated v agc remains at a substantially steady level . significantly , the process of reducing the v agc value shown in fig5 is substantially analogous to the process of increasing v agc illustrated in fig4 . fig6 and fig7 shows simulated waveforms illustrating attack time response ( fig6 ) and decay time response ( fig7 ) of the automatic gain control circuit in accordance with the present invention at an alternate frequency ( 10 kilohertz ) as compared to the examples of fig4 and fig5 . it is apparent that the response times , in terms of signal cycles , are substantially identical . significantly , the incremental change in v agc for each signal period is identical to that shown in the 1 kilohertz examples of fig4 and fig5 . in the simulated examples , the total attack response time and total delay response time is scaled linearly with frequency , hence , at 10 kilohertz the response times are 10 × shorter than the corresponding times for a 1 kilohertz signal . this is preferable in many cases to the prior art situation in which v agc , and hence gain response , increases faster at lower signal frequency than it does at higher input frequencies . however , because the change in v agc for each t 2 / t 3 pulse is uniform over frequency , it is a simple matter to decrease the frequency of t 2 / t 3 pulses so that the attack / decay response times are substantially similar in an absolute sense ( e . g ., by adding a divider to the t 2 / t 3 pulse generation circuitry so that only one t 2 / t 3 pulse is generated for every ten signal cycles ). although the invention has been described and illustrated with a certain degree of particularity , it is understood that the present disclosure has been made only by way of example and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention , as hereinafter claimed .