the principle of operation of the present invention is described in fig1 . the various figures illustrate several design variations for implementing various embodiments of the invention mi a non - exhaustive manner . different figures employ the similar numbers to label similar components with the leading digit representing the particular figure . thus , in fig1 modulator 102 senses voltage across dc blocking capacitor 100 as the control signal . modulator 102 modulates the output error signal with the control signal . comparator 104 produces the output error signal by comparing the output voltage to a voltage provided by reference 106 in conjunction with a feedback network . the modulated output error signal is , next , applied to comparator 108 of pwm controller 110 . the phase of the control signal is modified so that pwm controller 110 senses voltage variations across capacitor 100 . pwm controller 110 responds to the changes in control signal and the resultant modulated output error signal by adjusting the duty cycle of the half - bridge to control switches 112 and 114 in order to counteract variations in the output voltage . this feedback eliminates the effect of voltage variation across dc blocking capacitor 100 on the output voltage . therefore , the effect of the resonant circuit formed by primary equivalent magnetizing inductance 116 and dc blocking capacitor 100 is removed from the voltage regulating loop . in the design described above , the duty cycle controls the power converter . the pwm controller 110 determines the duty cycle d with the aid of the output of internal comparator 108 . accordingly , the duty cycle is related to the difference of this internal comparator &# 39 ; s inputs , the modulated output error signal and a ramp signal as shown in eqn . 1 . d ≈( v control + v output — error )− v ramp eqn . 1 where v control is the control signal modulating the output error signal v output — error , and v ramp is the ramp signal . fig2 illustrates such an embodiment with modulator 202 receiving the control signal and the output error signal . rearranging eqn . 1 , an equivalent equation is obtained as shown in eqn . 2 . d ≈ v output — error −[ v ramp +(− v control )] eqn . 2 eqn . 2 shows that following rearrangement the introduced control signal can be interpreted to modulate the ramp signal input of modulator 102 of fig1 . of course , in the alternative arrangement the phase of the control signal is inverted as well to ensure consistency . fig3 shows such an embodiment with modulator 302 receiving the ramp signal and the control signal . furthermore , the control signal , v control , in an embodiment of the invention , also functions as a ramp signal . this is possible , for instance , when the slope of the ramp signal is a function of the voltage across the dc blocking capacitor 100 . then removing the separate ramp signal further simplifies the system as is shown in fig4 . the embodiment shown in fig4 consists of a half - bridge converter having output nodes 418 and 420 and a duty cycle ( 1 − d ) and ( d ) produced by pwm controller 410 driving switches 412 and 414 . the switching operation of switches 412 and 414 converts the dc supply voltage from input nodes 422 and 424 to a pulsating voltage across nodes 426 and 424 . transformer 428 receives this pulsating voltage with dc blocking capacitor 400 blocking off the dc component . as shown , transformer 428 , having primary and secondary windings with n 1 and n 2 turns respectively , presents magnetizing inductance reflected to the primary side as inductor 416 . the aforesaid pulsating voltage is coupled to the secondary winding and rectified in half - wave configuration by diodes 430 and 432 . the rectified current / voltage is then filtered to remove ripples by output filter formed by inductor 434 and capacitor 436 to provide smooth dc voltage output across output nodes 418 and 420 . the ramp signal received at comparator 408 in pwm controller 410 following modulation provides inner loop compensation as described previously . however , instead of using a constant ramp signal and like techniques , it is possible to employ a variable ramp signal . several components , namely controlled current source 438 , capacitor 440 and switch 442 generate this variable ramp signal in an embodiment illustrated in fig4 . in fig4 current source 438 has an amplitude proportional to the control signal sensed across dc blocking capacitor 400 with proportionality constant k . switch 442 discharges capacitor 440 after duty cycle d is determined by the pwm controller . the following analysis although described in the context of fig4 to illustrate the operation of the invention , is not intended to be limiting on the scope of the claimed invention . thus , the slope of the modulated voltage ramp signal m is m = i current   _   source c current   _   source eqn .  3 this slope is not constant and depends on the voltage across blocking capacitor 400 . thus , m = k · v control c current   _   source eqn .  4 where v control is the voltage across blocking capacitor 400 , k is the proportionality constant and c current — source is the capacitance of capacitor 440 . node 424 is the reference node for measuring voltage . the pwm controller 410 compares the ramp signal and the output error signal to produce duty cycle d . it can be shown that v output   _   error = k · v control · d f sw · c current   _   source eqn .  5 where v output — error is the output error signal with node 424 being the reference node and f sw is the switching frequency of the converter . s · l induct · δi induct =( 1 − d )· δ v input − δv control eqn . 6 where v input is the input voltage , v control is the voltage across blocking capacitor 400 , v output — error is the output error feedback voltage , and v o is the output voltage across output nodes 418 and 420 . δ represents the small perturbation of the parameter on its right hand side . d , i rectified and v control are the steady state values of d , i rectified and v control respectively . eqn . 10 is obtained directly by adding perturbation to eqn . 5 which is the effect produced by the inner compensation loop . solving eqn . 6 - 11 gives the transfer function from the output error feedback voltage , v output — error , to the output voltage v o . this result is shown in eqn . 12 . δ   v o δ   v output   _   error = n 2 n 1 · f sw · c current   _   source k · 1 1 + s 2 · l ripple   _   filter · c ripple   _   filter eqn .  12 eqn . 12 shows that the transfer function from the output error feedback voltage , v output — error , to the output voltage v o is second order , depending on the output filter formed by l ripple — filter and c ripple — filter . this transfer function is independent of primary magnetizing inductance 434 and the dc blocking capacitor 400 due to the presence of the inner compensation loop . the above calculations show the effect of inner loop compensation by using a voltage proportional to the voltage across the dc blocking capacitor , e . g ., capacitor 400 , to produce the ramp signal . since the modulation signal is already a ramp signal , no extra ramp signal is required . the voltage variation on the dc blocking capacitor 400 introduces corresponding change in the duty cycle for controlling switches 412 and 414 to regulate the output voltage . thus , the effect of the resonant circuit formed by the primary reflected magnetizing inductance and the dc blocking capacitor is removed and the control loop is greatly simplified and made more stable . fig5 shows an embodiment of the invention . resistor 548 and capacitor 540 produce the voltage ramp signal for the pwm controller 510 and switch 542 . resistor 548 connected to the dc blocking capacitor 500 detects the voltage variation across capacitor 900 . the charging current injected to capacitor 540 is approximately equal to the voltage across capacitor 500 divided by the resistance of resistor 548 if the voltage of the ramp signal is much smaller than voltage across capacitor 500 . this is also an illustrative example of the controlled current source described previously . the duty cycle d responds to the voltage variation of capacitor 500 to cancel out or reduced the effect on the output voltage v o . this performs the inner loop compensation that removes or reduces the effect of the resonant circuit formed by the primary reflected magnetizing inductance 516 and the dc blocking capacitor 500 . fig6 and 7 show comparison of the gain plot and phase plot of the first embodiment without and with inner loop compensation respectively . a constant voltage ramp signal is applied to the pwm controller for the one without inner loop compensation . the circuit parameters used are as follows , l ripple — filter = 1 . 2 uh , the inductance in output filter ; and c ripple — filter = 1200 uf , the capacitance in the output filter . the resonant frequency of the resonant circuit formed by the primary reflected magnetizing inductance 516 and the dc blocking capacitor 500 is around 1 . 7 khz and the resonant frequency formed by the output filter elements 534 and 536 is around 4 khz . specifically , fig7 shows significant suppression of the effect of the resonant circuit elements inductor 516 and capacitance 500 in comparison with the fig6 in which no inner loop compensation is implemented . fig8 shows another embodiment of the present invention which employs an additional winding 854 to sample the voltage accross dc blocking capacitor 800 . specifically , inner loop compensation is applied to a half - bridge converter with full wave rectification . two switches 812 and 814 are driven with duty cycle ( 1 − d ) and ( d ) respectively by the pwm controller 810 . the switching operation of switches 812 and 814 converts the dc supply voltage from node 822 and 824 to a pulsating voltage coupled to the main transformer 828 through a path including the dc blocking capacitor 800 . turning on switch 814 in accordance with duty cycle d applies the voltage across capacitor 800 to winding 856 of the main transformer 828 . moreover , this voltage is reflected onto coupled winding 854 of transformer 828 . thus , turning on switch 814 obtains , through winding 854 , a voltage that is a function of the voltage across the dc blocking capacitor 800 . rectifier 852 and the phase of the winding 854 are arranged to produce the required voltage for the output error signal modulation . this voltage is a function of the voltage across the dc blocking capacitor 800 with the correct phase as described previously in order to ensure effective inner loop compensation . the modulation adjustment network 802 adjusts the level of modulation to suit pwm controller 810 . fig9 illustrates an embodiment employing two resistors 956 and 958 to implement modulation network 902 similar to modulation network 802 . to this end , the following equation shows the modulated error signal vmod output error at the input to comparator 908 of pwm controller 910 with the drop across diode 952 ignored . v mod   _   output   _   error = 1 r 956 + r 958 · (  v output   _   error · r 956 - v control · n 4 n 1 · r 958 ) eqn .  13 v output — error is the output error signal , v control is the voltage across the dc blocking capacitor 900 , n 4 and n 1 are the number of turns of winding 954 and the number of turns of winding 960 respectively while node 924 serves as the reference node in the above expressions . another embodiment extends the present invention to a full bridge converter as shown in fig1 . fig1 illustrates dc input applied to input nodes 1022 and 1024 . switches 1012 , 1013 , 1014 and 1015 are connected in full bridge configuration and driven by duty cycles d 1 , d 2 , d 3 and d 4 respectively to convert the dc input to a pulsating voltage coupled to transformers 1028 and 1029 . the dc blocking capacitor 1000 prevents dc from entering transformers 1028 and 1029 . the ac pulsating voltage couples to the secondary windings followed by rectification at rectifiers 1030 and 1032 . a low pass output filter formed by inductor 1034 and capacitor 1036 provides a smooth dc output by reducing ripples . the ramp signal for the pwm controller 1010 is modulated by the voltage across the dc blocking capacitor 1000 through the controlled current source i constant — current 1038 . the operational principles behind the functioning of this embodiment are similar to those illustrated previously except that the present embodiment extends to a full - bridge converter . the duty cycles d 1 , d 2 , d 3 , and d 4 obtained from the pwm controller 1010 for driving the four switches 1012 , 1014 , 1013 and 1015 are adjusted in response to the modulated ramp signal . of course , in this arrangement , voltage variation across capacitor 1000 is reflected in the modulated ramp signal to produce the desired inner loop compensation . therefore , there are disclosed several designs and principles for designing a power converter for dc to dc voltage conversion to generate a desired and easily regulated output voltage . such a power converter includes input terminals for receiving power , at least one switch coupled to the input terminals to generate a variable current in accordance with a duty cycle ; a magnetic component suitable for transforming the variable current to generate a transformed current ; an input capacitor coupled to magnetic component ; a rectifying circuit for rectifying the transformed current to generate a rectified current ; a filter for smoothing the rectified current at output terminals ; a feedback network generating an error signal reflecting deviation of a voltage at the output terminals from a desired reference ; and a controller receiving the error signal , sensing the voltage across the input capacitor and responsive to a ramp signal for generating driving signals to operate the at least one switch in accordance with the duty cycle whereby the power converter operates as a closed loop feedback system . variations and enhancements include different modulation schemes , use of current sources , different methods for sampling the voltage across one or more blocking capacitors of interest and extension to full - bridge power converter design . although the preceding description of the invention is in the context of the embodiments described herein , this is not intended to be a limitation on the scope of the invention . as readily recognized by one of ordinary skill in the art , the disclosed invention encompasses the disclosed embodiments along with other embodiments providing different filter configurations , diodes , rectifiers and magnetic materials . these variations are intended to be within the scope of the following claims .