embodiments of the present invention are directed to a method and apparatus for selecting an internal address having reduced current consumption . certain details are set forth below to provide a sufficient understanding of the invention . however , it will be clear to one skilled in the art that the invention may be practiced without these particular details . in other instances , well - known circuits , control signals , and timing protocols have not been shown in detail in order to avoid unnecessarily obscuring the invention . fig4 illustrates an address selection circuit 400 according to an embodiment of the present invention . the address selection circuit 400 includes a transfer gate 402 having an input to which one bit of the external address is applied and an output coupled to a latch circuit 420 . the transfer gate 402 couples the external address applied to the latch circuit 420 in response to a high ara signal . a transfer gate 404 is also included in the address selection circuit 400 . the transfer gate 404 has an input to which one bit of the cbr address is applied and an output coupled to the latch circuit 420 . the output of a two - input nor gate is coupled to the control terminals of the transfer gate 404 . thus , the transfer gate 404 couples the cbr address applied to its input to the latch circuit 420 in response to either an auto - refresh command signal aref_h or a self - refresh command signal sref_en having a high logic level . the operation of the address selection circuit 400 will be explained with respect to the timing diagram illustrated in fig5 . as previously discussed with respect to the timing diagram of fig3 the ara signal is strobed twice during a memory access operation . as illustrated in fig5 the ara signal is active a first time between times t 0 and t 1 to latch a row address corresponding to the row of memory that will be activated during the memory access operation . the ara signal is active a second time between times t 2 and t 3 to latch the row address of the row of memory to be deactivated to complete the memory array access operation . in response to the ara signal becoming high at the time t 0 , the transfer gate 402 couples the external address applied to its input to the latch circuit 420 to be stored . as the ara signal transitions low , the transfer gate 402 merely decouples the external address from the latch circuit 420 . however , because the external address is latched while the ara signal is active , the latched external address remains valid until either transfer gates 402 or 404 couple a new row address to the latch circuit 420 . consequently , the internal address provided by the address selection circuit 400 does not transition upon the . ara signal returning low , unlike the conventional address selection circuit 200 ( fig2 ). the internal address transitions a second time when the ara signal strobes for the second time at the time t 2 . again , as with the first time the ara signal is strobed , the external address is latched by the latch circuit 420 when the transfer gate 402 is activated by the ara signal and remains valid after the ara signal returns to a low logic level at a time t 3 . where the auto - refresh or self - refresh mode is enabled , an active auto - refresh command signal aref_h or self - refresh command signal sref_en is generated and provided to the nor gate 408 . either an active aref_h or sref_en signal will enable the transfer gate 404 to couple the cbr address to the latch circuit 420 for provision to the row address latches / decoders as the internal address . after an auto - refresh command is issued and subsequently becomes inactive , the cbr address remains latched until a new address is provided to the latch circuit 420 . in a self - refresh mode , the multiplexer can be made to remain on for the duration , or clocked as the other signals , depending on the state of the self - refresh mode enable signal sref_en . it will be appreciated that those of ordinary skill in the art will have a sufficient understanding of the present to generate the ara signal and the aref_h and sref_en signals in a coordinated fashion such that only one of the transfer gates 402 and 404 are active at a given time to avoid address contention . comparing the timing diagram of fig4 for the address selection circuit 400 and the timing diagram of fig2 for the conventional address selection circuit 200 , it is apparent that the unnecessary transitions of the internal address that occurred at times t 1 and t 3 for the conventional address selection circuit 200 are avoided by the address selection circuit 400 . consequently , the current consumption of the address selection circuit 400 is less than that of the conventional address selection circuit 200 . in summary , embodiments of the present invention avoid the unwanted transitions in the internal address by neither providing the cbr address or the external address as a default . instead , embodiments of the present invention select whether to provide the cbr address or external address through a command signal , and subsequently latching the address that is to be provided as the internal address . the ara signal continues to be the external row address selection signal , which allows the external address to be latched . however , when the ara signal becomes inactive , the internal address signal remains valid until receiving a subsequent active ara signal , or an auto - refresh or self refresh enable signal , which couples the cbr address to the latch circuit . fig6 is a block diagram of a computer system 600 including computing circuitry 602 . the computing circuitry 602 contains a memory 601 , that can be a volatile memory , such as a dram , or a non - volatile memory , such as a flash memory . the computing circuitry 602 could also contain both a dram and flash memory . the memory 601 includes charge pump circuitry having oscillator circuitry according to embodiments of the present invention . the computing circuitry 602 performs various computing functions , such as executing specific software to perform specific calculations or tasks . in addition , the computer system 600 includes one or more input devices 604 , such as a keyboard or a mouse , coupled to the computer circuitry 602 to allow an operator to interface with the computer system . typically , the computer system 600 also includes one or more output devices 606 coupled to the computer circuitry 602 , such output devices typically being a printer or a video terminal . one or more data storage devices 608 are also typically coupled to the computer circuitry 602 to store data or retrieve data from external storage media ( not shown ). examples of typical storage devices 608 include hard and floppy disks , tape cassettes , and compact disc read - only memories ( cd - roms ). the computer circuitry 602 is typically coupled to the memory device 601 through appropriate address , data , and control busses to provide for writing data to and reading data from the memory device . from the foregoing it will be appreciated that , although specific embodiments of the invention have been described herein for purposes of illustration , various modifications may be made without deviating from the spirit and scope of the invention . accordingly , the invention is not limited except as by the appended claims .