the present invention provides a system and method for fso communication with fading resistance , high spectral efficiency , and protocol independence . a delayed diversity approach is taken , based on ultra - dense wavelength division multiplexing ( udwdm ) and / or m - ary optical modulation to improve spectral efficiency . ( dense wavelength division multiplexing uses channel spacings of about 50 ghz . udwdm uses channel spacings of about 10 ghz .) it is shown below that the number of redundant channels can be made variable , thus dynamically optimizing spectrum usage based on average link quality . forward error correcting ( fec ) codes are employed as a bad block detector , thus providing an effective means of identifying the block from the valid channel among the available channels . fec codes are also used as a means for correcting data errors . protocol independence is maintained throughout the system , making it usable in all data communication scenarios . the system is shown to be scalable to very high data rates . the present invention includes a method for reliably recombining the delayed channels at the receiver . a shortcoming of the prior art regarding delay diversity [ ref . 4 ] is that the only method described therein for recombining the received channels is through a logical or function with on - off keyed ( ook ) data . while this may make some intuitive sense , it is in fact unworkable . such prior art assumes that when a fade occurs , the photoreceiver produces a logical zero . in reality , all realizable photoreceivers produce a random data output during a fade . the or function then produces a similar random data output , resulting in a corrupted system output alternative solutions are hinted at in a generic sense but none are identified . in the present invention , all of the diverse channels have an added forward error correction code applied to each block of data . referring to fig1 , fec encoder 10 adds the encoding overhead to the input data 11 . the length of the data block and the particular type of fec can be chosen by the system designer based on tradeoffs between coding gain , coding overhead , and hardware complexity . in one embodiment , a conventional ( 255 , 238 ) reed - solomon fec is chosen . the decoding algorithm for reed - solomon provides a status flag showing the success of the decoding process . if the data is sufficiently corrupt , as in the case of a severe fade , the code will fail to completely correct the data and will re port this failure status . this information , in the form of a digital logic bit 22 provided by each of the delayed channel fec decoders 12 , is passed to the output channel selector 24 . the selector can then evaluate each channel on the basis of decoding success or failure , and the first successful channel data 20 , will be passed along to the final system output 26 . a feature of the fec system is that the decoding failure status information can be analyzed statistically in real time to directly measure fso link quality and bit - error - rate of the recovered data . an obvious advantage of using fec codes is the effective improvement in signal to noise ratio , also known as the coding gain . using a sophisticated fec code , such as a turbo product code , can drastically reduce the number of single - bit errors due to conventional wideband noise as well as some short burst errors . in the embodiment illustrated generally in fig1 , the fec encoded user data 14 is split from the original into a at least one , and preferably a plurality of copies by delay means 15 , 16 , 17 into delayed copies 15 ′, 16 ′, 17 ′ respectively , where each copy is delayed in time relative to the original and the other copies . preferably , the delays will be equal and in series . the delays can be created in a variety of ways , e . g ., electronically , physically , e . g ., by transmitting each packet of user data through a length of cable or optically , e . g ., by placing an optical delay between the udwdm laser and the multiplexor . the original and the delayed channels are transmitted over several closely - spaced wavelengths within the ultradense wavelength division multiplexing ( udwdm ) regime by udwdm lasers 18 , 19 , 20 , 21 to produce respective beams 18 ′, 19 ′, 20 ′, 21 ′. this contrasts with prior art [ christopher ] where the chosen wavelengths were in widely - separated optical bands such as visible , near - infrared , and far - infrared . using such diverse wavelengths results in exceptionally difficult optical system design and is also subject to the limited availability of suitable optical components , such as modulators , outside of the bands commonly used in commercial lightwave communications . by choosing udwdm , for instance 10 ghz channel spacing in the 1550 nm infrared band , hundreds of channels can be practically implemented with commercial components . the beams from udwdm lasers 18 , 19 , 20 , 21 are combined , e . g ., in a wdm multiplexor 22 as is known in the art the udwdm lasers may be configured to operate in an on - off keyed mode or a non - return to zero mode . other optical beam combining configurations could be used alternately . the combined beam 23 is transmitted over the desired fso channel and received , e . g ., by wdm demultiplexor 24 . the demultiplexed beams 18 ″, 19 ″, 20 ″, 21 ″ are each detected by respective photoreceivers 25 , 26 , 27 , 28 , realigned temporally in respective receive delays 29 , 30 , 31 , decoded by respective fec decoders 32 , 33 , 34 , 35 before passing into decision logic means 36 which outputs recovered user data 37 . note that the receive delays 29 , 30 , 31 may be alternately located , e . g ., after the fec decoders . in another embodiment ( fig2 ), the delayed channels are transmitted over a single wavelength by employing higher - order optical modulation such as m - ary phase shift keying ( psk ). in prior art [ christopher ], a single wavelength is proposed with two delayed channels carried simultaneously though polarization multiplexing . however , this limits the utilization to two channels per wavelength . it also requires the optical system to be designed with polarization - maintaining components , which can add complexity . in other prior art [ ref . 5 ], m - ary keying is proposed for its increased spectral efficiency but does not address the problems associated with long fades . in the present invention , m delayed channels are mapped into 2 m phase - shifted states of the optical carrier . thus , the advantages of delay diversity are combined with the enhanced spectral efficiency of m - ary keying . in fig2 , delayed data flows into a digital logic circuit configured as an m - ary psk encoder 40 . elements shown in fig2 that are similar or identical to elements of fig1 are given the same reference numbers . the output of encoder 40 drives an optical phase modulator 41 which phase modulates light 42 provided by laser 43 . modulated light 44 is transmitted over the fso link and received by an optical m - ary phase decoder 45 . such decoders are typically based on mach - zehnder interferometers . the separated optical output channels 44 . 1 , 44 . 2 , 44 . 3 , 44 . 4 of decoder 45 drive a set of photoreceivers that turn the optical signals into electrical ook signals . the remainder of the system is similar to that of fig1 . a further advantage of psk is that the information is conveyed in the phase of the optical carrier rather than the amplitude . in the presence of amplitude noise , which is the very nature of atmospheric scintillation as well as conventional electrical and optical noise sources , psk offers improved noise rejection [ ref . 6 ]. other high - order modulation formats are also usable in this system . examples include all the known combinations of amplitude , frequency , and phase modulation . in another embodiment ( fig3 ), with like elements as numbered previously , the delayed channels are transmitted over several udwdm wavelengths , with each wavelength modulated by m - ary keying . this permits a compromise where m is a lower value , such as 2 , which might be necessary to enable operation with an optical channel where the signal - to - noise ratio is insufficient to support higher - order modulation . lower - order modulation is also simpler and cheaper to implement in the figure , qpsk encoder 50 provides a set of signals corresponding to the original packet of fec encoded user data 14 ′ and the first copy 15 ′ that drive optical phase modulator 41 . 1 , which modulates a beam from laser 43 . 1 that is send to wdm multiplexor 22 . similarly , qpsk encoder 51 provides a set of signals corresponding to fec encoded user data 16 ′ and 17 ′ that drive optical phase modulator 41 . 2 , which modulates a beam from laser 43 . 2 that is send to wdm multiplexor 22 . the beams are combined in wdm multiplexor 22 , transmitted across fso channel 23 , recombined in wdm demultiplexor 24 and decoded in qpsk decoders 52 , 53 . the remainder of the system is similar to that of fig1 and 2 . fig4 is exemplary of an embodiment where the number of redundant channels and the inter - channel delay times can be varied dynamically to accommodate changes in fso link quality . for instance , if the observed fading decreases in frequency or length , the number of redundant channels can be reduced , thus allowing a larger total number of data channels to occupy the available optical spectrum . delay times can be dynamically tuned to optimize the performance of the system in response to observed fade statistics . changing delay time is easily accomplished by manipulating memory address pointers . changing the number of channels involves turning specific lasers on or off . a reverse communications channel is required to transmit the desired channel count and delay setting from the receiver back to the transmitter . this reverse channel need not have high bandwidth and could be implemented as either an optical or radio link in the figure , an error statistics computation module 60 reads the decoder status from the fec decoders of the previous embodiments and send a command and control signal 62 to a transmitter 64 and receiver 66 , which adjusts the delay diversity communications transmission system through a memory control / channel control module 68 . block 70 is similar to the previously described embodiments , which did not include the module 68 . another feature of the system presented in this invention is that it is protocol - independent . input data is treated as a simple serial bit stream with no special requirements on data format or coding . the recovered output data is a bit - by - bit copy of the original input . davidson , frederic m ., and koh , yutai t ., “ interleaved convolutional coding for the turbulent atmospheric optical communication channel .” ieee trans . on communications , vol . 36 . no . 9 , september 1988 , pp . 993 - 1003 . shou - kuo shao and ming - seng kao , “ wdm coding for high - capacity lightwave systems ,” journal of lightwave technology , vol . 12 , no . 1 , january 1994 , pp . 137 - 148 . [ 3 ] davis , christopher c . and smolyaninov , igor i ., “ the effect of atmospheric turbulence on bit - error - rate in an on - off - keyed optical wireless system .” free - space laser communication and laser imaging , proc . of spie , vol . 4489 , 2002 , pp . 126 - 137 . ungerboeck , gottfried , “ channel coding with multilevel / phase signals .” ieee trans . information theory , vol . it - 28 , january 1982 , pp55 - 67 . h . nishizawa , y . yamada , y . shibata , and k . habara , “ 10 - gb / s optical dpsk packet receiver proof against large power fluctuations ,” ieee photonics technology let , vol . 11 , no . 6 , june , 1999 pp . 733 - 735 . the following discussion provides implementation details for an embodiment of a fade - tolerant forward error correction ( fec ) system for use in ultra - dense wavelength division multiplexed ( udwdm ) free - space optical ( fso ) communication links . information is presented at the block diagram level with discussions of design options and tradeoffs . a fundamental overview of the delay diversity fec system appears in figure . it consists of a transmitter / encoder ( left side of the diagram ) 80 , a receiver / decoder 82 , and output selection logic 86 . an incoming user data stream passes through a conventional fec encoding process that adds parity bits . copies of the encoded data are delayed by several milliseconds per copy and then transmitted as a set of redundant channels . after passing through the transmission medium , received data is decoded and passed through complementary delays . during decoding , an extra flag is added to each block of data indicating whether each particular block was successfully decoded . data from each redundant channel then reaches the output selection logic where the “ success ” bit is evaluated . the first valid channel is then routed to the final destination . although not shown in the figure , note that error correction is possible in some cases where fading has corrupted a portion of the packet of data . the amount of data that can be corrected depend on the power of the particular fec decoder . a block diagram of the transmitter / encoder section is shown in figure . this illustrates the generation of the first 3 channels of fec encoded data of the previous embodiments , and like reference numbers are employed . data 11 from the user &# 39 ; s data source enters the transmitter / encoder as a serial stream . this is referred to herein as the data path . the output of the transmitter is another serial stream running at a faster rate to accommodate added fec and sync bits . this is referred to herein as the channel path . exact speeds for the two streams must be calculated in advance and very stable clocks must be used to avoid buffer overrun problems . in general , the channel should run slightly faster ( e . g ., 1 %) than calculated . this keeps the transmit buffer empty and has a low risk of overflowing the receiver buffer . user data enters a clock / data recovery ( cdr ) chip 90 that retimes the data and regenerates the data clock . the recovered data clock is divided by n in module 92 , where n is the transmitter &# 39 ; s parallel data path width in bits . data is demultiplexed 1 : n and passed as a stream of parallel words to the fec encoder 10 . demultiplexing is commonly referred to as deserialization , and specialized chips are available to perform this function . the fec encoder adds parity words and may perform interleaving of the data to improve burst error performance . it is important that this encoder and its complementary decoder be highly deterministic in terms of propagation delay . iterative codes such as turbo product codes can be problematic if the iteration count is variable . since the delay coding scheme is so highly dependent upon relative inter - channel timing , it is obvious why these processing delays must be managed . a parallel logic design is required to manage the data rate . an example of a suitable fec encoder available as a vhdl core is the advanced hardware architectures g709d - 2 . 5 , which uses a ( 255 , 237 ) reed - solomon code and has i / o timing features suitable for this design . a start command is given to the fec encoder by the timing and control logic , which keeps track of the number of bytes in each encoded buffer . after encoding , data streams out of the encoder at the higher channel rate and into a sync word inserter 94 . the sync word is a defined bit pattern that appears at the start of each encoded buffer of data . it is used by the receiver to locate start - of - data . a start , or insert , command is given to the sync inserter by the timing and control logic . data from the sync inserter then passes to the delay fifo cascade , which comprises delay fifo 2 ( 96 ) and delay fifo 3 ( 98 ). ( a non - delayed channel 100 is also provided .) this large memory produces the required time delay for each of the redundant data channels . delay time is the channel rate divided by the number of bits stored in the fifo . for instance , a 2 . 5 gbps channel rate requires 2 . 5 mbits of fifo storage per millisecond of delay . fast , high - capacity fifo chips are required and may be cascaded to expand the total storage . fifo width is driven by maximum clock speed : fifo width equals channel rate divided by fifo speed . for instance , 2 . 5 gbps data in a 16 - bit data path requires a 156 mhz memory clock ( 102 ). example devices are the idt terasync series with capacities up to 9 mbit per chip , speeds to 225 mhz , and various widths from 9 to 72 bits . timing and control logic manipulates the read / write pointers and clocks to the fifos . a typical initialization procedure begins with the memory reset and both the read and write pointers set to zero . data is written to memory , with only the write clock active , until the desired number of words are stored . then the clocks are both enabled , thus keeping them locked together but with the desired phase delay . parallel data is clocked out of each delay fifo into a serializer , which is typically implemented as a fast shift register . the serial output runs at the channel speed and is routed to the optical transmitter . delay fifos , each with their associated serializer ( 96 ′ and 98 ′), can be cascaded to create any number of delayed redundant channels . for the non - delayed channel , data 100 from the sync inserter is passed directly to the output serializer 100 ′. alternatively , the entire encoding system could be duplicated for each channel , though that would probably result in an overall increase in complexity and cost . a timing and control subsystem is also required . content of that subsystem is highly dependent on implementation , and it may be diffused throughout the design . main functions are initialization , management of fifo pointers , and synchronization of data flow between functional blocks . figure is a block diagram of the receiver / decoder section of a single channel of the previously described embodiments ; however , the receive delay is implemented after the fec decoder . received channel data , e . g ., 19 ″, in serial format , enters a clock / data recovery ( cdr ) chip 110 that retimes the data and regenerates the channel clock . the recovered channel clock is divided by n ( 112 ), where n is the receiver &# 39 ; s parallel data path width in bits . data is demultiplexed 1 : n ( 114 ) and passed as a stream of parallel words to the sync logic 116 . since fecs operate on blocks of data , the incoming channel data contains a sync word to flag start - of - block . sync logic performs this function , and more . the sync word is detected by a simple pattern matching process . because there may be errors in the raw data , it may be useful to add a tolerance of a few bits to the matching rule . it is also a good idea to search for the inverted version of the sync word as well , because some communications systems may have a logic inversion . if the sync word is found to be inverted , all data must be inverted as well . once the sync word is located , it is discarded , and the ( optionally - inverted ) data is passed to the decoder fifo 118 . a critical timing output from the sync logic is a flag to indicate start - of - block . depending upon the timing and design specifics of the overall decoding system , a small decoder fifo 120 may be required after sync detection . a clock generator 122 provides a stable clock at the user data rate divided by n , where n is the receiver &# 39 ; s parallel data path width in bits . this clock is distributed to the fec decoder and delay fifo 124 , the output decision logic 126 , and the system timing logic . the fec decoder performs de - interleaving , removal of parity bits , and correction of errors . its algorithm must be an exact complement to that used by the fec encoder . in the design given by the aha model g709d - 2 . 5 , some dedicated fifo memory is also required . decoding begins when the required amount of data has been loaded into memory . an appropriate start signal is generated by the system timing logic to trigger decoding when memory is full . when decoding is finished , the decoder generates a complete bit to signal downstream consumers that the first word of a block of data is exiting the decoder . the decoder must also generate an uncorrectable bit if the decoding process has failed to fully correct all errors . this bit is set at the same time as the complete bit . both status bits are combined with the decoded data into a larger parallel word that is passed to the delay fifo . after decoding , parallel data with the uncorrectable and complete bits is sent to the delay fifo . a different delay is required for each of the redundant data channels , and those delays must be equal to the delays chosen for the encoder / transmitter channels . similar memory technology and design would be used here . data and status bits from each of the redundant channel decoders is routed to the output decision logic 36 , shown in figure . this subsystem decides which ( if any ) of the available channels is carrying a valid message , and routes that data to the output which is ultimately connected to the user &# 39 ; s device . a simple sequence of events occurs for each data block . first , the complete bit is detected on each channel , indicating the start of a new packet . simultaneously , any channel may assert the uncorrectable bit , indicating that the following block of data is defective . the first channel with a valid block should be gated to the output . words of data are clocked through continuously by the data clock / n clock . implementation of this subsystem is probably in an asic or fpga , subject to speed limits and data path widths that we have already discussed . if all channels indicate defective data , the system designer has several options . you could take no special action and simply route one channel to the output , with the assumption that the destination device will be able to handle a defective message , perhaps by requesting retransmission . or , the output logic can generate a failure flag to explicitly notify the destination device . the output data could also be set to a pre - defined pattern instead of simply passing along defective data . a timing analysis of the entire system is required to determine how much inter - channel jitter may be expected . if all channels are guaranteed to be within a fraction of a clock cycle at all times , the decision logic design problem is very simple . otherwise , additional buffering and synchronization tricks are required to realign the channels . for instance , each data block could include a sequential serial number , much like ip protocol . with suitable buffering , the decision logic can locate and match serial numbers for sets of data blocks . 1 . communications channel interface hardware . for instance , lengths of cables and fibers and propagation time though various electro - optical components are all constant values ( except for some temperature drift ). it is clear that the delays in these components can easily add up to several nanoseconds , which is an indicator for incorporating de - skewing hardware . 2 . data processing logic . with a competent design , there should be little or no variation in propagation time through the encoder or decoder sides of the system . this is also why an fec algorithm with fixed delay was chosen . 1 . clock - data recovery . recovering a noisy signal and retiming it to picosecond tolerances always results in some jitter . 2 . loss of sync in the receiver deserializer . this results in a bit rotation in the parallel output of the device , which may appear as at least a temporary n - bit delay . 3 . receiver channel response during loss of signal . cdrs are based on phase - locked loops that may rapidly drift and then take some microseconds to re - acquire lock . thus , the channel clock may suffer a transient change in frequency . only the basic architectural design concepts are presented here . there are many implementation - dependent choices that affect design details for a delay - diversity system . a thorough understanding of the particular application is required before embarking on a design , including : 6 . need for flexibility or adaptability , such as channel count or speed ; and these considerations will be understood by those skilled in the art . the upper speed limit is defined only by the state of the art in semiconductors , cost , and willingness to create a complex high - speed digital design . with a reasonable parallel data path width such as 16 bits , 200 mhz asics , and current fifo memory capacity ( 9 mbit chips ), it is reasonable to build a system that operates around 2 . 5 gbps with 10 ms delay . the system can be designed with programmable rates , allowing it to synchronize to virtually any data source . no protocol dependence of any kind is assumed herein . there may be reasons to design the data input / output portion of the system in such a way that it is aware of a particular protocol . for instance , it could operate on ip packets as the basic block of data to which fecs are applied . added deadtime due to the fifo delays can certainly have an impact on protocol performance if handshaking ( acknowledgement ) packets are required . running tcp / ip with a full - duplex link and 10 ms of delay in each direction will result in a packet rate of no more than 50 packets / sec at startup , accelerating as the number of forward packets per ack is increased . other protocols such as udp do not require acks and thus are immune to this problem , but leave the designer with packet sequencing issues . simulations and analysis of data acquired on real fso links will provide an optimal number of redundant channels to implement simple tests indicate that three or four channels are almost always sufficient , and using more than four probably will offer negligible improvements . therefore , a design based on four channels is recommended at this time . note that one or more channels can be freely disconnect without altering the hardware in any way . thus , a two - or three - channel configuration is automatically available with a four - channel implementation . it is also possible to design in a dynamically - flexible channel count . the objective is to increase the maximum link throughput by minimizing the number of channels required to obtain the desired error performance . since the output decision logic supplies a measure of the number of bad blocks received , a real - time statistical technique could be devised to minimize the channel count . information would have to be sent via a back - channel to the transmitter , telling it which channels to activate for what purpose . to overcome a maximum channel fade duration of 10 ms , the total fifo delay on the transmitter needs to be at least 10 ms . this is the current working value based on the present inventors &# 39 ; link data and should be used in initial design efforts . experience with different kinds of links ( e . g ., airborne ) will lead to different recommendations . it would be wise to build flexibility into the design . for instance , fifo pointers could be user - programmable to permit adjustable delays . the tradeoffs here are the number of fifo chips required , versus the robustness of the system with regards to fade duration , versus the added deadtime of long delays . user data can enter and exit the system via serial or parallel interfaces . herein is shown serial data into the encoder and parallel data out of the decoder . there will be no impact on system performance , regardless of choice . in the simplest implementation , each of the redundant channels is assigned to its own optical wavelength . this takes advantage of the abundance of optical bandwidth and the reasonable cost of wdm channels . fundamental to the present work is the ability to use complex modulation ( e . g ., quadrature phase shift keying ( qpsk )) as a means of encoding more than one of the redundant channels onto a single optical wavelength . this increases the total theoretical capacity of an optical link by increasing bandwidth utilization . it reduces the number of optical transmitters and receivers , but may require additional components ( optical , microwave , or digital ) to handle the complex modulation . while non return to zero ( nrz ) modulation is simple , it does not permit multiplexing and has poor amplitude noise rejection . therefore , it is likely that a psk scheme is a worthwhile investment in any case . the foregoing description of the invention has been presented for purposes of illustration and description and is not intended to be exhaustive or to limit the invention to the precise form disclosed . many modifications and variations are possible in light of the above teaching . the embodiments disclosed were meant only to explain the principles of the invention and its practical application to thereby enable others skilled in the art to best use the invention in various embodiments and with various modifications suited to the particular use contemplated . the scope of the invention is to be defined by the following claims .