referring to fig2 , there is shown a block diagram of one embodiment of an optical reader 10 suitable for use in practicing the present invention . reader 2009 includes a scanning section 2011 , which is enclosed by dotted lines at the left side of fig2 . scanning section 2011 includes an illuminator 2012 , such as an led array , a laser , or the like , which produces a light beam represented by outer defining rays 2014 , 2014 ′. the beam strikes a target 2016 on which are found visible indicia , such as 1d or 2d bar code symbols or ocr characters . this light beam is reflected through optics 2019 , the reflected beam being shown representatively as rays 2018 , 2018 ′. optics 2019 projects an image of the indicia onto an image sensor 2022 which , in the embodiment of fig2 , preferably comprises a 1d ccd type image sensor . analog signals developed by image sensor 2022 in response to light incident thereon are received and processed by a signal processing circuit 2024 and an analog to digital converter 2025 to produce a digitized video output signal on an output conductor 2026 . reader 2009 also includes scanning control and decoding circuitry which preferably comprises a programmed microcomputer 2029 together with a dma controller 2032 . in operation , microcomputer 2029 controls the operation of scanning section 2011 and decodes the data produced thereby in accordance with a program stored in a rom 2050 . dma controller 2032 assists microcomputer 2029 by taking over there from the task of receiving digitized video data produced by scanning section 2011 and directing this data through a bus interface 2046 and a bus 2047 to a ram 2048 . dma controller 2032 may also include circuitry which performs a variety of other support and housekeeping functions for microcomputer 2029 and in this way allows the latter to devote more time to decoding activities and thereby increase the data throughput rate for the reader as a whole . if desired , these functions may be integrated into a single application specific integrated circuit ( asic ). one example of an asic of this type is commercially available from welch allyn , inc ., skaneateles falls , n . y . under the part number designation 21203276 - 01 . operation of scanning section 2011 is controlled by a trigger 2028 , which can be a manual trigger , or an automatic trigger that responds to the presence of indicia . trigger 2028 is coupled to microcomputer 2029 via an i / o port section 2033 . microcomputer 2029 outputs a scan enable signal on a line 2034 responsive to the trigger 2028 to turn on scanning section 2011 and begin scanning target symbol 2016 . control signals are output on a line 2036 to control clock generator 2038 which in turn provide suitable enabling signals for illuminator 2012 and clock signals 2042 for image sensor 2022 as required for the proper operation thereof . clock generator 2038 , is also arranged to generate a scan interrupt ( or end of scan ) signal which is applied as an input to i / o port 2033 via conductor 2039 to provide microcomputer 2029 with information that indicates the times at which each block of scan data ends . microcomputer 2029 may also be provided with a uart 2052 and an auxiliary i / o port section 2054 for connecting communications devices ( not shown ) to the reader . representative of such devices are a keyboard when the scanner is employed in a wedge configuration , a telecommunications network , and other devices as may be required for a given application of the system . a typical scan cycle for the reader of fig2 ( a linear scanning device ) is shown in fig2 . during the time period of the scan ( 5 msec is used in the figure , although this can vary ) the cycle begins with illumination pulse 2100 during which the target is illuminated . the target may contain bar code or any other indicia which is amenable to scanning and decoding . during the illumination pulse 2100 , photosensors in image sensor 2022 receive a linear image of the target and convert that image to an electrical representation thereof . this electrical representation is then transferred via a transfer gate 2105 to an analog shift register and clocked with pulses 2110 to shift the image out as an analog signal 2115 . analog signal 2115 is then transformed into a digitized video output signal 2120 by an a / d converter 2025 and output over a line 2026 . video signal 2120 is a digitized representation of whatever high contrast elements were observed during illumination pulse 2100 . the time between successive leading and trailing edges of the video out signal 2120 is then timed using the microprocessor clock counts as a time reference , to produce a timercount representation 2125 of the result of the scan . this timercount representation is preferably produced by timer circuitry , included with dma controller 2032 , which then controls the storage of the resulting timercount representation in ram 2048 , while concurrently the microprocessor may be undertaking other operations including the decoding of prior scan data . referring to fig2 a there is shown a second embodiment 2009 ′ of a reader suitable for use in practicing the present invention . reader 2009 ′ of fig2 a is generally similar to reader 2009 of fig2 , except that it has a scanning section 2011 ′ which includes a 2d image sensor 2022 ′ that processes indicia , such as 2d bar codes symbols , on a full frame rather than line - by - line basis , and a microcomputer 2029 ′ that is programmed to control sensor 2022 ′ and decode output signals produced thereby . because 2d image sensors have many more pixels than a 1d image sensor , the reader of fig2 a will be understood to operate with higher clock rates and to use microcomputers and memory structures that are somewhat different from their counterparts in the reader of fig2 . these differences are differences of degree rather than of kind , however , and do not involve the broader aspects of the present invention , as will be made clear later in connection with fig2 a - 24d . unlike currently available 1d image sensors , some 2d image sensors include much of the control and clock generating circuitry necessary to control their operation . in the reader of fig2 a this fact is reflected by the showing of clock generator circuitry 2038 ′ within the outlines of image sensor 2022 ′. similarly , image sensor 2022 ′ of fig2 a is shown as including on - chip control circuitry 2039 ′ for generating control signals which in the case of the embodiment of fig2 are supplied by microcomputer 2029 . these differences between the readers of fig2 and 21a will be understood to reflect different manufacturer selected groupings of known imaging control circuitry and not to be material to the practice of the present invention . because 2d image sensors produce video output signals that include data for a number of different horizontal rows of the symbols imaged thereby , and are designed to be used without regard to the orientation of the symbol with respect thereto , their outputs are more usefully processed and stored as bit mapped or bit image representations of symbols than as timercount representations thereof . as a result , dma controller 2032 ′ of the embodiment of fig2 a need not include timer circuitry of the type included in dma controller 2032 of the embodiment of fig2 . on the other hand , dma controller 2032 ′ of the embodiment of fig2 a preferably does include circuitry for receiving the “ end of frame ” signal produced by 2d image sensor 2022 ′ and using it as a scan interrupt signal without involving microcomputer 2029 ′. as in the case of dma controller 2032 , dma controller 2032 ′ and the associated scanning control circuitry may be integrated into a single asic . in both embodiments , however , the dma controller is designed to receive and process image data of the type produced by the image sensor with which it is used and to control the storage of that image data in the form and in the quantity best suited to the decoding activity of the microcomputer with which it is used . thus , while dma controllers 2032 and 2032 ′ differ in the specifics of their design , they operate in generally the same way to receive and store image data for decoding by the associated microcomputer with minimal involvement by that microcomputer . with the embodiment of fig2 the stored scan data is a timercount representation of a 1d image of the indicia of interest , as shown in fig2 . because the number of memory locations necessary to store this scan data is dependent upon the number of data transitions in the scan , the length of a complete block of scan data will vary from scan to scan . with the embodiment of fig2 a , however , stored scan data is the bit mapped or bit representation of the indicia of interest . because the number of memory locations necessary to store this scan data depends only on the number of pixels in the 2d image sensor , the length of a complete block of scan data will be the same for each scan . in order to avoid unnecessary repetition , the terms “ scan ” and “ block of scan data ” as used herein will be understood to refer to both of the above - described types of scans generically where the context permits , or non - generically to one or the other of these types of scans where the context indicates that only one or the other is being referred to . for example , the descriptions of fig2 and 24 which follow are framed in generic terms and will be understood to apply to embodiments of the invention which use either 1d or 2d image sensors . the descriptions of fig2 - 29 , on the other hand , will be framed in embodiment - specific terms , except where otherwise indicated . scanning of indicia can take place under either of two generalized conditions , depending upon the decoding load presented by the indicia . under light decoding loads , shown in fig2 a for a prior art reader , the amount of data to be decoded is relatively small , allowing scan data from a complete scan to be decoded in a time which is less than the duration of a scan . under this condition , the result of each scan is decoded before the completion of the following scan , and no problems arise as a result of any mismatch between the scan time and the decode time of the reader . the prior art and the instant invention perform equally well under such light decoding loads as will be seen later from fig2 . under heavy decoding loads , however , prior art methods do not allow sufficient time for decoding . thus , as shown in fig2 b , when a first scan scan 1 is completed , a second scan scan 2 is initiated immediately . scan 2 is then followed by scan 3 while the decoding of scan 1 is still in progress . as this situation continues , the decoding process will be seen to fall further and further behind the scanning process until , at some point , the data memory becomes filled . when this occurs new scan data will overwrite old scan data which was not processed , thereby causing a loss of large blocks of scan data . in the embodiment of the invention disclosed in prior u . s . pat . no . 5 , 463 , 214 , this problem is solved by modifying the reader in a way that allows the scanning process to be suspended and restarted as required to prevent the decoding process from falling so far behind the scanning process that data overflows the memory and is lost . this solution to the problem may be understood with reference to fig2 a and 24b . referring to fig2 a , there is shown the operation of the subject embodiment of the invention under light decoding loads . it will be noted that , under this condition , the relationship between scanning and decoding is the same as that shown in fig2 a . fig2 b shows the relationship which exists between the scanning and decoding processes when the subject embodiment of the invention is used under heavy decoding loads . as shown in fig2 b , the suspension of the scanning process continues until the results of the prior scan have been decoded . this prevents the decoding process from falling more than a small amount of time behind the scanning process . as a result , there cannot arise a situation , such as that which can arise with the prior art , in which there is a massive loss of scan data . because this embodiment of the invention is described in detail in the last - mentioned copending application , it will not be described in detail herein . referring to fig2 c there is shown the tracking relationship which exists between the scanning and decoding operations when these operations are controlled in accordance with a first embodiment of the present invention . with this embodiment , under heavy decoding loads , decoding proceeds without interruption so long as the scanning function is called for . as shown in fig2 c , each decoding operation begins immediately after the preceding decoding operation ends , and proceeds on the basis of the scan data from the then most current complete block of scan data . more particularly , fig2 c illustrates one possible scenario in which decoding of scan 1 data is immediately followed by the decoding of scan 2 data . this occurs because scan 3 data is incomplete at the time that the second decoding operation begins . the decoding of scan 2 data , however , is immediately followed by the decoding of scan 5 data . this occurs because scan 5 data represents the then most current complete block of scan data . while the results of scans 3 and 4 are therefore unused and skipped over , the data lost by their non - use is provided by more current scan data or , if decoding is unsuccessful , by the results of a later scan . any occasional decoding failure that results from the skipping of relatively old blocks of scan data is in any case more than offset by the avoidance of the large scale data losses discussed in connection with fig2 b . referring to fig2 d there is shown the tracking relationship which exists between the scanning and decoding operations when these operations are controlled in accordance with an embodiment of the present invention which includes two and only two scan data memory spaces a and b . with this embodiment decoding does not proceed without interruption . as shown in fig2 d , each decoding operation begins at the beginning of a block of scan data . in the event that the end of a decoding operation does not coincide with the beginning of such a block , i . e ., occurs while a scanning operation is still in progress , the beginning of the next decoding operation will be delayed until the scanning operation that is then in progress is completed , and then proceeds with reference to the block of scan data which is produced by that scanning operation . more particularly , fig2 d shows that the decoding of scan 1 data is completed while scan 3 is still in progress , overwriting data for scan 2 . under this condition , decoding is discontinued for a time period t s1 that is equal to the time necessary for scan 3 to be completed . at the end of time period t s1 , decoding resumes with the then most current block of scan data , namely : the scan data produced during scan 3 . thus , like the embodiment whose operation is illustrated fig2 c , the embodiment whose operation is illustrated in fig2 d begins its decoding operation with the then most current complete block of scan data . referring to fig2 e there is shown the tracking relationship which exists between the scanning and decoding operations when these operations are controlled in accordance with an embodiment of the invention which includes three scan data memory spaces a , b and c . with this embodiment decoding proceeds without interruption so long as the scanning function is called for . as shown in fig2 e , each decoding operation begins immediately after the preceding decoding operation ends , and proceeds on the basis of scan data from the memory which contains the then most current complete block of scan data . more particularly , fig2 e shows that the decoding of scan 1 is completed while scan 3 is still being acquired . under this condition , with three memory spaces available , decoding is immediately undertaken on the most recent complete scan ( scan 2 ) which is contained in memory space b . upon the completion of the decoding of scan 2 , decoding is commenced on scan 4 which is contained in memory space a . thus , the utilization of three memory spaces allows the decoding portion of the invention to be occupied one hundred percent of the time . the embodiment illustrated in fig2 c is best suited for use with readers having memories and addressing procedures which can accommodate large numbers of relatively short blocks of scan data having sizes that are not known in advance . applications of this type typically include readers , such as that shown in fig2 , which use 1d image sensors . the embodiments illustrated in fig2 d and 24e , on the other hand , are best suited for use with readers having memories and addressing procedures which can accommodate small numbers of relatively long blocks of scan data of fixed length . applications of these types typically include readers , such as that shown in fig2 a , which use 2d image sensors . with the embodiment illustrated in fig2 d , only two scan data memory spaces are used and decoding is discontinuous . with the embodiment illustrated in fig2 e three scan data memory spaces are used and decoding is continuous . as will be explained more fully later , more than three scan data memory spaces can be used if additional decoding resources are made available . each one of these different embodiments which is used in a particular application is a design choice which is based on economic considerations . the fact that some embodiments of the invention use 1d image sensors while others use 2d image sensors should not be taken to mean that embodiments which use 1d image sensors can only read 1d symbols or that embodiments which use 2d image sensors can only read 2d symbols . this is because techniques exist for using either type of image sensor to read both 1d and 2d symbols . it will therefore be understood that the present invention is not restricted to use with any one type of image sensor or to any one type of bar code or other optically encoded symbol . referring to fig2 a , there is shown a memory space m1 suitable for use in storing blocks of scan data of the type produced by the reader of fig2 , together with a pointer or tracking memory m2 suitable for use in storing address or pointer information that makes it possible for the reader to identify the beginning and end point of a block of interest . as shown in fig2 a , the block of scan data produced during a first scan of the target is stored in memory m1 beginning at address ss 1 ( scan start for scan 1 ) and ending at address se1 ( scan end for scan 1 ). similarly , the block of scan data resulting from a second scan of the target is stored between addresses ss2 and se2 , and so on . because scanning takes place continuously , the end of one scan block ( e . g . se1 ) coincides with the beginning of the next scan block ( e . g ., ss2 ). the sizes ( in memory space ) of these blocks will ordinarily vary from block to block , depending on the number of data transitions in each 1d scan of the target . the boundaries between blocks will , however , be fixed by the occurrence times of the scan interrupt signals which are generated by the image sensor or its clock generating circuitry . as will be explained more fully in connection with the flow charts of fig2 and 27 , locations ss and se of memory m2 are updated in the course of a series of scans so that they always identify or otherwise point to the address of the beginning and ending of the most recently produced complete block of scan data . as a result , when the decoding circuitry is ready to decode the most recently produced complete block of scan data , it need only refer to locations ss and se to obtain information as to where to begin and end decoding . before decoding begins , the contents of locations ss and se are written into locations ds ( decode start ) and de ( decode end ) so that locations ss and se can continue to be updated while decoding proceeds on the basis of the contents of locations ds and de . in the preferred embodiment , the decoding circuitry is programmed to mark these beginning addresses as “ invalid ” ( for example , by changing its sign ) after it is acquired . since the decoding processor is programmed to decode only “ valid ” data , this assures that it can decode a single block of scan data only once . referring to fig2 b there are shown a plurality of memory spaces ma , mb . . . mn suitable for use in storing blocks of scan data of the type produced by the reader of fig2 a , together with a pointer or tracking memory mp suitable for use in storing address or pointer information for identifying the memory spaces to be used for entering new scan data , decoding , etc . since the amount of scan data in each block of scan data is known in advance , being the same for each scan , the starting and ending addresses for each memory space ( e . g ., a 1 and b 1 and a n and b n ; etc .) will also be the same for each scan . as a result , the memory to be used for storing new scan data , decoding etc . maybe specified by specifying just a few bits stored in memory mp . location cs , for example , may be used as a pointer which identifies the memory where the current scan is being stored , and location ns may be used as a pointer which identifies where the next scanned image is to be stored . similarly , location cd may be used as a pointer which identifies the memory space where the current decode is being undertaken . finally , location nd may be used as a pointer which identifies where the next available image is for decoding purposes . under ordinary circumstances , three scan data memory spaces will be sufficient to keep the decoding activity of the reader fully occupied and current . this is because the tracking method of the invention allows the skipping over of old blocks of scan data as necessary for the decoder to remain occupied and current . if the decoding load becomes extremely heavy , however , it is possible that more old blocks of scan data are skipped over than is advisable . in such instances , it may be desirable to increase the number of memory spaces from 3 to n , where n may be 4 or even more , and to use more than one decoding circuit . if such an increased number of memories and decoders is used , blocks of scan data may be distributed among the memories according to a simple sequential rule and kept track of by increasing the number of bits in the pointers of memory space mp . in addition , the decoding circuits may be assigned to the then most current complete block of scan data as they become free . it will be understood that all such numbers of memory spaces and decoding circuits and the associated tracking procedure are within the contemplation of the present invention . the manner in which the circuits of fig2 and 21a are used with the memory structures of fig2 a and 25b , respectively , to produce the tracking relationships shown in fig2 c , 24d and 24e , respectively , will now be described with reference to the flow charts of fig2 , 27 , 28 and 29 , respectively . referring to fig2 and 27 , there are shown flow charts which illustrate the scanning and decoding operations used by the embodiment of fig2 . these processes are made up of a hardware component which operates independently and simultaneously with the microprocessor to acquire images while the microprocessor is decoding prior images . secondly , a software interrupt routine is triggered by the scanning hardware which maintains the loose linkage between the hardware and the software of the present embodiment . turning first to the scanning process shown in fig2 , this process begins with block 2600 , which causes the scanning hardware to test for whether scanning is enabled by the microprocessor at blocks 2710 and 2745 . if not , the reader cycles through block 2600 and waits . when scanning is enabled , the hardware operation proceeds to block 2605 which illuminates the bar code symbol . after exiting block 2605 , the operation is directed to block 2610 where the operation scans the 1d ccd who &# 39 ; s output is stored by the dma into a memory space . after exiting block 2610 , the operation at block 2615 causes a signal which indicates that a scan has been completed . upon completion , the scanning operation loops back to the beginning of the scanning operation at block 2600 to acquire more scans unless disabled by the microprocessor . referring to fig2 when the end of scan interrupt signal is captured in the microprocessor at block 2750 , the microprocessor halts whatever it was doing . at block 2755 , the address associated with the end of the previously completed block of scan data is set into scan start pointer ss ; this address is the memory address corresponding to the occurrence of the scan interrupt signal at the start of the most recent scan . it also causes the current address contained in the dma pointer to be set into scan end pointer se at block 2760 ; this address is the memory address corresponding to the occurrence of the scan interrupt signal at the end of the most recent scan . this leaves both of the pointers ss and se with valid addresses which bracket the most recent scan . this data is thus immediately available for decoding in accordance with the decoding operations shown in the flow chart of fig2 . at this point after block 2760 , the microprocessor &# 39 ; s operation returns from the end of scan interrupt at block 2765 and resumes what it was previously doing . it is this interrupt routine in conjunction with block 2705 and block 2725 of the decoding process which manipulate the memory pointers and embody the loose linkage between the scanning hardware and the decoding routine undertaken by the microprocessor . such decoding routine is used to decode scan data produced by the above described scanning process and will now be described with reference to the flow chart of fig2 . decoding begins with block 2700 when the processor waits until scanning is called for by , for example , the pulling of trigger 2028 . when scanning is called for , the processor at block 2705 initializes the ss pointer to an invalid number and sets the se pointer equal to the dma pointer which is equal to the beginning address of the top of the first in - first out memory space . after the initialization is completed , the processor at block 2710 enables the scanning hardware at block 2600 to proceed with acquiring scans . at block 2715 , the processor again checks to see if scanning is still called for in order to prevent an unnecessary decode cycle . if not , the processor proceeds to block 2745 and disables the scanning hardware . when scanning is enabled , the processor at block 2720 examines pointer ss to see if it contains a valid address , i . e ., to see if there is a block of scan data which is ready to be decoded . when ss pointer is valid , the processor proceeds to block 2725 which causes it to set decoding start and end pointers ds and de to the addresses contained in ss and se pointers , respectively , which identify the memory space location of the most recent scan data . the processor then sets pointer ss to an invalid value to assure that it does not decode that block of scan data more than once . once the processor has completed the above - described steps , it proceeds with decoding , as called for by block 2730 . if decoding is successful ( block 2735 ), the decoded message is output , as called for by block 2740 , and , if scanning is still being called for by block 22715 , the processor proceeds to block 2720 to commence another decode cycle . if decoding was not successful , no message is output and the processor is looped back to block 2715 to see if scanning is still being called for . since , as explained earlier , scanning takes less time than decoding under heavy decoding loads , there will ordinarily be no operating condition under which the decoder must wait for further valid data . thus , the operation depicted in the flow charts of fig2 and 27 results in the desired continuous decoding action . while , for the sake of clarity , the flow charts of fig2 and 27 illustrate the scanning and decoding operations as proceeding separately and virtually independently , these operations will ordinarily proceed simultaneously ( i . e ., in parallel ) with the scanning operation being undertaken and controlled by hardwired scanning circuitry associated with dma controller 2032 and the enabling of the scanning hardware and decoding operation being undertaken and controlled by microcomputer 2029 . this is because paralleling of the two operations in this way allows the reader to use its processing resources more efficiently and to use less total program memory space . because the programming techniques necessary to perform the scanning and decoding operations on a parallel basis are well known to those skilled in the art they will not be described in detail herein . referring to fig2 and 29 , there are shown flow charts which illustrate the scanning and decoding operations preferably used by the embodiment of fig2 a . these processes are made up of a hardware component which operates independently and simultaneously with the microprocessor to acquire images while the microprocessor is decoding prior images . secondly , software interrupt routines are triggered by the scanning hardware to maintain the loose linkage between the hardware and the software of the present embodiment . turning first to the scanning process shown in fig2 , this process begins with block 2800 , which causes the scanning hardware to test for whether scanning is enabled by the microprocessor at blocks 2910 and 2950 . if not , the reader cycles through block 2800 and waits . when scanning is enabled , the dma pointer is loaded with a value from the next scan pointer ns which points to the start address of the memory space where the next scan data block will be stored . the scanning hardware at block 2810 causes a signal , start of scan interrupt , which indicates that a scan is commencing and which is captured by the microprocessor . the scanning hardware then proceeds to block 2810 to illuminate the image . next , the scanning hardware at block 2820 scans the image sensor and stores its contents in the memory space pointed to by ns . after exiting block 2820 , the hardware causes a signal , end of scan interrupt , which indicates that a scan has been completed and which is captured by the microprocessor . after block 2825 , the scanning operation loops back to the beginning of the scanning operation at block 2800 and proceeds to acquire more images unless disabled by the microprocessor . referring to fig2 when the start of scan interrupt is captured in the microprocessor at block 2955 , the microprocessor halts whatever it is doing . at block 2960 , the current scan cs pointer is set equal to ns . pointer cs will now point to the memory space which will contain the most recently completed scan . the interrupt routine then proceeds to block 2965 where ns is advanced to the next memory space which is not equal to current decode cd pointer which points to the start address of the memory space where the current decoding is to occur . pointer ns will now point to a memory space where the next scanned image can be stored . at this point after block 2965 , the microprocessor operation returns from the start of scan interrupt at block 2970 and resumes what it was previously doing . again referring to fig2 when the end of scan interrupt is captured in the microprocessor at block 2975 , the microprocessor halts whatever it is doing . at block 2980 , the processor checks to see if ns is equal to cs . if ns is equal to cs , then the microprocessor resumes what it was doing without setting next decode nd pointer to a valid value . if ns is not equal to cs , nd is set equal to cs at block 2985 so the decode routine will have a valid nd pointer and know the memory space which contains the next image to be decoded . at this point after block 2985 , the microprocessor operation returns from the end of scan interrupt at block 2970 and resumes what it was previously doing . it is the above interrupt routines in conjunction with blocks 2905 , 2925 and 2935 of the decoding process which manipulate the memory pointers to inform the decoding routine of the most recent image to decode and embody the loose linkage between the scanning hardware and the decoding routine undertaken by the microprocessor . these interrupt and memory pointer routines are independent of any memory constraints such that they work equally well with two , three or more memory spaces . simultaneously and independent of these above functions of the invention , the processor undertakes the decoding of the most recent block of scan data . referring now to fig2 , there will now be described a decoding process suitable for use with the embodiment of fig2 a . the processor begins the decoding routine at block 2900 where the processor waits until scanning is called for by , for example , the pulling of trigger 2028 . when scanning is called for , the processor at block 2905 initializes cd to be marked as invalid to prevent decoding from being attempted before a usable image becomes available . block 2905 also sets nd pointer to invalid and ns pointer equal to the first memory space in which the next image is to be stored . after setting the various pointers , the processor at block 2910 enables the scanning hardware at block 2800 to proceed with acquiring images . at block 2915 , the processor again checks to see if scanning is still called for . if not , the processor proceeds to block 2950 and disables the scanning hardware . when scanning is enabled , the processor waits at block 2920 and examines nd to see if it contains a valid address , i . e ., to see if there is an image which is ready to be decoded . this wait interval may correspond to time intervals t s0 , t s1 , etc . in fig2 d . once a memory space contains a complete image , the processor at block 2925 sets cd pointer equal to nd pointer , thereby informing the decode routine of the memory space location of the most recent image available . the processor at block 2930 decodes the image in the memory space pointed to by cd pointer . at the same time , nd is set to an invalid value to prevent the image in the memory space pointed to by nd from being decoded more than once . once the decode of the image pointed to by cd is complete , the processor sets ns equal to cd and then sets cd invalid at block 2935 to free up the memory space which was pointed to by cd such that newly acquired images can be stored therein ( see block 2965 ). once decoding is complete , at block 2940 a determination is made as to whether decoding was successful . if decoding was successful , the decoded message is output as called for by block 2945 and , if scanning is still being called for ( block 2915 ), the processor loops back to blocks 2915 and 2920 to wait to begin another decoding cycle . if decoding was not successful , block 2940 causes the processor to loop back for a new decoding cycle without outputting any data message . in either case , if scanning is no longer required , the processor proceeds to block 2950 and disables the scanning hardware . as explained in connection with the embodiment of fig2 and 27 , the showing of the scanning and decoding operations of the embodiment of fig2 and 29 in separate flow charts does not mean that these operations are performed separately and independently . it will , therefore , be understood that the scanning and decoding operations shown in fig2 and 29 are preferably performed substantially simultaneously , with the scanning operation being performed by hardwired scanning circuitry associated with dma controller 2032 and the decoding operation being performed by microcomputer 2029 . while this invention has been explained with reference to the structure disclosed herein , it is not confined to the details set forth and this application is intended to cover any modifications and changes as may come within the scope of the following claims : [ end of excerpt of u . s . patent application ser . no . 08 / 516 , 185 , filed aug . 18 , 1995 .] [ the following is an excerpt from the referenced u . s . patent application ser . no . 08 / 205 , 539 , filed mar . 4 , 1994 ]. it is therefore a primary object of the present invention to provide optimal throughput in decoded - output optical scanners . it is another object of the present invention to provide optimal throughput in optical scanners that can be stopped and started instantaneously . it is still another object of the present invention to provide optimal throughput in ccd based optical scanners . it is a further object of the present invention to provide optimal throughput in ccd based bar - code scanners . it is still a further object of the present invention to provide optimal throughput in two - dimensional ccd based bar - code scanners . it is yet another object of the present invention to provide a decoded - output optical scanner where the scanning function waits until decoding of an earlier scan has been completed . these and other objects of the present invention are attained by a method of improving throughput in a scanner whose scanning action is capable of being stopped and started instantly , comprising the steps of a ) storing results of a first scan of a target containing indicia in a first region of a memory and b ) upon determining that the first scan is complete 1 ) decoding results of the first scan 2 ) initiating a second or subsequent scan 3 ) storing results of the second scan of the target containing indicia in a second region of a memory , and 4 ) awaiting completion of the decoding before initiating an additional scan . for a better understanding of these and other objects of the present invention , reference is made to the detailed description of the invention which is to be read in conjunction with the following drawing , wherein : fig3 is a block diagram representing the elements that constitute a decoded - output ccd scanner . fig3 a and b shows schematically the operation of the prior art and the instant invention in scanning under different load conditions . fig3 is a flow diagram showing the preferred embodiment of the instant invention . turning now to the drawing and particularly , fig3 thereof , there is seen a block diagram of a system 3010 that embodies the teachings of the present invention . system 3010 includes a scanning section 3011 , which is enclosed by the dotted line at the left side of fig3 , illuminator 3012 , which can be an led array , a laser , or the like , produces a light beam represented by outer defining rays 3014 , 3014 ′. the beam strikes a target 3016 on which are found visible indicia , such as one or two dimensional bar code or ocr characters . the light beam is reflected through optics 3020 , the reflected beam being shown representatively as rays 3018 , 3018 ′. the optics project an image of the indicia onto image sensor 3022 , which is preferably realized as a ccd array or matrix . signals developed by the image sensor 3022 responsive to light incident thereon are conducted through signal processing electronics 3024 , and a suitably conditioned video signal 3026 is presented to an enhanced microcomputer or microprocessor 3030 . operation of the scanning section 3011 is controlled by a trigger 3028 , which can be a manual trigger , or an automatic trigger that responds to the presence of indicia . the trigger 3028 is coupled to the microcomputer 3030 via an i / o port section 3032 . the microcomputer asserts an enable signal 3034 responsive to the trigger 3028 to turn on the illuminator 3012 and the image sensor 3022 . control signals 3036 are provided for clock generators 3038 that provide suitable enabling signals for the illuminator 3012 , and clock signals 3042 for the image sensor 3022 as are required for the operation of a ccd device . the microcomputer is provided with a timer and dma controller 3044 . the video signal is conducted through a bus interface 3046 onto bus 3049 , and then stored as data at an address in a ram 3048 , the transfer mediated by the dma controller 3044 . the stored data is representative of the optical pattern of the indicia on the target 3016 . while dma access to the ram is preferred for rapidity of operation , other memory addressing techniques can be also used . other conventional provisions include a uart 3052 and an auxiliary i / o port section 3054 for connecting communications devices ( not shown ) to the scanner . representative of such devices are a keyboard when the scanner is employed in a wedge configuration , a telecommunications network , and other devices as may be required for a given application of the system . a rom 3050 contains system programs , and may also contain a program for decoding the data stored in the ram 3048 . of course the program could equivalently reside in ram 3048 , and be loaded therein from a secondary memory storage ( not shown ), or via communications interface 3056 . in this particular embodiment as shown , the decoder is integrated into the scanner , although it could also be external thereto . a typical scan cycle for a ccd scanner is shown in fig3 . during the time period of the scan ( 5 msec is used in the figure , although this can vary ) the cycle begins with illumination pulse 3100 during which brief time period the target is illuminated . the target may contain bar code or any other indicia such as ocr which are amenable to scanning and decoding . during the illumination pulse 3100 period , photosensors in the scanner obtain a linear image of the target which is then transferred via a transfer gate 3105 to the charge coupled device . the ccd is clocked with pulses 3110 to shift the image out to a ccd analog signal 3115 . the ccd analog signal 3115 is then transformed via the microprocessor to a digitized signal termed video out 3120 in fig3 . video out 3120 is a digitized representation of whatever high contrast elements were observed during the illumination period 3100 . this could be the black regions of a bar code , for example . it can be seen that there is not regularity to either the size or the placement of the ‘ 1 ’ and ‘ 0 ’ segments of the video out 3120 . the time between successive leading and trailing edges of the video out signal 3120 is then timed using the microprocessor clock counts 3125 as reference . next the information is then stored in memory 3130 . scanning of indicia can take place under either of two generalized conditions with respect to the information load presented by the indicia . these are there being a light load of information or a heavy load thereof . the situation is set forth in fig3 . the prior art and the instant invention perform equally well under a light load . this can be seen by inspecting the representation of the timing of successive scans and decoding operations of prior art 3135 and the instant invention 3155 under a light information load . each decode of a previous scan &# 39 ; s information can be completed during a subsequent scan . however , under a heavy information load it can be seen that the prior art methods 3140 did not allow sufficient time for decoding . thus , for the method illustrated , after scan1 3141 is completed scan2 3142 is initiated immediately before the decoding of scan1 3143 . scan2 3142 is completed while decode1 3143 is still in progress and so scan3 3144 is initiated . the decoding process falls further and further behind the scanning process until some point where memory is filled and information must be discarded . this contrasts with the heavy information load handling of the instant invention 3160 . again scan1 3161 obtains and stores information in memory . then scan2 3162 is initiated immediately before the decoding of scan1 3165 is begun . however when scan2 3162 is terminated , the decode 3163 is not yet completed . therefore the scanner is halted at 3170 and only restarted at 3171 to perform scan3 3164 when the decode of scan1 3163 is completed . of course immediately after scan3 3164 is initiated , so is the decoding of scan2 3165 . fig3 shows the steps used to accomplish this synchronization of scanning and decoding so that information does not have to be discarded from memory . the scanning process as a whole is initiated in step 3200 by an act such as turning on the power to the scanner or depressing a button or other trigger to initiate the illumination . the first scan is then initiated in step 3203 . this first scan is a special instance as it is the one time , under normal circumstances , that a scan will be initiated without a decoding operation being initiated as well . after this step 3203 the succeeding steps are repeated from one cycle to the next . first a determination is made as to whether the present scan is complete 3205 . this is accomplished via a signal from the scanner to the microprocessor informing the microprocessor that the scan is complete . the signal may either be initiated by the scanner or be a response to a query signal from the microprocessor . once the scan is complete , and the information garnered from the scan has been placed in ram memory , then in the preferred embodiment the last memory location containing information from the previous scan is marked in step 3208 . this can be done using timing information with respect to the last scan . in this embodiment memory is handled as a circular queue ( with each region logically successive to both the prior and subsequent regions of memory ) so as to maximize the use of memory , as only the amount needed for each scan is used by it . however storage of the information can take place using two predetermined blocks of memory where each block is of sufficient size to accommodate the greatest possible information obtainable from a single scan . the information from the scan may have been transferred to memory by any of the techniques that are well known in the art such as , for example , direct memory access . a new scan is then initiated in step 3209 and thereafter the microprocessor begins , in step 3210 , decoding the results from the prior scan that are already completely stored in memory . a determination is then made under microprocessor control in step 3212 as to whether the symbol decoding is successful . this query breaks into two parts : first has the decoding been completed and second has the last collection of information been decoded so as to obtain a valid symbol ? if the decoding is not complete then no new scan is initiated until such time as it is complete — that is initiation of scanning will be prevented . if however the decoding is complete but does not yield a valid results , then the information will have to be discarded and the system will return to wait for the present scan to be completed . if , on the other hand , a valid decode has been accomplished , then a determination will be made in step 3215 , again under microprocessor control , as to whether the entire group of scans has successfully decoded a complete symbol or informational grouping . if not , the system will wait for the completion of the current scan . if so , then in step 3218 the completed group of scans comprising a message will be processed and / or output as directed by the microprocessor using the peripherals which are attached to the system . the process will then end in step 3020 by either having the power disconnected or the button or trigger for illumination released . it can be seen that by practicing this invention information is decoded at a rate that keeps up with the scanning process so that no discarding of stored information due to memory constraints is ever necessary . while this invention has been explained with reference to the structure disclosed herein , it is not confined to the details set forth and this application is intended to cover any modifications and changes as may come within the scope of the following claims : [ end of excerpt of u . s . patent application ser . no . 08 / 205 , 539 , filed mar . 4 , 1994 ]. [ the following is an excerpt from the referenced u . s . patent application ser . no . 08 / 504 , 643 , filed jul . 20 , 1995 ]. in accordance with the present invention there is provided an improved bar code reader which uses a 1d image sensor and yet which is able to read both 1d and 2d bar code symbols . this bar code reader is specially adapted to practice a novel method for one dimensionally and asynchronously imaging a bar code symbol , and acquiring and storing a digital representation of one or more imaged slices thereof . in the case of 1d linear symbols or 1d stacked symbols , these one or more digital representations preferably comprise “ timercount ” representations of the imaged slices , i . e ., representations which record the occurrence times of the transitions occurring within the slices . these slices preferably extend across all of the code bars of each row of the symbol and have a resolution which is sufficient to permit the information encoded in the symbol to be accurately decoded . in the case of 2d matrix symbols , these digital representations comprise “ bit image ” or “ bit mapped ” representations of the imaged slices , i . e ., representations which record the locations of each data element or bit of the imaged slice . when a plurality of successive bit image representations ( hereafter often abbreviated to “ bit representations ”) are considered together , they together comprise a stored representation in which the bits making up the symbol are stored or mapped in memory space in a way that is closely related to the way in which the bits making up the symbol are positioned in the physical space of the printed symbol . because of this close relationship , the bit representation , once acquired and stored , can be used and decoded in much the same way as a 2d image which has been acquired and stored by a 2d bar code reader , once its finder pattern has been identified and located . significantly , the reader of the invention may be used with both 1d and 2d bar code symbols , provided that it is equipped with software that enables it to distinguish between the various types of bar code symbologies that may be used . in the case of distinguishing between 1d and 2d symbols , this comprises software which enables the reader to distinguish between 1d bar code symbols and 2d bar code symbols and , if it is a 1d symbol , to decode the symbol using one or more timercount representations thereof . in the case of distinguishing between the various kinds of 2d symbols , this comprises software which enables the reader to successively test for the presence of the finder patterns that are characteristic of the different 2d bar code symbologies and , when the finder pattern has been identified , to decode the symbol using the stored bit representations thereof . the accomplishment of these two results is facilitated by the fact that the reader of the invention generates both timercount and bit representations of the symbol substantially simultaneously and in real time . as will be explained more fully presently , one important advantage of the present invention is its ability to determine , solely from information contained in a succession of imaged slices or scans , when to stop acquiring data from the 2d symbol . the present invention accomplishes this by examining the bit representations of successive imaged slices , substantially in real time , for indications of the presence of the types of finders that are used with 2d bar code symbologies . among these finders are “ peripheral ” type finders , such as those used with the datamatrix symbology , “ waistband ” type finders such as those used with the code one symbology , and “ central ” or “ bullseye ” type finders , such as those used by the maxicode and aztec symbologies . the last mentioned symbology is described in copending u . s . patent application ser . no . 08 / 441 , 446 , filed may 15 , 1995 , entitled “ two dimensional data encoding structure and symbology for use with optical readers ”. with “ bullseye ” type symbologies , the presence of the central finder is indicated by the emergence of easily recognized numerical patterns that are derived from the above - mentioned succession of bit representations using a new finder identifying algorithm to be described hereinafter . with the “ peripheral ” and “ waistband ” type finders , the finders may be identified by means of the known finder identifying algorithms for the datamatrix and code one symbologies . if symbols with more than one type of finder are being autodiscriminated , these finder identifying algorithms may be applied alternatively and successively , i . e ., as candidate algorithms , until one actually succeeds , and makes decoding possible . in the preferred embodiment of the method of the invention , advantage is taken of the fact that many 1d bar code readers already include programmed control circuitry which operates in conjunction with a fixed frequency timing signal to convert the video signal for a 1d slice of the symbol into a “ timercount ” representation thereof . these timercount representations of the symbol are produced for each successive slice of the symbol , substantially in real time , as the reader is moved manually across the symbol . as this occurs these timercount representations are stored in successive locations of a timercount memory space . at approximately the same time , these timercount representations are converted to the corresponding bit representations , using a simple well - known conversion algorithm and then stored in an image memory space . in this way , the method of the invention takes the fullest possible advantage of existing capabilities of existing 1d bar code readers to enable the reader to distinguish between and then decode both 1d and 2d symbols . it will be understood , however , that , if taking advantage of existing bar code reader capabilities is not important , the reader may be designed so that the timercount and bit image signals are generated simultaneously and independently . in the event that it is known that the reader will be used to read only 2d bar code symbols , the inclusion in the method ( or apparatus ) of the invention of steps ( or circuitry ) that are used to identify and process 1d bar code symbols is unnecessary . it will therefore be understood that , in embodiments of the latter type , the generation of timercount representations becomes optional , being included or not included depending upon whether or not it is useful in generating the bit representations used with 2d bar code symbols . in embodiments of the latter type , there may also be eliminated those steps or program segments that are directed only to the identification and processing of 1d bar code symbols . in accordance with a secondary feature of the invention , digital representations are stored in both of the above - mentioned memories , substantially in real time , on a first in - first out basis , with representations of old slices being shifted through the memory ( or at least with respect to an address pointer ) as representations of new slices are stored . on reaching the end of the memory space , representations of old slices are re - entered at the beginning of the memory space . as a result , the two memory spaces contain two circulating representations of the symbol being read , one a timercount representation and one a bit representation . sets of newly received timercount representations are examined as they occur and , if they indicate the presence of a 1d symbol , are decoded at once . if this decoding does not succeed , indicating that a 2d symbol may be present , the bit representations are examined to determine if a finder can be identified and located . once the finder is identified and located , the portion of the symbol that is then being imaged is known . the finding of this finder may then be used to continue the imaging of the symbol until there are enough stored representations of the symbol to allow the latter to be decoded . thereafter , optionally , the bit representations may be reorganized ( e . g . rewritten in a different order or re - addressed ) so that both the individual data bits and the finder pattern are located in their true relative positions with respect to one another . if the image memory space is too small for this to be done within the image memory , the reorganization may take place in the course of transferring the bit representation from the image memory to the timercount memory . in either case , the resulting bit image will be in condition for decoding using the decoding algorithm that is associated with the symbology indicated by the type of finder that has been found . in its apparatus aspect the present invention contemplates a 1d bar code reader which is in many respects similar to existing 1d bar code readers , except that its timing , memory structure and programming has been altered in a way that allows it to be used in accordance with the above summarized method . more particularly , the apparatus of the invention may comprise a 1d bar code reader which has been modified to increase its clock rate by an amount sufficient to enable it to be used to image many successive slices of the symbol as it is moved there across . in addition , the memory structure of the reader is modified to make the above - mentioned memory spaces available for use in storing and shifting the timercount and bit representations which are associated with these slices . finally , the programming of the reader is modified to coordinate the generation and storage of the latter representations , to differentiate between 1d and 2d bar code symbologies and , if a 2d symbology is used , to identify the symbology on the basis of the type of finder that is used , and then discontinue the imaging of the symbol after there has been stored a number of digital representations which is sufficient for decoding purposes . ( it should be noted in the last mentioned connection that , because error correction data is encoded in 2d bar code symbols along with message data , it is often possible to fully decode a message even though a part of the symbol is missing .) because the functions of these modifications have already been discussed in connection with the foregoing summary of the method of the invention , they will not be repeated here . other objects and advantages of the present invention will be apparent from the following description and drawings . fig3 is a block diagram of a bar code reader suitable for use in practicing the present invention ; fig3 shows an exemplary architecture for the perom program block shown in fig3 ; fig3 shows an exemplary architecture for the sram block of fig3 ; fig3 shows a bar code reader with a shipping carton which bears both 1d and 2d bar code symbols ; fig3 shows the bar code reader of the invention being moved across a 2d bar code symbol ; fig3 - 1 , 38 - 2 and 38 - 3 show the contents of the image memory at various stages in the scanning of the symbol of fig3 ; fig3 shows the relationship between the various representations of data read from a slice of a bar code symbol ; and fig4 - 42 are flow charts which illustrate the operation of the present invention . referring to fig3 there is shown a block diagram of a bar code reader of a type which is suitable for use in practicing the present invention . this bar code reader may be a 1d bar code reader of the type sold by welch allyn , inc ., skaneateles , n . y . under the model designation st - 3000 - 22 , provided that certain modifications to be discussed later are made thereto . the bar code reader includes an illumination system which may comprise a plurality of 660 nm light emitting diodes 16 that illuminate a narrow strip or slice of a bar code symbol 4018 . reader 4010 also includes focusing optics 4019 which may be of the type described in u . s . pat . no . 5 , 291 , 008 , which is assigned to the assignee of the present invention , and incorporated herein by reference . focusing optics 4019 causes light returning from the bar code symbol along a receive path 4014 to be focused or imaged upon a 1d image sensor 4017 which may be of the charge coupled type . sensor 4017 develops analog signals that represent the optically readable content of a complete slice of the bar code symbol . these analog signals are supplied to signal processing circuit 4020 , which provides signal conditioning and digitization , using a high frequency timing signal or clock received over a clock input line 4023 . digitization is accomplished using an analog reconstruction circuit which is disclosed in u . s . pat . no . 5 , 294 , 783 , of common assignee herewith , and also incorporated herein by reference . the resulting video signal representation of the imaged slice is supplied via an output line 4025 to programmed control circuitry 4030 of fig3 . programmed control circuit 4030 performs various tasks necessary to the operation of the reader . it includes a central processing unit 4040 which may comprise a motorola mc68hc11 microcontroller / microprocessor and has an address space of 64 kbytes . this microprocessor includes serial and parallel i / o , interrupt logic , an oscillator , and clock logic . microprocessor 4040 is also provided access to an 8 kbyte static random access memory ( sram ) 4042 and a 32 kbyte read only program memory ( perom ) 4045 . the capabilities of microprocessor 4040 are enhanced by a multifunctional application specific integrated circuit ( asic ) 4035 which may be of the type sold under the product designation 21203276 - 01 by welch allyn , inc . as shown in fig3 asic 4035 has four principal functional subunits or blocks . a clock control subunit 4043 facilitates switching the scan rate of image sensor 4017 between 50 , 100 , and 200 scans / second , although only the latter is used with the present invention . a memory management subunit 4046 ( mmu ) provides memory management capability . the timer / dma subunit 4048 , coupled to signal processing circuit 4020 , automates the capture of image data for subsequent processing . finally interface subunit 4044 serves as a rs - 232 communications interface for bar code reader 4010 , via line 4037 . asic 4035 and its subunits allow microprocessor 4040 to concentrate its resources on decoding data read from the bar code symbol . asic 4035 as a whole is controlled by microprocessor 4040 through a suitable bus 4039 . the timing of the circuitry of fig3 is controlled by asic 4035 based on a timing signal received from a crystal 4049 . to increase the performance of the reader , and to handle the high image sampling rates necessary to read two dimensional bar code symbols , a crystal having a frequency of 14 . 7456 mhz , has been substituted for the 7 . 3728 mhz crystal which is included in the unmodified model st3000 - 22 bar code reader . other modifications to the basic model st3000 - 22 include the use of the following : sram 4042 — a 70 ns , 8k × 8 cmos ram sold by sony corp . under the product designation cxk5864bm - 70l . perom 4045 — a 90 ns rom sold by atmel under the product designation at29c256 - 9 . regarding the above mentioned modifications , the use of a higher timing signal frequency is the most important to the present invention and the remaining modifications are made to assure reliable operation of the circuitry at this higher frequency . firmware resident in the perom 4045 contains the stored program for microprocessor 4040 . portions of the program realized in the perom 4045 are conventional , and allow the bar code reader 4010 to function as a conventional autodiscriminating reader for linear bar code symbologies . broadly speaking , firmware 4060 includes 4 main program segments as shown in fig3 . a variety of system supervisory functions , indicated by reference numeral 4062 include the initialization of volatile hardware and memory regions , controlling and sequencing the scanning and decoding operations , and monitoring and maintaining i / o between the bar code reader , the operator , and external equipment . decoding functions , indicated by reference numeral 4064 , are accomplished in several stages . first a preliminary examination for the presence of a 1d bar code symbol is performed . if a 1d linear symbol is found , an attempt is made to decode the symbol with reference to the timercount representations of the slices until decoding is successful , one timercount representation of the symbol often being sufficient for this purpose . if further representations indicate that a stacked 1d stacked symbol is found , this procedure is repeated until all rows of the symbol have been successfully decoded . if it is determined that the symbol is a 2d symbol , the symbol is examined with reference to successive bit representations of the imaged slices , which are stored in sram 4042 substantially in real time . as this is occurring the representations are examined to identify the type and location of the finder pattern therefor . the identification is facilitated by the fact that the simultaneous availability of a number of bit representations allows the recognition of data structures such as finders which cannot be recognized and identified from a single bit representation . once the latter have been determined , additional bit representations are stored until there have been stored a number of such representations which is sufficient to make possible the decoding of the symbol . the stored 2d image may then be decoded using a decoding algorithm of a type appropriate to the symbology used to encode the symbol . in operation , a user will normally depress a trigger ( or set the unit to automatic scan mode ) and sweep the scanner over the image one or more times until the audio alert ( e . g ., a “ beep ”) is heard and the decoded information is output . alternatively , the user might manually specify whether 1d and 2d codes are to be read , or this could be determined automatically by the reader . the menu functions , indicated by reference numeral 4066 , are routines called in response to decoding special bar code symbols , so - called bar code “ menus ” that set non - volatile bits or values within a designated configuration region of the perom 4045 , thus governing various operating characteristics of the bar code reader 4010 , such as scan rate , beeper volume , mode of operation ( manual or auto - trigger ), enablement of decoding of particular bar code symbologies , etc . communications functions 4068 service the hardware and include protocols needed to deliver scanned data to an attached device . the bar code reader 4010 can support a number of communications protocols and interfaces , including laser output , ocia , ocr , rs - 232 , various commercial terminals and keyboard wedges . except for the above - discussed modifications to the circuitry and programming of the reader , reader 4010 is of a type that is commercially available to and understood by those skilled in the art . accordingly , the circuitry shown in fig3 and 35 will not be further described herein . referring to fig3 there is shown an enlarged view of sram 4042 which illustrates how the latter is organized for use in practicing the present invention . in the embodiment of fig3 the 8 kilobytes of memory which are included within sram 4042 are grouped into a first or image memory space 4042a which includes approximately 3 . 7 kilobytes , a second or timercount memory space 4042b which includes 4 kilobytes , and a third or accessory memory space 4042c which includes approximately 0 . 3 kilobytes , and which may be used as a “ connectivity ” register in the course of identifying the finder pattern of the symbol , and as a set of general purpose registers for conventional microprocessor housekeeping functions . it will be understood that these numbers are exemplary only and that these memory spaces may be located either on the same chip or on separate chips . in the preferred embodiment , second memory space 4042b is used on a first in - first out basis to receive and store successive timercount representations of the slices of the bar code symbol which are imaged as reader 4010 is manually moved across a bar code symbol . in the case of 2d symbols , this movement may be asynchronous and may be in any direction , provided that enough of the symbol can be imaged along that direction to make decoding possible . in the case of 1d symbols , this movement may also be asynchronous , but must be within a range of directions that allows each code bar of the symbol to be included within the timercount representation . the numbers which are included in each timercount representation comprise the number of timing pulses which have occurred at the times when the video signal from signal processing circuit 4020 undergoes transitions from 1 &# 39 ; s to 0 &# 39 ; s or vice - versa . an illustration of how the data from a video signal for an imaged slice is converted to a timercount representation thereof , and then stored in timercount memory 4042b is shown in fig3 . similarly , first or image memory space 4042a is used on a first in - first out basis to receive and store successive bit representations of the slices of the bar code symbol which are imaged as reader 10 is manually moved across a bar code symbol . these bit representations contain substantially the same information as the timercount representations thereof , although in a different format , the conversion of one format to the other being possible with the use of known conversion algorithms . in the preferred embodiment of the invention , the bit representation of each slice is derived from the corresponding timercount representation thereof by the use of such an algorithm , as suggested by fig3 . this conversion is performed because it makes possible the use of the timercount generating circuitry and programming of existing 1d readers with a minimum of modification . more generally , however , the bit representation of each imaged slice of the bar code symbol may be derived directly from the video signal , if desired . a series of examples of how the bit representations of successive slices are “ shifted ” through image memory 4042a during the movement of the reader across a bar code symbol is shown in fig3 - 1 through 38 - 3 . fig3 shows the bar code reader of the invention together with a package marked with examples of the types of bar code symbols which it is able to read . included among these examples are a 1d linear bar code symbol 4072 , a 1d stacked symbol 4078 , and a 2d bar code symbol 4076 . all of the illustrated symbols could , in principle , be read omnidirectionally , i . e ., in any direction , by the scanner if there were no resolution , memory or processing limitations in the bar code scanner . in the case of 2d bar code symbols , this omnidirectional reading can be easily achieved because readers designed for use with such symbols require a relatively low resolution along its two mutually perpendicular axes . in the case of 1d bar code symbols , high resolution along only the horizontal axis of the symbol is important because information is encoded in the edge positions of the code bars of the symbol . this , together with the need to image all code bars in each imaged slice , place practical limits on the range of directions along which 1d symbols can be read . thus , while the invention can read both 1d and 2d symbols , it is , for practical reasons , fully omnidirectional only for 2d symbols . fig3 , 38 - 1 , 38 - 2 , 38 - 3 and 38 - 6 illustrate how a 2d bar code symbol which use above mentioned aztec symbology is read in accordance with the method and apparatus of the invention . line segments ( a ), ( b ), ( c ) of fig3 represent various 1d slices imaged by the reader as it is swept across 2d bar code symbol 4080 . as shown in fig3 each imaged slice produces a video signal 4082 . timercounts representing the occurrence times of transitions between black to white and white to black image elements are measured and stored sequentially in respective locations within memory 4042b , which serves as a timercount memory . as the timercount representation of each slice is stored in timercount memory 4042b , the timercount data for the preceding slice is converted into the bit representation of that slice and stored in a respective location in memory 4042a , which serves as an image memory . in the preferred embodiment of the present invention , which is based on a modified 1d reader , the above - described conversion of the timercount representation to the corresponding bit representation is performed by microprocessor 4040 , while the storing of the timercount and bit representations is handled by the timer and dma subunit of asic 4035 . with a total of only 8 kilobytes of storage space in sram 4042 , the amount of memory space that is available for storing the bit image is limited to about 3 . 7 k . as a result , the bit image produced by the embodiment of fig3 has a relatively low resolution , namely : 170 lines of 176 bits each . this resolution may , however , be increased as necessary by increasing the storage capacity of sram 4042 , and / or the number of light responsive elements in 1d sensor 4017 , and / or the frequency with which the video signal is examined for the occurrence of transitions . bit representations 4081 , 4082 , and 4083 of fig3 - 1 , 38 - 2 and 38 - 3 represent the con of image memory 4042a after the reader has imaged symbol slices a , b , and c , respectively of symbol 4080 . as can be seen , when image memory 4042a is filled through the end thereof an input pointer p jumps back to the beginning of the memory space , so that slices of the bit image are effectively shifted or circulated through the image memory . a similar circulation occurs for the timercount representations stored in timercount memory 4042b . the circulation of these representations is shown in fig3 as closed loops shown in dotted lines . as the bit representations of symbol 4080 are imaged and stored , they are analyzed ( as will be described below ) to see if the finder pattern has been located . if the 2d symbol uses the aztec symbology , this finder pattern will include the set of nested or concentric black and white squares labelled 4085 in fig3 and 39 . fig3 - 2 and 38 - 3 show symbol images 4082 and 4083 which include this finder pattern . once this finde pattern is found , data from a predetermined number of additional slices of the symbol are processed and input into timercount memory 4042b and image memory 4042a in order to assure that enough of the image of the symbol is stored to allow the latter to be decoded . since the position of the resulting image with respect to the boundaries of the memory space ( or address pointer p ) cannot be predicted in advance , the image may be stored in two parts as shown for bit image 4083 in fig3 - 3 . if desired , in order to facilitate decoding , these two parts may be joined together into a single image by reorganizing ( as by reordering ) the bit representations stored in the image memory . the purpose of this reorganization is to assure the formation of a substantially complete , decodable image of the bar code symbol as a whole , i . e ., an image in which the bits of the bit image representations are located ( in memory space ) in their true relative positions with respect to the finder . thus , bits which are adjacent to one another in the physical space containing the printed symbol will be adjacent to one another in the memory space containing the stored image thereof . if image memory space 4042a is too small for the above - described reorganization , a similar result may be achieved by transferring the image to the timercount memory as a complete unit with all parts of the image including the finder located on the same side of the pointer of the timercount memory . while such a transfer involves the overwriting of data previously stored in the timercount memory , such overwriting is not a problem since the data stored in the timercount memory is then no longer needed . it will be understood that the above - described reorganization of the captured image of a bar code symbol is a desirable but not essential part of the present invention . this is because a reorganization of this type is necessary or desirable with some decoding algorithms , but unimportant with others . whether or not such a reorganization is necessary or even beneficial is also dependent upon the type of finder pattern that is used in the bar code symbol . thus , the present invention contemplates a reorganization of the captured image of the symbol in those cases where such a reorganization is necessary or beneficial to decoding , but no reorganization in those cases where it is not necessary or beneficial . as will be explained more fully presently , the above - described image capture process takes place within the framework of an image analysis or typing process that involves a series of attempts to decode the unknown symbol as a 1d linear or 1d stacked symbol and , if it cannot do so , a series of attempts to identify a 2d finder and then decode the symbol using the identified finder . the image analysis process as a whole is best visualized with reference to the flow chart of fig4 . the 1d part of this analysis is best visualized with reference to the flow chart of fig4 . the 2d part of the analysis is best visualized with reference to the flow chart of fig4 . for the sake of clarity and “ connectedness ”, the flow charts of both fig4 and 42 include ( above their respective dotted lines ) the part of the flow chart of fig4 that leads into them . the above - summarized image analysis framework will now be described with reference to fig4 - 42 . turning first to the flow chart of fig4 , the image analysis begins with block 4102 which calls for the reader to wait for a trigger press . when this trigger press does occur , the reader enables its scanning and timing mechanisms as called for by block 4104 to initiate the imaging of stored slices . the reader then tests to see if the trigger is still depressed ( block 4106 ). if the trigger is not still depressed , the reader knows that the read is being terminated and directs the disabling of the scanning and timing mechanisms ( block 4120 ) before returning to its wait condition ( block 4102 ). if the trigger is still depressed , the reader waits for the completion of the next scan slice ( block 4108 ) and then begins the image analysis proper by proceeding to block 4200 . block 4200 , which will be described more fully in connection with fig4 , represents the steps necessary to decode a 1d symbol of either type , if one is present , and the reader attempts to perform this decoding on encountering this block . the reader continues this attempt until the attempt is successful and a complete message is ready , or until the attempt fails . if the reader determines that the former has occurred ( block 4112 ), i . e ., “ data ready ”, the reader produces a beep and outputs its data , as called for by block 4118 , before disabling the scanning and timing mechanisms ( block 4120 ) and returning to its wait state ( block 4102 ). if the reader cannot decode the symbol or otherwise produce a complete message , block 4112 directs the reader to block 4300 , which represents the steps necessary to decode a 2d symbol of any of a variety of types . this is done because one reason why no data was ready ( block 4112 ) may be that the symbol is not a 1d symbol , i . e ., is a 2d symbol . whether or not that is actually the case at that time remains to be determined . this is because the reason why there was no “ data ready ” may be that the symbol was damaged or was a 1d symbol read from an unpermitted direction . thus , block 4300 gives the reader a chance to decode the symbol as a 2d symbol before allowing it to give up and return to its wait state . upon completing the steps called for by block 4300 , the reader determines if a decodable message is ready ( block 4116 ) and , if so , outputs its data and returns to its wait state . if a decodable message is not ready , it may be because more of the 2d symbol needs to be imaged before decoding can occur . as a result , the reader is directed back to block 4106 to repeat the above - described analysis process for additional scan slices until a complete decoded message is ready and then outputs the message and returns to its wait state . in view of the foregoing , it will be seen that the analysis process shown in the flow chart of fig4 will ultimately output a decodable message from both 1d and 2d symbols provided only that the symbol is readable and is read from a permitted direction . in doing so , the reader , in effect , finally determines which type and subtype of symbol is present by determining which symbol type and subtype resulted in a decodable message . referring to fig4 , there is shown ( below the dotted line ) the steps necessary to decode and assemble into a message the data encoded in a 1d linear or 1d stacked symbol , if one is present . these steps employ a process of elimination similar to that discussed in connection with fig4 . more particularly , the flow chart determines if a 1d linear or 1d stacked symbol is present by attempting to decode first one and then the other , and deciding if one or the other is present by whether or not the attempted decoding was successful . because 1d autodiscriminating algorithms ( i . e ., algorithms which are capable of differentiating between and then decoding any of a variety of different subtypes of 1d linear symbols ) are well known in the art , the steps involved in carrying out the actions called for by blocks 4202 through 4210 of fig4 will not be discussed in detail herein . similarly , because an algorithm suitable for use in decoding 1d stacked symbols is taught by the above - cited allais patent , the steps involved in carrying out the actions called for by blocks 4212 and 4214 of fig4 will not be described in detail herein . referring to fig4 , there is shown ( below the dotted line ) the steps involved in decoding and assembling into a message the data encoded in a 2d symbol ( if any ) having any of a variety of different types of finder patterns , such as central finders , waistband finders and peripheral finders , among others . in doing so , fig4 employs a process of elimination similar to that discussed in connection with fig4 . more particularly , after converting the current timercount representation to its corresponding bit representation ( block 4302 ), the reader correlates the current bit representation with the bit representations of a number of preceding scan slices to determine if a finderlike pattern is present , as called for by blocks 4304 and 4306 . this may be accomplished by applying a number of candidate finder identifying algorithms , image processing algorithms , or known fuzzy logic pattern recognition techniques , such as those described in u . s . pat . no . 5 , 401 , 949 ( ziemacki ). if a finder - like pattern is found , the reader acquires enough additional representations to permit the symbol to be decoded . this is accomplished with the use of a scan counter and associated control blocks 4308 through 4316 . once this has been done , the reader determines the orientation of the 2d image and attempts to decode it as called for by block 4318 . if the attempted decode is successful , the reader outputs its data and returns to its wait state ( block 4320 ). if it is not successful , the reader is directed back to block 4106 to make another try at decoding . the examination of the sets of bit representations for the type of finder ( if any ) that is present preferably involves the application of a process of elimination which uses the same algorithms which are used by conventional readers to located their finders . the waistband type finder used with the code one symbology may , for example , be found using the algorithm described in “ uniform symbology specification code one ”, published by aim usa technology group , under publication no . tsc 059 . similarly , the peripheral type finder used with the data matrix symbology may be found using the algorithm recommended by its originator , and the circular central type finder used by the maxi code symbology may be found using the algorithm recommended by its originator . in the case of the aztec symbology , a particularly advantageous algorithm for finding the finder has been developed which also works well with symbols using other types of central finders such as maxicode . because a description of the latter algorithm is not as yet publicly available , a description thereof will now be provided . with finder patterns of the central type the bits of successive slices are examined to find a small “ island ” ( black region ) within a larger “ lake ” ( white region ), within an island , within a lake , etc . this is done by determining how isolated each pixel is from the top and sides of an image , by which measure the center of any bull &# 39 ; s - eye stands out plainly . an explanation of a quick scanning algorithm for finding such a bull &# 39 ; s - eye structure will now be given . the following algorithm , presented descriptively and in c code to be more easily understood by a computer programmer , locates a point of high “ isolation ”— e . g ., the center of a bull &# 39 ; s - eye — in a stored image . first assume that a fully contrasted image of “ n ” pixels wide of the 2d bar code is stored in the array i [ x ][ y ] where 0 ≦ x & lt ; n and each element i [ x ][ y ] is valued either 0 ( for white ) or 1 ( for black ). this can be either a single image frame ( 0 ≦ y & lt ; m ) from a 2d sensor or a continuously acquired image ( 0 & lt ;= y & lt ;??) rolling off a 1d sensor that moves in relation to the target . a “ level ” array l [ x ] “ n ” values wide is first established , where l is an unsigned integer . l is initialized to the values of the top row in i as follows : for ( x = 0 ; x & lt ; n ; x ++) l [ x ]= i [ x ][ 0 ]; subsequent rows of the image are processed in sequence by bi - directional scans through l as follows : for ( y = 1 ; y & lt ; m ; y ++) { working first left - to - right , the left - most l is set equal to the left - most i value in that row , then each subsequent l [ x ] is set to : ( a ) the lesser of its current value ( from the row above ) or its left - hand neighbor , and then ( b ) plus one if needed to make the new l and its corresponding i both even or odd . this can be represented mathematically in c code as follows . l [ 0 ] = i [ 0 ][ y ]; for ( x = 1 ; x & lt ; n − 1 ; x ++) { if ( l [ x − 1 ] & lt ; l [ x ]) l [ x ] = l [ x − 1 ]; if (( l [ x ] { circumflex over ( )} i [ x ][ y ]% 2 == 1 ) l [ x ] = l [ x ] + 1 ; } working then back right - to - left , the right - most l is set equal to the right - most 1 , then subsequent l &# 39 ; s are reduced by 2 ( 1 or more times ) if they exceed their right - hand neighbor by 2 ( 1 or more times ): l [ n − 1 ] = i [ n − 1 ][ y ]; for ( x = n − 2 ; x & gt ;= 0 ; x −−) { while ( l [ x ] & gt ;= l [ x + 1 ] + 2 ) l [ x ] = l [ x ] − 2 ; } as the process is repeated with data from each subsequent scan , from row to row the l values will start to reflect how isolated any image region is from its top and sides . after processing a row through part of a bull &# 39 ; s - eye , the sequence of l values in its vicinity will look something like : the “ finder ( or bull &# 39 ; s - eye ) located ” criterion may be characterized as 4 or more consecutive increases in isolation value followed by 4 or more consecutive decreases . the highest values mark the center of the “ bull &# 39 ; s eye .” scanning through l with a simple state machine ( probably as part of the right - to - left scan above but shown here as a separate operation ) detects this condition : state = peakx = 0 ; for ( x = n − 1 ; x ≧ 0 ; x −−) { switch ( state ) { case 0 : case 1 : case 2 : case 3 : if ( l [ x ] & lt ; l [ x + 1 ]) state = 0 ; if ( l [ x ] & gt ; l [ x + 1 ]) { peakx = x ; state ++; } break ; case 4 : if ( l [ x ] & gt ; l [ x + 1 ]) peakx = x ; if ( l [ x ] & lt ; l [ x + 1 ]) state ++; break ; case 5 : case 6 : case 7 : if ( l [ x ] & gt ; l [ x + 1 ]) state = 0 ; if ( l [ x ] & lt ; l [ x + 1 ]) state ++; break ; default : } } if this scan through l ends with “ state ”= 8 , then the point i [ peakx ][ y ] is a candidate bullseye center . the true center of the bull &# 39 ; s - eye will have the highest level of isolation , so the search will continue for the possibility of a candidate having a higher level of l . if a variable peakl is initialized to zero at the top of the scan , then the candidate bull &# 39 ; s - eye center location can be logged by : if (( state == 8 ) & amp ;& amp ; ( l [ peakx ] & gt ; peaki )) { peaki = l [ peakx ]; eyex = peakx ; eyey = y ; } } when an entire image has been scanned , then a non - zero “ peakl ” indicates a bull &# 39 ; s - eye was found adjoining pixel i [ eyex ][ eyey ]. alternately , in the case of a continuously flowing image , acquisition should be terminated a suitable number of rows ( e . g ., half the size of the image buffer ) past the most recent updating of “ peakl ”. this is the number “ n ” referred to in connection with block 308 above . the current invention utilizes the second acquisition method , by choosing to terminate acquisition n scans after the most recent updating of “ peakl ”. analysis continues , allowing for a higher peakl , and therefore a more likely candidate for the bull &# 39 ; s - eye center to be found subsequently . when all imaged slices have been stored and the finder has been located , the symbol is then ready for decoding with reference to the finder . while the present invention has been particularly shown and described with reference to the embodiments illustrated in the drawing , one skilled in the art will understand that various changes in detail may be effected therein without departing from the spirit and scope of the invention as recited by the claims . [ end of excerpt of u . s . patent application ser . no . 08 / 504 , 643 , filed jul . 20 , 1995 ]. while the present invention has necessarily been described with reference to a number of specific embodiments , it will be understood that the time spirit and scope of the present invention should be determined only with reference to the following claims .