the pattern forming method according to one embodiment of the present invention will be explained with reference to fig1 a - 1e , 2 a - 2 e , 3 a - 3 b , 4 and 5 a - 5 b . fig1 a - 1e and 2 a - 2 e are sectional views of a package substrate in the steps of the pattern forming method according to the present embodiment , which explain the method . fig3 a and 3b are plan views showing the pattern forming method according to the present embodiment . fig4 is a plan view showing one example of disalignment of lsi chips . fig5 a and 5b are plan views of one example of a basic mask pattern and the mask pattern as corrected . grooves 12 for a plurality of lsi chips to be embedded in are formed in a core substrate 10 to be the base ( fig1 a , fig3 a ). in place of forming the grooves 12 , a core substrate with mold frames for the lsi chips to be embedded in may be used . then , lsi chips 14 are fit in the grooves 12 formed in the core substrate 12 and secured with a resin ( fig1 b ). the lsi chips are embedded with the circuit surfaces thereof faced upward . preferably , the resin is set by pressing the surfaces of the lsi chips 14 with a parallel plate , so that the circuit surfaces of the lsi chips 14 can be flush with the level of a height of the core substrate 10 . next , a resin 16 is filled in the gaps between the lsi chips 14 without adhering the resin 16 to the circuit surfaces of the lsi chips 14 to thereby make the surface flat ( fig1 c , fig3 b ). at this time , there is a risk that the respective lsi chips 14 may be disaligned due to alignment accuracy when the lsi chips 14 are secured to the core substrate 10 and stresses produced when the resin 16 is dried . the disalignment will include x - axial disalignment , y - axial disalignment , rotations , etc . fig4 shows an image in which the lsi chip 14 a has a disalignment containing rotation , and the lsi chip 14 b and the lsi chip 14 c have y - axial disalignments . in fig4 , the dotted lines indicate the basic positions of the lsi chips 14 , and the solid lines indicate positions where the lsi chips 14 have been actually located . then , a photosensitive dielectric resin 18 is applied to the core substrate 10 with the lsi chips 14 embedded in , and dried ( fig1 d ). thus , a base pattern formed by the lsi chips 14 is formed on the core substrate 10 . the base pattern is a pattern including a tetragonal shape , a polygonal shape , etc . which is formed over the core substrate 10 . at least one interconnection layer is to be formed on the base pattern . in the present embodiment , outline shapes of the lsi chips 14 correspond to the base pattern . next , relative positions of the respective lsi chips 14 with respect to the core substrate 10 are detected by optical means . the positions of the lsi chips 14 may be detected by detecting the edges of the lsi chips 14 or alignment marks on the lsi chips 14 . then , based on the detected positional information of the lsi chips 14 , positions of the electrodes ( not shown ) formed on the lsi chips 14 are computed . for the computation , positional relationships between the edges of the lsi chips 14 and the electrodes or positional relationships between the alignment marks and the electrodes are beforehand in storage means , so that positions of the electrodes of the lsi chips 14 are computed , based on the stored information . next , based on the computed positional information of the electrodes of the respective lsi chips , basic pattern data of via holes , which has been in advance stored in the storage means is corrected to compute corrected pattern data . the basic pattern data is pattern data of idealistic locations of the lsi chips 14 without disalignments . the corrected pattern data is a pattern data of the basic pattern which has been corrected so that positions of the respective via holes are above the electrodes of the actual lsi chips . for example , in a case that the basic pattern data of the via holes is based on coordinate origins of the respective vial holes , the coordinate origins of the respective via holes are shifted by amounts corresponding to disalignment amounts of the lsi chips to thereby produce the corrected pattern data . then , based on the thus - computed corrected pattern data of the via holes , a mask pattern is produced and displayed on a liquid crystal panel . next , with the liquid crystal panel displaying the mask pattern as a mask , the photosensitive dielectric resin 18 is exposed and developed . the liquid crystal panel is thus used as a mask to thereby prepare mask patterns corrected suitably corresponding to disalignments of the lsi chips 14 . thus , via holes 20 are formed in the photosensitive dielectric resin 18 in alignment with the positions of the electrodes of the respective lsi chips 14 ( fig1 e ). the photosensitive dielectric resin 18 is to be an inter - layer insulating film for insulating the interconnection layers . then , a titanium nitride film , for example , is deposited on the entire surface to form a barrier metal layer 22 of the titanium nitride film ( fig2 a ). next , a photoresist film 24 is applied to the barrier metal layer 22 and dried . then , based on the computed positional information of the electrodes of the lsi chips 14 , basic pattern data of an interconnection layer , which has been beforehand stored in the storage means is corrected to compute corrected pattern data . here , the basic pattern data is idealistic pattern data of the lsi chips 14 without disalignments . the corrected pattern data is a pattern data of the basic pattern which has been corrected so that contact positions of the respective interconnections are above the via holes 20 formed in the photosensitive dielectric resin 18 . for example , in a case that the basic pattern of the interconnection layer is based on coordinate origins of the respective via holes 20 , the corrected pattern data can be produced , based on coordinate origins of the via holes 20 , which have been corrected in consideration of the positional information of the lsi chips . then , based on the thus computed corrected pattern data of the interconnection layer , the mask pattern is produced and displayed on a liquid crystal panel . at this time , when the photoresist film 24 is provided by a positive resist , the mask pattern is formed on the liquid crystal panel so that a region for the interconnection layer to be formed in is a transmitting region . fig5 a shows one example of the mask pattern formed based on the basic pattern data , and fig5 b shows one example of the mask pattern formed based on the corrected pattern data . when the basic pattern of the interconnection layer is corrected , it is preferable to suitably adjust a width of the interconnection so as not to change the width of the interconnection . especially , there is a risk that the breakage of the equipment or obstruction of the normal circuit operation is occurred because of exceeding the upper limit of the current density when the width of the interconnection narrows , so that it is effective to suitably adjust the width of the interconnection . then , with the liquid crystal panel displaying the mask pattern as a mask , the photoresist film 24 is exposed and developed . thus , the photoresist film 24 in the region for the interconnection layer to be formed in is selectively removed ( fig2 b ). next , with the photoresist film 24 formed , copper , for example , is deposited by plating with the barrier metal layer 22 as a seed layer to form a copper film 26 selectively in the region for the interconnection layer to be formed in ( fig2 c ). then , after the photoresist film 24 has been removed , with the copper film 26 as a mask , the barrier metal layer 22 is etched off to form the interconnection layer 28 , etc . of the barrier metal layer 22 and the copper layer 26 laid the one on the other ( fig2 d ). next , in the same way as in the steps of , e . g ., fig1 d to 2 d , on the photosensitive dielectric resin with the interconnection layer formed on , photosensitive dielectric resins 30 , 34 , 38 , etc . and interconnection layers 32 , 36 , etc . are repeated formed to thereby form a multi - level interconnection layer 40 on the core substrate 10 ( fig2 e ) as described above , according to the present embodiment , positions of the lsi chips with respect to the core substrate are detected , the pattern data for a pattern to be formed on the core substrate is corrected based on positional information of the lsi chips , a mask pattern based on the corrected pattern data is displayed on a liquid crystal panel , and the pattern is formed by lithography with the liquid crystal panel as a mask , whereby even when the lsi chips are disaligned with the core substrate , the multi - level interconnection layer can be formed on the core substrate accurately in alignment with the lsi chips . in the present embodiment , the patterning is performed in the process of forming the multi - level interconnection layer 40 by using information of positions of the electrodes of the lsi chips 14 . however , it is possible that positions of the via holes or the interconnection layer formed on the core substrate 10 are detected to obtain new positional information , and based on the positional information , the patterning of the upper layers is performed . in the latter , the multi - level interconnection layer 40 can be formed while not only disalignments of the lsi chips 14 , but also distortions and shrinkages of patterns taking place in processes , as of thermal processing , etc ., are corrected . in the present embodiment , positions of the lsi chips are detected after the photosensitive dielectric resin 18 has been applied to , but the positional detection of the lci chips may be performed before the application of the photosensitive dielectric resin 18 . when positions of the lsi chips are detected , the entire surface region of the core substrate is divided in a plurality of units , and the positional detection of the lsi chips may be performed for the respective units . in the present embodiment , the present invention has been explained by means of the example that the multi - level interconnection layer is formed on the core substrate with the lsi chips embedded in . however , the present invention is not limited to the process of fabricating package substrates and is applicable widely to the formation of patterns by photolithography . the present invention is advantageously applicable especially to cases where different factors for disalignment are present in one and the same plane and where distortion and shrinkage take place due to build - up , etc . the base pattern is not limited to a pattern formed on the core substrate 10 . as described above , a pattern formed by the interconnection layer formed on the core substrate 10 , etc . may be also included in the base pattern .