reference will now be made in detail to a preferred embodiment of the present invention , examples of which are illustrated in the accompanying drawings . for purposes of describing this embodiment of the present invention , the examples shown , including the drawings , assume the use of a pentium iii class microprocessor . in particular , a cache - line width of 32 - bytes , an uncached data width of 8 - bytes , and a maximum execution queue length of four are assumed . referring to fig1 a hybrid multi - processor computer system including processors and reconfigurable processors is shown with processor boards 10 0 - 10 n . referring to the first processor board 10 0 , it contains two processors 100 0a and 100 0b . each processor connects to a bridge 110 0 that in turn connects to a multiplexer 14 0 via data bus 20 0 . in a further embodiment of the processor board 10 j , the processors 100 i a + b are connected to an uncached device 111 i through a memory i / o bridge 110 j . the multiplexers 14 0 - 14 n are switches to direct data to and from either the common memory 18 via the crossbar 16 , or the map devices 12 0 - 12 n . the map devices 12 0 - 12 n are shown on the processor side of the crossbar 16 . further embodiments of the hybrid computer system may place a map on the memory side of the crossbar 16 , or in various other locations in the computer system . in any of these configurations the present invention will operate in a similar manner . each bus 20 0 - 20 n , 22 0 - 22 n , 24 0 - 24 n , and 26 communicates via a 32 - byte cache line protocol . in other words , data passed along these paths are in blocks 32 - bytes , or 16 - words w 0 - w 15 , wide . referring to fig2 and 3 , a 16 - word w 0 - w 15 cache line is represented in fig2 . a processor of the type used in the accompanying examples is only capable of transferring four words w 0 - w 3 of data at a time to an uncached device , such as the map . fig3 represents the available four words w 0 - w 3 from the cache line . the last 12 words w 4 - w 15 of a cache line are invalid and unusable when communicating with an uncached device . referring to fig4 during a write to the map the microprocessor fetches a standard 32 - byte cache line from common memory . a map command of 2 - bytes is used for the current example . there are up to sixteen 2 - byte commands within the cache line of data read by the processor . in order to avoid the delay of waiting for the individual write transactions to complete serially , the addresses of the write transactions to the map are stridden on cache line boundaries so that the transaction depth of the microprocessor can be fully utilized . because each write transfer uses a different cache line address , all of which map into the receive fifo of the map device , the microprocessor can issue as many of these transactions as is allowed by the transaction depth of the processor . as the microprocessor receives the reply to the write transactions , and the transaction queue is drained , more write transactions can be issued . this sequence is continued until the cache line of data is consumed , and the next cache line is fetched from common memory . referring to fig5 the method of handling a write request for an uncached device according to the present invention includes the steps as follows . the processor receives an uncached device write request , step 30 . the processor retrieves a data block , equivalent to the processor &# 39 ; s cache line width , from the cached common memory address space , step 32 . the data is written to the cache and available to the processor , step 34 . the processor spreads the useable data onto successive cache lines , step 36 . the processor writes the data to multiple addresses of the receive fifo of the uncached device using the maximum number of write commands permitted by the transaction queue , step 38 . if additional data is available in the cache line , steps 36 and 38 are repeated , step 39 . referring to fig6 a read command virtually reverses the process . a first - in / first - out queue 40 , or output fifo , is located on each map device . the output fifo 40 provides a queue for information ready to be read from the map . the top of the queue includes four consecutive addresses 41 - 44 that are mapped as memory locations for the processor . the tail addresses of the queue 45 1 - 45 n are not mapped , but simply provide additional space for the queue to grow . by providing multiple consecutive cache line addresses 41 - 44 a processor can request data from each one without waiting for the response delay that accompanies a request to an identical address . the optimum number of these addresses is equal to the main memory latency divided by the microprocessor transaction period , or the execution queue depth of the processor , which ever is smaller . the src - 6 computer with intel pentium iii processors , and map devices can be used as an example . the pentium iii processor has an execution queue depth of four , which is smaller than the main memory latency divided by 50 ns per transaction . therefore , the present invention alleviates the processor waits by mapping the first four addresses in the output fifo 41 - 44 . with four addresses the processor is able to request data from all four simultaneously in lieu of four single requests to one address at the front of the queue . the four data elements read from the front of the queue are subsequently loaded into a single cache line represented by fig3 and written to memory . referring to fig7 once these four data items have been read from the output fifo 40 , any remaining contents of the output fifo 40 are moved to the front of the queue . once the remaining data has been moved to occupy the first four addresses of the queue 41 - 44 it can be read in the same manner as the first four data items . referring to fig8 the method of reading from an uncached device , according to the present invention , is as follows . the processor receives a request for a read to an uncached device , step 50 . the processor requests data located in the four successive cache line memory addresses associated with the uncached device , step 52 . the processor combines the data from these addresses into a single cache line , step 54 . the processor writes the newly formed cache line to the cache and common memory , step 56 . it will be apparent to those skilled in the art that various modifications and variations can be made in the method for bandwidth enhancement of the present invention without departing from the spirit or scope of the invention . thus , it is intended that the present invention covers the modifications and variations of this invention provided that they come within the scope of any claims and their equivalents .