fig1 is an illustration providing a partial cross - sectional view of a portion of a semiconductor memory device incorporating an embodiment of the invention . as shown , p - type conductive strips 101 , 102 and 103 are situated upon n - type conductive substrate 104 . metal runners 105 and 106 are orient , ed orthogonally to the p - type conductive strips . the p - type conductive strips have a width w , and are separated from adjacent p - type conductive strips by a distance w ; where w is the minimum feature size for the particular fabrication technique being employed . likewise , the width of , and separation between , metal runners 105 and 106 are also w . although it appears from fig1 that metal runners 105 and 106 are in direct contact with p - type conductive strips 101 , 102 , and 103 , the metal runners remain electrically isolated from the p - type conductive strips because of a thin non - conductive oxide ( not shown in fig1 ) on the surface of the p - type conductive strips . as also shown , vertically - oriented columns of n - type conductive material 107 and 108 , each having a radius of r ( where 2r is less than w ), are situated beneath the areas where metal runner 105 overlays conductive strips 101 and 102 , respectively . these n - type conductive columns are orthogonally oriented with respect to the surface of n - type conductive substrate 104 , conductive strips 101 and 102 , and metal runners 105 and 106 . each of these n - type columns serves to provide an n - type conductive path between metal runner 105 and n - type conductive substrate 104 . in contrast , no such n - type column exists beneath the area where metal runner 105 overlays p - type conductive strip 103 . it is the presence or absence of these columns of n - type material beneath the areas where the metal runners intersect the p - type conductive strips which serves to indicate digital data . in particular , the presence of an n - type column indicates a logical value of 0 , while the absence of an n - type column indicates a logical value of 1 . each intersection between a metal runner and a p - type conductive strip serves as a one - bit rom . fig2 provides a schematic illustration of the equivalent circuit for three of the one - bit roms illustrated in fig1 . jfet 201 is formed by p - type conductive strip 101 and n - type column 107 . the drain contact for transistor 201 is provided by metal runner 105 , and the source contact for the jfet is provided by n - type conductive substrate 104 . similarly , jfet 202 is formed by p - type conductive strip 102 and n - type column 108 , with metal runner 105 serving as a drain contact , and n - type conductive substrate 104 serving as a source contact . the channels of each of these jfets are formed by the respective n - type columns . the gate of each jfet is formed by the material of the p - type conductive strip surrounding the n - type channel . as stated above , there is no n - type column beneath the area where metal runner 105 overlays p - type conductive strip 103 . therefore , diode 203 ( as opposed to a jfet ) is formed by p - type conductive strip 103 and n - type conductive substrate 104 . there is no electrical contact between metal runner 105 and diode 203 . to read the value of the digital information stored in the one - bit rom at the intersection of p - type conductive strip 101 and metal runner 105 , the voltage between p - type conductive strip 101 ( the gate contact of jfet 201 ) and n - type conductive substrate 104 ( the source contact of jfet 201 ) is set to zero . at the same time , a negative voltage of sufficient potential to pinch - off current flow within the channel of jfet 202 is applied between p - type conductive strip 102 ( the gate contact of jfet 202 ) and n - type conductive substrate 104 ( the source contact of jfet 202 ), and between p - type conductive strip 103 and n - type conductive substrate 104 . the pinch - off voltage is approximately given by : ## equ1 ## where q is the electronic charge ( 1 . 6 × 10 - 19 coulomb ), ε s is the dielectric constant of silicon ( 1 . 0 × 10 - 12 farad / cm ), r is the radius of the jfet channel ( n - type column 108 in the case of jfet 202 ), and n is the dopant concentration of the material within the jfet channel . under these applied voltages , a low resistance path will be provided between metal runner 105 and n - type conductive substrate 104 by n - type column 107 within jfet 201 . contrastingly , no such low resistance path between metal runner 105 and n - type conductive substrate 104 will be evident through jfet 202 ( which is pinched - off by voltage v g ), or through diode 203 ( metal runner 105 is electrically isolated from this diode ). therefore , if a resistance measurement taken between metal runner 105 and n - type conductive substrate 104 under these conditions yielded a low value , it could be concluded that a logical 0 was stored within the one - bit rom at the intersection of p - type conductive strip 101 and metal runner 105 . if the data stored within the rom at the intersection of p - type conductive strip 103 and metal runner 105 is to be read , the voltage between p - type conductive strip 103 and n - type conductive substrate 104 is set to zero . at the same time , a negative voltage of sufficient potential to pinch - off current flow within the channel of jfets 201 and 202 is applied between p - type conductive strip 101 ( the gate contact of jfet 201 ) and n - type conductive substrate 104 ( the source contact of jfet 201 ), and between p - type conductive strip 102 ( the gate contact of jfet 202 ) and n - type conductive substrate 104 ( the source contact of jfet 202 ). with these voltages applied , neither jfet 201 , jfet 202 , nor diode 203 will provide a low resistance path between metal runner 105 and n - type conductive substrate 104 ( both jfets will be pinched - off ). therefore , if a resistance measurement taken between metal runner 105 and n - type conductive substrate 104 under these conditions yielded a relatively high value , it could be concluded that a logical 1 was stored within the one - bit rom at the intersection of p - type conductive strip 103 and metal runner 105 . as described above , each intersection between metal runner 105 and p - type conductive strips 101 , 102 and 103 serves as a single bit rom . similarly , single bit roms are also located at the intersection of metal runner 106 and the three p - type conductive strips ( 101 , 102 and 103 -- see fig1 ). the configuration and operation of these roms would be identical to those associated with metal runner 105 . however , when reading the content of these roms , resistance measurements would have to be taken between metal runner 106 and n - type conductive substrate 104 . although fig1 provides an illustration of a device containing only six one - bit roms , it will be clear to those skilled in the art that the basic architecture of this device would , in a commercial product , be extended to provide semiconductor memory devices consisting of many hundreds of thousands , or multiple millions of one - bit roms arranged in a minimum period lattice structure upon a single semiconductor chip . present , well - known methods of semiconductor fabrication will facilitate the production of the semiconductor memory device of fig1 . in one particular method of fabrication , p - type conductive strips 101 , 102 and 103 are fashioned upon n - type conductive substrate 104 by growing an epitaxial layer of p - type conductive material upon n - type conductive substrate 104 . selected regions of this epitaxial layer are then etched away so that parallel p - type conductive strips of width w are formed . a layer of protective oxide is then grown upon the surface of the p - type conductive strips . a hole is then opened in the protective oxide at each site upon the p - type conductive strips where a one - bit rom storing a logical 0 is to be located . no such holes are opened in the protective oxide at the sites where one - bit roms storing logical 1s are to be located . these holes will have a diameter approximately equal to w ( as w was defined as the minimum feature size the particular fabrication technique being employed could produce ). next , n - type polysilicon is deposited over the surface of the oxide and the regions of the p - type conductive strips exposed through the holes in the oxide . this n - type polysilicon layer is then oxidized , effectively reducing the size of the holes as this oxide grows upon the n - type polysilicon walls of each hole . following this oxidation , jfets are formed by ion implanting a column of n - type material into the p - type conductive strips at each reduced diameter hole . this implantation is performed using with a narrow , fixed - position ion beam focused upon each region of p - type strip exposed through the holes in the protective oxide ( the oxidized n - type polysilicon is employed as a mask during this process ). the ion beam is kept in a fixed position during implantation to ensure a narrow column , and the orientation of the beam is kept orthogonal to the surface of the p - type strips to ensure the orthogonality of each implanted column . to increase surface conductivity of the implanted columns , a thin layer of n - type material is formed upon the exposed surface of the columns and surrounding p - type conductive strips . metal runners 105 and 106 are then fabricated so that they contact each of these n - type regions at the site of each rom storing a logical 0 . for roms storing logical 1s , the metal runners contact oxidized n - type polysilicon ( which serves as an insulator ). the doping concentration of the implanted n - type column must be chosen so that the implanted column is not destroyed as a result of impurity diffusion effects resulting from post - implantation processing of the semiconductor device ( i . e ., the fabrication of the metal runners and / or any annealing performed to activate the implanted column of n - type material ). avoiding such unwanted effects by &# 34 ; thermal budgeting &# 34 ; is well known , and it will be clear to those skilled in the art of semiconductor processing as to the particular dopant concentrations needed to ensure the fabrication of a workable device . fig3 provides a simplified cross - sectional view of the one - bit roms at the intersection of metal runner 105 with p - type conductive strips 102 and 103 . as shown , the rom at the intersection of metal runner 105 and p - type conductive strip 102 consists of a jfet including n - type column 108 . as described above , this n - type column was implanted into p - type conductive strip 102 through a layer of oxidized n - type polysilicon ( 301 ), and a hole opened in a protective oxide ( 302 ). an n - type conductive layer ( 303 ) was then formed upon the exposed surface of the n - type column and the surrounding p - type region . the rom at the intersection of metal runner 105 and p - type conductive strip 103 does not include a jfet , as a hole was not opened in protective oxide 302 over p - type conductive strip 103 to allow the implantation of an n - type column . a partial cross - sectional view of a rom incorporating an alternate embodiment of the invention is shown in fig4 . as illustrated , p - type conductive strips 401 , 402 , 403 , 404 and 405 are situated upon a conductive substrate 406 . adjacent to each of these p - type strips are n - type strips 407 , 408 , 409 and 410 , which serve to isolate the p - type strips from each other . metal runners 411 and 412 are orthogonally oriented with respect to the p - type and n - type strips . the p - type strips have a width of w , where w is the minimum feature size for the particular fabrication technique being employed . however , the n - type strips are ion implanted ( in a manner similar to that described for the semiconductor memory devices shown in fig1 and 3 ), and may therefore have a width less than w . the width of , and the separation between metal runners 411 and 412 are also equal to w . although it appears that metal runners 411 and 412 are in direct contact with the p - type and n - type conductive strips , the metal runners are isolated from the strips by a thin non - conductive oxide ( not shown in fig4 ). a one bit rom exists at each intersection of a metal runner and a p - type strip . as also shown , vertically - oriented columns of n - type conductive material 413 and 414 , each having a radius of r ( where 2r is less than w ), are situated beneath the areas where metal runner 411 overlays p - type conductive strips 402 and 403 , respectively . each of these n - type columns serves to provide an n - type conductive path between metal runner 411 and n - type conductive substrate 406 . no such n - type column is shown to exist beneath the area where metal runner 411 overlays p - type conductive strip 404 . each intersection between a metal runner and a p - type conductive strip serves as a one - bit rom , wherein the presence of an n - type column indicates a logical value of 0 , and the absence of an n - type column indicates a logical value of 1 . electrically , the equivalent circuit for the three one - bit roms associated with the portion of metal runner 411 illustrated in fig4 would be similar to the circuit illustrated in fig2 . a first jfet would be formed by p - type conductive strip 402 and n - type column 413 . metal runner 411 serves as the drain contact for this jfet , and the source contact would be n - type conductive substrate 406 . similarly , a second jfet is formed by p - type conductive strip 403 and n - type column 414 , with metal runner 411 serving as a drain contact , and n - type conductive substrate 406 serving as a source contact . the channels within each of these jfets are formed by the respective n - type columns . the gate of each jfet is formed by the material of the p - type conductive strip surrounding the n - type channel . a diode is formed by p - type conductive strip 404 and n - type conductive substrate 406 . to read the value of the digital information stored within the one - bit rom at the intersection of p - type conductive strip 402 and metal runner 411 , the voltage between p - type conductive strip 402 ( the gate contact of the first jfet ) and n - type conductive substrate 406 ( the source contact of the first jfet ) is set to zero . at the same time , a negative voltage of sufficient potential to pinch - off current flow within the channel of the second jfet is applied between p - type conductive strip 403 ( the gate contact of the second jfet ) and n - type conductive substrate 406 ( the source contact of the second jfet ). similar negative potentials are also applied between p - type conductive strips 401 , 404 and 405 and n - type conductive substrate 406 . the negative potentials being applied to the p - type conductive strips may result in condition called &# 34 ; punchthrough ,&# 34 ; which occurs when the depletion regions resulting from the applied negative voltages extend through the entirety of the n - type regions separating the p - type strips . this condition may result in current flowing from p - type strip 402 to p - type strips 401 and 403 ( via n - type strips 407 and 408 ), and cause a false reading of the digital information stored at the intersection of strip 402 and runner 411 . to mitigate the effects of punchthrough , regulated current paths to n - type conductive substrate 406 from p - type strips 402 and 404 are established ( illustrated as the paths including current generators 415 and 416 ). to mitigate the effects of punchthrough , regulated current paths to n - type conductive substrate 406 from p - type strips 401 and 403 are established . enough current is permitted to flow through each so that the depletion regions are controlled , but not so much as to allow the negative potential between conductive substrate 406 and p - type strips 401 and 403 to fall below the minimum level required to ensure pinch - off . under these applied voltages , a low resistance path will be provided between metal runner 411 and n - type conductive substrate 406 by n - type column 413 . contrastingly , no such low resistance path between metal runner 411 and n - type conductive substrate 406 will be evident through the second jfet ( which is pinched - off ), or through the diode formed by p - type conductive strip 404 and n - type conductive substrate 406 . therefore , a resistance measurement taken between metal runner 411 and n - type conductive substrate 406 under these conditions would yield a low reading , and indicate a logical 0 stored within the one - bit rom at the intersection of p - type conductive strip 403 and metal runner 411 . as with the previously described embodiment , data stored within other roms of the memory device of fig4 could be read by applying a zero voltage to the p - type conductive strip associated with a particular rom , and a negative voltage to all other p - type conductive strips . a resistance measurement between the metal runner associated with that particular rom and n - type conductive substrate 406 would reflect the logical value stored within that rom . a low resistance measurement would indicate the presence of a jfet and logical value of 0 . contrastingly , a high resistance measurement would indicate that no jfet exists at that runner and strip intersection , and a logical value of 1 is stored there . the fabrication of the semiconductor memory device of fig4 is similar to that of the device illustrated in fig1 . a p - type conductive region is fashioned upon n - type conductive substrate 406 through well - known epitaxial methods . n - type conductive strips 407 - 410 are then ion implanted through this p - type conductive region . this implantation also serves to separate the epitaxial p - type conductive region into p - type conductive strips 401 - 405 . a layer of protective oxide is then grown upon the surface of the p - type and n - type conductive strips . a hole ( having a diameter approximately equal to w ) is then opened in the protective oxide at each site upon the p - type conductive strips where a one - bit rom storing a logical 0 is to be located . n - type polysilicon is then deposited over the surface of the oxide and oxidized to reducing the size of the holes . jfets are then formed by ion implanting a column of n - type material into the p - type conductive strips at each reduced diameter hole . metal runners 411 and 412 are then fabricated so that they contact each of these implanted columns of n - type material at the site of each rom storing a logical 0 . for roms storing logical 1s , the metal runners contact oxidized n - type polysilicon ( which serves as an insulator ). it will be understood that the particular embodiment described above is only illustrative of the principles of the present invention , and that various modifications could be made by those skilled in the art without departing from the scope and spirit of the present invention , which is limited only by the claims that follow . one such modification would include extending the invention to architectures encompassing many hundreds of thousands , or multiple millions of one - bit roms fabricated in a minimum period lattice structure upon a semiconductor chip . furthermore , it will also be evident that the particular conductivity types specified for the various regions in the above embodiments could be reversed , as long as the polarity of any applied voltages were also reversed . other embodiments of the invention could be realized by substituting conductive semiconductor material runners for the metal runners . these semiconductor material runners would be fabricated from material having the same conductivity type as the columns of material implanted within the semiconductor memory device to indicate logical 0s .