referring to fig1 a phase converter embodying features of the present invention includes first and second input terminals in 1 and in 2 , first , second and third output terminals out 1 , out 2 and out 3 , a means for storing electricity in the form of a first capacitor c 1 , a first circuit means for charging the first capacitor in the form of a charging circuit 10 from the first and second input terminals in 1 and in 2 , a second circuit means for supplying a third phase to the third output terminal out 3 in the form of an output circuit 11 , and a controller 12 . the first and second input terminals in 1 and in 2 are generally connected to an electrical single phase alternating current ( ac ) voltage source such as a socket or two terminals connected to a utility company step - down transformer . in the illustrated embodiment the voltage between first and second input terminals in 1 and in 2 may be 480 vac . other voltages are suitable . the end of the capacitor c 1 that is positively charged by the charging circuit will hereinafter be designated the positive end and the opposite end will be designated the negative end . preferably , the storage capacitor c 1 is an electrolytic capacitor having a positive and a negative end . the charging circuit 10 has an input h bridge 14 , a first inductor l 1 and a first current transducer ct 1 . the input h bridge 14 includes first , second , third and fourth input switches , shown as first , second , third and fourth input transistors z 1 , z 2 , z 3 and z 4 , first , second , third and fourth input diodes d 1 , d 2 , d 3 , and d 4 the first current transducer ct 1 may be a current transformer , a hall - effect current sensor or other device . in the illustrated embodiment the first current transducer has a primary winding and a secondary winding . one end of the first inductor l 1 is connected to the first input terminal in 1 and the other end of the first inductor l 1 is connected to one end of the primary winding of the first current transducer ct 1 . the anode of the first input diode d 1 , the cathode of the second input diode d 2 , the emitter of the first input transistor z 1 and the collector of the second input transistor z 2 all are connected to the other end of the primary winding of the first current transducer ct 1 . the cathode of the first input diode d 1 and the collector of the first input transistor z 1 are connected to the positive end of the first capacitor c 1 . the anode of the second input diode d 2 and the emitter of the second input transistor z 2 are connected to the negative end of the first capacitor c 1 . the anode of the third input diode d 3 , the cathode of the fourth input diode d 4 , the emitter of the third input transistor z 3 and the collector of the fourth input transistor z 4 all are connected to the second input terminal in 2 . the cathode of the third input diode d 3 and the collector of the third input transistor z 3 are connected to the positive end of the first capacitor c 1 . the anode of the fourth input diode d 4 and the emitter of the fourth input transistor z 4 are connected to the negative end of the first capacitor c 1 . the output circuit 11 has an output h bridge , a second inductor l 2 , a second current transducer ct 2 , a transformer t 1 , second , third , fourth and fifth capacitors c 2 , c 3 , c 4 and c 5 , and first , second and third output terminals out 1 , out 2 and out 3 . the output h bridge includes first , second , third and fourth output switches , shown as first , second , third and fourth output transistors z 5 , z 6 , z 7 and z 8 , and first , second , third and fourth output diodes d 5 , d 6 , d 7 and d 8 . the second inductor l 2 and the second current transformer each include a primary winding and a secondary winding . the cathodes of the first and third output diodes d 5 and d 7 and the collectors of the first and third output transistors z 5 and z 7 are connected to the positive end of the first capacitor c 1 . the anodes of the second and fourth output diodes d 6 and d 8 and the emitters of the second and fourth output transistors z 6 and z 8 are connected to the negative end of the first capacitor c 1 . the anode of the first output diode d 5 , the cathode of the second output diode d 6 , the emitter of the first output transistor z 5 and the collector of the second output transistor z 6 are connected to one end of the primary winding of the second inductor l 2 . the other end of the primary winding of the second inductor l 2 is connected to one end of the second capacitor c 2 and to one end of the primary winding of the transformer t 1 . the anode of the third output diode d 7 , the cathode of the fourth output diode d 8 , the emitter of the third output transistor z 7 and the collector of the fourth output transistor z 8 are connected to one end of the primary winding of the second current transducer ct 2 . the other end of the primary winding of the second current transducer ct 2 is connected to the other end of the second capacitor c 2 and the other end of the primary winding of the transformer t 1 . one end of the secondary winding of the transformer t 1 and one end of the third capacitor c 3 are connected to the second output terminal out 2 and to one end of the fourth capacitor c 4 . the other end of the fourth capacitor c 4 is connected to the first output terminal out 1 . the other end of the secondary winding of the transformer t 1 and the other end of the third capacitor c 3 are connected to the third output terminal t 3 . one end of the fifth capacitor c 5 is connected to the first output terminal out 1 and the other end of the fifth capacitor c 5 is connected to the third output terminal out 3 . the first input terminal in 1 is connected to the first output terminal out 1 and the second input terminal in 2 is connected to the second output terminal out 2 . the controller 12 includes a plurality of connections to the above described circuit that are described by way of example , and not as a limitation , hereinafter as terminals . the first , second , third , and fourth positive transistor terminals vge 1 +, vge 2 +, vge 3 +, and vge 4 + are connected to the gates of the first , second , third and fourth input transistors z 1 , z 2 , z 3 and z 4 . the first , second , third and fourth negative transistor terminals vge 1 −, vge 2 −, vge 3 − and vge 4 − are connected to the emitters of the first , second , third and fourth input transistors z 1 , z 2 , z 3 and z 4 . the fifth , sixth , seventh and eighth positive transistor terminals vge 5 +, vge 6 +, vge 7 +, and vge 8 + are connected to the gates of the first , second , third and fourth output transistors z 5 , z 6 , z 7 and z 8 . the fifth , sixth , seventh and eighth negative transistor terminals vge 5 −, vge 6 −, vge 7 −, and vge 8 − are connected to the emitters of the first , second , third and fourth output transistors z 5 , z 6 , z 7 and z 8 . the voltage in terminal vin is connected to the first input terminal in 1 , the voltage out terminal vout is connected to the third output terminal out 3 and the signal common terminal sc is connected to the second input terminal in 2 . the positive and negative current in terminals iin + and iin − are connected to opposite ends of the secondary winding of the first current transducer ct 1 . the positive and negative current out terminals iout + and iout − are connected to opposite ends of the secondary winding of the second current transducer ct 1 . the positive and negative first capacitor voltage terminals vc 1 + and vc 1 − are connected to opposite ends of the secondary winding of the second inductor l 2 . the positive and negative transformer voltage terminals vdc + and vdc − are connected to opposite ends of the primary winding of the transformer t 1 . as shown in fig2 controller 12 includes a microcontroller m 1 , first , second , third , fourth and fifth buffer amplifiers ba 1 , ba 2 , ba 3 , ba 4 and ba 5 , a first input circuit cir 1 , a second input circuit cir 2 , and first , second , third , fourth , fifth , sixth , seventh and eighth output drivers od 1 , od 2 , od 3 , od 4 , od 5 , od 6 , od 7 and od 8 . the input of the first buffer amplifier ba 1 is connected to the voltage in terminal vin and the output of the first buffer amplifier ba 1 is connected to the microcontroller m 1 . the input of the second buffer amplifier ba 2 is connected to the voltage out terminal vout and the output of the second buffer amplifier ba 2 is connected to the microcontroller m 1 . the input of the third buffer amplifier ba 3 is connected to the positive current in terminal iin + and the output of the third buffer amplifier ba 3 is connected to the microcontroller m 1 . the input of the fourth buffer amplifier ba 4 is connected to the positive current out terminal iout + and the output of the fourth buffer amplifier ba 4 is connected to the microcontroller m 1 . the input of the fifth buffer amplifier ba 5 is connected to the first input circuit cir 1 and the output of the fifth buffer amplifier ba 5 is connected to the microcontroller m 1 . the first input circuit cir 1 includes a first resistor r 1 , first , second , third and fourth controller diodes d 9 , d 10 , d 11 , d 12 , and sixth and seventh capacitors c 6 and c 7 . the anode of the first controller diode d 9 and the cathode of the third controller diode d 11 are connected to the positive first capacitor voltage terminal vcl +, and the anode of the second controller diode d 10 and the cathode of the fourth controller diode d 12 are connected to the negative first capacitor voltage terminal vc 1 −. the sixth capacitor c 6 is connected between the cathodes of the first and second controller diodes d 9 and d 10 , and the input to the fifth buffer amplifier ba 5 . the anodes of the third and fourth controller diodes d 11 and d 12 are connected to ground . the seventh capacitor c 7 and the first resistor r 1 each connect between the input to the fifth buffer amplifier ba 5 and ground . the second input circuit cir 2 includes second , third and fourth resistors r 2 , r 3 and r 4 , an eighth capacitor c 8 and a sixth buffer amplifier ba 6 . one end of the second resistor r 2 is connected to the positive transformer voltage terminal vdc + and one end of the third resistor r 3 is connected to the negative transformer voltage terminal vdc −. the other ends of the second and third resistors r 2 and r 3 are each connected to one end of the fourth resistor r 4 , one end of the eighth capacitor c 8 and to the negative input of the sixth buffer amplifier ba 6 . the positive input of the sixth buffer amplifier ba 6 is connected to vref , and the controls of the sixth buffer amplifier ba 6 are connected to vcc and ground . the other ends of the fourth resistor r 4 and the eighth capacitor c 8 , and the output of the sixth buffer amplifier ba 6 are connected together to the microcontroller m 1 . the inputs of the first , second , third , fourth , fifth , sixth , seventh and eighth output drivers od 1 , od 2 , od 3 , od 4 , od 5 , od 6 , od 7 and od 8 are each connected to the microcontroller m 1 . the positive outputs of the first , second , third , fourth , fifth , sixth , seventh and eighth output drivers od 1 , od 2 , od 3 , od 4 , od 5 , od 6 , od 7 and od 8 are connected to the first , second , third , fourth , fifth , sixth , seventh and eighth positive transistor terminals vge 1 +, vge 2 +, vge 3 +, vge 4 +, vge 5 +, vge 6 +, vge 7 +, and vge 8 +, respectively . the negative outputs of the first , second , third , fourth , fifth , sixth , seventh and eighth output drivers od 1 , od 2 , od 3 , od 4 , od 5 , od 6 , od 7 and od 8 are connected to the first , second , third , fourth , fifth , sixth , seventh and eighth negative transistor terminals vge 1 −, vge 2 −, vge 3 −, vge 4 −, vge 5 −, vge 6 −, vge 7 −, and vge 8 −, respectively . the negative current in terminal iin −, the negative current out terminal iout − and the signal common terminal sg are connected to ground . referring to fig1 and 2 , the first , second third and fourth input diodes d 1 , d 2 , d 3 and d 4 rectify input voltage and charge the first capacitor c 1 . during the input positive half cycle , when the voltage at the first input terminal in 1 is greater that the voltage at the second input terminal , current flows through the first and fourth input diodes d 1 and d 4 . during this input positive half cycle , the third input transistor z 3 is switched on and off at a high frequency with a variable duty cycle with pulse width modulation ( pwm ) to induce current flow through the first inductor l 1 . the pwm switching of the third input transistor z 3 in combination with the first inductor l 1 can charge the first capacitor c 1 above maximum voltage between the first and second input terminals in 1 and in 2 and the pwm duty cycles are selected to provide a sinewave current flow through the first inductor l 1 , as fully described in u . s . pat . no . 6 , 297 , 971 . during the input negative half cycle , the fourth input transistor z 4 is switched with pwm . power can be directed from the first capacitor c 1 back through the first and second input terminals in 1 and in 2 to the voltage source by closing the fourth input transistor z 4 and pwm switching the first input transistor z 1 during the input positive half cycle , and closing the third input transistor z 3 and pwm switching the second input transistor z 2 during the input negative half cycle . the input h bridge 14 in combination with the first inductor l 1 controllably charges the first capacitor c 1 while providing a sinewave input current and controllably directs power from the first capacitor c 1 back to the voltage source as needed . the output circuit 11 functions in a similar fashion . during the output positive half cycle , when the voltage supplied to the third output terminal out 3 is positive , the first output transistor z 5 is turned on and the fourth output transistor z 8 is pwm switched to provide a sinusoidal positive voltage at the third output terminal out 3 . during the output negative half cycle the second output transistor z 6 is closed and the third output transistor z 7 is pwm switched , reversing the direction of current flow through the transformer t 1 and providing a sinusoidal negative voltage to the third output terminal out 3 . the first , second , third and fourth output diodes d 5 , d 6 , d 7 and d 8 form a full - wave rectifier bridge so that when the voltage across the load is greater than the voltage across the first capacitor c 1 , power will be fed back to the first capacitor c 1 . the controller 12 monitors the input and output voltages and currents , and switches the first , second , third and fourth input and output transistors z 1 , z 2 , z 3 , z 4 , z 5 , z 6 , z 7 and z 8 appropriately . the input voltage is sampled at the voltage in terminal vin , and the generated phase is sampled at the voltage out terminal vout . the signal common terminal sc is used for the reference point . the current through the first inductor l 1 is measured using the first current transducer ct 1 and the second current transducer ct 2 measures the current through the second inductor l 2 . the peak - to - peak value of the high frequency signal across the second inductor l 2 is exactly equal to the dc value of the voltage across the first capacitor c 1 . the voltage across the first capacitor c 1 is measured by applying the signal across the first capacitor voltage terminals vc 1 + and vc 1 −, which are connected to opposite ends of the secondary winding of the second inductor l 2 , to the full - wave rectifier of the first input circuit cir 1 . the high - pass filter , in the first input circuit cir 1 , at the rectifier output gives a dc voltage directly proportional to the first capacitor c 1 voltage which can then be referenced to the signal common terminal sc and measured by the microprocessor m 1 . the same result could be obtained by using a secondary coil on the first inductor l 1 . the second input circuit cir 2 provides the integral of the voltage across the primary winding of the transformer t 1 , to assure that the transformer t 1 voltage has an average value of zero . typically the controller 12 would produce a pwm frequency between 1 khz and 100 khz . the controller 12 also senses for overload conditions in the input and output current and in the individual transistors and adjusts the transistor modulation to limit the transistor current to safe values . [ 0040 ] fig3 shows a phase converter embodying features of the present invention , with an alternative charging circuit 10 having the first , second , third and fourth input diodes d 1 , d 2 , d 3 and d 4 , the first current transducer ct 1 , the first inductor l 1 , the first input transistor z 1 , and a fifth input diode d 13 . the anode of the first input diode d 1 and the cathode of the second input diode d 2 are connected to the first input terminal in 1 . the anode of the third input diode d 3 and the cathode of the fourth input diode d 4 are connected to the second input terminal in 2 . the cathodes of the first and third input diodes d 1 and d 3 are connected to one end of the first current transducer ct 1 . the other end of the first current transducer ct 1 is connected to one end of the first inductor l 1 . the other end of the first inductor l 1 is connected to the collector of the first input transistor z 1 and to the anode of the fifth input diode d 13 . the cathode of the fifth input diode d 13 is connected to the positive end of the first capacitor c 1 . the anodes of the second and fourth input diodes d 2 and d 4 are connected to the emitter of the first input transistor z 1 and to the negative end of the first capacitor c 1 . the controller 12 includes a plurality of connections to the above described circuit that are described for the circuit in fig3 as in the circuit of fig1 as terminals . the first positive transistor terminals vge 1 + is connected to the gate of the first input transistor z 1 and the first negative transistor terminals vge 1 − is connected to the emitter of the first input transistor z 1 . the fifth , sixth , seventh and eighth positive transistor terminals vge 5 +, vge 6 +, vge 7 +, and vge 8 + are connected to the gates of the first , second , third and fourth output transistors z 5 , z 6 , z 7 and z 8 . the fifth , sixth , seventh and eighth negative transistor terminals vge 5 −, vge 6 −, vge 7 −, and vge 8 − are connected to the emitters of the first , second , third and fourth output transistors z 5 , z 6 , z 7 and z 8 . the voltage in terminal vin is connected to the first input terminal in 1 , the voltage out terminal vout is connected to the third output terminal out 3 and the signal common terminal sc is connected to the second input terminal in 2 . the positive and negative current in terminals iin + and iin − are connected to opposite ends of the secondary winding of the first current transducer ct 1 . the positive and negative current out terminals iout + and iout − are connected to opposite ends of the secondary winding of the second current transducer ct 1 . the positive and negative first capacitor voltage terminals vc 1 + and vc 1 − are connected to opposite ends of the secondary winding of the second inductor l 2 . the positive and negative transformer voltage terminals vdc + and vdc − are connected to opposite ends of the primary winding of the transformer t 1 . referring to fig4 controller 12 includes a microcontroller m 1 , first , second , third , fourth and fifth buffer amplifiers ba 1 , ba 2 , ba 3 , ba 4 and bas , a first input circuit cir 1 , a second input circuit cir 2 , and first , fifth , sixth , seventh and eighth output drivers od 1 , od 5 , od 6 , od 7 and od 8 . the input of the first buffer amplifier ba 1 is connected to the voltage in terminal vin and the output of the first buffer amplifier ba 1 is connected to the microcontroller m 1 . the input of the second buffer amplifier ba 2 is connected to the voltage out terminal vout and the output of the second buffer amplifier ba 2 is connected to the microcontroller m 1 . the input of the third buffer amplifier ba 3 is connected to the positive current in terminal iin + and the output of the third buffer amplifier ba 3 is connected to the microcontroller m 1 . the input of the fourth buffer amplifier ba 4 is connected to the positive current out terminal iout + and the output of the fourth buffer amplifier ba 4 is connected to the microcontroller m 1 . the input of the fifth buffer amplifier ba 5 is connected to the first input circuit cir 1 and the output of the fifth buffer amplifier bas is connected to the microcontroller m 1 . the first input circuit cir 1 includes a first resistor r 1 , first , second , third and fourth controller diodes d 9 , d 10 , d 11 , d 12 , and sixth and seventh capacitors c 6 and c 7 . the anode of the first controller diode d 9 and the cathode of the third controller diode d 11 are connected to the positive first capacitor voltage terminal vc 1 +, and the anode of the second controller diode d 10 and the cathode of the fourth controller diode d 12 are connected to the negative first capacitor voltage terminal vc 1 −. the sixth capacitor c 6 is connected between the cathodes of the first and second controller diodes d 9 and d 10 , and the input to the fifth buffer amplifier ba 5 . the anodes of the third and fourth controller diodes d 11 and d 12 are connected to ground . the seventh capacitor c 7 and the first resistor r 1 each connect between the input to the fifth buffer amplifier ba 5 and ground . the second input circuit cir 2 includes second , third and fourth resistors r 2 , r 3 and r 4 , an eighth capacitor c 8 and a sixth buffer amplifier ba 6 . one end of the second resistor r 2 is connected to the positive transformer voltage terminal vdc + and one end of the third resistor r 3 is connected to the negative transformer voltage terminal vdc −. the other ends of the second and third resistors r 2 and r 3 are each connected to one end of the fourth resistor r 4 , one end of the eighth capacitor c 8 and to the negative input of the sixth buffer amplifier ba 6 . the positive input of the sixth buffer amplifier ba 6 is connected to vref , and the controls of the sixth buffer amplifier ba 6 are connected to vcc and ground . the other ends of the fourth resistor r 4 and the eighth capacitor c 8 , and the output of the sixth buffer amplifier ba 6 are connected together to the microcontroller m 1 . the inputs of the first , fifth , sixth , seventh and eighth output drivers od 1 , od 5 , od 6 , od 7 and od 8 are each connected to the microcontroller m 1 . the positive outputs of the first , fifth , sixth , seventh and eighth output drivers od 1 , od 5 , od 6 , od 7 and od 8 are connected to the first , fifth , sixth , seventh and eighth positive transistor terminals vge 1 +, vge 5 +, vge 6 +, vge 7 +, and vge 8 +, respectively . the negative outputs of the first , fifth , sixth , seventh and eighth output drivers od 1 , od 5 , od 6 , od 7 and od 8 are connected to the first , fifth , sixth , seventh and eighth negative transistor terminals vge 1 −, vge 5 −, vge 6 −, vge 7 −, and vge 8 −, respectively . the negative current in terminal iin −, the negative current out terminal iout − and the signal common terminal sg are connected to ground . the phase converter shown in fig3 and 4 functions in a similar fashion the phase converter shown in fig1 and 2 , except that power cannot be fed back from the first capacitor c 1 to the first and second input terminals in 1 and in 2 . the first , second , third and fourth input diodes d 1 , d 2 , d 3 and d 4 form a full - wave rectifier . the first input transistor z 1 is pwm switched to , in combination with the first inductor l 1 , provide draw a sinusoidal input current from the first and second input terminals in 1 and in 2 . the fifth input diode d 13 prevents reverse current flow between the positive and negative ends of the first capacitor c 1 . [ 0050 ] fig5 shows the voltages v 1 , v 2 and v 3 at the first , second and third output terminals out 1 , out 2 and out 3 , respectively , over a period of about 30 milliseconds for an input source of 240vac across the first and second input terminals in 1 and in 2 . the voltages v 1 and v 2 are about 120 vrms with a maximum amplitude of 120 ×{ square root }{ square root over ( 2 )}= 170v and are 180 degrees out of phase . the maximum amplitude of voltage v 3 is 170 ×{ square root }{ square root over ( 3 )}= 294v and voltage v 3 is 90 degrees out phase with v 1 and v 2 . fig6 shows these same voltages as the voltages v 32 , v 13 and v 21 between the first , second and third output terminals out 1 , out 2 and out 3 . in this way , by increasing the amplitude of the voltage at the third output terminal out 3 and shifting the phase by 90 degrees , balanced three phase ac power is produced by the converter and supplied to the load . the static phase converter of the present invention , unlike many prior known devices , does not require that the components be selected to match a specific load and provides balanced three phase ac power over a range of loads . this static phase converter is more efficient , less complex and less expensive than prior known inverters . this phase converter provides sinusoidal input current instead of highly peaked input current , preventing negative effects on the power grid . this phase converter can be used to supply power to inductive , capacitive or resistive loads . the phase converter of the present invention does not require the voltage doubling required by the phase converter of u . s . pat . no . 6 , 297 , 971 , because the output h bridge 15 switches the output of the first capacitor c 1 . in the illustrated embodiment the output h bridge 15 switches the output of the first capacitor c 1 by cyclically reversing the current direction through the primary winding of the transformer t 1 . the bus capacitor voltage in the present invention is half that of the prior version , and therefore switches with half the voltage rating can be used . higher input voltages are possible with the same switches used in the prior version , or faster and less expensive switches can be used for the prior input voltage . although the present invention has been described with a certain degree of particularity , it is understood that the present disclosure has been made by way of example and that changes in details of structure may be made without departing from the spirit thereof .