the preferred embodiments of the invention will now be described in detail while referring to the drawings . the same reference numerals are used throughout to denote identical or corresponding components , and no explanation for them will be given . while referring to fig1 , a transparent latch circuit 10 comprises a multiplexer ( mux ) 1 , a master latch circuit 2 , a slave latch circuit 3 , an inverter 4 and a latch stop circuit 5 . the mux 1 receives a function data signal di and a scan data signal si , and selects a signal to be output to the master latch circuit 2 . specifically , the mux 1 receives a select signal se from a controller ( not shown ), and when the select signal se level is l , the mux 1 outputs the function data signal di to the master latch circuit 2 , while when the select signal se level is h , the mux 1 outputs the scan data signal si to the master latch circuit 2 . the inverter 4 receives a clock signal clk , inverts the signal clk and outputs the inverted signal as a signal φiv 4 , and the latch stop circuit 5 , constituted by a nand gate , receives the signal φiv 4 and a test signal te and outputs the nand of these signals . specifically , when the test signal te level is l , the latch stop circuit 5 outputs a level h latch stop signal φg 5 . when the test signal te level is h , the latch stop circuit 5 outputs , as a signal φg 5 , a signal complementary to the signal φiv 4 . while referring to fig2 , the master latch circuit 2 includes nand gates 22 to 25 and an inverter 21 . the nand gate 22 receives a signal ( the function data signal di or the scan data signal si ) from the mux 1 and the signal φiv 4 from the inverter 4 , and outputs the nand of these signals as a signal φg 22 . the nand gate 23 receives the signal φiv 21 from the inverter 21 and the signal φiv 4 , and outputs the nand of these signals as a signal φg 23 . the inverter 21 receives a signal ( the function data signal di or the scan data signal si ) from the mux 1 , and inverts the signal . the nand gates 24 and 25 constitute an sr latch circuit 26 . the nand gate 24 of the sr latch circuit 26 has two input terminals ; one terminal is connected to the output terminal of the nand gate 22 , and the other is connected to the output terminal of the nand gate 25 . the nand gate 25 has two input terminals ; one terminal is connected to the output terminal of the nand gate 23 , and the other is connected to the output terminal of the nand gate 24 . when the signal φg 22 level is h , and the signal φg 23 level is l , the sr latch circuit 26 outputs a signal φm at level l . when the signal φg 22 level is l and the signal φg 23 level is h , the sr latch circuit 26 outputs a signal φm at level h . when both of the signals φg 22 and φg 23 are at level h , the sr latch circuit 26 latches the signal φm . the structure of the slave latch circuit 3 is the same as that of the master latch circuit 2 . it should be noted that in the slave latch circuit 3 a nand gate 22 receives the signal φm from the master latch circuit 2 and the signal φg 5 from the latch stop circuit 5 ; a nand gate 23 receives the signal φiv 21 from an inverter 21 , which inverts the signal φm , and the signal φg 5 from the latch stop circuit 5 ; and an sr latch circuit 26 outputs a signal do . an explanation will now be given for a normal operation and the scan test operation performed by the thus arranged transparent latch circuit 10 . normal operation of the transparent latch circuit during a normal operation , the test signal te level is l . then , since the select signal se received by the mux 1 is at level l , the mux 1 selects the function data signal di and the master latch circuit 2 receives the function data signal di . at this time , the master latch circuit 2 in the transparent latch circuit 10 serves as a latch circuit , and the slave latch circuit 3 simply lets the received signal pass through . this processing will be described in detail below . [ heading - 0050 ] ( 1 ) case wherein the clock signal clk drops from level h to level l when the clock signal clk drops from level h to level l , the signal φiv 4 output by the inverter 4 goes to level h . at this time , while the function data signal di is at level l , the signal φg 22 output by the nand gate 22 goes to level h and the signal φg 23 output by the nand gate 23 goes to level l . as a result , the sr latch circuit 26 outputs the signal φm at level l . when the function data signal di is at level h , the signal φg 22 goes to level l and the signal φg 23 goes to level h . as a result , the sr latch circuit 26 outputs the signal φm at level h . therefore , when the clock signal clk drops from level h to level l , the master latch circuit 2 outputs the function data signal d 1 as the signal φm . at this time , the slave latch circuit 3 lets the signal φm received from the master latch circuit 2 pass through , and outputs the signal as the signal do . specifically , during a normal operation , since the test signal te is at level l , the latch stop circuit 5 outputs the latch stop signal φg 5 at level h . when the signal φm is at level h , the signal φg 22 output by the nand gate 22 goes to level l , and the signal φg 23 output by the nand gate 23 goes to level h , so that the sr latch circuit 26 outputs the signal do at level h . when the signal φm is at level l , the signal φg 22 goes to level h , while the signal φg 23 goes to level l , and the sr circuit 26 outputs the signal do at level l . therefore , the received signal φm passes through the slave latch circuit 3 , which outputs the signal as the signal do . [ heading - 0053 ] ( 2 ) case wherein the clock signal clk rises from level l to level h when the clock signal clk rises from level l to level h , the master latch circuit 2 latches the signal φm . specifically , since the signal φiv 4 goes to level l , the signals φg 22 and φ 23 output by the nand gates 22 and 23 in the master latch circuit 2 go to level h . therefore , the sr latch circuit 26 latches the signal φm . at this time , since the test signal te is at level l , the latch stop circuit 5 outputs the latch stop signal φg 5 at level h . thus , the received signal φm passes through the slave latch circuit 3 , which outputs the signal as the signal do . in this manner , during a normal operation , the master latch circuit 3 in the transparent latch circuit 10 serves as a latch circuit , and the received signal φm is passed through the slave latch circuit 3 . therefore , overall , the transparent latch circuit 10 functions as a latch circuit . test scan operation of the transparent latch circuit referring to fig3 , the test signal te goes to level h during the test scan operation . further , since the scan data signal si is employed for the test scan , the select signal se also goes to level h . then , when at time t1 the clock signal clk goes to level h , the signal φiv 4 output by the inverter 4 goes to level l . at this time , since the select signal se is at level h , the mux 1 selects the scan data signal si . in the master latch circuit 2 , the nand gates 22 and 23 receive the signal φiv 4 at level l , and outputs the signals φg 22 and φg 23 at level h . as a result , the sr latch circuit 26 latches the signal φm . further , since , at time t1 , the master latch circuit 2 receives a scan data signal si - 3 , the signal φm is equal to the scan data signal si - 3 . thus , during the period ( from time t1 to t2 ) wherein the clock signal clk is at level h , the master latch circuit 2 continues to latch the scan data signal si - 3 . focusing on the operation of the slave latch circuit 3 during the period from time t1 to t2 , the latch stop circuit 5 receives the test signal te at level h and the signal φiv 4 at level l , and outputs the signal φg at level h . when the slave latch circuit 3 receives the signal φm at level h , the nand gate 22 receives the signal φg 5 at level h and the signal φm at level h , and outputs the signal φg 22 at level l . further , the nand gate 23 receives the signal φiv 21 at level h and the signal φg 5 at level h , and outputs the signal φg 23 . as a result , the sr latch circuit 26 outputs the signal do at level h . on the other hand , when the slave latch circuit 3 receives the signal φm at level l , the nand gate 22 outputs the signal φg 22 at level h , and the nand gate 23 outputs the signal φg 23 at level l . as a result , the sr latch circuit 26 outputs the signal do at level l . therefore , with a delay of γt following time t1 , the output signal do goes to the same level as the signal φm ( i . e ., the scan data signal si - 3 ). the delay γt is generated using the time constant for the transparent latch circuit 10 . the operation of the transparent latch circuit 10 during the period from time t2 to t3 will now be described . when the clock signal clk goes to level l at time t2 , the signal φiv 4 input to the nand gates 22 and 23 of the master latch circuit 2 goes to level h . therefore , the scan test data signal si , received during the period from time t2 to t3 , is passed through the sr latch circuit 26 , in the master latch circuit 2 , that outputs this signal si unchanged . at time t2 , the slave latch circuit 3 receives the signal φg 5 at level l , and the signals φg 22 and φg 23 , output by the nand gates 22 and 23 in the slave latch circuit 3 , go to level h . therefore , until time t3 , in the slave latch circuit 3 , the sr latch circuit 26 latches the signal φm ( i . e ., the scan data signal si - 3 ) received by the slave latch circuit 3 . following time t3 , the operation performed during the period from time t1 to t2 is repeated . at time t5 , the select signal se goes to level l , and the mux 1 selects a function data signal so 0 that is then output to the master latch circuit 2 . this is the result of observations made of the output of a logic cone encompassing a plurality of the transparent latch circuits 10 . at this time , since the test signal te is maintained at level h , the master latch circuit 2 and the slave latch circuit 3 perform the same operations as when the scan data signal si is received . through the above described processing performed , during a scan test operation , at the leading edge of the clock signal clk , the master latch circuit 2 in the transparent latch circuit 10 latches the received scan data signal si , and the received signal φm is passed through the slave latch circuit 3 . at the trailing edge of the clock signal clk , the received scan data signal si passes through the master latch circuit 2 , and the slave latch circuit 3 latches the output signal do . thus , the transparent latch circuit 10 functions as a flip - flop circuit . according to this embodiment , since in the scan test operation the transparent latch circuit 10 serves as a flip - flop circuit , a one - phase clock can be employed to perform the scan test , and during a normal operation , the transparent latch circuit 10 can be used as a latch circuit . therefore , since the transparent latch circuit 10 of this embodiment is employed as a ram wrapper or for cycle stealing , the scan test can be performed using a one - phase signal , and the test coverage in the gsd can be improved . according to the transparent latch circuit 10 of the first embodiment , upon receiving the latch stop signal φg 5 during a normal operation , the latch the slave latch circuit 3 lets a received signal pass through , and the master latch circuit 2 serves as a latch circuit . however , during a normal operation , the master latch circuit may let a received signal pass through , and the latch circuit 3 may serve as a latch circuit . while referring to fig4 , a transparent latch circuit 20 comprises a latch stop circuit 50 , instead of the inverter 4 and the latch stop circuit 5 of the transparent latch circuit 10 . the latch stop circuit 50 has two input terminals , at one of which it receives a test signal te and at the other , a clock signal clk . thereafter , a nand of the test signal te and the clock signal clk is obtained and output by the latch stop circuit 50 . specifically , when the test signal te is at level l , the latch stop circuit 50 outputs a latch stop signal φg 50 at level h . and when the test signal is at level h , the latch stop circuit 50 outputs a signal / clk that is complementary to the clock signal clk . the output signal of the latch stop circuit 50 is transmitted to nand gates 22 and 23 of a master latch circuit 2 , while the clock signal φclk is transmitted to nand gates 22 and 23 of a slave latch circuit 3 . the other components of the structure are the same as those for the transparent latch circuit 10 . using this circuit configuration for the transparent latch circuit 20 , during a normal operation , the latch stop circuit 50 outputs the latch stop signal φg 50 , and as a result , a received function data signal di is passed through the master latch circuit 2 . at this time , the slave latch circuit 3 receives the clock signal clk , and serves as a latch circuit . during the scan test operation , the latch stop circuit 50 outputs the signal / clk while the master latch circuit 2 and the slave latch circuit 3 function as latch circuits , and overall , the transparent latch circuit 20 serves as a flip - flop circuit . since the transparent latch circuit 20 serves as a latch circuit during a normal operation , and serves as a flip - flop circuit during the scan test operation , the test coverage can be improved for the gsd , for which the scan test is performed using a one - phase signal . third embodiment according to the first and the second embodiments , the transparent latch circuits 10 and 20 function as latch circuits during a normal operation , and function as flip - flop circuits during a scan test operation , so that a scan test is enabled for the gsd . when the two transparent latch circuits 10 of the first embodiment are connected , this circuit structure can be operated as a flip - flop circuit , even during a normal operation . specifically , when at the preceding stage the master latch circuit 2 in the transparent latch circuit 10 latches the function data signal di , at the succeeding stage an input signal is passed through the master latch circuit 2 in the transparent latch circuit 10 , while when at the preceding stage the function data signal di passes through the master latch circuit 2 of the transparent latch circuit 10 , at the succeeding stage the master latch circuit 2 of the transparent latch circuit 10 latches the output signal do . as for the transparent latch circuit 20 , the same arrangement is employed as that used in the second embodiment . in order to perform the above described operation , a circuit device for inverting the clock signal clk must be inserted between the transparent latch circuits at the two stages . however , since clock skew would occur upon the insertion of the circuit device , and since an erroneous operation may occur as a result of the clock skew , it is preferable that the clock skew be prevented . as is shown in fig5 , a transparent latch circuit 30 according to a third embodiment is a combination of the transparent latch circuits 10 and 20 . specifically , the output terminal of the slave latch circuit 3 of the transparent latch circuit 10 is connected to the function data signal di input terminal of the mux 1 of the transparent latch circuit 20 , and the input terminal of the inverter 4 of the transparent latch circuit 10 is connected to the clock signal clk input terminal of the transparent latch circuit 20 . normal operation of the transparent latch circuit 30 in fig5 will now be explained . while referring to fig6 , during a normal operation , a test signal te input to the transparent latch circuit 30 goes to level l . as a result , the slave latch circuit 3 of the transparent latch circuit 10 receives a latch stop signal φg 5 from the latch stop circuit 5 , permits the signal φm , received from the master latch circuit 2 , to pass through continuously , and outputs the signal φm to the transparent latch circuit 20 . therefore , in the transparent latch circuit 10 , only the master latch circuit 2 serves as a latch circuit . in the transparent latch circuit 20 , the master latch circuit 2 receives the latch stop signal φg 50 from the latch stop circuit 50 , permits the signal received from the transparent latch circuit 10 to pass through , and outputs the signal to the slave latch circuit 3 , which serves as a latch circuit of the transparent latch circuit 20 . therefore , during a normal operation , in the transparent latch circuit 30 , the master latch circuit 2 , in the transparent latch circuit 10 , and the slave latch circuit 3 , in of the transparent latch circuit 20 , function as latch circuits . when the clock signal clk goes to level h at time t10 , the signal φiv 4 input to the master latch circuit 2 , in the transparent latch circuit 10 , goes to level l , while the clock signal clk input to the slave latch circuit 3 , in the transparent latch circuit 20 , is at level h . therefore , during the time period t10 to t20 , the master latch circuit 2 in the transparent latch circuit 10 latches a received function data signal di , and after a delay of γt2 from time t10 , in accordance with the time constant , the slave latch circuit 3 in the transparent latch circuit 3 passes the function data signal di through . when the clock signal clk goes to level l at time t20 , the master latch circuit 2 in the transparent latch circuit 10 passes a received function data signal d 2 through , while the slave latch circuit 3 in the transparent latch circuit 20 latches an output signal do ( function data signal d 1 ). as a result , during a normal operation , the transparent latch circuit 30 functions as a flip - flop circuit . further , since a circuit device for inverting the clock signal clk need not be arranged between the transparent latch circuits 10 and 20 , clock skew does not occur . preferred embodiments of the present invention have been explained . these embodiments , however , are merely examples . the present invention is not limited to the embodiments and can be provided by variously modifying the embodiments without departing from the scope of the invention .