shown in fig2 is a perspective diagram of a system in which the present invention may be employed . a transparent digitizer 22 , of a type which is commercially available from a number of sources , is placed over a flat display panel 24 , which may be of the liquid crystal display type , also commercially available . a stylus 26 is electronically coupled to the digitizer 22 through electronic control circuitry , represented by block 28 . the display panel 24 is coupled to the control circuitry 28 by means of a data processor 30 which performs the necessary translation of the data from the digitizer 22 to cause a representation of said data to appear on the display panel 24 . thus as the operator writes on the the digitizer 22 using the stylus 26 , the writing is digitized , processed and displayed on the display panel 24 substantially simultaneously . as previously described in the background of the invention , the quality of the digitized handwritten script displayed on the panel 24 is determined by the resolution of the digitizer and the particular display which is used . use of a display with a lower resolution than the digitizer resolution requires a downscaling of the digitizer data before the data can be displayed . such downscaling may result in a distorted appearance of the written material on the display because of a larger quantization error at the lower resolution . in the present invention , the distortion referred to above is reduced or eliminated by the introduction of a hysteresis loop into the process of mapping the high resolution data from the digitizer 22 into the lower resolution display 24 . fig3 a and 3b show respective graphical representations of two mapping processes . in fig3 a , no hysteresis is used , while in fig3 b , hysteresis is used . the horizontal coordinates of both of these graphs represent the high resolution data hrd , while the vertical coordinates represent the mapped lower resolution data lrd . the scale of reduction from hrd to lrd in these graphs is 8 to 1 . let it be assumed that the analog signal being processed by the digitizer is at a transition level , where the hrd is continuously switching between the digital values 7 and 8 , due to a small electrical noise in the signal . therefore in the case of the mapping process with no hysteresis , as shown in fig3 a , the lrd will be continuously shifting between the digital values of zero and 1 , as represented by the arrows 36 and 38 , indicating movement in two opposite directions . similar shifting movements are indicated between the lrd levels of 1 and 2 by the arrows 40 and 42 when the hrd is shifting between the levels of 15 and 16 ; between the levels 2 and 3 by the arrows 44 and 46 when the hrd is shifting between the levels 23 and 24 ; and between the levels 3 and 4 by the arrows 48 and 50 when the hrd is shifting between the levels 31 and 32 . when hysteresis is employed in the mapping process , as illustrated in fig3 b , no such shifting back and forth takes place . the hysteresis loop 61 is shown in fig3 b as having a width of 4 hrd units , represented by the distance between a first vertical line 52 and a second vertical line 54 extending between lrd values of zero and 1 . the transitions in the lrd are direction dependent . thus the line 52 at hrd - 6 represents a downward movement as shown by the arrow 56 thereon , representing a return from the one lrd level to the zero level , while the line 54 at hrd - 10 represents an upward movement as shown by the arrow 58 thereon , representing a movement from the zero lrd level to the one level . the horizontal line 60 between the lines 52 and 54 represents a shifting of hrd points between 10 and 6 . in contrast to the digitizer without hysteresis , the lrd value will be at zero for both values of hrd - 7 and hrd - 8 . in fact as long as the amount of hysteresis in the hysteresis loop 61 is greater than the noise level , the output will stay the same for a fixed input . it will be noted that two threshold values th1 and th2 are graphically represented in fig3 b , and are used in the mapping process , as will subsequently be described . the threshold value th1 represented by line 62 is selected to have a value which is half of the width of the hysteresis loop , or 2 in the illustrated example . the threshold value th2 represented by line 64 is selected to have a value which equals the scale of reduction minus the value of th1 , or 8 minus 2 equals 6 , in the illustrated example . it will be noted that other means of determining the threshold values could be selected , if desired , in accordance with the particular requirements of the mapping process used . it should be noted that the hysteresis approach does not eliminate the signal noise , but instead suppresses it . therefore the uncertainty in the hrd due to noise is no longer magnified when the data is downscaled to the lower resolution of the display 24 . the hysteresis effect can be implemented in firmware or software in association with the data processor 30 using a routine such as is illustrated in fig4 . this routine commences with the start block 70 , and is actually initiated when the stylus 26 is operated on the digitizer 22 , as represented in block 72 . the resulting positional data is digitized , as represented in block 74 . the scale factor between the hrd and the lrd , which is fixed for a particular system , is determined , as represented in block 76 . next , the high resolution data hrd is divided by the scale factor s to provide a quotient q and remainder r , as represented in block 78 . fixed values are provided for the two thresholds th1 and th2 , as represented in block 80 . a comparison is now made to determine whether the remainder r is less than the threshold value th1 , as represented by decision block 82 . if so , a further comparison is made , as represented by block 84 , to determine whether a previous value of lower resolution data plrd is less than the quotient q . if so , the lower resolution data value is set equal to q - 1 ( block 86 ). the previous lower resolution data plrd is then set equal to the lower resolution value lrd ( block 88 ), and the process returns over path 90 to block 72 for further operation of the stylus . returning to block 84 , if plrd is not less than q , the process continues to block 92 , in which lrd is set equal to q . the process then continues to block 88 and over path 90 back to block 72 , as previously described . returning to block 82 , if the remainder r is not less than the threshold value th1 , the process continues to block 94 , where a determination is made as to whether the remainder r is greater than the threshold value th2 . if not , the process continues to the previously described block 92 , and further continues through block 88 and return path 90 back to block 72 . on the other hand , if r is greater than th2 in block 94 , the process continues to decision block 96 , in which a determination is made as to whether plrd is greater than q . if not the process continues via the previously described blocks 92 and 88 , and over return path 90 to block 72 . if plrd is greater than q , the process continues to block 98 , in which lrd is set equal to q + 1 . from there , the process continues via block 88 and return path 90 back to block 72 . in order to illustrate the process described above , let it be assumed that the scale of reduction equals 8 , the width of the hysteresis loop equals 4 , plrd equals 1 and hrd equals 7 . then q equals zero , r equals 7 . th1 equals 2 and th2 equals 6 . starting with block 82 , r is not less than th1 , so the process continues to block 94 . since r ( 7 ) is greater than th2 ( 6 ), the process goes to block 96 . since plrd ( 1 ) is greater than q ( zero ), lrd is set equal to q + 1 , or 1 , as per block 98 . plrd remains at a value of one , and the process returns to block 72 . if plrd is equal to zero , the process is the same as described above up to block 96 . since plrd ( zero ) is not greater than q ( zero ), the process goes to block 92 , in which lrd is set equal to q and is thus equal to zero . this illustrates the directional and hysteresis aspect of the algorithm of fig4 in which the value of lrd is not increased to a new level until the high resolution data has actually reached an upper threshold level corresponding to the next higher level of lrd , but in which , when lrd is at a given level , it is not reduced to the next lower level even though the hrd drops slightly below the upper threshold of the lrd . in general , if the hrd falls outside the upper and lower thresholds of the hysteresis loop , then lrd equals q . in the cases in which hrd is within the hysteresis loop , the value of lrd depends on the direction of the data . if the data is increasing , then lrd equals q - 1 when r is less than th1 , and lrd equals q when r is greater than th2 . for decreasing data , lrd equals q if r is less than th1 , and lrd equals q plus 1 if r is greater than th2 . the previous low resolution data plrd is checked against q to determine the direction of the data . while the form of the invention shown and described herein is admirably adapted to fulfill the objects primarily stated , it is to be understood that it is not intended to confine the invention to the form or embodiment disclosed herein , for it is susceptible of embodiment in various other forms within the scope of the appended claims .