the following discussion is directed to various embodiments of the invention . although one or more of these embodiments may be preferred , the embodiments disclosed should not be interpreted or otherwise used as limiting the scope of the disclosure , including the claims . in addition , one skilled in the art will understand that the following description has broad application , and the discussion of any embodiment is meant only to be exemplary , and is not intended to intimate that the scope of the disclosure , including the claims , is limited to these embodiments . fig1 illustrates an exemplary computer system 100 . the computer system of fig1 includes a central processing unit (“ cpu ”) 102 that may be electrically coupled to a bridge logic device 106 via a cpu bus . the bridge logic device 106 is sometimes referred to as a “ north bridge .” the north bridge 106 electrically couples to a main memory array 104 by a memory bus , and may further electrically couple to a graphics controller 108 via an advanced graphics processor (“ agp ”) bus . note that the main memory array 104 may include magnetic memory array utilizing the methods for determining memory element values disclosed below . the north bridge 106 may couple cpu 102 , memory 104 , and graphics controller 108 to the other peripheral devices in the system through , for example , a primary expansion bus (“ bus a ”) such as a pci bus or an eisa bus . various components that operate using the bus protocol of bus a may reside on this bus , such as an audio device 110 , an ieee 1394 interface device 112 , and a network interface card (“ nic ”) 114 . these components may be integrated onto the motherboard , as suggested by fig1 , or they may be plugged into expansion slots 118 that are connected to bus a . if other secondary expansion buses are provided in the computer system , another bridge logic device 119 may be used to electrically couple the primary expansion bus , bus a , to a secondary expansion bus (“ bus b ”). this bridge logic 119 is sometimes referred to as a “ south bridge .” fig2 a shows a schematic representation of magnetic memory array 210 , which may be implemented in memory array 104 . memory array 210 may include magnetic memory elements 212 . memory elements 212 may be arranged in an array of columns c 0 – c n − 1 and rows r 0 – r n − 1 . individual memory elements may be depicted as resistive elements interconnecting rows and columns as shown . for example , memory element “ 0 . 0 ” would represent the memory element that is located at the intersection of row r 0 and column c 0 . note that the magnetic memory elements may be modeled using a variety of devices such as capacitors , resistors , inductors , tunnel junctions in series with diodes , or other combinations of integrated circuit elements . accompanying circuitry 220 a – d may write data to and read data from the memory elements 212 . digital values may be written in memory array 210 by setting the resistance of the memory elements 212 , where various resistive values may be assigned to various digital values . for example , memory element 0 . 0 may contain a resistance of 1 mω for a digital ‘ 1 ’ or 1 . 1 mω for a digital ‘ 0 ’, although the resistances may vary as desired . in addition , each memory element may be capable of being set to several distinct resistive values so that there may be n distinct data values represented by each memory element for n distinct resistive states . for example , memory element 0 . 0 may be set to four distinct resistive values , such as 1 . 0 mω , 1 . 1 mω , 1 . 2 mω , and 1 . 3 mω , so that memory element 0 . 0 may be able to represent four distinct digital values — e . g ., 00 , 01 , 10 , and 11 , respectively . in order to determine the digital value contained in a memory element , voltage sources may be coupled to the rows r and columns c of memory array 210 , as shown in fig2 b . coupling voltage sources to the array as shown offers the ability to isolate desired memory elements from undesired memory elements , while also allowing the digital value of the desired memory element to be determined . for example , memory element 0 . 0 may be isolated and read by coupling voltage source v y to columns c 0 – c n - 1 , voltage source v x to rows r 1 – r n − 1 , and ground to row r 0 as shown . a voltage equivalent to voltage source v y may be provided to column c 0 by read circuitry 222 . if v y and v x are equal , then memory elements 1 . 0 through n − 1 . 0 may be isolated from memory element 0 . 0 , which may have v y across it . with memory element 0 . 0 isolated from the other memory elements in the same column , the current supplied to column c 0 may represent the resistance of memory element 0 . 0 , so that the digital value of memory element 0 . 0 may be determined by measuring the current in column c 0 . in addition to providing voltage source v y to column c 0 , read circuitry 222 may be used to measure the current supplied to column c 0 . however , v y and v x may not be equal to each other and therefore the current supplied to column c 0 may also represent current in undesired memory elements , such as memory elements 1 . 0 through n − 1 . 0 . fig3 shows an exemplary implementation of read circuitry 222 coupled to one or more memory elements 223 . circuitry 222 may be included in accompanying circuitry 220 a – d ( fig2 a and 2b ). referring to fig3 , memory elements 223 may include a desired memory element ( i . e ., a memory element that is to be measured ), as well as other undesired memory elements ( i . e ., memory elements that may impact the measurement of the desired memory element ). the desired memory elements may be represented by resistance r mem , while the undesired memory elements may be represented by resistance r leak . a gain stage 224 may have its negative input coupled to the memory elements 223 , its positive input coupled to a predetermined voltage v y , and its output coupled to a controller 226 , where the controller 226 forms a negative feedback loop . controller 226 may be used to vary the amount of current in the feedback loop , where gain stage 224 may determine the amount of current that controller 226 shall provide . the undesired memory elements r leak may have one terminal coupled to the negative terminal of gain stage 224 , which may be at a voltage potential v x ′ as indicated in fig3 , and its other terminal coupled to voltage source v x . the desired memory element may have one terminal coupled to the negative terminal of gain stage 224 and the other terminal coupled to a switch 230 . the gain stage 224 may attempt to maintain equal potentials at its positive and negative input nodes — i . e ., v y equal to v x ′. the switch 230 may couple the desired memory element r mem to ground or may couple the desired memory element r mem to some other known state , such as voltage source v x or high a impedance state . a current source 228 may also be coupled between a voltage supply v s and the controller 226 . with the gain stage 224 configured in a negative feedback arrangement as shown in fig3 , a voltage of approximately equal to voltage source v x , indicated by v x ′, may be established at the negative input of the gain stage 224 . the voltages present at the input terminals may not be equal for various reasons including input offset errors of the gain stage 224 . in establishing v x ′ at the negative node of gain stage 224 , the controller 226 may moderate the current flowing from current source 228 . the controller 226 may be a metal oxide semiconductor transistor (“ mosfet ”). the amount of current necessary to establish v x ′ at the negative input terminal may be designated as i sense . under normal memory operation , the switch 230 may couple the desired memory element r mem to ground . if v x ′ and v y are equal to each other , the undesired memory elements r leak may conduct a minimal amount of current ( e . g ., 1 na ) and may therefore be isolated from the desired memory element r mem . in this manner , i sense may be primarily provided to r mem and may indicate the resistance and digital value of the desired memory element r mem . in some situations , it may be difficult to generate matching voltages for v y and v x ′. if , v x ′ and v y are not equal , then a portion of i sense may be provided to r leak , and consequently the digital value of the desired memory element r mem may be skewed by the undesired memory elements r leak . using switch 230 , the amount of skew introduced by the undesired memory elements r leak may be characterized and compensated for if necessary , so that i sense may be used to accurately determine the digital value of r mem . note that this compensation may be made prior to or after measurement of i sense . for example , gain stage 224 may have its offset voltage adjusted to compensate for skew prior to measuring i sense , or i sense may be measured and a correction factor may be added or subtracted from i sense to correct for the amount of skew . i sense may be measured at the junction between the current source 228 and the switch 226 , as indicated by i out . additionally , read circuitry 222 may include detection circuitry ( not specifically shown in fig3 ) that measures the difference in the magnitude of i sense with switch 230 in various conducting states . for example , when switch 230 couples the desired memory element r mem to ground , the magnitude of i sense may be 1 . 5 μa , with 1 μa flowing in r leak and 0 . 5 μa flowing in r mem — i . e ., r mem enabled . alternatively , when switch 230 couples the desired memory element r mem to v x , the magnitude of i sense may be 1 . 01 μa , with 1 μa flowing in r leak and 0 . 01 μa flowing in r mem — i . e ., r mem disabled . in this example , the detection circuitry may note a 0 . 49 μa difference between the two values of i sense . consequently , this difference may be compared to a predetermined difference amount , and then may represent the digital value of r mem . for example , a digital ‘ 1 ’ may be represented by a difference current measurement in the range of 0 . 45 μa to 0 . 60 μa , and therefore a 0 . 49 μa difference may indicate a digital ‘ 1 ’. in addition , read circuitry may monitor the current in the desired memory element and determine the derivative of the current while the desired memory element r mem is being switched . in this manner , the peak value of the derivative may indicate the digital value of r mem . in at least some embodiments , the current in the undesired memory elements r leak should be less than or equal to about five times the current in the desired memory elements r mem . fig4 illustrates a possible method for determining the digital value of a desired memory element r mem . a column of interest , which may contain the desired memory element r mem , may be selected from within the memory elements 212 by coupling a voltage v y to the appropriate columns of memory elements 212 as shown in block 500 . this may include coupling read circuitry 222 to the column of interest containing the desired memory element r mem , where , read circuitry 222 may provide the voltage v y to the column of interest . note that read circuitry 222 may measure the amount of current i sense provided to the column of interest in order to determine the digital value of the desired memory element r mem . a row of interest , which may contain the desired memory element r mem , may be isolated from other rows by coupling voltages v x ( and thereby generating v x ′), to the rows which do not contain the desired memory element r mem as shown in block 502 . because voltage v x ′ may not equal v y the undesired memory elements r leak may conduct current and the current i sense measured by the read circuitry 222 may not accurately reflect the digital value of the desired memory element r mem . switch 230 may disable the desired memory element r mem by coupling it to v x or to a high impedance state as shown in block 504 . with the desired memory element r mem coupled to voltage v x or to a high impedance state , the desired memory element r mem may be isolated so that amount of current in the undesired memory elements r leak may be characterized by measuring the current i sense as shown in block 506 . in block 508 , the amount of skew introduced by the undesired memory elements r leak may be compensated for by using various techniques — e . g ., adjusting the input offset voltage of gain stage 224 . as shown in fig3 , gain stage 224 may include an external control line for making the input offset adjustment . the desired memory element r mem may be enabled by coupling it to ground using switch 230 as shown in block 510 . with the desired memory element r mem enabled , read circuitry 222 may measure i sense as shown in block 512 . measuring the current i sense after the compensating for the current consumed by the undesired memory elements r leak may allow the digital value of the desired memory element r mem to be accurately determined . note that the above discussion and figures address the situation where v x ′ may be at a lower potential than v y , and therefore the current in the undesired memory elements r leak may flow from the negative terminal of gain stage 224 to voltage source v x . however , v x ′ may be at a higher potential than v y , and therefore the current in the undesired memory elements r leak may flow from v x to the negative terminal of gain stage 224 . accordingly , the methods , memory systems , and circuitry described above for compensating for the current in the undesired memory elements r leak may be used regardless of the direction of the current in the undesired memory elements r leak . the above discussion is meant to be illustrative of the principles and various embodiments of the present invention . numerous variations and modifications will become apparent to those skilled in the art once the above disclosure is fully appreciated . for example , the switch 230 may be implemented using a tri - state buffer . accordingly , aspects of the embodiments may be combined together in various forms to achieve desirable results . it is intended that the following claims be interpreted to embrace all such variations and modifications .