fig2 is a block diagram illustrating an embodiment of the present invention . the output compaction architecture 200 comprises a response shaper 210 which is inserted between the outputs of the scan chains 221 , 222 , . . . , 225 and the inputs of the output compactor 250 . the output compactor 250 advantageously need not be a sophisticated array of exclusive - or ( xor ) gates . in fact , the output compactor 250 can be implemented by any xor network - based compactor and even the most primitive xor tree . it is accepted that the output compactor 250 will allow some masking of faults to occur during compaction . the response shaper 210 , the operation and design of which is further described in detail herein , serves to “ reshape ” responses from the scan chains 221 , 222 , . . . , 225 in a manner that preferably minimizes the masking of faults by the output compactor 250 . fig3 through 5 illustrate the principles behind the reshaping of the scan chain responses . fig3 depicts a simple 4 - to - 1 output compactor implemented with xor gates 351 , 352 , 353 that can be used to observe four internal scan chains 321 , 322 , 323 , and 324 with one external scan chain output ( so ) 360 . assume that the four scan flip - flops ( depicted as rectangles ) s 1 , 1 , s 2 , 1 , s 3 , 1 , and s 4 , 1 in the scan chains currently hold the responses of the circuit to the previous test pattern . with reference to fig3 through 5 , the notation g / f , where g = f = 0 or 1 , inside each of the scan flip - flops denotes the good circuit and faulty circuit responses that are captured into the flip - flop . when the good circuit value of a flip - flop is opposite to its faulty circuit value , i . e ., 1 / 0 or 0 / 1 , then the flip - flop is said to capture an error . fig3 shows that flip - flops s 1 , 1 and s 3 , 1 , whose values are scanned out at the same cycles , have captured errors . values that are scanned out of each internal scan chain output will propagate through the output compactor network to the external scan chain output 360 which in turn is observed by automatic test equipment ( ate ). even though there are multiple scan flip - flops that captured errors , the good circuit value at the external scan chain output is equivalent to its faulty circuit value . the errors that are propagated to the two inputs of the second stage xor gate 353 are “ masked .” therefore , the defect that caused errors at s 1 , 1 and s 3 , 1 cannot be observed by the ate because the two errors cancel each other out when they pass through the xor network . fig4 shows another case where the error values are masked . again , a simple 4 - to - 1 output compactor is depicted with xor gates 451 , 452 , 453 that can be used to observe four internal scan chains 421 , 422 , 423 , and 424 with one external scan chain output 460 . if an error is scanned out with an unknown value at the same cycle , the error is masked and cannot be observed by the ate . in fig4 , the symbol “ u ” denotes an unknown value , i . e ., a value that can be either 0 or 1 . among the four flip - flops that are scanned out at the current shift cycle , only s 1 , 1 has an error value . however , since the good circuit value at s 2 , 1 is unknown , the error value at s 1 , 1 cannot be observed . unknown values can occur for several reasons : for example , the circuit can have flip - flops that are not scanned , the circuit can contain bus drivers whose control signals are not fully decoded , etc . normally , good circuit responses of a circuit are computed by conducting logic simulation for the circuit . limitations in simulation accuracy can also cause unknown values . fig5 illustrates how reshaping responses helps the simple output compactor depicted in fig3 and 4 detect defects . assume that scan chains 521 , 522 , 523 , 524 of a circuit capture responses as shown in fig5 a . fig5 a shows that flip - flops s 1 , 1 , s 1 , 3 , and s 3 , 3 hold errors . if the simple output compactor depicted in fig3 and 4 is used to compress output responses , then all errors are masked and no defect can be observed at the output of the output compactor . the error in s 1 , 1 is scanned out with the unknown value in s 2 , 1 and the two errors in s 1 , 3 , and s 3 , 3 are scanned at the same shift cycles . assume that a flip - flop , which is initialized to 1 / 1 before the scan shift operation starts , is inserted between s 1 , 1 and the corresponding input to the compactor to delay the first scan chain 521 by one clock cycle , as depicted in fig5 b . that is , responses captured in the scan chain 521 are “ reshaped ” by the inserted flip - flop . in fig5 b , no error value is scanned out with another error or unknown value at any shift cycle and all errors can be observed at the output of the compactor . the simple shape compactor can thereby detect defects when even number errors are scanned out and / or errors are scanned out along with unknown values at the same shift cycle . fig6 shows an implementation of a response shaper 610 for a circuit with four scan chains 621 , 622 , 623 , 624 . in accordance with an embodiment of the invention , the response shaper 610 is comprised of delay elements 615 , 616 , 617 , 618 , multiplexers 611 , 612 , 613 , 614 , and a 2 - to - 4 decoder 619 . each delay element and multiplexer is inserted between each scan chain output and the corresponding input of the output compactor 650 . the 2 - to - 4 decoder 619 generates signals that select a scan chain output that will be delayed . for example , if the input of the decoder is set to i , where i = 1 , 2 , 3 , or 4 , then responses that are scanned out of chain i are delayed before they are input to the compactor and responses from the other scan chains are input to the compactor without any delay . it should be noted that delay elements that can delay the selected scan chain by more than one cycle can be readily used , in the situation where it is anticipated that no error can be observed at the output of the compactor 650 by delaying only one shift cycle ( for example , where an error appears with an unknown value and another unknown value appears at the next cycle ). fig7 depicts an alternative embodiment which does not utilize delay elements to reshape responses of selected scan chains . the function of this response shaper 710 is similar to that of the response shaper illustrated in fig6 . again , the response shaper 710 is inserted between four scan chains 721 , 722 , 723 , 724 and the output compactor 750 . however , unlike the response shaper shown in fig6 which delays responses of the selected scan chain , responses of the selected scan chain in fig7 will be input to the compactor earlier than the other scan chains , for example by one cycle . the response shaper 710 comprises a 2 - to - 4 decoder 719 that generates signals to four multiplexers 711 , 712 , 713 , 714 which can selectively advance responses from one of the scan chains 721 , 722 , 723 , 724 . since delay elements are not used , this approach can reduce hardware overhead to implement the response shaper . fig8 shows an example of how the two different schemes can also be combined together to both delay and advance responses of selected scan chains . an extra multiplexer is provided with each element of the response shaper 810 that is inserted between each scan chain output and each corresponding input of the output compactor 850 . the extra multiplexer is responsive to a control signal that can select whether to delay or advance a scan chain in a shift cycle while the decoder 819 is still used to identify which of the scan chains 821 , 822 , 823 , 824 will be delayed or advanced . if the circuit into which the response shaper is inserted has a large number of scan chains , then the hardware overhead of the above embodiments can be reduced by selectively inserting the response shaper elements into the output compaction scheme , as illustrated by fig9 . in fig9 , the delay elements and multiplexers from the above - described response shaper embodiment are only inserted for selected scan chains to reduce hardware overhead . although the circuit has four scan chains 921 , 922 , 923 , 924 , the response shaper 910 only inserts delay elements and multiplexers for two scan chains 921 , 923 , as depicted in fig9 . fig1 is a flowchart of processing performed to generate the control signals for the above - described response shaper , in accordance with an illustrative embodiment of the invention . at step 1001 , a fault simulation is run with the pre - computed test patterns from a first test pattern p 1 to a last test pattern p n , where n is the number of pre - computed test patterns . at step 1002 , an identification is made of faults f i newly detected by each test pattern p i , where i = 1 , 2 , . . . n . this is conducted under the assumption that all scan chains are directly observed without an output compactor . at step 1003 , the masked faults for each test pattern are identified , namely those faults which can be observed without the use of an output compactor but cannot be observed if the scan chains are observed via the output compactor . these masked faults are placed into a masked fault list f mask . at step 1004 , responses are computed to each test pattern . from the last test pattern p n toward the first test pattern p 1 , responses are computed to each test pattern , r i , where i = 1 , 2 , . . . n , and the values captured in each scan flip - flop . if there is any fault in f i that is masked when the scan chains are observed via the output compactor , then search is conducted for a scan chain that allows all faults to be detected when it is delayed ( or advanced depending on the embodiment discussed above ). if there is more than one such scan chain , then a decision can be made to select the scan chain that can detect the most faults in the masked fault list f mask . as a fault is determined to be detectable by a reshaped scan chain , the fault is dropped from the fault list : an identification is made of all faults from the entire fault list that are detected when the selected scan chain is delayed ( or advanced ) and the detected faults are removed from fault list f i for every test pattern p i , where i = 1 , 2 , . . . n , and also from the masked fault list f mask . at step 1005 , the input signals for the decoder of the response shaper are generated for each test pattern using the information obtained in step 1004 . in the foregoing , if it is assumed that the response shaper will delay and / or advance only a single scan chain for entire shift cycles to scan out a response completely , then there is a need for only one set of decoder control signals for each test pattern . this advantageously minimizes the test data volume that is to be stored to control the response shaper . if , however , there are test patterns having detected faults that cannot be detected by delaying or advancing any scan chain , then it should be noted that it is possible to switch scan chains that are reshaped in the middle of scan shift operation for the response . thus , multiple sets of control signals would be generated for those test patterns . although this may increase test data volume , it could advantageously achieve the same fault coverage that can be achieved when scan chains are directly observed without the use of any output compactor — even in the presence of a large number of unknown values . while exemplary drawings and specific embodiments of the present invention have been described and illustrated , it is to be understood that that the scope of the present invention is not to be limited to the particular embodiments discussed . thus , the embodiments shall be regarded as illustrative rather than restrictive , and it should be understood that variations may be made in those embodiments by workers skilled in the arts without departing from the scope of the present invention as set forth in the claims that follow and their structural and functional equivalents . as but one of many variations , it should be understood that the response shaper described herein can be utilized with a wide variety of output compaction schemes .