reference will now be made in detail to some embodiments of the invention , examples of which are illustrated in the accompanying drawings . although embodiments of the invention are discussed below with reference to the figures , those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes as the invention extends beyond these limited embodiments . for example , it should be appreciated that those skilled in the art will , in light of the teachings of the present invention , recognize a multiplicity of alternate and suitable approaches , depending upon the needs of the particular application , to implement the functionality of any given detail described herein , beyond the particular implementation choices in the following embodiments described and shown . that is , there are numerous modifications and variations of the invention that are too numerous to be listed but that all fit within the scope of the invention . also , singular words should be read as plural and vice versa and masculine as feminine and vice versa , where appropriate , and alternatives embodiments do not necessarily imply that the two are mutually exclusive . an aspect of the present invention is to provide a relatively low - cost and effective control methodology capable of regulating the output voltage of a flyback converter from the primary side with reasonably good accuracy from 0 % to 100 % of its rated load in at least some applications . in this way , the secondary side control circuit and the optical coupler may be eliminated , thereby reducing costs and improving reliability at least due to a lower component count . as mentioned above , at least two factors can account for errors in the voltage regulation of a primary side controlled flyback converter circuit . such factors include : 1 ) the transformer copper loss varies with output current and input voltage , and 2 ) the voltage sensing of the dcm operation is not accurate . to address the first factor , a current source that provides a current at a level derived from the primary switch current is used to compensate for the variations . to address the second factor , an adaptive sampling and hold circuit is used to capture the feedback voltage when the current of the secondary winding of the transformer discharges to zero . based on this control methodology , two associated pwm controller ic chip embodiments will be described in some detail below . fig3 shows , in accordance with an embodiment of the present invention , a schematic diagram of an exemplary primary side controlled constant - output - voltage flyback converter circuit implementing a first embodiment of pwm controller ic chip 204 in accordance with an aspect of the present invention . the exemplary circuit shown in fig3 comprises a transformer 201 that has three windings ( primary with n p turns , secondary with n s turns and auxiliary with n a turns ), a secondary side resistor 301 ( which represents the copper loss of transformer 201 ), a secondary rectifier 302 , an output capacitor 303 , and a peak current mode pwm control in pwm controller ic 204 . resistor 101 and capacitor 102 provide the initial start - up energy for pwm controller ic 204 . once the flyback converter is stable , pwm controller ic 204 is powered by the auxiliary winding of transformer 201 via rectifier 103 . the output voltage is fed back to the fb input pin of pwm controller ic chip 204 via the auxiliary winding and voltage divider resistors 108 and 109 . those skilled in the art , in light of the teachings of the present invention , will readily recognize that the feedback for the fb input pin may come from any other suitable source beyond the auxiliary winding of the transformer , for example , from the primary winding . in alternate embodiments of the present invention ( not shown ), the transformer does not have any auxiliary windings and only has a primary and secondary winding . those skilled in the art will recognize a multiplicity of alternate and suitable transformer types and interface circuit configurations to be operable with connection to the fb input pin . pwm controller ic 204 is optionally capable of self - starting from the input line through a combination of a relatively large time constant charging resistor 101 and an energy storage capacitor 102 . fig4 is an exemplary block diagram of a first embodiment of pwm controller ic chip 204 . the first embodiment of pwm controller ic comprises an internal power mosfet as the main switch and a current sense mosfet . hence , no external mosfet or current sense resistor is needed for relatively low power applications . as illustrated in fig4 , a vcc supply 401 provides an internal power supply and reference voltage . the feedback voltage v fb is amplified by a buffer 402 and then sampled and held by a sample - and - hold circuit 403 . in the preferred embodiment of the present invention , the feedback voltage is sampled and held at the point that v fb has the minimum variation with respect to time . at this point , the output diode 302 generally has a minimum voltage and its temperature effect is typically the smallest . in applications that do not require such buffering , this buffer stage may be removed in alternate embodiments ( not shown ). an error amplifier 404 then compares the feedback voltage with a reference voltage ( v ref ). a resistor 408 and a capacitor 409 form a compensation network for error amplifier 404 . a comparator 411 serves as a peak current mode pwm comparator with a slope compensation input . in other embodiments of the present invention ( not shown ), the comparator may be configured by those skilled in the art to compare any suitable ramp signals depending upon the needs of the particular application . a system oscillator 410 provides a frequency jittering function that widens the frequency spectrum and achieves a lower conducting emi emission . the jittering function is preferably implemented as a digital jitter circuit that is configured to achieve more overall voltage regulation precision and is largely insensitive to temperature variations and other parasitic components . an example of a preferred frequency jittering circuit is described in connection with fig1 . alternate embodiments of the present invention may not include the frequency jittering function in system oscillator 410 and / or slope compensation . in many applications , slope compensation and the system oscillator jitter function can improve converter operation in certain input / output operating conditions . however , these functions are completely optional , whereby alternate embodiments of the present invention may not include either one or both . a pwm control unit 412 then generates the correct pwm waveform by utilizing a cycle - by - cycle current limiting function . a mosfet 413 is a high speed mosfet gate driver . a power mosfet 415 serves as the main switch , while a mosfet 414 and a resistor 416 form a current sense circuit . as will be readily apparent to the system designer , some applications may not require resistor 416 to generate the current sensing voltage feedback or it may be located in other circuit configurations , or embedded into other system components . as will be readily recognized by those skilled in the art , depending upon the needs of the particular application and available technology , the power mosfet may be formed in any suitable manner ; by way of example , and not limitation , the power mosfet may be comprised of a multiplicity of smaller mosfet devices to form a single power mosfet . a timing generator 405 senses the negative going - edge of v fb waveform and produces triggering signals for sample - and - hold circuits 403 and 406 . a voltage controlled current source 407 then programs the current source to output a current having a level of β · i p according to equation ( 2 ) described below , and is useful in many applications to make the feedback voltage largely independent of transformer copper loss . this is achieved by inserting a shunt current source ( not shown in fig3 ) at the mid - point of the feedback voltage divider resistors 108 and 109 . the shunt current source is preferably programmed to provide a current proportional to the current of the primary switch ( shown as current i p in fig3 ). the calculation of the resistance of upper resistor 108 of the feedback voltage divider follows equation ( 5 ) below . those skilled in the art will recognize a multiplicity of alternate and suitable means for achieving the same function as voltage controlled current source 407 instead of that shown . sample - and - hold circuit 403 samples the buffered feedback voltage and sample - and - hold circuit 406 samples the current of the primary switch . in the present embodiment , the primary current i p flows through mosfet 414 and power mosfet 415 , and the portion of i p flowing through mosfet 414 is inversely proportional to the on resistance of mosfet 414 and power mosfet 415 . resistor 416 produces a voltage that is also proportional to the primary current i p . sample - and - hold circuit 406 then senses the voltage across resistor 416 , whereby the output voltage of the sample - and - hold circuit 406 controls the output current of voltage controlled current source 407 . in this way , the combination of 406 and 407 work to carry out equation ( 2 ) below . it should be appreciated that in contrast to conventional approaches that only work in dcm , the present embodiment implements a method for using “ sampled auxiliary flyback voltage ” to control the primary current . sampling the auxiliary flyback voltage at a known time point provides a more accurate representation of the actual output voltage in most applications . the present embodiment is largely independent of auxiliary voltage and / or current variations by , for example , basing output current control based only on primary current sensing and the ratio of t_r / t_on , which works in both dcm and ccm . hence , embodiments of the present invention preferably do not use auxiliary voltage to control primary current by essentially scaling the peak current ( i peak ) as proportional to the square root of the output voltage , as is done in conventional approaches . fig5 illustrates exemplary ideal waveforms of the auxiliary winding voltage , primary switch current and secondary rectifier current of the flyback converter of fig3 operating in continuous current mode ( ccm ). with reference to both fig4 and 5 , main switch 415 turns on at t 1 , turns off at t 2 and turns on again at t 3 . the switching period is t , the turn - on time is ton and the turn - off time is t r . the voltage at the auxiliary winding ( v a ) at the time just before t 3 can be expressed as , v a =( n a / n s )·( v o + v d1 + i s · r s ) ( 1 ) we may then assume that shunt current i 407 of current source 407 , as shown in fig4 , is programmed by , the output voltage sense v fb can be expressed by , v fb =( r 2 /( r 1 + r 2 ))·( n a / n s ·( v o + v d1 + i s · r s )−( r 1 · r 2 )/( r 1 + r 2 ))· β i s ·( n s / n p ), ( 4 ) where resistors 108 and 109 are referenced as r 1 and r 2 , respectively . r 1 =( n p · n a · r s )/( β · n s · n s ) ( 5 ) v fb =( r 2 /( r 1 + r 2 ))·( n a / n s )·( v o + v d1 ) ( 6 ) therefore , if the shunt current i 407 of voltage controlled current source 407 is programmed per equation ( 2 ) and the value of r 1 is chosen by equation ( 5 ), then output voltage sense v fb is practically independent of the copper loss ( i s · r s ) of transformer 201 . it should also be noted that , for ccm operation , v fb is preferably sampled and held at the time just before t 3 , as it is optimal to sense the feedback voltage at the time just before the primary winding turns on for ccm and at the time when the current of the secondary winding of the transformer discharges to zero . fig6 illustrates exemplary ideal waveforms of the auxiliary winding voltage , primary switch current and secondary rectifier current of the flyback converter of fig3 operating in discontinuous current mode ( dcm ). with reference to both fig4 and 6 , main switch 415 turns on at t 1 , turns off at t 2 and turns on again at t 4 . the switching period is t , the turn - on time is ton and the turn - off time is equal to ( t 4 − t 2 ). t r is equal to ( t 3 − t 2 ). as shown in fig6 , the current at the secondary winding of transformer 201 discharges to zero at t 3 . the voltage v a at the auxiliary winding between times t 3 and t 4 oscillates at a frequency determined by the parasitic inductance and capacitance of the circuit . in this case , v fb is preferably sampled and held at the time just before t 3 to achieve a more accurate feedback voltage . fig7 is an exemplary schematic diagram of a primary side controlled constant - output - voltage flyback converter circuit implementing the first embodiment of pwm controller ic chip 204 in an emitter switching configuration according to an embodiment of the present invention . as mentioned above , for low - power applications , no external power mosfet or current sense circuit is needed . as shown in fig7 , the first embodiment of pwm controller ic chip 204 is configured to drive an npn bipolar transistor in an emitter switching configuration to boost output power for higher power applications . in such a configuration , with reference to both fig4 and 7 , internal mosfet 415 drives the emitter of external npn transistor 705 , which serves as the main switch . to achieve further power handling capability and / or switching frequency , an external mosfet must typically be used as the main switch as shown in fig9 . fig8 illustrates an exemplary block diagram of a pwm controller ic chip 804 , in accordance with a second embodiment of the present invention . pwm controller ic chip 804 does not include internal power mosfet 415 , current sensing mosfet 414 and current sensing resistor 416 from the first pwm controller ic chip embodiment of fig4 . in this second embodiment , the current driving capability of gate drive 413 results in improved control for larger mosfets . in this second embodiment , gate drive 413 is designed with appropriate current driving capability suitable for controlling larger mosfets . fig9 is an exemplary schematic diagram of a primary side controlled constant - output - voltage flyback converter circuit implementing pwm controller chip 804 with an external mosfet and current sensing resistor , in accordance with an embodiment of the present invention . the functional blocks shown in the prior embodiments may be implemented in accordance with known techniques as will be readily apparent to those skilled in the art . however , some embodiments of the present invention include implementation approaches that are not conventional . for example , without limitation , the foregoing jitter functional block may be implemented as follows . fig1 illustrates a schematic diagram of an exemplary system oscillator 410 having a digital frequency jittering circuit that is suitable to implement the foregoing jitter functional block , in accordance with an embodiment of the present invention . the frequency jittering in the present embodiment is implemented by a digital control scheme , which departs from known approaches . an oscillator 817 is preferably a current controlled oscillator . there is preferably an uncontrolled , base - line , current source 801 , which , in one aspect , is present to set a minimum oscillator frequency , f min , that the switched current sources will jitter from . in the embodiment shown , the current to oscillator 817 is controlled by a multiplicity of switched current sources 802 - 804 that carry out the jittering of the oscillator &# 39 ; s minimum frequency . the frequency of the system oscillator output signal is generally proportional to the total current entering into oscillator 817 . in alternate embodiments , any number of current sources may be implemented depending upon the needs of the particular application . the jitter behavior is generated by feeding back a pseudo random digital signal to a multiplicity of series connected flip - flops ( e . g ., 818 to 823 ). current sources 801 , 802 , 803 and 804 are presently preferred to be currents of magnitudes 100 μa , 2 . 5 μa , 5 μa and 10 μa , respectively . each switched current source is presently configured with four current control switches ( e . g ., control switches 805 , 806 , 811 and 812 for switched current source 802 ) that are arranged in two parallel legs with each leg having two switches in series . in this way , for current to flow into oscillator 817 at least one leg must have both of its switches turned on . in similar fashion , four switches ( 807 , 808 , 813 and 814 ) are connected to switched current source 803 and another four switches ( 809 , 810 , 815 and 816 ) are connected to switched current source 804 . all of these switches are closed or open by a control input from an output from the series connected flip - flop chain . in the example shown , the switch 805 is open when q 5 is at logic level “ 1 ” and is closed when q 5 is at logic level “ 0 ”. similarly , the switch 806 is open when q 5 is at logic level “ 0 ” and is closed when q 5 is at logic level “ 1 ”, and so on . when all the switched current sources are enabled , a maximum frequency , f max , of the system oscillator output signal is achieved . as will be readily apparent to those skilled in the art , in light of the present teachings , the choice of which flip - flop outputs connect to which current control switch will determine a certain jittering pattern . an aspect of this digital frequency jittering scheme is that the period and the step of frequency variation may be relatively precisely controlled , and is largely insensitive to temperature variations . it should be appreciated that in contrast to conventional analog techniques for jittering the oscillator frequency , the digital jittering approach of the present embodiment always provides a digitally calculated frequency step irrespective of the known shortcomings that analog based techniques suffer from , such as temperature , input , output age dependences , etc . those skilled in the art , in light of the present teachings , will readily recognize a multiplicity of alternate and suitable implementations that implement the spirit of the present embodiment . by way of example , and not limitation , current based operation may be replaced with a voltage based approach , and the number and topology of the switches and / or current sources and / or flip - flop chain may be altered as needed for the particular application , and other suitable means to selectively control the pattern of current flowing into the current controlled oscillator . fig1 illustrates an exemplary jitter frequency control logic diagram for the exemplary digital frequency jittering circuit of fig1 , in accordance with an embodiment of the present invention . in the example shown , frequency variation from its maximum ( f max ) to minimum ( f min ) corresponding to the logic states “ 0 ” or “ 1 ” of q 2 , q 3 , q 4 and q 5 . having fully described at least one embodiment of the present invention , other equivalent or alternative techniques for a primary side constant output voltage controller according to the present invention will be apparent to those skilled in the art . the invention has been described above by way of illustration , and the specific embodiments disclosed are not intended to limit the invention to the particular forms disclosed . accordingly , various modifications , adaptations , and combinations of various features of the described embodiments can be practiced without departing from the scope of the invention as set forth in the claims .