referring first to fig1 which illustrates the circuitry upon which the invention improves , the translation circuit takes an input signal which transitions between 0 volts and a voltage vdd 1 , which is typically in the range of 1 . 8 volts to 2 . 5 volts , and converts that to an output voltage which transitions between 0 volts and a higher voltage in the range of 3 . 1 to 3 . 5 volts ( vdd 2 ). the purpose of the circuit is to provide a voltage level transition without requiring any standby current . in the illustrated circuit , the input data , which swings between 0 and 1 . 8 - 2 . 5 volts is applied to the input of an inverter circuit 101 which includes a p - channel mos transistor 115 and an n - channel mos transistor 117 connected in series and having their gates tied to the input terminal 102 . as the input voltage swings from 0 to vdd 1 , the applied signal crosses the threshold voltage ( vt ) of n - channel mos transistor 103 , which has its gate also connected to the input terminal 102 . when the input data signal exceeds the threshold voltage vt of transistor 103 it turns on and pulls down node d to ground which turns on p - channel mos transistor 105 which pulls up node c , that is , node c goes to the high voltage vdd 2 . when node c goes to the high voltage vdd 2 , that voltage is applied to inverter 113 , formed by p - channel mos transistor 119 and n - channel mos transistor 121 , which inverts the signal and produces a low voltage ( e . g . ground ) output at output node e . mos transistors 105 and 109 are cross - connected and form a bi - stable circuit . the operation of the fig1 circuit as just described was for an input signal transition from low to high voltage . on the high to low transition of the input signal at terminal 102 there will be a threshold at which the node b of inverter 101 will be pulled high ( vdd 1 ) due to mos transistor 115 turning on and mos transistor 117 turning off . as soon as node b goes high , n - channel mos transistor 107 will begin to conduct and pull node c down to ground voltage . in addition , n - channel mos transistor 103 which had been pulling down the gate of mos transistor 105 will also be turned off . as a consequence of mos transistor 107 turning on and mos transistor 103 turning off , the node c voltage is at ground which is in turn applied to inverter 113 which supplies an output at a voltage level vdd 2 to output node e . p - channel mos transistor 109 is used to pull node d high when mos transistor 103 turns off and mos transistor 107 turns on . this shuts off mos transistor 105 so there is no standby current flowing through the transistor path of mos transistors 105 and 107 . inverter 111 inverts the signal at node d and provides a complementary output at node f to the signal at node e . inverter 111 also provides loading on node d so that the timing of operation for the transitions experienced by nodes c and d will be essentially the same . the circuitry of fig1 performs well when the input voltage at terminal 102 swings from 0 volts into a range of 1 . 8 to 2 . 5 volts ( vdd 1 ). if a lower input voltage range is encountered , however , for example , if the input signal to the fig1 circuit swings between 0 and less than 1 . 5 volts , e . g . 1 . 4 volts , then node b only transitions between 0 and 1 . 4 volts which does not provide sufficient gate voltage for mos transistor 107 . in a typical fabrication , mos transistor 107 is sized much smaller than mos transistor 103 in order to enable the fig1 circuit to operate with equal timing on low to high and high to low transitions . however , when mos transistor 107 is sized much smaller than mos transistor 103 and when the input voltage range is likewise low , mos transistor 107 cannot be properly driven and the circuity does not function correctly and with equal time for output node e transition from high to low and low to high . as noted earlier , this is illustrated by fig2 and 3 . fig4 illustrates modifications to fig1 in accordance with the present invention . to the extent that fig4 employs the same elements as described above with respect to fig1 they have been identified with like reference numbers . to the fig1 circuit , the invention adds a &# 34 ; low voltage &# 34 ; input control line 141 , a pair of n - channel mos transistors 143 and 145 connected in a series between node c and ground with the gate input to mos transistor 143 being connected to the low voltage line 141 and the gate to mos transistor 145 being connected to node b . in addition , an enable input terminal 147 is provided which is connected to the gate input of n - channel mos transistor 149 which , in turn , is connected between n - channel mos transistor 121 of inverter 113 and ground . the enable input terminal 147 is also connected to the gate of p - channel mos transistor 151 which has its source and drains connected between output terminal 123 ( node e ) and supply voltage vdd 2 . the manner in which the fig4 circuit works will now be described . it will be assumed that the fig4 circuit will be operating in a low voltage mode and hence , a control signal will go &# 34 ; high &# 34 ; on the &# 34 ; low voltage &# 34 ; input line 141 . this will turn on mos transistor 143 and allow mos transistor 145 to turn on and off and affect the voltage on node c as mos transistors 143 and 145 are connected in a series . mos transistor 143 provides additional drive for node c to compensate for the weak drive provided by mos transistor 107 . one end of mos transistor 143 is connected to node c , while the other end is connected to mos transistor 145 which has its other terminal connected to ground . with the circuit of fig4 as the data input at terminal 102 makes a transition from a high to a low state , and node b goes high , mos transistor 107 , and mos transistor 145 turn on and , node c is assuredly pulled down to zero volts ( ground ). accordingly , the timely transition from high to low on the output line 123 of node e , when operating with low voltages , is ensured . mos transistor 143 and its associated input on &# 34 ; low voltage &# 34 ; line 141 is provided so that the circuitry including mos transistor 145 is only activated when using the fig4 circuit in a low voltage mode . in other words , mos transistors 143 and 145 are not operated when the circuit is otherwise operating with an input voltage that swings from 0 to a range of 1 . 8 to 2 . 5 volts , as the &# 34 ; low voltage &# 34 ; line 141 is disabled . the &# 34 ; low voltage &# 34 ; input control line 141 may be selectively enabled by a breakable fuse connection 140 , by an open circuit but shortable antifuse , or by a bonded wire connection to thereby program the fig4 circuit to operate in the low voltage mode . in lieu of a programmable fuse or antifuse or bonded connection , line 141 can be automatically enabled by sensing the peak voltage at the data input terminal 102 by a peak voltage detector 211 , and when the peak voltage falls below a preset value e . g . 1 . 5 volts and is detected by threshold circuit 213 the &# 34 ; low voltage &# 34 ; line is enabled by a signal from the threshold circuit 213 . all other operations of the fig4 circuit are as described above with respect to fig1 and are not repeated herein . the fig4 circuit also provides a selective enable terminal 147 and enable terminals 148 , 150 . enable and enable terminals receive respective and complementary enable and enable control signals . when the enable terminal 147 is disabled by going &# 34 ; low &# 34 ; this prevents the output line 123 ( node e ) from providing a transitioning data output . this is particularly useful for a power down mode of operation . in order to provide the enable / disable function , an n - channel mos transistor 149 is provided in series between the inverter 113 and ground , which is switched on by the presence of a &# 34 ; high &# 34 ; enable signal on terminal 147 . when the enable signal at terminal 147 is &# 34 ; low &# 34 ;, mos transistor 149 is off and no matter what happens at node c , the inverter 113 will not operate and the output signal at terminal 123 ( node e ) will not switch . at the same time mos transistor 149 is turned off by a &# 34 ; low &# 34 ; signal at enable terminal 147 this same &# 34 ; low &# 34 ; signal is provided to p - channel mos transistor 151 which turns on to hold the output line 123 ( node e ) at the supply voltage vdd 2 . if the data output line 124 is used by downstream circuits , similar circuits are provided for disabling output line 124 , including p - channel mos transistor 155 which turns on in the presence of a &# 34 ; low &# 34 ; signal on enable terminal 150 and is turned off by a &# 34 ; high &# 34 ; input which disables inverter 111 . this same &# 34 ; high &# 34 ; input is applied , via terminal 148 to n - channel mos transistor 153 which turns on to hold output line 124 at ground potential . as a result , when output line 123 is held &# 34 ; high &# 34 ; by the lack of an enable signal at terminal 147 , output line 124 is held &# 34 ; low &# 34 ;. fig5 illustrates the output signals produced by the fig4 circuit when the input voltage to the inverter 101 transitions from high to low and low to high between 0 and 1 . 4 volts . as shown , the output voltage of the fig4 circuit ( vout ) is essentially symmetrical on both transitions , unlike the output voltage vout shown in fig3 . accordingly , the fig4 circuit has substantially improved signal transitions compared to the fig2 circuit when a lower input voltage range e . g . less than approximately 0 to 1 . 5 volts , is used . fig6 illustrates one environment in which the invention may be used . fig6 illustrates a logic system 301 containing a programmable logic unit 303 which supplies signals for control and / or storage to a memory device 305 . the logic unit 303 typically operates within a voltage range which is lower than the voltage range of operation of memory device 305 . accordingly , a voltage translator 307 constructed as described above with respect to fig4 provides the interface between the logic unit 303 and memory device 305 . the logic unit 303 may be a hardware or software programmable logic array or may be a processing unit such as a microprocessor . it provides the data input signals to the voltage translator 307 which provides output signals at the correct voltage level for memory device 305 . in addition , the voltage translator 307 may be separate from the memory device 305 or integrated as part of the memory device 305 . the logic unit 303 may also interface with other devices , such as input / output devices , e . g . display , keyboard , storage disc , etc . still further , the logic unit 303 , voltage translator 307 and memory device 305 can all be integrated on a single disc and housed in a single integrated circuit package . although the invention has been described and illustrated with respect to particular mos transistors i . e . p - channel and n - channel mos transistors , it should be apparent to one of ordinary sill in the art that a complementary circuit can be constructed . in addition , other types of transistors may also be used in order to obtain the same or similar results . these and other modifications can be easily made without departing from the spirit and scope of the invention . accordingly , the invention is not to be construed as being limited by the foregoing description , but is only to be considered as limited by the scope of the appended claims .