hereinafter , preferred embodiments of the present invention will be described referring to the accompanying drawings . fig1 is a view showing a configuration of a clock signal detection circuit according to a first embodiment of the present invention , as shown in fig1 , this clock signal detection circuit includes ( inside the semiconductor integrated circuit ) an inverter 1 for inverting a clock signal ck , tristate buffer circuit 2 having an output enable terminal to which the clock signal inverted by the inverter 1 is supplied , and a buffer circuit 3 to which an output signal of the tristate buffer circuit 2 is input . the output signal from the tristate buffer circuit 2 is also supplied to a terminal ( a pad ) 4 of the semiconductor integrated circuit . an external resistor , as an impedance element , is disposed between the pad 4 and the earth potential ( ground ). fig2 is a circuit diagram showing a configuration of the tristate buffer circuit shown in fig1 . as shown in fig2 , tristate buffer circuit 2 is provided with a p channel mos transistor qp 1 and a n channel mos transistor qn 1 that form an inverter , a p channel mos transistor qp 2 and a n channel mos transistor qn 2 for respectively supplying source current to transistors qp 1 and qn 1 , and an inverter 20 for inverting an output enable signal oe bar of the negative - true logic to output an output enable signal oe . the transistor qp 2 is disposed between the higher power source potential v dd and performs switching in accordance with the output enable signal oe bar of the negative - true logic applied to an output enable terminal 22 . in contrast , the transistor qn 2 is disposed between the transistor qn 1 and the lower power source potential v ss ( assumed to be the earth potential in the present embodiment ) and performs switching in accordance with the output enable signal oe output from the inverter 20 . when the output enable signal oe bar of the negative - true logic is in the low level , the transistors qp 2 and qn 2 turn on to cause the transistors qp 1 and qn 1 to operate as an inverter that inverts input signal in applied to an input terminal 21 and output the inverted signal from an output terminal 23 as an output signal out . in contrast , when the output enable signal oe bar of the negative - true logic is in the high level , the transistors qp 2 and qn 2 turn off to cause the transistors qp 1 and qn 1 to turn off resulting in the high - impedance state of the output terminal 23 independent of the state of the input signal in applied to the input terminal 21 . referring to fig1 again , the earth potential is supplied to the input terminal of the tristate buffer circuit 2 for providing thereto a low level input signal . the tristate buffer circuit 2 inverts the low level input signal to generate the high level output signal when the clock signal ck is in the high level , and makes the output terminal be in the high impedance when the clock signal is in the low level . the resistor 5 is disposed between the pad 4 and the earth potential . in general , an equivalent circuit of a resistor includes a resistance component and a capacitance component connected in parallel to the resistance component , further , the tristate buffer circuit 2 has output capacitance , and the buffer circuit has input capacitance , furthermore , there is stray capacitance in interconnection wiring . accordingly , there is also provided a capacitance component in addition to the resistance component between the pad 4 and the earth potential . electric potential of the pad 4 ( hereinafter referred to as pad potential ) v p is integrated ( smoothed ) by the resistance component and the capacitance component mentioned above when the output terminal of the tristate buffer circuit 2 is in the high impedance state . the buffer circuit 3 outputs a detection signal det in accordance with the output level of the tristate buffer circuit 2 , namely the pad potential v p . fig3 is a waveform chart showing waveforms at various points in the circuit shown in fig1 . while the clock signal ck is supplied , the high level of the clock signal ck causes the high level in the pad potential v p because the output signal of the tristate buffer circuit 2 is supplied thereto , and during the clock signal ck is in the low level , the pad potential v p smoothly drops by a discharge through the resistor 5 . in contrast , when the clock signal ck is held to the low level , the output terminal of the tristate buffer circuit 2 is held in the high impedance state causing the pad potential v p to approach the earth potential by discharging through the resistor 5 . assuming that an input level that causes the output level of the buffer circuit 3 to be changed to the other level is a threshold level v th , the detection signal det is in the high level while the pad potential v p is higher than the threshold level v th , but when the pad potential v p goes below the threshold level v th , the detection signal det also goes to the low level . thus , it is possible to reliably detect whether or not the clock signal ck is supplied with a simple circuit configuration . next , a second embodiment of the present invention will be described . fig4 is a view showing a configuration of a clock detection circuit according to the second embodiment of the present invention . in the present embodiment , the higher power source potential v dd is supplied to the input terminal of the tristate buffer circuit 2 , and the resistor 5 is disposed between the pad 4 and the power source potential v dd . the other portion of the configuration not mentioned here is substantially the same as in the first embodiment . the tristate buffer circuit 2 inverts the high level of the input signal to generate the low level output signal when the clock signal ck is in the high level , and when the clock signal ck is in the low level , the tristate buffer circuit 2 changes a state of its output terminal to the high impedance state . while the clock signal ck is supplied , the high level of the clock signal ck causes the low level of the pad potential v p because the output potential of the tristate buffer circuit 2 is applied thereto , and during the time the clock signal ck is held in the low level , the pad potential v p smoothly increases by charging through the resistor 5 . in contrast , when the supply of the clock signal ck stops , the pad potential v p approaches the power source potential v dd by charging through the resistor 5 . while the pad potential v p is below the threshold level v th , the detection signal det remains in the low level , but when the pad potential v p exceeds the threshold level v th , the detection signal det is switched to the high level . thus , with a simple circuit configuration , it is possible to reliably detect whether or not the clock signal ck is supplied thereto . in the above embodiments , the resistor 5 is provided externally . however , the resistor 5 can be formed inside the semiconductor integrated circuit . alternatively , a transistor can also be used instead of the resistor . next , a third embodiment of the present invention that uses a transistor as the impedance element will be described . fig5 is a view showing a configuration of a clock signal detection circuit according to the third embodiment of the present invention . as shown in fig5 , an n channel mos transistor 6 is disposed between the output terminal of the tristate buffer circuit 2 and the earth potential . since the gate of the transistor 6 is provided with a predetermined bias voltage v b , electric current corresponding to the bias voltage v b flows in the transistor 6 , which is equivalent to the resistor . in general , transistors have capacitance components between the drain and the gate , and between the gate and the source . furthermore , the tristate buffer circuit 2 has the output capacitance , and the buffer circuit 3 has the input capacitance . in addition , there is the stray capacitance around the interconnection wiring . accordingly , the resistance component and the capacitance component are disposed between the output terminal of the tristate buffer circuit 2 and the earth potential . when the output terminal of the tristate buffer circuit 2 is in the high impedance state , the output potential thereof is integrated ( smoothed ) by the resistance component and the capacitance component mentioned above . the buffer circuit 3 outputs the detection signal det in accordance with the output potential of the tristate buffer circuit 2 . regarding the overall operation , description for the first embodiment can substantially be applied to the present embodiment . according to the present embodiment , the clock signal detection circuit can be realized without using the resistor 5 , a passive element ( see fig1 .). next , a fourth embodiment of the present invention will be described . fig6 is a view showing a configuration of a clock signal detection circuit according to the fourth embodiment of the present invention . as shown in fig6 , this clock signal detection circuit , in addition to the circuit of the first embodiment shown in fig1 , includes ( inside the semiconductor integrated circuit ) a tristate buffer circuit 6 whose output enable terminal is provided with the clock signal ck , a buffer circuit 7 to which the output signal of the tristate buffer circuit 6 is input , and an and circuit 10 to which the output signals of the buffer circuits 3 and 7 are input . the output signal of the tristate buffer circuit 6 is also supplied to a pad 8 of the semiconductor integrated circuit . an external resistor 9 as an impedance element is disposed between the pad 8 and the earth potential . the earth potential is supplied to the input terminal of the tristate buffer circuit 6 to provide the input terminal with the low level input signal . the tristate buffer circuit 6 inverts the low level of the input signal to generate the high level signal as an output signal when the clock signal ck is in the low level , and when the clock signal is in the high level , the tristate buffer circuit 6 sets the output terminal to the high impedance state in addition to a resistance component of the resistor 9 , various capacitance components are provided between the pad 8 and the earth potential such as a capacitance component of the resistor 9 , an output capacitance of the tristate buffer circuit 6 , an input capacitance of the buffer circuit 7 , and stray capacitance along the interconnection wiring . electric potential of the pad 8 ( hereinafter referred to as pad potential ) v q is integrated ( smoothed ) by the resistance components and the capacitance component mentioned above when the output terminal of the tristate buffer circuit 6 is in the high impedance state . the buffer circuit 7 generates an output signal in accordance with the output potential of the tristate buffer circuit 6 , namely the pad potential v q . while the clock signal ck is supplied , the low level of the clock signal ck causes the high level of the pad potential v q because the output potential of the tristate buffer circuit 6 is applied thereto , and during the time the clock signal ck is held in the high level , the pad potential v q smoothly decreases by discharging through the resistor 9 . in contrast , when the clock signal ck stops in the high level , the output terminal of the tristate buffer circuit 6 is set to the high impedance state causing the pad potential v q to approach the earth potential by discharging through the resistor 9 . assuming that an input level that causes the output level of the buffer circuit 7 to be changed to the other level is a threshold level v th7 , the output potential of the buffer circuit 7 is the high level while the pad potential v q is higher than the threshold level v th7 , but when the pad potential v q goes below the threshold level v th7 , the output potential of the buffer circuit 7 also goes to the low level . also , the buffer circuit 3 generates an output signal in accordance with the output potential of the tristate buffer circuit 2 , namely the pad potential v p . when the clock signal ck stops in the low level , the output terminal of the tristate buffer circuit 2 is set to the high impedance state causing the pad potential v p to approach the earth potential by discharging through the resistor 5 . assuming that an input level that causes the output level of the buffer circuit 3 to be changed to the other level is a threshold level v th3 , the output potential of the buffer circuit 3 is the high level while the pad potential v p is higher than the threshold level v th3 , but when the pad potential v p goes below the threshold level v th3 , the output potential of the buffer circuit 3 also goes to the low level . since the output signals of the buffer circuit 3 and 7 are input to the and circuit 10 , when the clock signal ck stops in either the high level or the low level , either one of the output signals of the buffer circuits 3 and 7 becomes the low level , and accordingly , the detection signal det output from the and circuit 10 becomes the low level . in this manner , according to the present embodiment , even if the clock signal ck stops in either the high level or low level , it is possible to detect that supply of the clock signal ck stops . note that in the present embodiment a resistor formed inside the semiconductor integrated circuit or an impedance element such as transistor can also be used instead of the resistor 5 and / or 9 .