as illustrated in fig1 the write driver circuitry 10 embodying the invention comprises a supply voltage source vcc referenced to ground , a source j1 deriving a bias current ib from source vcc , and positive and negative data input terminals d and d , respectively . a bias control switch bcs1 directs the bias current ib to a current gain circuit cg1 if data input terminal d is low ; whereas a bias control switch bcs2 directs the bias current to a current gain circuit cg2 if data input terminal d is low . current gain circuit cg1 amplifies bias current ib to remove the write current iw from terminal + w of an inductive magnetic head rh ; whereas current gain circuit cg2 amplifies the bias current to remove the write current from terminal - w of the head . a current source switch css1 is connected to supply voltage source vcc and to input terminal d and to head terminal + w ; whereas current source switch css2 is connected to the supply voltage source and to input terminal d and to head terminal - w . when data input terminal d is high and d is low , switch css1 will prevent the write current from flowing into terminal + w of the head and switch css2 will allow the write current to flow into terminal - w of the head . conversely , when input terminal d is high and d is low , write current flow into terminal - w will be prevented and current flow into terminal + w will be permitted . a controllable reference voltage circuit crv is interposed between a select line sel and ground gnd . the write driver circuitry is active when the select line is low and only one of the data inputs d or d is high . the purpose of circuit crv is to maintain the head at a potential substantially near ground to prevent electro - erosion of the pole tips of the head . to achieve high data rates , the circuit crv should also be connected to the gain circuits cg1 and cg2 to prevent them from saturating ; however , this connection is not necessary for proper operation at low data rates . refer now to fig2 which depicts in specific detail how the functions described in connection with fig1 can be implemented . as illustrated in fig2 the write driver circuitry 10 embodying the invention comprises npn bipolar transistors q1 - q10 , field effect transistors ( fets ) m1 - m9 ( of which m1 , m2 , m4 , m7 and m9 are peets and m3 , m5 , m6 and m8 are nfets ), resistors r1 - r6 and diodes d1 - d5 . as will be apparent from subsequent description , bias control switch bcs2 , current source switch css2 , and current gain circuit cg2 have configurations which are mirrors of those of bcs1 , css1 and cg1 , respectively . bias control switch bcs1 comprises fet m1 whose gate is connected to input terminal d and source is connected to current source j1 . bias control switch bcs2 comprises fet m9 whose gate is connected to input terminal d and whose source is connected to current source j1 . current source switch css1 comprises fets m2 and m3 whose gates are commonly connected to input terminal d and whose drains are connected to each other and to the base of transistor q3 . the sources of fets m2 and m3 are connected to supply voltage source vcc and to ground , respectively . current source switch css2 comprises fets m7 and m8 whose gates are connected to input terminal d and whose drains are connected to each other and to the base of transistor q7 . the sources of fets m7 and m8 are connected to supply voltage source vcc and to ground , respectively . the emitter of transistor q3 is connected to terminal + w of write head rh , and the emitter of transistor q7 is connected to the terminal - w of the head . resistor r4 shunts terminals + w and - w , and resistor r4 aids in dampening transient response from a change in current direction through the inductive write head rh . current gain circuit cg1 comprises transistors q1 , q2 , q4 and resistor r1 . transistor q1 has its collector connected to the drain of fet m1 and to the base of transistor q2 and to a resistor r2 of the controllable reference voltage circuit crv . the bases of transistor q1 and transistor q4 are connected to the emitter of transistor q2 and also via resistor r1 to ground . the emitters of transistors q1 and q4 are connected to ground . current gain circuit cg2 comprises transistors q10 , q9 , q8 and resistor r6 . transistor q10 has its collector connected to the drain of fet m9 and to the base of transistor q9 and to resistor r5 of the controllable reference voltage circuit crv . the bases of transistors q10 and q8 are connected to the emitter of transistor q9 and also via resistor r5 to ground . the emitters of transistor q10 and q8 are connected to ground . controllable reference voltage circuit crv comprises , in addition to resistors r2 and r5 , resistor r3 , transistors q5 and q6 , diodes d1 - d5 , and fets m4 , m5 and m6 . resistors r2 , r3 and r5 and the bases of transistors q5 and q6 are connected to a common node a . node a is also connected to ground via serially connected diodes d2 , d3 and d4 . the collectors of transistors q5 and q6 are connected to supply voltage source vcc . the emitter of transistor q5 is connected via diode d1 to the collector of transistor q4 and to the drain of fet m5 . the emitter of transistor q6 is connected via diode d5 to the collector of transistor q8 and to the drain of fet m6 . fets m5 and m6 have their sources connected to ground , and their gates connected to a select line sel . fet m4 also has its gate connected to select line sel , its source connected to supply voltage source vcc , and its drain connected to resistor r3 of the controllable reference voltage circuit crv . the write driver circuitry 10 above described modulates the writing of data by head rh on a magnetic recording disk 12 . note that the ground connection gnd is maintained at the same potential as that of the disk 12 . in operation , when line sel is low and only one of the data inputs d or d is high , the write drive circuitry will be active . with line sel low , pfet m4 will be on , and nfets m5 and m6 will be off . with m4 on , the series connection of m4 , resistor r3 and diodes d2 , d3 and d4 creates a reference voltage at the anode of diode d2 . because the input devices m1 - m9 are fets , complementary cmos logic levels are provided for the data inputs d and d . the status of select line sel and of these cmos logic levels and of the data inputs d and d determines whether the write driver circuitry 10 is active or inactive . assume initially that line sel is low and either data input d or d are high . under this condition , write driver circuitry 10 will be active . the low signal in line sel will turn on pfet m4 and cause it to turn off nfets m5 and m6 and concurrently , via resistor r3 and diodes d2 , d3 , d4 , create a reference voltage at node a . if d is high and d low , with line sel now low pfet m1 will be off and pfet m9 will be on , allowing bias current ib to flow through m9 . meanwhile , fets m7 and m8 will invert data input d and bring the voltage at the base of transistor q7 close to the potential of the ground connection gnd , thereby restricting the flow of write current iw via the emitter of transistor q7 to terminal - w of the head . concurrently , pfets m2 and m3 will invert the d input and bring the voltage at the base of transistor q3 close to that of power supply vcc , allowing the write current iw to flow via the emitter of transistor q3 from terminal + w to terminal - w of the head . meanwhile , data input d will turn on fet m9 and allow the bias current ib to turn on transistor q9 and cause it to turn on transistors q8 and q10 . this permits the full amount of write current to flow from source vcc , via the collector / emitter of transistor q3 , terminals + w and - w of head rh and the collector / emitter of transistor q8 to ground in a positive direction . with data input d high , fet m1 will be off ; and hence transistors q1 q2 and q4 will not affect the write current iw . as earlier noted , the circuitry for driving the write current iw in a negative direction through the head rh is symmetrical . thus if d is high and d is low while line sel is low , pfet m9 will be off and pfet m1 will be on , allowing bias current ib to flow through m1 . meanwhile , pfet m2 and nfet m3 will invert data input d and bring the voltage at the base of transistor q3 close to the potential of the ground connection gnd thereby restricting the flow of write current iw via the emitter of transistor q3 to terminal + w of the head . concurrently , pfet m7 and nfet m8 will invert the d input and bring the voltage at the base of transistor q7 close to that of power supply vcc , allowing the write current iw to flow via the emitter of transistor q7 from terminal - w to terminal + w of the write head . according to features of the invention , the resistors r2 and r5 connected to node a are large in value ( e . g ., & gt ; 40 , 000 ohms ). the small currents through resistors r2 and r5 provide a trickle current through the collectors of transistors q1 and q10 . this keeps transistors q1 , q2 , q4 , q8 , q9 and q10 on with a small amount of collector current through transistors q4 and q8 . the purpose of this small collector current is to increase the transition rate by keeping these transistors on . in addition , transistors q5 and q6 in combination with diodes d1 and d5 , respectively , of the controllable reference voltage circuit crv restrict transistors q4 and q8 from going into saturation , thereby enhancing the transition rate . if these transistors were allowed to saturate , the transistors would be slower in changing current direction through the inductive write head rh . resistor r4 dampens the response of the write circuit iw through the inductive write head and thereby reduces the settling time of the write current after a transition . to reduce power consumption , write current iw can be multiplied by increasing the ratio of transistors q4 to q1 and of transistors q8 to q10 . the ratio increase can be achieved by using multiple discrete transistors or by increasing the areas for q4 and q8 . transistors q2 and q9 reduce the effects of beta variations in transistors q1 , q4 , q8 and q10 . also resistors r1 and r6 affect the transition time for switching current direction through the head . if write driver circuitry 10 is used in a multiple port configuration , the circuitry in fig2 should be replicated for each port . in such event , node b , supply source vcc and the ground connection gnd would be common nodes for all of the write driver ports ; and data inputs d and d would be multiplexed between the driver ports and controlled independently for each port . it will be understood that , if desired , the write driver circuitry above described may be modified by interchanging the supply voltage source vcc and ground connection gnd . in this event , pnp transistors would be substituted for the npn transistors q1 - q10 , nfets would be substituted for pfets m1 , m2 , m4 , m7 , and m9 , pfets would be substituted for nfets m3 , m5 , m6 and m8 , and all devices including bias current source j1 that are shown as connected to source vcc would be connected to gnd and conversely . a computer simulation of the write current iw through the inductive write head rh showed that with a supply voltage of three volts a rise time of less than 11 ns was achieved with data rates of at least five megabytes with typical write current values and write head characteristics . the write driver circuitry 10 , as thus far described , will operate satisfactorily . however , the power supply monitoring circuit 20 illustrated in fig3 is preferably added to the write driver circuitry 10 of fig2 in order to insure that the write drive circuitry will be rendered inactive when the power supply voltage from vcc is below a preselected value . as illustrated in fig3 circuit 20 comprises a reference voltage source vref1 that provides a reference voltage with a relatively small tolerance variation as compared to that of power supply source vcc . resistors r10 and r11 are connected in series from source vcc to ground to create a voltage vref2 that is proportional to the power supply voltage . an operational transconductance amplifier ota generates a current from the difference in voltage of vref1 and vref2 . the output of the ota is connected to capacitor c1 , resistor r12 and the input of an inverter 21 . the output of inverter 21 connects to the input of another inverter 22 and also to select line sel ( described in fig1 and 2 ). the output of inverter 22 is connected to the inputs of two nand gates 23 , 24 . the other inputs to nand gates 23 and 24 are dp and dp , respectively . these inputs dp and dp constitute the data inputs when using a monitoring circuit 20 , and the outputs of nand gates 23 and 24 are d and d , respectively . the ratio of the resistances of resistors r10 and r11 determine the preselected value below which the write driver circuitry 10 is deactivated . while the voltage of vref2 is substantially more positive than that of vref1 , the power supply voltage will be above the preselected value and a current will flow to node c , to which capacitor c1 and resistor r12 are connected in parallel . under this condition , a dc bias current will flow through resistor r12 and create a dc voltage , and any ac current will be bypassed through capacitor c1 . the dc voltage will be above the threshold voltage of inverter 21 , and this will make the select line sel low . the output of the inverter 22 will be high and allow both inputs dp and dp to pass through the respective nand gates 22 and 23 and render the write driver circuitry 10 active . when the voltage of vref1 is substantially more positive than that of vref2 , the power supply voltage vcc will be below the preselected value . under this condition , bias current will flow from node c ; and since the output current of the ota is limited , the output voltage of the ota will be limited between ground and that of vcc . as a result , the dc voltage will be below the threshold voltage of inverter 21 , with the result that select line sel and the nand outputs d and d will be high . consequently , the nand gates 23 and 24 will not pass the inputs dp and dp , and with line sel and d and d high , the write driver circuitry 10 will be rendered inactive . while the invention has been shown and described with respect to a preferred embodiment thereof , it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the scope and teaching of the invention . accordingly , the embodiment as herein disclosed is to be considered merely as illustrative and the invention is to be limited only as specified in the claims .