fig9 is a block diagram showing an outline structure of a thin film el display device 21 as a capacitive display device to which a drive method as one of the embodiments of the invention is applied . in the drawing , a display panel 22 is made of thin film el element , and its practical composition is same as explained in the prior art , thus , the same explanation is omitted here . scanning side electrodes y1 , y2 , . . . , yn ( collectively indicated by reference code y ) of the display panel 22 are connected to a scanning side drive circuit 24 , data side electrodes x1 , x2 , . . . , xn ( collectively indicated by reference code x ) of the display panel 22 are connected to a data side drive circuit 26 , and a display control circuit 27 for controlling these circuits is connected to the scanning side drive circuit 24 and data side drive circuit 26 . fig1 is a circuit diagram showing an outline structure of the output portion corresponding to an arbitrary pixel of the data side drive circuit 26 . in fig1 , a counter 28 is a circuit for counting clocks φ for gradation given from the display control circuit 27 , and it is connected to a comparator 29 . a latch circuit 30 is a circuit for holding the gradation display data given from the display control circuit 27 while illuminating the corresponding pixel . it is also connected to the comparator 29 . here , as the gradation display data per pixel , 4 - bit data &# 34 ; d 0 , d 1 , d 2 , d 3 &# 34 ; is given , and the gradation of 16 stages is obtained . the comparator 29 possesses a function for delivering a voltage v a at h level when the counting of the counter 28 coincides with the gradation display data &# 34 ; d0 , d1 , d2 , d3 &# 34 ; held by the latch circuit 30 . the comparator 29 is connected to the gate of a first n - channel mos transistor 32 through an inverter 31 , and is also connected to the gate of a second n - channel mos transistor 33 . the drain of the first n - channel mos transistor 32 is connected to a power supply 34 for feeding a potential hvcc of the modulation pulse . further , the source of this first transistor 32 is connected to the drain of the second n - channel mos transistor 33 , and the source of the second transistor 33 is grounded . the connecting point of the source of the first n - channel mos transistor 32 and the drain of the second n - channel mos transistor 33 is connected to an output terminal 35 . between the source and gate of the first n - channel mos transistor 32 , a zener diode 36 for passing a current in a reverse direction to the transistor 32 is connected . fig1 is a timing chart showing the operation of the gradation display drive by the above thin film el display apparatus 21 . fig1 is a graph showing the relation between the pulse width and brightness of the modulation pulse applied to an el substance 4 ( see fig1 ). this el substance 4 possesses a characteristic to increase the brightness when the applied voltage is higher , or when the applied time is longer if the voltage is constant . on the basis of this characteristic , it is possible to control to display the el substance 4 in gradation by the pwm system . when a binary code of , for example , &# 34 ; 0111 &# 34 ; is applied from the display control circuit 27 to the latch circuit 30 as gradation display data &# 34 ; d3 , d2 , d1 , d0 ,&# 34 ; if clocks φ for gradation are sequentially entered from the display control circuit 27 into the counter 28 as shown in fig1 ( 1 ). the counting of the counter 28 first becomes &# 34 ; 0000 &# 34 ; by the first clock φ input , and the counting increases at every input of clock φ thereafter . when eight clocks φ for gradation are entered in the counter 28 , and its counting reaches the gradation display data &# 34 ; d3 , d2 , d1 , d0 &# 34 ; held by the latch circuit 30 , the output voltage v a of the comparator 29 is inverted from l level to h level as shown in fig1 ( 2 ). as a result , the gate potential of the first n - channel mos transistor 32 and the gate potential of the second n - channel mos transistor 33 are respectively changed from the hitherto h level to l level and l level to h level , the first transistor 32 is inverted from on to off , and the second transistor 33 is inverted from off to on . therefore , the modulation voltage vm taken out from the output terminal 35 is inverted from h level to l level when eight clocks φ for gradation are entered into the counter 28 . up to this point of inversion , a voltage equal to the voltage hvcc of the power supply 34 is being applied to the gate of the first n - channel mos transistor 32 , and the h level of the voltage of the output terminal 35 when the first transistor 33 is turned on , that is , the modulation voltage vm , is nearly equal to the voltage hvcc of the power supply 34 . meanwhile , the time width of the waveform of this modulation voltage vm possessing a frequency of 1 mhz to 500 khz , or the pulse width of modulation pulse , varies along with the gradation display data shown above . the pulse width is broadened as the value of the gradation display data increases . this modulation voltage vm is applied to the data side electrodes 25 containing one pixel corresponding to it . at this time , the scanning side electrodes y are provided with a writing voltage vw equal to the threshold voltage vth at which the voltage level starts light emission of the el layer in the reverse polarity to the modualtion voltage vm . therefore , the above pixel is provided with an active voltage in the waveform as shown in fig1 ( 5 ) on the basis of the scanning side electrode y . thus , the pixel emits light only for the period of pulse width of the modulation pulse . that is , the emission brightness of the pixel varies depending on the gradation display data , and gradation display is effected . incidentally , application of a writing pulse into the scanning side electrodes y is effected in linear sequence of the scanning side electrodes . accordingly , the gradation display data is sequentially changed into the data corresponding to the pixels contained in the corresponding scanning side electrodes y . furthermore , in the above driving operation , in the first field , when a writing pulse of negative polarity with respect to , for example , the data side electrodes x is applied to the scanning side electrodes y , in the second field , a writing pulse of positive polarity with respect to the scanning side electrodes y is applied to the data side electrodes x . thus , ac driving for repeating the first field and second field alternately is effected . in the case of the above driving , the drain and source are nearly at the same potential when the first n - channel mos transistor 22 is turned on , and the heat loss caused by the flowing current is kept low . fig1 is a block diagram showing an outline structure of a ramp voltage generating circuit 37 for supplying a ramp voltage at modulation voltage v m to the output stage of the data side drive circuit 26 . in fig1 , a constant current circuit 38 is a circuit for passing a specific current by receiving a modualtion start signal v m - on from other functional part of the data side drive circuit 26 , and it is connected to the power supply hvcc and also to one of the terminals of the capacitor 39 , while the other terminal of the capacitor 39 is grounded . a converter 40 is a circuit for receiving a charging voltage of a capacitor 39 , and delivering a voltage v r varying according to this charging voltage , and it is connected to the power supply hvcc and also to the connecting point a of the constant current circuit 38 and capacitor 39 . between the connecting point a and the ground , a switch 41 to be turned on by receiving a modulation end signal v m - off given from other functional part of the data side drive circuit 26 is connected . the voltage of the power supply hvcc is set at the peak value of the modulation voltage v m . fig1 is a circuit diagram showing an example of practical composition of a ramp voltage generating circuit 37 shown in fig1 . in fig1 , the constant current circuit 38 is composed of resistances r1 , r2 , r3 , n - channel mos transistor q1 , and pnp transistor q2 . that is , resistances r1 , r2 are connected in series , and one end of the resistance r1 is connected to the power supply hvcc , and the other end of the resistance r2 is connected to the drain of the n - channel mos transistor q1 . further the source of this transistor q1 is grounded , and a voltage of h level is applied to the gate of this transistor q1 as the modulation start signal v m - on . at the connecting point b of the resistances r1 , r2 , the base of the pnp transistor q2 is connected , the emitter of the transistor q2 is connected to the power supply hvcc through resistance r3 , and the collector of the transistor q2 is connected to one of the terminals of the capacitor 13 . the converter 40 is composed of n - channel mos transistor q3 , the gate of the transistor q3 is connected to the connecting point a of the capacitor 39 transistor q2 , and the drain of the transistor q3 is connected to the power supply hvcc , and the source of the transistor q3 is connected to the output stage of the data side drive circuit 26 shown above ( fig9 ). the transistor q3 has a sufficient current supply capacity , and its source voltage does not vary depending on the output stage of the data side drive circuit 26 . the switch 41 is also composed of n - channel mos transistor q4 , its drain is connected to the connecting point a , its source is grounded , and a voltage of h level is applied to its gate as modulation termination signal v m - off . fig1 ( 1 ), ( 2 ), and ( 3 ) show the applied voltage waveform to the pixel in the gradation display driving in the thin film el display apparatus 21 described above , the waveform of the supply current at this time , and the waveform of the current flowing in the emission layer of the pixel , respectively . referring to these waveform diagrams , the operation is described below . from time t0 , application of writing voltage vw from the scanning side drive circuit 24 shown in fig9 to the scanning side electrodes y is started . further , the writing voltage vw reaches the emission threshold voltage vth ( time t1 ), h level voltage is applied to the gate of the transistor q1 of the ramp voltage generating circuit shown in fig1 as modulation start signal v m - on . as a result , the transistor q1 is turned on , and the base potential of the transistor q2 is lowered , and the transistor q2 is turned on . sequentially , a constant current begins to flow from the power supply hvcc into the capacitor 39 through resistance r3 and transistor q2 . the charging voltage of the capacitor 39 rises at a specific gradient as the time passes . therefore , in the transistor q3 which receives this charging voltage as a gate signal , its output or the source voltage v r increases in proportion to the charging voltage . that is , the output of the transistor q3 becomes a ramp voltage v r elevating at a specific gradient with the passing of the time . this ramp voltage v r is supplied to the output stage of the data side drive circuit 26 , and is applied to the data side electrodes x as modulation voltage v m . after a specific time t ( time t3 ), h level voltage applied to the gate of the transistor q4 of the ramp voltage generating circuit 37 shown in fig1 as modulation termination signal v m - off . then the electric charge in the capacitor 39 is discharged , the charging voltage in the capacitor 39 is suddently lowered , and the ramp voltage v r drops at the same time . in this way , the modulation voltage v m in the ramp waveform with pulse width t is applied from the data side drive circuit 26 into the data side electrodes x . at this time , the effective voltage v a applied to the corresponding pixel becomes a waveform as indicated by solid line in fig1 ( 1 ). therefore , the waveform of the power supply current at this time becomes as shown in fig1 ( 2 ), that is , the passing time after the effective voltage v a has exceeded the emission threshold voltage vth becomes longer . meanwhile , the effective voltage v a is not rectangular wave , but is a superimposed wave of the rectangular writing voltage vw and modulation voltage v m of ramp waveform . therefore the power supply current is not a peak current , but attenuates smoothly . this tendency directly continues in the current flowing in the emission layer of the pixel , and the waveform of this current is kept low in the peak value as shown in fig1 ( 3 ) it then attenuates smoothly to becomes a waveform having a long passing time . besides , by setting the pulse width of the modulation volta v m making up the ramp waveform in several short steps as indicated by single dot chain line 1 in fig1 ( 1 ), the current passing time flowing in the emission layer of the pixel shown in fig1 ( 2 ) can be also shortened . thus , gradation display is realized . in this case , since the current passing time flowing in the emission layer of the pixel is longer than in the prior art , the variable setting range of the pulse width of modulation voltage v m . that is , the effective movable range indicated by symbol t in fig1 ( 1 ) is widened , and the gradation display of multiple stages can be easily effected . moreover , the peak value of the current flowing in the emission layer of the pixels can be kept low , and the current at the brightness of each gradation stage is small . thus , the brightness does not change significantly due to error in the pulse width of the modulation voltage v m . therefore , the gradation of each stage can be stably displayed . in this embodiment , it is explained to drive the thin film el display apparatus 21 , but this invention may be similarly applied to the driving of other capacitive display apparatuses such as a plasma display . fig1 is a block diagram showing an outline structure of a thin film el display apparatus 21a to which a drive method of another embodiment of the invention is applied . in the drawing , a display panel 22 is made of thin film el element , and its practical composition is the same as the structure explained in the prior art . thus , the same explanation is omitted here . plural scanning side electrodes y1 , y2 , . . . , ym - 1 , ym arranged on the display panel 22 are connected to a scanning side drive circuit 24 disposed at the right side of fig1 . in a direction orthogonal to the scanning side electrodes y1 to ym , plural data sides electrodes x1 , x2 , . . . , xn - 1 , xn are connected to a data side drive circuit 26 disposed in the upper side of fig1 . in the scanning side drive circuit 24 , output circuits 42 are individually connected to the scanning side electrodes y1 to ym , through these output circuits 42 , writing voltage - vw or + vw is selectively applied to the scanning side electrodes y1 to ym from a minus power supply 43a to which a switch 58a is connected , or from a plus power supply 43b to which a switch 58b is connected . these output circuits 42 are connected to a shift register 44 , and in synchronism with a clock clk3 entered from the clock input terminal of the shift register 44 , scanning data s - data for setting the scanning side electrodes y1 to ym in linear sequence is transferred to the shift register 44 . thus , the output circuits 42 are turned on in the linear sequence of the scanning side electrodes y1 to ym . on the other hand , in the data side driving circuit 26 , output circuits 45 which are switches for push - pull action being composed of c - mos transistors are individually connected to the data side electrodes xl to xn . through these output circuits 45 , the modulation voltage v m is selectively applied to the data side electrodes x1 to xn from a power supply 46 having a switch 49 . besides , depending on the setting state of the output circuit 45 , the data side electrodes xl to x2 are clamped to the ground . these output circuits 45 are connected to a comparator 47 . this comparator 47 is connected to shift register 49 by way of a latch circuit 48 . the shift register 49 makes a shift action in synchronism with the clock clk1 entered from the clock input terminal , and it transfers the gradation display data corresponding to the data side electrodes x1 to xn . further , the data transferred to the shift register 49 is sent to the comparator 47 . the comparator 47 possesses a function for determining the gradation width corresponding to the gradation display data , by comparing the 3 - bit parallel data sent from the counter 50 with the gradation display data given from the latch circuit 48 . in fig1 , meanwhile , each pixel in the display panel 22 is equivalently expressed by capacitors . fig1 is a block diagram showing a correcting circuit 51 for correcting the brightness difference among pixels caused by the line resistance of data side electrodes x1 to xn . in the correcting circuit 51 in fig1 , the clock generator 52 is a circuit for generating a fundamental clock clk for determining the gradation width corresponding to the gradation display data . it can be operated by the enable signal clke given from its input terminal . in the next stage of the clock generator 52 , a delay circuit 53 is connected which delays the fundamental clock clk by a predetermined amount and applies it as clock clk2 of the counter 50 in the data side drive circuit 26 . a scanning line position detection circuit 54 is connected to this delay circuit 53 . the scanning line position detection circuit 54 possesses the functions for counting up and counting down the horizontal sync signals hd entered from the input terminal 55 as clocks , and it is reset by a vertical sync signal vd entered from the input terminal 56 . the count - up signal or count - down signal of the scanning line position detection circuit 54 is sent into the delay circuit 53 , and delay is processed in the delay circuit 53 according to the quantity corresponding to this signal . at the input terminal 57 of the scanning line position detection circuit 54 , a signal edd for determining which one of the above count - up signal or count - down signal should be sent into the delay circuit 53 is entered . in this embodiment , the signal edd is set at l level , and a count - down signal is sent to the delay circuit 53 . when the signal edd is set at h level , a count - up signal is sent into the delay circuit 53 . the basic operation of the thin film el display apparatus 21a in fig1 is explained below while referring to the timing chart shown in fig1 . to the shift register 49 of the data side drive circuit 26 , gradation display data is transferred in a form of 3 - bit binary code in synchronism with the clock clk1 . this 3 - bit gradation display data is temporarily held in the latch circuit 48 . in this state , the clear signal clr hitherto entered in the comparator 47 and counter 50 is canceled as shown in fig1 ( 1 ) ( time t1 ). the data side electrode x corresponding to the data of &# 34 ; 0 &# 34 ; out of the gradation display data held in the latch circuit 48 is clamped to the ground level , and all other data side electrodes x corresponding to other data are pulled up to the modulation voltage v m . suppose , for example , gradation display data 0 , 2 , 4 , and 7 are given to the output ports 45 corresponding to the data side electrodes x1 , x2 , xn - 1 , xn of the data side drive circuit 26 . at this time , the output circuit 45 of the data side electrode x1 is clamped to the ground simultaneously with cancellation of clear signal clr , thereby becoming the waveform shown in fig1 ( 3 ). that is , the gradation width is set at zero . at the output circuit 45 of the data side electrode x2 , on the other hand , the counting of the clocks clk2 [ see fig1 ( 2 )] counted by the counter 50 is compared with the gradation display data &# 34 ; 2 &# 34 ; in the comparator 47 . this counting value is clamped to the ground level at the timing of becoming &# 34 ; 2 &# 34 ; ( time t2 ), and the gradation width tw of the waveform shown in fig1 ( 4 ) is set . likewise , the output circuit 45 of the data side electrode xn - 1 is clamped to the ground level at the timing when the counting of the counter 50 becomes 4 ( time t3 ), and the gradation width t4 of the waveform shown in fig1 ( 5 ) is set . as for the output circuit 45 of the data side electrode xn , similarly , it is clamped to the ground level at the timing ( time t4 ) when the counting of the counter 50 becomes 7 . thus , the gradation width t7 of the waveform shown in fig7 ( 6 ) is set . therefore , at the data side electrodes xl , x2 , xn - 1 , xn , modulation voltages v m in the pulse width corresponding to the gradation display data 0 , 2 , 4 , 7 are applied . on the other hand , in the scanning side drive circuit 24 , while the clear signal clr is being cancelled by the data side drive circuit 26 , one of all output circuits 42 is turned on , and the writing voltage - vw is applied only to one corresponding scanning side electrode y . in the next field , the writing voltage + vw is applied in the same way . when the above operation is repeated in the linear sequence of the scanning side electrodes y , the pixels positioned on each scanning electrodes y emit light or do not , depending on the gradation display data . thus , screen having gradation in brightness is displayed on the whole . next the operation of brightness correction by the correcting circuit 51 shown in fig1 , is explained by referring to the timing chart shown in fig1 . a clock generator 52 delivers a fundamental clock clk in the waveform shown in fig1 ( 1 ) as the basis for determining the gradation width . in the scanning line position detection circuit 54 , after being reset by receiving a vertical sync signal vd , the horizontal sync signals hd are counted down as clock signals . in this count - down action , the number &# 34 ; m &# 34 ; of the horizontal sync signal hd in one field is set as the initial value . when the first horizontal sync signal hd in the field is counted , the count - down signal &# 34 ; m - 1 &# 34 ; is sent into the delay circuit 53 . at the delay circuit 53 , by the portion corresponding to this count - down signal &# 34 ; m - 1 &# 34 ; delay processing is conducted on the fundamental clock clk as shown in fig1 ( 2 ), and this clock is given to as clock clk2 of the counter 50 of the data side drive circuit 26 . in this case , since the count - down signal &# 34 ; m - 1 &# 34 ; is large , the delay amount ta corresponding to the fundamental clock clk of the clock clk2 is large . therefore , in the data side drive circuit 26 , the timing for starting counting of the clock clk2 in the counter 50 is significantly delayed . thus , a modulation voltage v m of pulse width ta + ta larger than the pulse width ta corresponding to the gradation data by the portion of delay amount ta is applied . fig2 shows the waveform of applied voltage to the pixel a at the intersecting position between the first scanning side electrode y1 and the data side electrode xl . specifically , fig2 ( 1 ) shows the waveform of modulation voltage v m applied from the data side electrode x1 , and fig2 ( 2 ) shows the waveform of the writing voltage - vw corresponding to the emission threshold voltage vth given from the first scanning side electrode y1 . the effective voltage applied to the pixel a at this time has the waveform as shown in fig2 ( 3 ). that is , at this pixel a , since a modulation voltage v m with a pulse width of ta + ta wider than the delay portion ta of the clock clk2 than the pulse width ta corresponding to the gradation display data as explained above is applied , the area is increased by the portion indicated by the shaded area in fig2 ( 3 ) of the portion higher than the emission threshold voltage vth contributing to the emission at the effective voltage . thus , it is corrected to a higher brightness by the portion of this area increase . in the correcting circuit 51 in fig1 , when the count - down of the scanning line position detection circuit 54 is advanced , when the count - down signal becomes m - m or zero , the delay amount in the delay circuit 53 becomes zero , and the delay amount with respect to the fundamental clock clk of the clock clk2 also becomes zero . therefore , at the data side drive circuit 26 , the starting timing for counting the clock clk2 in the counter 50 is not delayed , and the modulation voltage v m in the pulse width ta corresponding to the gradation display data is applied . in this case , since the count - down signal of the scanning line position detection circuit 54 is m - m , writing voltage - vw is applied to the scanning side electrode ym . fig2 shows the waveform of the applied voltage to the pixel b at the intersecting position with the data side electrode x1 , similar to the case of the m - th scanning side electrode ym shown above . specifically , fig2 ( 1 ) shows the integration distribution when the modulation voltage v m applied from the data side electrode xl is influenced by the line resistance of the transparent electrode fig2 ( 2 ) denotes the waveform of writing voltage - vw corresponding to the emission threshold voltage vth given from the m - th scanning side electrode ym . therefore , at this time , the effective voltage applied to the pixel b becomes the waveform as shown in fig2 ( 3 ). in this case , since the pixel b is remote from the output circuit 45 , it is influenced heavily by the line resistance . thus applied modulation voltage v m becomes an integration waveform as shown in fig2 ( 1 ), and of the portion over the emission threshold voltage vth contributing to emission at the effective voltage , the shaded area in fig2 ( 3 ) is increased . however , if the same gradation display data as the pixel a positioned on the first scanning side electrode y1 is set in the pixel b , the area increment indicated by shaded area in fig2 ( 3 ) caused at the effective voltage in the case of pixel a when a modulation voltage v m with a pulse width of ta + ta greater than the pulse width ta corresponding to the gradation display data mentioned above , becomes nearly equal to the area increment due to the effect of the line resistance in the shaded area in fig2 ( 3 ) at the effective voltage applied to the pixel b . in other words , between the pixels , a , b positioned on the same data side electrode xl , the brightness is identical for the same gradation display data . the amount of correction of brightness is determined depending on the value of the count - down signal of the scanning line position detection circuit 54 . further since the value of the count - down signal indicates the position of the scanning side electrode y at which the writing voltage - vw is applied at that time . at last , therefore , by the portion of increase of line resistance , the amount of brightness correction decreases in the linear sequence of the scanning side electrodes y . thus , the sum of the increment of brightness due to effects of line resistance and the increment of brightness due to brightness correction is always the same . in this way , a same brightness is always obtained for the same gradation display data , between pixels over the entire screen . in this embodiment , as shown in fig2 and 21 , since the application timing of the modulation voltage v m is set so that the rising part of the modulation voltage v m may be dislocated from the portion corresponding to emission of the effective voltage applied to pixels , if the modulation voltage v m is influenced by the line resistance to become an integration waveform , the rising part does not matter particularly . on the other hand , when setting the application timing of the modulation voltage v m so that the descending portion of the modulation voltage v m may be dislocated from the portion contributing to emission of the effective voltage , the descending portion of the integration waveform does not matter . however , the rising portion matters . this rising portion of the integration waveform acts to reduce the area of the effective voltage applied to the pixels as the effects of the line resistance becomes larger , reverse to the case of the foregoing embodiment , and in this case the brightness correction should be reverse to the embodiment . in other words , the signal edd applied to the input terminal of the scanning line position detection circuit 54 shown in fig1 should be set to h level , contrary to the case of the embodiment . fig2 is a block diagram showing an outline composition of thin film el display apparatus 21b to which a drive method of a further different embodiment of the invention is applied . in the drawing , a display panel 22 is composed of thin film el element , and its practical composition is same as previously explained regarding the prior art . thus the same explanation is omitted here . plural scanning side electrodes y1 , y2 , . . , ym - 1 , ym arranged on the display panel 22 are connected to a scanning side drive circuit 24 disposed at the right side in fig2 . of the plural data side electrodes x1 , x2 , . . . , xn - 1 , xn arranged toward the orthogonal direction to the scanning side electrodes y1 to ym , odd - numbered data side electrodes x1 , . . . , xn - 1 ( hereinafter arbitrary data side electrodes are indicated by symbol x ) are connected to a first data side drive circuit 26a provided at the upper side in fig2 , and even - numbered data side electrodes x2 , . . . , xn are connected to a second data side drive circuit 26b disposed at the lower side in fig2 . in the scanning side driving circuit 24 , output circuits 42 are individually connected to the scanning side electrodes y1 to ym , and writing voltage - vw or voltage + vw corresponding to the emission threshold voltage vth is selectively applied to the scanning side electrodes y1 to ym from a negative power supply 43a or a positive power supply 43b through these output circuits 42 . these output circuits 42 are connected to a shift register 44 , and the scanning data s - data for setting the scanning side electrodes y1 to ym in linear sequence are transferred to the shift register 44 in synchronism with the clock clk3 entered from the clock input terminal of the shift register 44 . further , the output circuits 42 are turned on in the linear sequence of the scanning side electrodes y1 to ym . in the first data side drive circuit 26a , output circuits 45a are individually connected to odd - numbered data side electrodes x1 , . . . , xn - 1 , and a modulation voltage v m is selectively applied to the data side electrodes x1 , . . . , xn - 1 from the power supply 46 through these output circuit 45a . besides , depending on the setting state of the output circuits 45a , the data side electrodes x1 , . . . , xn - 1 are clamped at the ground level . these output circuits 45a are connected to a comparator 47a . the comparator 47a is connected to a shift register 49a through a latch circuit 48a . the shift register 49a is a circuit for transferring the gradation display data corresponding to the data side electrodes x1 , . . . , xn - 1 by shifting in synchronism with the clock clk1 entered from the clock input terminal . further gradation display data transferred to the shift register 49a is temporarily held in a latch circuit 48a , and is sent into the comparator 47a . the comparator 47a compares the 3 - bit parallel data given from the counter 50a and the gradation display data given from the latch circuit 48a , and determines the gradation width corresponding to the gradation display data . the composition of the second data side drive circuit 26b is same as that of the first data side drive circuit 26a , and output circuits 45b are individually connected to the even - numbered data side electrodes x2 , . . . , xn . through these output circuits 45b , modulation voltage v m is selectively applied to the data side electrodes x2 , . . . , xn from the power supply 46 . these output circuits 45b are connected to a comparator 47b , and the comparator 47b is connected to a shift register 49b through a latch circuit 48b . the comparator 47b compares the 3 - bit parallel data given from the counter 50b with the gradation display data given from the latch circuit 48b , and determines the gradation width corresponding to the gradation display data . in fig2 , meanwhile , the pixels in the display panel 22 are equivalently expressed by capacitors . fig2 is a block diagram showing a correcting circuit 51a for correcting the brightness difference among pixels caused due to the line resistance of the data side electrodes xl to xn in the above thin film el display apparatus 21b . in the correcting circuit 51a in fig2 , a clock generator 52 is a circuit for generating a fundamental clock clk for determining the gradation width corresponding to the gradation display data . it is operated by an enable signal clke given from its input terminal . at the next stage of the clock generator 52 , a first delay circuit 53a for delaying the fundamental clock clk by a predetermined amount and producing , as a clock , odd - clk2 of the counter 50a of the first data side drive circuit 26a , and a second delay circuit 53b for delaying the fundamental clock clk by a predetermined amount and giving as a clock even - clk2 of the counter 50b of the second data side drive circuit 26b are connected . a scanning line position detection circuit 54 is connected to these delay circuits 53a , 53b . this scanning line position detection circuit 54 has the function of counting up or down the horizontal sync signals hd entering from its input terminal 55 as a clock , and it is reset by a vertical sync signal entering from the input terminal 56 . either the count - up signal or the count - down signal of the scanning line position detection circuit 54 is given to the first delay circuit 53a , the other is given to the second delay circuit 53b , and delaying process is effected in the delay circuit 53a , 53b by the portion corresponding to these signals . a signal edd for determining to send the count - up signal and count - down signal to either one of the two delay circuits 53a , 53b is fed into the input terminal 57 of the scanning line position detection circuit 54 . in this embodiment , the signal edd is set at l level , and a count - down signal is given to the first delay circuit 53a , and a count - up signal is given to the second delay circuit 53b . when the signal edd is set at h level , a count - up signal is given to the first delay circuit 53a , and a count - down signal is given to the second delay circuit 53b . the basic operation of the thin film el display apparatus 21b shown in fig2 is explained below while referring to the timing chart shown in fig1 . to the shift registers 49a , 49b of the first and second data side drive circuits 26a , 26b , gradation display data is transferred in a form of 3 - bit binary code in synchronism with the clock clk1 . this 3 - bit gradation display data is temporarily held in the latch circuits 48a , 48b . in this state , the clear signal clr entered hitherto in the comparators 47a , 47b and counters 50a , 50b is cleared as shown in fig1 ( 1 ). then , the data side electrode x corresponding to &# 34 ; 0 &# 34 ; data among the gradation display data held in the latch circuits 48a , 48b is clamped at the ground level , and all other data side electrodes x corresponding to the other data are pulled up to the modulation voltage v m . suppose the gradation display data 0 , 2 , 4 , and 7 are given to the output circuits 45a , 45b corresponding to the data side electrodes x1 , x2 , xn - 1 , xn of the data side drive circuit 26a , 26b . at this time , the output circuit 45a of the data side electrode x1 is clamped at the ground level simultaneously with clearing ( time t0 ) of the clear signal clr to become a waveform as shown in fig1 ( 3 ). that is , the gradation width is set to zero . at the output circuit 45b of the data side electrode , the counting value of the clock clk2 counted by the counter 50b as shown in fig1 ( 2 ) is compared with the gradation display data &# 34 ; 2 &# 34 ; in the comparator 47b . when the counting becomes 2 ( time t1 ), it is clamped at the ground level , and the gradation width t2 in the waveform shown in fig1 ( 4 ) is set . likewise , the output circuit 45a of the data side electrode xn - 1 is clamped at the ground level when the counting of the counter 50a becomes 4 ( time t2 ), and the gradation width t4 in the waveform shown in fig1 ( 5 ) is set . the output circuit 45b of the data side electrode xn is clamped at the ground level when the counting of the counter 50b becomes 7 ( time 3 ), and the gradation width t7 in the waveform shown in fig1 ( 6 ) is set . therefore , in the data side electrodes x1 , x2 , xn - 1 , xn , modulation voltages v m in the pulse width corresponding to the gradation display data 0 , 2 , 4 , and 7 are applied . on the other hand , in the scanning side drive circuit 24 , while the clear signal clr is being canceled in the data side drive circuits 26a , 26b , only one of the output circuits 42 is turned on . thus , a writing voltage - vw corresponding to the emission threshold voltage vth is applied only one corresponding scanning side electrode y . when this operation is repeated in the linear sequence of the scanning side electrodes y , the pixels on the scanning side electrodes y are illuminated or not in the brightness corresponding to the gradation display . thus , a screen having gradation in brightness on the whole is displayed . the operation of the brightness correction by the correcting circuit 51a shown in fig2 is described below by referring to the timing chart shown in fig2 . the clock generator 52 delivers a fundamental clock clk which becomes the basis for determining the gradation width [ see fig2 ( 1 )]. in the scanning line position detection circuit 54 , after being reset by receiving a vertical sync signal vd , the horizontal sync signals hd as clock are counted up and counted down at the same time . in the count - up operation , &# 34 ; 0 &# 34 ; is set as the initial value . in the count - down operation , the number &# 34 ; m &# 34 ; of the horizontal sync signals hd in one filed is set as the initial value . when the first horizontal sync signal vd is counted , this count - down signal &# 34 ; m - 1 &# 34 ; is sent into the first delay circuit 53a , and the count - up signal &# 34 ; 1 &# 34 ; is sent into the second delay circuit 53b . by the amount corresponding to the count - down signal &# 34 ; m - 1 &# 34 ; and the count - up signal &# 34 ; 1 &# 34 ; the delay circuits 53a , 53b delay the fundamental clocks clk . these clocks are given as clock odd - clk2 of the counter 50a of the first data side drive circuit 26a and clock even - clk2 of the counter 50b of the second data side drive circuit 26b . in this case , since the count - down signal &# 34 ; m - 1 &# 34 ; is sufficiently larger than the count - up signal &# 34 ; 1 &# 34 ;, the delay amount ta of the clock odd - clk2 with respect to the fundamental clock clk is sufficiently large as shown in fig2 ( 3 ), while the delay amount tb of the clock even - clk2 is a small value as shown in fig2 ( 2 ). therefore , in the first data side drive circuit 26a , the timing to start counting of the clock odd - clk2 in the counter 50a is considerably delayed , and a wider gradation than the gradation width corresponding to the gradation display data is set in the output circuit 45a . further , modulation voltage v m of a wider pulse width ta - ta than the pulse width ta corresponding to the gradation display data is applied to the odd - numbered data side electrodes x1 , . . . , xn - 1 . by contrast , in the second data side drive circuit 26b , the timing to start counting of the clock even - clk2 in the counter 50b is hardly delayed , the gradation width nearly corresponding to the gradation display data is set in the output circuit 45b , and a modulation voltage v m in a pulse width ta nearly corresponding to the gradation display data is applied to the even - numbered data side electrodes x2 , . . . , xn . fig2 shows the waveform of applied voltage corresponding to pixels at intersecting positions of the first scanning side electrode y1 and odd - numbered data side electrodes x1 , . . . , xn - 1 . of them , fig2 ( 1 ) indicates the waveform of modulation voltage v m applied from the data side electrodes x1 , . . . , xn - 1 , and fig2 ( 2 ) shows the waveform of the writing voltage - vw corresponding to the emission threshold voltage vth applied from the first scanning side electrode y1 . the effective voltage applied to the above pixels at this time becomes as shown in fig2 ( 3 ). that is , on these pixels , modulation voltage v m in a pulse width ta + ta wider than the pulse width ta corresponding to the gradation display data by the portion of delay amount ta of the clock odd - clk2 is applied as mentioned above . of the portion above the emission threshold voltage vth contributing to emission at the effective voltage , the portion indicated by shaded area in fig2 ( 3 ) is increased in the area , and the brightness is corrected to the higher side by the portion of this area increment . on the other hand , fig2 shows the waveform of applied voltage to pixels at the intersecting positions of the first scanning side electrode y1 and the even - numbered data side electrodes x2 , . . . , xn . of them , fig2 ( 1 ) indicates the waveform of the modulation voltage v m applied from the data side electrodes x2 , . . . , xn , and fig2 ( 2 ) denotes the waveform of writing voltage - vw corresponding to the emission threshold voltage vth applied from the first scanning side electrode y1 . therefore , the effective voltage applied to the pixels at this time has the waveform as shown in fig2 ( 3 ). in this case , since the pixels are remote from the output circuit 45b , the effect of the line resistance is significant , and the modulation voltage v m being applied becomes the integration waveform as shown in fig2 ( 1 ). further , of the portion above the emission threshold voltage vth contributing to emission at the effective voltage , the portion indicated by shaded area in fig2 ( 3 ) is increased . since the modulation voltage v m in the pulse width ta nearly corresponding to the gradation display data is applied to these pixels , if the same gradation display data are set in the odd - numbered data side electrodes x1 , . . . , xn - 1 and even - numbered data side electrodes x2 , . . . , xn , the area increment indicated by shaded area in fig2 ( 3 ) caused at the effective voltage applied to the pixels corresponding to the odd - numbered data side electrodes x1 , . . . , xn - 1 becomes nearly equal to the area increment due to the effect of line resistance indicated by shaded area in fig2 ( 3 ) at the effective voltage applied to the pixels corresponding to the even - numbered data side electrodes x2 , . . . , xn . therefore , among the pixels positioned on the first scanning side electrode y1 , the brightness is the same for same gradation display data . in the correcting circuit 51a in fig2 , when the count - up or count - down of the scanning line position detection circuit 54 is advanced ( therefore , the scanning side electrode y to which the writing voltage - vw is applied is shifted downward at the same time ), the delay amount ta of the clock odd - clk2 delivered from the first delay - circuit 53a is gradually decreased in response , while the delay amount tb of the clock even - clk2 delivered from the second delay circuit 53b is gradually increased . further , when the writing voltage - vw is applied to the middle scanning side electrode y , the delay amounts ta , tb of the two clocks odd - clk2 , even - clk2 become equal to each other . at this time , at the pixel positioned on the middle scanning side electrode y , the line length of the odd - numbered data side electrodes x1 , . . . , xn - 1 and the line length of the even - numbered data side electrodes x2 , . . . , xn become equal to each other , and the effects of the line resistance are nearly identical . accordingly , the brightness corrections of equivalent extents are effected , so that the brightness of pixels may be uniform . when the count - up and count - down of the scanning line position detection circuit 54 in the correcting circuit 51a in fig2 are further advanced ( therefore , the scanning side electrode to which the writing voltage - vw is applied is shifted downward from the middle ), the relation between the delay amount ta of the clock odd - clk2 delivered from the first delay circuit 53a and the delay amount tb of the clock even - clk2 delivered from the second delay circuit 53b is inverted . similarly , the brightness correction corresponding to each delay amount is effected on the corresponding pixels . in other words , the delay amounts ta , tb of two clocks odd - clk2 , even - clk2 always keep a complementary relation within one field . in this way , among the pixels in the entire screen , a same brightness is obtained for the same gradation display data . in this embodiment , meanwhile ,. as shown in fig2 and 21 , since the application timing of the modulation voltage v m is set so that the rising part of the modulation voltage v m may be dislocated from the portion contributing to the emission out of the effective voltage applied to the pixels , if the modulation voltage v m is influenced by the line resistance to become integration waveform , its rising part does not pose any problem . by contrast , when the application timing of the modulation voltage v m is set so that the descending part of the modulation voltage v m may be dislocated from the portion contributing to the emission of the effective voltage , the descending part of the integration waveform does not matter , but the rising part poses a problem . the rising part of the integration waveform acts to decrease the area of the voltage applied to the pixels as the effect of the line resistance increases , reverse to the case of the above embodiment . further , in this case the brightness should be corrected in the reverse manner of the shown embodiment . that is , the signal edd applied to the input terminal of the scanning line position detection circuit 54 shown in fig2 should be set to h level , contrary to the above embodiment . incidentally , this invention is not limited to the thin film el display apparatus 21 , 21a , 21b , but it may be freely embodied in any arbitrary capacitive display apparatus such as a plasma display apparatus . the invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof . the present embodiments are therefore to be considered in all respects as illustrative and not restrictive , the scope of the invention being indicated by the appended claims rather than by the foregoing description and all changes which come within the meaning and the range of equivalency of the claims are therefore intended to be embraced therein .