embodiments of the present invention will be explained in detail with reference to the accompanying drawings hereinafter . [ 0028 ] figs . 1a to 1 g are sectional views showing steps of manufacturing a semiconductor device according to a first embodiment of the present invention . fig . 2a is a plan view showing a configuration in fig1 d , and fig . 2b is a plan view showing a configuration in fig . 1e . to begin with , the steps needed to manufacture the configuration shown in fig . 1a will be explained hereunder . in fig . 1a , a field oxide film 2 is formed around a transistor forming region on a surface of a p - type silicon substrate ( semi - conductor substrate ) 1 . the field oxide film 2 is formed by the selective oxidation method which employs a pattern formed of silicon nitride , for example , as an oxidation preventing mask . a mos transistor 3 is then formed in the transistor forming region on the silicon substrate 1 . the mos transistor 3 is formed along following steps . a silicon dioxide ( sio 2 ) film serving as a gate insulating film 3 a is then formed on the surface of the silicon substrate 1 by the thermal oxidation method . a gate electrode 3 g is then formed on the gate insulating film 3 a . while using the gate electrode 3 g as a mask , an n - type impurity such as phosphorus , arsenic , etc . is then ion - implanted into the silicon substrate 1 on both sides of the gate electrode 3 g . in turn , insulative sidewalls 3 w are formed on both side surfaces of the gate electrode 3 g . while using the sidewalls 3 w and the gate electrode 3 g as a mask , the n - type impurity is then ion - implanted into the silicon substrate 1 . according to such twice impurity ion implantation , first and second impurity diffusion layers 3 d , 3 s having an ldd configuration respectively are formed in the silicon substrate 1 on both side of the gate electrode 3 g . with the above , the steps of forming the mos transistor 3 are completed . subsequently , a first interlayer insulating film 4 formed of silicon dioxide is formed on the field oxide film 2 and the mos transistor 3 to have a thickness of 500 nm . the first interlayer insulating film 4 can be formed by the chemical vapor deposition method using silane ( sih 4 ) as the reaction gas . a plurality of films of a capacitor are formed on the first interlayer insulating film 4 in the region where the field oxide film 2 is formed . first , as shown in fig . 1b , a 20 nm thick titanium ( ti ) film 5 a and a 175 nm thick platinum ( pt ) film 5 b are formed in sequence on the first interlayer insulating film 4 by the sputter method . the ti film 5 a and the pt film 5 b are employed as a lower electrode 5 of the capacitor q . an oxide dielectric film 6 of the capacitor q is then formed on the lower electrode 5 . as the oxide dielectric film 6 , for example , a plzt film or a pzt film which is formed by the sputter method to have a thickness of 300 nm is available . the plzt is obtained by adding lanthanum ( la ) into the pzt . this lanthanum is doped to improve capacitor characteristics . a composition ratio of constituent elements of the plzt film , for example , lead ( pb ), lanthanum ( la ), zirconium ( zr ), and titanium ( ti ) are set to 1 . 07 , 0 . 03 , 0 . 30 , and 0 . 70 respectively . after such oxide dielectric film 6 has been formed , rta ( rapid thermal annealing ) is then carried out in the oxygen - containing atmosphere at 850 ° c . for about 10 second to improve crystal property of the oxide dielectric film 6 . a platinum film is then formed on the oxide dielectric film 6 to have a thickness of 175 nm . this platinum film is employed as upper electrodes 7 of the capacitor q . the platinum film is then patterned into rectangular patterns of 2 × 2 μm 2 , for example , by the plasma etching and the photolithography using resist , as shown in a plan view of fig . 2a . thus , a plurality of upper electrodes 7 are formed separately at a distance of 1 μm . positions of a plurality of capacitors q can be defined by these rectangular upper electrodes 7 . in this case , a gas containing chlorine ( c 1 ) is employed as an etchant of the pt film . since damage is caused on the boundary between the upper electrodes 7 and the oxide dielectric film 6 in this etching , such damage is then removed by oxygen - annealing . this oxygen - annealing is effected by exposing the upper electrodes 7 and the oxide dielectric film 6 to the oxygen atmosphere at the substrate temperature of 650 ° c . for 60 minute . oxygen is supplied to the oxide dielectric film 6 via the upper electrodes 7 . the oxide dielectric film 6 is then patterned by the photolithography method , as shown in fig2 a , to be left at least below the rectangular upper electrodes 7 , and the lower electrode 5 is then patterned by the photolithography method such that a part of the lower electrode 5 is exposed from the oxide dielectric film 6 . since the oxide dielectric film 6 is damaged by the photolithography method , the oxygen - annealing is then performed at the substrate temperature of 550 ° c . for 60 minute in order to restore the film quality of the oxide dielectric film 6 . after above patterning has been finished , the upper electrodes 7 , the oxide dielectric film 6 , and the lower electrode 5 have their sectional shapes , as shown in fig1 c , respectively . then , as shown in fig . 1d , a second interlayer insulating film 8 made of silicon dioxide is formed on the capacitors q and the first interlayer insulating film 4 to have a thickness of 200 nm . the second interlayer insulating film 8 is grown at the substrate temperature of 390 ° c . by vaporizing teos ( tetra ethoxy silane ), which is organic silicon compound having low reduction property , and then introducing it into the reaction atmosphere together with the carrier gas . the first interlayer insulating film 4 and the second interlayer insulating film 8 are then patterned by the photolithography method . thus , as shown in fig1 e , first openings 8 a for exposing the first impurity diffusion layers 3 d of the mos transistors 3 respectively , a second opening 8 b for exposing a part of the lower electrode 5 , and third openings 8 c for exposing a part of the upper electrodes 7 respectively are formed . with the use of resist , patterning of the first interlayer insulating film 4 and the second interlayer insulating film 8 , both being formed of sio 2 , are executed by the plasma etching using a gas containing fluorine ( f ). since the oxide dielectric film 6 is damaged via the third openings 8 c and the upper electrodes 7 in forming and patterning the second interlayer insulating film 8 , the oxide dielectric film 6 is annealed in the oxygen atmosphere at the substrate temperature of 550 ° c . in order to recover a normal state of the damaged oxide dielectric film 6 . then , as shown in fig . 1f , a titanium nitride ( tin ) film 9 of 100 nm thickness is formed on the second interlayer insulating film 8 and in the first to third openings 8 a to 8 c by the reactive sputter method . by patterning the tin film 9 by virtue of the photolithography method , local interconnections 9 a which connect the upper electrodes 7 and the impurity diffusion layers 3 d via the first openings 8 a and the third openings 8 c respectively are formed and simultaneously a lower electrode leading wiring 9 b which extends the lower electrode 5 to the external device is formed . the local interconnections 9 a are patterned to cover the rectangular upper electrodes 7 respectively , as shown in fig . 2b . in this case , since it is possible to miniaturize the tin film 9 serving as the local interconnections 9 a by the photolithography , the local interconnections 9 a can be patterned such that a distance between a plurality of local interconnections 9 a which cover a plurality of upper electrodes 7 separately is set to 1 μm to 0 . 4 μm . then , as shown in fig . 1g , a third interlayer insulating film 10 is formed under the same conditions as those in growing the second interlayer insulating film 8 using teos . thus , the local interconnections 9 a and the lower electrode leading wiring 9 b are covered with the third interlayer insulating film 10 . in addition , an sog film 11 is formed by coating a solution , in which silicon compound is solved into an organic solvent , on the third interlayer insulating film 10 and then firing the solution . hydrogen is contained in the material which is employed in growing the third interlayer insulating film 10 and the sog film 11 . however , since the oxide dielectric film 6 formed below the upper electrodes 7 is covered with the local interconnections 9 a formed of tin which does not transmit the hydrogen , the damage of the oxide dielectric film 6 due to the reduction action is hardly caused . accordingly , no oxygen - annealing of the oxide dielectric film 6 is needed after the third interlayer insulating film 10 and the sog film 11 have been formed . as a result , there is no possibility that the local interconnections 9 a and the lower electrode leading wiring 9 b are oxidized . then , by patterning the third interlayer insulating film 10 and the sog film 11 by virtue of the photolithography method , a fourth opening 11 a is formed on the lower electrode leading wiring 9 b and simultaneously fifth openings 11 b are formed on the second impurity diffusion layers 3 s of the mos transistors 3 . a first wiring 12 which is connected to the lower electrode leading wiring 9 b via the fourth opening 11 a is then formed on the sog film 11 . second wirings 13 which are connected to the second impurity diffusion layers 3 s via the fifth openings 11 b are then formed on the sog film 11 . the first wiring 12 and the second wirings 13 are composed of a quadruple - layered film which consists of titanium , titanium nitride , aluminum , and titanium nitride , respectively . electric characteristics of the capacitors q in the semiconductor device formed according to the above - mentioned steps will be evaluated in the following . when a hysteresis curve of polarization of the capacitor q and an applied voltage is checked , a result shown in fig3 has been derived . in fig3 , two intercepts of the hysteresis curve on the y - axis are called spontaneous polarization ( pr ) which acts as an index for indicating ferroelectricity . a value of |+ pr |+|− pr | has become 35 . 0 μc / cm 2 by calculation . on the contrary , as shown in fig4 a , in the semiconductor device in which local interconnections 30 a each having a width narrower than that of the upper electrode 7 of the capacitor q are formed , a hysteresis curve of the capacitor q can be given as shown in fig . 4b . a value of |+ pr |+|− pr | has become 24 . 2 μ c / cm 2 by calculation . the cause of reduction in the spontaneous polarization like the above may be supposed as that the oxide dielectric film 6 made of ferroelectric material lacks the oxygen due to the reduction action of the hydrogen , which is generated in forming the third interlayer insulating film 10 and the sog film 11 on the local interconnections 30 a , to thus cause reduction in a dielectric constant . therefore , it has been found that , as shown in fig2 b , formation of the local interconnections 9 a made of metal nitride in the range overlapping on the rectangular upper electrodes 7 is effective at preventing the damage of the oxide dielectric film 6 due to the reduction gas being generated in forming the insulating film on the local interconnections 9 a . in the above examples , the local interconnections 9 a are formed by the titanium nitride . however , the local interconnections 9 a may be formed by a metal like nitride alloy such as tungsten nitride , titanium - tungsten nitride , etc ., which does not have hydrogen permeability and whose fine patterning can be easily made . in the above examples , the plzt and the pzt are employed as the oxide dielectric film 6 made of ferroelectric material . however , ferroelectrics such as ( ba , sr ) tio 3 , pb ( zr , ti ) o 3 , ( pb , la )( zr , ti ) o 3 , srbi 2 ta 2 o 9 , ta 2 o 3 , etc . may be employed . in this case , it is possible to fabricate the capacitors having good characteristics by adopting the above local interconnections 9 a . further , iridium ( ir ), ruthenium ( ru ), or conductive ceramics may be selected in addition to platinum ( pt ) as constituent material of the upper electrodes 7 . a reference 30 b in fig . 4a denotes a lower electrode leading wiring . in the first embodiment , since the substantial size of the capacitor q is defined according to sizes of the rectangular upper electrodes 7 as described above , miniaturization of the capacitor q is restricted by a working precision of the upper electrode 7 . therefore , in the second embodiment , formation of the capacitor which is not restricted by the pattern precision of the upper electrodes 7 will be explained hereunder . at first , like the first embodiment , the lower electrode 5 and the oxide ferroelectric film 6 are formed on the first interlayer insulating film 4 in the state shown in fig . 1a . the lower electrode 5 and the oxide ferroelectric film 6 are then patterned into the same shapes as those in the first embodiment by the photolithography method . their sectional shapes are given as shown in fig . 5a . an intermediate insulating film 15 for covering the first interlayer insulating film 4 is formed under the same conditions as those of the second interlayer insulating film 8 using the above teos . then , as shown in fig5 b , windows 16 for defining the areas of the capacitor q respectively are formed by patterning the intermediate insulating film 15 , so that a part of the oxide ferroelectric film 6 is exposed from the windows 16 . planar shapes and positions and largeness of the windows 16 become identical to those of the upper electrodes 7 shown in fig . 2a . a 175 nm thick platinum film is then formed on the intermediate insulating film 15 and in the windows 16 . then , as shown in fig5 c , the platinum film is patterned to be left in the windows 16 and their peripheral regions , so that the left platinum films are employed as upper electrodes 17 . after this , in order to eliminate the damage of the oxide ferroelectric film 6 caused at the time of formation of the upper electrodes 17 and formation of the intermediate insulating film 15 , the oxygen - annealing is applied . like the first embodiment , the second interlayer insulating film 8 is then formed , then the first openings 8 a to the third openings 8 c are formed in the second interlayer insulating film 8 , and then the local interconnections 9 a for covering the windows 16 are formed to define at least the positions of the capacitors q . the steps carried out after the local interconnections 9 a have been formed are similar to those in the first embodiment . in the end , as shown in fig . 5d , a sectional shape of the semiconductor device according to a second embodiment is formed . as discussed above , since it is designed that the positions and the size of the capacitors q would be defined by the windows 16 , the positions and the size of the capacitors q are restricted according to the pattern precision of the intermediate insulating film 15 . thus , the pattern precision of the intermediate insulating film 15 , i . e ., the silicon dioxide film becomes higher than that of the metal film such as titanium nitride , etc . as a result , finer capacitor shapes can be achieved with good reproducibility . even if the structure of the second embodiment is employed , degradation of the capacitors q due to the reduction gas ( hydrogen ) can be suppressed since the local interconnections 9 a connected to upper electrodes 14 are arranged to cover the capacitors q like the first embodiment . in case the structure of the second embodiment is adopted , the silane gas may be employed to form the intermediate insulating film 15 prior to formation of the upper electrodes 17 . this is because the upper electrodes have not been formed on the oxide ferroelectric film 6 yet and thus there is no necessity that film peeling of the upper electrodes due to degradation in film quality of the oxide ferroelectric film 6 should be taken account at this stage . a large quantity of hydrogen is generated when the silane gas is employed , so that the film quality of the oxide dielectric film is deteriorated . however , the film quality of the oxide dielectric film can be restored by performing the oxygen - annealing succeedingly . since the silicon oxide film which employs the silane as material has fine film quality and is hard to absorb moisture rather than the silicon oxide film which employs organic silicon as material , the ferroelectric memory device which has excellent moisture resistance can be implemented if the silane gas is employed as the material gas . in the first and second embodiments of the present invention , as shown in fig1 f and fig5 d , the local interconnections 9 a are connected directly to the impurity diffusion layers 3 d . in this event , plugs may be filled in the first openings 8 a which are formed on the impurity diffusion layers respectively and then the local interconnections 9 a may be connected to the impurity diffusion layers 3 d via the plugs . therefore , the step of forming the plugs and the step of connecting the plugs and the local interconnections 9 a will be explained hereunder . the structure in the first embodiment will be employed as the capacitor structure to be described in the following , but the structure in the second embodiment may also be employed . at first , as shown in fig6 a , the first interlayer insulating film 4 is formed to have a thickness of 200 nm , and then a fourth interlayer insulating film 20 is formed on the first interlayer insulating film 4 to have a thickness of 1000 nm . in this case , silicon nitride oxide is employed as material constituting the first interlayer insulating film 4 , and silicon oxide is employed as material constituting the fourth interlayer insulating film 20 . then , as shown in fig6 b , the fourth interlayer insulating film 20 is planarized by the cmp ( chemical mechanical polishing ) method . this polishing is stopped at the location where the first interlayer insulating film 4 covering the gate electrode 3 g which extends as the word line on the field oxide film 2 is exposed . then , as shown in fig6 c , first openings 20 d and fourth openings 20 s are formed on the first impurity diffusion layers 3 d and the second impurity diffusion layers 3 s respectively by patterning the first interlayer insulating film 4 and the fourth interlayer insulating film 20 by virtue of the photolithography method . then , as shown in fig . 6d , a tungsten film 21 is formed on the fourth interlayer insulating film 20 and in the first openings 20 d and the fourth openings 20 s . the tungsten film 21 is polished by the cmp method to be left only in the first openings 20 d and the fourth openings 20 s . the tungsten film 21 left in the first openings 20 d is used as first plugs 21 d , while the tungsten film 21 left in the fourth openings 20 s is used as second plugs 21 s . then , as shown in fig6 e , in order to prevent oxidation of surfaces of the first plugs 21 d and the second plugs 21 s filled in the first openings 20 d and the fourth openings 20 s respectively , an oxidation preventing film 22 is formed on the fourth interlayer insulating film 20 , the first plugs 21 d , and the second plugs 21 s . it is preferable to employ the silicon nitride or the silicon nitride oxide as constituent material of the oxidation preventing film 22 . then , as shown in fig6 f , the capacitors consisting of the lower electrode 5 , the dielectric film 6 , and the upper electrodes 7 are formed via the steps explained in the first embodiment . in this case , the dielectric film 6 has the same planar shape as the lower electrode 5 . after this , a fifth interlayer insulating film 23 covering the lower electrode 5 is formed and then the second interlayer insulating film 8 is formed in the same way as the first embodiment . then , the second opening 8 b for exposing the lower electrode 5 , the third openings 8 c for exposing a part of the upper electrodes 7 , and fifth openings 8 d for exposing the first plugs 21 d are formed by patterning the second interlayer insulating film 8 , the fifth interlayer insulating film 23 , and the dielectric film 6 . as in the first embodiment , the local interconnections 9 c which have their size to overlap with the upper electrodes 7 and which extend from the third openings 8 c to the fifth openings 8 d respectively are formed on the second interlayer insulating film 8 . at the same time , the lower electrode leading wiring 9 b is formed to extend from the second opening 8 b over the second interlayer insulating film 8 . then , the third interlayer insulating film 10 and the sog film 11 are formed via the same steps as those in the first embodiment , and the first wiring 12 and the second wirings 13 are then formed . as described above , according to the present invention , the capacitors are covered with the local interconnections whose fine patterning can be achieved and also the upper electrodes of the capacitors and the impurity diffusion layers are connected by the local interconnections respectively . therefore , individual capacitors can be covered with the local interconnections without fail if the capacitors employing the oxide dielectric film are fabricated with a high integration density . as a result , hydrogen diffusion into the capacitors can be prevented by the local interconnections even when the hydrogen is generated in forming the insulating film on the local interconnections , and thus the succeeding oxygen - annealing of the oxide dielectric film can be omitted and also the oxidation of the local interconnections can be prevented . in addition , the windows are opened in the insulating film which is formed on the oxide dielectric film , and then the oxide dielectric film and the upper electrodes are connected via the windows . therefore , a higher integration density of the capacitors can be achieved according to the size of the windows which are formed in the insulating film and which enable higher precision of the patterning .