example embodiments will now be described more fully with reference to the accompanying drawings . first , the behavior of a digital design is formalized using an intuitive notion that represents the design with hardware components reacting to input sequences . the emphasis is on the usage model and methodology rather than rigorous model checking or sequential equivalence checking theories . in a design with non - determinism due to partially initialized registers or the use of x in various forms , the values observed on the outputs are characterized with respect to determinism and whether the correct design description is sufficiently masking the non - determinism from the outputs . a hardware design can be described as a tuple v , init , trans , where v = i ∪ s ∪ c , and i is the set of input variables , s is the set of state - holding variables , and c is the set of intermediate combinational variables . each variable is a vector of 1 - bit components , and each can take the value of 0 and 1 . thus , the valuations of an n - bit variable belongs to { 0 , 1 } n . with a fully initialized design and no use of x , the valuations of all the design variables are deterministically dependent on the inputs . non - determinism is present when some components can take either 0 or 1 even if the inputs are fully specified . in this disclosure , this is referred to as x or don &# 39 ; t care , interchangeably . a formal verification engine will exhaustively try 0 or 1 in place of the x , in order to determine certain properties . therefore , the formal analysis is based solely on the { 0 , 1 } domain . let , and denote the sets of all possible valuations of s , c and i , respectively . init is a subset of representing the group of initial states . trans : × → × is a transition function such that ( s ′, c )= trans ( s , in ) where s , in and c are the valuations of s , i and c respectively at the current time frame , and s ′ is the valuation of s at the next time frame . we focus in this disclosure on designs with a single clock domain . in such designs , the succession of time frames is defined by the edges of the most frequent clock in the system . let m = v , init , trans be a hardware design . let ( s 1 , . . . , s n s ), ( c 1 , . . . , c n c ) and ( i 1 , . . . , i n l ) denote the elements of s , c and i respectively . let proj s ( s , j ) return the valuation of s j under s . in other words s = ( proj s ( s , 1 ), . . . , proj s ( s , n s ) . let proj c and proj i be defined similarly . let val m ( s , in , v ) denote the valuation of the variable v , given that the valuation of s is s , and the valuation of i is in . val m is computed using the proj and trans functions . formally , given that , let val m k be a generalization of val that takes into account the time frames of the design . formally val m k is defined recursively as follows : val m k ( s , in 1 , in 2 , . . . , in k + 1 , v )= val m k − 1 ( s ′, in 2 , . . . , in k + 1 , v ); where ( s ′, c )= trans ( s , in 1 ) in words , val m k ( s , in 1 in 2 , . . . , i k + 1 , v ) is the valuation of the variable v at the current time frame , the input at the current time frame is in k + 1 . let m = v , init , trans be a hardware design . let equal k : init 2 × k + 1 ×( i ∪ s ∪ c )→{ true , false } be a function defined as equal m k ( s 0 1 , s 0 2 , in 1 , . . . , in k + 1 , var )≡ val m k ( s 0 1 , in 1 , . . . , in k + 1 , var )= val m k ( s 0 2 , in 1 , . . . , in k + 1 var ). if we let o =( o 1 , . . . , o n o ) ε ( i ∪ s ∪ c ) n o denote the vector of outputs , then equal m k ( s 0 1 , s 0 2 , in 1 , . . . , in k + 1 , o j ) is true for any input sequence and any two initial states if and only if , the input sequence cannot differentiate between the initial states based on the valuation of o j . in many practical cases , a generalized notion of output equivalence is more suitable ; each output is “ guarded ” by a valid bit , which determines whether the value on that output should necessarily be deterministic . in this disclosure , it is assumed , without loss of generality , that each output signal has a valid bit ; an output signal without a valid bit can be described as an output signal with a valid bit set to the constant true ; for this purpose , val ( s , in , true )= true for any sε ε and in ε . the following generalizes the definitions of value to valid - value which takes into account the valid bit ( if invalid , value is assumed to be 0 ), and of valid - equal to be the analogue of equal . let ov =( ov 1 , . . . , ov n o ) ⊂ ( i ∪ s ∪ c ∪{ true }) n o denote the vector of the valid bits , where ov i is the valid bit of o i . let valid - value m k init × k + 1 ×( i ∪ s ∪ c ∪{ true })×( i ∪ s ∪ c )→{ true , false }× be defined as follows : let valid - equal m k : init 2 × k + 1 ×( i ∪ s ∪ c ∪{ true })×( i ∪ s ∪ c )→{ true , false } be a function such that valid - equal m k ( s 0 1 , s 0 2 , in 1 , . . . , in k + 1 , valid , var )= true if and only if valid - value m k ( s 0 1 , in 1 , . . . , in k + 1 , valid , var )= valid - value m k ( s 0 2 , in 1 , . . . , in k + 1 , valid , var ) informally , if the design starts from the initial state s 0 1 or s 0 2 and gets the input sequence in 1 , . . . , in k + 1 , the valuation of the valid bit “ valid ” should be the same , and if so the valuation of the variable “ var ” is the same as well . using this notation , a design with internal non - determinism has no asymptotically observable don &# 39 ; t - cares if valid - equal can be established for all design outputs starting at a given time frame . as defined formally in the following definition : definition 1 . a hardware design m is valid outputs consistent at ( after ) k 0 , denoted by voutput - consistent - at ( after ) ( m , k 0 ), if the following holds for k = k 0 (∀ k ≧ k 0 ): ∀ j ε { 1 , . . . , n o },∀ s 0 1 , s 0 2 εinit ,∀ in 1 , . . . , in k + 1 ε : valid - equal m k ( s 0 1 , s 0 2 , in 1 , . . . , in k + 1 , ov j , o j ) informally , a hardware design passes voutput - consistent - after ( m , k 0 ), if after getting k ≧ k 0 , inputs , the valuations of the valid bits are not affected by the initial state , and if a valid bit ov i valuation is true , the valuation of o i is not affected by the initial state . given a design m = v , init , trans and k 0 , the goal is to determine whether voutput - consistent - after ( m , k 0 ) is true . this , in turn , proves that there are not observable don &# 39 ; t - cares on the outputs starting at time frame k 0 for the given reset sequence . this goal is equally applicable for chip - level and block - level descriptions . when performing analysis at the level of the chip , and particularly for microprocessors and micro - controllers , designers are often forced to differentiate between “ good ” and “ bad ” don &# 39 ; t - cares on the outputs . for example , cpu designs are generally characterized by architectural and non - architectural elements , and a set of specification ( isa ) that defines how the processor reacts to executing programs ( i . e . their effect on the architectural elements from a programmer viewpoint ), and defines environment constrains including legal versus illegal input sequences or programs . if a microprocessor design contains an uninitialized architectural element , inconsistency will generally arise ; the executing program may read the value of an uninitialized architectural element before writing to it , and in turn introduce an x on the output that would otherwise be absent if the program is legal . this imposes restrictions on the types of don &# 39 ; t - cares that are acceptable on the outputs . for this purpose , it is suggested that the following alternative consistency criterion which takes into account the legality of the input . definition 2 . a hardware design m is legally consistent at ( starting from ) k 0 , denoted by legally - consistent - at ( after ) ( m , k 0 ), if the following holds for k = k 0 (∀ k ≧ k 0 ): ∀ j ε { 1 , . . . , n o },∀ s 0 1 , s 0 2 εinit ,∀ in 1 , . . . , in k + 1 ε : legal ( in 1 , . . . , in k + 1 ) valid - equal m k ( s 0 1 , s 0 2 , in 1 , . . . , in k + 1 , ov j , o j ) where legal : *→ boolean returns true if and only if according to the specification of the design behavior the input sequence is well defined and a valid output is expected to react to it . the function legal is usually infeasible to accurately define in a way that allows practical reasoning approaches to yield meaningful results . in the following section , a methodology is presented that allows the user to ( partially ) define the legality of an input stream either through invariants or properties imposed directly on the input stream or through imposing constraints on the design components that affect the propagation of don &# 39 ; t - cares . an efficient realization of the sequential x detection system relies on duplicating the design in order to allow simultaneous examination of different assignments to non - deterministic components , while exhaustively examining all possible combinations of the deterministic components that drive values to the circuit ( inputs and state initializations ). given a design d that is being checked for x consistency , two instances of the design d 1 and d 2 are created . across the two instances , components with deterministic values are tied , including inputs and register initialization , while allowing non - determinism for others by leaving them duplicated . a component is marked as “ safe - x ” if its corresponding components are tied together so that x originating from them are not leading to violating the consistency check . the following describes the general case where only inputs are marked as safe . with reference to fig1 , the most generic x check allows for a qualifier or valid bit , which indicates when x is allowed . for each observation point o j , with a valid bit ov j , let o 1 j , o 2 j be correspond to o j in d 1 , d 2 , and ov 1 j corresponds to ov j in d 1 then the wire o j — consistent = ov 1 j ? ( o 1 j == o 2 j ): 1 ′ b1 is used to model the function at the observation point , and the conjunction of all the wires is defined as checking that outputs_consistent = true indicates that no x is shown on the observable points . this check can be done with any model checker . methodology for approximating legal x behavior is further described below . one can use definition 1 as a first order approximation for the consistency criterion in definition 2 assuming a tautological “ legal ” function . in this case , valid - equal will generally fail and return a witness showing an x on the output ; in other words , a don &# 39 ; t - care originating from an uninitialized element and propagating to the output . diagnosing this case may determine that it is a “ good ” don &# 39 ; t - care , and as a result there is a need for fixing a bug in the design logic , or ignoring the x showing on the output , or permanently resetting the source state element and paying a certain cost of area and power . otherwise , this is a “ bad ” don &# 39 ; t - care , i . e ., a false alarm originating particularly from architectural elements . to eliminate this , the designer may decide to reset the register for verification purposes , but this may mask bugs that are otherwise present in the original design . instead , this methodology allows the user to mark the register as “ safe ” for x purposes . the methodology allows the designer to mark an x - generating register as safe , by checking whether all the outputs are consistent given that the subset s safe ⊂ s is initialized consistently to a random value . in most practical cases , choosing s safe ={ uninitialized architectural registers } will prune out “ false alarms ” in which don &# 39 ; t - care values are being propagated from free architectural elements . we will next present the formal definition for this criterion , analyze its relation to the previous criterion , and address its limitations and ways to improve upon it . definition 3 . a hardware design m is s safe safe x consistent at ( starting from ) k 0 , where s safe ⊂ s , denoted by safe - x - consistent - at ( after ) ( m , k 0 , s safe ), if the following holds for k = k 0 (∀ k ≧ k 0 ): ∀ j ε { 1 , . . . , n o },∀ s 0 1 , s 0 2 εinit ,∀ in 1 , . . . , in k + 1 ε : ua - legal ( in 1 , . . . , in k + 1 ) [ consistent ( s 0 1 , s 0 2 , s safe ) oa - legal ( in 1 , . . . , in k + 1 )] valid - equal m k ( s 0 1 , s 0 2 , in 1 , . . . , in k + 1 , ov j , o j ) where consistent is a relation such that consistent ( s 0 1 , s 0 2 , s safe ) ∀ s j εs safe : proj s ( s 0 1 , j )= proj s ( s 0 2 , j ), u a - legal is an under - approximation of the function legal ( i . e . u a - legal ⊂ legal ), and o a - legal is an over - approximation of the function legal ( i . e ., legal ⊂ o a - legal ). under - approximations are usually added by restricting inputs through constant assignment or adding assumptions on a group of inputs or design elements . over - approximations are usually specified through invariants that were previously proven for the design . with reference to fig3 , an iterative methodology is described in which the designer modifies the design to prune out the false counterexamples by initializing some uninitialized registers or marking them as safe , and tries to minimize the number of reset registers . assume that each state element s j εs has a type t i ε { free , safe , reset } and s reset εinit be the reset state . in this case s safe is equivalent to { s j εs : t j = safe }. given the vector t , and the reset state s reset εinit ( the state in which the design will be when all the registers are reset ), let apply ( m = v , init , trans , s reset , t ) be a function that applies the reset values from s reset onto the state elements . formally , apply ( m = v , init , trans , s reset , t ) returns m ′= v , init ′, trans , where init ′={ s 0 εinit |∀ j :( t j = reset ) proj s ( s 0 , j )= proj s ( s reset , j )} given over - and under - approximations of the function legal , the type of each register , and k 0 provided by the user , the design is first checked for consistency via the safe - x - consistent - after criterion applied on the design ( registers are either reset , marked as safe , or left uninitialized ). if the check fails , a counterexample is generated alongside a list of registers that are contributing to the x &# 39 ; s showing on the outputs . based on that and the knowledge about the design , the user can determine whether this is a false alarm involving illegal input or a genuine case indicating a potential bug in the design or lack of reset . the user may then update the type map and the approximations and re - iterate , or invoke an algorithm that computes a minimal set of registers whose reset can eliminate the x from the outputs , which helps in updating the type map and the approximations . the formulation of this process , which is also relevant in the case that the consistency check passes ( need to minimize the registers being reset ), is explained in the next sub - section . provided the set s safe that was created incrementally ( through interactive work with the tool ) or a - priori , and after automatically minimizing the reset subset , the user may want to diagnose the proof for false positives , or minimize the reset subset further based on the design knowledge and input legality . for each safe register s j the safe - x proof is re - run after setting t j to free , if no counterexample is found , the register s j should not be in s safe ; otherwise , the counterexample is displayed , at which point the user can update the over approximation if the counterexample is “ bad ”, or fix the design if it is a “ good ” counterexample . this methodology provides a framework for an automated safe x consistency check method . the method also allows over and under approximations to be used to constrain the design behavior . furthermore , this method enables minimizing the initialization of registers for the purpose of saving area and power , while checking that adding x as a result of non - initialization does not lead to undesired observable x . an example of implementing the third method using the x consistency check is by iteratively and exhaustively un - initializing registers that are initialized in the original circuit , and for each un - initialization combination , the x consistency check is applied . if the proof passes in a given iteration , the register ( s ) that were purposely un - initialized introduced an x that was not observable on the sample points , and thus can be left without initialization in the original circuit . in other words , the x consistency check is not only a method for validating the current initialization and lack thereof ( which introduces x ), but also improving the circuit to further introduce safe x values that save area and power . fig4 provides an overview of a computer - implemented method for verifying a hardware design in accordance with this disclosure . in an example embodiment , a hardware design description is provided at 41 for an electronic circuit using a hardware description language , such as verilog . it is readily understood that other representation of the electronic circuit are contemplated by this disclosure . a set of design elements is first extracted at 42 from the hardware design description , where the set of design elements represent the electronic circuit in terms of signals and logical operations performed on the signals . for example , design elements may include but are not limited to gates , flip - flops , etc . the set of design elements may include deterministic elements and non - deterministic elements , where a deterministic element has a value selected from zero or one and a non - deterministic element has a value denoted by a variable , such as x . for illustration purposes , a deterministic element may be an initialized register , while a non - deterministic element may be a non - initialized register . one or more sample points of the electronic circuit are then checked as indicated at 44 . referencing the notation above , voutput - consistent - after ( m , k — 0 ) can be proven with any model checker . to do so , a first set of values are assigned to each deterministic element of the electronic circuit . the electronic circuit is then checked across all possible values for the non - deterministic elements . for a given non - deterministic element , non - determinism is indicated when two values assigned to the given non - deterministic element yield different values at one or more sampling points . the process may be iterated as necessary ( e . g ., exhaustively unless prevented by constraints ) using a different set of values of the deterministic elements of the circuit . as noted above , this method is not limited to any particular type of model checker . the remainder of this disclosure describes a more efficient approach that examines non determinism on intermediate points in the design , such as state holding variables . for a given hardware design d that is being checked , two instances of the design d 1 , d 2 . . . d n , are created . for each state holding variable s j , let s 1 j , s 2 j be correspond to s j in d 1 , d 2 , then the wire s j — consistent =( s 1 j == s 2 j ) is used to indicate that the state holding variable is consistent , and the conjunction of all the wires is defined as states_consistent = j = 1 j = n o s j — consistent . algorithm 1 shows how this is done using an auxiliary method that checks states_consistent starting at a given cycle k 0 . an example of an improved implementation given in algorithm 2 borrows the concept of “ valid bits ” to state elements , such that s j — consistent = sv 1 j ? ( s 1 j == s 2 j ): 1 ′ b1 . the logic representation of the valid bits is dependent on the circuit at hand . the algorithm uses an inductive argument based on the valid bits as a way to temporally abstract the behavior of the design with respect to non - determinism in the registers . the variation given in algorithm 3 describes the case where valid bits are used in conjunction with marking registers as safe - x . definition 4 . a hardware design m is state consistent at k ′, denoted by state - consistent - at ( m , k ′), if the following holds for k = k ′: ∀ s 0 1 , s 0 2 εinit ,∀ in 1 , . . . , in k + 1 ε ,∀ jε { 1 , . . . , n s }: val m k ( s 0 1 , in 1 , . . . , in k + 1 , s j )= val m k ( s 0 2 , in 1 , . . . , in k + 1 , s j ) informally , if we start from any initial state and get any k 0 , inputs , the valuation of s will be independent of the initial state . ((∀ kε { k 0 , k 0 + 1 , . . . , k ′} voutput - consistent - at ( m , k )) state - consistent - at ( m , k ′)) voutput - consistent - after ( m , k 0 ) the following algorithm is based on assertions ( 1 ) and ( 2 ), which can be shown trivially . it attempts to find a pivotal k ′ that satisfies assertion ( 2 ). if the algorithm is unable to find such a k ′, it will attempt to prove that ∀ kε { k 0 , k 0 + 1 , . . . , k max }: voutput - consistent - at ( m , k ), where , k max is a given parameter . algorithm 1 for k ′ ← k 0 to k max if (! ( voutput - consistent - at ( m , k ′))) print “ the design is not consistent starting from k 0 ” return 0 if ( state - consistent - at ( m , k ′)) print “ the design is consistent starting from k 0 ” return 1 print “ the design is consistent ∀ k ε { k 0 , k 0 + 1 ,..., k max }”. return 2 algorithm 1 passes on two illustrative examples as will be described below . on real - life designs , however , a modified version of algorithm 1 was used in order to achieve a proof with unbounded depth . similarly to the outputs , it uses “ valid bits ” for the state - holding variables , and attempts to prove an invariant on the state - holding variables that can lead to convergence on verifying the property . note also that algorithm 1 assumed no x on inputs or wires . algorithms 2 and 3 below make no such assumptions . without loss of generality , assume that each state - holding variable has a valid bit . let sv =( sv 1 , . . . , sv ns ) ⊂ ( i ∪ s ∪ c ∪{ true }) n s denote the vector of the valid bits , where sv j is the valid bit of s j . definition 5 . a hardware design m is valid states consistent at k ′, denoted by vstate - consistent - at ( m , k ′), if the following holds for k = k ′: ∀ s 0 1 , s 0 2 εinit ,∀ in 1 , . . . , in k + 1 ε ,∀ jε { 1 , . . . , n s } valid - equal m k ( s 0 1 , s 0 2 , in 1 , . . . , in k + 1 , sv j , s j ) definition 6 . a hardware design m satisfies the valid state consistent invariant , denoted by vstate - consistent - invariant ( m ), if the following holds ∀{ circumflex over ( k )} ε : ( v state - consistent - at ( m ,{ circumflex over ( k )} )) ( v state - consistent - at ( m ,{ circumflex over ( k )} + 1 )) definition 7 . a hardware design m satisfies the unobservable x invariant , denoted by unobservable - x - invariant ( m ), if the following holds ∀{ circumflex over ( k )} ε : ( v state - consistent - at ( m ,{ circumflex over ( k )} )) ( v state - consistent - at ( m ,{ circumflex over ( k )} )) definition 8 . a hardware design m is inductively consistent , denoted by ic ( m ), if the following holds : ((∀ kε { k 0 , k 0 + 1 , . . . , k ′}: voutput - consistent - at ( m , k )) vstate - consistent - at ( m , k ′) ic ( m )) voutput - consistent - after ( m , k 0 ) the following algorithm is based on assertion ( 3 ), which can be shown trivially . it attempts to find a pivotal k ′ such that vstate - consistent - at ( m , k ′) holds . if such a k ′ is found , and ic ( m ) holds , then the design is consistent starting from k 0 . otherwise , it will attempt to prove that ∀ kε { k 0 , k 0 + 1 , . . . , k max }: voutput - consistent - at ( m , k ), where k max is a given parameter . print “ the design is not consistent starting from k 0 ” print “ the design is not consistent starting from k 0 ” print “ the design is consistent ∀ k ε { k 0 , k 0 + 1 ,..., k max ,}” without loss of generality , in what follows we will extend the previous algorithms for the cluster of designs that are “ consistently initialized ”, as defined below , for the purpose of safe - x . definition 9 . let m be a hardware design . s j is a consistently initialized state - holding variable , denoted by consistently - initialized - variable ( m , s j ) if the following holds : ∀ s 0 1 , s 0 2 εinit : proj s ( s 0 1 , j )= proj s ( s 0 2 , j ) informally , s j is a consistently initialized state - holding variable , if its valuations in all of the initial states are the same . definition 10 . let m be a hardware design . s j is a free - state holding variable , denoted by free - variable ( m , s j ), if init is closed under changes in the value of s j , formally : ∀ s 0 1 εinit ,∀ y ε j ,∃ s 0 2 εinit : proj s ( s 0 2 , j )= y ∀ lε { 1 , . . . , n s }\{ j }: proj s ( s 0 1 , l )= proj s ( s 0 2 , l ) where j , denotes the set of all possible valuations of s j . definition 11 . let m be a hardware design . m is consistently initialized , denoted by consistently - initialized ( m ), if the following holds : denote the set of all the free state - holding architectural variables of a microprocessor design cpu by . formally ={ s j εs ∩ r : free - variable ( cpu , s j )}. let denote the set of all possible valuations to the set . while reference is made to a microprocessor , it is understood that the concept described herein are not limited thereto and is applicable to any hardware design or portions thereof let the function reg - map ( cpu , fr ), where cpu = v , init , trans is a microprocessor design , and frε , return cpu ′= v , init ′, trans , where init ′={ s 0 εinit | the valuation of in s 0 is fr }. assertion 4 . safe - x - consistent - after ( cpu , k 0 ) ∀ frε : consistent - after ( reg - map ( cpu , fr ), k 0 ). the rhs of assertion 4 can be checked by applying algorithm 2 with the reg - map option of reveal for an arbitrary fr 0 ε . print “ the design is not consistent starting from k 0 ” print “ the design is consistent ∀ k ε { k 0 , k 0 + 1 ,..., k max }”. the methodology described in fig5 refines the one shown in fig3 based on algorithm 3 . the safe - x - consistent - after now results in either successfully proving the property , or failing due to two possible reasons ; failure due to a legitimate counterexample , or failure due to a negative result in the induction ( in which case reveal - seqx reports success for bounded equivalence with k max ). the rest of the flow is similar in the earlier case , while in the latter , an automatic algorithm can be used to update the valid bits . the reveal - seqx application integrates an implementation of algorithm 3 and the reveal model checker , based on the configuration in fig2 . the algorithm was run on a 64 - bit alpha processor , a 5 - stage pipeline where much of the internal state is reset . the design is intended to have a register file attached to inputs and outputs of the core , but due to the nature of the sequential x algorithm , we did not need to supply a safe - x list . the design is safe - x consistent with k 0 = 4 and an empty s safe . it also has been applied on a publicly available mips core , which is also a 5 - stage pipeline , and contains 1615 single - bit registers , with s safe consisting of the architectural memories and the registers file . the run time for these examples on a machine with intel core i7 cpu 860 at 2 . 80 ghz and 8 gb memory is seconds to show a witness for an x bug , and minutes for a full proof . the techniques described herein may be implemented by one or more computer programs executed by one or more processors . the computer programs include processor - executable instructions that are stored on a non - transitory tangible computer readable medium . the computer programs may also include stored data . non - limiting examples of the non - transitory tangible computer readable medium are nonvolatile memory , magnetic storage , and optical storage . some portions of the above description present the techniques described herein in terms of algorithms and symbolic representations of operations on information . these algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art . these operations , while described functionally or logically , are understood to be implemented by computer programs . furthermore , it has also proven convenient at times to refer to these arrangements of operations as modules or by functional names , without loss of generality . unless specifically stated otherwise as apparent from the above discussion , it is appreciated that throughout the description , discussions utilizing terms such as “ processing ” or “ computing ” or “ calculating ” or “ determining ” or “ displaying ” or the like , refer to the action and processes of a computer system , or similar electronic computing device , that manipulates and transforms data represented as physical ( electronic ) quantities within the computer system memories or registers or other such information storage , transmission or display devices . certain aspects of the described techniques include process steps and instructions described herein in the form of an algorithm . it should be noted that the described process steps and instructions could be embodied in software , firmware or hardware , and when embodied in software , could be downloaded to reside on and be operated from different platforms used by real time network operating systems . the present disclosure also relates to an apparatus for performing the operations herein . this apparatus may be specially constructed for the required purposes , or it may comprise a general - purpose computer selectively activated or reconfigured by a computer program stored on a computer readable medium that can be accessed by the computer . such a computer program may be stored in a tangible computer readable storage medium , such as , but is not limited to , any type of disk including floppy disks , optical disks , cd - roms , magnetic - optical disks , read - only memories ( roms ), random access memories ( rams ), eproms , eeproms , magnetic or optical cards , application specific integrated circuits ( asics ), or any type of media suitable for storing electronic instructions , and each coupled to a computer system bus . furthermore , the computers referred to in the specification may include a single processor or may be architectures employing multiple processor designs for increased computing capability . the algorithms and operations presented herein are not inherently related to any particular computer or other apparatus . various general - purpose systems may also be used with programs in accordance with the teachings herein , or it may prove convenient to construct more specialized apparatuses to perform the required method steps . the required structure for a variety of these systems will be apparent to those of skill in the art , along with equivalent variations . in addition , the present disclosure is not described with reference to any particular programming language . it is appreciated that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein . the present disclosure is well suited to a wide variety of computer network systems over numerous topologies . within this field , the configuration and management of large networks comprise storage devices and computers that are communicatively coupled to dissimilar computers and storage devices over a network , such as the internet . the foregoing description of the embodiments has been provided for purposes of illustration and description . it is not intended to be exhaustive or to limit the disclosure . individual elements or features of a particular embodiment are generally not limited to that particular embodiment , but , where applicable , are interchangeable and can be used in a selected embodiment , even if not specifically shown or described . the same may also be varied in many ways . such variations are not to be regarded as a departure from the disclosure , and all such modifications are intended to be included within the scope of the disclosure .