fig1 a - 1 f are cross sectional views showing manufacturing steps of a semiconductor device according to a preferred embodiment 1 of the present invention . among these manufacturing steps , first , as shown in fig1 a , locos isolation areas 2 are formed on a silicon substrate 1 through a step similar to that customarily practiced . following this , gate electrodes 3 are formed on the surface the silicon substrate 1 between the locos isolation areas 2 . side walls 4 of silicon oxide are formed at side faces of the gate electrodes . next , as shown in fig1 b , a teos ( tetra etyle ortho silicate ) layer 5 is formed by a cvd method so as to cover the surface of the silicon substrate 1 . following this , a photoresist layer is formed on the teos layer 5 and patterned , so that a resist mask 6 is formed above the locos isolation areas 2 . while the resist mask 6 is laid over the locos isolation areas 2 in this embodiment , the resist mask 6 may be wider or narrower than the locos isolation areas 2 . next , as shown in fig1 c , the teos layer 5 is selectively removed using the resist mask 6 , leaving the teos layer 5 only above the locos isolation areas 2 . the resist mask 6 is removed after this step . next , as shown in fig1 d , boron ions 7 are implanted into the silicon substrate 1 with a high acceleration energy , whereby p - type first implantation regions 8 are formed . since the boron ions 7 are implanted with high acceleration energy , the first implantation regions 8 are formed deep from the surface of the silicon substrate 1 . more specifically , the acceleration energy is 20 through 100 kev , while a concentration of the p - type impurity in the first implantation regions 8 is approximately 1 × 10 10 through 1 × 10 − 3 . the boron ions 7 entering the locos isolation areas 2 stop within the locos isolation areas 2 and do not travel beyond the locos isolation areas 2 . next , as shown in fig1 e , boron ions 9 are implanted into the silicon substrate 1 with a low acceleration energy , whereby p - type second implantation regions 10 are formed . since the boron ions 9 are implanted with low acceleration energy , the second implantation regions 10 are formed shallow from the surface of the silicon substrate 1 . more specifically , the acceleration energy for boron ions is 1 through 20 kev , the acceleration energy for bf 2 ions is 5 through 40 kev , a concentration of the p - type impurity in the second implantation regions is approximately 1 × 10 18 through 1 × 10 22 cm − 3 . through these steps , as shown in fig2 f , the gate electrodes 3 and source / drain regions which include the first and the second implantation regions 8 and 10 are formed on the silicon substrate 1 sandwiched by the locos isolation areas 2 . following this , electrodes and the like are formed by a conventional method , thereby completing a semiconductor device . executing the ion implantation steps in this manner with the teos layer 5 formed on the locos isolation areas 2 , it is possible to stop the ions implanted into said locos isolation area 2 within said locos isolation area 2 . this prevents the implanted ions from passing through the locos isolation areas 2 and forming a p - type region under the locos isolation areas 2 as in the case of the conventional manufacturing method . in consequence , it is possible to maintain an isolation breakdown voltage of the locos isolation areas high . fig2 a - 2 d are cross sectional views showing manufacturing steps of a semiconductor device according to a preferred embodiment 2 of the present invention . among these manufacturing steps , first , as shown in fig2 a , through steps similar to the conventional steps , locos isolation areas 2 and gate electrodes 3 are formed on a silicon substrate 1 . following this , a photoresist layer ( not shown ) is formed so as to cover the surface of the silicon substrate 1 . the photoresist layer is patterned by a generally used method , whereby a resist mask 16 is formed above the locos isolation areas 2 . next , as shown in fig3 b , boron ions 7 are implanted into the silicon substrate 1 with a high acceleration energy , whereby p - type first implantation regions 8 are formed . since the boron ions 7 are implanted with high acceleration energy , the first implantation regions 8 are formed deep from the surface of the silicon substrate 1 . more specifically , the acceleration energy is 20 through 100 kev , while a concentration of the p - type impurity in the first implantation regions 8 is approximately 1 × 10 10 through 1 × 10 19 cm − 3 . next , as shown in fig2 c , boron ions 9 are implanted into the silicon substrate 1 with a low acceleration energy , whereby p - type second implantation regions 10 are formed . since the boron ions 9 are implanted with low acceleration energy , the second implantation regions 10 are formed shallow from the surface of the silicon substrate 1 . more specifically , the acceleration energy for boron ions is 1 through 20 kev , the acceleration energy for bf 2 ions is 5 through 40 kev , a concentration of the p - type impurity in the second implantation regions 10 is approximately 1 × 10 18 through 1 × 10 22 cm − 3 . through these steps , as shown in fig2 d , the gate electrodes 3 and source / drain regions which include the first and the second implantation regions 8 and 10 are formed on the silicon substrate 1 sandwiched by the locos isolation areas 2 . following this , electrodes and the like are formed by a conventional method , thereby completing a semiconductor device . executing the ion implantation steps in this manner with the resist mask 16 formed on the locos isolation areas 2 , it is possible to stop the ions implanted into said locos isolation area within said locos isolation area . this prevents the implanted ions from forming a p - type region under the locos isolation areas 2 as in the case of the conventional manufacturing method and makes it possible to maintain an isolation breakdown voltage of the locos isolation areas high . fig3 a - 3 i are cross sectional views showing manufacturing steps of a semiconductor device according to a preferred embodiment 3 of the present invention . the manufacturing steps also serves as some of manufacturing steps for a flash memory . among these manufacturing steps , first , as shown in fig3 a , through a step similar to that customarily practiced , locos isolation areas 2 are formed on a silicon substrate 1 . following this , a first gate material layer 11 and an insulation film 12 are formed successively , so as to cover the silicon substrate 1 . the first gate material layer 11 is formed by polycrystalline silicon , for instance . meanwhile , the insulation film 12 is formed by silicon oxide , for example . after a photoresist layer is then formed covering the insulation film 12 , the photoresist layer is patterned , so that a resist mask 13 is formed above the locos isolation areas 2 and above a memory cell formation region . while the resist mask 13 is formed to have the same width as the locos isolation areas 2 as herein described , the resist mask 13 may be formed narrower or wider than the locos isolation areas 2 . next , as shown in fig3 b , using the resist mask 13 , the first gate material layer 11 and the insulation film 12 are selectively etched . after the etching step , the resist mask 13 is removed . next , as shown in fig3 c , a second gate material layer 14 is deposited to cover the silicon substrate 1 . the second gate material layer 14 is formed by polycrystalline silicon , for instance . following this , a photoresist layer is formed covering the second gate material layer 14 . the photoresist layer is then patterned , thereby forming a resist mask 15 . next , as shown in fig3 d , using the resist mask 15 , the second gate material layer 14 is selectively etched . the resist mask 15 is thereafter removed . as a result , a mask formed by the first gate material layer 11 and the insulation film 12 is formed on the locos isolation areas 2 . next , as shown in fig3 e , after covering a transistor region a with a photoresist layer ( not shown ), the first gate material layer 11 and the insulation film 12 are selectively etched using the second gate material layer 14 as a mask . the photoresist layer is thereafter removed . in consequence , gate electrodes 3 formed by the second gate material layer 14 is realized in the transistor region a . in a memory cell region b , a stacked layer structure is formed which includes the first gate material layer 11 , the insulation film 12 and the second gate material layer 14 . the first gate material layer 11 and the second gate material layer 14 become a floating gate and a control gate , respectively , of a flash memory . while a gate oxide film is formed between the gate electrodes 3 and the silicon substrate 1 , fig3 a through 3e omit this . next , as shown in fig3 f , side walls 4 are formed at side faces of the gate electrodes 3 within the transistor region a . at this step , side walls are formed at side faces of the stacked layer structure , too , within the memory cell region b ( not shown ). steps in fig3 f through 3i are steps related to the transistor region a , and therefore , show only the transistor region a . next , as shown in fig3 g , boron ions 7 are implanted into the silicon substrate 1 with a high acceleration energy , whereby p - type first implantation regions 8 are formed . since the boron ions 7 are implanted with high acceleration energy , the first implantation regions 8 are formed deep from the surface of the silicon substrate 1 . more specifically , the acceleration energy is 20 through 100 kev , while a concentration of the p - type impurity in the first implantation regions 8 is approximately 1 × 10 16 through 1 × 10 19 cm − 3 . next , as shown in fig3 h , boron ions 9 are implanted into the silicon substrate 1 with a low acceleration energy , whereby p - type second implantation regions 10 are formed . since the boron ions 9 are implanted with low acceleration energy , the second implantation regions 10 are formed shallow from the surface of the silicon substrate 1 . more specifically , the acceleration energy for boron ions is 1 through 20 kev , the acceleration energy for bf 2 ions is 5 through 40 kev , a concentration of the p - type impurity in the second implantation regions 10 is approximately 1 × 10 18 through 1 × 10 22 cm − 3 . through these steps , as shown in fig3 i , the gate electrodes 3 and source / drain regions which include the first and the second implantation regions 8 and 10 are formed on the silicon substrate 1 sandwiched by the locos isolation areas 2 . following this , electrodes and the like are formed by a conventional method , thereby completing a semiconductor device . executing the ion implantation steps in this manner with the mask comprised of the first gate material layer 11 and the insulation film 12 formed on the locos isolation areas 2 , it is possible to stop the ions implanted into said locos isolation area within said locos isolation area . this prevents creation of a p - type region under the locos isolation areas 2 and allows maintaining an isolation breakdown voltage of the locos isolation areas high . particularly since the mask comprised of the first gate material layer 11 and the insulation film 12 is formed through manufacturing steps for a flash memory , the mask is obtained without increasing the number of manufacturing steps . while the foregoing has described the embodiments 1 through 3 in relation to the manufacturing steps for forming the side walls 4 at the side faces of the gate electrodes 3 , the side walls 4 may not be formed . further , while the foregoing has described an example that the ion implantation step includes the first ion implantation step and the second ion implantation step , the source / drain region may be formed only through the first ion implantation step .