the embodiments set forth below represent the necessary information to enable those skilled in the art to practice the embodiments and illustrate the best mode of practicing the embodiments . upon reading the following description in light of the accompanying drawing figures , those skilled in the art will understand the concepts of the disclosure and will recognize applications of these concepts not particularly addressed herein . it should be understood that these concepts and applications fall within the scope of the disclosure and the accompanying claims . it will be understood that , although the terms first , second , etc . may be used herein to describe various elements , these elements should not be limited by these terms . these terms are only used to distinguish one element from another . for example , a first element could be termed a second element , and , similarly , a second element could be termed a first element , without departing from the scope of the present disclosure . as used herein , the term “ and / or ” includes any and all combinations of one or more of the associated listed items . the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure . as used herein , the singular forms “ a ,” “ an ,” and “ the ” are intended to include the plural forms as well , unless the context clearly indicates otherwise . it will be further understood that the terms “ comprises ,” “ comprising ,” “ includes ,” and / or “ including ” when used herein specify the presence of stated features , integers , steps , operations , elements , and / or components , but do not preclude the presence or addition of one or more other features , integers , steps , operations , elements , components , and / or groups thereof . unless otherwise defined , all terms ( including technical and scientific terms ) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs . it will be further understood that terms used herein should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein . turning now to fig3 , a schematic representation of differential power amplifier circuitry 68 is shown according to one embodiment of the present disclosure . according to this embodiment , the differential power amplifier circuitry 68 includes a differential transistor pair 70 including a first transistor tr1 and a second transistor tr2 , an input transformer 72 , an output transformer 74 , and biasing circuitry 76 . the input transformer 72 includes a primary winding 78 coupled between ground and a single - ended input terminal 80 and a secondary winding 82 coupled between a first differential output terminal 84 and a second differential output terminal 86 . the input transformer 72 is adapted to receive a single - ended input signal at the single - ended input terminal 80 and produce a differential output signal at the first differential output terminal 84 and the second differential output terminal 86 . the output transformer 74 includes a primary winding 88 coupled between a first differential input terminal 90 and a second differential input terminal 92 and a secondary winding 94 coupled between a single - ended output terminal 96 and ground . the output transformer 74 is adapted to receive a differential input signal at the first differential input terminal 90 and the second differential input terminal 92 and produce a single - ended output signal at the single - ended output terminal 96 . according to one embodiment , a supply voltage vcc is coupled at the midpoint of the primary winding 88 of the output transformer 74 . the first transistor tr1 includes a collector contact 98 , an emitter contact 100 , and a base contact 102 . the collector contact 98 of the first transistor tr1 is coupled to the first differential input terminal 90 of the output transformer 74 . the emitter contact 100 of the first transistor tr1 is coupled to ground . the base contact 102 of the first transistor tr1 is coupled to the first differential output terminal 84 of the input transformer 72 through a first coupling capacitor cb1 . the second transistor tr2 also includes a collector contact 104 , an emitter contact 106 , and a base contact 108 . the collector contact 104 of the second transistor tr2 is coupled to the second differential input terminal 92 of the output transformer 74 . the emitter contact 106 of the second transistor tr2 is coupled to ground . the base contact 108 of the second transistor tr2 is coupled to the second differential output terminal 86 of the input transformer 72 through a second coupling capacitor cb2 . the biasing circuitry is coupled to the base contact 102 of the first transistor tr1 and the base contact 108 of the second transistor tr2 . the biasing circuitry is adapted to set the quiescent operating characteristics of the differential transistor pair 70 , as will be discussed in further detail below . the differential power amplifier circuitry 68 is adapted to receive an input signal v_input at the single - ended input terminal 80 of the input transformer 72 , and produce at the single - ended output terminal 96 of the output transformer 74 an amplified output signal v_output . due to the topology of the differential power amplifier circuitry 68 , a high level of efficiency and stability can be achieved , thereby extending the battery life of a mobile device in which the differential power amplifier circuitry 68 is incorporated , as will be discussed in further detail below . according to one embodiment , the first coupling capacitor cb1 and the second coupling capacitor cb2 are designed to resonate with the secondary winding 82 of the input transformer 72 about one or more passing frequency bands . when resonant with the secondary winding 82 of the input transformer 72 , the first coupling capacitor cb1 and the second coupling capacitor cb2 form a substantially low impedance path between the secondary winding 82 of the input transformer 72 and the differential transistor pair 70 . accordingly , signals about the one or more passing frequency bands will be delivered to the differential transistor pair 70 for amplification . when not resonant with the secondary winding 82 of the input transformer 72 , the first coupling capacitor cb1 and the second coupling capacitor cb2 form a substantially high impedance path between the secondary winding 82 of the input transformer 72 and the differential transistor pair 70 . accordingly , signals outside of the one or more passing frequency bands will be blocked from reaching the differential transistor pair 70 , and will not be amplified . by designing the first coupling capacitor cb1 and the second coupling capacitor cb2 such that they are resonant with the secondary winding 82 of the input transformer 72 about one or more passing frequency bands , instability of the differential power amplifier circuitry 68 at undesirable frequency ranges can be avoided . fig4 shows the differential power amplifier circuitry 68 of fig3 including further details of the biasing circuitry 76 according to one embodiment of the present disclosure . according to this embodiment , the biasing circuitry 76 includes a biasing current source i_bias , a first diode connected transistor td1 , a second diode connected transistor td2 , a first biasing transistor tb1 , and a second biasing transistor tb2 . the first diode connected transistor td1 includes a collector contact 110 , an emitter contact 112 , and a base contact 114 . the second diode connected transistor td2 also includes a collector contact 116 , an emitter contact 118 , and a base contact 120 . the emitter contact 118 of the second diode connected transistor td2 is coupled to ground . the collector contact 116 of the second diode connected transistor td2 is coupled to the emitter contact 112 of the first diode connected transistor td1 . the collector contact 110 of the first diode connected transistor td1 is coupled to the biasing current source i_bias . the base contact 114 of the first diode connected transistor td1 and the base contact 120 of the second diode connected transistor td2 are coupled to the collector contact 110 of the first diode connected transistor td1 and the collector contact 116 of the second diode connected transistor td2 , respectively . accordingly , a first biasing voltage v — bias is generated across the first diode connected transistor td1 and the second diode connected transistor td2 . according to one embodiment , the first diode connected transistor td1 and the second diode connected transistor td2 are diodes . the first biasing transistor tb1 includes a collector contact 122 , an emitter contact 124 , and a base contact 126 . the collector contact 122 of the first biasing transistor tb1 is coupled to a battery voltage v_batt . the base contact 126 of the first biasing transistor tb1 is coupled between the collector contact 110 of the first diode connected transistor td1 and the biasing current source i_bias such that the base contact 126 of the first biasing transistor tb1 receives the first biasing voltage v_bias . the emitter contact 124 of the first biasing transistor tb1 is coupled to the base contact 102 of the first transistor tr1 through a first biasing resistor rb1 in order to deliver a first biasing current ib1 to the base contact 102 of the first transistor tr1 . the second biasing transistor tb2 also includes a collector contact 128 , an emitter contact 130 , and a base contact 132 . the collector contact 128 of the second biasing transistor tb2 is coupled to the battery voltage v_batt . the base contact 132 of the second biasing transistor tb2 is coupled to the collector contact 110 of the first diode connected transistor td1 and the biasing current source i_bias such that the base contact 132 of the second biasing transistor tb2 receives the first biasing voltage v_bias . the emitter contact 130 of the second biasing transistor tb2 is coupled to the base contact 108 of the second transistor tr2 through a second biasing resistor rb2 in order to deliver a second biasing current ib2 to the base contact 108 of the second transistor tr2 . in a quiescent state of operation , wherein no input signal v_input is present , a dc collector current ic will flow in the collector contact of the first transistor tr1 and the second transistor tr2 . the collector current ic is determined by the ratio of the respective areas of the first diode connected transistor td1 , the second diode connected transistor td2 , the first biasing transistor tb1 , the second biasing transistor tb2 , the first transistor tr1 , and the second transistor tr2 , as well as the biasing current source i_bias . for input signals v_input having a small amplitude , the operating conditions will remain substantially similar to those where no input signal v_input is present . further , the input impedance will be equal to the parallel combination of the base - emitter junction of the first transistor tr1 and the first biasing resistor rb1 , or the base - emitter junction of the second transistor tr2 and the second biasing resistor rb2 . as the amplitude of the input signal v_input increases , the differential power amplifier circuitry 68 will behave as indicated in fig5 a - 5f . the input signal v_input presented to the single - ended input terminal 80 of the input transformer 72 is split into a differential signal . the non - inverted portion of the input signal v_input is delivered through the first coupling capacitor cb1 to the base contact 102 of the first transistor tr1 . the inverted portion of the input signal v_input is delivered through the second coupling capacitor cb2 to the base contact 108 of the second transistor tr2 . during the positive half cycle of the input signal v_input shown in fig5 a , the non - inverted portion of the input signal v_input causes the voltage at the base contact 102 of the first transistor tr1 to rise , thereby increasing the collector current ic1 of the first transistor tr1 . this causes the voltage at the collector contact 98 of the first transistor tr1 to fall , as is shown in fig5 b - 1 . the increase in the voltage at the base contact 102 of the first transistor tr1 also causes an increase in the voltage at the emitter contact 124 of the first biasing transistor tb , as is shown in fig5 c - 1 . this causes the first biasing transistor tb1 to turn off , thereby lowering the first biasing current ib1 to zero , as is shown in fig5 d - 1 . additionally , this causes the first biasing transistor tb1 to present a substantially high impedance to the base contact 102 of the first transistor tr1 , as is shown in fig5 e - 1 . during the same positive half cycle of the input signal v_input shown in fig5 a , the inverting portion of the input signal v_input causes the voltage at the base contact 108 of the second transistor tr2 to fall , thereby turning off the second transistor tr2 and essentially lowering the collector current ic2 of the second transistor tr2 to zero . this causes the voltage at the collector contact 104 of the second transistor tr2 to rise , as shown in fig5 b - 2 . the decrease in the voltage at the base contact 108 of the second transistor tr2 also causes a decrease in the voltage at the emitter contact 130 of the second biasing transistor tb2 , as shown in fig5 c - 2 . this causes the second biasing transistor tb2 to pass more current , thereby increasing the second biasing current ib2 , as shown in fig5 d - 2 . additionally , this causes the second biasing transistor tb2 to present a substantially low impedance to the base contact 108 of the second transistor tr2 , as is shown in fig5 e - 2 . because the second transistor tr2 is in an off state , the current flows into and charges the second coupling capacitor cb2 . during the negative half cycle of the input signal v_input shown in fig5 a , the first transistor tr1 will behave in a substantially similar manner to the second transistor tr2 , and vice versa . fig5 f shows the input impedance of the differential power amplifier circuitry 68 during both the positive and negative half cycle of the input signal v_input . as is shown , the input impedance of the differential power amplifier circuitry 68 at high drive levels is about equal to the base - emitter impedance of the first transistor tr1 and the second transistor tr2 . this is greater than the input impedance seen at low drive levels of the input signal v_input , where the input impedance is equal to the base - emitter impedance of the first transistor tr1 in parallel with the first biasing resistor rb1 and the base - emitter impedance of the second transistor tr2 in parallel with the biasing resistor rb2 . thus , it is shown that the input impedance increases with the drive level of the input signal v_input . the relationship of the input impedance to the drive level of the input signal v_input minimizes the effect of net gain decreases as the drive level increases ( due to effects such as compression , where the output voltage becomes limited by the supply voltage vcc ). accordingly , the differential power amplifier circuitry 68 may operate at higher power levels without losing linearity . further , the biasing current requirements of the circuitry may be reduced while maintaining the same linearity at a given maximum output power level , thereby saving power in a mobile device in which the differential power amplifier circuitry 68 is incorporated . fig6 shows the differential power amplifier circuitry 68 of fig3 including further details of the biasing circuitry 76 according to one embodiment of the present disclosure . according to this embodiment , the biasing circuitry 76 includes a first biasing current source i_bias1 , a second biasing current source i_bias2 , a first diode connected transistor td1 , a second diode connected transistor td2 , a third diode connected transistor td3 , a fourth diode connected transistor td4 , a first biasing transistor tb1 , and a second biasing transistor tb2 . the first diode connected transistor td1 includes a collector contact 134 , an emitter contact 136 , and a base contact 138 . the second diode connected transistor td2 also includes a collector contact 140 , and emitter contact 142 , and a base contact 144 . the emitter contact 142 of the second diode connected transistor td2 is coupled to ground . the collector contact 140 of the second diode connected transistor td2 is coupled to the emitter contact 136 of the first diode connected transistor td1 . the collector contact 134 of the first diode connected transistor td1 is coupled to the first biasing current source i_bias1 . the base contact 138 of the first diode connected transistor td1 and the base contact 144 of the second diode connected transistor td2 are coupled to the collector contact 134 of the first diode connected transistor td1 and the collector contact 140 of the second diode connected transistor td2 , respectively . accordingly , a first biasing voltage v_bias1 is generated across the first diode connected transistor td1 and the second diode connected transistor td2 . similarly , the third diode connected transistor td3 includes a collector contact 146 , an emitter contact 148 , and a base contact 150 . the fourth diode connected transistor td4 also includes a collector contact 152 , an emitter contact 154 , and a base contact 156 . the emitter contact 154 of the fourth diode connected transistor td4 is coupled to ground . the collector contact 152 of the fourth diode connected transistor td4 is coupled to the emitter contact 148 of the third diode connected transistor td3 . the collector contact 146 of the third diode connected transistor td3 is coupled to the second biasing current source i_bias2 . the base contact 150 of the third diode connected transistor td3 and the base contact 156 of the fourth diode connected transistor td4 are coupled to the collector contact 146 of the third diode connected transistor td3 and the collector contact 152 of the fourth diode connected transistor td4 , respectively . accordingly , a second biasing voltage v_bias2 is generated across the third diode connected transistor td3 and the fourth diode connected transistor td4 . the first biasing transistor tb1 includes a collector contact 158 , an emitter contact 160 , and a base contact 162 . the collector contact 158 of the first biasing transistor tb1 is coupled to a battery voltage v_batt . the base contact 162 of the first biasing transistor tb1 is coupled between the collector contact 134 of the first diode connected transistor td1 and the first biasing current source i_bias1 such that the base contact 162 of the first biasing transistor tb1 receives the first biasing voltage v_bias1 . the emitter contact 160 of the first biasing transistor tb1 is coupled to the base contact 102 of the first transistor tr1 through a first biasing resistor rb1 in order to deliver a first biasing current ib1 to the first transistor tr1 . the second biasing transistor tb2 includes a collector contact 164 , an emitter contact 166 , and a base contact 168 . the collector contact 164 of the second biasing transistor tb2 is coupled to a battery voltage v_batt . the base contact 168 of the second biasing transistor tb2 is coupled between the collector contact 146 of the third diode connected transistor td3 and the second biasing current source i_bias2 such that the base contact 168 of the second biasing transistor tb2 receives the second biasing voltage v_bias2 . the emitter contact 166 of the second biasing transistor tb2 is coupled to the base contact 108 of the second transistor tr2 through a second biasing resistor rb2 in order to deliver a second biasing current ib2 to the second transistor tr2 . in a quiescent state of operation , wherein no input signal v_input is present , a dc collector current ic will flow in the collector contact of the first transistor tr1 and the second transistor tr2 . the collector current ic is determined by the ratio of the respective areas of the first diode connected transistor td1 , the second diode connected transistor td2 , the third diode connected transistor td3 , the fourth diode connected transistor td4 , the first biasing transistor tb1 , the second biasing transistor tb2 , the first transistor tr1 , and the second transistor tr2 , as well as the first biasing current source i_bias1 and the second biasing current source i_bias2 . for input signals v_input having a small amplitude , these conditions will remain substantially similar . as the amplitude of the input signal v_input increases , the differential power amplifier circuitry 68 will behave as indicated in fig5 a - 5f , as described above . once again , due to the input impedance characteristics of the differential power amplifier circuitry 68 , the effects of net gain decreases as the drive level of the input signal v_input increases ( due to effects such as compression , where the output voltage becomes limited by the supply voltage vcc ) are reduced . accordingly , the differential power amplifier circuitry 68 may operate at higher power levels without losing linearity . further , the biasing current requirements of the circuitry may be reduced while maintaining the same linearity at a given maximum output power level , thereby saving power in a mobile device in which the differential power amplifier circuitry 68 is incorporated . those skilled in the art will recognize improvements and modifications to the preferred embodiments of the present disclosure . all such improvements and modifications are considered within the scope of the concepts disclosed herein and the claims that follow .