a memory connected state detecting circuit for automatically detecting the memory connected condition , comprising a timing circuit responsive to a certain operation mode signal and a clock signal for producing different timing and control signals and address information , a switching circuit for controlling the read / write operations in such a manner that each data for checking is written in each of designated addresses and it is read just after it has been written , and a latching circuit for latching the data read from the memory . with this construction , it has become possible to detect whether or not the memory capacity of an additional memory or memories mounted can sufficiently cover the memory area designated by a computer , without providing any mechanical switches and associated wiring .