a delay optimization algorithm has four major steps : selecting signal connections to target for delay improvement ; unrouting all signals containing those candidate connections ; rerouting those signals , using a “ load - balancing ” heuristic ; and during rip - up and re - try routing , protecting wiring to all signal loads routed by the heuristic , including non - timing critical loads . load balancing includes applying a branching penalty on logic cell output wire segments , and encouraging all non - route critical loads to route through a single buffered wire segment .