ramping voltage circuits are described for augmenting or supplying a higher power - up slope upon initial power - up or a wake - up transition from a period of dormancy to a semiconductor memory device . such ramping voltage circuits are responsive to a power - up signal , and are capable of increasing by at least two orders of magnitude the power - up slope , thereby enabling far quicker device turn - on . in one embodiment , a level shifter is used to ramp up the power - on voltage . in another embodiment , the internal voltage line is effectively shorted to an external voltage line via a power - up turned - on pmos or depletion - type nmos transistor .