there is disclosed a digital loop circuit for controlling synchronization around a closed loop communication system . the control circuit is designed to automatically adjust the delay of the loop to maintain a constant frame bit length without regard to the number of stations connected into the loop . as stations are added or subtracted from the loop , the system operates to add or subtract delay as necessary . a fifo register having a bit capacity equal to the frame size is inserted serially in the loop and a separate clock is used to control the input and the output of the fifo register . if a unique frame bit is not received in the anticipated position the output fifo clock skips one count per frame thereby adding delay to the loop . the loop control circuit operates for situations where the framing bit is on a separate channel and also when the framing bit is on the actual data channel .