an effective - to - real address translation cache management apparatus and method utilizes an effective - to - real address translation cache segment register latch having a bit corresponding to each of the segment registers . when a segment register is utilized to perform an effective - to - real address translation , which is stored in the effective - to - real address translation cache , the corresponding bit in the effective - to - real address translation cache segment register latch is set . in this way , a record is kept of which segment registers are currently mapped in the effective - to - real address translation cache . when a move to segment register instruction alters the content of a segment register , then the effective - to - real address translation cache segment register latch is examined to determine if that segment register has been mapped in the effective - to - real address translation cache . if so , then an effective - to - real address translation cache invalidation latch is set . otherwise , the move to segment register has no effect on the effective - to - real address translation cache . when a context synchronizing event occurs , the effective - to - real address translation cache invalidation latch is examined to determine whether or not to invalidate the effective - to - real address translation cache . in this way , the frequency of effective - to - real address translation cache invalidation may be reduced thereby increasing processor efficiency .