a semiconductor memory device having a unit memory cell consisting of , a ferroelectric capacitor having a first and second electrodes , and an access transistor connected to the first electrode of the capacitor and to the bit line , is disclosed . an imprint compensation circuit for applying a predetermined voltage to the first electrode through the write path of the memory device , or for applying a signal in the form of pulse to the second electrode , where data access of the memory device is prohibited , in order to imprint the ferroelectric capacitor in first and second directions from the reference point , creating a normal polarization characteristic .