a computer architecture that incorporates display memory into system memory is disclosed , which comprises a memory , a memory controller and a display controller . both of the memory controller and the display controller are employed to control access of the memory device having system data and display data stored therein . built - in signals and an arbiter are provided between the controllers to arbitrate the priorities of the two controllers to access the memory device . furthermore , request and grant signals are used to initiate the refresh of the main memory to maintain data therein . the control circuits of the two controllers to the memory device are connected to each other to prevent signals contention .