a bus driver circuit divides an internal data bus for an integrated circuit memory into at least two groups , designated by speed . a faster group of data lines and a slower group of data lines are placed in an interleaved fashion in order to provide a two group shielding solution . at the earliest opportunity following the reception of a read command , the data from memory banks in the memory is sorted into these two groups . for a ddr3 memory , the sorting method is based on the a2 column address , known as c2 . all of the data is brought out of the banks in parallel and sorted as it enters the main amplifiers . these main amplifiers are also divided into two groups , faster and slower . each amplifier then connects to a data line of the same group . the clock assigned to the fast group fires right away , thereby connecting the data associated with the fast amplifiers to the fast data group . this data group then proceeds to the output buffers through the entire data path as fast as possible . the second , slower data group is started with a delayed clock signal and proceeds through the data path to the output buffer maintaining a fixed delay . since the first and second data groups are not switching at the same time they act as shields to one another .