digital communications devices having high - speed add - compare - select circuits , and methods for designing the same . the add - compare - select circuits include logic segments separated by delay devices . the separation of the logic segments allows for pipelining of the add - compare - select processes and advantageous circuit retiming . the pipelining and advantageous circuit retiming permit the digital communications devices to be clocked at higher rates than similar digital communications devices having conventional add - compare - select circuits .