a direct memory access control system supplies the respective status signals indicating timings of the read data effective state or writable state between the input / output interface and memory interface , both interfaces maintain the read data effective state and writable state of the input / output memory and synchronous memory under control until the later timing comes up . consequently , it is possible to match the read data effective timing and writable timing of the synchronous memory and input / output memory , thus making possible flyby transfer of data between both memories .