a prefetch controller implements an upgrade when a real read access request hits the same memory bank and memory address as a previous prefetch request . in response per - memory bank logic promotes the priority of the prefetch request to that of a read request . if the prefetch request is still waiting to win arbitration , this upgrade in priority increases the likelihood of gaining access generally reducing the latency . if the prefetch request had already gained access through arbitration , the upgrade has no effect . this thus generally reduces the latency in completion of a high priority real request when a low priority speculative prefetch was made to the same address .