a digital logic circuit is provided for multiplying , such as doubling , the frequency of an input clock pulse sequence of period t . the circuit in one embodiment includes complementarily clocked first and second chains of cascaded delay elements . further , the n &# 39 ; th one of set of clocked latches derives its input from the 2n &# 39 ; th one of the delay elements in the first chain , where n is a running integer index . the circuit also includes a set of two - input logic gates , one of whose inputs is the output of a separate one of the logic elements in the second chain and the other of whose inputs is an output of a separate one of the latches . each of the outputs of these logic gates is fed to a multiple input output logic gate whose output has a desired double - frequency feature relative to the frequency of the clocked pulse sequence .