a process is provided for producing active and passive devices on various levels of a semiconductor topography . as such , the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed . the multi - level fabrication process not only adds to the overall circuit density , but does so with emphasis placed on high performance interconnection between devices on separate levels . the interconnect configuration is made as short as possible between features within one transistor level to features within another transistor level . this interconnect scheme lowers resistivity by forming a gate conductor of an upper level transistor upon a gate conductor of a lower level transistor . alternatively , the gate conductors can be a single conductive entity . in order to abut the gate conductors together , or form a single gate conductor , the upper level transistor is inverted relative to the lower level transistor . in addition to the inverted , shared gate conductor , the multi - level transistor fabrication process incorporates formation of openings and filling of those openings to produce interconnect to junctions of the upper / lower transistors . interconnecting the gate conductors of a pair of stacked transistors and connecting specific junctions of those transistors allow development of a high density nor gate . the nor gate includes two pairs of stacked transistors , wherein one transistor of a pair can be connected to the other transistor of that pair or connected to one or both transistors of the other pair .