a software product including codes for the method of determining parasitic resistance and capacitance from a layout of an lsi is executed by a computer . the method is achieved by providing a plurality of patterns of a wiring structure which contains a target interconnection ; and by producing a library configured to store parameters indicating the parasitic resistance and the parasitic capacitance in relation to the target interconnection to each of the plurality of patterns . the producing is achieved by calculating the parameters to a plurality of conditions corresponding to deviation in manufacture of the wiring structure for each of the plurality of patterns .