an integrated circuit handling , packaging and testing apparatus in the form of a testable chip carrier comprising a rigid substrate onto which a chip may be bonded , and which provides a high density interconnect pattern orthogonally aligned to the chip bond pads for wire bonding thereto . the interconnect also provides external bonding points patterned for similar orthogonal alignment to the external device to which the chip is to be connected , and the dimensions of the carrier are substantially smaller than an equivalent standard or custom package type . a hermetic or non - hermetic seal lidding operation may be carried out on the chip and carrier . the carrier also provides a detachable test perimeter allowing full - functional testing and burn - in of the attached wire - bonded chip prior to placement on a printed circuit board or multi - chip module . signal integrity is improved by the exact alignment of the carrier - to - chip and carrier - to - external device connections , and manufacturing techniques allow for the use of optimum interconnect materials , multi - layer structures and the addition of passive components external to the chip . the carriers may be integrated with heatsinks .