the present application discloses a method for manufacturing a gate - all - around field effect transistor , comprising the steps of forming a suspended fin in a semiconductor substrate ; forming a gate stack around the fin ; and forming source / drain regions in the fin on both sides of the gate stack , wherein an isolation dielectric layer is formed in a portion of the semiconductor substrate which is adjacent to bottom of both the fin and the gate stack . the present invention relates to a method for manufacturing a gate - all - around device on a bulk silicon substrate , which suppress a self - heating effect and a floating - body effect of the soi substrate , and lower a manufacture cost . the inventive method is a conventional top - down process with respect to a reference plane , which can be implemented as a simple manufacture process , and is easy to be integrated into and compatible with a planar cmos process . the inventive method suppresses a short channel effect and promotes miniaturization of mosfets .