a flash memory cell formed in a semiconductor substrate is disclosed . the cell includes an n - well formed within the substrate . next , a p + drain region is formed within the n - well . a floating gate is formed above the n - well being separated from the substrate by a thin oxide layer . the floating gate is formed adjacent to the p + drain region . finally , a control gate is formed above the floating gate , the floating gate and the control gate being separated by a dielectric layer . the new cell is read by measuring the gidl current at p +/ n - well junction , which is exponentially modulated by the floating gate potential . the new cell is programmed by band - to - band hot electron injection and is erased by f - n tunneling through the overlap area of floating gate and n - well .