techniques are provided for implementing freeze logic on programmable logic blocks . the output signal of a register in each programmable logic block is driven to a predefined state in response to a freeze signal . the freeze signal also causes a multiplexer in each programmable logic block to select the output signal of the register . the multiplexer drives an output signal of the programmable logic block to a predefined state to eliminate contention between circuit elements . the freeze logic requires a small amount of area in each programmable logic block .