hardware and / or software countermeasures are provided to reduce or eliminate vulnerabilities due to the observable and / or predictable states and state transitions of microprocessor components such as instruction cache , data cache , branch prediction unit , branch target buffer and other components . for example , for branch prediction units , various hardware and / or software countermeasures are provided to reduce vulnerabilities in the branch prediction unit and to protect against the security vulnerabilities due the observable and / or predictable states and state transitions during bpu operations .