a circuit for generating a timing signal , the circuit having a memory and a pulse generator , the timing signal consisting of a number of pulses . the memory stores pulse count data , including an indication of the number of pulses in the timing signal , and rising edge and falling edge position data of the timing signal . the pulse generator produces the timing signal in accordance with the pulse count data and has a first circuit for generating rising edge signals , a second circuit for generating falling edge signals , an active control circuit for setting , in correspondence only with the pulse count data , corresponding rising edge signals as active state rising edge signals , and corresponding falling edge signals as active state falling edge signals , and a third circuit for generating said timing signal corresponding to the active state rising edge signals and the active state falling edge signals .