in some implementations , a memory controller is configured receive a data word to be stored in the memory , generate error checking and correcting information for the data word , the data word and ecc information forming an encoded word , and distribute bits of the encoded word across the plurality of concurrently accessible memory devices in accordance with one or more indications specifying a number of the bits of the encoded word to store in a wordline of each of the plurality of concurrently accessible memory devices , wherein bits of the data word are to be stored in two or more memory devices of the plurality of memory devices , and bits of the ecc information are to be stored in two or more memory devices of the plurality of memory devices .