according to an aspect of the invention , a device structure is provided where charging and discharging occur in a trapping region formed by a stack of films that is placed on the back of a thin silicon channel . uncoupling the charging mechanisms that lead to the memory function from the front gate transistor operation allows efficient scaling of the front gate . but significantly more important is a unique character of these devices : these structures can be operated both as a transistor and as a memory . the thin active silicon channel and the thin front oxide provide the capability of scaling the structure to tens of nanometers , and the dual function of the device is obtained by using two voltage ranges that are clearly distinct . at small voltages the structure operates as a normal transistor , and at higher voltages the structure operates as a memory device .