a method for making an improved electrically programmable read - only - memory device having non - volatile memory cells with enhanced capacitive coupling was achieved . the array of memory cells consists of a single field effect transistor having an additional floating gate . the fet is formed in a well etched into an insulating layer on the substrate surface . after forming the fet gate oxide , a polysilicon layer is patterned to form a trench - like floating gate with increased capacitive coupling . an interlevel dielectric layer is deposited . a second poly - silicon layer is deposited in the well and chem / mech polished back to form the control gate . the insulating layer having the wells is selectively removed . lightly doped source / drain areas , self - aligned to the fet gate electrodes , are implanted and after forming sidewall spacers on the gate electrodes , source / drain contacts and buried bit lines are formed by a second implant . an insulating layer is deposited over the array of fets having contact openings to the fet control gates . another polysilicon layer is deposited and patterned to form the word lines . the word lines and buried bit lines are connected to the peripheral circuits to complete the eprom chip .