a memory device includes a base memory with a defective memory cell . a read circuit with a serial output port and parallel input ports is connected to the base memory . the read circuit converts parallel read data received at the parallel input ports to a first serial data stream , which is applied to the serial output port . the first serial data stream includes a faulty bit corresponding to the defective memory cell . a spare memory stores a spare bit corresponding to the defective memory cell . a bit insertion circuit is connected to the spare memory and the serial output port of the read circuit . the bit insertion circuit substitutes the faulty bit value of the first serial data stream with the spare bit .