ceramic packages for encapsulating integrated circuit chips are made of layers which are laminated together in a co - firing process . a signal layer includes leads electrically connecting external pins with the chip itself . other layers supply ground and power to the chip by way of the signal layer . the layers are designed so that when a new chip is to be introduced , only one layer of the package , called a &# 34 ; via layer ,&# 34 ; needs to be re - designed for the new chip . the via layer is programmed with connections or &# 34 ; vias &# 34 ; at specific locations between the signal layer and a power or ground layer above or below the signal layer . the &# 34 ; vias &# 34 ; are conductive dots that extend through the via layer . the layer opposite the signal layer on the other side of the via layer contains &# 34 ; internal supply and ground bars &# 34 ; that are electrically connected to internal supply and ground layers . therefore , selective positioning of the vias enables each signal lead in the signal layer to be selectively connected to internal power or ground . the internal supply and ground bars are aligned transversely with respect to the signal lead , and are close to the chip to minimize the inductance of the connections . for custom chip designs , the programmed via layer enables certain bonding areas to be preassigned to power and ground while permitting the circuit designer to freely select the assignment of the external pins .