a chip package having an array of leads , wherein successive leads are staggered in all three dimensions relative to one another . such a staggered arrangement permits a large number of leads available in a confined space while maintaining the minimum separation necessary between adjacent leads . the leads are formed by placing asymmetric top and bottom masks on a lead frame , and partially etching the top of the lead frame , while partially and over etching the bottom of the lead frame . although the resulting leads are staggering in three dimensions , no additional processing steps are needed beyond those used to fabricate conventional packages .