one embodiment of the present invention provides a system that facilitates reducing static power consumption of a processor . during operation , the system receives a signal indicating that instruction execution within the processor is to be temporarily halted . in response to this signal , the system halts an instruction - processing portion of the processor , and reduces the voltage supplied to the instruction - processing portion of the processor . full voltage is maintained to a remaining portion of the processor , so that the remaining portion of the processor can continue to operate while the instruction - processing portion of the processor is in reduced power mode .