to fabricate a semiconductor memory , one or more pairs of first structures are formed over a semiconductor substrate . each first structure comprises a plurality of floating gates of memory cells and a first conductive line providing control gates for the memory cells . the control gates overlie the floating gates . each pair of the first structures corresponds to a plurality of doped regions each of which provides a source / drain region to a memory cell having the floating and control gates in one or the structure and a source / drain region to a memory cell having floating and control gates in the other one of the structures . for each pair , a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions . in some embodiments , the first doped regions are separated by insulation trenches . the second conductive line may form a conductive plug at least partially filling the region between the two first structures .