systems and methods for enabling on - chip features via efuses . a system comprises an electronic fuse array coupled to each features capability register within an instantiated computational block . the efa comprises a plurality of rows wherein programming an row comprises blowing one or more efuses of the row . a valid row comprises programmed efuses corresponding to one or more on - chip enabled features . the efa is further configured to prevent enabling of disabled on - chip features from occurring subsequent to a predetermined point in time , such as the time of shipping the chip to the field for use by end - users , by establishing a particular default state for electronic fuses and rendering unusable any unprogrammed entries of the efa . in one embodiment , some features correspond to on - chip hardware cryptographic acceleration . by preventing the ability to re - enable these features after shipping , it is possible to send semiconductor chips to foreign countries with only predetermined features enabled and no threat of disabled features being later enabled .