a method and apparatus for visually inspecting and sorting semiconductor wafers and the individual microcircuits or chips thereon . the preferred embodiment employs a scanner to obtain a virtual reality image of the wafer and all chips are identified and sorted by applying high - speed image processing routines . the resulting wafer map provides unique image controlled chip coordinates making the chips identifiable even after the chips are diced apart . the wafer may contain different kinds of chips in irregular patterns . a gross - defect , visual inspection sorts out defective chips based on image completeness maximizing the yield and throughput . all inspections and identifications are performed on the virtual wafer or chip images scanned into a computer memory with full physical wafer correlation but without having to manipulate the wafer . the inspection time is , therefore , largely free due to overlapping it by regular transport operations .