a dual mode regulator , having a high current pwm regulator mode and a low current ldo regulator mode , briefly changes the operating parameters of the pwm and ldo regulators during a transition between modes . changes during the transition period include : raising the error amplifier reference voltage of the ldo or pwm regulator to ensure a definite handover , raising the bias current in the ldo stages during the transition to cause the ldo regulator to quickly and stably respond to voltage glitches , and augmenting the ldo regulator series pass transistors with one or more additional pass transistors during the transition to enable the ldo regulator to handle higher currents . after the transition , the operating parameters of the enabled regulator portion are reset to their nominal values . the pwm regulator is started with a soft start routine to limit current through the power transistor . if the pwm regulator uses a synchronous rectifier , a reverse current limiting circuit is preferably used to limit reverse current when the pwm regulator is starting up to avoid loading down the ldo regulator .