integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines , a sense amplifier and a plate / bit line selection switch , coupled to the plurality of bit lines , for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line , in response to a column select signal . the inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations . the reference cell array also preferably comprises a plurality of ferroelectric reference cells which each comprise first and second access transistors therein and first and second ferroelectric capacitors therein which store complementary states . during a reading operation , the complementary data stored in the first and second ferroelectric reference capacitors is simultaneously provided to a portion of a first bit line which is electrically connected to a second input of a sense amplifier . data in a memory cell within the array is also provided to another portion of the first bit line which is electrically connected to a first input of the sense amplifier . the sense amplifier is then activated to amplify a difference in potential between the different portions of the first bit line as complementary signals and then the signals are provided as output data .