a memory cell of the type employing a pair of cross - coupled cmos inverters of a sram is disclosed in which the load misfets are stacked above the semiconductor substrate and over the drive misfets . each load misfet of a memory cell consists of a source , drain and channel region formed of a semiconductor strip , such as a polycrystalline silicon film strip , and a gate electrode consisting of a different layer conductive film than that of the drive misfets . in a memory cell having such a stacked arrangement , the source region and gate electrode of each load misfet thereof are patterned to have a widely overlapping relationship with each other to form a capacitor element thereacross such that an increase in the overall capacitance associated with each of the memory cell storage nodes is effected thereby decreasing occurrence of soft error . the overlapping relationship for effecting the large capacitor element across the source and gate of the respective load misfets is provided by an ion implanting scheme of a p - type impurity into the semiconductor strip . a separate mask for ion - implantation for the formation of the source region of the load misfet is added followed by the addition of the gate electrode thereof in a manner so as to have a widely overlapping relationship with that of the source region .