a memory cell having n transistors including at least one pair of access transistors , one pair of pull - down transistors , and one pair of pull - up transistors to form a memory cell , wherein n is an integer at least equal to six , wherein each of the access transistors and each of the pull - down transistors is a same one of an n - type or a p - type transistor , and each of the pull - up transistors is the other of an n - type or a p - type transistor , wherein at least one of the pair of the pull down transistors and the pair of the pull up transistors are asymmetric .