an instruction processor suitable for use in a reduced instruction - set computer employs an instruction pipeline which performs conditional branching in a single processor cycle . the processor treats a branch condition as a normal instruction operand rather than a special case within a separate condition code register . the condition bit and the branch target address determine which instruction is to be fetched , the branch not taking effect until the next - following instruction is executed . in this manner , no replacement of the instruction which physically follows the branch instruction in the pipeline need be made , and the branch occurs within the single cycle of the pipeline allocated to it . a simple circuit implements this delayed - branch method . a computer incorporating the processor readily executes special - handling techniques for calls on subroutine , interrupts and traps .