to provide a variable dividing circuit having a high operational speed . the variable dividing circuit includes a shift register configured by cascade connection of d - type flip - flops with an initializing means by clock synchronization ; and a multiplexer 12 for selecting any one of output signals at respective stages of the shift register ; wherein the variable dividing circuit initializes each stage of the d - type flip - flops . in this case , in an input terminal 10 of the flip - flop at the first stage , a signal at an h level or at an l level is inputted in accordance with an initializing means .