a power gated semiconductor integrated circuit comprises : logic circuit to be power gated , said logic circuit having a virtual ground rail ; footer device disposed between said virtual ground rail and a ground rail for reducing power consumption of said logic circuit ; and virtual rail voltage clamp disposed electrically in parallel with said footer device for limiting the voltage at the virtual ground rail , the virtual rail voltage clamp comprising at least one nfet . a total of n f nfets are connected to the virtual ground rail of the integrated circuit for use as both virtual rail voltage clamps and footer devices . a quantity of n max - vc nfets are scanned and perform the function of voltage clamps and the remaining nfets perform power gating . manufacturing variability immunity and tuning of the variability immunity is achieved by adjusting the quantity n max - vc based upon testing of the manufactured integrated circuit .