a discharge circuit for a semiconductor memory includes a first node , a second node for receiving a control signal having first and second states , and a circuit connected between the first node and ground potential and to the second node . the circuit couples the first node to ground potential when the control signal has the first state and substantially isolates the first node from ground potential when the control signal has the second state . the circuit includes a first subcircuit for defining a current path between the first node and ground potential . the first subcircuit includes a plurality of transistors connected in series , each of which having a gate , source and drain . the circuit further includes a second subcircuit for effecting predetermined gate - to - source , and drain - to - source voltages of the transistors of the first subcircuit when the control signal has the second state .