a method implemented in hardware to concurrently obtain memory access locality information for a large number of contiguous sections of system memory for the purposes of optimizing memory and process assignments in a multiple - node numa architecture computer system including a distributed system memory . page access monitoring logic is included within each processing node which contains a portion of shared system memory . this page access monitoring logic maintains a plurality of page access counters , each page access counter corresponding to a different memory page address within the shared system memory . whenever the processing node generates a transaction requiring access to a memory address within system memory , the page access monitoring logic increments a count value contained within the page access counter corresponding to the memory address to which access is sought . each processing node further includes page access counter search logic connected to the plurality of page access counters , which is enabled upon completion of page access monitoring , for sequentially comparing the contents of each page access counter with a predetermined minimum count value to identify the page access counters having contents equal to or greater than the minimum count value , and to identify the memory page addresses associated with the page access counters having contents equal to or greater than the minimum count value . this information can thereafter be used to optimize memory and process assignments in the computer system .