the invention includes a method of and an apparatus for testing an integrated circuit which includes simulating the integrated circuit and generating an input vector to and expected output from the integrated circuit . this input vector and expected output are generated by entering test vectors into the circuit simulator and the integrated circuit is tested using the input vector to yield a first resulting output . a test hardware vector is also created to capture state information pertaining to the integrated circuit . the test hardware vector and the input vector are combined to create a joint input vector and debugging is performed on the integrated circuit by modifying the joint input vector and evaluating the resulting output .