source and drain regions of an fet are etched by a crystallographic anisotropic etch to form a cavity surrounded by crystallographic facets . the exposure of the sidewalls of shallow trench isolation is avoided or reduced compared to the prior art . the crystallographic anisotropic etch may be combined with an isotropic etch or a recess etch to create undercuts beneath gate spacers and / or a pegging line beneath a top surface of the sti . the at least one cavity is then filled with a lattice - mismatched embedded material so that stress is applied to the channel of the fet . the resulting structure has increased containment of the embedded semiconductor region by shallow trench isolation . a reduction in stress due to the unconstrained sidewall area and an increase in the junction current due to the recessing of the pegging line are eliminated or alleviated .