the storage space of the instant system is considered , for refresh purposes , to contain 512 groups of 26 bit digital words with each group containing 128 such words . memory refresh is implemented by sequentially refreshing the groups of digital words at the rate of one group every 2 . 8 microseconds , giving an expected total memory refresh time of approximately 1 . 43 milliseconds . a particular digital word from each group of digital words refreshed is read from the memory and transmitted to a parity check circuit which generates fault signals for any digital word having faulty parity . at the end of each of the approximately 1 . 43 millisecond refresh cycles , the particular word read from each group refreshed is changed so that at the end of 128 full refresh cycles , the parity of every digital word in the memory has been checked . further , circuitry is provided to store the location of the first failing digital word in a trap register in response to an indication of faulty parity .