a spare logic circuit for implementing any one of a plurality of logic gates includes a multiplexer circuit whose select inputs are utilized as logic gate inputs , and whose output is utilized as a logic gate output . each of a plurality of data inputs of the multiplexer circuit is configured to receive one of first and second logic voltage levels which define the desired logic function . by modifying a single photolithographic mask , the spare logic gate can be : configured to perform the desired logic function ; connected into a target logic circuit ; or both configured and connected into a target logic circuit .