a processor of processes data using a cache circuit . the processor is coupled to a functionally detachable device via the cache circuit . when a cache line is loaded into cache memory , it is tested whether the cache line has an address within a detachable device address range allocated to the detachable device . if so , identification of the cache line , or a range of addresses that includes the address of the cache line is stored . when a flush command is received that requires write back cached data to the detachable device , the identification is used to select the cache line for selective write back to the detachable device . thus less cache data needs to be invalidated when a device is functionally detached from the circuit .