in an integrated circuit fabrication sequence , a relatively thick sacrificial layer is deposited on a nonplanar surface of a device wafer in which high - resolution features are to be defined . the thick layer is characterized by a conforming lower surface and an essentially planar top surface and by the capability of being patterned in a high - resolution way . an intermediate masking layer and then a thin resist layer are deposited on the top surface of the sacrificial layer , the thickness of the resist layer being insufficient by itself to provide adequate step coverage if the resist layer were applied directly on the nonplanar surface . a high - resolution pattern defined in the resist layer is transferred into the intermediate masking layer . subsequently , a dry processing technique is utilized to replicate the pattern in the sacrificial layer . a high - resolution pattern with near - vertical sidewalls is thereby produced in the sacrificial layer . by means of the patterned sacrificial layer , high - resolution features are then defined in the underlying nonplanar surface .