a field effect transistor inverter - level shifter circuit which accepts ttl input level signals and generates mos output level signals consists of the series combination of a load device , an enhancement mode transistor , and a depletion mode transistor . the gates of the enhancement and depletion mode transistors are connected to an input terminal . the source of the enhancement transistor is connected to the drain of the depletion transistor . the depletion transistor acts to control the potential of the source of the enhancement transistor so as to allow it to tolerate worse case ttl input potential &# 34 ; 0 &# 34 ; levels while not becoming more than only weakly biased on .