a method for panel optimization provides for optimal layout of printed circuit boards on factory arrays , as well as the layout of arrays on panels . by using nesting algorithms to quickly simulate a large number of permutations , an optimal panelization solution can be quickly reached . the method includes the steps of collecting the necessary data , performing a panel dimension loop , an array length loop , and an array width loop . for every case , a total efficiency factor is calculated to help determine the optimal layout .