in a communications system having a plurality of stations interconnected by a two - line circuit , in which the two - line circuit consists of a data bus circuit for transmitting a series of data bits between at least one sending station and at least one receiving station of the plurality of stations and a clock bus circuit for transmitting clock signals in synchronism with each of the data bits ; the data bus circuit sends a signal or a command requesting the receiving station to enter a standby or an execute state after taking in data supplied , while a logic value on the clock bus circuit is fixed . in more detail , the sending station transmits signals to make at least one of the receiving stations enter the standby state after taking in data and then sends data to another receiving station , after which the sending station sends a signal or command to make both the first and second receiving stations simultaneously enter the execute state . the signal or command requesting the standby or execute state is added at the end of a data packet containing a series of data . the data packet includes data to be transferred to the receiving station and an address of the receiving station .