a ferroelectric memory device includes a microelectronic substrate and a plurality of ferroelectric capacitors on the substrate , arranged as a plurality of row and columns in respective row and column directions . a plurality of parallel plate lines overlie the ferroelectric capacitors and extend along the row direction , wherein a plate line contacts ferroelectric capacitors in at least two adjacent rows . the plurality of plate lines may include a plurality of local plate lines , and the ferroelectric memory device may further include an insulating layer disposed on the local plate lines and a plurality of main plate lines disposed on the insulating layer and contacting the local plate lines through openings in the insulating layer . in some embodiments , ferroelectric capacitors in adjacent rows share a common upper electrode , and respective ones of the local plate lines are disposed on respective ones of the common upper electrodes . ferroelectric capacitors in adjacent rows may share a common ferroelectric dielectric region . related fabrication methods are discussed .