calculating unit having adder blocks , each having single adders , a carry input , a carry output , and a carry pass output , wherein a signal at the carry pass output is indicative of a carry passing through the adder block . depending on the carry pass output signal , a clock generator for feeding the adder blocks with operands to be processed is decelerated . a determining unit determines in which of the adder blocks a least significant bit of an operand to be subtracted is disposed . a deactivating unit deactivates a carry pass output of adder block provided for lower order digits with respect to the adder block in which the least significant bit is disposed , and a feeding unit feeds a carry into the carry input of this adder block in which the least significant bit is disposed .