a microprocessor having three kinds of bus cycle mode including a read cycle , a write cycle and an instruction fetch cycle , comprises a register having three bits corresponding to the read cycle , the write cycle and the instruction fetch cycle , respectively . a combinational circuit is connected to receive a code set in the register and coded information indicating the kind of bus cycle mode . an output circuit receiving an output of the combinational circuit operates to output the output of the combinational circuit in synchronism with a start of a corresponding bus cycle .