an sram cell has reduced gate and sub - threshold leakage currents . the sram cell is designed to include eight operatively coupled transistors to reduce leakage currents irrespective of data stored in the sram cell . the transistors lower the effective supply voltage at different nodes , when either bit ‘ 0 ’ or ‘ 1 ’ is stored in the sram cell . the reduced effective supply voltage is passed to other coupled transistors for minimizing leakages . the sram cell operates in an active mode and dissipates no dynamic power during active mode to inactive mode transition and vice - versa operations . the sram cell is also capable of reducing bit line leakage currents under suitable conditions .