a processor interface chip and a maintenance diagnostic chip are provided coupled with two microprocessors designed to be run in tandem . the processor interface chip includes logic for interfacing between the microprocessors and a main memory , logic for pipelining multiple microprocessor requests between the microprocessors and main memory , logic for prefetching data before a microprocessor issues a read request , logic for allowing a boot to occur from code anywhere in physical memory without regard to the microprocessors &# 39 ; fixed memory location for boot code , and logic for intelligently limiting the flow of interrupt information over a processor bus between the microprocessors and the processor interface chip . the maintenance diagnostic chip includes logic to halt either of the microprocessors if an error is detected , and read out the state of the microprocessors and a secondary cache attached to the microprocessors , before the state of the microprocessors at the time of the fault changes to a different state which might hide evidence of the cause of the fault .