in the course of unit timing , there exists the possibility for a non - compute on a particular net in an ic chip design , which could be caused by numerous things , including but not limited to a pin being tied to power , a floating output , or invalid timing test for a given phase at a test point . a process automatically verifies that all non - computes are understood and exist for valid reasons , in order to ensure all necessary paths are being timed . the process takes a conventional comprehensive report output of a unit timing run and generates macro specific n / c reports for designers to review and sign off on .