the reliability and performance of planarized metallization patterns in an electrical device , for example copper , inlaid in the surface of a layer of dielectric material overlying a semiconductor wafer substrate , are enhanced by a method for reliably depositing a barrier layer selective to the metallization patterns . the method comprises forming a sacrificial dielectric layer above a substrate . metallization patterns are formed in the sacrificial dielectric layer . the barrier layer is selectively deposited on the metallization patterns . portions of the barrier material undesirably deposited on the sacrificial dielectric layer are removed by removing the sacrificial dielectric layer , thus preventing bridging of adjacent metallization features by the barrier layer portions . an interlevel dielectric layer is then formed in place of the sacrificial dielectric layer . the selectively deposited barrier layer advantageously reduces parasitic capacitance between metallization features in comparison to a conventional blanket - deposited silicon nitride barrier layer .