a prescaler which can be used in a pll includes a counter section and an extender section . the counter section has a pair of staged , synchronous flip - flops which generate a frequency divided signal by frequency dividing an input oscillation signal by either two or three . the extender section has a plurality of staged , asynchronous flip - flops which generates a second frequency divided signal . a switching circuit connected between the extender section and the counter section controls whether the counter section operates as either a binary counter or a ternary counter . power conservation is achieved by limiting the counter section to only a pair of flip - flops .