one embodiment of the present invention sets forth a memory module that includes at least one memory chip , and an intelligent chip coupled to the at least one memory chip and a memory controller , where the intelligent chip is configured to implement at least a part of a ras feature . the disclosed architecture allows one or more ras features to be implemented locally to the memory module using one or more intelligent register chips , one or more intelligent buffer chips , or some combination thereof . such an approach not only increases the effectiveness of certain ras features that were available in prior art systems , but also enables the implementation of certain ras features that were not available in prior art systems .