circuitry for providing external access to signals that are internal to an integrated circuit chip package . a plurality of n : 1 multiplexers are physically distributed throughout the integrated circuit die . each of the multiplexers has its n inputs coupled to a nearby set of n nodes within the integrated circuit , and each of the multiplexers is coupled to a source of select information operable to select one node from the set of n nodes for external access . each of the multiplexers has its output coupled to an externally - accessible chip pad . the integrated circuit is a microprocessor , and the source of select information may include a storage element . if so , additional circuitry is provided for writing data from a register of the microprocessor to the storage element using one or more microprocessor instructions . each multiplexer may be coupled to a different source of select information , or all multiplexers may be coupled to the same select information . moreover , a fixed set of interconnect traces may be provided to couple a fixed set of nodes to an additional set of externally - accessible chip pads . one or more m : 1 multiplexers may also be provided , having their m inputs coupled to m different outputs of the n : 1 multiplexers . each of the m : 1 multiplexers may be coupled to a second source of select information . preferably , the outputs of the m : 1 multiplexers will be coupled to a circuitry for facilitating debug and performance monitoring of the integrated circuit .