a memory circuit with glitch - less transfer of timing information . in one embodiment , the invention is a memory circuit including a controller , multiple loads , a command link communicatively coupling the controller and the loads and a data link . the data link includes multiple data clocks and communicatively couples the controller and the multiple loads . in another embodiment , the invention transfers data between a memory controller and a ram by coupling the controller and the ram using a data bus and multiple clock lines . the invention transfers a read / write command from the controller to the ram and then transfers data associated with the read / write command , clocking the data using one of the clock lines .