a computer processor including a single fused - unfused floating point multiply - add module computes the result of the operation a * b + c for floating point numbers for fused multiply - add rounding operations and unfused multiply - add rounding operations . in one embodiment , a fused multiply - add rounding implementation is augmented with additional hardware which calculates an unfused multiply - add rounding result without adding additional pipeline stages . in one embodiment , a computation by the fused - unfused floating point multiply - add module is initiated using a single opcode which determines whether a fused multiply - add rounding result or unfused multiply - add rounding result is generated .