provided are a method of creating an optimized tile - switch mapping architecture in an on - chip bus , and a computer readable recording medium for recording the method . the method of creating a tile - switch mapping architecture includes first , second and third calculating steps . the method of creating a tile - switch mapping architecture minimizes the hop distance between cores when the mapping relationship between cores and tiles is determined , to thereby minimize energy consumption and communication delay time in an on - chip bus . furthermore , the method of creating a tile - switch mapping architecture presents a standard for comparing the optimization of other mapping architectures .