a single loop pll frequency synthesizer for operation in the mhz to ghz range , suitable for integration in integrated circuits , operates at high comparison frequencies thus achieving superior phase noise performance , having wide loop bandwidths while able to tune in small frequency steps . it is based on the fact that the output frequency and the reference clock frequency always have a rational relationship , and so can always be represented as a ratio of two integer numbers . this ratio is expanded into various expressions of equivalent fraction expansions taking the form of a series of divided , added or subtracted terms , each being a rational number in itself . this ratio is realized in hardware through stages of frequency conversions using single sideband mixers ( either the upper or lower sideband , and frequency dividers . this process of frequency translation thus generates the comparison frequency to which the pll phase - locks the vco .