a programmable logic device can be configured as a finite impulse response filter capable of operating in either interpolation mode or decimation mode and of switching between those modes at run time . the fir filter structure can be mapped onto a specialized processing block of the programmable logic device that includes multipliers and adders for adding the products of the multipliers . the fir filter structure minimizes the number of multipliers used by reusing various calculations that are repeated as a result of the interpolation or decimation operation , using multiplexers or other run - time - controllable selectors to select which current or stored multiplier outputs to use .