a gate electrode control structure of an mos - gated semiconductor device includes four doped regions including a first region forming a first p - n junction with an enclosing composite region comprising a second , lightly doped region wholly enclosing a third heavily doped region partly enclosing the first region , and a fourth region forming a p - n junction with the third region . the gate electrode control structure is fabricated using known gate electrode self - alignment doping processes but wherein , in the process for forming the third heavily doped region , a spacer layer is provided on the gate electrode for defining a spacing between the third region and the channel region with an improved degree of precision .