a master and slave arrangement of processors includes a clock signal synchronization apparatus . the clock signals of two assemblies in micro - synchronous operation are only allowed to exhibit an extremely slight phase difference . a system clock signal is generated by a voltage controlled oscillator , which is fed by phase detectors with a filter at the output of each phase detector . switches are provided between the filter output and the voltage controlled oscillator input . the phase detectors compare the system clock signal and a reference clock signal . a delay is provided at the input of one phase detector .