the manufacture of n - channel and p - channel transistors in a cmos process which involves employing gate spacer oxide layers for of reducing the under - diffusion of the implanted source - drain regions under the gate areas . the spacer oxide widths for the n - channel and the p - channel transistor are set differently so that both transistor types can be optimized independently of one another and without an additional expenditure for more masking steps . the method is employed for the manufacture of large scale integrated circuits for fast switching speeds .