the present invention is directed to circuitry for achieving concurrent synchronization of carrier phase and clock timing in double - sideband , suppressed carrier transmissions systems . a phase - lock loop is used in the respective carrier and clock recovery networks . the carrier recovery loop is similar to the conventional &# 34 ; costas loop &# 34 ;. the plls are cross coupled in an interdependent recovery structure to enable a more effective clock and carrier regeneration .