an electrically programmable read only memory contains alternating metal bit lines and diffused bit lines . each diffused bit line is broken into a plurality of segments . each of the segments of the diffused bit line comprises a virtual source . a multiplicity of floating gate transistors are arranged in rows and columns . the floating gate transistors in each column are divided into m groups of n floating gate transistors each . the floating gate transistors in the n th and the th columns , where n is an odd integer given by 1 ≦ n ≦ n and is the maximum number of columns in the array are connected to the segments of one diffused bit line placed between the n th and the th columns . at least one first transfer transistor is arranged to connect one segment comprising a virtual source to a first metal bit line . the first metal bit line functions as the source for the n floating gate transistors in the th column connected to said one segment . at least one second transfer transistor connects the same one segment comprising a virtual source to a second metal bit line . the second metal bit line functions as a source for the n floating gate transistors in the n th column connected to said one segment . the removal of each select transistor from the cell where it previously resided in series with its corresponding floating gate transistor , and the combining of a plurality of select transistors into one select transistor substantially reduces the area taken by each memory cell in the array .