tester edge placement accuracy is important for testing of semiconductor component devices . the value of that accuracy is quantified to the device manufacturer in terms of yield loss and bad parts sold as good parts . a simulation is presented that models the tester accuracy , the device edge distribution and their interaction for a example device having an operating speed of 800 mbps . the same model can be applied for microprocessors or other parts that operate near the limits of ate performance . in an example given , the estimated losses due to lack of appropriate tester accuracy are considerable : with the estimated yields and selling prices for the example device , the model shows a value of over $ 1 m for every 1 ps of enhanced tester edge placement accuracy .