this invention discloses a dmos planar power device having a plurality of transistor cells formed in a semiconductor substrate with a drain region of a first conductivity type disposed at a bottom surface of the substrate . each of the dmos transistor cells includes a polysilicon segment constituting a gate supported on a top surface of the substrate wherein the gate being disposed substantially in a center portion of the transistor cell . the dmos transistor cell further includes a source region of the first conductivity type disposed in the substrate surrounding edges of the gate with a portion extends underneath the gate . the dmos transistor cell further includes a body region doped with a body dopant of a second conductivity type disposed in the substrate encompassing the source region . the body region has a portion extending underneath the gate having a under - the - gate distance less than a lateral diffusion of the body dopant and the body region having outer edges extending outwardly to neighboring transistor cells . the dmos transistor cell further includes a shallow low - concentration first - conductivity - type region under the gate wherein the shallow low - concentration first - conductivity - type region having a depth shallower than a depth of the source region .