a semiconductor memory device includes a memory cell array including a plurality of memory cell transistors , an x decoder designating a position of an x axis of the memory cell , a y decoder designating a position of a y axis crossing the x axis , a controller collectively controlling operations of read , write and erase of the memory cell transistors via the x decoder and the y decoder , a semiconductor time switch generating an output signal after a predetermined life time elapses without a power source , and a refresh trigger circuit receiving the output signal from the semiconductor time switch , and giving the controller instructions to transfer information stored in one area of the memory cell array to other area thereof to refresh the information .