a circuit for detecting a single bit upset in a dynamic logic circuit includes a latch circuit having an input for receiving a reset signal , and an output for providing a flag output signal , the latch circuit being clocked by a first clock signal , a first transistor having a drain coupled to the output of the latch circuit , a gate for receiving a second clock signal , and a source , and a second transistor having a drain coupled to the source of the first transistor , a gate for receiving a third clock signal , and a source coupled to ground .