a processor method and apparatus that allows for the overlapped execution of multiple iterations of a loop while allowing the compiler to include only a single copy of the loop body in the code while automatically managing which iterations are active . since the prologue and epilogue are implicitly created and maintained within the hardware in the invention , a significant reduction in code size can be achieved compared to software - only modulo scheduling . furthermore , loops with iteration counts less than the number of concurrent iterations present in the kernel are also automatically handled . this hardware enhanced scheme achieves the same performance as the fully - specified standard method . furthermore , the hardware reduces the power requirement as the entire fetch unit can be deactivated for a portion of the loop &# 39 ; s execution . the basic design of the invention involves including a plurality of buffers for storing loop instructions , each of which is associated with an instruction decoder and its respective functional unit , in the dispatch stage of a processor . control logic is used to receive loop setup parameters and to control the selective issue of instructions from the buffers to the functional units .