a pmos transistor is coupled directly to both v cc and v ss , for use in an electrostatic discharge protection device , thereby protecting the i / o pad of an integrated circuit . the direct coupling of the pmos transistor to both voltage levels , v cc and v ss , greatly reduces the overall esd hazard , i . e , to all four esd conditions : 1 ) positive against v ss , 2 ) negative against v ss , 3 ) positive against v cc , and 4 ) negative against v cc , the most critical of these tests being the positive against v ss and positive against v cc .