to vigorously test synchronization logic and protocols in a digital circuit design , a synchronization logic model uses randomization to emulate the uncertainty in synchronization clock delay time exhibited in actual circuits . the synchronization logic model is inserted into a software description of the design so that simulation will reveal faulty assumptions in the synchronization protocol . additionally , where a non - synchronized signal crosses from one clock domain to another clock domain in an asynchronous digital design , a transition on the non - synchronized signal triggers an “ x ” value window on the signal for a selected period relative to the receiving clock period , so that simulation will fail if the receiving logic samples the signal value during the “ x ” value window . these techniques aid in effective testing of the design .