montgomery multiplication can be computed quickly by using carry save adders and parallel multipliers . we present an enhanced technique for very fast montgomery multiplication that can be used for rsa calculations . this invention utilizes a scalable bit word implementation , suitable for very large bit encryptions . such designs can be deployed on mid - level fpgas that have dedicated multiplier logic , on asics , or on custom circuits . to our knowledge , our technique yields some of the fastest rsa encryption times to be reported , having area requirements similar to related work . such circuits can be ideal for increased security in sensitive communication fields .