for one disclosed embodiment , a processor comprises a plurality of processor cores to operate at variable performance levels . one of the plurality of processor cores may operate at a performance level different than a performance level at which another one of the plurality of processor cores may operate . logic of the processor is to monitor activity of one or more of the plurality of processor cores . logic of the processor is to constrain power of one or more of the plurality of processor cores based at least in part on the monitored activity . other embodiments are also disclosed .