a method for communicating with and controlling design logic modules external to a system - on - chip design during verification of the design uses verification software to generate and apply test cases to stimulate components of an soc design in simulation ; the results are observed and used to de - bug the design . typically , soc designs interface with cores that are external to the design . existing methods of including such external cores in a verification test of a soc design typically entail having to create special test cases to control the external cores ; such test cases typically do not communicate with test cases being applied internally to the soc and therefore lack realism . an external memory - mapped test device according to the present invention is coupled between a soc design being tested in simulation , and cores external to the soc design . internal emmtd logic provides for control and status monitoring of an external core coupled to an emmtd bi - directional bus by enabling functions including driving data on the bus , reading the current state of data on the bus , and capturing positive and negative edge transitions on the bus . in one embodiment , a test case being executed by a simulator embedded processor in the soc can communicate with and control elements external to the soc , by using the emmtd to perform such functions as initiating external core logic which drives test signals to an internal core , directly controlling an internal core via its external interface , or determining the status of an external core .