a bus arbiter circuit including a bus arbitration logic circuit , a command logic circuit coupled to the bus arbitration logic circuit , a decode circuit having a plurality of programmable option select registers wherein the decode circuit is coupled to the bus arbitration logic circuit and command logic circuit and an operating mode decode logic circuit coupled to the bus arbitration logic circuit , the command logic circuit and the decode circuit , the operating mode decode logic circuit for decoding signals provided to the bus arbiter circuit and for determining the meaning of the contents of the programmable option select registers .