processing units each having a first memory and a system controller are interconnected over a bus . the system controller includes access control units for controlling access to copies of tags of the first memories in the processing units and access to second memories to which a plurality of ways lead , and thus controls access to memories or memory access requested by the processing units . in the information processing system , a plurality of memory interfaces are included for enabling access to the second memories on an interleaving basis . furthermore , the same numbers of copies of tags and memory access control units as the number of memory interfaces are included for enabling access to tags on the interleaving basis . since access to the memories and tags on the interleaving basis is thus enabled , even if the number of processing units increases , competition for the memory access control units subsides and the efficiency of memory access improves .