a system , method , and memory controller are provided that alters a memory command stream to a hardware memory . data is written to the hardware memory and , after the data is stored in the memory , error correction code is received from the memory . bit errors are identified based upon the error correction code that was received . the memory command stream is then altered based upon the number of bit errors that were identified . in one embodiment , altering the memory command stream includes adjusting a memory refresh rate , while in another embodiment , altering the memory command stream includes adjusting a memory usage delay .