disclosed herein is a device that includes : a plurality of delay circuits each including an input node , an output node , a first power node and a second power node , and a control circuit . the delay circuits are coupled in series with the input node of a leading delay circuit receiving a first clock signal and the output node of a last delay circuit producing a second clock signal . the control circuit coupled to receive the first and second clock signals to control an operating voltage supplied between the first and second power lines . the first power nodes of the delay circuits are connected in common to the first power line , and the second power nodes the delay circuits are connected in common to the second power line .