the present invention concerns a circuit comprising a memory array having a plurality of wordlines and a plurality of bitlines , a reference circuit , a column select circuit , an enable control circuit , and one or more sense amplifiers . the reference circuit may be configured to present a reference voltage signal in response to a dummy wordline and a virtual ground signal , where the dummy wordline may be synchronized with each of the plurality of wordlines . the column select circuit may be configured to present the virtual ground signal in response to a column select signal . the enable control circuit may be configured to present an enable signal in response to the dummy wordline . the sense amplifiers may be configured to generate an output in response to the enable signal , the reference signal and the bitlines .