in recent system lsis , a plurality of rams differing in capacity and in bit width have come to be mounted on a single chip according to the needs on the system side . however , when testing the plurality of rams , if the rams differ in capacity , they cannot be tested using the same test pattern even if a special pin is provided for each ram , because x , y address mapping differs between the different rams ; accordingly , the test has to be performed by dividing the rams into groups each consisting of rams having the same memory space , and this has lead to increased test time . an external address signal and a test - only address signal are provided as ram control signals and , in the latter case , the number of x , y addresses in each of the rams 4 and 5 is set equal to that of the largest capacity ram 3 within the same chip , thereby making the x , y address mapping the same for all the rams 3 to 5 .