a cmos - based bus - hold circuit having overvoltage tolerance . the bus - hold circuit of the present invention includes , in addition to conventional input and latching inverters , a sense circuit and an arbiter circuit designed in combination to block overvoltage events from powering the latching inverter . the sense circuit includes a comparator designed to compare the potential of a standard high - potential power supply rail to the potential associated with a signal applied to the bus - hold circuit &# 39 ; s input node . the higher of those two potentials is used to activate the arbiter circuit that in turn couples the higher of those two signals to a pseudo high - potential power rail . the pseudo high - potential power rail is used to supply power to the latching inverter such that the latching inverter will not be activated during overvoltage conditions , particularly when the circuit is in its high - impedance state . the bus - hold circuit may be similarly designed to establish an undervoltage tolerance as well .