a processor is disclosed that can map a request from a central processing unit that uses memory - mapped input - output space to a second processing domain , such as a multithreaded processing domain . a request addressed to the input - output space of the central processing unit is converted to a corresponding command that simulates an operation between components in the multithreaded processing domain . the command is executed in the multithreaded processing domain . information is accessed according to the request in response to executing the command .