a method of manufacturing integrated circuits utilizing chemical mechanical polishing is disclosed . a dielectric layer , illustratively , having a dopant , dye , etc . termed a &# 34 ; marker layer &# 34 ; is formed upon a wafer having partially fabricated integrated circuits thereon . an undoped , undyed layer is deposited upon the marker layer . the undoped or undyed layer is polished and the waste slurry is monitored until a signal indicating the exposure of the signal layer is obtained . analysis of the signal provides an indication of when the cmp process should be terminated .