a nonvolatile semiconductor memory includes a plurality of memory cells arranged in columns and rows , a plurality of word lines , a plurality of bit lines , a plurality of output buffers , a plurality of page latches 18 l , and a plurality of quick current level translators . each qclt is connected to and is shared by a plurality of bit lines through a first column decoder 44 / 46 u and is also connected to a plurality of page latches through a second column decoder 46 l . each page latch is connected to one corresponding output buffer through a third column decoder circuit 38 / 40 / 42 . the page latches are grouped in a plurality of sub - pages . the qclt performs high speed and high accuracy current - mode comparison and converts the result of comparison into binary codes . these codes are stored in q - latches 36 u - 2 . the qclt functions as a current - mode analog - to - digital converter which converts the memory cell current to binary codes . the data latched in q - latches will be transferred to page latches 34 for reading out . the cell current sensing devices are separated from the data storage devices . hence , the qclt can perform current sensing operation while the page latch data are being clocked out simultaneously . within the pitch of 32 bit lines , the qclt can be designed to achieve high speed sensing , while each page latch has a pitch of 2 bit lines , and shared by two columns of memory cells . high speed sensing makes qclt more appealing to multi - level cell products . since multiple sensing iterations are required to determine which levels the cell current located between . higher speed means less waiting time .