a volatile field programmable gate array having a configurable logical structure portion that is configurable with encrypted configuration data stored external to the fpga in configuration data memory . on fpga reconfiguration , for example on power - up , the encrypted configuration data is supplied to an input of the fpga . in the fpga , the configuration data is first decrypted by a decryption algorithm embedded in logic , the algorithm using as an operand a decryption key stored in the fpga in a non - volatile memory , for example eeprom . the decrypted configuration data is then distributed to the volatile functional portion of the fpga in a conventional manner . the functional portion may be sram . with this design , unauthorized reading of the configuration data of the fpga by observation of the stream of configuration data transmitted to the fpga from the external memory , for example during power - up , will only result in encrypted configuration data being obtained . in this way , the design affords enhanced security against the loss of commercially valuable intellectual property and confidential information constituted by the unencrypted configuration data .