memory apparatus including a byte - bank organized in n rows and 8 columns , having a capacity of log 2 bytes , a log 2 bit address bus operative to address the byte - bank , an address offset bus operative to generate offsets to bits of the byte - bank with an address conversion operator , and an adder in operative communication with the address offset bus and the log 2 bit address bus , the adder operative to add addresses of the byte - bank with the offset generated by the address conversion operator and output a result to the log 2 bit address . a random access memory array may include a plurality of the byte - banks .