automatic generation of post - layout optimization circuitry allows a computer system running an integrated circuit design tool to automatically compensate for timing errors by synthesizing circuit elements to bring the timing within specified timing constraints . a new circuit element is assigned a location without determining an allowable physical location on the integrated circuit , and all timing calculations are based on the assigned location . then , once the timing constraints have been met by one or more new circuit elements , an incremental layout is performed to find physical locations for the new circuit elements , using the assigned locations as initial targets . by using assigned locations during timing calculations and later determining valid physical locations , many different circuit configurations may be evaluated in a short period of time , with only the best ones going through the more time - consuming step of layout and routing .