a phase locked loop circuit 11 includes a phase detection circuit 12 , a means for phase adjustment , and a recovery circuit 18 . the phase detection circuit 12 monitors the phase relationship between two signals and communicates the phase relationship to the phase adjustment means . the phase adjustment means provides appropriate delay to one of the signals to synchronize the two signals . the recover circuit 18 monitors the phase adjustment means for synchronization failures and provides appropriate notice to the phase adjustment means . the phase locked loop circuit 11 provides improved phase jitter resolution through the phase adjustment means . the circuit provides failure identification and correction through the recovery circuit resulting in improved phase locked loop circuit performance and reliability .