we report methods relating to scan warmup of integrated circuit devices . one such method may comprise loading a scan test stimulus to and unloading a scan test response from a first set of logic elements of an integrated circuit device at a scan clock first frequency equal to a test clock frequency ; adjusting the scan clock from the first frequency to a second frequency by a scan warmup unit , wherein the scan clock second frequency is equal to a system clock frequency ; and capturing the scan test response by a shift logic at the scan clock second frequency . we also report processors containing components configured to implement the method , and fabrication of such processors . the methods and their implementation may reduce di / dt events otherwise commonly occurring when testing logic elements of integrated circuit devices .