a method for fabrication of a high - voltage , high - frequency mos - transistor combines a deep n - well and a p - well process and the formation of an extended drain region , and a channel region , the channel having a short length and becoming well aligned with the gate edge . the deep n - well and the p - well are both produced by ion implantation . the method is compatible with a standard cmos process and gives low manufacturing costs , increased breakdown voltage , better overall high - frequency performance , and the prevention of the “ body effect ” occurring by isolation of the p - well .