a vertical cmos semiconductor device and a method of making the device . a polysilicon gate post rises normal to a surface of a substrate . an annular transistor encircles the gate post . the transistor consists of a channel layer sandwiched between a pair of source / drain layers . each layer lies directly above the layer beneath , with the gate post projecting up through the layers . one or more additional transistors of the same or differing polarities may be stacked above the first transistor , the various transistors being suitably spaced apart from each other . electrical connections with the gate post and the various source / drain layers may be configured to provide a complementary inverter or some other circuit as desired .