an integrated circuit including pairs of strained complementary cmos field - effect devices consisting of n - fet and p - fet transistors on a substrate . the n - fet is provided with a compressive dielectric stressor , while the p - fet is provided with a tensile stressed dielectric . each dielectric stressor includes a discrete horizontal segment on a surface overlying and contacting the gate of the respective fet . the stress enhancement is insensitive to pc pitch , and by reducing the height of the polysilicon stack , the scalability which is achieved contributes to a performance improvement . the n - fet leverages higher stress values that are obtainable in the compressive liners are greater than 3 gpa compared to less than 1 . 5 gpa for tensile liners .