a digital signal processor comprises a code converter which converts an integer coded in a binary two &# 39 ; s complement code to an integer coded in a sign magnitude binary code and / or a code converter which converts the smb code to the btc code . an integer coded in the btc code and stored in an m - bits register is converted to an integer coded in the smb code and input to an n - bits register , by an exclusive or processing of the bits with the sign bits and by supplementing a logic &# 34 ; 1 &# 34 ; in the less significant bit next to the least significant bit of the result of the exclusive or operation . an integer coded in the smb code and stored in an n - bits register is converted to an integer coded in the btc code and input to an m - bits register , by an exclusive or processing of m - 1 bits of magnitude bits with a sign bit . the code converters have a relatively simple construction , will not output an incorrect result , and are most suitable for processing ac signals .