the present invention relates to a parallel variable length decoder and a method for decoding a signed variable length code word . variable length decoding is a widely - used method in data compression , especially , in the applications of image data communication and storage . many international standards have adopted this technique in video data compression , for example , jpeg , mpeg , ccitt h . 261 and so on . two programmable logic arrays are used in conventional vld which differ only in there sign . the present invention uses a single pla which is triggered by bits of signed fixed length inputs , not including a sign bit . the pla output an unsigned run - level pair . the vld processes the sign bit outside the pla . a mask circuit is used to extract the sign bit which is then combined with the decoded unsigned run - level pair to get a signed run - level pair .