the present invention relates to a transistor circuit , and more specifically to a static decoder circuit made up of a series circuit of a nor logic gate circuit consisting of a plurality of misfet &# 39 ; s for receiving address signals through the gates , an inverter circuit for receiving the output of the logic gate circuit through the gate , a first misfet for receiving the output of the logic gate circuit through the gate , and a second misfet for receiving the output of the inverter circuit through the gate , wherein said nor logic gate circuit and inverter circuit are connected to a ground terminal via a first switching misfet which receives the control signals through the gate , and said series circuit is connected to a power supply terminal via a second switching misfet which receives the control signals through the gate . according to the circuit of the present invention , said first and second switching misfet &# 39 ; s are rendered off by said control signals during the standby periods , such that the current pass is completely interrupted between the power supply terminal and the ground terminal in the decoder circuit , and the output of the decoder circuit is rendered to acquire the ground level .