provided is directed to a circuit for controlling a pulse width which can be adjustable to a next generation standard dram such as a high speed ddr2 or ddr3 as well as a high speed graphic dram for supplying various cas latencies by means of including : a mode register set for setting a plurality of cas latencies according to an operation frequency by a command inputted from a chip set ; and a pulse generation circuit for generating a pulse having a variable width by using a delay time according to the plurality of cas latencies set in the mode register set .