the present invention relates to a device for generating at least one code phase the device comprising a shift register comprising n outputs and to which a code sequence to be phased is applied , and at least one logic branch controlled by at least one combination control signal on the basis of which the logic branch combines the code phase from i outputs of the shift register . n is an integer greater than 2 and i is an integer between 2 and n . said at least one logic branch preferably comprises i two - input selectors , to the first input of each of which is connected one input of the shift register and to the second input is connected one combination control signal , and an i - input combiner , to whose outputs are connected the outputs of said i selectors and from whose output said code phase is obtained .