a mechanism for implementing the chinese remainder theorem includes a signal processing architecture that is effectively configured principally of binary adders and lookup tables having small address space . through a set of lookup tables referencing a prescribed divisor , a respective set of summands are expressed in terms of quotients and remainders . those signal lines over which the quotient representative data is produced are summed in a modulo - power - of two adder , while the remainder data is summed in a simple binary adder . the resulting sums are then recombined into a common data format , using a reduced capacity lookup table and binary adders .