an architecture and method relating to a floating point operation which performs the mathematical computation of a * b + c . the multiplication is accomplished in two or more stages , each stage involving corresponding sets of partial products and concurrently accomplished incremental summations . a pipelined architecture provides for the summation of the least significant bits of an intermediate product with operand c at a stage preceding entry into a full adder . thereby , a significant portion of the full adder can be replaced by a simpler and smaller incrementer circuit . partitioning of the multiplication operation into two or more partial product operations proportionally reduces the size of the multiplier required . pipelining and concurrence execution of multiplication and addition operation in the multiplier provides in two cycles the results of the mathematical operation a * b + c while using a full adder of three - quarters normal size .