a network processor exchanges data of various descriptions via a plurality of network nodes with external network devices , such as other processors , controllers , transducers , or sensors . the network processor includes a master processor for control tasks of the processor , and a network coprocessor for supporting network tasks . a first and a second bus system , associated with the master processor and the network coprocessor with its associated functional units , particularly data link layer memory devices , respectively , serves to separate the two fields of tasks from each other . this permits both a support of gateway functions and a support of higher layer functions . higher layer memory devices , whose messages are ultimately sent or received by the master processor , are accessible from the master processor or the network coprocessor directly or indirectly via the first and / or second bus systems .