a full duplex transmission circuit for a signal having alternating synchronization words with data words . the circuit comprising a phase - locked loop including a frequency synchronizer adapted to provide an emission clock signal . a sampling signal having its phase locked on the shift between an emitted signal and a received signal is generated using a clock signal provided by the phase - locked loop . the circuit includes circuitry for imparting to the frequency synchronizer a frequency multiplier function to reduce a duration of phase skips of the sampling signal .