a method and apparatus for improving a delay line circuit of a digital delay lock loop circuit . each delay stage of the delay line consists of three gates , two nands and one inverter . the reduction in the total number of gates decreases the unit delay time for each stage , improving the resolution of each stage of the delay line . in addition , the reduction in the total number of gates in each stage significantly reduces the amount of space necessary for the circuitry of the delay line , resulting in an overall decrease in the size of the ddll circuit .