a clock generation circuit includes a clock generation unit suitable for generating a first clock , a first inversion clock having an opposite phase to the first clock , a second clock having a different phase from the first clock , and a second inversion clock having an opposite phase to the second clock ; and a reset control unit suitable for comparing the phases of the first and second clocks , and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock .