a semiconductor memory device executes the control of data input / output in accordance with control signals and address signals . the device includes data buses , a memory cell array including a plurality of memory cells , a circuit for selecting a specific memory cell from the memory cells to provide the data buses with cell information data stored in the selected cell and data output control circuit for controlling data output from the memory device , based on at least one control signal provided to the control circuit . the control circuit has an output terminal for outputting the output data , and maintains the terminal at a high - impedance state as long as the cell information provided on the data buses is not supplied to the control circuit .