aspects of the invention for testing and debugging an embedded device under test may include the step of loading an instruction into a parameterized shift register of a bist module coupled to each one of a plurality of embedded memory modules comprising the embedded device under test . an identity of the loaded instruction may be determined subsequent to loading the instruction into the parameterized shift register . a plurality of test signals may be generated which correspond to the determined identity of the loaded instruction . in this regard , each of the generated plurality of test signals may control the execution of the testing and debugging of a corresponding one of each of the plurality of embedded memory modules that make up the embedded device under test .