in one embodiment , a bist engine performs bist testing of embedded memory in an integrated circuit device via an bus from the configuration bitstream engine . during bist testing , data is written into the embedded memory at - speed , which may require the bitstream engine to produce a higher frequency than originally used for configuration . between consecutive write operations , the bist engine is capable of reading the previously written set of data from the embedded memory and comparing that read - back data with the corresponding original set of data to determine whether a bist error has occurred . by performing back - to - back write / read - back operations faster than the configuration speed and using a dedicated w / rb bus , bist testing can be optimally performed without false - positive - invoking delays and undesirable resource utilization .