a system for controlling the dma transfer for a plurality of io devices has an io controller for each group of the io devices . data is retrieved from memory and stored in the io controller where it is analyzed . the retrieved data has a structure that permits a group of dma start request quads to be linked together for parallel or pipeline processing of the dma transfer requests . each start request quad has a pointer for additionally retrieving corresponding command data . the command data is set forth in a number of blocks , each linked to the next one by a pointer . when a dma processing has been completed , the termination or completion status is entered into a specific entry in a completion list for the corresponding io device . thus , a determination can be made as to whether specific io devices have completed a requested dma processing . expansion of the system is accomplished by using combinations of main and sub controllers , where one main controller provides the aforementioned data structures for many sub controllers in order to enable the dma processing to be performed for io devices connected to the sub controllers with less frequent access of system main memory and the system bus .