a memory cell array has memory cells arranged in a matrix form . the memory cell includes a floating gate and a control gate . word lines are each coupled to the control gates of the memory cells which are arranged on a corresponding one of the rows in the memory cell array . bit lines are each coupled to drains of the memory cells which are arranged on a corresponding one of the columns in the memory cell array . an external voltage is supplied from the exterior to an external voltage input terminal . a first voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the word line coupled to the control gates . a second voltage generating circuit lowers the external voltage to generate a voltage which is to be supplied to the bit line coupled to the drains .