a method and structure are disclosed that are advantageous for aligning a contact plug within a bit line contact corridor to an active area of a dram that utilizes an insulated sleeve structure . a lower bulk insulator layer , a capacitor dielectric layer , a cell plate conductor layer , and an upper bulk insulator layer are formed upon a semiconductor substrate . an etch removes the cell plate conductor layer , the capacitor dielectric layer , and the lower bulk insulator layer so as to form an opening terminating within the lower bulk insulator layer . a sleeve insulator layer is deposited upon the upper bulk insulator layer and within the opening . another etch removes the sleeve insulator layer from the bottom surface within the lower bulk insulator layer . a still further etch creates a contact hole that exposes a contact . the contact can be upon a transistor gate , a capacitor storage node , or an active region on the semiconductor substrate . a conductive plug is then formed in the contact hole so as to be in electrical communication with the contact . the sleeve insulator layer electrically insulates the conductive plug from the cell plate conductor layer and self - aligns the blcc so as to improve contact plug alignment tolerances between the blcc and the capacitor components .