a method of aligning a clock signal and a data strobe signal in a system comprising a memory controller and a memory , and a corresponding memory system are provided . the method comprising the steps of : putting the memory into a write levelling mode ; incrementing an alignment delay applied to the data strobe signal until a transition point occurs at which a response of the memory to issuance of the data strobe signal transitions to an inverse state ; performing an oversampling of the response of the memory over a selected interval following said transition point ; repeating the steps of incrementing and performing an oversampling until , for a selected alignment delay , a majority of results of the oversampling is in the inverse state ; performing a cycle alignment detection procedure to determine an identified clock cycle of a plurality of adjacent cycles of the clock signal , the identified clock cycle responsible for the transition point ; and applying the selected alignment delay to the data strobe signal and applying a clock cycle selection to a data path in the system to match the identified clock cycle .