logic circuits that support the addition of three binary numbers using hardwired adders are described . in one embodiment , this is accomplished by using a 3 : 2 compressor , using hardwired adders to add the sums and carrys produced by the 3 : 2 compression , and sharing carrys data calculated in one logic element with the following le . in such an embodiment , with the exception of the first and last les in a logic array block , each le in effect lends one look - up table to the le below and borrows one lut from the le above . the lut being lent or borrowed is one that implements the carry function in the 3 : 2 compressor model . in another aspect , an embodiment of the present invention provides les that include selectors to select signals corresponding to the addition of three binary numbers mode .