a gate array base cell performs logic and memory cell functions and comprises a first p - channel transistor for performing logic functions and having a first predetermined transconductance area and a second p - channel transistor for performing memory cell functions and having a second predetermined transconductance area . the second transconductance area is smaller than said first predetermined transconductance area . the gate array base cell has programmable connections to first p - channel transistor and second p - channel transistor for selectively performing memory cell functions and logic functions . the gate array base cell may be connected to operate as a memory cell with logic functions or separately as a memory cell or a logic gate array , such as a two - input nand gate .