at least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self - aligned double patterning process , forming a first metal feature having a first width on a first track of a metal layer using the sadp process , forming a second metal feature having a second width on a second track of the metal layer . the second track is adjacent to the first track . the method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths , rendering the first and second features decomposable using the sadp process ; and decomposing e overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern .