a process for the manufacturing of an integrated circuit including a low operating voltage , high - performance logic circuitry and an embedded memory device having a high operating voltage higher than the low operating voltage of the logic circuitry , providing for : on first portions of a semiconductor substrate , forming a first gate oxide layer for first transistors operating at the high operating voltage ; on second portions of the semiconductor substrate , forming a second gate oxide layer for memory cells of the memory device ; on the first and second gate oxide layers , forming from a first polysilicon layer gate electrodes for the first transistors , and floating - gate electrodes for the memory cells ; forming over the floating - gate electrodes of the memory cells a dielectric layer ; on third portions of the semiconductor substrate , forming a third gate oxide layer for second transistors operating at the low operating voltage ; on the dielectric layer and on the third portions of the semiconductor substrate , forming from a second polysilicon layer control gate electrodes for the memory cells , and gate electrodes for the second transistors ; in the first portions of the semiconductor substrate , forming source and drain regions for the first transistors ; in the second portions of the semiconductor substrate , forming source and drain regions for the memory cells ; in the third portions of the semiconductor substrate , forming source and drain regions for the second transistors .