this invention provides methods of forming a field - effect transistor in an integrated circuit using self - aligning technology on the basis of a sidewall spacer masking procedure , both for defining the device isolation features and the source and drain regions . the active region is defined after patterning the gate electrode by means of deposition and etch processes instead of overlay alignment technique . thus , the present invention enables an increase of the integration density of semiconductor devices , a minimization of the parasitic capacitances in field - effect transistor devices , and a quicker manufacturing process .