this disclosure concerns a semiconductor memory device comprising memory cells including floating bodies and storing therein logic data ; bit lines and word lines connected to the memory cells ; sense amplifiers connected to the bit lines ; a refresh controller instructing a refresh operation for restoring deteriorated storage states of the memory cells ; and a refresh interval timer setting a refresh interval between one refresh operation and a next refresh operation to a first interval in a data read mode or a data write mode , and setting the refresh interval to a second interval longer than the first interval in a data retention mode , the data read mode being a mode in which the data stored in the selected memory cell is read to an outside of the device , the data write mode being a mode in which data from the outside is written to the selected memory cell .