a ddr sdram where unidirectional row logic is associated with and connected to a single memory array instead of being associated with and connected to multiple memory arrays . the unidirectional row logic is located in the outward periphery of its associated array , but is not within a throat region between two arrays . the location of the row logic allows the throat region to include more bidirectional io circuitry and signal lines servicing two arrays , which increases the performance of the sdram . in addition , separate power bussing is employed for the memory arrays and io circuitry . this prevents noise from the arrays from affecting the io circuitry and signal lines of the throat region and vice versa .