an abstraction based multi - phase method for vlsi chip floorplanning is described . the abstraction based approach provides a solution to macro floorplanning in the presence of leaf level intermediate logic , and achieves it without loss of accuracy in the results . annotations generated during abstraction are presented as floorplanning constraints which account for the abstracted data . the floorplanning and placement algorithms handle detailed netlists consisting of large blocks and small leaf level cells in an efficient manner . the abstraction based approach phases out by abstracting the leaf level logic and reintroducing them in the form of floorplan constraints . the abstraction and bundling phases achieves a significant improvement in the performance of a simulated annealing based floorplanner . the overall concept of driving a floorplanning algorithm with a path based hyper - edge representation also helps to provide structural information about the netlist to the floorplanner .