a self - timed data ordering method and circuit for multi - data rate memories orders a plurality of data words substantially simultaneously retrieved during successive read operations of a memory device . a data word ordering designator is stored from each of the successive read operations and managed in a first - in first - out manner . the data word ordering designator configures ordering circuitry for the desired ordering of the plurality of data words simultaneously retrieved . following the ordering of the plurality of data words , the properly ordered data words are latched in their desired order for subsequent delivery . once the properly ordered data words are latched , the ordering circuitry is reconfigured according to the next oldest data word ordering designator . the data word ordering designator retains the pipelined ordering of the corresponding read operations to the corresponding memory banks of the memory device .