a method of incrementally reducing a design is disclosed . a logic verification tool receives a design and a property for verification with respect to the design , and then selects one or more of a plurality of diverse techniques for reducing the design . the logic verification tool then reduces the design to create a reduced design using the one or more techniques and attempts to generate a valid solution for the property on the reduced design . the logic verification tool determines whether a valid solution is generated , and , if not , replaces the design with the reduced design . until a valid solution is generated , the logic verification tool iteratively performs the selecting , reducing , determining and replacing steps .