a time division multiplexer chip having particular application in a digital voice processing system wherein voice processing functions are run in software . the tdm chip has a pair of rams which are in communication with a bus and at least one interface that provides communication with other devices . an bank switch controls the rams so that their communication with the bus and the interface alternates , i . e . while the first ram is in communication with the interface the other ram is in communication with the bus . after a determined period the communications are reversed . this scheme provides faster processing and more efficient use of the components . including is a provision for allowing multiple interfaces to communicate with the ram alternatively in a time shared manner .