a frequency synthesizer device has an input port for a digital code which defines the frequency to be synthesized and an accumulator circuit for successively counting the digital codes in the form of numbers in time with signals of an accumulation clock . an accumulation decoder is coupled to the accumulator circuit and supplies accumulation information relating to the counted number in the accumulator circuit . a variable divider circuit is controlled by this accumulation information to supply the synthesized frequency signals based upon the signals of a reference clock .