video display pipes may terminate with a fifo buffer from which pixels are provided to a display controller to display the pixels on a graphics / video display . the display pipes may frequently process the pixels at a much higher rate than at which the display controller fetches the pixels from the fifo buffer . in an error - checking only mode , the fifo may be disabled , and an error - checking block connected in front of the fifo may receive the pixels processed by the display pipes as fast as the display pipes are capable of processing the pixels . accordingly , the length of test / simulation time required to perform a test may be determined by the rate at which pixels are generated rather than the rate at which the display controller displays the pixels . it also becomes possible to perform testing / simulation in environments where a display is not supported or is not available . the results generated by the error - checking may be read and compared to an expected value to detect test pass / fail conditions .