a semiconductor integrated circuit includes : a plurality of scan flip - flops configured to form a scan chain in a scan test ; and a plurality of clock gating circuits connected between a clock input and corresponding portions of the plurality of scan flip - flops , respectively . the plurality of clock gating circuits are connected in serial to form a chain and gating setting data is inputted in serial through the chain connection . each of the plurality of clock gating circuits controls a connection between the clock input and a corresponding portion of the plurality of scan flip - flops based on the gating setting data .