to date , bandwidth mismatch within time - interleaved analog - to - digital converters has been largely ignored because compensation for bandwidth mismatch is performed by digital post - processing , namely finite impulse response filters . however , the lag from digital post - processing is prohibitive in high speed systems , indicating a need for blind mismatch compensation . even with blind bandwidth mismatch estimation , though , adjustment of the filter characteristics of track - and - hold circuits within the ti adcs can be difficult . here , a t / h circuit architecture is provided that uses variations of the gate voltage of a sampling switch to change the bandwidth of the t / h circuits so as to precisely match the bandwidths .