an lsi integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units . the system and each minimum replaceable unit fully conforms to the level sensitive scan design rules . . each of the minimum replaceable units includes a shift register segment having more than two shift register stages . each register stage of each shift register segment of each minimum replaceable unit includes a master flip - flop and a slave flip - flop . connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register . additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units . the additional circuit means facilitates and is utilized in testing the circuit integrity of each minimum replaceable unit .