integrated circuit memory devices include an array of memory cells electrically coupled to a plurality of word lines and a word line driver circuit . the word line driver circuit includes a variable - width pulse generator having a first delay unit therein . the word line driver circuit is configured to drive a selected one of the plurality of word lines with a first word line signal having a leading edge synchronized with a leading edge of a clock signal and a trailing edge synchronized with a trailing edge of the clock signal when a one - half period of the clock signal is greater than a length of delay provided by the first delay unit . the word line driver circuit is further configured to drive the selected one of the plurality of word lines with a second word line signal having a leading edge synchronized with the leading edge of a clock signal and a trailing edge synchronized with an edge of a signal generated by the first delay unit when the one - half period of the clock signal is less than the length of the delay provided by the first delay unit .