when executing successive processing of conventional software , a parallel processing apparatus turns a processing state discrimination flag off , increases a program count by 1 at a time , reads out one instruction , and processes that instruction in an arithmetic unit . when executing parallel processing for new software , the parallel processing apparatus turns the processing state discrimination on , increases the program count by m at a time , reads out m instructions , and exercises parallel processing over m instructions in m arithmetic units . in order to select either of the above described two kinds of processing , a discrimination changeover instruction having function of changing over the processing state discrimination flag is added . instructions are processed in arithmetic unit in accordance with the processing state discrimination flag . in this way , successive processing and parallel processing are provided with compatibility and are selectively executed . further , the parallel processing apparatus making great account of compatibility of a great part of software reads out m instructions without using the processing state flag , decodes the m instructions , checks whether a branch instruction exists in the k - th instruction , then executes the first to the - th instructions in k + 1 arithmetic units , and prevent execution of the - th to m - th instructions . by executing the k - th branch instruction , the parallel processing apparatus calculates an address nm + h of its branch destination , performs calculation to check whether the condition is satisfied or not , then prevents execution of instructions of addresses nm to nm + h - 1 , and executes instructions of addresses nm + h to m . in this way , the parallel processing apparatus executes a plurality of instructions and successively executes branch instructions .