a method and associated architecture for dividing column readout circuitry in an active pixel sensor in a manner which reduces the parasitic capacitance on the readout line . in a preferred implementation , column readout circuits are grouped in blocks and provided with block signaling . accordingly , only column output circuits in a selected block significantly impart a parasitic capacitance effect on shared column readout lines . block signaling allows increasing pixel readout rate while maintaining a constant frame rate for utility in large format high - speed imaging applications .