a semiconductor memory architecture is disclosed which results in reduced power dissipation . this reduction is accomplished by partitioning the word line of an array into segments thereby forming selectable blocks within the array . the power is reduced by the number of blocks by which the array can be partitioned . the word line segments are routed to a central decoder with a block select provision . routing is accomplished with interconnect lines which are typically metal layers . the array remains continuous in spite of block partitioning .