an encryption - decryption circuit for encrypting and decrypting data . the encryption - decryption circuit comprises : 1 ) an n - bit shift register for storing and shifting an n bit keyword ; 2 ) a first exclusive - or gate array for receiving m bits from the n - bit shift register and generating a one - bit exclusive - or result that is shifted into an input of the n - bit shift register ; and 3 ) a second exclusive - or gate array comprising k exclusive - or gates , each of the k exclusive - or gates receiving one of k bits from the n - bit shift register and one of k data bits from a received k - bit data word and generating therefrom an exclusive - or result . the k exclusive - or gates thereby produce one of : i ) a k - bit encrypted data word and ii ) a k - bit unencrypted data word .