a display data synthesizer circuit is used for a display panel having a multiplicity of display elements selectively excited for display of the desired pattern of characters or symbols . the display elements are divided into a plurality of sections which are sequentially driven and in driving each section , selected display elements of that section are excited simultaneously for a predetermined period of time , by sequentially synthesizing and holding the display data for the respective sections in the order of the driving operations thereof . the circuit includes a series output shift register and a parallel output shift register . the series output shift register stores a plurality of bits included in a display data for one section , applied thereto bit - serially at a first repetitive speed , and outputs the stored data at a second repetitive speed higher than the first repetitive speed . the parallel output shift register receives bit - serially the display data derived from the series output shift register , and holding it for a predetermined period of time , applies it bit parallelly to the drive circuit of the display panel for that same period . the series output shift register receives and stores the display data for the next section during the time when the parallel output shift register applies the display data held thereby to the drive circuit . the second repetitive speed is so selected as to make the data transfer time from the series output shift register to the parallel output shift register sufficiently short so that the display disturbances of the display panel are not substantially recognized visually .