a unique way of using a 2 n bit synchronization pattern to obtain a faster and more reliable calibration of multiple data paths in a memory system is disclosed . if the 2 n bit synchronization pattern is generated with a known clock phase relationship , then the data - to - clock phase alignment can be determined using simple decode logic to predict the next m - bits from a just - detected m - bits . if the succeeding m - bit pattern does not match the predicted pattern , then the current data - to - clock alignment fails for a particular delay value adjustment in the data path undergoing alignment , and the delay in that data path is adjusted to a new value . all data alignment is ensured to occur to a desired edge of the clock signal , e . g ., a positive going edge , by forcing a failure of all predicted m - bit patterns which are associated with an undesired edge , e . g ., a negative going edge , of the clock signal .