a tester that is well suited for operation at high speeds or with narrow pulses . the tester includes a state based pulse shaping circuit that combines edge signals into a pulsed output signal . the circuit combines groups of set and reset signals . the edge signals define the start and stop of pulses in the output signal even if the set and reset edge signals overlap or successive set signals overlap or successive reset signals overlap . this circuit allows for a low cost and low power cmos implementation of an output signal formatter .