a method and apparatus for testing or diagnosing faults in a scan - based integrated circuit using a unified self - test and scan - test technique . the method and apparatus comprises using a unified test controller to ease prototype debug and production test . the unified test controller further comprises using a capture clock generator and a plurality of domain clock generators each embedded in a clock domain to perform self - test or scan - test . the capture clocks generated by the capture clock generator are used to guide at - speed or reduced - speed self - test within each clock domain . the frequency of these capture clocks can be totally unrelated to those of system clocks controlling the clock domains . this unified approach allows designers to test or diagnose stuck - type and non - stuck - type faults with a low - cost dft tester or a low - cost dft debugger . a computer - aided design method is further developed to realize the method and synthesize the apparatus .