a decoder for a memory device includes driving devices each applying a respective line voltage to a respective line of the memory device when turned on . the decoder also includes a control device coupled to the plurality of driving devices at a common node for generating a voltage that controls the driving devices to turn on or off . also , a capacitor coupled to the common node increases the voltage at the common node from an initial boost voltage to a final boost voltage . thus , a line of a memory device is driven to a boost voltage with minimized area and wiring complexity .