the present invention includes a adaptable high - performance node with several features that enable it to provide high performance along with adaptability . a preferred embodiment of the rxn includes a run - time configurable data path and control path . the rxn supports multi - precision arithmetic including 8 , 16 , 24 , and 32 bit codes . data flow can be reconfigured to minimize register accesses for different operations . for example , multiply - accumulate operations can be performed with minimal , or no , register stores by reconfiguration of the data path . predetermined kernels can be configured during a setup phase so that the rxn can efficiently execute , e . g ., discrete cosine transform , fast - fourier transform and other operations . other features are provided .