a system comprises a controller device , an integrated circuit buffer device and a first and second memory device . a first plurality of signal lines is coupled to the controller device . a second plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device . the second plurality of signal lines carries first address information from the integrated circuit buffer device to the first memory device . a third plurality of signal lines is coupled to the first memory device and the integrated circuit buffer device . the third plurality of signal lines carries first control information from the integrated circuit buffer device to the first memory device . a first signal line is coupled to the first memory device and the integrated circuit buffer device . the first signal line carries a first signal from the integrated circuit buffer device to the first memory device . the first signal synchronizes communication of the first control information from the integrated circuit buffer device to the first memory device .