the present invention provides a thin film transistor array panel comprising an insulating substrate ; a gate line formed on the insulating substrate ; a gate insulating layer formed on the gate line ; a drain electrode and a data line having a source electrode formed on the gate insulating layer , the drain electrode being adjacent to the source electrode with a gap therebetween ; and a pixel electrode coupled to the drain electrode , wherein at least one of the gate line , the data line , and the drain electrode comprises a first conductive layer comprising a conductive oxide and a second conductive layer comprising copper .