a dram memory cell and process sequence for fabricating a dense layout is fabricated with silicon - on - insulator cmos technology . specifically , the present invention provides a dense , high - performance sram cell replacement that is compatible with existing soi cmos technologies . various gain cell layouts are known in the art . the present invention improves on the state of the art by providing a dense layout that is fabricated with soi cmos . in general terms , the memory cell includes a first transistor provided with a gate , a source , and a drain respectively ; a second transistor having a first gate , a second gate , a source , and a drain respectively ; and a capacitor having a first terminal , wherein the first terminal of said capacitor and the second gate of said second transistor comprise a single entity .