a one - transistor , floating - body dynamic random access memory cell is provided that includes a field - effect transistor fabricated using a process compatible with a standard cmos process . the field - effect transistor includes a source region and a drain region of a first conductivity type and a floating body region of a second conductivity type , opposite the first conductivity type , located between the source region and the drain region . a buried region of the first conductivity type is located under the source region , drain region and floating body region . the buried region helps to form a depletion region , which is located between the buried region and the source region , the drain region and the floating body region . the floating body region is thereby isolated by the depletion region . a bias voltage can be applied to the buried region , thereby controlling leakage currents in the 1t / fb dram cell .