disclosed herein is a delay circuit for performing one of a charge and a discharge in two stages , and delaying a signal , the delay circuit including an output section configured to output a delayed signal ; two power supplies ; and a delay inverter ; wherein the delay inverter has a first transistor and a second transistor of an identical channel type for one of a first charge and a first discharge , the first transistor and the second transistor being connected in series with each other between the output section and one power supply , and the delay inverter has a third transistor of a different channel type from the first transistor and the second transistor for one of a second charge and a second discharge , the third transistor being connected in parallel with one of the first transistor and the second transistor .