an sram wafer is conventionally fabricated through the definition of the gate poly . the pmos oxide is then applied in a layer that uniformly covers the surface and sidewalls of the gate poly , then the interpoly contacts are patterned and etched and the nmos s / d &# 39 ; s are implanted . the pmos load poly is deposited , again in a layer that uniformly covers the pmos oxide over the surface and sidewalls of the gate poly . oxide spacers are formed on the pmos poly along the gate poly sidewalls , and a p + implantation forms the pmos sources and drains . the oxide spacers protect an l - shaped region along the poly gate sidewall from the p + implant , thus defining pmos load channels on either side of the gate poly that are gated by the gate poly sidewalls . the foot of the l on one side and the extension of the l above the gate poly on the other create gate / drain offsets that reduce i . optionally , a gate poly / oxide stack may be used to enlarge one of the gate / drain offsets .