a static random access memory includes a pair of p - channel metal - oxide - semiconductor transistors which serve as variable resistors for terminating bit lines and a control circuit for causing the pmos transistors to have a low impedance level during read out and an intermediate impedance level during writing so that sudden d . c . current is suppressed and the voltage at the bit lines is prevented from being lowered . the variable resistor device can constitute a current mirror circuit along with a metal - insulator - semiconductor transistor of the control circuit , so that it becomes possible to provide a stable control which is invulnerable to manufacturing tolerances .