a memory controller includes a buffer control circuit to enable / disable buffer coupled to a terminated bus . the bcc can detect transactions and speculatively enable the buffers before the transaction is completely decoded . if the transaction is targeted for the terminated bus , the buffers will be ready to drive signals onto the terminated bus by the time the transaction is ready to be performed , thereby eliminating the “ enable buffer ” delay incurred in some conventional mcs . if the transaction is not targeted for the terminated bus , the bcc disables the buffers to save power . in mcs that queue transactions , the bcc can snoop the queue to find transactions targeted for the terminated bus and begin enabling the buffers before these particular transactions are fully decoded .