the present invention is directed to an apparatus and method for reducing a parasitic capacitance in an integrated circuit . the apparatus includes a substrate and a biasing device . the substrate has a circuit disposed thereon , wherein a first capacitance exists between the substrate and an element of the circuit . the biasing device dc biases a first portion of the substrate to a voltage different than a voltage of a second portion of the substrate , thereby inducing a second capacitance between the first portion of the substrate and the second portion of the substrate . the second capacitance is in series with the first capacitance .