an encoding circuit converts successive bits of the original data to successive bits of coded data at a coding rate equal to m / n , where m and n are each an integer satisfying m & lt ; n , in accordance with a rule of a run - length - limited coding system and contains an encoder which inputs parallel m bits of the original data , and outputs parallel n bits of coded data corresponding to the input . successive bits of data which are to be encoded are cyclically divided into a plurality of groups , and the data in the plurality of groups are input in a plurality of shift registers , respectively . each of the plurality of shift registers simultaneously supplied a part of the m bits of the input to the encoder , synchronizing with a clock . the n bits of the output of the encoder is received in parallel in another shift register , and are serially output from the shift register , synchronizing with a second clock . the circuit reduces the maximum required frequency value of its internal clock by operating with only two clock signals . a decoding circuit converts the coded data to the original data .