a system for reducing test data volume in the testing of logic products such as modules on integrated circuit chips , and systems comprised of multiple integrated circuit chips . test stimulus data are loaded from a tester into the logic product to apply to portions of combinational logic circuitry therein in order to detect faults comprises “ care ” bits and “ non - care ” bits . the care bits target focal faults of interest in the logic circuitry being tested while the non - care bits do not . non - care bits in the test vector data are filled with repetitive , repeating , or other background data sequences . the background data sequences are constructed such that they can be algorithmically recovered from a small amount of initialization data . the recovery can use hardware that is located in the product under test , inside the tester , or between the product under test and the tester , or software residing in the tester and operating while the test is performed . the software and / or hardware recover the full test input stimulus data including the fill data from the much more compact source data . the use of a compacted data format for the fill data provides for a high degree of compressibility of the total test input stimulus vector data set . the method for test data reduction combines the compact data representation for the input stimulus data with on - product or off - product compression of the test response data . the response data compression can be accomplished by the use of error - detecting codes , by comparing the responses from several identical products under test . the combination of data compression techniques for both , test input stimulus data and test output response data , results in significantly better overall data reduction .