a hardware logic arrangement for subtraction using a 3 : 2 carry - save - adder for use with high speed floating point computation circuits . three operands to be combined are routed to the three inputs of the csa via separate multiplexors and appropriate inverting logic . output sum and carry vectors are routed via further muxs to separate latch storage registers . subtraction executed as addition of the inverse of an operand is implemented by routing a constant &# 34 ; 1 &# 34 ; to the mux steering the output carry vector to its associated latch .