an encoder for enabling selection of output bits that reduce run - length includes classification circuitry , a disparity control circuit , encoding circuitry , and a run - length control circuit . the classification circuitry is configured to receive data in a first bitwidth . an output of the classification circuitry is in communication with the disparity control circuit . the encoding circuitry is configured to encode the data received in the first bitwidth into a second bitwidth . the run - length control circuit is included in the encoding circuit and is selectively triggered in one coding scheme when a contiguous portion of the data of the first bitwidth is of a particular sequence , e . g ., all logic ones , to generate a control signal . the run - length control circuit receives as additional inputs outputs of a portion of the encoding circuitry and a disparity signal from the current encoding cycle . the control signal , when generated , reduces run - length of the second bitwidth .