a cache coherency mechanism for a computer system having a plurality of processors , each for executing a sequence of instructions , at least one of the processors having a cache memory associated therewith . the computer system includes a memory that provides an address space where data items are stored for use by all of the processors . a behavior store holds in association with an address of each item , a cache behavior identifying the cacheable behavior of the item , the cacheable behaviors including a software coherent behavior and an automatically coherent behavior . when a cache coherency operation is instigated by a cache coherency instruction , the operation is effected dependent on the cacheable behavior associated with the specified address of the item . methods for modifying the coherency status of a cache are also described .