a method and apparatus for optimizing body bias connections to nfets and pfets using a deep n - well grid structure . a deep n - well is formed below the surface of a cmos substrate supporting a plurality of nfets and pfets having a nominal gate length of less than 0 . 2 microns . the deep n - well is a grid structure with a regular array of apertures providing electrical continuity between the bottom of the substrate and the nfets . the pfets reside in surface n - wells that are continuous with the buried n - well grid structure . the grid and n - well layout is performed on the basis of the functionality of the pfets contained in the n - wells .