a semiconductor integrated circuit includes a first pad allocated to receive a row address , a second pad allocated to discriminate a first input / output mode and a second input / output mode , a detector configured to generate a detection signal in response to logic levels of the first and second pads , and a column address controller configured to deassert a column address to a logic low level in response to a deasserted detection signal . the semiconductor integrated circuit may selectively support one of first and second memory capacities and one of the first and second input / output modes using the logic levels of the first and second pads .