an area efficient realization of an n - bit constant coefficient adder / subtractor implemented on fpgas , utilizing n luts with single output generation capability . it includes three inputs from every lut for addition / subtraction , without any requirement for extra logic for support of arithmetic mode and carry chains . for fpgas supporting 4 - input luts , the concept is further enhanced with the capability to perform addition and subtraction dynamically , by exploiting the fourth unused input of the luts . another embodiment involves delay - optimized realization of an n - bit constant coefficient adder / subtractor implemented on fpgas with 4 - input luts . luts in the implementation have single output generation capability without any carry generation and propagation . the implementation utilizes n + 1 luts and gives a delay proportional to n / 2 of routing resource used . however , the implementation becomes more efficient by the use of cascade chains . the delay optimization is achieved by doing computation in two parallel chains .