a flash memory device includes a memory cell array , a clock signal input , an input for receiving a signal designating a writing operating mode , a plurality of data input / output pads , and a data input / output buffer circuit that is electrically connected to the clock signal input and to the plurality of data input / output pads . the data input / output buffer circuit is configured to receive data that is to be written to the memory cell array through the data input / output pads in synchronization with a clock signal that is applied to the clock signal input in response to activation of the signal designating the writing operating mode .