a system and method for front - end bypass testing in an electronic circuit . according to one embodiment , the integrated circuit that includes a memory block having at least one input and at least one output that wherein a critical path in the integrated circuit exists through the memory block . at least one input is associated with a block of input logic and at least one output is associated with a block of output logic . the integrated circuit also includes a test circuit coupled to the memory block and operable to verify the block of input logic and the block of output logic while at the same time not impacting the critical path of the integrated circuit .