a semiconductor memory chip in accordance with the present invention includes a first memory array to be tested including a plurality of memory cells arranged in rows and columns , the memory cells being accessed to read and write data thereto by employing bitlines and wordlines , the data provided on input / output pins , and a pattern generator formed on the memory chip . the pattern generator further includes a programmable memory array including a plurality of memory banks , the memory banks having memory cells arranged in rows and columns , each bank being capable of storing data for a pattern to be generated for each of the input / output pins of the first memory array . an addressing circuit for accessing the data stored in the programmable memory array to address individual data to be transmitted to and from the first memory array is included .