a control store for a microprocessor is divided into two segments with one segment of the control store located on the microprocessor chip and the other segment of the control store located on a separate chip . in multiprocessor applications , a number of the microprocessors share the control store segment on the separate chip . each control store word includes a field containing a prediction of the address for the next control store word needed by the microprocessor . the predicted address is used to access the control store prior to receipt of the actual request by the processor . when the processor actually requests the next control store word , a compare is performed between the predicted address and the address actually requested by the processor . if they match , the control store word is passed on to the processor . if they do not , the address actually requested by the processor is used to obtain the next control store word . in multiprocessor applications , a number of microprocessors share the same control store segment on the separate chip . as long as the actual address requested by a microprocessor matches the predicted address stored with the previously accessed control store word in the shared segment of the control store , that microprocessor retains access to the shared control store segment . however , on occurrence of a mismatch it loses its priority to access the shared segment and must await the satisfaction of all pending requests of other microprocessors before it can again access the shared segment and obtain the control store word at the actual address requested .