a latching cmos comparator method and circuit are disclosed . the comparator circuit includes a differential input stage and a latching stage . the input stage includes a differential amplifier and a moore mirror load . the load includes a first cross - coupled amplifier pair , and a pair of diode - connected transistors coupled in parallel to the first amplifier to control gain . the input stage devices are sized to provide a gain on the order of 10 to 20 . the latch clock signal is isolated from the input stage to avoid injected charge offset error . the second or latching stage includes a second cross - coupled transistor amplifier coupled to the input stage to provide additional gain . the latch clock signal is provided to a digital switch which controls gain in the second amplifier . the digital switch enables a second pair of diode - connected transistors disposed in parallel to the latch stage amplifier pair , to reduce gain during sampling , for a total input referenced gain on the order of 60 during sampling . the digital switch disables the diode - connected transistors during latching , so that the second amplifier operates at maximum gain during latching . the digital switch circuitry isolates the latch clock signal from the latching nodes . after latching , the diode - connected devices speed recovery by clamping the latching node voltages . the latching nodes are coupled through inverters to an rs flip - flop circuit .