disclosed is a cascode configuration that moves the gate of the cascode substantially without delay relative to an output node by capacitively coupling the latter onto the cascode gates . the passive coupling eliminates the need for actively driving the gates of the cascode . in some embodiments , the only circuitry needed on the cascode gate may be a biasing circuit that limits the swing on the cascode gate between v max and 2 × v max , where v max is a transistor device rating .