a digital power management system for an analog - to - digital converter operates to cause the sample rate of the analog - to - digital converter to function at an original desired frequency so long as changing input signals are present . whenever activity at the input of the analog - to - digital converter ceases to change , the system automatically decreases the clock signal sampling rate to a slower clock frequency , or shuts down the application of clock signals . this conserves power until a change in the analog input is detected , whereupon the system automatically increases the sample clock frequency back to the original frequency .