a system and method for increasing the throughput of a processor during cache misses . during the retrieval of the cache miss data , subsequent memory requests are generated and allowed to proceed to the cache . the data for the subsequent cache hits are stored in a bypass retry device . also , the cache miss address and memory line data may be stored by the device when they are retrieved and they may be sent them to the cache for a cache line replacement . the bypass retry device determines the priority of sending data to the processor . the priority allows the data for memory requests to be provided to the processor in the same order as they were generated from the processor without delaying subsequent memory requests after a cache miss .