a process is provided for producing active and passive devices on various levels of a semiconductor topography . as such , the present process can achieve device formation in three dimensions to enhance the overall density at which an integrated circuit is formed . the multi - level fabrication process not only adds to the overall circuit density but does so with emphasis placed on interconnection between devices on separate levels . thus , high performance interconnect is introduced whereby the interconnect is made as short as possible between features within one transistor level to features within another transistor level . the interconnect employs a via routed directly between the drain region of an upper level transistor to the gate of a lower level transistor so as to effect a direct coupling between the output of one transistor to the input of another . direct coupling in this fashion affords a lower propagation delay and therefore achieves the benefit of a higher performance , faster switching circuit .