an interrupt controller has an interrupt controller , an interrupt control register having registers each including first and second flip - flops , a channel selector , and a read / write circuit . the interrupt controller receives interrupt requests from external devices and transmits these interrupt requests to external processing devices . the interrupt control register includes registers for recording data to control operation of the interrupt controller and the state of a plurality of interrupt requests . the channel selector assigns one register from the registers . the first flip - flop indicates the generation of an initial interrupt request . the second flip - flop indicates the generation of following interrupt requests when the first flip - flop has already been set to indicate the generation of the initial interrupt request . the read / write means , connected to the second flip - flop , writes data into the second flip - flop based on control signals from the external devices and outputs the data of the second flip - flop to the external devices .