a logic level converter for translating differential cmos logic signals to into differential logic signal pairs such as those associated with ecl levels . the converter includes two components . a first component consists of two branches coupled to the switchable cmos level input and it provides a first switchable translated output . the second component is an ecl current switch . the current associated with the converter is mirrored through the branches to minimize the effects of fabrication , temperature , and / or power supply vagaries , as well as a very fast and tolerance independent signal level translation .