a semiconductor memory device includes a memory cell array of memory cells each including a cell transistor and a ferroelectric capacitor ; a sense amp circuit operative to sense / amplify a signal read out of the ferroelectric capacitor through a pair of bit lines ; a pair of decoupling transistors provided on the pair of bit lines to decouple the bit lines ; a control circuit operative to provide a control signal to the gates of the decoupling transistors to control conduction of the decoupling transistors ; and a dummy capacitor provided in connection with at least either one of the pair of bit lines between the decoupling transistors and the sense amp circuit . the control circuit is configured to be capable of turning the decoupling transistors from on to off when a certain period of time elapsed after the beginning of reading .