a output storage latch within a combinational logic circuit may be adapted to form a scan flip - flop latch that supports both functional operation and scan chain testing of a combinational logic matrix included in the combinational logic circuit . a described master / slave clock approach allows the scan flip - flop latch to support receiving into a scan chain a sequence of test input data , execution of combinational logic matrix testing based on the test input data , and sequentially outputting test results to a test result register for comparison with expected results . the described scan flip - flop latch may be used along side unaltered output storage latches thereby allowing flexibility with respect to the number and placement scan chain test points within an integrated circuit . use of the described dual - use scan flip - flop latch results in a less complex circuit design , reduced circuit area requirements and improved reliability .