the present invention provides a row decoder of a semiconductor storage device that prevents an increase in a circuit area while maintaining a high operation speed . namely , the row decoder of the semiconductor storage device includes a word line selection circuit that has voltage application mos transistors for each of plural word lines , the voltage application mos transistors applying a normal voltage to the word lines corresponding to memory cells selected among plural memory cells positioned at a portion where the plural word lines intersect plural bit lines in a predetermined normal operation , and applying a high voltage in a predetermined high voltage operation ; and a level shift circuit that outputs the normal voltage or a ground voltage lower than the normal voltage in the normal operation , and that outputs the normal voltage or the high voltage in the high voltage operation , to the voltage application mos transistor .