a memory circuit is comprised of a memory cell of pnpn - equivalent 4 - layer construction , a selective input circuit composed of a pair of an npn transistor and a pnp transistor , and a read - out circuit for reading the information stored in the memory cell . the emitters of the transistors included in the selective input circuit are connected to one of the selective input terminals , the bases thereof to the other selective input terminal , the collector of one of the transistors to the write input terminal of the memory cell , and the collector of the other transistor to the input terminal of the read - out circuit . thus , both the writing and reading operations are controlled from the same selective input terminal , and power consumption of the selective input circuit in the holding mode is substantially zero .