a multivalued subtractor for processing a multiplication of a first data and a second data , which are one of binary logic and multivalued logic , includes a first and second input circuit . the first input circuit includes parallel inputs for binary logic and multivalued logic , and receives the first data . the first input circuit also outputs a first set of bit data representing the first data . similarly , the second input circuit includes parallel inputs for binary logic and multivalued logic , and receives the second data . the second input circuit also outputs a second set of bit data representing the second data . a subtracting circuit , connected to the first and said second input circuits , subtract the second set of bit data from the first set of bit data . a output circuit , connected to the subtracting circuit , converts the output of the subtracting circuit into data in binary logic and multivalued logic , in parallel , and outputs converted data in binary logic and multivalued logic , in parallel .