an apparatus comprising a first circuit and a second circuit . the first circuit may be conf igured to generate an address signal in response to a first ramp signal , a second ramp signal , and a format signal . the second circuit may be configured to generate the first and second ramp signals in response to a one or more control signals . the address signal may support a raster format when the format signal is in a first state and may support a macroblock format when the format signal is in a second state .