a method for bursting data in a wide i / o memory device with improved access time and reduced data - bus complexity . the memory read operation accesses n bits of data which are output in eight n / 8 - bit i / o words in any particular order in accordance with the burst base address and linear or interleaved burst sequence controls . for every i / o , eight bits of data are presented to a 9 - to - 1 multiplexer . the first of eight bits in the burst sequence is the access time - limiting bit and is preselected by the burst base addresses of the 9 - to - 1 multiplexer . subsequent bits in the burst sequence have extra half - cycles to be output , and use look - aside 8 - to - 1 multiplexers controlled by a burst counter with timings synchronized to the burst data clock timings .