a configuration of logic elements enables existing serial - in - parallel - out shift registers to perform their own bit count , report the receipt of a valid transmission consisting of an expected number of bits and report the receipt of an invalid transmission consisting of greater than the expected number of bits . logic elements additional to the foregoing enable sipo shift registers to receive valid transmissions of varying expected numbers of bits . special purpose integrated circuits are disclosed which also contain the aforementioned configurations of logic elements . newly designed sipo shift registers which contain within them the foregoing configurations of logic elements are further disclosed . potential messages of multiple acceptable message lengths are accommodated . some embodiments are equipped with tri - state data outputs .