an architecture for testing a plurality of circuits on an integrated circuit is described . the architecture includes a tap linking module located between test pins on the integrated circuit and 1149 . 1 test access ports of the plurality of circuits to be tested . the tap linking module operates in response to 1149 . 1 scan operations from a tester connected to the test pins to selectively switch between 1149 . 1 taps to enable test access between the tester and plurality of circuits . the tap linking module &# 39 ; s 1149 . 1 tap switching operation is based upon augmenting 1149 . 1 instruction patterns to affix an additional bit or bits of information which is used by the tap linking module for performing the tap switching operation .