a fifo memory is disclosed which includes a plurality of memory cells , a mode circuit designating a first or a second mode in response to a mode signal supplied thereto , a selection circuit for selecting a first number of the memory cells each time a clock signal is generated in the first mode and for selecting a second number of the memory cells each time the clock signal is generated in the second mode , the first number being different from the second number , and an access circuit for accessing the selected memory cells to write data thereinto and to read data therefrom , whereby the number of memory cells to accessed is changeable in the mode to be performed .