according to an one aspect of the present invention , it is provided a non - volatile semiconductor memory device comprising : a first n type well ; a plurality of p type non - volatile memory cells arranged in matrix and formed in the n type well ; a plurality of sub - bit lines , each of the sub - bit lines being connected to drains of the p type non - volatile memory cells in a respective one of columns of the matrix ; a first p type well ; and a plurality of n type selection transistors , each of the selection transistors selectively connecting a respective one of sub - bit lines to a corresponding one of main bit lines .