a digital signal processor structure by performing length - scalable fast fourier transformation discloses a single processor element , and a simple and effective address generator are used to achieve length - scalable , high performance , and low power consumption in split - radix - 2 / 4 fft or ifft module . in order to meet different communication standards , the digital signal processor structure has run - time configuration to perform for different length requirements . moreover , its execution time can fit the standards of fast fourier transformation or inverse fast fourier transformation .