an improved automated testing system that decreases the number of test signals that must be stored in the tester pattern memory for a timed test pattern . in the present invention , a timed test pattern is controlled by a timing generator operable to change the timing interval of individual test cycles during the timed test pattern between first and second timing intervals , thereby decreasing the number of test signals stored in pattern memory for the timed test pattern . the method and apparatus of the present invention can be implemented to test integrated circuits comprising circuitry operating in first and second time domains wherein the first and second timing intervals of the timed test pattern correspond to the first and second time domains of the circuit , respectively .