a system is provided for a display of ct cine images stored in a hybridized memory including both dynamic random access memory and video random access memory frame buffer . the system includes memory address space which is allocated between the vram and dram . non - linear , chained direct memory access control provides a system to write a series of 640 × 512 pixel images directly from the frame buffer at 60 frames per second . the chaining provides a means for skipping over unused addresses at the end of a display line , thus maximizing utilization of expensive vram memory .