a semiconductor device has multilevel memory cells , each cell storing at least three levels of data each . the multilevel memory cells are arranged so as to correspond to a physical address space , each cell storing 2 n levels of data each expressed by n number of bits . a logical address is converted into a physical address of the physical address space . a judgement is made as to whether a logical address space including the logical address matches the physical address space . when matched , the most significant bit x 1 is specified by performing a single comparison operation using a reference value . the specified bit is output from one of the cells corresponding to the physical address . if not matched , the bits are specified by performing multiple comparison operations using different reference values .