a simplified boundary scan test method capable of performing boundary test scanning of semiconductor chips . the test method includes providing valid test data to a first terminal of the semiconductor device and purposely providing invalid test data to a second terminal of the semiconductor device in a predetermined pattern algorithm . preload data is also preloaded onto the semiconductor device . the valid and invalid test data is then captured in the semiconductor device . if the captured data is as expected , it signifies that there is no problem with the boundary scan circuitry on the device . on the other hand if the captured data differs from what is expected , it signifies that there may be a problem with the boundary scan circuitry .