apparatus and method for expediting the alignment of the fraction portion of operands in floating point operations . the alignment is performed in the arthmetic logic unit where the argument of the operand a exponent is subtracted from the argument of the operand b exponent . because the result b - a can be a negative quantity , the result a - b can also be required . the arthmetic logic unit of the present invention provides additional apparatus for simultaneously determining b - a and a - b . the additional apparatus includes components in the propagate bit and generate bit cell for determining an auxiliary generate bit ; an additional carry - chain array for combining the carry - in signal , the propagate bit and the auxiliary generate bit ; and selection circuits for selecting the appropriate result .