according to disclosed embodiments , a semiconductor memory is disclosed that includes a memory array connected to a number of registers by a transfer bus of reduced size . reduction of transfer bus size can be achieved without a significant increase in data processing speed . according to one embodiment a semiconductor memory can include a number of cell regions arranged in a first direction . sense amplifier banks are connected to the cell regions and a transfer bus is disposed over the cell regions in the first direction . the transfer bus includes switching circuits corresponding to each cell region . the switching circuits can divide the transfer bus into a number of transfer bus line portions .