a system for generating crc code words associated with data ranging up to w - bytes in width . the system is an iterative approach for providing a crc calculation circuitry with the crc calculation being subdivided into a blocks with selectable bus widths which blocks can be cascaded to provide calculation for a parallel bus width of any arbitrary number of bytes . the circuitry includes a first plurality of serially coupled code - generation blocks each for generating a crc value based on data input to each block ; a second plurality of parallel coupled code - generation blocks each for generating a crc value based on data inputs , and , a device for selecting particular crc code generation blocks in the first and second pluralities to be included in a crc calculation based on the data input such that any number of data input bytes may be processed .