a pll architecture is disclosed which incorporates a coarse adjustment feedback loop and a fine adjustment feedback loop together providing a combined error signal to a single vco . the coarse adjustment feedback loop includes two digital counters set to divide the vco output frequency by two different numbers . the outputs of the counters are coupled to the inputs of respective phase - frequency detectors , and the pump - up output of one of the detectors and the pump - down output of the other detector are used as the coarse adjustment pump - up and pump - down signals , respectively , in the coarse adjustment feedback loop . the coarse adjustment feedback loop thereby establishes a frequency range limitation for the fine adjustment feedback loop .