the present disclosure relates to semiconductor manufacturing and the teachings of the present disclosure may be embodied in a semiconductor chip with an interconnect monitor . some embodiments may include arrays of diodes on the semiconductor chip ; each diode with a stack of vertical interconnects and metal contacts , the stack and the diode connected in series and control mechanisms for addressing the diodes . the control mechanisms may include first inverters for applying either a high or a low voltage to columns of the diode stacks , connected at one end of each diode stack . each first inverter may include reverse logic receiving a reverse logic signal and configured to invert a logic signal fed to the device for applying a relatively high or low voltage and second inverters for applying either a high or a low voltage to rows of the diode stack in the one of the plurality of arrays , connected at a second end of said diode stack , wherein each second inverter comprises reverse logic receiving an inverted reverse logic signal and configured to invert a logic signal fed to the device for applying a relatively high or low voltage .