a dram memory array is disclosed that uses a current limiting circuit employing current feedback to clamp the current flow to reduced levels than were previously possible . the current limiting circuit comprises a long length , depletion mode transistor that has its gate voltage reduced when row - to - column shorts exist to limit the bleed current . an alternative embodiment uses a p - channel fet in series with the depletion mode transistor and has its gate tied to a negative supply and passes current until both digit lines approach approximately 0 . 3 volts .