potential lithographic hot spots associated with a lithographic level are marked by a marker layer identifying a marked region . multiplicate layers are generated for each design shape in that lithographic level in each marked region . each multiplicate layer includes a different type of variant for each design shape in the lithographic level . the different types of variants correspond to different design environments . lithographic simulation is performed with each type of variants under the constraint of long range effects , such as pattern density , provided by adjacent shapes in the lithographic level . in each marked region , the results of lithographic simulations are evaluated to determine an optimal type among the variants . the optimal type is retained for the lithographic level in each marked region , thereby providing a chip design layout in which various marked regions can include different types of variant shapes to provide local lithographic optimization .