a flip - flop circuit is provided for use in a phase - locked loop circuit , the flip - flop having two signal paths for selecting a vco output during velocity lock and phase lock . the two signal paths comprise identical environments and therefore eliminate the phase step exhibited by prior art designs in shifting between velocity lock and phase lock . the circuit is also useful in any application where a clock to output delay of a flip - flop connected for normal operation , must have its propagation delay matched to a circuit which simply delays a signal by the same amount .