in a microprocessor including a data memory device a simple checking circuit is provided for reading out the data onto a data bus line to check whether the data must be debugged . the checking circuit reads out data stored in an accumulator , register , etc . onto the data bus line . the checking circuit allows the microprocessor to operate normally in the absence of a checking signal and respectively connects the accumulator , register , or ram outputs to the data bus in accordance with the timing signals from the microprocessor timing signal generator in the presence of the checking signal . a program counter of the microprocessor is also inhibited from incrementing when the checking signal is present .