a reconfigurable register array structure allows an agent to transmit data from a single channel or in bundled form from multiple channels . the structure makes economical use of valuable chip space by reducing the size of the overall register array system . a coalescing prestage is used to collect data from single channels or from multiple channels and to multiplex the data , based on a priority scheme , to supply the data to a primary stage of first - in - first - out register arrays . the coalescing prestage may include one or more first registers , a delay register , multiplexers to select outputs of the first registers , and multiplexers to select outputs of the delay register . alternatively , the coalescing prestage may include one or more register array structures , each such structure having independent write ports , one for each channel . data coalesced in the coalescing prestage is provided to a primary stage . the primary stage may include one or more logical register arrays configured as one physical array . separate write pointers may be used to ensure data from a particular channel is provided to the correct location in the physical array .