a method of power electronic packaging includes a practicable and reliable method of fabricating power circuit modules and associated connections that are compatible with the standard top layer metalization of commercially available power devices . a planar single - or multi - layer membrane structure is attached to a carrier frame , and a via pattern is formed in the membrane . power devices are aligned and attached to the planar membrane structure ; a top layer interconnect structure is formed by metalizing the vias and the film ; and a circuit is formed by patterning a deposited metal layer . the carrier frame is removed , and upper and lower thermal base plate sub - assemblies are attached to the power device - on - membrane structure . the planar device - on - membrane structure accommodates different types of power devices having variations in thickness . the thermal base plate sub - assemblies may include integral , high - performance heat exchangers for providing a low thermal resistance path to the ambient .