a process of fabricating the storage capacitor of a dram memory ic device having increased electrode surface area is disclosed . the hemispherical - grain silicon layer used to effect the area increase does not suffer stripping - off during the process of removal of its native oxide . the prevention of the stripping - off is achieved by the employment of a amorphous silicon layer underlying the hemispherical - grain silicon layer . the amorphous silicon layer improves the adhesiveness of the hemispherical - grain silicon layer , thereby preventing its stripping - off .