in some embodiments , the present invention is directed to methods that involve the combination of step - and - flash imprint lithography with a multi - tier template to simultaneously pattern multiple levels of , for example , an integrated circuit device . in such embodiments , the imprinted material generally does not serve or act as a simple etch mask or photoresist , but rather serves as the insulation between levels and lines , i . e ., as a functional dielectric material . after imprinting and a multiple step curing process , the imprinted pattern is filled with metal , as in dual damascene processing . typically , the two printed levels will comprise a “ via level ,” which is used to make electrical contact with the previously patterned under - level , and a “ wiring level .” the present invention provides for the direct patterning of functional materials , which represents a significant departure from the traditional approach to microelectronics manufacturing .