a semiconductor structure having a body capacitance plate , which is formed with a process that assures that the body capacitance plate is self - aligned to both the source line diffusion and the bitline diffusion is provided . thus the amount of overlap between the sl and the bitline diffusions and the body capacitance plate is precisely controlled . more specifically , the present invention forms the structure of a 1t - capacitorless soi body charge storage cell having sidewall capacitor plates using a process that assures that there is 1 ) minimal overlap between plate and source / drain diffusions , and 2 ) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances . the inventive cell results in larger signal margin , improved performance , smaller chip size , and reduced dynamic power dissipation relative to the prior art .