a receiver direct current offset correction loop circuit digitizes the baseband analog control voltage using an analog - to - digital converter block 160 , which is then processed at control block to drive compensation circuitry 164 in a classic feedback configuration . the dcocl is augmented by an independent automatic gain control circuit that utilizes the same control signal . the agc circuit includes a multiplicity of adjustable gain stages with threshold and characteristic response that is controlled by agc control block . both the agc and dcocl circuits are dynamically configured for optimum complimentary operation via the microprocessor depending on the receiver &# 39 ; s operating environment and protocol requirements . subsequent direct current voltage drift is detected by the digital signal processor block which in turn flags the microprocessor to reinitiate the correction sequence when needed . subsequent to the microprocessor controlled hardware correction sequence , the dsp digitally equalizes any remaining offset errors in the recovered data through a multiplicity of compensation algorithms optimized to specific operating environments . this provides for optimum correction of the baseband dc offsets with minimal degradation of receiver performance .