a method for generating stimuli and test responses for testing faults in a scan - based integrated circuit in a selected scan - test mode or a selected self - test mode , the scan - based integrated circuit containing a plurality of scan chains , n clock domains , and c cross - clock domain blocks , each scan chain comprising multiple scan cells coupled in series , each clock domain having one capture clock , each cross - clock domain block comprising a combinational logic network . the method comprises compiling the scan - based integrated circuit into a sequential circuit model ; specifying input constraints on the scan - based integrated circuit during a shift and capture operation ; specifying a clock grouping to map the n clock domains into g clock domain groups , where n & gt ; g & gt ; 1 ; transforming the sequential circuit model into an equivalent combinational circuit model according to the input constraints and the clock grouping ; and generating the stimuli and test responses on the equivalent combinational circuit model according to the input constraints .