a rom is provided with sufficient input address terminals for receipt of a unique address for each data storage location , even though the number of rom input addresses exceeds the capacity of the processor and address bus . a dual mode read operation includes a random address mode for randomly accessing the rom and a sequential address mode for accessing sequentially stored data strings at a high access rate . a first portion of the bus addresses are allocated as random reading mode bus addresses , the bus addresses having direct correspondence with rom addresses . other bus addresses are allocated as sequential reading mode bus addresses for addressing the rom in sequential rom address order for reading data . successive output by the processor of the same sequential reading mode bus address effects application to the rom of sequentially numbered rom addresses . the first numbered address of the plurality of the sequential rom address string is loaded as data into at least one counter . processor output of the sequential reading mode address effectuates application of the contents of the counter as an address to the rom and increments the counter so that a successive output of the same address by the processor causes the incremented address to be applied to the rom . this arrangement has particular applicability in vehicle diagnostics equipment .