a programmable array logic device including a programmable logic array , at least one register pair , a multiplexer coupled to the register pair so that they can share a common i / o pin , and an observability buffer for controlling the multiplexer . a dual clock buffer is provided so that registers within the register pair can be clocked singly when in a preload mode or together when in a logic or verification mode . when in the logic mode , either the output of a buried state register or a output register is observed at the i / o pin under the control of a product term generated by the logic array . when in the preload mode the register to be preloaded is selected by an externally provided preload select signal . in the verification mode , which typically follows a programming mode , individually selected product terms within the logic array can be observed by clocking them into the register pairs .