a row address detection circuit includes a fuse bank , including a plurality of fuses connected to a common node . a precharge circuit is connected to bias the common node at a supply voltage . the fuse bank is also coupled through an isolation circuit to a buffer circuit . selected ones of the fuses are blown in a pattern corresponding to an address of a defective circuit to enable a redundant circuit to be substituted for the defective circuit . the isolation circuit allows the buffer circuit to measure the node voltage to determine if an input to a group of address select lines corresponds to the address of the defective circuit , yet isolates the buffer circuit from the common node to prevent partially blown fuses from placing an excessive load on the buffer circuit . in one embodiment , the isolation circuit is realized with a pair of transistors of opposite channel type coupled for synchronous switching to provide substantial isolation while minimizing voltage drop .