apparatus whereby data processing units exchange information with each other through a common memory without delay caused by limiting access to the memory to one data processing unit at a time . the invention includes a pair of random access memories ; a first logic circuit controlled by one of the data processing units and the address signals from both dpus ; first and second sets of gates controlled by the first logic circuit to allow one dpu access to one ram while the other dpu has access to the other ram ; and a second logic circuit to coordinate operation of the dpus so that each dpu has read / write access to one or the other of the rams at all times . in operation , one dpu has access to one ram while the other dpu has access to the other ram . at the appropriate time , as determined by the handshake logic circuitry , the dpu access is switched between rams .