a multi - priority encoder includes a plurality of interconnected , single - priority encoders arranged in descending priority order . the multi - priority encoder includes circuitry for blocking a match output by a lower level single - priority encoder if a higher level single - priority encoder outputs a match output . match data is received from a content addressable memory , and the priority encoder includes address encoding circuitry for outputting the address locations of each highest priority match line flagged by the highest priority indicator . each single - priority encoder includes a highest priority indicator which has a plurality of indicator segments , each indicator segment being associated with a match line input .