a synchronous semiconductor memory device has a read data bus for transferring data from a memory cell array to a read amplifier , and a write data bus for transferring data from a write driver to the memory cell array . to control equalization of the read and write data buses , an internal control clock signal is driven to a first level in delayed synchronization with an external clock signal , to a second level in synchronization with the external clock signal at the end of write operations , and to the second level in synchronization with a read amplifier control signal during read operations . the read and write data bus equalization times can therefore be separately optimized , enabling the memory to operate at a higher clock frequency than if the internal control clock signal were to be generated in the same way during both read and write operations .