a method of designing a power switch block for an integrated circuit layout in a predefined integrated circuit technology is disclosed . the power switch block includes a segment comprising a plurality of spaced parallel conductors each having a predefined height in said technology , a stack of a first power switch of a first conductivity type and a pair of drivers for respectively driving the first power switch and a second power switch , said drivers having predefined dimensions in said technology , and the second switch of a second conductivity type . the method comprises providing respective predefined width / length ratios for said power switches ; determining a total height of the segment from the sum of the predefined heights of the individual conductors and respective spacings between said individual conductors , determining the height of the first transistor from the difference between the total height and the predefined driver height ; determining the width of the first transistor from the combined predefined widths of the pair of drivers ; optimizing the first power switch layout within its determined height and width based on its predefined width / length ratio ; and optimizing the second power switch layout based on its predefined width / height ratio .