an integrated processor is provided with a memory control unit having refresh queue logic for refreshing dynamic random access memory banks during idle memory cycles . the refresh queue logic includes a queue counter and allows the refresh requests to be given a lower priority than other memory transactions until the required refresh rate is in danger of being violated . at this lower priority the refresh requests are honored and retired from a refresh queue only in the absence of other memory transactions . in the event that the refresh queue becomes full , top priority is given to the execution of a refresh request . in this case , a refresh request is honored and retired from the queue immediately after the conclusion of the current memory transaction . this queuing mechanism allows the refresh requests to be buffered until idle memory cycles are available or until absolutely necessary to prevent the violation of refresh timing constraints .