a non - volatile memory device includes an array of flash memory cells therein and a voltage generator . the voltage generator is configured to generate a program voltage , a pass voltage , a blocking voltage and a decoupling voltage during a flash memory programming operation . the blocking voltage is generated at a level that inhibits inadvertent programming of an unselected memory cell . this voltage level of the blocking voltage is set so that vdcp & lt ; vblock ≦ vpass & lt ; vpgm . the decoupling voltage has a magnitude that is greater than a maximum threshold voltage of an erased memory cell in the array and less than a minimum threshold voltage of a programmed memory cell in the array . a row selection circuit is also provided . this row selection circuit is electrically coupled to word lines in the array and to the voltage generator . the row selection circuit is configured to route the program , blocking , decoupling and pass voltages from the voltage generator to first , second , third and fourth word lines in the array , respectively , where the second word line is spaced between the first and third word lines .