semiconductor wafer processes employing two and three masks are disclosed for fabricating a plurality of insulated gate field effect transistors to be used singly as discrete devices or interconnected as integrated circuits on the wafer by means of diffused regions at a first level and a composite of polysilicon and metal silicide layers at a second level . the first mask of the two - mask process is used in opening windows through a thick oxide layer covering the wafer for the gate and diffused regions including the source and drain regions . after forming a thin oxide layer in these windows , the wafer is coated with successive layers of polysilicon and silicon nitride . then , a second masking operation yields a pattern out of the polysilicon - nitride layer including gate electrodes and a top - lying interconnection level which abuts to openings etched through the thin oxide layer . doping impurities are diffused therethrough to form source and drain regions and crossunders . after etching the nitride layer a silicide forming metal is deposited and sintered to form a silicide layer on all exposed silicon surfaces lowering the sheet resistance of the polysilicon layer and joining the interconnection pattern with the source and drain regions . the process is completed by removing the remaining unreacted metal using a maskless aqua regia etch .