an apparatus causes invalid data to be read again from a memory device before being read by a device . a transaction queue stores pending and dispatched device transactions , the queue includes an input for receiving transactions , an output for dispatching transactions , a pointer for pending transactions , and a pointer for dispatched transactions . a master controller responds to an invalid data signal by preventing the transaction queue from dispatching pending transactions to the memory device , by causing the transaction queue to dispatch again the device read transaction which resulted in the invalid data and , subsequently , by causing the data which was read again from the memory device to be accepted by the destination device , by setting the dispatched transaction pointer to the pending transactions pointer , and by enabling the transaction queue to dispatch pending transactions to the memory device .