an sram circuit structure and method for reducing leakage currents and / or increasing the speed of the devices . various forms of sram devices may be fabricated utilizing the techniques , such as single port and dual port ram devices . by way of example the sram structure utilizes separate write and read lines , splits the circuit into portions which can benefit from having differing threshold levels , and can allow splitting read path transistors for connection to a first terminal and a virtual node connected to a source transistor . the structure is particularly well suited for forming transistors in a combination of nmos and pmos , or solely in nmos . memory arrays may be organized according to the invention in a number of different distributed or lumped arrangements with the reference read paths and sense blocks being either shared or dedicated .