a memory device including a balanced switching circuit and methods for controlling an array of transfer gates . the balanced switching circuit comprises a plurality of transfer gates . the plurality of transfer gates are arranged in n rows and n columns with the n transfer gates in each row connected in series between a first signal terminal and a second signal terminal . each one of n clock terminals is coupled to a respective control terminal of only one transfer gate in each row and only one transfer gate in each column . the transfer gates are selectively clocked or activated in response to clock signals to couple the first signal terminal to the second signal terminal such that the switching speed is independent of the order in which the individual series connected pass transistors or transfer gates are activated .