a dual access dram includes first and second sets of data lines . by adding a second set of multiplexing transistors to data lines that are controlled with timing and addressing similar to an existing set of multiplexing transistors , data can be transferred to a second subarray by way of an additional set of data lines . the second set of data lines are additional internal read / write lines used in addition to the normal set of data lines . the second set of data lines are designed to have short lengths with correspondingly low capacitance so that additional loading on the sense amplifiers is small .