a synchronous dynamic random access memory integrated circuit configured to receive an external reset signal for resetting the ic includes a low voltage mos input buffer configured to generate a buffered reset signal rst from the external reset signal . the sdram ic further includes a reset circuit is configured to generate an internal reset signal reset_en from the rst signal , a clock enable signal cke which indicates a time when the sdram is ready to receive an external command , and a mode register programming signal mrs p which indicates a time when a mode register is to be loaded with data . the reset circuit activates the reset_en signal in response to the external reset signal becoming active to thereby start an internal reset interval during which one or more circuit blocks in the sdram ic are powered down .