a dynamic system coupled with “ pre - silicon ” design methodologies and “ post - silicon ” current optimizing programming methodologies to improve and optimize current delivery into a chip , which is limited by the physical properties of the connections . the mechanism consists of measuring or estimating power consumption at a certain granularity within a chip , converting the power information into c4 current information using a method , and triggering throttling mechanisms where applicable to limit the current delivery per c4 beyond pre - established limits or periods . design aids are used to allocate c4s throughout the chip based on the current delivery requirements . the system coupled with design and programming methodologies improve and optimize current delivery is extendable to connections across layers in a multilayer 3d chip stack .