the invention describes a structure and a process for providing esd semiconductor protection with reduced input capacitance . the structure consists of heavily doped p + guard rings surrounding the i / o esd protection device and the vcc to bss protection device . in addition , there is a heavily doped n + guard ring surrounding the i / o protection device its p + guard ring . the guard rings enhance structure diode elements providing enhanced esd energy discharge path capability enabling the elimination of a specific conventional vss to i / o pad esd protection device . this reduces the capacitance seen by the i / o circuit while still providing adequate esd protection for the active circuit devices .