a memory test control circuit in an mml integrated circuit is connected to a first pad which receives memory control signals to control first and second memories of the mml circuit . the memory test control circuit is also connected to a second pad which receives memory data signals for the first and second memories . the memory test control circuit is also connected to the logic block and to the first and second memories . the memory test control circuit transmits the memory control signals and the memory data signals to the first and second memories when the first and second memories are tested and transmits the memory control signals and the memory data signals to the logic block during normal operation of the mml integrated circuit . accordingly , the memory test control circuit allows pass - through of memory data and control signals directly to the memory blocks during test mode , and provides the memory data and control signals to the logic block during normal operations .