a flash memory array with self - limiting erase for preventing over - erasure utilizes a self - limiting - rase floating gate transistor coupled to the memory array or to each row of memory cells . the self - limiting - erase transistor has a smaller threshold voltage than the memory cells . when all memory cells or one row of memory cells are erased , the drain of the transistor is connected via a feedback path to all word lines of the memory array or to the corresponding word line for that row of memory cells . when the self - limiting - erase transistor is turned on due to full erasing , the potential of the word lines is pulled up to the erasing voltage which is applied at the sources of the memory cells , thereby the erase operation is stopped automatically .