a system on chip contains a core circuit and an input / output circuit embedded with an array of single - poly erasable programmable read only memory cells , each of which comprises a first pmos transistor serially connected to a second pmos transistor . the first and second pmos transistors are both formed on an n - well of a p - type substrate . the first pmos transistor includes a single - poly floating gate , a first p + doped drain region and a first p + doped source region , the second pmos transistor includes a single - poly select gate and a second p + doped source region , and the first p + doped source region of the first pmos transistor serves as a drain of the second pmos transistor .