the invention is directed to an apparatus and method for predicting the number of bits which must be taken into account to normalize the result of a floating point addition or subtraction . the apparatus and method employ : a low precision floating point adder / subtractor , a priority encoder that determines the position of the most significant non - zero bit to generate the normalization amount and preround logic which pre - shifts a rounding bit in the opposite direction of normalization . the method and apparatus operate in parallel with a full precision floating point adder to eliminate the need for a full - precision floating point normalization calculation and rounding computation in most circumstances . the normalization amount for successful low - precision floating - point addition / subtraction is calculated by the time the full - precision floating - point addition / subtraction stage occurs . moreover , the pre - round logic supplies a carry bit to the full - precision adder / subtractor thus saving the time associated with a full - precision rounding bit addition . thus , this low - precision floating - point addition / subtraction technique results in a significant enhancement of performance in floating - point addition / subtraction .