a digital phase detector that stores four sequential digital samples in a shift register . the contents of the shift register is evaluated at one half the clock frequency which generated the digital samples . the digital phase detectors predicts what the value should be for each of the two middle samples in the shift register . the predicted value and the actual value of each middle are used to generated a correction signal . the correction signals for the two middle samples are then added to produce a total correction signal which is to be used in controlling the phase and frequency of the voltage controlled oscillator in the phase locked loop generating the clock that controls the generation of the digital samples .