the present invention relates to a memory device having reduced access time of memory cells in a test mode . the memory device forms , in the test mode , read data d r by applying ex - or processing to a plurality of data read from a memory cell array 11 by a data processing circuit 5 , to provide the formed data to the outside through a data output circuit 6 . the timing of the output of data to the outside is delayed , by delay circuit 12 in the test mode , than that in the normal operation by a time period corresponding to time required for the ex - or processing in data processing circuit 5 . consequently , output of invalid data to the outside can be prevented , and thus access time of valid data can be reduced .