an integrated circuit is provided that includes a first internal circuit using a first internal clock signal whose first edges are active . the first internal circuit includes a test cell having an input and an output , a first transmission line connected to the input of the test cell , and a second transmission line connected to the output of the test cell . the test cell includes first and second latches and a selection circuit . the first latch stores either information on the first transmission line or information received from another test cell , and the second latch selectively receives the information stored in the first latch . the selection circuit provides to the second transmission line either the information on the first transmission line or the information stored in the second latch . the test cell also includes means for storing the information on the first transmission line in the second latch during second edges of the first internal clock signal when the test cell is not in test mode . in a preferred embodiment , the second latch is a transparent latch . a method for transmitting a logic signal in an integrated circuit is also provided .