a method for manufacturing electronic devices , such as memory cells and lv transistors , with salicided junctions , that includes : depositing an upper layer of polycrystalline silicon ; defining the upper layer , obtaining floating gate regions on first areas , lv gate regions on second areas of a substrate , and undefined regions on the first and third areas of the substrate ; forming first cell source regions laterally to the floating gate regions ; forming lv source and drain regions laterally to the lv gate regions ; forming a silicide layer on the lv source and drain regions , on the lv gate regions , and on the undefined portions ; defining hv gate regions on the third areas , and selection gate regions on the first areas ; forming source regions laterally to the selection gate regions , and source and drain regions laterally to the hv gate regions .