a self - timed multiplier unit includes a multiplier and a clock generator . the multiplier has a first set of semiconductor circuits in a critical path . the clock generator has a second set of semiconductor circuits configured to control a clock period of said clock generator selected to set a clock period longer than the propagation delay through the critical path of the multiplier . the clock generator may include a delay circuit having a delay to set the clock period longer than the propagation delay through the critical path of said multiplier . the clock generator uses circuit with identical logical design including the same standard cells , the same logic design or the same floor plan . close matching of these circuit causes the multiplier and the clock generator to experience the same pvt speed variations .