a system and method is disclosed for adaptively adjusting a duty cycle of a signal between a first and second chip in a 3d architecture / stack for adaptively calibrating a chip in a 3d architecture / stack . in one embodiment , the system includes a first chip and a second chip located within the 3d chip stack , wherein the first chip generates a calibration signal , the second chip receives the calibration signal and compares it to a reference signal to generate a comparison signal that further compared to a reference duty signal to generate a reference duty comparison signal , that is then provided to the first chip to generate a drive signal that adjusts a duty cycle of the calibration signal .