low power design is a critical concern and metric for integrated circuits . during scan based manufacturing test , electric power dissipation becomes even more critical as the chip may not have been designed to tolerate excessive switching during scan test . excessive electric power dissipation during scan test can result in excessive voltage variations , reduced noise margins and other signal integrity issues which could invalidate the test or may lead to premature chip failure . power dissipation during test is minimized by selecting particular values for the unused care - bits in values of the test vectors on a probabilistic basis to minimize switching , while preserving test vector quality .