the present invention relates to a finite field multiplier used for implementing an encrypting algorithm circuit , thereby minimizing power consumption and circuit area in implementing the finite field multiplier with a lfsr structure . the finite field multiplier of the present invention is an operator performing a modular operation on the multiplication result of two data represented on a polynomial basis in a galois field into an irreducible polynomial . the lfsr structure is a serial finite field multiplication structure , and has a merit over an array structure and a hybrid structure in application to systems that are limited in size and power due to its simplicity of circuits and also its capability of being implemented in a small size .