the invention assures data consistency at a time of data update . also , the invention results in a reduction in the access time required to store incoming data . in response to an equality signal from a comparator circuit of a write buffer circuit which is then in an active level , data is immediately read out from a data buffer store having an address corresponding to the equality signal . a unidirectional tristate buffer is provided for temporarily disconnecting an address bus extending between a cpu and the write buffer circuit , again when such equality signal is in an active level . similarly , a bidirectional tristate buffer is provided for temporarily disconnecting a data bus extending between the cpu and the write buffer circuit . at times a local controller may take over command of buffer storage of data , with an interrupt of the local controller if the central processor seizes command .