a flash memory using a pre - sensing amplifier coupled to receive differential inputs from a pair of memory cells of said flash memory array and to generate a differential output from the pre - sensing amplifier . the differential output is coupled to a bus , which is also coupled to a post - sensing amplifier . the differential configuration on the bus allows marginal voltage differences to be detected by the post - sensing amplifier so that logic states from the flash memory can be sensed without the bus transitioning to half of the supply voltage .