a semiconductor memory , such as dynamic random access memory , is provided for replacing a defective memory cell with a spare memory cell . the dram includes a main section which has a memory cell array with a plurality of memory cells arranged in an array . a spare section having a spare memory cell array also includes a plurality of memory cells arranged in an array . an address decoder specifies addresses , respectively , of the main section array and the spare section array . a defective bit replacement control circuit is connected to the address decoder and includes a plurality of electrically rewritable nonvolatile memory cells . the address decoder conducts a change - over operation for specifying an address of the first or second arrays according to a storage state , i . e ., contents , of electrically rewritable nonvolatile memory cells .