a method of and apparatus for continuously checking a cmos sram memory system . each memory cell has a bistable circuit for retaining the state of the cell , along with a totally redundant bistable circuit . added circuitry provides continuous comparing of the binary state of the bistable circuit and the redundant bistable circuit within the memory cell . this testing is performed at a low level within the memory cell eliminating the power dissipation and size requirements associated with additional drivers . an error line is shared amongst a number of memory cells . by continuously monitoring in this manner , the time of failure as well as the fact of failure can be determined .