a desired fifo buffer fill level is continuously derived during mapping or demapping of plesiosynchronous data signals into synchronized data signals , or vice - versa . one of j predefined integer values i i is repetitively consecutively produced during each consecutive one of j fifo buffer write clock cycles , where i = 1 , . . . , j and where j and the integer values i i are selected such that ∑ i = 1 j ⁢ ⁢ i i j closely approximates the number of bits read from the fifo buffer per fifo buffer write clock cycle . during each k th consecutive fifo buffer write clock cycle , a bits_read value i k + i k - 1 is produced where k = 1 , . . . , p ; a bits_written value is produced ; a gap_pattern value is derived by subtracting the bits_read value from the bits_written value ; and , the gap_pattern is added to a predefined value representative a fifo buffer center fill level to produce the desired fifo buffer fill level .