an enhanced computer system architecture provides a processor supported by a general cache and a mini - cache wherein the mini - cache will supply requested data words not available in the general cache thus eliminating the extra clock periods necessary to access main memory . the mini - cache stores frequently used data words and is refilled concurrently during processor command execution and is settable for handling data words or code words or both . a data queue storage stores a block of words which duplicate words in main memory . if the requested address matches an address register block in the mini - cache , the data queue store will make the words in the data queue available to requests from the processor . the mini - cache also monitors the system bus for any &# 34 ; write &# 34 ; operations which might change the validity of the data in the address register block of the mini - cache . in this case , the data stored in the mini - cache is invalidated and cannot be used by the processor . additionally , the mini - cache can be added to or removed from system operations .