in a computer wherein a central processor and at least one peripheral controller have access to a memory , this latter is divided into two simultaneously accessible zones , namely a private zone accessible by the processor and a direct access zone accessible both by the processor and by the peripheral controller . a logic unit synchronizes the controller &# 39 ; s access to the direct access zone with the processor &# 39 ; s access to the private zone , the controller &# 39 ; s access being delayed , if necessary to occur simultaneously with the processor &# 39 ; s access . the peripheral controller &# 39 ; s access is thereby achieved without interruption of processor operations .