the inspection and measurement of critical dimensions of patterned features during the manufacture of sub - micron integrated circuits relies heavily upon the scanning - electron - microscope . this instrument is capable of quick , clean , and accurate measurements of features on large in - process silicon wafers . however , such features are frequently isolated from the electrical ground of the microscope by virtue of their circuit design . this creates a charge build up from the electron beam in the sem and causes distorted and indistinct images , incapable of being measured . also , such static charge build - up can be destructive to certain circuit elements . this invention teaches the use of independent inspection test structures , fabricated in wafer saw kerf regions or within designated test sites , especially designed to provide a reduction or elimination of charge build up during sem observation . the structures are built to follow conventional processing and carry the desired features to be examined at each successive process level . they are particularly useful for examining and measuring contact and via openings , and measuring interconnection metal line widths and spacings , including polysilicon structures .