a 2 - bit non - volatile memory transistor having a pair of isolated floating gate electrodes is provided . one of the floating gate electrodes is located over a first source / drain region , and a first adjacent end of a channel region . the other floating gate electrode is located over a second source / drain region and a second adjacent end of the channel region . a control gate extends over both floating gate electrodes and a centrally located portion of the channel region . the floating gate electrodes are independently programmed and independently read , thereby enabling the nvm transistor to effectively store 2 - bits of data .