a central processor through an asynchronous service processor , selectively resets an input / output channel designated in an instruction called clear channel that is executed by the central processor . as part of the execution of this instruction , the service processor also communicates a reset signal to the peripheral equipment associated with that channel in case the designated channel is malfunctioning and cannot relay a reset signal normally to the peripheral equipment associated with the designated channel . the reset signal for the peripheral equipment is supplied through a connection between the service processor and particular lines in i / o interface cables of that channel . programming routines that use the clear channel instruction are designed to preserve the integrity of data held by peripheral equipment that is associted with two channels when the peripheral equipment has exclusive affiliations with the designated channel . other systems that are eligible to communicate with the affiliated equipment are conditioned to a quiescent state before the reset operation is carried out , and are kept in that state until the affiliations are re - established .