a process for receiving a binary digital signal by a method for the reception of a binary digital signal , which may also have phase shifts , with a supplied clock that may have any desired phase position with respect to the digital signal and may deviate somewhat in frequency from the bit sequence frequency of the digital signal . from the clock there is formed over a delay chain a series of clocks , which have approximately equal phase intervals . short pulses are derived from the clocks . t12 ). upon the arrival of each edge of a digital signal that has been selected as the effective edge , there is derived a read pulse which may also be delayed , with which the presence of pulses may be determined through and gates . through sr flip - flops and and gates , clocks selected with the pulses that are present are switched through and or - linked for use as an input clock . the total delay of this process step is , if necessary , dimensioned in such a way by delaying the read pulse that the effective edge of the input clock occurs always one half clock period after the effective edge of the digital signal . an application of the invention is in synchronous switching matrices and in block switching .