various logic gates and methods for using such are disclosed herein . for example , some embodiments of the present invention provide parallel differential logic gates . such logic gates include two or more differential input pairs . the collectors of the first transistors in each of the differential pairs are all electrically coupled to an upper voltage via a first load resistor . similarly , the collectors of the second transistors in each of the differential pairs are all electrically coupled to an upper voltage via a second load resistor . depending upon the relative values selected for the first and second load resistors , the gate operates as an and gate or an or gate .