Why cache read miss is faster than write miss? <p>I need to calculate an array (writeArray) using another array (readArray) but the problem is the index mapping is not the same between arrays (Value at index x of writeArray must be calculated with value at index y of readArray) so it's not very cache friendly.</p> <p>However I can either choose if the loop browses readArray sequentially or writeArray sequentially.</p> <p>So here is a simplified code :</p> <pre><code>int *readArray = new int[ARRAY_SIZE]; // Array to read int *writeArray = new int[ARRAY_SIZE]; // Array to write int *refArray = new int[ARRAY_SIZE]; // Index mapping between read and write, could be also array of pointers instead indexes // Code not showed here : Initialization of readArray with values, writeArray with zeroes and refArray with random indexes for mapping between readArray and writeArray (values of indexes between 0 and ARRAY_SIZE - 1) // Version 1: Random read (browse writeArray/refArray sequentially) for (int n = 0; n &lt; ARRAY_SIZE; ++n) { writeArray[n] = readArray[refArray[n]]; } // Version 2: Random write (browse readArray/refArray sequentially) for (int n = 0; n &lt; ARRAY_SIZE; ++n) { writeArray[refArray[n]] = readArray[n]; } </code></pre> <p>I was thinking that cache read misses was more slower than write misses (because CPU needs to wait before reading complete if the next instruction depends of read data but for writing it doesn't need to wait for processing the next instruction) but with profiling it's seems that version 1 is faster than version 2 (version 2 is about 50% more slower than version 1).</p> <p>I tried also this :</p> <pre><code>// Version 3: Same as version 2 but without polluting cache for (int n = 0; n &lt; ARRAY_SIZE; ++n) { _mm_stream_si32(&amp;writeArray[refArray[n]], readArray[n]); } </code></pre> <p>Because I don't need to read values of writeArray so there is no reason to pollute the cache with written values but this version is more more slower than other versions (6700% more slower than version 1).</p> <p>Why write miss is slower than read miss ? Why bypassing cache for writing is more slower than using it even if we don't read these written data after ?</p>