Passing array from system verilog to VHDL <p>I have a code in VHDL which requires an array of elements as generic. COEF_LIST : coef :=(0,0,1,1,2,-2,1,-2,1)</p> <p>How do I send new set of COEF_LIST from my system verilog testbench to VHDL entity?</p> <p>Generic in VHDL is same as parameter in verilog.</p> <p>I declared coef as </p> <pre><code> parameter real COEFF[8:0] = '{0,0,1,1,2,-2,1,-2,1}; </code></pre> <p>in system verilog.</p> <p>I tried passing using (in my verilog testbench)</p> <pre><code> vhdl_entity #( .COEF_LIST(COEFF) ) </code></pre> <p>I get the following error</p> <pre><code> **.COEF_LIST(COEFF) | </code></pre> <p>ncelab: *E,CFIGTC (./vhdl_entity_tb.vams,41|36): VHDL generic vhdl_entity.COEF_LIST (../views/rtl/vhdl_entity.vhd: line 34, position 14) type is not compatible with Verilog. irun: <em>E,ELBERR: Error during elaboration (status 1), exiting.*</em></p> <p>This doesn't work. How do I make it compatible with VHDL? I am using incisiv 13.20.008 version</p> <p>Could anyone please suggest what to do?</p>