 <p>When I use Quartus II ver 15.0, assiging "don't care" to output is OK and generated area-efficient circuit.</p> <p>For example, if I synthesize this code, that :</p> <pre><code>module test1 ( input wire a, input wire b, output reg [3:0] s ); always @* begin case ({a,b}) 2'b00 : s = 4'b1000; 2'b01 : s = 4'b0100; 2'b10 : s = 4'b0010; 2'b11 : s = 4'b0001; default: s = 4'b0000; endcase end endmodule </code></pre> <p>Quartus generated a circuit which uses <strong>5 Logic Elements</strong>. <a href="https://i.stack.imgur.com/CaJOR.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/CaJOR.png" alt="not optimized"></a></p> <p>However, If I use "don't care" assignment in the code above:</p> <pre><code>module test1 ( input wire a, input wire b, output reg [3:0] s ); always @* begin case ({a,b}) 2'b00 : s = 4'b1xxx; 2'b01 : s = 4'b01xx; 2'b10 : s = 4'b001x; 2'b11 : s = 4'b0001; default: s = 4'b0000; endcase end endmodule </code></pre> <p>a circuit which uses only <strong>2 Logic Elements</strong> is generated. It's interesting that although the total logic elements are less used, the generated circuit seems to be more complex. <a href="https://i.stack.imgur.com/lBuCY.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/lBuCY.png" alt="optimized"></a></p> <p>I was wondering whether the generated circuit is correct. So I ran Quartus's simulator with the circuit which uses "don't care". The result is the simplest circuit we want. <a href="https://i.stack.imgur.com/uLD1U.png" rel="nofollow noreferrer"><img src="https://i.stack.imgur.com/uLD1U.png" alt="enter image description here"></a></p>