Calculating CPI with multi-level caches and hit/miss latencies <p>Consider a pipelined processor with just one level of cache. Assume that in the absence of memory delays, the baseline CPI of this processor is 2. Now assume that the percentage of memory instructions in a typical program executed on this CPU is 50% and the memory access latency is 150 cycles. Assuming that the I-cache delays are already accounted for in the baseline CPI, consider the following two alternatives for the D-cache design:</p> <p>Alternative 1: </p> <blockquote> <p>A small D-cache with a hit rate of 94% and a hit access time of 1 cycle (assume that no additional cycles on top of the baseline CPI are added to the execution on a cache hit in this case).</p> </blockquote> <p>Alternative 2:</p> <blockquote> <p>A larger D-cache with a hit rate of 98% and the hit access time of 2 cycles (assume that every memory instruction that hits into the cache adds one additional cycle on top of the baseline CPI).</p> </blockquote> <p>Question 1: </p> <blockquote> <p>Estimate the CPI metric for both of these designs</p> </blockquote> <p>I believe that the formula to answer this questions is:</p> <p>CPI = (Base CPI) + (D-Cache miss rate) + <s>(I-Cache miss rate)</s></p> <p>--D-Cache miss rate = (percent of memory accesses) * (Average Memory Access Time)</p> <p>-- --AMAT = (Hit access time) + (miss rate) * (miss penalty)</p> <p>And therefore: </p> <p>CPI = (Base CPI) + (percent of memory accesses) [(hit access time) + (miss rate)(miss penalty)]</p> <p>Question 2: </p> <blockquote> <p>Now assume that the L2 cache is also added to the system with the hit rate of 75% and access latency of 10 cycles. </p> </blockquote> <p>I'm not sure where to go with this. </p> <p>Does the addition of the L2 cache change the overall hit rate and access latency, and therefore, I simply change the hit rate and access latency variables in my original formula? </p> <p>Or do I change the formula to account for the L2 cache variables during misses in the L1 cache?</p>