 <p>Use a loop statement:</p> <pre><code>decode_process: process(clk) -- synchronous reset, no rst in sensitivity list begin if clk'event and clk = '1' then if rst = '1' then out_address &lt;= (others =&gt; '0'); else for i in 0 to 10 loop if i = to_integer(unsigned(in_address)) then out_address(i) &lt;= '1'; else out_address(i) &lt;= '0' ; end if; end loop; -- name: for i in 0 to 10 generate -- if (i = to_integer(unsigned(in_address))) then -- out_address(i) &lt;= '1'; -- else -- out_address(i) &lt;= '0'; -- end if; -- end generate name; end if; end if; end process; </code></pre> <p>Also notice <code>rst</code> was removed from the sensitivity list, it's written as a synchronous reset.</p> <p>A loop statement can be synthesized, see now rescinded IEEE Std 1076.6-2004 8.8.9, Syntax, Sequential statements, Loop statement or your particular synthesis vendor's tool documentation. The sequential statements found in a loop are replicated for each value of the loop parameter which is treated as a constant.</p> <p><strong>So what's the difference between generate iteration and loop iteration?</strong></p> <p>Simulation cycles emulate concurrency for signal assignments even in sequential statements (e.g. in a process). There are no dependencies between one if statement and another in the synthesized (unrolled) loop. They will be <code>i</code> number of <code>in_address</code> recognizers comparing <code>i</code> to in_address each providing one bit of <code>out_address</code>. The first one assigning <code>a(0)</code>, the second <code>a(1)</code>... In this case the loop statement will produce the same logic a generate statement would (using conditional signal assignment, although the sequential logic (clock) semantics would make it look awkward).</p> <p>Let's compare this to using a generate statement in a concurrent statement appropriate place:</p> <pre><code>architecture foo of address_decoder is function to_std_ulogic (inp: boolean) return std_ulogic is begin if inp = TRUE then return '1'; else return '0'; end if; end; begin decoder: for i in 0 to 10 generate out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end generate; end architecture; </code></pre> <p>The function <code>to_std_ulogic</code> taking a boolean argument has been added for brevity in the conditional signal assignment statement to <code>out_address(i)</code>.</p> <p>This looks nice and compact and may likely synthesize depending on the ability to use the function converting a boolean to a std_ulogic.</p> <p>However, it expands out for elaboration:</p> <pre><code>architecture fum of address_decoder is function to_std_ulogic (inp: boolean) return std_ulogic is begin if inp = TRUE then return '1'; else return '0'; end if; end; begin decoder0: block constant i: integer := 0; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder1: block constant i: integer := 1; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder2: block constant i: integer := 2; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder3: block constant i: integer := 3; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder4: block constant i: integer := 4; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder5: block constant i: integer := 5; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder6: block constant i: integer := 6; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder7: block constant i: integer := 7; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder8: block constant i: integer := 8; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder9: block constant i: integer := 9; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; decoder10: block constant i: integer := 10; begin out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))) when clk'event and clk = '1'; end block; end architecture; </code></pre> <p>And worse still, each of those block statement concurrent conditional signal assignment statements become a process statement of the form:</p> <pre><code>decoder10: block constant i: integer := 10; begin process begin if clk'event and clk = '1' then out_address(i) &lt;= to_std_ulogic(i = to_integer(unsigned(in_address))); end if; wait on clk, in_address; end process; </code></pre> <p>So now all the sudden instead of simulating one process you have eleven and each of those processes is sensitive to both clk and in_address, meaning the process with become active more than on just both clock edges. </p> <p>So not only do the loop statement and the generate statement equivalent produce the same hardware after elaboration and synthesis, the loop statement is guaranteed to be faster in simulation, which is it's intended purpose.</p> <p>Everything in a VHDL design specification devolves into block statements, process statements and subprograms (functions, procedures). Concurrent procedures are also devolved, while functions are expressions.</p> <p>It's guaranteed that synthesis elaborates a design first. The synthesis difference in this case between the generate statement and a single process containing a loop is grouping. A process statement is translated separately unless a synthesis tool accepts an attribute allowing flattening (e.g. DISSOLVE_HIERARCHY as an attribute on the generate statement). </p> <p>In the loop statement in a single process case you have the opportunity to share address recognizer logic between the 10 signal assignments by default, potentially generating less logic.</p> <p>So there can be little difference in synthesis, but a significant difference in simulation, where the practical impact depends on the size of your design.</p>