what is meant by lagging and leading current in ac circuit
Leading and lagging current Leading and lagging current are phenomena that occur as a result of alternating current. In a circuit with alternating current, the value of voltage and current vary sinusoidally. In these types of circuits, the terms lead, lag, or in phase are used to describe current with reference to voltage. Current is in phase with voltage when there is no phase shift between the sinusoids describing their time varying behavior. This generally occurs when the load drawing the current is resistive.
Power factor There is also a difference between a lagging and leading power factor. The terms refer to whether the phase of the current is leading or lagging the phase of the voltage. A lagging power factor signifies that the load is inductive, as the load will “consume” reactive power, and therefore the reactive component   Q  {\displaystyle Q}  is positive as reactive power travels through the circuit and is “consumed” by the inductive load. A leading power factor signifies that the load is capacitive, as the load “supplies” reactive power, and therefore the reactive component   Q  {\displaystyle Q}  is negative as reactive power is being supplied to the circuit.
Electric current The consequence of this convention is that electrons, the charge carriers in metal wires and most other parts of electric circuits, flow in the opposite direction of conventional current flow in an electrical circuit.
CMOS CMOS circuits are constructed in such a way that all P-type metal-oxide-semiconductor (PMOS) transistors must have either an input from the voltage source or from another PMOS transistor. Similarly, all NMOS transistors must have either an input from ground or from another NMOS transistor. The composition of a PMOS transistor creates low resistance between its source and drain contacts when a low gate voltage is applied and high resistance when a high gate voltage is applied. On the other hand, the composition of an NMOS transistor creates high resistance between source and drain when a low gate voltage is applied and low resistance when a high gate voltage is applied. CMOS accomplishes current reduction by complementing every nMOSFET with a pMOSFET and connecting both gates and both drains together. A high voltage on the gates will cause the nMOSFET to conduct and the pMOSFET not to conduct, while a low voltage on the gates causes the reverse. This arrangement greatly reduces power consumption and heat generation. However, during the switching time, both MOSFETs conduct briefly as the gate voltage goes from one state to another. This induces a brief spike in power consumption and becomes a serious issue at high frequencies.