3D integration of III-V semiconductors with Si CMOS is
highly attractive
since it allows combining new functions such as photonic and analog
devices with digital signal processing circuitry. Thus far, most 3D
integration approaches have used epitaxial growth on Si, layer transfer
by wafer bonding, or die-to-die packaging. Here we present low-temperature
integration of InAs on W using Si3N4template
assisted selective area metal–organic vapor-phase epitaxy (MOVPE).
Despite growth nucleation on polycrystalline W, we can obtain a high
yield of single-crystalline InAs nanowires, as observed by transmission
electron microscopy (TEM) and electron backscatter diffraction (EBSD).
The nanowires exhibit a mobility of 690 cm2/(V s), a low-resistive,
Ohmic electrical contact to the W film, and a resistivity which increases
with diameter attributed to increased grain boundary scattering. These
results demonstrate the feasibility for single-crystalline III-V back-end-of-line
integration with a low thermal budget compatible with Si CMOS.