<SYSTEM_TASK:>
Solve the following problem using Python, implementing the functions described below, one line at a time
<END_TASK>
<USER_TASK:>
Description:
 def write_PIA0_B_control(self, cpu_cycles, op_address, address, value):
 """ write to 0xff03 -> PIA 0 B side Control reg. TODO: Handle IRQ bit 7 | IRQ 1 (VSYNC) flag bit 6 | IRQ 2 flag(not used) bit 5 | Control line 2 (CB2) is an output = 1 bit 4 | Control line 2 (CB2) set by bit 3 = 1 bit 3 | select line MSB of analog multiplexor (MUX):
 0 = control line 2 LO / 1 = control line 2 HI bit 2 | set data direction: 0 = $FF02 is DDR / 1 = $FF02 is normal data lines bit 1 | control line 1 (CB1):
 IRQ polarity 0 = IRQ on HI to LO / 1 = IRQ on LO to HI bit 0 | VSYNC IRQ: 0 = disable IRQ / 1 = enable IRQ """

        log.critical(
            "%04x| write $%02x (%s) to $%04x -> PIA 0 B side Control reg.\t|%s",
            op_address, value, byte2bit_string(value),
            address, self.cfg.mem_info.get_shortest(op_address)
        )

        if is_bit_set(value, bit=0):
            log.critical(
                "%04x| write $%02x (%s) to $%04x -> VSYNC IRQ: enable\t|%s",
                op_address, value, byte2bit_string(value),
                address, self.cfg.mem_info.get_shortest(op_address)
            )
            self.cpu.irq_enabled = True
            value = set_bit(value, bit=7)
        else:
            log.critical(
                "%04x| write $%02x (%s) to $%04x -> VSYNC IRQ: disable\t|%s",
                op_address, value, byte2bit_string(value),
                address, self.cfg.mem_info.get_shortest(op_address)
            )
            self.cpu.irq_enabled = False

        if not is_bit_set(value, bit=2):
            self.pia_0_B_control.select_pdr()
        else:
            self.pia_0_B_control.deselect_pdr()

        self.pia_0_B_control.set(value)