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Solve the following problem using Python, implementing the functions described below, one line at a time
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Description:
 def instruction_SEX(self, opcode):
 """ This instruction transforms a twos complement 8-bit value in accumulator B into a twos complement 16-bit value in the D accumulator. source code forms: SEX CC bits "HNZVC": -aa0- // 0x1d SEX inherent case 0x1d: WREG_A = (RREG_B & 0x80) ? 0xff : 0; CLR_NZ; SET_NZ16(REG_D); peek_byte(cpu, REG_PC); #define SIGNED(b) ((Word)(b&0x80?b|0xff00:b)) case 0x1D: /* SEX */ tw=SIGNED(ibreg); SETNZ16(tw) SETDREG(tw) break; """

        b = self.accu_b.value
        if b & 0x80 == 0:
            self.accu_a.set(0x00)

        d = self.accu_d.value

#        log.debug("SEX: b=$%x ; $%x&0x80=$%x ; d=$%x", b, b, (b & 0x80), d)

        self.clear_NZ()
        self.update_NZ_16(d)