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Solve the following problem using Python, implementing the functions described below, one line at a time
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Description:
 def rtl_all(*vectorlist):
 """ Hardware equivalent of python native "all". :param WireVector vectorlist: all arguments are WireVectors of length 1 :return: WireVector of length 1 Returns a 1-bit WireVector which will hold a '1' only if all of the inputs are '1' (i.e. it is a big ol' AND gate) """

    if len(vectorlist) <= 0:
        raise PyrtlError('rtl_all requires at least 1 argument')
    converted_vectorlist = [as_wires(v) for v in vectorlist]
    if any(len(v) != 1 for v in converted_vectorlist):
        raise PyrtlError('only length 1 WireVectors can be inputs to rtl_all')
    return and_all_bits(concat_list(converted_vectorlist))