The board HES-US-440 offers a unique combination of Xilinx Virtex UltraScale XCVU440 logic module and Xilinx Zynq-7000 host module featuring ARM dual core Cortex-A9 CPU that allows building a self contained, one-board testbench for the design. It has been optimized for high speed physical prototyping and emulation of medium size ASIC up to 26 Million gates or the largest FPGA designs. The board contains two independent SO-DIMM slots connected to UltraScale that deliver up to 64 GB of DDR4 and two RLDRAM3 modules with SRAM-like interface, low latency and aggregated capacity of 1152 Mb. Such a memory-reach board design makes it applicable for numerous High Performance Computing (HPC) applications apart from physical prototyping. It can be also reused for HES emulation applications like simulation acceleration or co-emulation with virtual models.

Very precisely designed clocking block provides 7 regulated any-frequency clock sources and 2 of them are length aligned global clock lines routed to both FPGA devices. The global clock network can be also driven from external sources via dedicated SMA connectors. Complementary to global clocks there are 3 separate clock oscillators dedicated to high speed serial I/O links (GTH, QSFP+, SATA) and 4 oscillators dedicated for using with DDR memories. All on-board clock lines use LVDS signalling to assure high level of signals integrity and immunity to distractions.
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