In radar communication , the ambiguity function plays an important role in estimating the delay and Doppler shift introduced in received signal . With the limitation of ambiguity function based on Fourier transform , the FRFT based ambiguity function has been introduced . But it imposes a large computational complexity in the problems where only delay and Doppler shift is needed to estimate . In this paper , we study the adversarial attack and defence problem in deep learning from the perspective of Fourier analysis . We first explicitly compute the Fourier transform of deep ReLU neural networks and show that there exist decaying but non-zero high frequency components in the Fourier spectrum of neural networks . We demonstrate that the vulnerability of neural networks towards adversarial samples can be attributed to these insignificant but non-zero high frequency components . A complete representation of nonstationary signals requires frequency analysis that is local in time , resulting in the time – frequency analysis of signals . The Fourier transform analysis has long been recognized as the great tool for the study of stationary signals and processes where the properties are statistically invariant over time . However , it can not be used for the frequency analysis that is local in time . In this method , the two original images are self-encoded in the manner that one of the two images is directly separated into two phase masks ( PMs ) and used as keys for encryption , and then multiplied by a PM which is generated by using phase retrieval algorithm . At last , the whole encryption process is completed by a Fourier transform operation . In the decryption process , the image without a separation and the two PMs used as keys for encryption are all treated as encoded data . Firstly , the on-axis Fourier Transform digital hologram is divided into sub-holograms . Then the reconstruction result of every sub-hologram is obtained according to the position of corresponding sub-hologram in the hologram reconstruction plane with Fourier transform operation . Finally , the reconstruction image of on-axis Fourier Transform digital hologram can be acquired by the superposition of the reconstruction result of sub-holograms . It is shown that the CS can be successfully applied to both , musical and speech signals , but the speech signals are more demanding in terms of the number of observations . Also , our results show that discrete cosine transform domain allows better reconstruction using lower number of observations , compared to the Fourier transform domain , for both types of signals . In this paper , we present an iterative method to reduce the sensitivity of a general restoration scheme ( but specified to the Wiener filter ) with regards to wrong estimates of the said parameters . Within the Fourier transform domain , a sensitivity analysis is tackled in depth with the purpose of defining a number of iterations for each frequency element , which leads to the aimed desensitisation regardless of the errors on estimates . Experimental computations using meaningful values of parameters are addressed . Analog filters and direct digital filters are implemented using digital signal processing techniques . Specifically , Butterworth , Elliptic , and Chebyshev filters are implemented using the Motorola 56001 Digital Signal Processor by the integration of three software packages : MATLAB , C++ , and Motorola 's Application Development System . Analysis the working process of the asphalt concrete mixer control system , this article introduces a new type of intelligent control system based on the fuzzy expert control technology . To minimize the control error caused by nonlinearity and long time delay in the working process , the advance technology of fuzzy control , expert system and digital signal processing are adopted in the control system . A linear filter required by the prediction was designed to perform the prediction of the temperature change history in the working process of the mixer . Summary form only given . Mobile phones and modern hearing aids comprise advanced digital signal processing techniques as well as coding algorithms . From a functional point of view , digital hearing devices and mobile phones are approaching each other . Power and cost effciency , exibility , performance , and reliability of signal processing in digital domain have promoted designers to gradually replace the traditional analog domain signal processing1 with the signal processing in digital domain . The digital domain signal processing has been proven to be a very powerful tool in many different applications such as in telecommunications , controlling systems , measurement equipments , etc . , and hence plays a very important role in modern industrial products . In this paper , we design and implement an underwater modem by utilizing a general-purpose digital signal processor star kit ( DSK ) which embeds Texas Instrument TMS320C6416 digital signal processor ( DSP ) . Digital-domain signal processing for data transmission and reception is conducted in the DSP . We evaluate the performance of the implemented modem in un-derwater environment . The invention provides a hydrological comprehensive measurement device , comprising a operation control part , a measurement detecting part and an auxiliary assembly , wherein the operation control part is arranged in a ship body over the surface of water , and used for displaying data , accepting input operation and controlling the work state of the measurement detecting part ; the measurement detecting part is a device used for measuring a underwater geological structure , and is fixed under the surface of the water outside the ship body by a ship body fixing support ; the auxiliary assembly comprises a laser range finder and a printing device ; and the operation control part is connected with the laser range finder and the printing device by water data cables , and is connected with the measurement detecting part by an underwater data cable . The hydrological comprehensive measurement device mainly utilizes a phased array sonar for measuring depth and an acoustic Doppler for measuring speed , and adopts an embedded software and hardware technology , a high-speed DSP ( digital signal processing ) signal processing technology and the like to rapidly measure water depth , flow speed , river width , gradient and position information . The Z-Transform Infinite Impulse Response Digital Filter Design The Discrete Fourier Transform and Fast Fourier Transform Algorithms Multirate Digital Signal Processing Response of Linear Systems to Discrete-Time Random Processes , Power Spectrum Estimation , and Detection of Signals in Noise Finite Register Length Effects in Digital Signal Processing Signal Processing System Design Adaptive Filtering . We address a new approach to solve the ill-posed nonlinear inverse problem of high-resolution numerical reconstruction of the spatial spectrum pattern ( SSP ) of the backscattered wavefield sources distributed over the remotely sensed scene . An array or synthesized array radar ( SAR ) that employs digital data signal processing is considered . By exploiting the idea of combining the statistical minimum risk estimation paradigm with numerical descriptive regularization techniques , we address a new fused statistical descriptive regularization ( SDR ) strategy for enhanced radar imaging . In the experimental teaching to the Matlab software as a platform to design filter in accordance with the principles of programming of the window function design method using the Matlab Signal Processing Toolbox provides fir1 function filter , as well as call filter design and analysis toolbox provides graphics user interface design filter . Teaching effectiveness of Matlab into the teaching process , not only allows students to intuitively understand and in-depth understanding of the theoretical knowledge of digital signal processing and analysis methods , can also improve students ' practical ability and the ability to analyze and solve problems , improve the quality of teaching . A training sequence is used to estimate channels . Frequency offset estimation , dispersion compensation , phase estimation and the like of receiving signals are not necessary , so that requirement of digital signal processing of modules is lowered and complexity of the processing is lowered . By the testing method of the spectrum features of the optical passive device , the spectrum features of the optical passive device such as amplitude response and phase frequency features are obtained through channel estimation of the optical passive device . Weather radar is a type of radar that used to detect rainfall , the direction of movement and speed , to know the level of rain and cloud composition . One of the problems that occurs in weather radar is the amount of raw data to be acquired in the digital signal processing process is too large , the size until Gigabyte . In order that , we using Compressive Sampling(CS ) to reduce the radar 's beat signal , as part of weather radar data . Macromodeling-Simulation process for signal in- tegrity verifications has become necessary for the high speed circuit system design . This paper aims to introduce a " VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques " framework ( known as SIM- DSP framework ) , which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase . Core identification modules and peripheral (pre-/post-)processing modules have been devel- oped and assembled to form a verification flow . This paper builds on a previous study that compared two different ECG acquisition systems , one of which uses PS25015A dry electrodes and the other , which uses two different silver/silver chloride ( Ag/AgCl ) wet electrodes . The adaptive filtering technique was implemented in order to test its effectiveness when applied to a wearable ECG medical device , intended to monitor the user ’s ECG throughout daily activities , such as walking . According to statistical analysis , the dry electrodes may have a better SNR . Therefore , there is a need to employ a nonlinear echo canceller . In this paper , a kernel expansion on a family of adaptive filtering algorithms based on least mean square filter is proposed . Kernel methods help model the nonlinear echo path and attain global minimum easily by finding the optimal set of filter weights . The implementation is based on the fast lossless ( FL ) compression algorithm reported in Fast Lossless Compression of Multispectral-Image Data ( NPO-42517 ) , NASA Tech Briefs , Vol . 30 , No. 8 ( August 2006 ) , page 26 , which achieves excellent compression performance and has low complexity . This algorithm performs predictive compression using an adaptive filtering method , and uses adaptive Golomb coding . The implementation also packetizes the coded data . It is imperative to remove baseline wander from Electrocardiogram ( ECG ) before utilizing it for diagnostic purpose . In this paper , an adaptive filtering based technique is investigated for removal of baseline wander from the ECG signals obtained from a Holter ECG monitor . It uses a reference signal , obtained by adding absolute power spectrum of 3-channel accelerometer output connected to an ECG electrode . This paper presents the design of an adapting filtering method to remove the noise in the biomedical signal records . The major concern about analyze the presence of various artifacts in ECG records and modular artifacts in EEG records caused due to various noise factors . Based on the discussing the adapting filtering algorithms of LMS algorithm , LMF algorithm and the combined LMS/F algorithm , this paper introduced a positive numberγas the modifying factor to modify the combined LMS/F algorithm . The modified combined LMS/F algorithm improved the convergence speed and the tracking characteristic of the time-variable system , while it kept the characteristic of a small steady state error and its stability . The speed of the MAC unit determines the overall performance of the system . MAC unit basically consists of Multiplier , adder and an accumulator unit . In most of the cases floating point adder/subtractor and a multiplier are presented in IEEE-754 format for single precision format . The utility model discloses an extra bass circuit and a television with the extra bass circuit . The circuit comprises a low pass filter , an adder and a signal amplification circuit , wherein the low pass filter includes two paths for respectively receiving the L channel voice frequency signals and the R channel voice frequency signals ; after the filtering processing , the signals are output by the low pass filter to the adder for mixing , and then output by the adder to the signal amplification circuit for the amplification processing ; and after the amplification , a bass loudspeaker is driven to output the audio frequencies of the bass parts . The utility model has the advantages of simple structure and low cost ; and compared with the prior art , the extra bass circuit has a wider audio range , that is , in addition to match with the design requirements of panel TV sets for narrow frames , the circuit greatly increases the low frequency parts of program sounds , and has lower basses and higher pitches . The basic of all of these operations is multi operand addition . To improve this operation 's performance , many methods are used , that carry save adder ( CSA ) is the best method until now . This paper proposed a new method with the same performance as CSA but with 40 % less logic gates than CSA . Carry-save adder ( CSA ) is one of the most widely used implementation units for arithmetic circuits . However , the existing approaches to the CSA transformation have an inherent limitation in the scope of CSA application , i.e. , transforming each of operation trees separately without any interaction among them , which results in a locally optimized CSA circuit . In this brief , based on the extracted features of the arithmetic operations of the ALU , we propose a new special low-complexity QCA 4:1 multiplexer , which is application-specific to the proposed ALU . Moreover , a new QCA full adder is proposed based on the cell interaction . Likewise , a QCA multilayer ALU structure is designed based on the validated proposed structures to carry out four logical and eight arithmetic operations . The metric of error distance is used to evaluate the reliability of the approximate designs . Simulation by Cadence 's Spectre in TSMC 65 nm process has shown that the proposed designs consume less power and have better performance ( such as a lower propagation delay ) compared to the accurate XOR/XNOR-based adder , while the error distance remains similar or better than other approximate adder designs . Approximate adders have been considered as a potential alternative for error-tolerant applications to trade off some accuracy for gains in other circuit-based metrics , such as power , area and delay . Existing approximate adder designs have shown substantial advantages in improving many of these operational features . However , the error characteristics of the approximate adders still remain an issue that is not very well understood . The design requires only n ancillary qubits but will need more quantum hardware than the non-restoring division circuit . Both proposed quantum circuits are based on ( i ) a new quantum conditional addition circuit , ( ii ) a new quantum adder-subtractor and ( iii ) a new quantum subtraction circuit . Further , both designs are compared and shown to be superior to existing work in terms of T-count and T-depth . The floating-point operators use the word format and exceptions as described by the IEEE std-754 . A dual-path adder implementation is described in detail , as are floating-point multiplier , divider and square root components . Results and comparisons with other works are given . In the proposed MRB computational rule , the intermediate sum and intermediate carry are obtained in terms of conventional ( Posibits ) and inverted encoding of Negabits ( IEN ) representation replacing the redundant digits . The proposed MRB adder is synthesized and simulated using Xilinx-ISE 14.4 software and implemented on vertex-4 FPGA device . The propagation delay and device utilization are obtained from synthesis report and are compared with conventional redundant binary adder . It has three major stages : partial product generation stage , partial product reduction stage , and the final adder stage . The proposed structure introduces a new MUX-based compressor in the partial product reduction stage to reduce power and increase speed , and in the final adder stage , the Sparse-tree-based inverted end-around-carry adder reduces the number of critical path circuit blocks , also avoids wire interconnection problem . The proposed multiplier is implemented using both 32 nm CNTFET ( Carbon-Nanotube FET ) and bulk CMOS technology for performance comparison . Experiments on the actual fault coverage for the ISCAS 85 benchmark circuits show that extremely high postcompaction fault coverage ( close to 100 % ) is obtained with ABC . They also indicate that the use of a rotate-carry adder does not always improve the fault coverage ; in some cases , the fault coverage is actually reduced . Herein , we present a series of entirely DNA-based logic gates ( AND , OR , and XOR ) that operate with mutually compatible oligonucleotide inputs and outputs . A DNA-based half-adder was assembled through the combination of an AND gate and an XOR ( eXclusive OR ) gate in a shared solution , thus demonstrating both the sequence addressability and cross-compatibility of the gates . The use of a single molecular-recognition platform gives these gates the potential to be assembled into higher-order circuits that are ‘ ‘ virtually wired ’ ’ through the information contained within oligonucleotide sequences . Digital Signal Processing ( DSP ) systems operating on analog inputs are often limited by sampling rates of Analog to Digital Converters ( ADC ) . ADCs are critical components since they tend to determine the overall system performance . The state of the art of compiling digital signal processing ( DSP ) algorithms into silicon is discussed . It is indicated how digital signal processing differs from numerical data processing , including the consequences for the synthesis tools . The new controller automatically selects the most appropriate PI parameters to achieve a fast response rate on basis of the tracking errors . In the experimental setup , the new controller is realized with a digital signal process ( DSP ) system , implemented in a conventional AFM system . Experiments are carried out by comparing the new method with the standard PI controller . So , CPNR mapping is taken into account . With the recent advances in Genomic signal process ( GSP ) domain , researchers are applying digital signal process ( DSP ) techniques in raw genomic information for extracting the hidden features among proteins . Wavelet transformation has been a really novel strategy for the analysis and process of non-stationary signals like bio signals within which each time and frequency data area unit required . A fuzzy basis neuro-network is utilized for online tuning of the PI controller to ensure optimum drive performance . The DC generator simulates the propeller characteristic as the load of the propulsion motor , the proposed observer and controller had been investigated , and they have been carried out in the digital signal process ( DSP ) . The DS-SS ( Direct Sequence Spread Spec1nun ) transmitter is part of a low data rate ( ∼150 kbps - burst rate and 64 bps - average data rate ) wireless communication system . It is traditionally implemented using Digital Signal processing chip ( DSP ) . However , with rapid increase in variety of services through cell phones , such as , web access , video transfer , online games etc . A method utilizing MPEG-1 computer picture processing technique and hard ware of DSP+FPGA to fabricate digital audio and vedio collecting compression card includes the following steps : carrying on A/D conversion and synchronous processing for audio and video analog signal through digitization processing chip and to convert it to be digital signal which is stored into storage RAM through digital signal control chip ( FPGA ) , afterwards carrying on preprocessing by digital signal processing chip DSP as required according to the specific needs andto pick up relative data , and then forwarding the required result through PCI bus to computer for processing to finish the interface function . The utility model discloses an electric vehicle charging power demand predicting system , which comprises a signal modulation module , an analog/digital ( A/D ) conversion module , a digital signal process ( DSP ) processing module , a dual-port random access memory ( RAM ) transmission module , a complex programmable logic device/field-programmable gate way ( CPLD/FPGA ) conversion interface , an ARM9 statistic and output unit and a power demand predicting unit ; and the input of the signal modulation module is respectively connected with the output of a voltage collection module and a current collection module . Due to the adoption of the electric vehicle charging power demand predicting system , the charging power demand of an entire power matching network area can be calculated , and the prediction on the charging power demand can be realized . SOLUTION : A camera 10 stores the picture element expression of the picture in a memory 12 . A digital signal processing device(DSP ) 14 processes the picture in the memory 12 with the memory 16 as a program storage memory and a scratch pad memory and decides the positions of the features of the face . The emphasis picture is generated by form-processing the picture which is band- filtered . Compact , reliable , flexible and cost effective signalling subsystems are needed in the present day digital switching systems ( DSS ) . This paper describes a single board versatile signalling subsystem based on digital signal processing (DSP)/digital techniques . Specifically , the design implements all the functions required in a DSS to implement dual tone multifrequency ( DTMF , also known as multifrequency push button ) signalling and signalling system R2 ( SS R2 ) . In this paper , a new two-step timing acquisition method combining energy detection ( ED ) scheme with the monobit digital receiver is proposed . The usage of the monobit digital receiver , with the comparator instead of high resolution ADC , can reduce the complexity greatly ; using the ED scheme to cut down the received data region , the computational load of digital signal processing ( DSP ) part can be decreased significantly . The acquisition probability of each step is analyzed in this paper . Issues of segmentation and positioning have always been at the heart of marketing management . In recent years , much methodological progress has been made in order to carry out these two tasks simultaneously , that is , to combine certain types of clustering algorithms with appropriate multidimensional scaling or unfolding procedures . When trying to provide managers with a tool to support marketing decision-making in segmentation and positioning , the ease of use and the visual quality of results must be emphasized . Arrangement theory plays an essential role in the study of the unfolding model used in many fields . This paper describes how arrangement theory can be usefully employed in solving the problems of counting ( i ) the number of admissible rankings in an unfolding model and ( ii ) the number of ranking patterns generated by unfolding models . The paper is mostly expository but also contains some new results such as simple upper and lower bounds for the number of ranking patterns in the unidimensional case . In the process , we state and prove a tight upper bound on the minimum number of processors required to execute the static schedule produced by our algorithms . We also construct an unfolding algorithm for split-node graphs and combine it with our scheduling methods to achieve rate-optimality in all cases . Finally , we demonstrate our methods on a specific example . In the framework of functional testing from algebraic specifications , the strategy of test selection which has been widely and efficiently applied is based on axiom unfolding . In this paper , we propose to extend this selection strategy to a modal formalism used to specify dynamic and reactive systems . The aim of integration testing is to test the composition of modules assuming that they have previously been verified , i.e. assuming their correctness . One of the main method for the selection of test cases from first-order specifications , called axiom unfolding , is based on a proof search for the different instances of the property to be tested , thus allowing the coverage of this property . The idea here is to use deduction modulo as a proof system for structured first-order specifications in the context of integration testing , so as to take advantage of the knowledge of the correctness of the individual modules . In this paper , we study the problem of exploiting parallelism when a hard real-time streaming application modeled as a Synchronous Data Flow ( SDF ) graph is mapped onto a Multi-Processor System-on-Chip ( MPSoC ) platform . We propose a new unfolding graph transformation and an algorithm that adapts the parallelism in the application according to the resources in an MPSoC by using the unfolding transformation . We evaluate the efficiency of our unfolding graph transformation and the performance and time complexity of our algorithm in comparison to the existing approaches . Transformation rules for ( Flat ) GHC programs are presented , which re ne the previous rules proposed by one of the authors ( Furukawa et al. 1987 ) . The rules are based on unfolding/folding and are novel in that they are stated in terms of idempotent substitutions with preferred directions of bindings . They are more general than the old rules in that no mode system is assumed and that the rule of folding is included . The accuracy of probabilistic risk assessment of rotor disks is strongly dependent on the accurate description of the size and shape distributions of anomalies in alloys . These size-shape distributions of anomalies are often derived from planar sectioning data measurements using stereological unfolding algorithms . Since it is impossible to accurately predict the shape and orientation parameters of a general ellipsoid based on measurements obtained from two-dimensional sectioning data , the anomaly model should be limited to a spheroid . We present two classes of transformation both followed by regression . In the first application stereological unfolding is desired to reconstruct spatial data from planar sections . In the second case a grey-tone image from scanning electron microscopy is evaluated . The template structure is unfolded by selectively ( targeted ) pulling on different portions of the protein using the geometric based technique FRODA , and then refolded using hierarchically restrained replica exchange molecular dynamics simulations ( hr-REMD ) . FRODA unfolding is used to create a diverse set of topologies for surveying near native-like structures from a template and to provide a set of persistent contacts to be employed during re-folding . We have tested our approach on 13 previous CASP targets and observed that this method of folding an ensemble of partially unfolded structures , through the hierarchical addition of contact restraints ( that is , first local and then nonlocal interactions ) , leads to a refolding of the structure along with refinement in most cases ( 12/13 ) . The paper presents a catalogbased algorithm called the Yo-Yo Algorithm for consistent instance migration in Petri net workflow models . It uses a technique of folding and unfolding of nets . The algorithm is formulated in terms of Colored Derivation Trees , a novel representation of the runtime states of workflow nets . To overcome this , we propose two new non-linear dimensionality reduction algorithms for evolutionary multi-objective optimization , namely C-PCA-NSGA-II and MVU-PCA-NSGA-II . While the former is based on the newly introduced correntropy PCA [ 2 ] , the later implements maximum variance unfolding principle [ 3,4,5 ] , in a novel way . We also establish the superiority of these new EMO procedures over the earlier PCA-based procedure , both in terms of accuracy and computational time , by solving upto 50-objective optimization problems . This paper discusses the learning and educational potentialities of the Venice Unfolding prototype , an experimental tabletop application designed to explore and investigate urban and territorial contents and knowledge . The prototype supports and transforms ways of approaching various strategies involved in urban and territorial planning processes . This distinction is easy to recognize empirically because the inter-item correlation matrix for the two types of data typically shows different patterns . Furthermore , for both types of unfolding models , correspondence analysis ( CA ) , which is a rival method for dimensionality reduction , outperforms PCA in terms of representation of both person and item locations , especially for the exponential unfolding model . Finally , it is shown that undoubled CA outperforms doubled CA for both types of unfolding models . The first mechanism involves the stacking of the decoder on top of the representation of the encoder in a manner that preserves the temporal resolution of the sequences ; this is in contrast with architectures that encode the source into a fixed - size representation . The second mechanism is the dynamic unfolding mechanism that allows the network to process in a simple and efficient way source and target sequences of different lengths ( Sect . [ reference ] ) . The proposed ByteNet architecture is composed of a decoder that is stacked on an encoder ( Sect . [ reference ] ) and generates variable - length outputs via dynamic unfolding ( Sect . [ reference ] ) . This is in contrast to models that compress the source representation into a fixed - size vector or that pool over the source representation with a mechanism such as attentional pooling . subsection : Dynamic Unfolding An encoder and a decoder network that process sequences of different lengths can not be directly connected due to the different sizes of the computed representations . In this manner the representation produced by the encoder can be efficiently computed , while maintaining high bandwidth and being resolution - preserving . Once the encoder representation is computed , we let the decoder unfold step - by - step over the encoder representation until the decoder itself outputs an end - of - sequence symbol ; the unfolding process may freely proceed beyond the estimated length of the encoder representation . Figure [ reference ] gives an example of dynamic unfolding . section : Conclusion In this work , we have provided a unique formulation that expresses many state - of - the - art SR models as a finite unfolding of a single - state RNN with various recurrent functions . Based on this , we extend existing methods by considering a dual - state design ; the two hidden states of our proposed DSRN operate at different spatial resolutions . uRAE + MLP : We use the Unfolding Recursive Autoencoder to get a 100 - dimensional vector representation of each sentence , and put an MLP on the top as in WordEmbed ; SENNA + MLP / sim : We use the SENNA - type sentence model for sentence representation ; SenMLP : As stated earlier , our model is not specially tailored for modeling synonymy , and generally requires instances to work favorably . Nevertheless , our generic matching models still manage to perform reasonably well , achieving an accuracy and F1 score close to the best performer in 2008 based on hand - crafted features , but still significantly lower than the state - of - the - art ( 76.8% / 83.6 % ) , achieved with unfolding - RAE and other features designed for this task . subsection : Discussions Pairwise interaction models were also considered to improve prediction performances . For example , the Universal Schema approach factorizes a 2D unfolding of the tensor ( a matrix of entity pairs vs. relations ) while extend this also to other pairs . In the Neural Tensor Network ( NTN ) model , combine linear transformations and multiple bilinear forms of subject and object embeddings to jointly feed them into a nonlinear neural layer . In tensor terminology , n - mode vectors of a D - order tensor Y ∈ RI1×I2×···×ID are In - dimensional vectors obtained from Y by varying the index in Indimension , while keeping all other indices fixed . An n - mode matrix unfolding of a tensor is a matrix which has all n - mode vectors as its columns [ 7 ] . Formally we use the operator T { In}×{Ij |j∈ [ D ] \n } to denote the n - mode matrix unfolding , which returns a matrix of size In × ∏ j∈ [ D ] \n Ij . Therefore , by clustering “ pixels ” of all images during learning , we expect to model local parts shared by multiple objects or scenes . To achieve this , we adopt the unfolding operator T { N , H , W}×{C} ( Y ) and use Rspatial ( Y , µ ) = 1 2NCHW NHW∑
In radar communication , the ambiguity function plays an important role in estimating the delay and Doppler shift introduced in received signal . With the limitation of ambiguity function based on Fourier transform , the FRFT based ambiguity function has been introduced . But it imposes a large computational complexity in the problems where only delay and Doppler shift is needed to estimate .
In this paper , we study the adversarial attack and defence problem in deep learning from the perspective of Fourier analysis . We first explicitly compute the Fourier transform of deep ReLU neural networks and show that there exist decaying but non-zero high frequency components in the Fourier spectrum of neural networks . We demonstrate that the vulnerability of neural networks towards adversarial samples can be attributed to these insignificant but non-zero high frequency components .
A complete representation of nonstationary signals requires frequency analysis that is local in time , resulting in the time – frequency analysis of signals . The Fourier transform analysis has long been recognized as the great tool for the study of stationary signals and processes where the properties are statistically invariant over time . However , it can not be used for the frequency analysis that is local in time .
In this method , the two original images are self-encoded in the manner that one of the two images is directly separated into two phase masks ( PMs ) and used as keys for encryption , and then multiplied by a PM which is generated by using phase retrieval algorithm . At last , the whole encryption process is completed by a Fourier transform operation . In the decryption process , the image without a separation and the two PMs used as keys for encryption are all treated as encoded data .
Firstly , the on-axis Fourier Transform digital hologram is divided into sub-holograms . Then the reconstruction result of every sub-hologram is obtained according to the position of corresponding sub-hologram in the hologram reconstruction plane with Fourier transform operation . Finally , the reconstruction image of on-axis Fourier Transform digital hologram can be acquired by the superposition of the reconstruction result of sub-holograms .
It is shown that the CS can be successfully applied to both , musical and speech signals , but the speech signals are more demanding in terms of the number of observations . Also , our results show that discrete cosine transform domain allows better reconstruction using lower number of observations , compared to the Fourier transform domain , for both types of signals .
In this paper , we present an iterative method to reduce the sensitivity of a general restoration scheme ( but specified to the Wiener filter ) with regards to wrong estimates of the said parameters . Within the Fourier transform domain , a sensitivity analysis is tackled in depth with the purpose of defining a number of iterations for each frequency element , which leads to the aimed desensitisation regardless of the errors on estimates . Experimental computations using meaningful values of parameters are addressed .
Analog filters and direct digital filters are implemented using digital signal processing techniques . Specifically , Butterworth , Elliptic , and Chebyshev filters are implemented using the Motorola 56001 Digital Signal Processor by the integration of three software packages : MATLAB , C++ , and Motorola 's Application Development System .
Analysis the working process of the asphalt concrete mixer control system , this article introduces a new type of intelligent control system based on the fuzzy expert control technology . To minimize the control error caused by nonlinearity and long time delay in the working process , the advance technology of fuzzy control , expert system and digital signal processing are adopted in the control system . A linear filter required by the prediction was designed to perform the prediction of the temperature change history in the working process of the mixer .
Summary form only given . Mobile phones and modern hearing aids comprise advanced digital signal processing techniques as well as coding algorithms . From a functional point of view , digital hearing devices and mobile phones are approaching each other .
Power and cost effciency , exibility , performance , and reliability of signal processing in digital domain have promoted designers to gradually replace the traditional analog domain signal processing1 with the signal processing in digital domain . The digital domain signal processing has been proven to be a very powerful tool in many different applications such as in telecommunications , controlling systems , measurement equipments , etc . , and hence plays a very important role in modern industrial products .
In this paper , we design and implement an underwater modem by utilizing a general-purpose digital signal processor star kit ( DSK ) which embeds Texas Instrument TMS320C6416 digital signal processor ( DSP ) . Digital-domain signal processing for data transmission and reception is conducted in the DSP . We evaluate the performance of the implemented modem in un-derwater environment .
The invention provides a hydrological comprehensive measurement device , comprising a operation control part , a measurement detecting part and an auxiliary assembly , wherein the operation control part is arranged in a ship body over the surface of water , and used for displaying data , accepting input operation and controlling the work state of the measurement detecting part ; the measurement detecting part is a device used for measuring a underwater geological structure , and is fixed under the surface of the water outside the ship body by a ship body fixing support ; the auxiliary assembly comprises a laser range finder and a printing device ; and the operation control part is connected with the laser range finder and the printing device by water data cables , and is connected with the measurement detecting part by an underwater data cable . The hydrological comprehensive measurement device mainly utilizes a phased array sonar for measuring depth and an acoustic Doppler for measuring speed , and adopts an embedded software and hardware technology , a high-speed DSP ( digital signal processing ) signal processing technology and the like to rapidly measure water depth , flow speed , river width , gradient and position information .
The Z-Transform Infinite Impulse Response Digital Filter Design The Discrete Fourier Transform and Fast Fourier Transform Algorithms Multirate Digital Signal Processing Response of Linear Systems to Discrete-Time Random Processes , Power Spectrum Estimation , and Detection of Signals in Noise Finite Register Length Effects in Digital Signal Processing Signal Processing System Design Adaptive Filtering .
We address a new approach to solve the ill-posed nonlinear inverse problem of high-resolution numerical reconstruction of the spatial spectrum pattern ( SSP ) of the backscattered wavefield sources distributed over the remotely sensed scene . An array or synthesized array radar ( SAR ) that employs digital data signal processing is considered . By exploiting the idea of combining the statistical minimum risk estimation paradigm with numerical descriptive regularization techniques , we address a new fused statistical descriptive regularization ( SDR ) strategy for enhanced radar imaging .
In the experimental teaching to the Matlab software as a platform to design filter in accordance with the principles of programming of the window function design method using the Matlab Signal Processing Toolbox provides fir1 function filter , as well as call filter design and analysis toolbox provides graphics user interface design filter . Teaching effectiveness of Matlab into the teaching process , not only allows students to intuitively understand and in-depth understanding of the theoretical knowledge of digital signal processing and analysis methods , can also improve students ' practical ability and the ability to analyze and solve problems , improve the quality of teaching .
A training sequence is used to estimate channels . Frequency offset estimation , dispersion compensation , phase estimation and the like of receiving signals are not necessary , so that requirement of digital signal processing of modules is lowered and complexity of the processing is lowered . By the testing method of the spectrum features of the optical passive device , the spectrum features of the optical passive device such as amplitude response and phase frequency features are obtained through channel estimation of the optical passive device .
Weather radar is a type of radar that used to detect rainfall , the direction of movement and speed , to know the level of rain and cloud composition . One of the problems that occurs in weather radar is the amount of raw data to be acquired in the digital signal processing process is too large , the size until Gigabyte . In order that , we using Compressive Sampling(CS ) to reduce the radar 's beat signal , as part of weather radar data .
Macromodeling-Simulation process for signal in- tegrity verifications has become necessary for the high speed circuit system design . This paper aims to introduce a " VLSI Signal Integrity Macromodeling and Simulation via Digital Signal Processing Techniques " framework ( known as SIM- DSP framework ) , which applies digital signal processing techniques to facilitate the SI verification process in the pre-layout design phase . Core identification modules and peripheral (pre-/post-)processing modules have been devel- oped and assembled to form a verification flow .
This paper builds on a previous study that compared two different ECG acquisition systems , one of which uses PS25015A dry electrodes and the other , which uses two different silver/silver chloride ( Ag/AgCl ) wet electrodes . The adaptive filtering technique was implemented in order to test its effectiveness when applied to a wearable ECG medical device , intended to monitor the user ’s ECG throughout daily activities , such as walking . According to statistical analysis , the dry electrodes may have a better SNR .
Therefore , there is a need to employ a nonlinear echo canceller . In this paper , a kernel expansion on a family of adaptive filtering algorithms based on least mean square filter is proposed . Kernel methods help model the nonlinear echo path and attain global minimum easily by finding the optimal set of filter weights .
The implementation is based on the fast lossless ( FL ) compression algorithm reported in Fast Lossless Compression of Multispectral-Image Data ( NPO-42517 ) , NASA Tech Briefs , Vol . 30 , No. 8 ( August 2006 ) , page 26 , which achieves excellent compression performance and has low complexity . This algorithm performs predictive compression using an adaptive filtering method , and uses adaptive Golomb coding . The implementation also packetizes the coded data .
It is imperative to remove baseline wander from Electrocardiogram ( ECG ) before utilizing it for diagnostic purpose . In this paper , an adaptive filtering based technique is investigated for removal of baseline wander from the ECG signals obtained from a Holter ECG monitor . It uses a reference signal , obtained by adding absolute power spectrum of 3-channel accelerometer output connected to an ECG electrode .
This paper presents the design of an adapting filtering method to remove the noise in the biomedical signal records . The major concern about analyze the presence of various artifacts in ECG records and modular artifacts in EEG records caused due to various noise factors .
Based on the discussing the adapting filtering algorithms of LMS algorithm , LMF algorithm and the combined LMS/F algorithm , this paper introduced a positive numberγas the modifying factor to modify the combined LMS/F algorithm . The modified combined LMS/F algorithm improved the convergence speed and the tracking characteristic of the time-variable system , while it kept the characteristic of a small steady state error and its stability .
The speed of the MAC unit determines the overall performance of the system . MAC unit basically consists of Multiplier , adder and an accumulator unit . In most of the cases floating point adder/subtractor and a multiplier are presented in IEEE-754 format for single precision format .
The utility model discloses an extra bass circuit and a television with the extra bass circuit . The circuit comprises a low pass filter , an adder and a signal amplification circuit , wherein the low pass filter includes two paths for respectively receiving the L channel voice frequency signals and the R channel voice frequency signals ; after the filtering processing , the signals are output by the low pass filter to the adder for mixing , and then output by the adder to the signal amplification circuit for the amplification processing ; and after the amplification , a bass loudspeaker is driven to output the audio frequencies of the bass parts . The utility model has the advantages of simple structure and low cost ; and compared with the prior art , the extra bass circuit has a wider audio range , that is , in addition to match with the design requirements of panel TV sets for narrow frames , the circuit greatly increases the low frequency parts of program sounds , and has lower basses and higher pitches .
The basic of all of these operations is multi operand addition . To improve this operation 's performance , many methods are used , that carry save adder ( CSA ) is the best method until now . This paper proposed a new method with the same performance as CSA but with 40 % less logic gates than CSA .
Carry-save adder ( CSA ) is one of the most widely used implementation units for arithmetic circuits . However , the existing approaches to the CSA transformation have an inherent limitation in the scope of CSA application , i.e. , transforming each of operation trees separately without any interaction among them , which results in a locally optimized CSA circuit .
In this brief , based on the extracted features of the arithmetic operations of the ALU , we propose a new special low-complexity QCA 4:1 multiplexer , which is application-specific to the proposed ALU . Moreover , a new QCA full adder is proposed based on the cell interaction . Likewise , a QCA multilayer ALU structure is designed based on the validated proposed structures to carry out four logical and eight arithmetic operations .
The metric of error distance is used to evaluate the reliability of the approximate designs . Simulation by Cadence 's Spectre in TSMC 65 nm process has shown that the proposed designs consume less power and have better performance ( such as a lower propagation delay ) compared to the accurate XOR/XNOR-based adder , while the error distance remains similar or better than other approximate adder designs .
Approximate adders have been considered as a potential alternative for error-tolerant applications to trade off some accuracy for gains in other circuit-based metrics , such as power , area and delay . Existing approximate adder designs have shown substantial advantages in improving many of these operational features . However , the error characteristics of the approximate adders still remain an issue that is not very well understood .
The design requires only n ancillary qubits but will need more quantum hardware than the non-restoring division circuit . Both proposed quantum circuits are based on ( i ) a new quantum conditional addition circuit , ( ii ) a new quantum adder-subtractor and ( iii ) a new quantum subtraction circuit . Further , both designs are compared and shown to be superior to existing work in terms of T-count and T-depth .
The floating-point operators use the word format and exceptions as described by the IEEE std-754 . A dual-path adder implementation is described in detail , as are floating-point multiplier , divider and square root components . Results and comparisons with other works are given .
In the proposed MRB computational rule , the intermediate sum and intermediate carry are obtained in terms of conventional ( Posibits ) and inverted encoding of Negabits ( IEN ) representation replacing the redundant digits . The proposed MRB adder is synthesized and simulated using Xilinx-ISE 14.4 software and implemented on vertex-4 FPGA device . The propagation delay and device utilization are obtained from synthesis report and are compared with conventional redundant binary adder .
It has three major stages : partial product generation stage , partial product reduction stage , and the final adder stage . The proposed structure introduces a new MUX-based compressor in the partial product reduction stage to reduce power and increase speed , and in the final adder stage , the Sparse-tree-based inverted end-around-carry adder reduces the number of critical path circuit blocks , also avoids wire interconnection problem . The proposed multiplier is implemented using both 32 nm CNTFET ( Carbon-Nanotube FET ) and bulk CMOS technology for performance comparison .
Experiments on the actual fault coverage for the ISCAS 85 benchmark circuits show that extremely high postcompaction fault coverage ( close to 100 % ) is obtained with ABC . They also indicate that the use of a rotate-carry adder does not always improve the fault coverage ; in some cases , the fault coverage is actually reduced .
Herein , we present a series of entirely DNA-based logic gates ( AND , OR , and XOR ) that operate with mutually compatible oligonucleotide inputs and outputs . A DNA-based half-adder was assembled through the combination of an AND gate and an XOR ( eXclusive OR ) gate in a shared solution , thus demonstrating both the sequence addressability and cross-compatibility of the gates . The use of a single molecular-recognition platform gives these gates the potential to be assembled into higher-order circuits that are ‘ ‘ virtually wired ’ ’ through the information contained within oligonucleotide sequences .
Digital Signal Processing ( DSP ) systems operating on analog inputs are often limited by sampling rates of Analog to Digital Converters ( ADC ) . ADCs are critical components since they tend to determine the overall system performance .
The state of the art of compiling digital signal processing ( DSP ) algorithms into silicon is discussed . It is indicated how digital signal processing differs from numerical data processing , including the consequences for the synthesis tools .
The new controller automatically selects the most appropriate PI parameters to achieve a fast response rate on basis of the tracking errors . In the experimental setup , the new controller is realized with a digital signal process ( DSP ) system , implemented in a conventional AFM system . Experiments are carried out by comparing the new method with the standard PI controller .
So , CPNR mapping is taken into account . With the recent advances in Genomic signal process ( GSP ) domain , researchers are applying digital signal process ( DSP ) techniques in raw genomic information for extracting the hidden features among proteins . Wavelet transformation has been a really novel strategy for the analysis and process of non-stationary signals like bio signals within which each time and frequency data area unit required .
A fuzzy basis neuro-network is utilized for online tuning of the PI controller to ensure optimum drive performance . The DC generator simulates the propeller characteristic as the load of the propulsion motor , the proposed observer and controller had been investigated , and they have been carried out in the digital signal process ( DSP ) .
The DS-SS ( Direct Sequence Spread Spec1nun ) transmitter is part of a low data rate ( ∼150 kbps - burst rate and 64 bps - average data rate ) wireless communication system . It is traditionally implemented using Digital Signal processing chip ( DSP ) . However , with rapid increase in variety of services through cell phones , such as , web access , video transfer , online games etc .
A method utilizing MPEG-1 computer picture processing technique and hard ware of DSP+FPGA to fabricate digital audio and vedio collecting compression card includes the following steps : carrying on A/D conversion and synchronous processing for audio and video analog signal through digitization processing chip and to convert it to be digital signal which is stored into storage RAM through digital signal control chip ( FPGA ) , afterwards carrying on preprocessing by digital signal processing chip DSP as required according to the specific needs andto pick up relative data , and then forwarding the required result through PCI bus to computer for processing to finish the interface function .
The utility model discloses an electric vehicle charging power demand predicting system , which comprises a signal modulation module , an analog/digital ( A/D ) conversion module , a digital signal process ( DSP ) processing module , a dual-port random access memory ( RAM ) transmission module , a complex programmable logic device/field-programmable gate way ( CPLD/FPGA ) conversion interface , an ARM9 statistic and output unit and a power demand predicting unit ; and the input of the signal modulation module is respectively connected with the output of a voltage collection module and a current collection module . Due to the adoption of the electric vehicle charging power demand predicting system , the charging power demand of an entire power matching network area can be calculated , and the prediction on the charging power demand can be realized .
SOLUTION : A camera 10 stores the picture element expression of the picture in a memory 12 . A digital signal processing device(DSP ) 14 processes the picture in the memory 12 with the memory 16 as a program storage memory and a scratch pad memory and decides the positions of the features of the face . The emphasis picture is generated by form-processing the picture which is band- filtered .
Compact , reliable , flexible and cost effective signalling subsystems are needed in the present day digital switching systems ( DSS ) . This paper describes a single board versatile signalling subsystem based on digital signal processing (DSP)/digital techniques . Specifically , the design implements all the functions required in a DSS to implement dual tone multifrequency ( DTMF , also known as multifrequency push button ) signalling and signalling system R2 ( SS R2 ) .
In this paper , a new two-step timing acquisition method combining energy detection ( ED ) scheme with the monobit digital receiver is proposed . The usage of the monobit digital receiver , with the comparator instead of high resolution ADC , can reduce the complexity greatly ; using the ED scheme to cut down the received data region , the computational load of digital signal processing ( DSP ) part can be decreased significantly . The acquisition probability of each step is analyzed in this paper .
Issues of segmentation and positioning have always been at the heart of marketing management . In recent years , much methodological progress has been made in order to carry out these two tasks simultaneously , that is , to combine certain types of clustering algorithms with appropriate multidimensional scaling or unfolding procedures . When trying to provide managers with a tool to support marketing decision-making in segmentation and positioning , the ease of use and the visual quality of results must be emphasized .
Arrangement theory plays an essential role in the study of the unfolding model used in many fields . This paper describes how arrangement theory can be usefully employed in solving the problems of counting ( i ) the number of admissible rankings in an unfolding model and ( ii ) the number of ranking patterns generated by unfolding models . The paper is mostly expository but also contains some new results such as simple upper and lower bounds for the number of ranking patterns in the unidimensional case .
In the process , we state and prove a tight upper bound on the minimum number of processors required to execute the static schedule produced by our algorithms . We also construct an unfolding algorithm for split-node graphs and combine it with our scheduling methods to achieve rate-optimality in all cases . Finally , we demonstrate our methods on a specific example .
In the framework of functional testing from algebraic specifications , the strategy of test selection which has been widely and efficiently applied is based on axiom unfolding . In this paper , we propose to extend this selection strategy to a modal formalism used to specify dynamic and reactive systems .
The aim of integration testing is to test the composition of modules assuming that they have previously been verified , i.e. assuming their correctness . One of the main method for the selection of test cases from first-order specifications , called axiom unfolding , is based on a proof search for the different instances of the property to be tested , thus allowing the coverage of this property . The idea here is to use deduction modulo as a proof system for structured first-order specifications in the context of integration testing , so as to take advantage of the knowledge of the correctness of the individual modules .
In this paper , we study the problem of exploiting parallelism when a hard real-time streaming application modeled as a Synchronous Data Flow ( SDF ) graph is mapped onto a Multi-Processor System-on-Chip ( MPSoC ) platform . We propose a new unfolding graph transformation and an algorithm that adapts the parallelism in the application according to the resources in an MPSoC by using the unfolding transformation . We evaluate the efficiency of our unfolding graph transformation and the performance and time complexity of our algorithm in comparison to the existing approaches .
Transformation rules for ( Flat ) GHC programs are presented , which re ne the previous rules proposed by one of the authors ( Furukawa et al. 1987 ) . The rules are based on unfolding/folding and are novel in that they are stated in terms of idempotent substitutions with preferred directions of bindings . They are more general than the old rules in that no mode system is assumed and that the rule of folding is included .
The accuracy of probabilistic risk assessment of rotor disks is strongly dependent on the accurate description of the size and shape distributions of anomalies in alloys . These size-shape distributions of anomalies are often derived from planar sectioning data measurements using stereological unfolding algorithms . Since it is impossible to accurately predict the shape and orientation parameters of a general ellipsoid based on measurements obtained from two-dimensional sectioning data , the anomaly model should be limited to a spheroid .
We present two classes of transformation both followed by regression . In the first application stereological unfolding is desired to reconstruct spatial data from planar sections . In the second case a grey-tone image from scanning electron microscopy is evaluated .
The template structure is unfolded by selectively ( targeted ) pulling on different portions of the protein using the geometric based technique FRODA , and then refolded using hierarchically restrained replica exchange molecular dynamics simulations ( hr-REMD ) . FRODA unfolding is used to create a diverse set of topologies for surveying near native-like structures from a template and to provide a set of persistent contacts to be employed during re-folding . We have tested our approach on 13 previous CASP targets and observed that this method of folding an ensemble of partially unfolded structures , through the hierarchical addition of contact restraints ( that is , first local and then nonlocal interactions ) , leads to a refolding of the structure along with refinement in most cases ( 12/13 ) .
The paper presents a catalogbased algorithm called the Yo-Yo Algorithm for consistent instance migration in Petri net workflow models . It uses a technique of folding and unfolding of nets . The algorithm is formulated in terms of Colored Derivation Trees , a novel representation of the runtime states of workflow nets .
To overcome this , we propose two new non-linear dimensionality reduction algorithms for evolutionary multi-objective optimization , namely C-PCA-NSGA-II and MVU-PCA-NSGA-II . While the former is based on the newly introduced correntropy PCA [ 2 ] , the later implements maximum variance unfolding principle [ 3,4,5 ] , in a novel way . We also establish the superiority of these new EMO procedures over the earlier PCA-based procedure , both in terms of accuracy and computational time , by solving upto 50-objective optimization problems .
This paper discusses the learning and educational potentialities of the Venice Unfolding prototype , an experimental tabletop application designed to explore and investigate urban and territorial contents and knowledge . The prototype supports and transforms ways of approaching various strategies involved in urban and territorial planning processes .
This distinction is easy to recognize empirically because the inter-item correlation matrix for the two types of data typically shows different patterns . Furthermore , for both types of unfolding models , correspondence analysis ( CA ) , which is a rival method for dimensionality reduction , outperforms PCA in terms of representation of both person and item locations , especially for the exponential unfolding model . Finally , it is shown that undoubled CA outperforms doubled CA for both types of unfolding models .
The first mechanism involves the stacking of the decoder on top of the representation of the encoder in a manner that preserves the temporal resolution of the sequences ; this is in contrast with architectures that encode the source into a fixed - size representation . The second mechanism is the dynamic unfolding mechanism that allows the network to process in a simple and efficient way source and target sequences of different lengths ( Sect . [ reference ] ) .
The proposed ByteNet architecture is composed of a decoder that is stacked on an encoder ( Sect . [ reference ] ) and generates variable - length outputs via dynamic unfolding ( Sect . [ reference ] ) .
This is in contrast to models that compress the source representation into a fixed - size vector or that pool over the source representation with a mechanism such as attentional pooling . subsection : Dynamic Unfolding An encoder and a decoder network that process sequences of different lengths can not be directly connected due to the different sizes of the computed representations .
In this manner the representation produced by the encoder can be efficiently computed , while maintaining high bandwidth and being resolution - preserving . Once the encoder representation is computed , we let the decoder unfold step - by - step over the encoder representation until the decoder itself outputs an end - of - sequence symbol ; the unfolding process may freely proceed beyond the estimated length of the encoder representation . Figure [ reference ] gives an example of dynamic unfolding .
section : Conclusion In this work , we have provided a unique formulation that expresses many state - of - the - art SR models as a finite unfolding of a single - state RNN with various recurrent functions . Based on this , we extend existing methods by considering a dual - state design ; the two hidden states of our proposed DSRN operate at different spatial resolutions .
uRAE + MLP : We use the Unfolding Recursive Autoencoder to get a 100 - dimensional vector representation of each sentence , and put an MLP on the top as in WordEmbed ; SENNA + MLP / sim : We use the SENNA - type sentence model for sentence representation ; SenMLP :
As stated earlier , our model is not specially tailored for modeling synonymy , and generally requires instances to work favorably . Nevertheless , our generic matching models still manage to perform reasonably well , achieving an accuracy and F1 score close to the best performer in 2008 based on hand - crafted features , but still significantly lower than the state - of - the - art ( 76.8% / 83.6 % ) , achieved with unfolding - RAE and other features designed for this task . subsection : Discussions
Pairwise interaction models were also considered to improve prediction performances . For example , the Universal Schema approach factorizes a 2D unfolding of the tensor ( a matrix of entity pairs vs. relations ) while extend this also to other pairs . In the Neural Tensor Network ( NTN ) model , combine linear transformations and multiple bilinear forms of subject and object embeddings to jointly feed them into a nonlinear neural layer .
In tensor terminology , n - mode vectors of a D - order tensor Y ∈ RI1×I2×···×ID are In - dimensional vectors obtained from Y by varying the index in Indimension , while keeping all other indices fixed . An n - mode matrix unfolding of a tensor is a matrix which has all n - mode vectors as its columns [ 7 ] . Formally we use the operator T { In}×{Ij |j∈ [ D ] \n } to denote the n - mode matrix unfolding , which returns a matrix of size In × ∏ j∈ [ D ] \n Ij .
Therefore , by clustering “ pixels ” of all images during learning , we expect to model local parts shared by multiple objects or scenes . To achieve this , we adopt the unfolding operator T { N , H , W}×{C} ( Y ) and use Rspatial ( Y , µ ) = 1 2NCHW NHW∑
Doppler Estimation from Echo Signal Using FRFT Bandlimiting Neural Networks Against Adversarial Attacks The Gabor Transform and Time-Frequency Signal Analysis Double-image self-encoding and hiding based on phase-truncated Fourier transforms and phase retrieval Reconstruction of on-axis lensless Fourier transform digital hologram with the screen division method CS reconstruction of the speech and musical signals Iterative Desensitisation of Image Restoration Filters under Wrong PSF and Noise Estimates An integrated environment for filter design Application of Artificial Intelligence Technology in Asphalt Concrete Mixer Control System Advanced speech-audio processing in mobile phones and hearing aids: Synergies and distinctions Subthreshold Source‐Coupled Logic An Underwater Communication Modem Using TMS320C6416 DSK Hydrological comprehensive measurement device Digital Signal Processing: A System Design Approach From Matched Spatial Filtering towards the Fused Statistical Descriptive Regularization Method for Enhanced Radar Imaging Matlab Teaching Study in "Digital Signal Processing" Course Testing method of spectrum feature of optical passive device Recovery of radar's beat signal based on compressive sampling SIM-DSP: A DSP-Enhanced CAD Platform for Signal Integrity Macromodeling and Simulation Adaptive Filtering Technique and Comparison of PS25015A Dry Electrodes and Two Different Ag/AgCl Wet Electrodes for Wearable ECG Applications Nonlinear acoustic echo cancellation with kernelized adaptive filters Fast and Adaptive Lossless Onboard Hyperspectral Data Compression System Adaptive filtering for baseline wander removal in ECG Design of LMS algorithm for noise canceller based on FPGA A modified combined LMS/F algorithm and its application in adaptive cosite interference cancellation Performance Analysis of Floating Point MAC Unit Extra bass circuit and television with extra bass circuit Very Fast Multi Operand Addition Method by Bitwise Subtraction An Accurate Exploration of Timing and Area Trade-offs in Arithmetic Optimization using Carry-Save-Adders Design of an Efficient Multilayer Arithmetic Logic Unit in Quantum-Dot Cellular Automata (QCA) Approximate XOR/XNOR-based adders for inexact computing An Analytical Framework for Evaluating the Error Characteristics of Approximate Adders Quantum Circuit Designs of Integer Division Optimizing T-Count and T-Depth Comparison of logarithmic and floating-point number systems implemented on Xilinx Virtex-II field-programmable gate arrays A modified redundant binary adder for efficient VLSI architecture A high speed low power modulo 2n+1 multiplier design using carbon-nanotube technology On the quality of accumulator-based compaction of test responses Sequence-addressable DNA logic. A/D conversion based on signal decomposition for DSP applications Architecture-driven synthesis techniques for VLSI implementation of DSP algorithms An intelligent control scheme for precise tip-motion control in atomic force microscopy. IDENTIFICATION OF HOTSPOTS IN PROTEIN SEQUENCES USING CPNR AND DWT Sensorless Control for Ship Electric Propulsion IPMSM Drives using Fuzzy Neuro-network Direct Sequence Spread Spectrum Transmitter using FPGAs Making process of digital audio/video collecting and compressing card Electric vehicle charging power demand predicting system Position detection for element in picture A compact multifunction signalling subsystem A two-step IR-UWB acquisition method based on monobit receiver Managerial applicability of graphical formats to support positioning decisions MATHEMATICAL ENGINEERING TECHNICAL REPORTS Application of Arrangement Theory to Unfolding Models Time-constrained loop scheduling with minimal resources Test Selection Criteria for Modal Specifications of Reactive Systems Integration Testing from Structured First-Order Specifications via Deduction Modulo Exploiting resource-constrained parallelism in hard real-time streaming applications Transformation Rules for GHC Programs Estimating the Probabilistic Size and Shape Distributions of 3D Anomalies From Sectioning Measurements Using the Stereological Unfolding Approach Spatial Statistics in the Material Research Partial unfolding and refolding for structure refinement: A unified approach of geometric simulations and molecular dynamics. Catalog-based Token Transportation in Acyclic Block-Structured WF-nets Non-linear Dimensionality Reduction Procedures for Certain Large-Dimensional Multi-objective Optimization Problems: Employing Correntropy and a Novel Maximum Variance Unfolding Browsing and correlating architectural and territorial data in tangible maps - New knowledge opportunities in new learning places Two types of single-peaked data: Correspondence analysis as an alternative to principal component analysis Neural Machine Translation in Linear Time Image Super-Resolution via Dual-State Recurrent Networks Convolutional Neural Network Architectures for Matching Natural Language Sentences Complex Embeddings for Simple Link Prediction Learning Deep Parsimonious Representations
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FSKD (4) WASPAA Advanced Circuits for Emerging Technologies CSE (2) ITNG MWSCAS TASE ICTAC DATE FGCS PNSE @ Petri Nets EMO ArXiv 2018 IEEE/CVF Conference on Computer Vision and Pattern Recognition NIPS ICML NIPS
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