The contributions of this thesis towards the area of packet classification are hardware accelerators that allow packet classification to be implemented at core network line speeds when classifying packets using rulesets containing tens of thousands of rules . The hardware accelerators use modified versions of the HyperCuts packet classification algorithm . An adaptive clocking unit is also presented that dynamically adjusts the clock speed of a packet classification hardware accelerator so that its processing capacity matches the processing needs of the network traffic . To sustain the high throughput required by applications like network servers , high-speed implementations of public-key cryptosystems are needed . For that purpose , hardware-based accelerators are often the only solution reaching an acceptable performance-cost ratio . The fundamental question that arises is how to choose the appropriate efficiency-flexibility tradeoff . We describe how to represent the parallel architecture of the desired circuit using multi-threaded code which models the key architectural aspects of the circuits . We argue that descriptions in a regular , high-level language that can be automatically compiled into circuits makes hardware-based accelerators more accessible to software engineers . At high thread counts , execution time is dominated by worklist synchronization overhead and cache misses . Researchers have proposed hardware worklist accelerators to address scheduling costs , but these proposals often harden a specific scheduling policy and do not address high cache miss rates . We address this with Minnow , a technique that augments each core in a CMP with a lightweight Minnow accelerator . Researchers have demonstrated the benefits of hardware worklist accelerators , which offload scheduling and load balancing operations in parallel graph applications . However , many of these applications are still heavily memory latency-bound due to the irregular nature of graph data structure access patterns . This paper investigates the use of Triple Modular Redundancy ( TMR ) in hardware accelerators designs described in C programming language and synthesized by High Level Synthesis ( HLS ) . A setup composed of a soft-core processor and a matrix multiplication design protected by TMR and embedded into an SRAM-based FPGA was analyzed under accumulated bit-flips in its configuration memory bits . However , while the error tolerance of ANN algorithms is well documented , there are few in-depth attempts at demonstrating that an actual hardware ANN would be tolerant to faulty transistors . Most fault models are abstract and can not demonstrate that the error tolerance of ANN algorithms can be translated into the defect tolerance of hardware ANN accelerators . In this article , we introduce a hardware ANN geared towards defect tolerance and energy efficiency , by spatially expanding the ANN . In recent years , it is increasingly common to see using application specific instruction set processors ( ASIPs ) in embedded system designs . These ASIPs can offer the ability of customizing hardware computation accelerators for an application domain . Along with instruction set extensions ( ISEs ) , the customized accelerators can significantly improve the performance of embedded processors , which has already been exemplified in previous research work and industrial products . The cryptosystems are implemented using C++ on Intel(R ) Xeon(R ) multi-core 64-bit processors machine with CUDA-enabled Tesla K80 GPUs . The parallel implementation is based on OpenCL framework and can run on arbitrary hardware platform accelerators with minor changes . Several optimizations and efficient algorithms were used to compute the core operations in each cryptosystem to achieve optimum performance . In order to program the SPU we have developed an automatic toolchain that profiles an application and discovers its main computing bottlenecks . With that information our toolchain is able to both design hardware specific accelerators that can be automatically mapped in the aforementioned SPU , and generate the binary code necessary to run the application using those accelerators . The OpenSPARC with the new specific application accelerators , defined in a Hardware Description Language , can then be executed and measured . Furthermore , portability and standardization are discussed and the overhead associated with PAPI use is evaluated . Two hardware examples are proposed to evaluate this approach : a simple counter and an infrastructure for hardware accelerators called ARTICo3 . Therefore , dynamic resource management to adapt the system to different needs is required . In this paper , a new bus-based architecture , called ARTICo3 , which by means of Dynamic Partial Reconfiguration , allows the replication of hardware tasks to support module redundancy , multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented . A configuration-aware data transaction unit permits data dispatching to more than one module in parallel , or provide coalesced data dispatching among different units to maximize the advantages of burst transactions . System self-awareness enables the use of strategies to enhance system performance and power optimization taking into account run-time metrics . This is of particular importance when dealing with reconfigurable systems that may make use of such information for efficient resource management , such as in the case of the ARTICo3 architecture , which fosters dynamic execution of kernels formed by multiple blocks of threads allocated in a variable number of hardware accelerators , combined with module redundancy for fault tolerance and other dependability enhancements , e.g. side-channel-attack protection . In this paper , a model for efficient dynamic resource management focused on both power consumption and execution times in the ARTICo3 architecture is proposed . The approach enables the characterization of kernel execution by using the model , providing additional decision criteria based on energy efficiency , so that resource allocation and scheduling policies may adapt to changing conditions . IMPRESS is a reconfiguration tool for building highly-flexible reconfigurable systems . The integration of both tools results in an efficient reconfigurable design flow that decouples the implementation of reconfigurable accelerators from the implementation of an ARTICo3 static architecture that transparently distributes data to the accelerators . This static architecture is generated only once and reused in consecutive kernel implementations . Algorithmic modifications have been proposed to enable data-level parallelism and foster scalability in two ways : on the one hand , in the number of accelerators per reconfigurable device ; on the other hand , in the number of network nodes . Experimental results motivate the use of ARTICo3-enabled systems for on-board processing in applications traditionally addressed by high-performance on-Earth computation . Results also show that the proposed implementation may be better , for certain configurations , than an equivalent software-based solution in both performance and energy efficiency , achieving great scalability that is only limited by communication bandwidth . Over time , the SATA standard has been revised to provide greater bandwidth , with SATA III being the newest version of the standard . In this paper , we are the first to present a SATA III core designed for Altera Stratix V FPGAs . Our implementation is written using Verilog , and tested using an industry-standard SATA protocol analyzer . This paper introduces an application for Asian option pricing based on Curran 's approximation method that exploits a dataflow-oriented development approach , employing dedicated optimisations and replacing conventional floating-point with fixed-point formats wherever possible . The implementation targets a Maxeler server-class HPC system consisting of a CPU server node and Maxeler dataflow engines encapsulating Altera Stratix V FPGAs . The application has been evaluated on two different data sets and achieves a speed-up of 111x and 278.3x compared to a single-threaded software implementation , and 4x and 9.2x compared to a multi-threaded software implementation running on a dual socket CPU server with 12-core Intel Xeon E5 - 2697 v2 CPUs with up to 48 hyper-threads in total . In particular , the < inline-formula><tex-math notation="LaTeX">$n$</tex-math><alternatives > < inline-graphic xlink : href="arram-ieq1 - 2535385.gif"/></alternatives></inline-formula>-step FM-index , index oversampling , a seed-and-compare stage , and bi-directional backtracking are included . Our design is implemented and evaluated on a 1U Maxeler MPC-X2000 dataflow node with eight Altera Stratix-V FPGAs . Measurements show that our design is 28 times faster than Bowtie2 running with 16 threads on dual Intel Xeon E5 - 2640 CPUs , and nine times faster than Soap3-dp running on an NVIDIA Tesla C2070 GPU . The fault coverage of ROTE is also expected to be high at fault/defect densities of up to 25 % using our 1-diagnosable BISTer and up to 33 % using our 2-diagnosable BISTer . Our methods should thus prove useful for testing current very deep submicron FPGAs as well as future nano-CMOS and molecular nanotechnology FPGAs in which defect densities are expected to be in the 10 % range . From the Publisher : Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools , with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes . Three factors combine to determine the performance of an FPGA : the quality of the CAD tools used to map circuits into the FPGA , the quality of the FPGA architecture , and the electrical ( i.e. transistor-level ) design of the FPGA . This work presents a high-speed communication link implementation for a high-resolution camera used in a low earth orbit ( LEO ) satellite , that was already in space . The whole acquisition system involves three Microsemi FPGAs that move a great amount of data over a multi-link high-speed serial channel . The implementation of a custom protocol is proposed to perform a point-to-point communication . A kind of high speed and parallel hardware architecture is proposed and designed for digital signal processing of high frequency Pulse Doppler radar here . The platform is based on one XC7K410 T FPGA , two XC7K325 T FPGAs , one TMS320C6678 DSP , and four sets of MT41J256M8 DDR3 . The details of implementation including pulse compression , moving target detection and constant-false-alarm rate are described . Concurrent Logic CLi6000 devices are high granularity , RAM-based reconfigurable FPGAs . The architecture consists of a grid of small cells surrounded by programmable input/output blocks and programmable interconnect . It successfully overcomes the limitation of the existing SPFD-based local rewiring ( SPFD-LR ) that can only replace a wire with another wire having the same sink node . We apply SPFD-GR to the post-mapping area reduction for LUTbased FPGAs under circuit depth restriction . Experimental results show that the rewiring ability of SPFD-GR , in terms of the number of target wires found to ha ve alternative wires , is 1.45 and 3 times that of SPFD-LR and an ATPG algorithm ( with a preliminary experimental flow ) , respectively , and the run time is quite acceptable . It is being explored as one of the alternative technologies which may replace CMOS in the future . In this work , QCA based nano FPGAs are designed and simulated . The designs of the Configurable Logic Block ( CLB ) and the Programmable Switch Matrix ( PSM ) are first developed separately and then integrated together to form a complete QCA based FPGA . This initialised partially connected network is then trained using training data . The trained neural network is then implemented by fine-grain Xilinx XC6200 series FPGAs . This implementation requires fewer connections and can provide a very high speed classification for many real-time image recognition applications . However , SRAM-based FPGAs are very susceptible to neutron-induced soft errors . Consequently , an ANN running in SRAM-based FPGAs devices must be characterized under soft errors . This work shows the soft error effects of a feedforward ANN under fault injection emulation performed in the bitstream of the FPGA . This limits the generalization levels to a fixed and predefined set of LODs , and generally does not support smooth LOD transitions . However , fast GPUs and novel line rendering techniques can be exploited to integrate dynamic vector map LOD management into GPU‐based algorithms for locally‐adaptive line simplification and real‐time rendering . We propose a new technique that interactively visualizes large line vector datasets at variable LODs . In addition , we expose auto-tuning parameters to further enhance performance portability . We implemented a selection of convolution operations , covering the core operations needed for deploying three common image-processing neural networks , and tuned them for NVIDIA , AMD , and ARM Mali GPUs . Our experiments show that we can generate deep-learning kernels with minimal effort for new platforms and achieve reasonable performance . We present a customizable Collective Knowledge workflow to study the execution time vs. accuracy trade-offs for the MobileNets CNN family . We use this workflow to evaluate MobileNets on Arm Cortex CPUs using TensorFlow and Arm Mali GPUs using several versions of the Arm Compute Library . Our optimizations for the Arm Bifrost GPU architecture reduce the execution time by 2 - -3 times , while lying on a Pareto-optimal frontier . In this paper , the influence of one-sample delay for sampling and computation in digital control on the bandwidth of the inner current loop of a 400-Hz ground power unit ( GPU ) is analyzed first . The results show that it is difficult and even impossible for high-power 400-Hz GPUs to maintain low total harmonic distortion content in the output voltage with the conventional proportional-integral-based double-loop control . To improve the performance , resonant controllers with parallel structure which are widely used in active power filters are applied to the single-loop control of the 400-Hz GPU . The increase in performance of the last generations of graphics processors ( GPUs ) has made this class of platform a coprocessing tool with remarkable success in certain types of operations . In this paper we evaluate the performance of the Level 3 operations in CUBLAS , the implementation of BIAS for NVIDIAreg GPUs with unified architecture . From this study , we gain insights on the quality of the kernels in the library and we propose several alternative implementations that are competitive with those in CUBLAS . We present the design of our novel parallel algorithm Graphics processor Accelerated BFAST ( GrABFAST ) for large scale read alignment that overcomes these challenges and demonstrates superior performance compared to Intel multi-core architectures . Using 5 large genomes including those of Humans , Maize , Horse , Dog and Bacteria , we demonstrate a speedup of around 6x using Fermi Tesla C2070 GPUs vs the BFAST algorithm on 16 core Intel Xeon 5570 architecture . The advent of big datasets and high speed GPUs is fueling the growth in machine and deep learning techniques . In this paper we explore storing the training data in object storage and demonstrate how this can be done effectively while providing sufficient throughput to high performance GPUs . Advances in the video gaming industry have led to the production of low-cost , high-performance graphics processing units ( GPUs ) that possess more memory bandwidth and computational capability than central processing units ( CPUs ) , the standard workhorses of scientific computing . With the recent release of generalpurpose GPUs and NVIDIA ’s GPU programming language , CUDA , graphics engines are being adopted widely in scientific computing applications , particularly in the fields of computational biology and bioinformatics . The goal of this article is to concisely present an introduction to GPU hardware and programming , aimed at the computational biologist or bioinformaticist . We demonstrate the effectiveness of our proposed techniques by running experiments on the 2000-hour Switchboard speech recognition task and the ImageNet computer vision task . On an IBM P9 supercomputer , our system is able to train an LSTM acoustic model in 2.28 hours with 7.5 % WER on the Hub5 - 2000 Switchboard ( SWB ) test set and 13.3 % WER on the CallHome ( CH ) test set using 64 V100 GPUs and in 1.98 hours with 7.7 % WER on SWB and 13.3 % WER on CH using 128 V100 GPUs , the fastest training time reported to date . Image enhancement specific for infrared images is also implemented and evaluated , based on the Contrast Lim- ited Adaptive Histogram Equalization ( CLAHE ) . An embedded SLAM algorithm is presented with different hardware acceler- ators ( point detection , landmark tracking , active search , correlation , matrix operations ) . All the algorithms were simulated , implemented and verified using as target FPGAs . In this paper , we summarize the new development of hardware-acceler ation techniques and a parallel conformal Finite­ Difference Time-Domain ( FDTD ) method in computational electromagnetics engineering . We investigate the performance of a parallel conformal FDTD method on different hardware platforms , such as Intel and AMD processors , with vector-arithmeti c logic unit ( VALU ) acceleration , a regular PC clu ster , a high-performance server cluster , the use of a graphics-process ing unit ( GPU ) , and an IBM CELL processor . In addition , the FPGA can be reprogrammed for different data processing operations with high flexibility . The experimental results for one hundred 512 × 512 floating point matrix multiplications show that the proposed hardware accelerator platform with four FPGA EVBs at 125MHz clock rate can achieve the 4x speedup as compared with the computing server with an Intel I7 - 4770 CPU at 3.4GHz . In this paper , a saliency-based field-programmable gate array accelerator for revolutionary LCD power management is proposed that allows dynamic modulation of the different zones of the backlight panel . This hardware accelerator-based system is capable of processing a high-definition video stream in real-time and uses less than 50 % of the power that a normal LCD display system consumes , with minimum overhead . We also compare our proposed approach with other state-of-the-art power-aware methods and show numerous advantages using our data-driven strategy . Abstract The paper discusses the development of a hardware accelerator environment for ASIC design verification . A reprogrammable gate array serves as a breadboard for the ASIC design . We evaluate the execution time of the whole filtering process . Than we add a hardware accelerator part . This latter is implemented using fast parallel architecture . After that , we give a possible classification of image compression techniques , from the architecture requirements point of view , with a focus on a class of techniques for which the improvement is proposed . Finally , we introduce the proposed hardware accelerator solution , analyze the expected performance improvement , and discuss the implementational complexity . In conclusion , we present our plans for future work on the subject.<<ETX > > In this work , FPGA based pipelined architecture for blind and robust image watermarking algorithm has been presented using Wavelet Co-efficients Quantization . The architecture is designed using new hardware accelerator tool of Xilinx System Generator . The goal of this work is to utilize the option of System Generator for the designing of signal processing algorithm on FPGA and to optimize the design in terms of latency and hardware resources . Fractal dynamics can be used as an irregularity measure of signals and our work shows that it is a key discriminant for classification of falls from other activities of life . We design , implement and evaluate a hardware feature accelerator for computation of fractal features through multi-level wavelet transform on a reconfigurable embedded System on Chip , Zynq device for evaluating wearable accelerometer sensors . The proposed FDS utilises a hardware/software co-design approach with hardware accelerator for fractal features and software implementation of Linear Discriminant Analysis on an embedded ARM core for high accuracy and energy efficiency . The main challenges Level-1 track finding faces are the large data throughput from the detector at a collision rate of 40 MHz and a 4 microsecond latency budget to reconstruct charged particle tracks with sufficiently low transverse momentum to be used in the Level-1 trigger decision . Dedicated all-FPGA hardware systems with time-multiplexed architecture have been developed for track finding to address these challenges . The algorithm and performance of the pattern recognition and particle trajectory determination are discussed . The paper presents a multichannel digital processor based on a configurable computing ( FPGA ) device for acquisition and programmable data processing in multi-detector systems . Main features of the processor are reconfigurability , linearity , low noise and processing data rate through hardware and firmware architecture solutions that also allow the system to operate in presence of electromagnetic noise , while at the same time minimizing its own radiated emissions . There are well known cases where FPGAs provide high performance within a modest power budget , yet unlike conventional desktop solutions , they are oftentimes associated with long wait times before a device configuration is generated . Such long wait times constitute a bottleneck limiting the number of compilation runs performed in a day ; thus limiting to FPGA adaptation in modern computing platforms . This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity . In particular , the generation of both Gaussian ( low-pass ) and Laplacian ( band-pass ) pyramids can occur concurrently in real time using images from a video camera , assuming the standard frame rate of 30 images per second . Results are presented to illustrate the efficacy of reconfigurable FPGA-based machines to image processing applications.<<ETX > > A FPGA hardware core has been designed for real-time network simulations with up to 400 physiologically realistic , conductance-based neurons of the Hodgkin-Huxley type . A PC-FPGA interface allows easy parameter adjustment and on-line display of basic synchronization measures like field potentials , spike times or color-coded voltages of the complete array . Consequently , it becomes possible to design an FPGA accelerator that performs streaming memory accesses and parallel wavefront expansion on all wires in two connected sets . To test and evaluate our FPGA-accelerated PathFinder-based router , we implement it on DE1-SoC , Intel 's ARM+FPGA platform and run a set of benchmarks from the VTR suite . The results show that our implementation produces deterministic and good quality output . A Reconfigurable Processor for Forward Error Correction.- FPGA-Accelerated Deletion-Tolerant Coding for Reliable Distributed Storage.- LIRAC : Using Live Range Information to Optimize Memory Access.- Optimized Register Renaming Scheme for Stack-Based x86 Operations.- A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.- Customized Placement for High Performance Embedded Processor Caches.- A Multiprocessor Cache for Massively Parallel SoC Architectures.- Improving Resource Discovery in the Arigatoni Overlay Network.- An Effective Multi-hop Broadcast in Vehicular Ad-Hoc Network.- Functional Knowledge Exchange Within an Intelligent Distributed System.- Architecture for Collaborative Business Items.- Autonomic Management Architecture for Flexible Grid Services Deployment Based on Policies.- Variations and Evaluations of an Adaptive Accrual Failure Detector to Enable Self-healing Properties in Distributed Systems.- Self-organizing Software Components in Distributed Systems.- Toward Self-adaptive Embedded Systems : Multi-objective Hardware Evolution.- Measurement and Control of Self-organised Behaviour in Robot Swarms.- Autonomous Learning of Load and Traffic Patterns to Improve Cluster Utilization.- Parametric Architecture for Function Calculation Improvement.- Design Space Exploration of Media Processors : A Generic VLIW Architecture and a Parameterized Scheduler.- Modeling of Interconnection Networks in Massively Parallel Processor Architectures.- Invited Talk : Expanding Software Product Families : DNNs rely on a growing variety of matrix multiply operations ( i.e. , dense to sparse , FP32 to N-bit ) . We propose an OpenCL-based matrix multiply design template , which enables automated design exploration to generate optimized FPGA matrix accelerators for DNN applications . Given the desired matrix operations ( e.g. , sparsity , data types ) , our template rapidly produces performance and area estimates for a variety of design variants and/or FPGA platforms . The receiver is based on NovAtel ’s new FPGA based precise positioning receiver , the Euro-L5 . The receiver FPGA and software is configured to track the open service BOC(1,1 ) signal that will be transmitted on the Galileo L1 frequency . To reduce hardware design costs for this pre-production prototype development , the design was demonstrated at the L5/E5a frequency . In this paper we present an FPGA-based daughtercard designed for TIs C6000family of DSP starter kits ( DSKs ) . The hardware , initially designed for a course project , provides a platform for studying heterogeneous systems and hardware software co-design .
The contributions of this thesis towards the area of packet classification are hardware accelerators that allow packet classification to be implemented at core network line speeds when classifying packets using rulesets containing tens of thousands of rules . The hardware accelerators use modified versions of the HyperCuts packet classification algorithm . An adaptive clocking unit is also presented that dynamically adjusts the clock speed of a packet classification hardware accelerator so that its processing capacity matches the processing needs of the network traffic .
To sustain the high throughput required by applications like network servers , high-speed implementations of public-key cryptosystems are needed . For that purpose , hardware-based accelerators are often the only solution reaching an acceptable performance-cost ratio . The fundamental question that arises is how to choose the appropriate efficiency-flexibility tradeoff .
We describe how to represent the parallel architecture of the desired circuit using multi-threaded code which models the key architectural aspects of the circuits . We argue that descriptions in a regular , high-level language that can be automatically compiled into circuits makes hardware-based accelerators more accessible to software engineers .
At high thread counts , execution time is dominated by worklist synchronization overhead and cache misses . Researchers have proposed hardware worklist accelerators to address scheduling costs , but these proposals often harden a specific scheduling policy and do not address high cache miss rates . We address this with Minnow , a technique that augments each core in a CMP with a lightweight Minnow accelerator .
Researchers have demonstrated the benefits of hardware worklist accelerators , which offload scheduling and load balancing operations in parallel graph applications . However , many of these applications are still heavily memory latency-bound due to the irregular nature of graph data structure access patterns .
This paper investigates the use of Triple Modular Redundancy ( TMR ) in hardware accelerators designs described in C programming language and synthesized by High Level Synthesis ( HLS ) . A setup composed of a soft-core processor and a matrix multiplication design protected by TMR and embedded into an SRAM-based FPGA was analyzed under accumulated bit-flips in its configuration memory bits .
However , while the error tolerance of ANN algorithms is well documented , there are few in-depth attempts at demonstrating that an actual hardware ANN would be tolerant to faulty transistors . Most fault models are abstract and can not demonstrate that the error tolerance of ANN algorithms can be translated into the defect tolerance of hardware ANN accelerators . In this article , we introduce a hardware ANN geared towards defect tolerance and energy efficiency , by spatially expanding the ANN .
In recent years , it is increasingly common to see using application specific instruction set processors ( ASIPs ) in embedded system designs . These ASIPs can offer the ability of customizing hardware computation accelerators for an application domain . Along with instruction set extensions ( ISEs ) , the customized accelerators can significantly improve the performance of embedded processors , which has already been exemplified in previous research work and industrial products .
The cryptosystems are implemented using C++ on Intel(R ) Xeon(R ) multi-core 64-bit processors machine with CUDA-enabled Tesla K80 GPUs . The parallel implementation is based on OpenCL framework and can run on arbitrary hardware platform accelerators with minor changes . Several optimizations and efficient algorithms were used to compute the core operations in each cryptosystem to achieve optimum performance .
In order to program the SPU we have developed an automatic toolchain that profiles an application and discovers its main computing bottlenecks . With that information our toolchain is able to both design hardware specific accelerators that can be automatically mapped in the aforementioned SPU , and generate the binary code necessary to run the application using those accelerators . The OpenSPARC with the new specific application accelerators , defined in a Hardware Description Language , can then be executed and measured .
Furthermore , portability and standardization are discussed and the overhead associated with PAPI use is evaluated . Two hardware examples are proposed to evaluate this approach : a simple counter and an infrastructure for hardware accelerators called ARTICo3 .
Therefore , dynamic resource management to adapt the system to different needs is required . In this paper , a new bus-based architecture , called ARTICo3 , which by means of Dynamic Partial Reconfiguration , allows the replication of hardware tasks to support module redundancy , multi-thread operation or dual-rail solutions for enhanced side-channel attack protection is presented . A configuration-aware data transaction unit permits data dispatching to more than one module in parallel , or provide coalesced data dispatching among different units to maximize the advantages of burst transactions .
System self-awareness enables the use of strategies to enhance system performance and power optimization taking into account run-time metrics . This is of particular importance when dealing with reconfigurable systems that may make use of such information for efficient resource management , such as in the case of the ARTICo3 architecture , which fosters dynamic execution of kernels formed by multiple blocks of threads allocated in a variable number of hardware accelerators , combined with module redundancy for fault tolerance and other dependability enhancements , e.g. side-channel-attack protection . In this paper , a model for efficient dynamic resource management focused on both power consumption and execution times in the ARTICo3 architecture is proposed . The approach enables the characterization of kernel execution by using the model , providing additional decision criteria based on energy efficiency , so that resource allocation and scheduling policies may adapt to changing conditions .
IMPRESS is a reconfiguration tool for building highly-flexible reconfigurable systems . The integration of both tools results in an efficient reconfigurable design flow that decouples the implementation of reconfigurable accelerators from the implementation of an ARTICo3 static architecture that transparently distributes data to the accelerators . This static architecture is generated only once and reused in consecutive kernel implementations .
Algorithmic modifications have been proposed to enable data-level parallelism and foster scalability in two ways : on the one hand , in the number of accelerators per reconfigurable device ; on the other hand , in the number of network nodes . Experimental results motivate the use of ARTICo3-enabled systems for on-board processing in applications traditionally addressed by high-performance on-Earth computation . Results also show that the proposed implementation may be better , for certain configurations , than an equivalent software-based solution in both performance and energy efficiency , achieving great scalability that is only limited by communication bandwidth .
Over time , the SATA standard has been revised to provide greater bandwidth , with SATA III being the newest version of the standard . In this paper , we are the first to present a SATA III core designed for Altera Stratix V FPGAs . Our implementation is written using Verilog , and tested using an industry-standard SATA protocol analyzer .
This paper introduces an application for Asian option pricing based on Curran 's approximation method that exploits a dataflow-oriented development approach , employing dedicated optimisations and replacing conventional floating-point with fixed-point formats wherever possible . The implementation targets a Maxeler server-class HPC system consisting of a CPU server node and Maxeler dataflow engines encapsulating Altera Stratix V FPGAs . The application has been evaluated on two different data sets and achieves a speed-up of 111x and 278.3x compared to a single-threaded software implementation , and 4x and 9.2x compared to a multi-threaded software implementation running on a dual socket CPU server with 12-core Intel Xeon E5 - 2697 v2 CPUs with up to 48 hyper-threads in total .
In particular , the < inline-formula><tex-math notation="LaTeX">$n$</tex-math><alternatives > < inline-graphic xlink : href="arram-ieq1 - 2535385.gif"/></alternatives></inline-formula>-step FM-index , index oversampling , a seed-and-compare stage , and bi-directional backtracking are included . Our design is implemented and evaluated on a 1U Maxeler MPC-X2000 dataflow node with eight Altera Stratix-V FPGAs . Measurements show that our design is 28 times faster than Bowtie2 running with 16 threads on dual Intel Xeon E5 - 2640 CPUs , and nine times faster than Soap3-dp running on an NVIDIA Tesla C2070 GPU .
The fault coverage of ROTE is also expected to be high at fault/defect densities of up to 25 % using our 1-diagnosable BISTer and up to 33 % using our 2-diagnosable BISTer . Our methods should thus prove useful for testing current very deep submicron FPGAs as well as future nano-CMOS and molecular nanotechnology FPGAs in which defect densities are expected to be in the 10 % range .
From the Publisher : Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools , with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes . Three factors combine to determine the performance of an FPGA : the quality of the CAD tools used to map circuits into the FPGA , the quality of the FPGA architecture , and the electrical ( i.e. transistor-level ) design of the FPGA .
This work presents a high-speed communication link implementation for a high-resolution camera used in a low earth orbit ( LEO ) satellite , that was already in space . The whole acquisition system involves three Microsemi FPGAs that move a great amount of data over a multi-link high-speed serial channel . The implementation of a custom protocol is proposed to perform a point-to-point communication .
A kind of high speed and parallel hardware architecture is proposed and designed for digital signal processing of high frequency Pulse Doppler radar here . The platform is based on one XC7K410 T FPGA , two XC7K325 T FPGAs , one TMS320C6678 DSP , and four sets of MT41J256M8 DDR3 . The details of implementation including pulse compression , moving target detection and constant-false-alarm rate are described .
Concurrent Logic CLi6000 devices are high granularity , RAM-based reconfigurable FPGAs . The architecture consists of a grid of small cells surrounded by programmable input/output blocks and programmable interconnect .
It successfully overcomes the limitation of the existing SPFD-based local rewiring ( SPFD-LR ) that can only replace a wire with another wire having the same sink node . We apply SPFD-GR to the post-mapping area reduction for LUTbased FPGAs under circuit depth restriction . Experimental results show that the rewiring ability of SPFD-GR , in terms of the number of target wires found to ha ve alternative wires , is 1.45 and 3 times that of SPFD-LR and an ATPG algorithm ( with a preliminary experimental flow ) , respectively , and the run time is quite acceptable .
It is being explored as one of the alternative technologies which may replace CMOS in the future . In this work , QCA based nano FPGAs are designed and simulated . The designs of the Configurable Logic Block ( CLB ) and the Programmable Switch Matrix ( PSM ) are first developed separately and then integrated together to form a complete QCA based FPGA .
This initialised partially connected network is then trained using training data . The trained neural network is then implemented by fine-grain Xilinx XC6200 series FPGAs . This implementation requires fewer connections and can provide a very high speed classification for many real-time image recognition applications .
However , SRAM-based FPGAs are very susceptible to neutron-induced soft errors . Consequently , an ANN running in SRAM-based FPGAs devices must be characterized under soft errors . This work shows the soft error effects of a feedforward ANN under fault injection emulation performed in the bitstream of the FPGA .
This limits the generalization levels to a fixed and predefined set of LODs , and generally does not support smooth LOD transitions . However , fast GPUs and novel line rendering techniques can be exploited to integrate dynamic vector map LOD management into GPU‐based algorithms for locally‐adaptive line simplification and real‐time rendering . We propose a new technique that interactively visualizes large line vector datasets at variable LODs .
In addition , we expose auto-tuning parameters to further enhance performance portability . We implemented a selection of convolution operations , covering the core operations needed for deploying three common image-processing neural networks , and tuned them for NVIDIA , AMD , and ARM Mali GPUs . Our experiments show that we can generate deep-learning kernels with minimal effort for new platforms and achieve reasonable performance .
We present a customizable Collective Knowledge workflow to study the execution time vs. accuracy trade-offs for the MobileNets CNN family . We use this workflow to evaluate MobileNets on Arm Cortex CPUs using TensorFlow and Arm Mali GPUs using several versions of the Arm Compute Library . Our optimizations for the Arm Bifrost GPU architecture reduce the execution time by 2 - -3 times , while lying on a Pareto-optimal frontier .
In this paper , the influence of one-sample delay for sampling and computation in digital control on the bandwidth of the inner current loop of a 400-Hz ground power unit ( GPU ) is analyzed first . The results show that it is difficult and even impossible for high-power 400-Hz GPUs to maintain low total harmonic distortion content in the output voltage with the conventional proportional-integral-based double-loop control . To improve the performance , resonant controllers with parallel structure which are widely used in active power filters are applied to the single-loop control of the 400-Hz GPU .
The increase in performance of the last generations of graphics processors ( GPUs ) has made this class of platform a coprocessing tool with remarkable success in certain types of operations . In this paper we evaluate the performance of the Level 3 operations in CUBLAS , the implementation of BIAS for NVIDIAreg GPUs with unified architecture . From this study , we gain insights on the quality of the kernels in the library and we propose several alternative implementations that are competitive with those in CUBLAS .
We present the design of our novel parallel algorithm Graphics processor Accelerated BFAST ( GrABFAST ) for large scale read alignment that overcomes these challenges and demonstrates superior performance compared to Intel multi-core architectures . Using 5 large genomes including those of Humans , Maize , Horse , Dog and Bacteria , we demonstrate a speedup of around 6x using Fermi Tesla C2070 GPUs vs the BFAST algorithm on 16 core Intel Xeon 5570 architecture .
The advent of big datasets and high speed GPUs is fueling the growth in machine and deep learning techniques . In this paper we explore storing the training data in object storage and demonstrate how this can be done effectively while providing sufficient throughput to high performance GPUs .
Advances in the video gaming industry have led to the production of low-cost , high-performance graphics processing units ( GPUs ) that possess more memory bandwidth and computational capability than central processing units ( CPUs ) , the standard workhorses of scientific computing . With the recent release of generalpurpose GPUs and NVIDIA ’s GPU programming language , CUDA , graphics engines are being adopted widely in scientific computing applications , particularly in the fields of computational biology and bioinformatics . The goal of this article is to concisely present an introduction to GPU hardware and programming , aimed at the computational biologist or bioinformaticist .
We demonstrate the effectiveness of our proposed techniques by running experiments on the 2000-hour Switchboard speech recognition task and the ImageNet computer vision task . On an IBM P9 supercomputer , our system is able to train an LSTM acoustic model in 2.28 hours with 7.5 % WER on the Hub5 - 2000 Switchboard ( SWB ) test set and 13.3 % WER on the CallHome ( CH ) test set using 64 V100 GPUs and in 1.98 hours with 7.7 % WER on SWB and 13.3 % WER on CH using 128 V100 GPUs , the fastest training time reported to date .
Image enhancement specific for infrared images is also implemented and evaluated , based on the Contrast Lim- ited Adaptive Histogram Equalization ( CLAHE ) . An embedded SLAM algorithm is presented with different hardware acceler- ators ( point detection , landmark tracking , active search , correlation , matrix operations ) . All the algorithms were simulated , implemented and verified using as target FPGAs .
In this paper , we summarize the new development of hardware-acceler ation techniques and a parallel conformal Finite­ Difference Time-Domain ( FDTD ) method in computational electromagnetics engineering . We investigate the performance of a parallel conformal FDTD method on different hardware platforms , such as Intel and AMD processors , with vector-arithmeti c logic unit ( VALU ) acceleration , a regular PC clu ster , a high-performance server cluster , the use of a graphics-process ing unit ( GPU ) , and an IBM CELL processor .
In addition , the FPGA can be reprogrammed for different data processing operations with high flexibility . The experimental results for one hundred 512 × 512 floating point matrix multiplications show that the proposed hardware accelerator platform with four FPGA EVBs at 125MHz clock rate can achieve the 4x speedup as compared with the computing server with an Intel I7 - 4770 CPU at 3.4GHz .
In this paper , a saliency-based field-programmable gate array accelerator for revolutionary LCD power management is proposed that allows dynamic modulation of the different zones of the backlight panel . This hardware accelerator-based system is capable of processing a high-definition video stream in real-time and uses less than 50 % of the power that a normal LCD display system consumes , with minimum overhead . We also compare our proposed approach with other state-of-the-art power-aware methods and show numerous advantages using our data-driven strategy .
Abstract The paper discusses the development of a hardware accelerator environment for ASIC design verification . A reprogrammable gate array serves as a breadboard for the ASIC design .
We evaluate the execution time of the whole filtering process . Than we add a hardware accelerator part . This latter is implemented using fast parallel architecture .
After that , we give a possible classification of image compression techniques , from the architecture requirements point of view , with a focus on a class of techniques for which the improvement is proposed . Finally , we introduce the proposed hardware accelerator solution , analyze the expected performance improvement , and discuss the implementational complexity . In conclusion , we present our plans for future work on the subject.<<ETX > >
In this work , FPGA based pipelined architecture for blind and robust image watermarking algorithm has been presented using Wavelet Co-efficients Quantization . The architecture is designed using new hardware accelerator tool of Xilinx System Generator . The goal of this work is to utilize the option of System Generator for the designing of signal processing algorithm on FPGA and to optimize the design in terms of latency and hardware resources .
Fractal dynamics can be used as an irregularity measure of signals and our work shows that it is a key discriminant for classification of falls from other activities of life . We design , implement and evaluate a hardware feature accelerator for computation of fractal features through multi-level wavelet transform on a reconfigurable embedded System on Chip , Zynq device for evaluating wearable accelerometer sensors . The proposed FDS utilises a hardware/software co-design approach with hardware accelerator for fractal features and software implementation of Linear Discriminant Analysis on an embedded ARM core for high accuracy and energy efficiency .
The main challenges Level-1 track finding faces are the large data throughput from the detector at a collision rate of 40 MHz and a 4 microsecond latency budget to reconstruct charged particle tracks with sufficiently low transverse momentum to be used in the Level-1 trigger decision . Dedicated all-FPGA hardware systems with time-multiplexed architecture have been developed for track finding to address these challenges . The algorithm and performance of the pattern recognition and particle trajectory determination are discussed .
The paper presents a multichannel digital processor based on a configurable computing ( FPGA ) device for acquisition and programmable data processing in multi-detector systems . Main features of the processor are reconfigurability , linearity , low noise and processing data rate through hardware and firmware architecture solutions that also allow the system to operate in presence of electromagnetic noise , while at the same time minimizing its own radiated emissions .
There are well known cases where FPGAs provide high performance within a modest power budget , yet unlike conventional desktop solutions , they are oftentimes associated with long wait times before a device configuration is generated . Such long wait times constitute a bottleneck limiting the number of compilation runs performed in a day ; thus limiting to FPGA adaptation in modern computing platforms . This work presents an FPGA development paradigm that exploits logic variance and hierarchy as a means to increase FPGA productivity .
In particular , the generation of both Gaussian ( low-pass ) and Laplacian ( band-pass ) pyramids can occur concurrently in real time using images from a video camera , assuming the standard frame rate of 30 images per second . Results are presented to illustrate the efficacy of reconfigurable FPGA-based machines to image processing applications.<<ETX > >
A FPGA hardware core has been designed for real-time network simulations with up to 400 physiologically realistic , conductance-based neurons of the Hodgkin-Huxley type . A PC-FPGA interface allows easy parameter adjustment and on-line display of basic synchronization measures like field potentials , spike times or color-coded voltages of the complete array .
Consequently , it becomes possible to design an FPGA accelerator that performs streaming memory accesses and parallel wavefront expansion on all wires in two connected sets . To test and evaluate our FPGA-accelerated PathFinder-based router , we implement it on DE1-SoC , Intel 's ARM+FPGA platform and run a set of benchmarks from the VTR suite . The results show that our implementation produces deterministic and good quality output .
A Reconfigurable Processor for Forward Error Correction.- FPGA-Accelerated Deletion-Tolerant Coding for Reliable Distributed Storage.- LIRAC : Using Live Range Information to Optimize Memory Access.- Optimized Register Renaming Scheme for Stack-Based x86 Operations.- A Customized Cross-Bar for Data-Shuffling in Domain-Specific SIMD Processors.- Customized Placement for High Performance Embedded Processor Caches.- A Multiprocessor Cache for Massively Parallel SoC Architectures.- Improving Resource Discovery in the Arigatoni Overlay Network.- An Effective Multi-hop Broadcast in Vehicular Ad-Hoc Network.- Functional Knowledge Exchange Within an Intelligent Distributed System.- Architecture for Collaborative Business Items.- Autonomic Management Architecture for Flexible Grid Services Deployment Based on Policies.- Variations and Evaluations of an Adaptive Accrual Failure Detector to Enable Self-healing Properties in Distributed Systems.- Self-organizing Software Components in Distributed Systems.- Toward Self-adaptive Embedded Systems : Multi-objective Hardware Evolution.- Measurement and Control of Self-organised Behaviour in Robot Swarms.- Autonomous Learning of Load and Traffic Patterns to Improve Cluster Utilization.- Parametric Architecture for Function Calculation Improvement.- Design Space Exploration of Media Processors : A Generic VLIW Architecture and a Parameterized Scheduler.- Modeling of Interconnection Networks in Massively Parallel Processor Architectures.- Invited Talk : Expanding Software Product Families :
DNNs rely on a growing variety of matrix multiply operations ( i.e. , dense to sparse , FP32 to N-bit ) . We propose an OpenCL-based matrix multiply design template , which enables automated design exploration to generate optimized FPGA matrix accelerators for DNN applications . Given the desired matrix operations ( e.g. , sparsity , data types ) , our template rapidly produces performance and area estimates for a variety of design variants and/or FPGA platforms .
The receiver is based on NovAtel ’s new FPGA based precise positioning receiver , the Euro-L5 . The receiver FPGA and software is configured to track the open service BOC(1,1 ) signal that will be transmitted on the Galileo L1 frequency . To reduce hardware design costs for this pre-production prototype development , the design was demonstrated at the L5/E5a frequency .
In this paper we present an FPGA-based daughtercard designed for TIs C6000family of DSP starter kits ( DSKs ) . The hardware , initially designed for a course project , provides a platform for studying heterogeneous systems and hardware software co-design .
Energy Efficient Hardware Accelerators for Packet Classification and String Matching High-speed hardware implementations of Elliptic Curve Cryptography: A survey Synthesis of a Parallel Smith-Waterman Sequence Alignment Kernel into FPGA Hardware Minnow: Lightweight Offload Engines for Worklist Management and Worklist-Directed Prefetching Worklist-Directed Prefetching Applying TMR in Hardware Accelerators Generated by High-Level Synthesis Design Flow for Mitigating Multiple Bit Upsets in SRAM-Based FPGAs A defect-tolerant accelerator for emerging high-performance applications Dynamically utilizing computation accelerators for extensible processors in a software approach Accelerating subset sum and lattice based public-key cryptosystems with multi-core CPUs and GPUs Automatic generation and testing of application specific hardware accelerators on a new reconfigurable OpenSPARC platform A Unified Hardware/Software Monitoring Method for Reconfigurable Computing Architectures Using PAPI A dynamically adaptable bus architecture for trading-off among performance, consumption and dependability in Cyber-Physical Systems Execution modeling in self-aware FPGA-based architectures for efficient resource management Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images Design and implementation of open-source SATA III core for Stratix V FPGAs A Scalable Dataflow Implementation of Curran's Approximation Algorithm Leveraging FPGAs for Accelerating Short Read Alignment Efficient on-line testing of FPGAs with provable diagnosabilities Architecture and CAD for Deep-Submicron FPGAS High-Speed Serial Protocol Multi-Link and Multi-Stage for FPGAs Implementation architecture of signal processing in pulse Doppler radar system based on FPGA Multi-level logic synthesis for Concurrent Logic CLi6000 devices Theory and Algorithm for SPFD-Based Global Rewiring Design of a novel Quantum-dot Cellular Automata Field Programmable Gate Array Implementing neural network in custom computers SEU susceptibility analysis of a feedforward neural network implemented in a SRAM-based FPGA LOCALIS: Locally‐adaptive Line Simplification for GPU‐based Geographic Vector Data Visualization Enhancing the Programmability and Performance Portability of GPU Tensor Operations Multi-objective autotuning of MobileNets across the full software/hardware stack Single-Loop Digital Control of High-Power 400-Hz Ground Power Unit for Airplanes Evaluation and tuning of the Level 3 CUBLAS for graphics processors Grabfast: A CUDA based GPU accelerated fast short sequence alignment algorithm Object Storage for Deep Learning Frameworks Exploiting graphics processing units for computational biology and bioinformatics Improving Efficiency in Large-Scale Decentralized Distributed Training Development of algorithms and architectures for driving assistance in adverse weather conditions using FPGAs. (Développement d'algorithmes et d'architectures pour l'aide à la conduite dans des conditions météorologiques défavorables en utilisant les FPGA) FDTD Method in Computational Electromagnet ics Engineering FPGA-based accelerator platform for big data matrix processing A Saliency-Driven LCD Power Management System Reprogrammable gate arrays for hardware accelerated IC design verification HW/SW Design-Based Implementation of Vector Median Rational Hybrid Filter Architectural requirements for multimedia image compression, and a solution based on VLSI hardware accelerator FPGA based efficient architecture for image watermarking using Wavelet Co-efficients Quantization Hardware/Software Co-Design of Fractal Features Based Fall Detection System Level-1 Track Finding with an all-FPGA system at CMS for the HL-LHC Digital configurable processor for acquisition and elaboration of data from detector arrays A design assembly framework for FPGA back-end acceleration Finding lines and building pyramids with SPLASH 2 Real-Time Simulations of Synchronization in a Conductance-Based Neuronal Network with a Digital FPGA Hardware-Core Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform Architecture of Computing Systems - ARCS 2007, 20th International Conference, Zurich, Switzerland, March 12-15, 2007, Proceedings Customizable FPGA OpenCL matrix multiply design template for deep neural networks Galileo BOC(1,1) Prototype Receiver Development An FPGA-based daughtercard for TI's c6000 family of DSKs
f16a2004cd89a4774693ae5cf81e90da622b3ce2 c5b6039806a2bfd535716e6840b7a4f9ffdc3807 772961ff2cc7919653eea9ca70f1cb6c5d14c191 c933f69c4afd584924c204e11701b32cf037ffb2 bee8b4ecf8e41ef3c4931a82e0563d5b14ff9c00 a7d7824ca7885c3285c4701e12249fe30a2977b0 32c3d778d8cce464b3ad3de277666295f3a0b02a c0da1bc2f1f611f871345e1c08bd4bad07ce9c6a 19b9e2182335edc1c0fa32b13915053b85da8e20 9e022ee7f16f35341d7326d91d366c1e7d3608b1 c4dbdcf20c22339410c4746d816d7751f820ad32 bf3488c09e4a9bb0f7b983f8e6c4176202a01914 dc02696624848e7437d032e1963a5dd62a92ef13 952a9051c8b0063777b14f2e745ad901dcb4419d 6d31a1807b05d877085dbf2467ad7ccccbe52012 10f37802f8d77bd903a907671c1646f854748210 5b0dac47c5c7234dfc9063242099a38586ef8f2a 216d66c9f6f29da4bd02ba45521131249412a593 ca349b13690556403fc46ac19462a62a4c7f50f0 d39f916405acfae84d5509c2f18f816180422094 93d2d7800e9f462cfd40d6c5a7579257d707b984 a80d9f7c0edf04fede62e1b83a5d1ee173ffeee4 ee1a27584d3991771d009c161adf2ae2217dfc77 8807dc1444d7257699122fae242b137857bb0a21 37b6b4f47b2e278541292ff55107d417fbc3deca 00187bf0de9db4e4af11a47c5a0a058be0faf2da ff29fed2fa3e2ad3eae321b6de65d7edfc217270 6c1329841dbf00699820c441d2d5cc0a739ed19e 7ccd5a854003810480e6a5a224f55120213febf0 8c4647b0321da5f7808ba8e0f03151482d0fc934 38a562b42255245937a6269af9937405fca96e66 0d5cfacec03ac93f6cff5985b70b07e45438841f 15aa39678a8b89aa670edf23cf155980c52bc24b a5261dee9ea3d6c18d30c8a0170e9ee4e349d2c7 bc40ea6a543beb7ab6077c0f8745728c830e70f4 be205cd7c5db451af3c31fc449add036a24f92ef 046ff5a7d05177a2e63b7e78f2b558682153b526 c5e71cd2fac690b27233e854700ed9c2e9b42c5b a788c26e9b27fbcd23e52d1cdf3099bfbf18c245 6fbe4815019f3ad085ad080a3bc93688620eb37e ec42e0d068e1fb9de6a969bd8cfcee4f25782734 eea850a826ab266f1d0980f65a1a128bc01a725e 3b1308d1bbb21a13fe6a924f75323ed2abc9b98f 5f100923bc5fd257ff472e5de0eff29d844542df 7124e137e2d57e39d21c727bc6ffb725b52d3879 e2767a7d48876f80657f31224dc8afc86cf436c3 917955e8f2845f00286b274151ed7d1d6f7dc022 4bb5c70dd96f772094805ffcb4955a245d56ecb9 56a479668abb4802fddeda84bcf4333dd3af3abb dccd1c8574d3839abdb394acce17eeac7296a5c6 21d934b973b90bf55f10c1ce5148c5c6db88c184 aa2bcf1b207ddc27747eb0d98366ec2ddacf0400 37cff6f713e8b755a25a0c61b456c5036b0631d7 58b700d715122d9449058e71f1d8c4f22dce5249 44d55e229cabf60f9d540b593206512202abe02f
["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Geology","Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science","Medicine"] ["Computer Science"] ["Engineering","Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science","Engineering"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science","Medicine"] ["Computer Science","Mathematics"] ["Computer Science","Engineering"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Engineering","Medicine","Computer Science"] ["Physics"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"] ["Computer Science"]
2010 2007 2009 2018 2017 2017 2012 2009 2018 2011 2018 2014 2015 2020 2018 2016 2017 2017 2004 1999 2019 2019 1993 2001 2012 1998 2017 2020 2019 2018 2010 2008 2012 2018 2010 2020 2011 2015 2016 1990 2010 1994 2014 2020 2018 2009 2014 1994 2012 2019 2007 2017 2004 2005
ASPLOS ARC ISCA CODES+ISSS ReCoSoC FPL ReCoSoC ARC FPT IPDPS Workshops DAC FPL SMC LATS Euro-Par ReQuEST@ASPLOS IPDPS HiPC DIDL@Middleware ICASSP HICSS (1) ICANN (1) FPGA FPT MSE
https://api.semanticscholar.org/f16a2004cd89a4774693ae5cf81e90da622b3ce2 https://api.semanticscholar.org/c5b6039806a2bfd535716e6840b7a4f9ffdc3807 https://api.semanticscholar.org/772961ff2cc7919653eea9ca70f1cb6c5d14c191 https://api.semanticscholar.org/c933f69c4afd584924c204e11701b32cf037ffb2 https://api.semanticscholar.org/bee8b4ecf8e41ef3c4931a82e0563d5b14ff9c00 https://api.semanticscholar.org/a7d7824ca7885c3285c4701e12249fe30a2977b0 https://api.semanticscholar.org/32c3d778d8cce464b3ad3de277666295f3a0b02a https://api.semanticscholar.org/c0da1bc2f1f611f871345e1c08bd4bad07ce9c6a https://api.semanticscholar.org/19b9e2182335edc1c0fa32b13915053b85da8e20 https://api.semanticscholar.org/9e022ee7f16f35341d7326d91d366c1e7d3608b1 https://api.semanticscholar.org/c4dbdcf20c22339410c4746d816d7751f820ad32 https://api.semanticscholar.org/bf3488c09e4a9bb0f7b983f8e6c4176202a01914 https://api.semanticscholar.org/dc02696624848e7437d032e1963a5dd62a92ef13 https://api.semanticscholar.org/952a9051c8b0063777b14f2e745ad901dcb4419d https://api.semanticscholar.org/6d31a1807b05d877085dbf2467ad7ccccbe52012 https://api.semanticscholar.org/10f37802f8d77bd903a907671c1646f854748210 https://api.semanticscholar.org/5b0dac47c5c7234dfc9063242099a38586ef8f2a https://api.semanticscholar.org/216d66c9f6f29da4bd02ba45521131249412a593 https://api.semanticscholar.org/ca349b13690556403fc46ac19462a62a4c7f50f0 https://api.semanticscholar.org/d39f916405acfae84d5509c2f18f816180422094 https://api.semanticscholar.org/93d2d7800e9f462cfd40d6c5a7579257d707b984 https://api.semanticscholar.org/a80d9f7c0edf04fede62e1b83a5d1ee173ffeee4 https://api.semanticscholar.org/ee1a27584d3991771d009c161adf2ae2217dfc77 https://api.semanticscholar.org/8807dc1444d7257699122fae242b137857bb0a21 https://api.semanticscholar.org/37b6b4f47b2e278541292ff55107d417fbc3deca https://api.semanticscholar.org/00187bf0de9db4e4af11a47c5a0a058be0faf2da https://api.semanticscholar.org/ff29fed2fa3e2ad3eae321b6de65d7edfc217270 https://api.semanticscholar.org/6c1329841dbf00699820c441d2d5cc0a739ed19e https://api.semanticscholar.org/7ccd5a854003810480e6a5a224f55120213febf0 https://api.semanticscholar.org/8c4647b0321da5f7808ba8e0f03151482d0fc934 https://api.semanticscholar.org/38a562b42255245937a6269af9937405fca96e66 https://api.semanticscholar.org/0d5cfacec03ac93f6cff5985b70b07e45438841f https://api.semanticscholar.org/15aa39678a8b89aa670edf23cf155980c52bc24b https://api.semanticscholar.org/a5261dee9ea3d6c18d30c8a0170e9ee4e349d2c7 https://api.semanticscholar.org/bc40ea6a543beb7ab6077c0f8745728c830e70f4 https://api.semanticscholar.org/be205cd7c5db451af3c31fc449add036a24f92ef https://api.semanticscholar.org/046ff5a7d05177a2e63b7e78f2b558682153b526 https://api.semanticscholar.org/c5e71cd2fac690b27233e854700ed9c2e9b42c5b https://api.semanticscholar.org/a788c26e9b27fbcd23e52d1cdf3099bfbf18c245 https://api.semanticscholar.org/6fbe4815019f3ad085ad080a3bc93688620eb37e https://api.semanticscholar.org/ec42e0d068e1fb9de6a969bd8cfcee4f25782734 https://api.semanticscholar.org/eea850a826ab266f1d0980f65a1a128bc01a725e https://api.semanticscholar.org/3b1308d1bbb21a13fe6a924f75323ed2abc9b98f https://api.semanticscholar.org/5f100923bc5fd257ff472e5de0eff29d844542df https://api.semanticscholar.org/7124e137e2d57e39d21c727bc6ffb725b52d3879 https://api.semanticscholar.org/e2767a7d48876f80657f31224dc8afc86cf436c3 https://api.semanticscholar.org/917955e8f2845f00286b274151ed7d1d6f7dc022 https://api.semanticscholar.org/4bb5c70dd96f772094805ffcb4955a245d56ecb9 https://api.semanticscholar.org/56a479668abb4802fddeda84bcf4333dd3af3abb https://api.semanticscholar.org/dccd1c8574d3839abdb394acce17eeac7296a5c6 https://api.semanticscholar.org/21d934b973b90bf55f10c1ce5148c5c6db88c184 https://api.semanticscholar.org/aa2bcf1b207ddc27747eb0d98366ec2ddacf0400 https://api.semanticscholar.org/37cff6f713e8b755a25a0c61b456c5036b0631d7 https://api.semanticscholar.org/58b700d715122d9449058e71f1d8c4f22dce5249 https://api.semanticscholar.org/44d55e229cabf60f9d540b593206512202abe02f