After establishing of various possibilities of abstraction in HDLs (on values, time, and structure) many years ago, SystemVerilog as a combined HDVL offers a new approach to support also abstraction on ports. This interface concept extends the feasibilities for encapsulation when designing, connecting, and verifying the numerous interfaces in modern SoC designs. This can be done on an abstract, non-synthesizable level but also on RT level. The introduction of interfaces into SystemVerilog allows a more effective methodology for the implementation and verification of designs. First, an interface can be designed independently on the subblocks, which should be connected later. It contains not only the protocols for the transfers but also assertions derived from the specification to check all these transfers. Then, BFMs can be implemented using the interfaces and can be verified against the interface assertions. After implementation of the RTL code, this RTL code can be verified by using the BFMs and the assertions. Later, sub-designs are connected hierarchically whereby the assertion and the BFMs are used as the lowest level of the testbench hierarchy. SystemVerilog has a lot of benefits against traditional HDLs as VHDL or Verilog and also against HVLs, as it combines many well-known concepts in a pragmatic way.