This paper presents carry-lookahead adder (CLA) based design of the contemporary inexact-speculative adder (ISA) which is fine grain pipelined to include few logic gates along its critical path and thereby, enhancing the frequency of operation. Additionally, various stages of the proposed ISA architecture has been clock gated to reduce the power consumed by this design. Functional verification and hardware implementation for various configurations of the suggested ISA is carried out on field-programmable gate-array (FPGA) platform. It could operate at a maximum clock frequency of 324 MHz which is 52% better then the conventional ISA. Thereafter, the synthesis and post-layout simulation of 32-bit proposed ISA is carried out using 90 nm complementary metal-oxide semiconductors (CMOS) technology node for power and area analysis. Our design occupied 5.11 mm2 of chip area and consumed 9.68 mW of total power at 400 MHz clock frequency. The proposed ISA burns 52.8% lesser power than the state-of-the-art work.