	.file	"212642929.c"
	.intel_syntax noprefix
	.text
	.type	fsum, @function
fsum:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L2
.L3:
	mov	eax, DWORD PTR -4[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	rcx, QWORD PTR [rax]
	mov	eax, DWORD PTR -4[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	rdx, QWORD PTR [rax]
	mov	eax, DWORD PTR -4[rbp]
	lea	rsi, 0[0+rax*8]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rsi
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	eax, DWORD PTR -4[rbp]
	add	eax, 1
	mov	eax, eax
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	rcx, QWORD PTR [rax]
	mov	eax, DWORD PTR -4[rbp]
	add	eax, 1
	mov	eax, eax
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	rdx, QWORD PTR [rax]
	mov	eax, DWORD PTR -4[rbp]
	add	eax, 1
	mov	eax, eax
	lea	rsi, 0[0+rax*8]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rsi
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	add	DWORD PTR -4[rbp], 2
.L2:
	cmp	DWORD PTR -4[rbp], 9
	jbe	.L3
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	fsum, .-fsum
	.type	fdifference, @function
fdifference:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L5
.L6:
	mov	eax, DWORD PTR -4[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	rdx, QWORD PTR [rax]
	mov	eax, DWORD PTR -4[rbp]
	lea	rcx, 0[0+rax*8]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rcx
	mov	rcx, QWORD PTR [rax]
	mov	eax, DWORD PTR -4[rbp]
	lea	rsi, 0[0+rax*8]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rsi
	sub	rdx, rcx
	mov	QWORD PTR [rax], rdx
	add	DWORD PTR -4[rbp], 1
.L5:
	cmp	DWORD PTR -4[rbp], 9
	jbe	.L6
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	fdifference, .-fdifference
	.type	fscalar_product, @function
fscalar_product:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	QWORD PTR -40[rbp], rdx
	mov	DWORD PTR -4[rbp], 0
	jmp	.L8
.L9:
	mov	eax, DWORD PTR -4[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	mov	edx, DWORD PTR -4[rbp]
	lea	rcx, 0[0+rdx*8]
	mov	rdx, QWORD PTR -24[rbp]
	add	rdx, rcx
	imul	rax, QWORD PTR -40[rbp]
	mov	QWORD PTR [rdx], rax
	add	DWORD PTR -4[rbp], 1
.L8:
	cmp	DWORD PTR -4[rbp], 9
	jbe	.L9
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	fscalar_product, .-fscalar_product
	.type	fproduct, @function
fproduct:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	QWORD PTR -24[rbp], rdx
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rsi, rdx
	imul	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rsi
	add	rax, rax
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rcx
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rsi, rdx
	imul	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rsi
	add	rax, rax
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 72
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rcx
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 80
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 88
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rsi, rdx
	imul	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rsi
	add	rax, rax
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 96
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 104
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rcx
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 112
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 120
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rsi, rdx
	imul	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rsi
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, -128
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 136
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 144
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	fproduct, .-fproduct
	.type	freduce_degree, @function
freduce_degree:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 144
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 144
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 144
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 136
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 136
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 136
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, -128
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, -128
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, -128
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 120
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 120
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 120
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 112
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 112
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 112
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 104
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 104
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 104
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 96
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 96
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 96
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 88
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 88
	mov	rax, QWORD PTR [rax]
	lea	rcx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 88
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 80
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	add	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 80
	mov	rax, QWORD PTR [rax]
	add	rax, rax
	add	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 80
	mov	rax, QWORD PTR [rax]
	add	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR [rax], rdx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	freduce_degree, .-freduce_degree
	.type	div_by_2_26, @function
div_by_2_26:
.LFB5:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	shr	rax, 32
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	sar	eax, 31
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -8[rbp]
	shr	eax, 6
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	sar	rax, 26
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	div_by_2_26, .-div_by_2_26
	.type	div_by_2_25, @function
div_by_2_25:
.LFB6:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	rax, QWORD PTR -24[rbp]
	shr	rax, 32
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	sar	eax, 31
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -8[rbp]
	shr	eax, 7
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	sar	rax, 25
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	div_by_2_25, .-div_by_2_25
	.type	div_s32_by_2_25, @function
div_s32_by_2_25:
.LFB7:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	sar	eax, 31
	shr	eax, 7
	mov	DWORD PTR -4[rbp], eax
	mov	edx, DWORD PTR -20[rbp]
	mov	eax, DWORD PTR -4[rbp]
	add	eax, edx
	sar	eax, 25
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	div_s32_by_2_25, .-div_s32_by_2_25
	.type	freduce_coefficients, @function
freduce_coefficients:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 40
	mov	QWORD PTR -40[rbp], rdi
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 80
	mov	QWORD PTR [rax], 0
	mov	DWORD PTR -24[rbp], 0
	jmp	.L19
.L20:
	mov	eax, DWORD PTR -24[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	mov	rdi, rax
	call	div_by_2_26
	mov	QWORD PTR -8[rbp], rax
	mov	eax, DWORD PTR -24[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	sal	rax, 26
	mov	rcx, rax
	mov	eax, DWORD PTR -24[rbp]
	lea	rsi, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rsi
	sub	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	eax, DWORD PTR -24[rbp]
	add	eax, 1
	mov	eax, eax
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	mov	rcx, QWORD PTR [rax]
	mov	eax, DWORD PTR -24[rbp]
	add	eax, 1
	mov	eax, eax
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	mov	rdx, QWORD PTR -8[rbp]
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	eax, DWORD PTR -24[rbp]
	add	eax, 1
	mov	eax, eax
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	mov	rdi, rax
	call	div_by_2_25
	mov	QWORD PTR -8[rbp], rax
	mov	eax, DWORD PTR -24[rbp]
	add	eax, 1
	mov	eax, eax
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -8[rbp]
	sal	rax, 25
	mov	rcx, rax
	mov	eax, DWORD PTR -24[rbp]
	add	eax, 1
	mov	eax, eax
	lea	rsi, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rsi
	sub	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	eax, DWORD PTR -24[rbp]
	add	eax, 2
	mov	eax, eax
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	mov	rcx, QWORD PTR [rax]
	mov	eax, DWORD PTR -24[rbp]
	add	eax, 2
	mov	eax, eax
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	mov	rdx, QWORD PTR -8[rbp]
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	add	DWORD PTR -24[rbp], 2
.L19:
	cmp	DWORD PTR -24[rbp], 9
	jbe	.L20
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 80
	mov	rax, QWORD PTR [rax]
	sal	rax, 4
	add	rdx, rax
	mov	rax, QWORD PTR -40[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 80
	mov	rax, QWORD PTR [rax]
	add	rax, rax
	add	rdx, rax
	mov	rax, QWORD PTR -40[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 80
	mov	rax, QWORD PTR [rax]
	add	rdx, rax
	mov	rax, QWORD PTR -40[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 80
	mov	QWORD PTR [rax], 0
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR [rax]
	mov	rdi, rax
	call	div_by_2_26
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR [rax]
	mov	rdx, QWORD PTR -16[rbp]
	mov	rcx, rdx
	sal	rcx, 26
	sub	rax, rcx
	mov	rdx, rax
	mov	rax, QWORD PTR -40[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 8
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 8
	mov	rdx, QWORD PTR -16[rbp]
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	mov	edi, eax
	call	div_s32_by_2_25
	mov	DWORD PTR -20[rbp], eax
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 8
	mov	rdx, QWORD PTR [rax]
	mov	eax, DWORD PTR -20[rbp]
	sal	eax, 25
	movsx	rcx, eax
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 8
	sub	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 16
	mov	rcx, QWORD PTR [rax]
	mov	eax, DWORD PTR -20[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	add	rax, 16
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	freduce_coefficients, .-freduce_coefficients
	.type	fmul, @function
fmul:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 192
	mov	QWORD PTR -168[rbp], rdi
	mov	QWORD PTR -176[rbp], rsi
	mov	QWORD PTR -184[rbp], rdx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rdx, QWORD PTR -184[rbp]
	mov	rcx, QWORD PTR -176[rbp]
	lea	rax, -160[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fproduct
	lea	rax, -160[rbp]
	mov	rdi, rax
	call	freduce_degree
	lea	rax, -160[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	lea	rcx, -160[rbp]
	mov	rax, QWORD PTR -168[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L22
	call	__stack_chk_fail@PLT
.L22:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	fmul, .-fmul
	.type	fsquare_inner, @function
fsquare_inner:
.LFB10:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	sal	rax, 2
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rax
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rsi, rdx
	imul	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdi, [rsi+rax]
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rsi, rdx
	imul	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rsi
	add	rax, rax
	add	rax, rdi
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 72
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rsi, [rcx+rax]
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rcx
	add	rax, rax
	lea	rdx, [rsi+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 80
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 88
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rsi, rdx
	imul	rsi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rdi, rdx
	imul	rdi, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rdi
	add	rax, rax
	add	rax, rsi
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 96
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 104
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	add	rax, rax
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 112
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, [rcx+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 120
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	cdqe
	mov	rcx, rdx
	imul	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rax, rdx
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, -128
	add	rdx, rcx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 136
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 144
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE10:
	.size	fsquare_inner, .-fsquare_inner
	.type	fsquare, @function
fsquare:
.LFB11:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 176
	mov	QWORD PTR -168[rbp], rdi
	mov	QWORD PTR -176[rbp], rsi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rdx, QWORD PTR -176[rbp]
	lea	rax, -160[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare_inner
	lea	rax, -160[rbp]
	mov	rdi, rax
	call	freduce_degree
	lea	rax, -160[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	lea	rcx, -160[rbp]
	mov	rax, QWORD PTR -168[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L25
	call	__stack_chk_fail@PLT
.L25:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE11:
	.size	fsquare, .-fsquare
	.type	fexpand, @function
fexpand:
.LFB12:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 1
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 2
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 3
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	and	eax, 67108863
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 3
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 4
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 5
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 6
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	sar	rax, 2
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	and	edx, 33554431
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 6
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 7
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 8
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 9
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	sar	rax, 3
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 16
	and	edx, 67108863
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 9
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 10
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 11
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 12
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	sar	rax, 5
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	and	edx, 33554431
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 12
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 13
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 14
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 15
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	sar	rax, 6
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 32
	and	edx, 67108863
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 16
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 17
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 18
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 19
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 40
	and	edx, 33554431
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 19
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 20
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 21
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 22
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	sar	rax
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 48
	and	edx, 67108863
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 22
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 23
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 24
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 25
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	sar	rax, 3
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 56
	and	edx, 33554431
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 25
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 26
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 27
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 28
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	sar	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 64
	and	edx, 67108863
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 28
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 29
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 8
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 30
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 16
	or	rdx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 31
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	rax, 24
	or	rax, rdx
	sar	rax, 6
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 72
	and	edx, 67108863
	mov	QWORD PTR [rax], rdx
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE12:
	.size	fexpand, .-fexpand
	.type	fcontract, @function
fcontract:
.LFB13:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -56[rbp], rdi
	mov	QWORD PTR -64[rbp], rsi
	mov	DWORD PTR -36[rbp], 0
	jmp	.L28
.L33:
	mov	DWORD PTR -40[rbp], 0
	jmp	.L29
.L32:
	mov	eax, DWORD PTR -40[rbp]
	and	eax, 1
	test	eax, eax
	je	.L30
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	sar	eax, 31
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	and	eax, DWORD PTR -8[rbp]
	sar	eax, 25
	neg	eax
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	sal	eax, 25
	lea	ecx, [rdx+rax]
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rdx, rax
	movsx	rax, ecx
	mov	QWORD PTR [rdx], rax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	add	rax, 1
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	sub	eax, DWORD PTR -4[rbp]
	mov	edx, DWORD PTR -40[rbp]
	movsx	rdx, edx
	add	rdx, 1
	lea	rcx, 0[0+rdx*8]
	mov	rdx, QWORD PTR -64[rbp]
	add	rdx, rcx
	cdqe
	mov	QWORD PTR [rdx], rax
	jmp	.L31
.L30:
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	sar	eax, 31
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	and	eax, DWORD PTR -16[rbp]
	sar	eax, 26
	neg	eax
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	mov	edx, eax
	mov	eax, DWORD PTR -12[rbp]
	sal	eax, 26
	lea	ecx, [rdx+rax]
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rdx, rax
	movsx	rax, ecx
	mov	QWORD PTR [rdx], rax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	add	rax, 1
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	sub	eax, DWORD PTR -12[rbp]
	mov	edx, DWORD PTR -40[rbp]
	movsx	rdx, edx
	add	rdx, 1
	lea	rcx, 0[0+rdx*8]
	mov	rdx, QWORD PTR -64[rbp]
	add	rdx, rcx
	cdqe
	mov	QWORD PTR [rdx], rax
.L31:
	add	DWORD PTR -40[rbp], 1
.L29:
	cmp	DWORD PTR -40[rbp], 8
	jle	.L32
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	sar	eax, 31
	mov	DWORD PTR -24[rbp], eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	and	eax, DWORD PTR -24[rbp]
	sar	eax, 25
	neg	eax
	mov	DWORD PTR -20[rbp], eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	mov	edx, eax
	mov	eax, DWORD PTR -20[rbp]
	sal	eax, 25
	lea	ecx, [rdx+rax]
	mov	rax, QWORD PTR -64[rbp]
	lea	rdx, 72[rax]
	movsx	rax, ecx
	mov	QWORD PTR [rdx], rax
	mov	rax, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR [rax]
	mov	edx, eax
	mov	eax, DWORD PTR -20[rbp]
	imul	eax, eax, -19
	add	eax, edx
	movsx	rdx, eax
	mov	rax, QWORD PTR -64[rbp]
	mov	QWORD PTR [rax], rdx
	add	DWORD PTR -36[rbp], 1
.L28:
	cmp	DWORD PTR -36[rbp], 1
	jle	.L33
	mov	rax, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR [rax]
	sar	eax, 31
	mov	DWORD PTR -32[rbp], eax
	mov	rax, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR [rax]
	and	eax, DWORD PTR -32[rbp]
	sar	eax, 26
	neg	eax
	mov	DWORD PTR -28[rbp], eax
	mov	rax, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR [rax]
	mov	edx, eax
	mov	eax, DWORD PTR -28[rbp]
	sal	eax, 26
	add	eax, edx
	movsx	rdx, eax
	mov	rax, QWORD PTR -64[rbp]
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	sub	eax, DWORD PTR -28[rbp]
	mov	rdx, QWORD PTR -64[rbp]
	add	rdx, 8
	cdqe
	mov	QWORD PTR [rdx], rax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 8
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 8
	sal	rdx, 2
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 16
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 16
	sal	rdx, 3
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 24
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 24
	sal	rdx, 5
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 32
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 32
	sal	rdx, 6
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 48
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 48
	add	rdx, rdx
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 56
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 56
	sal	rdx, 3
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 64
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 64
	sal	rdx, 4
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	sal	rdx, 6
	mov	QWORD PTR [rax], rdx
	mov	rax, QWORD PTR -56[rbp]
	mov	BYTE PTR [rax], 0
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 16
	mov	BYTE PTR [rax], 0
	mov	rax, QWORD PTR -56[rbp]
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR [rax]
	or	eax, edx
	mov	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 1
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 2
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 3
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 3
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 3
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 4
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 5
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 6
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 6
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 6
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 7
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 8
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 9
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 9
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 9
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 10
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 11
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 12
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 12
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 12
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 13
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 14
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 15
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 16
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 16
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 17
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 18
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 40
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 19
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 19
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 19
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 20
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 21
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 48
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 22
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 22
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 22
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 23
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 24
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 56
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 25
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 25
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 25
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 26
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 27
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 64
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 28
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 28
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	or	edx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 28
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	sar	rax, 8
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 29
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	sar	rax, 16
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 30
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -64[rbp]
	add	rax, 72
	mov	rax, QWORD PTR [rax]
	sar	rax, 24
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, 31
	mov	BYTE PTR [rax], dl
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE13:
	.size	fcontract, .-fcontract
	.type	fmonty, @function
fmonty:
.LFB14:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 1360
	mov	QWORD PTR -1288[rbp], rdi
	mov	QWORD PTR -1296[rbp], rsi
	mov	QWORD PTR -1304[rbp], rdx
	mov	QWORD PTR -1312[rbp], rcx
	mov	QWORD PTR -1320[rbp], r8
	mov	QWORD PTR -1328[rbp], r9
	mov	rax, QWORD PTR 16[rbp]
	mov	QWORD PTR -1336[rbp], rax
	mov	rax, QWORD PTR 24[rbp]
	mov	QWORD PTR -1344[rbp], rax
	mov	rax, QWORD PTR 32[rbp]
	mov	QWORD PTR -1352[rbp], rax
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rcx, QWORD PTR -1320[rbp]
	lea	rax, -1280[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	mov	rdx, QWORD PTR -1328[rbp]
	mov	rax, QWORD PTR -1320[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsum
	lea	rdx, -1280[rbp]
	mov	rax, QWORD PTR -1328[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fdifference
	mov	rcx, QWORD PTR -1336[rbp]
	lea	rax, -1200[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	mov	rdx, QWORD PTR -1344[rbp]
	mov	rax, QWORD PTR -1336[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsum
	lea	rdx, -1200[rbp]
	mov	rax, QWORD PTR -1344[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fdifference
	mov	rdx, QWORD PTR -1328[rbp]
	mov	rcx, QWORD PTR -1336[rbp]
	lea	rax, -640[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fproduct
	mov	rdx, QWORD PTR -1344[rbp]
	mov	rcx, QWORD PTR -1320[rbp]
	lea	rax, -480[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fproduct
	lea	rax, -640[rbp]
	mov	rdi, rax
	call	freduce_degree
	lea	rax, -640[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	lea	rax, -480[rbp]
	mov	rdi, rax
	call	freduce_degree
	lea	rax, -480[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	mov	rax, QWORD PTR -640[rbp]
	mov	rdx, QWORD PTR -632[rbp]
	mov	QWORD PTR -1200[rbp], rax
	mov	QWORD PTR -1192[rbp], rdx
	mov	rax, QWORD PTR -624[rbp]
	mov	rdx, QWORD PTR -616[rbp]
	mov	QWORD PTR -1184[rbp], rax
	mov	QWORD PTR -1176[rbp], rdx
	mov	rax, QWORD PTR -608[rbp]
	mov	rdx, QWORD PTR -600[rbp]
	mov	QWORD PTR -1168[rbp], rax
	mov	QWORD PTR -1160[rbp], rdx
	mov	rax, QWORD PTR -592[rbp]
	mov	rdx, QWORD PTR -584[rbp]
	mov	QWORD PTR -1152[rbp], rax
	mov	QWORD PTR -1144[rbp], rdx
	mov	rax, QWORD PTR -576[rbp]
	mov	rdx, QWORD PTR -568[rbp]
	mov	QWORD PTR -1136[rbp], rax
	mov	QWORD PTR -1128[rbp], rdx
	lea	rdx, -480[rbp]
	lea	rax, -640[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsum
	lea	rdx, -1200[rbp]
	lea	rax, -480[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fdifference
	lea	rdx, -640[rbp]
	lea	rax, -160[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -480[rbp]
	lea	rax, -320[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	rdx, QWORD PTR -1352[rbp]
	lea	rcx, -320[rbp]
	lea	rax, -480[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fproduct
	lea	rax, -480[rbp]
	mov	rdi, rax
	call	freduce_degree
	lea	rax, -480[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	lea	rcx, -160[rbp]
	mov	rax, QWORD PTR -1304[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	lea	rcx, -480[rbp]
	mov	rax, QWORD PTR -1312[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	mov	rdx, QWORD PTR -1320[rbp]
	lea	rax, -960[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	rdx, QWORD PTR -1328[rbp]
	lea	rax, -800[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -800[rbp]
	lea	rcx, -960[rbp]
	mov	rax, QWORD PTR -1288[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fproduct
	mov	rax, QWORD PTR -1288[rbp]
	mov	rdi, rax
	call	freduce_degree
	mov	rax, QWORD PTR -1288[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	lea	rdx, -960[rbp]
	lea	rax, -800[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fdifference
	lea	rax, -1120[rbp]
	add	rax, 80
	mov	edx, 72
	mov	esi, 0
	mov	rdi, rax
	call	memset@PLT
	lea	rcx, -800[rbp]
	lea	rax, -1120[rbp]
	mov	edx, 121665
	mov	rsi, rcx
	mov	rdi, rax
	call	fscalar_product
	lea	rax, -1120[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	lea	rdx, -960[rbp]
	lea	rax, -1120[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsum
	lea	rdx, -1120[rbp]
	lea	rcx, -800[rbp]
	mov	rax, QWORD PTR -1296[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fproduct
	mov	rax, QWORD PTR -1296[rbp]
	mov	rdi, rax
	call	freduce_degree
	mov	rax, QWORD PTR -1296[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE14:
	.size	fmonty, .-fmonty
	.type	swap_conditional, @function
swap_conditional:
.LFB15:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	QWORD PTR -40[rbp], rdx
	mov	rax, QWORD PTR -40[rbp]
	neg	eax
	mov	DWORD PTR -8[rbp], eax
	mov	DWORD PTR -12[rbp], 0
	jmp	.L37
.L38:
	mov	eax, DWORD PTR -12[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	mov	ecx, eax
	mov	eax, DWORD PTR -12[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	xor	eax, ecx
	and	eax, DWORD PTR -8[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	xor	eax, DWORD PTR -4[rbp]
	mov	edx, DWORD PTR -12[rbp]
	lea	rcx, 0[0+rdx*8]
	mov	rdx, QWORD PTR -24[rbp]
	add	rdx, rcx
	cdqe
	mov	QWORD PTR [rdx], rax
	mov	eax, DWORD PTR -12[rbp]
	lea	rdx, 0[0+rax*8]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	xor	eax, DWORD PTR -4[rbp]
	mov	edx, DWORD PTR -12[rbp]
	lea	rcx, 0[0+rdx*8]
	mov	rdx, QWORD PTR -32[rbp]
	add	rdx, rcx
	cdqe
	mov	QWORD PTR [rdx], rax
	add	DWORD PTR -12[rbp], 1
.L37:
	cmp	DWORD PTR -12[rbp], 9
	jbe	.L38
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE15:
	.size	swap_conditional, .-swap_conditional
	.type	cmult, @function
cmult:
.LFB16:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 1408
	mov	QWORD PTR -1384[rbp], rdi
	mov	QWORD PTR -1392[rbp], rsi
	mov	QWORD PTR -1400[rbp], rdx
	mov	QWORD PTR -1408[rbp], rcx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	lea	rdx, -1280[rbp]
	mov	eax, 0
	mov	ecx, 19
	mov	rdi, rdx
	rep stosq
	lea	rdx, -1120[rbp]
	mov	eax, 0
	mov	ecx, 19
	mov	rdi, rdx
	rep stosq
	mov	QWORD PTR -1120[rbp], 1
	lea	rdx, -960[rbp]
	mov	eax, 0
	mov	ecx, 19
	mov	rdi, rdx
	rep stosq
	mov	QWORD PTR -960[rbp], 1
	lea	rdx, -800[rbp]
	mov	eax, 0
	mov	ecx, 19
	mov	rdi, rdx
	rep stosq
	lea	rax, -1280[rbp]
	mov	QWORD PTR -1360[rbp], rax
	lea	rax, -1120[rbp]
	mov	QWORD PTR -1352[rbp], rax
	lea	rax, -960[rbp]
	mov	QWORD PTR -1344[rbp], rax
	lea	rax, -800[rbp]
	mov	QWORD PTR -1336[rbp], rax
	lea	rdx, -640[rbp]
	mov	eax, 0
	mov	ecx, 19
	mov	rdi, rdx
	rep stosq
	lea	rdx, -480[rbp]
	mov	eax, 0
	mov	ecx, 19
	mov	rdi, rdx
	rep stosq
	mov	QWORD PTR -480[rbp], 1
	lea	rdx, -320[rbp]
	mov	eax, 0
	mov	ecx, 19
	mov	rdi, rdx
	rep stosq
	lea	rdx, -160[rbp]
	mov	eax, 0
	mov	ecx, 19
	mov	rdi, rdx
	rep stosq
	mov	QWORD PTR -160[rbp], 1
	lea	rax, -640[rbp]
	mov	QWORD PTR -1328[rbp], rax
	lea	rax, -480[rbp]
	mov	QWORD PTR -1320[rbp], rax
	lea	rax, -320[rbp]
	mov	QWORD PTR -1312[rbp], rax
	lea	rax, -160[rbp]
	mov	QWORD PTR -1304[rbp], rax
	mov	rcx, QWORD PTR -1408[rbp]
	mov	rax, QWORD PTR -1360[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	mov	DWORD PTR -1368[rbp], 0
	jmp	.L40
.L43:
	mov	eax, 31
	sub	eax, DWORD PTR -1368[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -1400[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	mov	BYTE PTR -1369[rbp], al
	mov	DWORD PTR -1364[rbp], 0
	jmp	.L41
.L42:
	movzx	eax, BYTE PTR -1369[rbp]
	shr	al, 7
	movzx	eax, al
	mov	QWORD PTR -1296[rbp], rax
	mov	rdx, QWORD PTR -1296[rbp]
	mov	rcx, QWORD PTR -1360[rbp]
	mov	rax, QWORD PTR -1344[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	swap_conditional
	mov	rdx, QWORD PTR -1296[rbp]
	mov	rcx, QWORD PTR -1352[rbp]
	mov	rax, QWORD PTR -1336[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	swap_conditional
	mov	r8, QWORD PTR -1336[rbp]
	mov	rdi, QWORD PTR -1344[rbp]
	mov	rcx, QWORD PTR -1320[rbp]
	mov	rdx, QWORD PTR -1328[rbp]
	mov	rsi, QWORD PTR -1304[rbp]
	mov	rax, QWORD PTR -1312[rbp]
	sub	rsp, 8
	push	QWORD PTR -1408[rbp]
	push	QWORD PTR -1352[rbp]
	push	QWORD PTR -1360[rbp]
	mov	r9, r8
	mov	r8, rdi
	mov	rdi, rax
	call	fmonty
	add	rsp, 32
	mov	rdx, QWORD PTR -1296[rbp]
	mov	rcx, QWORD PTR -1328[rbp]
	mov	rax, QWORD PTR -1312[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	swap_conditional
	mov	rdx, QWORD PTR -1296[rbp]
	mov	rcx, QWORD PTR -1320[rbp]
	mov	rax, QWORD PTR -1304[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	swap_conditional
	mov	rax, QWORD PTR -1344[rbp]
	mov	QWORD PTR -1288[rbp], rax
	mov	rax, QWORD PTR -1312[rbp]
	mov	QWORD PTR -1344[rbp], rax
	mov	rax, QWORD PTR -1288[rbp]
	mov	QWORD PTR -1312[rbp], rax
	mov	rax, QWORD PTR -1336[rbp]
	mov	QWORD PTR -1288[rbp], rax
	mov	rax, QWORD PTR -1304[rbp]
	mov	QWORD PTR -1336[rbp], rax
	mov	rax, QWORD PTR -1288[rbp]
	mov	QWORD PTR -1304[rbp], rax
	mov	rax, QWORD PTR -1360[rbp]
	mov	QWORD PTR -1288[rbp], rax
	mov	rax, QWORD PTR -1328[rbp]
	mov	QWORD PTR -1360[rbp], rax
	mov	rax, QWORD PTR -1288[rbp]
	mov	QWORD PTR -1328[rbp], rax
	mov	rax, QWORD PTR -1352[rbp]
	mov	QWORD PTR -1288[rbp], rax
	mov	rax, QWORD PTR -1320[rbp]
	mov	QWORD PTR -1352[rbp], rax
	mov	rax, QWORD PTR -1288[rbp]
	mov	QWORD PTR -1320[rbp], rax
	sal	BYTE PTR -1369[rbp]
	add	DWORD PTR -1364[rbp], 1
.L41:
	cmp	DWORD PTR -1364[rbp], 7
	jbe	.L42
	add	DWORD PTR -1368[rbp], 1
.L40:
	cmp	DWORD PTR -1368[rbp], 31
	jbe	.L43
	mov	rcx, QWORD PTR -1344[rbp]
	mov	rax, QWORD PTR -1384[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	mov	rcx, QWORD PTR -1336[rbp]
	mov	rax, QWORD PTR -1392[rbp]
	mov	edx, 80
	mov	rsi, rcx
	mov	rdi, rax
	call	memcpy@PLT
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L44
	call	__stack_chk_fail@PLT
.L44:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE16:
	.size	cmult, .-cmult
	.type	crecip, @function
crecip:
.LFB17:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 848
	mov	QWORD PTR -840[rbp], rdi
	mov	QWORD PTR -848[rbp], rsi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rdx, QWORD PTR -848[rbp]
	lea	rax, -816[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -816[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	rdx, QWORD PTR -848[rbp]
	lea	rcx, -176[rbp]
	lea	rax, -736[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -816[rbp]
	lea	rcx, -736[rbp]
	lea	rax, -656[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -656[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -736[rbp]
	lea	rcx, -176[rbp]
	lea	rax, -576[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -576[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -576[rbp]
	lea	rcx, -176[rbp]
	lea	rax, -496[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -496[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	DWORD PTR -820[rbp], 2
	jmp	.L46
.L47:
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	add	DWORD PTR -820[rbp], 2
.L46:
	cmp	DWORD PTR -820[rbp], 9
	jle	.L47
	lea	rdx, -496[rbp]
	lea	rcx, -96[rbp]
	lea	rax, -416[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -416[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	DWORD PTR -820[rbp], 2
	jmp	.L48
.L49:
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	add	DWORD PTR -820[rbp], 2
.L48:
	cmp	DWORD PTR -820[rbp], 19
	jle	.L49
	lea	rdx, -416[rbp]
	lea	rcx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	DWORD PTR -820[rbp], 2
	jmp	.L50
.L51:
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	add	DWORD PTR -820[rbp], 2
.L50:
	cmp	DWORD PTR -820[rbp], 9
	jle	.L51
	lea	rdx, -496[rbp]
	lea	rcx, -176[rbp]
	lea	rax, -336[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -336[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	DWORD PTR -820[rbp], 2
	jmp	.L52
.L53:
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	add	DWORD PTR -820[rbp], 2
.L52:
	cmp	DWORD PTR -820[rbp], 49
	jle	.L53
	lea	rdx, -336[rbp]
	lea	rcx, -96[rbp]
	lea	rax, -256[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -256[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	DWORD PTR -820[rbp], 2
	jmp	.L54
.L55:
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	add	DWORD PTR -820[rbp], 2
.L54:
	cmp	DWORD PTR -820[rbp], 99
	jle	.L55
	lea	rdx, -256[rbp]
	lea	rcx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	mov	DWORD PTR -820[rbp], 2
	jmp	.L56
.L57:
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	add	DWORD PTR -820[rbp], 2
.L56:
	cmp	DWORD PTR -820[rbp], 49
	jle	.L57
	lea	rdx, -336[rbp]
	lea	rcx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -96[rbp]
	lea	rax, -176[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -176[rbp]
	lea	rax, -96[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fsquare
	lea	rdx, -656[rbp]
	lea	rcx, -96[rbp]
	mov	rax, QWORD PTR -840[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE17:
	.size	crecip, .-crecip
	.globl	curve25519_donna
	.type	curve25519_donna, @function
curve25519_donna:
.LFB18:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 432
	mov	QWORD PTR -408[rbp], rdi
	mov	QWORD PTR -416[rbp], rsi
	mov	QWORD PTR -424[rbp], rdx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	DWORD PTR -388[rbp], 0
	jmp	.L60
.L61:
	mov	eax, DWORD PTR -388[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -416[rbp]
	add	rax, rdx
	movzx	edx, BYTE PTR [rax]
	mov	eax, DWORD PTR -388[rbp]
	cdqe
	mov	BYTE PTR -48[rbp+rax], dl
	add	DWORD PTR -388[rbp], 1
.L60:
	cmp	DWORD PTR -388[rbp], 31
	jle	.L61
	movzx	eax, BYTE PTR -48[rbp]
	and	eax, -8
	mov	BYTE PTR -48[rbp], al
	movzx	eax, BYTE PTR -17[rbp]
	and	eax, 127
	mov	BYTE PTR -17[rbp], al
	movzx	eax, BYTE PTR -17[rbp]
	or	eax, 64
	mov	BYTE PTR -17[rbp], al
	mov	rdx, QWORD PTR -424[rbp]
	lea	rax, -384[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fexpand
	lea	rcx, -384[rbp]
	lea	rdx, -48[rbp]
	lea	rsi, -144[rbp]
	lea	rax, -304[rbp]
	mov	rdi, rax
	call	cmult
	lea	rdx, -144[rbp]
	lea	rax, -224[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	crecip
	lea	rdx, -224[rbp]
	lea	rcx, -304[rbp]
	lea	rax, -144[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	fmul
	lea	rax, -144[rbp]
	mov	rdi, rax
	call	freduce_coefficients
	lea	rdx, -144[rbp]
	mov	rax, QWORD PTR -408[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	fcontract
	mov	eax, 0
	mov	rcx, QWORD PTR -8[rbp]
	sub	rcx, QWORD PTR fs:40
	je	.L63
	call	__stack_chk_fail@PLT
.L63:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE18:
	.size	curve25519_donna, .-curve25519_donna
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"212642929.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fsum, %function
fsum:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #16
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	mov	r3, #0
	str	r3, [fp, #-24]
	b	.L2
.L3:
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-32]
	add	r3, r2, r3
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-36]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	ip, [fp, #-24]
	lsl	ip, ip, #3
	ldr	lr, [fp, #-32]
	add	ip, lr, ip
	adds	r4, r0, r2
	adc	r5, r1, r3
	stm	ip, {r4-r5}
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	lsl	r3, r3, #3
	ldr	r2, [fp, #-32]
	add	r3, r2, r3
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	lsl	r3, r3, #3
	ldr	r2, [fp, #-36]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	ip, [fp, #-24]
	add	ip, ip, #1
	lsl	ip, ip, #3
	ldr	lr, [fp, #-32]
	add	ip, lr, ip
	adds	r6, r0, r2
	adc	r7, r1, r3
	stm	ip, {r6-r7}
	ldr	r3, [fp, #-24]
	add	r3, r3, #2
	str	r3, [fp, #-24]
.L2:
	ldr	r3, [fp, #-24]
	cmp	r3, #9
	bls	.L3
	nop
	nop
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
	.size	fsum, .-fsum
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fdifference, %function
fdifference:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, fp, lr}
	add	fp, sp, #12
	sub	sp, sp, #16
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	mov	r3, #0
	str	r3, [fp, #-16]
	b	.L5
.L6:
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-28]
	add	r3, r2, r3
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	ip, [fp, #-16]
	lsl	ip, ip, #3
	ldr	lr, [fp, #-24]
	add	ip, lr, ip
	subs	r4, r0, r2
	sbc	r5, r1, r3
	stm	ip, {r4-r5}
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
.L5:
	ldr	r3, [fp, #-16]
	cmp	r3, #9
	bls	.L6
	nop
	nop
	sub	sp, fp, #12
	@ sp needed
	pop	{r4, r5, fp, pc}
	.size	fdifference, .-fdifference
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fscalar_product, %function
fscalar_product:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, fp, lr}
	add	fp, sp, #8
	sub	sp, sp, #28
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-36]
	str	r3, [fp, #-32]
	mov	r3, #0
	str	r3, [fp, #-16]
	b	.L8
.L9:
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-28]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-16]
	lsl	r1, r1, #3
	ldr	r0, [fp, #-24]
	add	ip, r0, r1
	ldr	r1, [fp, #-36]
	mul	r0, r3, r1
	ldr	r1, [fp, #-32]
	mul	r1, r2, r1
	add	lr, r0, r1
	ldr	r4, [fp, #-36]
	umull	r0, r1, r4, r2
	add	r3, lr, r1
	mov	r1, r3
	stm	ip, {r0-r1}
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
.L8:
	ldr	r3, [fp, #-16]
	cmp	r3, #9
	bls	.L9
	nop
	nop
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, fp, pc}
	.size	fscalar_product, .-fscalar_product
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fproduct, %function
fproduct:
	@ args = 0, pretend = 0, frame = 736
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #736
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	str	r2, [fp, #-40]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	stm	r3, {r6-r7}
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #8
	adds	r2, r8, r6
	str	r2, [fp, #-52]
	adc	r2, r9, r7
	str	r2, [fp, #-48]
	sub	r2, fp, #52
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	ip, r2, r3
	umull	r2, r3, r4, r0
	add	r1, ip, r3
	mov	r3, r1
	adds	r1, r2, r2
	str	r1, [fp, #-700]
	adc	r3, r3, r3
	str	r3, [fp, #-696]
	sub	r9, fp, #700
	ldmia	r9, {r8-r9}
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-60]
	adc	r3, r9, r7
	str	r3, [fp, #-56]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #16
	sub	r2, fp, #60
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-68]
	adc	r2, r2, r7
	str	r2, [fp, #-64]
	sub	r2, fp, #68
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-76]
	adc	r3, r9, r7
	str	r3, [fp, #-72]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #76
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-84]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-80]
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #24
	sub	r2, fp, #84
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-92]
	adc	r2, r2, r7
	str	r2, [fp, #-88]
	sub	r2, fp, #92
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	str	r6, [fp, #-52]
	str	r7, [fp, #-48]
	mov	r2, r7
	add	r3, r3, r2
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-100]
	adc	r3, r9, r7
	str	r3, [fp, #-96]
	sub	r4, fp, #100
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-708]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-704]
	sub	r3, fp, #708
	ldmia	r3, {r2-r3}
	sub	r1, fp, #52
	ldmia	r1, {r0-r1}
	mov	ip, r0
	adds	ip, ip, r2
	str	ip, [fp, #-108]
	adc	r3, r1, r3
	str	r3, [fp, #-104]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #108
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-116]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-112]
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #32
	sub	r2, fp, #116
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-124]
	adc	r2, r2, r7
	str	r2, [fp, #-120]
	sub	r2, fp, #124
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-132]
	adc	r3, r9, r7
	str	r3, [fp, #-128]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #132
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-140]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-136]
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #140
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-148]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-144]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #148
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-156]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-152]
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #40
	sub	r2, fp, #156
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-164]
	adc	r2, r2, r7
	str	r2, [fp, #-160]
	sub	r2, fp, #164
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-172]
	adc	r3, r9, r7
	str	r3, [fp, #-168]
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #172
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-180]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-176]
	sub	r4, fp, #180
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-716]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-712]
	sub	r9, fp, #716
	ldmia	r9, {r8-r9}
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-188]
	adc	r3, r9, r7
	str	r3, [fp, #-184]
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #188
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-196]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-192]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #196
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-204]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-200]
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #48
	sub	r2, fp, #204
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-212]
	adc	r2, r2, r7
	str	r2, [fp, #-208]
	sub	r2, fp, #212
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-220]
	adc	r3, r9, r7
	str	r3, [fp, #-216]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #220
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-228]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-224]
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #228
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-236]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-232]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #236
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-244]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-240]
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #244
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-252]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-248]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #252
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-260]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-256]
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #56
	sub	r2, fp, #260
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-268]
	adc	r2, r2, r7
	str	r2, [fp, #-264]
	sub	r2, fp, #268
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	str	r6, [fp, #-52]
	str	r7, [fp, #-48]
	mov	r2, r7
	add	r3, r3, r2
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-276]
	adc	r3, r9, r7
	str	r3, [fp, #-272]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #276
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-284]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-280]
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #284
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-292]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-288]
	sub	r4, fp, #292
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-724]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-720]
	sub	r3, fp, #724
	ldmia	r3, {r2-r3}
	sub	r1, fp, #52
	ldmia	r1, {r0-r1}
	mov	ip, r0
	adds	ip, ip, r2
	str	ip, [fp, #-300]
	adc	r3, r1, r3
	str	r3, [fp, #-296]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #300
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-308]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-304]
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #308
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-316]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-312]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #316
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-324]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-320]
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #64
	sub	r2, fp, #324
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-332]
	adc	r2, r2, r7
	str	r2, [fp, #-328]
	sub	r2, fp, #332
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-340]
	adc	r3, r9, r7
	str	r3, [fp, #-336]
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #340
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-348]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-344]
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #348
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-356]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-352]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #356
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-364]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-360]
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #364
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-372]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-368]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #372
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-380]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-376]
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #380
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-388]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-384]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #388
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-396]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-392]
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #72
	sub	r2, fp, #396
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-404]
	adc	r2, r2, r7
	str	r2, [fp, #-400]
	sub	r2, fp, #404
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-412]
	adc	r3, r9, r7
	str	r3, [fp, #-408]
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #412
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-420]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-416]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #420
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-428]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-424]
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #428
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-436]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-432]
	sub	r4, fp, #436
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-732]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-728]
	sub	r9, fp, #732
	ldmia	r9, {r8-r9}
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-444]
	adc	r3, r9, r7
	str	r3, [fp, #-440]
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #444
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-452]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-448]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #452
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-460]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-456]
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #80
	sub	r2, fp, #460
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-468]
	adc	r2, r2, r7
	str	r2, [fp, #-464]
	sub	r2, fp, #468
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-476]
	adc	r3, r9, r7
	str	r3, [fp, #-472]
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #476
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-484]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-480]
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #484
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-492]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-488]
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #492
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-500]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-496]
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #500
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-508]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-504]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #508
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-516]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-512]
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #88
	sub	r2, fp, #516
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-524]
	adc	r2, r2, r7
	str	r2, [fp, #-520]
	sub	r2, fp, #524
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	str	r6, [fp, #-52]
	str	r7, [fp, #-48]
	mov	r2, r7
	add	r3, r3, r2
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-532]
	adc	r3, r9, r7
	str	r3, [fp, #-528]
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #532
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-540]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-536]
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #540
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-548]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-544]
	sub	r4, fp, #548
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-740]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-736]
	sub	r3, fp, #740
	ldmia	r3, {r2-r3}
	sub	r1, fp, #52
	ldmia	r1, {r0-r1}
	mov	ip, r0
	adds	ip, ip, r2
	str	ip, [fp, #-556]
	adc	r3, r1, r3
	str	r3, [fp, #-552]
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #556
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-564]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-560]
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #96
	sub	r2, fp, #564
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-572]
	adc	r2, r2, r7
	str	r2, [fp, #-568]
	sub	r2, fp, #572
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-580]
	adc	r3, r9, r7
	str	r3, [fp, #-576]
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #580
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-588]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-584]
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #588
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-596]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-592]
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #596
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-604]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-600]
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #104
	sub	r2, fp, #604
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-612]
	adc	r2, r2, r7
	str	r2, [fp, #-608]
	sub	r2, fp, #612
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-620]
	adc	r3, r9, r7
	str	r3, [fp, #-616]
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #620
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-628]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-624]
	sub	r4, fp, #628
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-748]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-744]
	sub	r9, fp, #748
	ldmia	r9, {r8-r9}
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-636]
	adc	r3, r9, r7
	str	r3, [fp, #-632]
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #112
	sub	r2, fp, #636
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-644]
	adc	r2, r2, r7
	str	r2, [fp, #-640]
	sub	r2, fp, #644
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-652]
	adc	r3, r9, r7
	str	r3, [fp, #-648]
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #652
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-660]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-656]
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r3, r3, #120
	sub	r2, fp, #660
	ldmia	r2, {r1-r2}
	mov	r0, r1
	adds	r0, r0, r6
	str	r0, [fp, #-668]
	adc	r2, r2, r7
	str	r2, [fp, #-664]
	sub	r2, fp, #668
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r2, r3
	asr	r3, r2, #31
	mul	lr, r2, r1
	mul	ip, r0, r3
	add	ip, lr, ip
	umull	r4, r5, r0, r2
	str	r4, [fp, #-52]
	str	r5, [fp, #-48]
	mov	r3, r5
	add	r3, ip, r3
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-676]
	adc	r3, r9, r7
	str	r3, [fp, #-672]
	sub	r4, fp, #676
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-756]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-752]
	sub	r3, fp, #756
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-32]
	add	r1, r1, #128
	sub	r5, fp, #52
	ldmia	r5, {r4-r5}
	mov	r0, r4
	adds	r0, r0, r2
	str	r0, [fp, #-684]
	mov	r0, r5
	adc	r3, r0, r3
	str	r3, [fp, #-680]
	sub	r4, fp, #684
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r2, r3
	asr	r3, r2, #31
	mul	r0, r2, r5
	mul	r1, r4, r3
	add	ip, r0, r1
	umull	r0, r1, r4, r2
	add	r3, ip, r1
	mov	r1, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r6, r3
	asr	r7, r6, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	mul	r2, r4, r7
	mul	r3, r6, r5
	add	ip, r2, r3
	umull	r2, r3, r6, r4
	add	ip, ip, r3
	mov	r3, ip
	ldr	ip, [fp, #-32]
	add	ip, ip, #136
	adds	lr, r0, r2
	str	lr, [fp, #-692]
	adc	r3, r1, r3
	str	r3, [fp, #-688]
	sub	r4, fp, #692
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-40]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	ip, r2, r3
	umull	r2, r3, r4, r0
	add	r1, ip, r3
	mov	r3, r1
	ldr	r1, [fp, #-32]
	add	r1, r1, #144
	adds	r0, r2, r2
	str	r0, [fp, #-764]
	adc	r3, r3, r3
	str	r3, [fp, #-760]
	sub	r3, fp, #764
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	nop
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
	.size	fproduct, .-fproduct
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	freduce_degree, %function
freduce_degree:
	@ args = 0, pretend = 0, frame = 280
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #280
	str	r0, [fp, #-32]
	ldr	r3, [fp, #-32]
	add	r3, r3, #64
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #144
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	ldr	r3, [fp, #-32]
	add	r3, r3, #64
	adds	r6, r4, r0
	adc	r7, r5, r1
	stm	r3, {r6-r7}
	ldr	r3, [fp, #-32]
	add	r3, r3, #64
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #144
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-244]
	adc	r3, r3, r3
	str	r3, [fp, #-240]
	sub	r1, fp, #244
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #64
	adds	r8, r4, r0
	adc	r9, r5, r1
	stm	r3, {r8-r9}
	ldr	r3, [fp, #-32]
	add	r3, r3, #64
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #144
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-32]
	add	r1, r1, #64
	adds	r0, r4, r2
	str	r0, [fp, #-44]
	adc	r3, r5, r3
	str	r3, [fp, #-40]
	sub	r4, fp, #44
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-32]
	add	r3, r3, #56
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #136
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	ldr	r3, [fp, #-32]
	add	r3, r3, #56
	adds	r2, r4, r0
	str	r2, [fp, #-52]
	adc	r2, r5, r1
	str	r2, [fp, #-48]
	sub	r2, fp, #52
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #56
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #136
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-252]
	adc	r3, r3, r3
	str	r3, [fp, #-248]
	sub	r1, fp, #252
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #56
	adds	r2, r4, r0
	str	r2, [fp, #-60]
	adc	r2, r5, r1
	str	r2, [fp, #-56]
	sub	r2, fp, #60
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #56
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #136
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-32]
	add	r1, r1, #56
	adds	r0, r4, r2
	str	r0, [fp, #-68]
	adc	r3, r5, r3
	str	r3, [fp, #-64]
	sub	r4, fp, #68
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-32]
	add	r3, r3, #48
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #128
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	ldr	r3, [fp, #-32]
	add	r3, r3, #48
	adds	r2, r4, r0
	str	r2, [fp, #-76]
	adc	r2, r5, r1
	str	r2, [fp, #-72]
	sub	r2, fp, #76
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #48
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #128
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-260]
	adc	r3, r3, r3
	str	r3, [fp, #-256]
	sub	r1, fp, #260
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #48
	adds	r2, r4, r0
	str	r2, [fp, #-84]
	adc	r2, r5, r1
	str	r2, [fp, #-80]
	sub	r2, fp, #84
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #48
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #128
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-32]
	add	r1, r1, #48
	adds	r0, r4, r2
	str	r0, [fp, #-92]
	adc	r3, r5, r3
	str	r3, [fp, #-88]
	sub	r4, fp, #92
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-32]
	add	r3, r3, #40
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #120
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	ldr	r3, [fp, #-32]
	add	r3, r3, #40
	adds	r2, r4, r0
	str	r2, [fp, #-100]
	adc	r2, r5, r1
	str	r2, [fp, #-96]
	sub	r2, fp, #100
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #40
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #120
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-268]
	adc	r3, r3, r3
	str	r3, [fp, #-264]
	sub	r1, fp, #268
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #40
	adds	r2, r4, r0
	str	r2, [fp, #-108]
	adc	r2, r5, r1
	str	r2, [fp, #-104]
	sub	r2, fp, #108
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #40
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #120
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-32]
	add	r1, r1, #40
	adds	r0, r4, r2
	str	r0, [fp, #-116]
	adc	r3, r5, r3
	str	r3, [fp, #-112]
	sub	r4, fp, #116
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-32]
	add	r3, r3, #32
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #112
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	ldr	r3, [fp, #-32]
	add	r3, r3, #32
	adds	r2, r4, r0
	str	r2, [fp, #-124]
	adc	r2, r5, r1
	str	r2, [fp, #-120]
	sub	r2, fp, #124
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #32
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #112
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-276]
	adc	r3, r3, r3
	str	r3, [fp, #-272]
	sub	r1, fp, #276
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #32
	adds	r2, r4, r0
	str	r2, [fp, #-132]
	adc	r2, r5, r1
	str	r2, [fp, #-128]
	sub	r2, fp, #132
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #32
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #112
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-32]
	add	r1, r1, #32
	adds	r0, r4, r2
	str	r0, [fp, #-140]
	adc	r3, r5, r3
	str	r3, [fp, #-136]
	sub	r4, fp, #140
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-32]
	add	r3, r3, #24
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #104
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	ldr	r3, [fp, #-32]
	add	r3, r3, #24
	adds	r2, r4, r0
	str	r2, [fp, #-148]
	adc	r2, r5, r1
	str	r2, [fp, #-144]
	sub	r2, fp, #148
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #24
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #104
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-284]
	adc	r3, r3, r3
	str	r3, [fp, #-280]
	sub	r1, fp, #284
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #24
	adds	r2, r4, r0
	str	r2, [fp, #-156]
	adc	r2, r5, r1
	str	r2, [fp, #-152]
	sub	r2, fp, #156
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #24
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #104
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-32]
	add	r1, r1, #24
	adds	r0, r4, r2
	str	r0, [fp, #-164]
	adc	r3, r5, r3
	str	r3, [fp, #-160]
	sub	r4, fp, #164
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-32]
	add	r3, r3, #16
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #96
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	ldr	r3, [fp, #-32]
	add	r3, r3, #16
	adds	r2, r4, r0
	str	r2, [fp, #-172]
	adc	r2, r5, r1
	str	r2, [fp, #-168]
	sub	r2, fp, #172
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #16
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #96
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-292]
	adc	r3, r3, r3
	str	r3, [fp, #-288]
	sub	r1, fp, #292
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #16
	adds	r2, r4, r0
	str	r2, [fp, #-180]
	adc	r2, r5, r1
	str	r2, [fp, #-176]
	sub	r2, fp, #180
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #16
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #96
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-32]
	add	r1, r1, #16
	adds	r0, r4, r2
	str	r0, [fp, #-188]
	adc	r3, r5, r3
	str	r3, [fp, #-184]
	sub	r4, fp, #188
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-32]
	add	r3, r3, #8
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #88
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	ldr	r3, [fp, #-32]
	add	r3, r3, #8
	adds	r2, r4, r0
	str	r2, [fp, #-196]
	adc	r2, r5, r1
	str	r2, [fp, #-192]
	sub	r2, fp, #196
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #8
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #88
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-300]
	adc	r3, r3, r3
	str	r3, [fp, #-296]
	sub	r1, fp, #300
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #8
	adds	r2, r4, r0
	str	r2, [fp, #-204]
	adc	r2, r5, r1
	str	r2, [fp, #-200]
	sub	r2, fp, #204
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	add	r3, r3, #8
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #88
	ldmia	r3, {r2-r3}
	ldr	ip, [fp, #-32]
	add	ip, ip, #8
	adds	lr, r0, r2
	str	lr, [fp, #-212]
	adc	r3, r1, r3
	str	r3, [fp, #-208]
	sub	r4, fp, #212
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-32]
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-32]
	add	r3, r3, #80
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #4
	orr	r3, r3, r0, lsr #28
	lsl	r2, r0, #4
	adds	r1, r4, r2
	str	r1, [fp, #-220]
	adc	r3, r5, r3
	str	r3, [fp, #-216]
	ldr	r3, [fp, #-32]
	sub	r2, fp, #220
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #80
	ldmia	r3, {r2-r3}
	adds	ip, r2, r2
	str	ip, [fp, #-308]
	adc	r3, r3, r3
	str	r3, [fp, #-304]
	sub	r3, fp, #308
	ldmia	r3, {r2-r3}
	adds	ip, r0, r2
	str	ip, [fp, #-228]
	adc	r3, r1, r3
	str	r3, [fp, #-224]
	ldr	r3, [fp, #-32]
	sub	r2, fp, #228
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-32]
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #80
	ldmia	r3, {r2-r3}
	adds	ip, r0, r2
	str	ip, [fp, #-236]
	adc	r3, r1, r3
	str	r3, [fp, #-232]
	ldr	r3, [fp, #-32]
	sub	r2, fp, #236
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	nop
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
	.size	freduce_degree, .-freduce_degree
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	div_by_2_26, %function
div_by_2_26:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #28
	str	r0, [fp, #-36]
	str	r1, [fp, #-32]
	sub	r5, fp, #36
	ldmia	r5, {r4-r5}
	mov	r0, #0
	mov	r1, #0
	mov	r0, r5
	mov	r1, #0
	mov	r1, r0
	str	r1, [fp, #-24]
	ldr	r1, [fp, #-24]
	asr	r1, r1, #31
	str	r1, [fp, #-20]
	ldr	r1, [fp, #-20]
	lsr	r1, r1, #6
	str	r1, [fp, #-16]
	ldr	r1, [fp, #-16]
	mov	r4, r1
	asr	r5, r4, #31
	sub	r1, fp, #36
	ldmia	r1, {r0-r1}
	adds	r2, r4, r0
	adc	r3, r5, r1
	mov	r0, #0
	mov	r1, #0
	lsr	r0, r2, #26
	orr	r0, r0, r3, lsl #6
	asr	r1, r3, #26
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	div_by_2_26, .-div_by_2_26
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	div_by_2_25, %function
div_by_2_25:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #28
	str	r0, [fp, #-36]
	str	r1, [fp, #-32]
	sub	r5, fp, #36
	ldmia	r5, {r4-r5}
	mov	r0, #0
	mov	r1, #0
	mov	r0, r5
	mov	r1, #0
	mov	r1, r0
	str	r1, [fp, #-24]
	ldr	r1, [fp, #-24]
	asr	r1, r1, #31
	str	r1, [fp, #-20]
	ldr	r1, [fp, #-20]
	lsr	r1, r1, #7
	str	r1, [fp, #-16]
	ldr	r1, [fp, #-16]
	mov	r4, r1
	asr	r5, r4, #31
	sub	r1, fp, #36
	ldmia	r1, {r0-r1}
	adds	r2, r4, r0
	adc	r3, r5, r1
	mov	r0, #0
	mov	r1, #0
	lsr	r0, r2, #25
	orr	r0, r0, r3, lsl #7
	asr	r1, r3, #25
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	div_by_2_25, .-div_by_2_25
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	div_s32_by_2_25, %function
div_s32_by_2_25:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	ldr	r3, [fp, #-16]
	asr	r3, r3, #31
	lsr	r3, r3, #7
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-8]
	add	r3, r2, r3
	asr	r3, r3, #25
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	div_s32_by_2_25, .-div_s32_by_2_25
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	freduce_coefficients, %function
freduce_coefficients:
	@ args = 0, pretend = 0, frame = 112
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #112
	str	r0, [fp, #-56]
	ldr	r3, [fp, #-56]
	add	r1, r3, #80
	mov	r2, #0
	mov	r3, #0
	stm	r1, {r2-r3}
	mov	r3, #0
	str	r3, [fp, #-52]
	b	.L19
.L20:
	ldr	r3, [fp, #-52]
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	ldmia	r3, {r2-r3}
	mov	r0, r2
	mov	r1, r3
	bl	div_by_2_26
	str	r0, [fp, #-36]
	str	r1, [fp, #-32]
	ldr	r3, [fp, #-52]
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	ldmia	r3, {r4-r5}
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #26
	orr	r1, r1, r2, lsr #6
	lsl	r0, r2, #26
	ldr	r3, [fp, #-52]
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	subs	r2, r4, r0
	str	r2, [fp, #-68]
	sbc	r2, r5, r1
	str	r2, [fp, #-64]
	sub	r2, fp, #68
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	ip, r3, r2
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	adds	lr, r0, r2
	str	lr, [fp, #-76]
	adc	r3, r1, r3
	str	r3, [fp, #-72]
	sub	r4, fp, #76
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	ldmia	r3, {r2-r3}
	mov	r0, r2
	mov	r1, r3
	bl	div_by_2_25
	str	r0, [fp, #-36]
	str	r1, [fp, #-32]
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	ldmia	r3, {r4-r5}
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #25
	orr	r1, r1, r2, lsr #7
	lsl	r0, r2, #25
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	subs	r2, r4, r0
	str	r2, [fp, #-84]
	sbc	r2, r5, r1
	str	r2, [fp, #-80]
	sub	r2, fp, #84
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-52]
	add	r3, r3, #2
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-52]
	add	r3, r3, #2
	lsl	r2, r3, #3
	ldr	r3, [fp, #-56]
	add	ip, r3, r2
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	adds	r6, r0, r2
	adc	r7, r1, r3
	stm	ip, {r6-r7}
	ldr	r3, [fp, #-52]
	add	r3, r3, #2
	str	r3, [fp, #-52]
.L19:
	ldr	r3, [fp, #-52]
	cmp	r3, #9
	bls	.L20
	ldr	r3, [fp, #-56]
	ldmia	r3, {r4-r5}
	ldr	r3, [fp, #-56]
	add	r3, r3, #80
	ldmia	r3, {r2-r3}
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	adds	r8, r4, r0
	adc	r9, r5, r1
	ldr	r3, [fp, #-56]
	stm	r3, {r8-r9}
	ldr	r3, [fp, #-56]
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-56]
	add	r3, r3, #80
	ldmia	r3, {r2-r3}
	adds	ip, r2, r2
	str	ip, [fp, #-140]
	adc	r3, r3, r3
	str	r3, [fp, #-136]
	sub	r3, fp, #140
	ldmia	r3, {r2-r3}
	adds	ip, r0, r2
	str	ip, [fp, #-92]
	adc	r3, r1, r3
	str	r3, [fp, #-88]
	ldr	r3, [fp, #-56]
	sub	r2, fp, #92
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-56]
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-56]
	add	r3, r3, #80
	ldmia	r3, {r2-r3}
	adds	ip, r0, r2
	str	ip, [fp, #-100]
	adc	r3, r1, r3
	str	r3, [fp, #-96]
	ldr	r3, [fp, #-56]
	sub	r2, fp, #100
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-56]
	add	r1, r3, #80
	mov	r2, #0
	mov	r3, #0
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-56]
	ldmia	r3, {r2-r3}
	mov	r0, r2
	mov	r1, r3
	bl	div_by_2_26
	str	r0, [fp, #-44]
	str	r1, [fp, #-40]
	ldr	r3, [fp, #-56]
	ldmia	r3, {r4-r5}
	sub	r1, fp, #44
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #26
	orr	r3, r3, r0, lsr #6
	lsl	r2, r0, #26
	subs	r1, r4, r2
	str	r1, [fp, #-108]
	sbc	r3, r5, r3
	str	r3, [fp, #-104]
	ldr	r3, [fp, #-56]
	sub	r2, fp, #108
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-56]
	add	r3, r3, #8
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-56]
	add	ip, r3, #8
	sub	r3, fp, #44
	ldmia	r3, {r2-r3}
	adds	lr, r0, r2
	str	lr, [fp, #-116]
	adc	r3, r1, r3
	str	r3, [fp, #-112]
	sub	r4, fp, #116
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-56]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	bl	div_s32_by_2_25
	str	r0, [fp, #-48]
	ldr	r3, [fp, #-56]
	add	r3, r3, #8
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-48]
	lsl	r3, r3, #25
	mov	r2, r3
	asr	r3, r2, #31
	ldr	ip, [fp, #-56]
	add	ip, ip, #8
	subs	lr, r0, r2
	str	lr, [fp, #-124]
	sbc	r3, r1, r3
	str	r3, [fp, #-120]
	sub	r4, fp, #124
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-56]
	add	r3, r3, #16
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-48]
	mov	r2, r3
	asr	r3, r2, #31
	ldr	ip, [fp, #-56]
	add	ip, ip, #16
	adds	lr, r0, r2
	str	lr, [fp, #-132]
	adc	r3, r1, r3
	str	r3, [fp, #-128]
	sub	r4, fp, #132
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	nop
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
	.size	freduce_coefficients, .-freduce_coefficients
	.section	.rodata
	.align	2
.LC0:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fmul, %function
fmul:
	@ args = 0, pretend = 0, frame = 176
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #176
	str	r0, [fp, #-168]
	str	r1, [fp, #-172]
	str	r2, [fp, #-176]
	ldr	r3, .L23
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	sub	r3, fp, #164
	ldr	r2, [fp, #-176]
	ldr	r1, [fp, #-172]
	mov	r0, r3
	bl	fproduct
	sub	r3, fp, #164
	mov	r0, r3
	bl	freduce_degree
	sub	r3, fp, #164
	mov	r0, r3
	bl	freduce_coefficients
	sub	r3, fp, #164
	mov	r2, #80
	mov	r1, r3
	ldr	r0, [fp, #-168]
	bl	memcpy
	nop
	ldr	r3, .L23
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L22
	bl	__stack_chk_fail
.L22:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L24:
	.align	2
.L23:
	.word	.LC0
	.size	fmul, .-fmul
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fsquare_inner, %function
fsquare_inner:
	@ args = 0, pretend = 0, frame = 464
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #464
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	stm	r3, {r6-r7}
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-32]
	add	r1, r3, #8
	adds	r3, r6, r6
	str	r3, [fp, #-44]
	adc	r3, r7, r7
	str	r3, [fp, #-40]
	sub	r3, fp, #44
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	str	r6, [fp, #-44]
	str	r7, [fp, #-40]
	mov	r2, r7
	add	r3, r3, r2
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #44
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r8, r2, r6
	mov	r3, r4
	adc	r9, r3, r7
	ldr	r3, [fp, #-32]
	add	r1, r3, #16
	adds	r3, r8, r8
	str	r3, [fp, #-332]
	adc	r3, r9, r9
	str	r3, [fp, #-328]
	sub	r3, fp, #332
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-52]
	adc	r3, r9, r7
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-32]
	add	r1, r3, #24
	sub	r4, fp, #52
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-340]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-336]
	sub	r3, fp, #340
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r7, #2
	orr	r3, r3, r6, lsr #30
	lsl	r2, r6, #2
	adds	r1, r8, r2
	str	r1, [fp, #-60]
	adc	r3, r9, r3
	str	r3, [fp, #-56]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	ip, r2, r3
	umull	r2, r3, r4, r0
	add	r1, ip, r3
	mov	r3, r1
	adds	r1, r2, r2
	str	r1, [fp, #-348]
	adc	r3, r3, r3
	str	r3, [fp, #-344]
	sub	r1, fp, #348
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #32
	sub	r5, fp, #60
	ldmia	r5, {r4-r5}
	mov	r2, r4
	adds	r2, r2, r0
	str	r2, [fp, #-68]
	mov	r2, r5
	adc	r2, r2, r1
	str	r2, [fp, #-64]
	sub	r2, fp, #68
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-76]
	adc	r3, r9, r7
	str	r3, [fp, #-72]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #76
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-84]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-80]
	ldr	r3, [fp, #-32]
	add	r1, r3, #40
	sub	r4, fp, #84
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-356]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-352]
	sub	r3, fp, #356
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-92]
	adc	r3, r9, r7
	str	r3, [fp, #-88]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #92
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-100]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-96]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	ip, r2, r3
	umull	r2, r3, r4, r0
	add	r1, ip, r3
	mov	r3, r1
	adds	r1, r2, r2
	str	r1, [fp, #-364]
	adc	r3, r3, r3
	str	r3, [fp, #-360]
	sub	r3, fp, #364
	ldmia	r3, {r2-r3}
	sub	r1, fp, #100
	ldmia	r1, {r0-r1}
	mov	ip, r0
	adds	ip, ip, r2
	str	ip, [fp, #-108]
	adc	r3, r1, r3
	str	r3, [fp, #-104]
	ldr	r3, [fp, #-32]
	add	r1, r3, #48
	sub	r4, fp, #108
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-372]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-368]
	sub	r3, fp, #372
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-116]
	adc	r3, r9, r7
	str	r3, [fp, #-112]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #116
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-124]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-120]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #124
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-132]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-128]
	ldr	r3, [fp, #-32]
	add	r1, r3, #56
	sub	r4, fp, #132
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-380]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-376]
	sub	r3, fp, #380
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	str	r6, [fp, #-44]
	str	r7, [fp, #-40]
	mov	r2, r7
	add	r3, r3, r2
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-140]
	adc	r3, r9, r7
	str	r3, [fp, #-136]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-148]
	adc	r3, r9, r7
	str	r3, [fp, #-144]
	sub	r4, fp, #148
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-388]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-384]
	sub	r3, fp, #388
	ldmia	r3, {r2-r3}
	sub	r1, fp, #140
	ldmia	r1, {r0-r1}
	mov	ip, r0
	adds	ip, ip, r2
	str	ip, [fp, #-156]
	adc	r3, r1, r3
	str	r3, [fp, #-152]
	sub	r4, fp, #156
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-396]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-392]
	sub	r1, fp, #396
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #64
	sub	r5, fp, #44
	ldmia	r5, {r4-r5}
	mov	r2, r4
	adds	r2, r2, r0
	str	r2, [fp, #-164]
	mov	r2, r5
	adc	r2, r2, r1
	str	r2, [fp, #-160]
	sub	r2, fp, #164
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-172]
	adc	r3, r9, r7
	str	r3, [fp, #-168]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #172
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-180]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-176]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #180
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-188]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-184]
	ldr	r3, [fp, #-36]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #188
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-196]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-192]
	ldr	r3, [fp, #-32]
	add	r1, r3, #72
	sub	r4, fp, #196
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-404]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-400]
	sub	r3, fp, #404
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-204]
	adc	r3, r9, r7
	str	r3, [fp, #-200]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #204
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-212]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-208]
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-220]
	adc	r3, r9, r7
	str	r3, [fp, #-216]
	sub	r4, fp, #220
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-412]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-408]
	sub	r3, fp, #412
	ldmia	r3, {r2-r3}
	sub	r1, fp, #212
	ldmia	r1, {r0-r1}
	mov	ip, r0
	adds	ip, ip, r2
	str	ip, [fp, #-228]
	adc	r3, r1, r3
	str	r3, [fp, #-224]
	ldr	r3, [fp, #-32]
	add	r1, r3, #80
	sub	r4, fp, #228
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-420]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-416]
	sub	r3, fp, #420
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-236]
	adc	r3, r9, r7
	str	r3, [fp, #-232]
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #236
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-244]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-240]
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #244
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-252]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-248]
	ldr	r3, [fp, #-32]
	add	r1, r3, #88
	sub	r4, fp, #252
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-428]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-424]
	sub	r3, fp, #428
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	str	r6, [fp, #-44]
	str	r7, [fp, #-40]
	mov	r2, r7
	add	r3, r3, r2
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	str	r6, [fp, #-52]
	str	r7, [fp, #-48]
	mov	r2, r7
	add	r3, r3, r2
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-260]
	adc	r3, r9, r7
	str	r3, [fp, #-256]
	sub	r4, fp, #260
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-436]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-432]
	sub	r3, fp, #436
	ldmia	r3, {r2-r3}
	sub	r1, fp, #52
	ldmia	r1, {r0-r1}
	mov	ip, r0
	adds	ip, ip, r2
	str	ip, [fp, #-268]
	adc	r3, r1, r3
	str	r3, [fp, #-264]
	sub	r4, fp, #268
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-444]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-440]
	sub	r1, fp, #444
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-32]
	add	r3, r3, #96
	sub	r5, fp, #44
	ldmia	r5, {r4-r5}
	mov	r2, r4
	adds	r2, r2, r0
	str	r2, [fp, #-276]
	mov	r2, r5
	adc	r2, r2, r1
	str	r2, [fp, #-272]
	sub	r2, fp, #276
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-284]
	adc	r3, r9, r7
	str	r3, [fp, #-280]
	ldr	r3, [fp, #-36]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	sub	r4, fp, #284
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r6
	str	r2, [fp, #-292]
	mov	r3, r4
	adc	r3, r3, r7
	str	r3, [fp, #-288]
	ldr	r3, [fp, #-32]
	add	r1, r3, #104
	sub	r4, fp, #292
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-452]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-448]
	sub	r3, fp, #452
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r8, r9, r4, r0
	add	r3, r3, r9
	mov	r9, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	adds	r3, r8, r6
	str	r3, [fp, #-300]
	adc	r3, r9, r7
	str	r3, [fp, #-296]
	ldr	r3, [fp, #-36]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	ip, r2, r3
	umull	r2, r3, r4, r0
	add	r1, ip, r3
	mov	r3, r1
	adds	r1, r2, r2
	str	r1, [fp, #-460]
	adc	r3, r3, r3
	str	r3, [fp, #-456]
	sub	r3, fp, #460
	ldmia	r3, {r2-r3}
	sub	r1, fp, #300
	ldmia	r1, {r0-r1}
	mov	ip, r0
	adds	ip, ip, r2
	str	ip, [fp, #-308]
	adc	r3, r1, r3
	str	r3, [fp, #-304]
	ldr	r3, [fp, #-32]
	add	r1, r3, #112
	sub	r4, fp, #308
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-468]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-464]
	sub	r3, fp, #468
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r2, r3
	asr	r3, r2, #31
	mul	lr, r2, r1
	mul	ip, r0, r3
	add	ip, lr, ip
	umull	r6, r7, r0, r2
	add	r3, ip, r7
	mov	r7, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	ip, r2, r3
	umull	r2, r3, r4, r0
	add	r1, ip, r3
	mov	r3, r1
	adds	r1, r6, r2
	str	r1, [fp, #-316]
	adc	r3, r7, r3
	str	r3, [fp, #-312]
	ldr	r3, [fp, #-32]
	add	r1, r3, #120
	sub	r4, fp, #316
	ldmia	r4, {r3-r4}
	mov	r2, r3
	adds	r2, r2, r2
	str	r2, [fp, #-476]
	mov	r3, r4
	adc	r3, r3, r3
	str	r3, [fp, #-472]
	sub	r3, fp, #476
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r2, r3
	asr	r3, r2, #31
	mul	lr, r2, r1
	mul	ip, r0, r3
	add	ip, lr, ip
	umull	r4, r5, r0, r2
	add	r3, ip, r5
	mov	r5, r3
	ldr	r3, [fp, #-36]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r6, r3
	asr	r7, r6, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r2, r3
	asr	r3, r2, #31
	mul	r0, r2, r7
	mul	r1, r6, r3
	add	ip, r0, r1
	umull	r0, r1, r6, r2
	add	r3, ip, r1
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #2
	orr	r3, r3, r0, lsr #30
	lsl	r2, r0, #2
	ldr	r1, [fp, #-32]
	add	r1, r1, #128
	adds	r0, r4, r2
	str	r0, [fp, #-324]
	adc	r3, r5, r3
	str	r3, [fp, #-320]
	sub	r4, fp, #324
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	ip, r2, r3
	umull	r2, r3, r4, r0
	add	r1, ip, r3
	mov	r3, r1
	ldr	r1, [fp, #-32]
	add	r1, r1, #136
	adds	r0, r2, r2
	str	r0, [fp, #-484]
	adc	r3, r3, r3
	str	r3, [fp, #-480]
	sub	r3, fp, #484
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-36]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	ip, r2, r3
	umull	r2, r3, r4, r0
	add	r1, ip, r3
	mov	r3, r1
	ldr	r1, [fp, #-32]
	add	r1, r1, #144
	adds	r0, r2, r2
	str	r0, [fp, #-492]
	adc	r3, r3, r3
	str	r3, [fp, #-488]
	sub	r3, fp, #492
	ldmia	r3, {r2-r3}
	stm	r1, {r2-r3}
	nop
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
	.size	fsquare_inner, .-fsquare_inner
	.section	.rodata
	.align	2
.LC1:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fsquare, %function
fsquare:
	@ args = 0, pretend = 0, frame = 168
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #168
	str	r0, [fp, #-168]
	str	r1, [fp, #-172]
	ldr	r3, .L28
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	sub	r3, fp, #164
	ldr	r1, [fp, #-172]
	mov	r0, r3
	bl	fsquare_inner
	sub	r3, fp, #164
	mov	r0, r3
	bl	freduce_degree
	sub	r3, fp, #164
	mov	r0, r3
	bl	freduce_coefficients
	sub	r3, fp, #164
	mov	r2, #80
	mov	r1, r3
	ldr	r0, [fp, #-168]
	bl	memcpy
	nop
	ldr	r3, .L28
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L27
	bl	__stack_chk_fail
.L27:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L29:
	.align	2
.L28:
	.word	.LC1
	.size	fsquare, .-fsquare
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fexpand, %function
fexpand:
	@ args = 0, pretend = 0, frame = 392
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #392
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	ldr	r3, [fp, #-36]
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #1
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r8, r4, r0
	orr	r9, r5, r1
	ldr	r3, [fp, #-36]
	add	r3, r3, #2
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	orr	r3, r8, r0
	str	r3, [fp, #-44]
	orr	r3, r9, r1
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-36]
	add	r3, r3, #3
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r7, r2, #8
	lsl	r6, r2, #24
	sub	r4, fp, #44
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r6
	str	r2, [fp, #-52]
	mov	r3, r4
	orr	r3, r3, r7
	str	r3, [fp, #-48]
	mvn	r2, #-67108864
	mov	r3, #0
	sub	r1, fp, #52
	ldmia	r1, {r0-r1}
	mov	ip, r0
	and	ip, ip, r2
	str	ip, [fp, #-60]
	and	r1, r1, r3
	str	r1, [fp, #-56]
	ldr	r3, [fp, #-32]
	sub	r2, fp, #60
	ldmia	r2, {r1-r2}
	stm	r3, {r1-r2}
	ldr	r3, [fp, #-36]
	add	r3, r3, #3
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #4
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-68]
	orr	r3, r5, r1
	str	r3, [fp, #-64]
	ldr	r3, [fp, #-36]
	add	r3, r3, #5
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	sub	r4, fp, #68
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r0
	str	r2, [fp, #-76]
	mov	r3, r4
	orr	r3, r3, r1
	str	r3, [fp, #-72]
	ldr	r3, [fp, #-36]
	add	r3, r3, #6
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-80]
	lsl	r3, r2, #24
	str	r3, [fp, #-84]
	sub	r2, fp, #76
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #84
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-92]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-88]
	mov	r0, #0
	mov	r1, #0
	sub	r4, fp, #92
	ldmia	r4, {r3-r4}
	mov	r2, r3
	lsr	r0, r2, #2
	mov	r2, r4
	orr	r0, r0, r2, lsl #30
	mov	r3, r4
	asr	r1, r3, #2
	ldr	r3, [fp, #-32]
	add	ip, r3, #8
	mvn	r2, #-33554432
	mov	r3, #0
	and	lr, r0, r2
	str	lr, [fp, #-100]
	and	r3, r1, r3
	str	r3, [fp, #-96]
	sub	r4, fp, #100
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #6
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #7
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-108]
	orr	r3, r5, r1
	str	r3, [fp, #-104]
	ldr	r3, [fp, #-36]
	add	r3, r3, #8
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	sub	r4, fp, #108
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r0
	str	r2, [fp, #-116]
	mov	r3, r4
	orr	r3, r3, r1
	str	r3, [fp, #-112]
	ldr	r3, [fp, #-36]
	add	r3, r3, #9
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-120]
	lsl	r3, r2, #24
	str	r3, [fp, #-124]
	sub	r2, fp, #116
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #124
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-132]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-128]
	mov	r0, #0
	mov	r1, #0
	sub	r4, fp, #132
	ldmia	r4, {r3-r4}
	mov	r2, r3
	lsr	r0, r2, #3
	mov	r2, r4
	orr	r0, r0, r2, lsl #29
	mov	r3, r4
	asr	r1, r3, #3
	ldr	r3, [fp, #-32]
	add	ip, r3, #16
	mvn	r2, #-67108864
	mov	r3, #0
	and	lr, r0, r2
	str	lr, [fp, #-140]
	and	r3, r1, r3
	str	r3, [fp, #-136]
	sub	r4, fp, #140
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #9
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #10
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-148]
	orr	r3, r5, r1
	str	r3, [fp, #-144]
	ldr	r3, [fp, #-36]
	add	r3, r3, #11
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	sub	r4, fp, #148
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r0
	str	r2, [fp, #-156]
	mov	r3, r4
	orr	r3, r3, r1
	str	r3, [fp, #-152]
	ldr	r3, [fp, #-36]
	add	r3, r3, #12
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-160]
	lsl	r3, r2, #24
	str	r3, [fp, #-164]
	sub	r2, fp, #156
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #164
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-172]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-168]
	mov	r0, #0
	mov	r1, #0
	sub	r4, fp, #172
	ldmia	r4, {r3-r4}
	mov	r2, r3
	lsr	r0, r2, #5
	mov	r2, r4
	orr	r0, r0, r2, lsl #27
	mov	r3, r4
	asr	r1, r3, #5
	ldr	r3, [fp, #-32]
	add	ip, r3, #24
	mvn	r2, #-33554432
	mov	r3, #0
	and	lr, r0, r2
	str	lr, [fp, #-180]
	and	r3, r1, r3
	str	r3, [fp, #-176]
	sub	r4, fp, #180
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #12
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #13
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-188]
	orr	r3, r5, r1
	str	r3, [fp, #-184]
	ldr	r3, [fp, #-36]
	add	r3, r3, #14
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	sub	r4, fp, #188
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r0
	str	r2, [fp, #-196]
	mov	r3, r4
	orr	r3, r3, r1
	str	r3, [fp, #-192]
	ldr	r3, [fp, #-36]
	add	r3, r3, #15
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-200]
	lsl	r3, r2, #24
	str	r3, [fp, #-204]
	sub	r2, fp, #196
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #204
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-212]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-208]
	mov	r0, #0
	mov	r1, #0
	sub	r4, fp, #212
	ldmia	r4, {r3-r4}
	mov	r2, r3
	lsr	r0, r2, #6
	mov	r2, r4
	orr	r0, r0, r2, lsl #26
	mov	r3, r4
	asr	r1, r3, #6
	ldr	r3, [fp, #-32]
	add	ip, r3, #32
	mvn	r2, #-67108864
	mov	r3, #0
	and	lr, r0, r2
	str	lr, [fp, #-220]
	and	r3, r1, r3
	str	r3, [fp, #-216]
	sub	r4, fp, #220
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #16
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #17
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-228]
	orr	r3, r5, r1
	str	r3, [fp, #-224]
	ldr	r3, [fp, #-36]
	add	r3, r3, #18
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	sub	r4, fp, #228
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r0
	str	r2, [fp, #-236]
	mov	r3, r4
	orr	r3, r3, r1
	str	r3, [fp, #-232]
	ldr	r3, [fp, #-36]
	add	r3, r3, #19
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-240]
	lsl	r3, r2, #24
	str	r3, [fp, #-244]
	sub	r2, fp, #236
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #244
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-252]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-248]
	ldr	r3, [fp, #-32]
	add	r1, r3, #40
	mvn	r2, #-33554432
	mov	r3, #0
	sub	r5, fp, #252
	ldmia	r5, {r4-r5}
	mov	r0, r4
	and	r0, r0, r2
	str	r0, [fp, #-260]
	mov	r0, r5
	and	r0, r0, r3
	str	r0, [fp, #-256]
	sub	r4, fp, #260
	ldmia	r4, {r3-r4}
	stm	r1, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #19
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #20
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-268]
	orr	r3, r5, r1
	str	r3, [fp, #-264]
	ldr	r3, [fp, #-36]
	add	r3, r3, #21
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	sub	r4, fp, #268
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r0
	str	r2, [fp, #-276]
	mov	r3, r4
	orr	r3, r3, r1
	str	r3, [fp, #-272]
	ldr	r3, [fp, #-36]
	add	r3, r3, #22
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-280]
	lsl	r3, r2, #24
	str	r3, [fp, #-284]
	sub	r2, fp, #276
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #284
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-292]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-288]
	mov	r0, #0
	mov	r1, #0
	sub	r4, fp, #292
	ldmia	r4, {r3-r4}
	mov	r2, r3
	lsr	r0, r2, #1
	mov	r2, r4
	orr	r0, r0, r2, lsl #31
	mov	r3, r4
	asr	r1, r3, #1
	ldr	r3, [fp, #-32]
	add	ip, r3, #48
	mvn	r2, #-67108864
	mov	r3, #0
	and	lr, r0, r2
	str	lr, [fp, #-300]
	and	r3, r1, r3
	str	r3, [fp, #-296]
	sub	r4, fp, #300
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #22
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #23
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-308]
	orr	r3, r5, r1
	str	r3, [fp, #-304]
	ldr	r3, [fp, #-36]
	add	r3, r3, #24
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	sub	r4, fp, #308
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r0
	str	r2, [fp, #-316]
	mov	r3, r4
	orr	r3, r3, r1
	str	r3, [fp, #-312]
	ldr	r3, [fp, #-36]
	add	r3, r3, #25
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-320]
	lsl	r3, r2, #24
	str	r3, [fp, #-324]
	sub	r2, fp, #316
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #324
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-332]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-328]
	mov	r0, #0
	mov	r1, #0
	sub	r4, fp, #332
	ldmia	r4, {r3-r4}
	mov	r2, r3
	lsr	r0, r2, #3
	mov	r2, r4
	orr	r0, r0, r2, lsl #29
	mov	r3, r4
	asr	r1, r3, #3
	ldr	r3, [fp, #-32]
	add	ip, r3, #56
	mvn	r2, #-33554432
	mov	r3, #0
	and	lr, r0, r2
	str	lr, [fp, #-340]
	and	r3, r1, r3
	str	r3, [fp, #-336]
	sub	r4, fp, #340
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #25
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #26
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-348]
	orr	r3, r5, r1
	str	r3, [fp, #-344]
	ldr	r3, [fp, #-36]
	add	r3, r3, #27
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #16
	orr	r1, r1, r2, lsr #16
	lsl	r0, r2, #16
	sub	r4, fp, #348
	ldmia	r4, {r3-r4}
	mov	r2, r3
	orr	r2, r2, r0
	str	r2, [fp, #-356]
	mov	r3, r4
	orr	r3, r3, r1
	str	r3, [fp, #-352]
	ldr	r3, [fp, #-36]
	add	r3, r3, #28
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-360]
	lsl	r3, r2, #24
	str	r3, [fp, #-364]
	sub	r2, fp, #356
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #364
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-372]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-368]
	mov	r0, #0
	mov	r1, #0
	sub	r4, fp, #372
	ldmia	r4, {r3-r4}
	mov	r2, r3
	lsr	r0, r2, #4
	mov	r2, r4
	orr	r0, r0, r2, lsl #28
	mov	r3, r4
	asr	r1, r3, #4
	ldr	r3, [fp, #-32]
	add	ip, r3, #64
	mvn	r2, #-67108864
	mov	r3, #0
	and	lr, r0, r2
	str	lr, [fp, #-380]
	and	r3, r1, r3
	str	r3, [fp, #-376]
	sub	r4, fp, #380
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	ldr	r3, [fp, #-36]
	add	r3, r3, #28
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r4, r3, #255
	mov	r5, #0
	ldr	r3, [fp, #-36]
	add	r3, r3, #29
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #8
	orr	r1, r1, r2, lsr #24
	lsl	r0, r2, #8
	orr	r3, r4, r0
	str	r3, [fp, #-388]
	orr	r3, r5, r1
	str	r3, [fp, #-384]
	ldr	r3, [fp, #-36]
	add	r3, r3, #30
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r0, r3, #255
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #16
	orr	r3, r3, r0, lsr #16
	lsl	r2, r0, #16
	sub	r1, fp, #388
	ldmia	r1, {r0-r1}
	mov	ip, r0
	orr	ip, ip, r2
	str	ip, [fp, #-396]
	orr	r3, r1, r3
	str	r3, [fp, #-392]
	ldr	r3, [fp, #-36]
	add	r3, r3, #31
	ldrb	r3, [r3]	@ zero_extendqisi2
	and	r2, r3, #255
	mov	r3, #0
	lsr	r1, r2, #8
	str	r1, [fp, #-400]
	lsl	r3, r2, #24
	str	r3, [fp, #-404]
	sub	r2, fp, #396
	ldmia	r2, {r1-r2}
	mov	r0, r1
	sub	r4, fp, #404
	ldmia	r4, {r3-r4}
	mov	ip, r3
	orr	r0, r0, ip
	str	r0, [fp, #-412]
	mov	r3, r4
	orr	r3, r2, r3
	str	r3, [fp, #-408]
	mov	r2, #0
	mov	r3, #0
	sub	r1, fp, #412
	ldmia	r1, {r0-r1}
	mov	ip, r0
	lsr	r2, ip, #6
	mov	ip, r1
	orr	r2, r2, ip, lsl #26
	asr	r3, r1, #6
	ldr	r1, [fp, #-32]
	add	ip, r1, #72
	mvn	r0, #-67108864
	mov	r1, #0
	and	lr, r2, r0
	str	lr, [fp, #-420]
	and	r3, r3, r1
	str	r3, [fp, #-416]
	sub	r4, fp, #420
	ldmia	r4, {r3-r4}
	stm	ip, {r3-r4}
	nop
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
	.size	fexpand, .-fexpand
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fcontract, %function
fcontract:
	@ args = 0, pretend = 0, frame = 48
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #52
	str	r0, [fp, #-56]
	str	r1, [fp, #-60]
	mov	r3, #0
	str	r3, [fp, #-48]
	b	.L32
.L37:
	mov	r3, #0
	str	r3, [fp, #-52]
	b	.L33
.L36:
	ldr	r3, [fp, #-52]
	and	r3, r3, #1
	cmp	r3, #0
	beq	.L34
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-60]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	mov	r3, r2
	asr	r3, r3, #31
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-60]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-20]
	and	r3, r3, r2
	asr	r3, r3, #25
	rsb	r3, r3, #0
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-60]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #25
	add	r3, r2, r3
	ldr	r2, [fp, #-52]
	lsl	r2, r2, #3
	ldr	r1, [fp, #-60]
	add	r1, r1, r2
	mov	r2, r3
	asr	r3, r2, #31
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	lsl	r3, r3, #3
	ldr	r2, [fp, #-60]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-16]
	sub	r3, r2, r3
	ldr	r2, [fp, #-52]
	add	r2, r2, #1
	lsl	r2, r2, #3
	ldr	r1, [fp, #-60]
	add	r1, r1, r2
	mov	r2, r3
	asr	r3, r2, #31
	stm	r1, {r2-r3}
	b	.L35
.L34:
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-60]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	mov	r3, r2
	asr	r3, r3, #31
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-60]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-28]
	and	r3, r3, r2
	asr	r3, r3, #26
	rsb	r3, r3, #0
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-60]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #26
	add	r3, r2, r3
	ldr	r2, [fp, #-52]
	lsl	r2, r2, #3
	ldr	r1, [fp, #-60]
	add	r1, r1, r2
	mov	r2, r3
	asr	r3, r2, #31
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	lsl	r3, r3, #3
	ldr	r2, [fp, #-60]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-24]
	sub	r3, r2, r3
	ldr	r2, [fp, #-52]
	add	r2, r2, #1
	lsl	r2, r2, #3
	ldr	r1, [fp, #-60]
	add	r1, r1, r2
	mov	r2, r3
	asr	r3, r2, #31
	stm	r1, {r2-r3}
.L35:
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	str	r3, [fp, #-52]
.L33:
	ldr	r3, [fp, #-52]
	cmp	r3, #8
	ble	.L36
	ldr	r3, [fp, #-60]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	mov	r3, r2
	asr	r3, r3, #31
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-60]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-36]
	and	r3, r3, r2
	asr	r3, r3, #25
	rsb	r3, r3, #0
	str	r3, [fp, #-32]
	ldr	r3, [fp, #-60]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #25
	add	r3, r2, r3
	ldr	r2, [fp, #-60]
	add	r1, r2, #72
	mov	r2, r3
	asr	r3, r2, #31
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-60]
	ldmia	r3, {r2-r3}
	mov	r1, r2
	ldr	r2, [fp, #-32]
	mov	r3, r2
	lsl	r3, r3, #28
	sub	r3, r3, r2
	lsl	r3, r3, #2
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r3, r1, r3
	mov	r2, r3
	asr	r3, r2, #31
	ldr	r1, [fp, #-60]
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-48]
	add	r3, r3, #1
	str	r3, [fp, #-48]
.L32:
	ldr	r3, [fp, #-48]
	cmp	r3, #1
	ble	.L37
	ldr	r3, [fp, #-60]
	ldmia	r3, {r2-r3}
	mov	r3, r2
	asr	r3, r3, #31
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-60]
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-44]
	and	r3, r3, r2
	asr	r3, r3, #26
	rsb	r3, r3, #0
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-60]
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-40]
	lsl	r3, r3, #26
	add	r3, r2, r3
	mov	r2, r3
	asr	r3, r2, #31
	ldr	r1, [fp, #-60]
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-40]
	sub	r3, r2, r3
	ldr	r2, [fp, #-60]
	add	r1, r2, #8
	mov	r2, r3
	asr	r3, r2, #31
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #8
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-60]
	add	ip, r3, #8
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #2
	orr	r3, r3, r0, lsr #30
	lsl	r2, r0, #2
	stm	ip, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #16
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-60]
	add	ip, r3, #16
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #3
	orr	r3, r3, r0, lsr #29
	lsl	r2, r0, #3
	stm	ip, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #24
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-60]
	add	ip, r3, #24
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #5
	orr	r3, r3, r0, lsr #27
	lsl	r2, r0, #5
	stm	ip, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #32
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-60]
	add	ip, r3, #32
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #6
	orr	r3, r3, r0, lsr #26
	lsl	r2, r0, #6
	stm	ip, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	ldr	r1, [fp, #-60]
	add	r1, r1, #48
	adds	r4, r2, r2
	adc	r5, r3, r3
	mov	r2, r4
	mov	r3, r5
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #56
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-60]
	add	ip, r3, #56
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #3
	orr	r3, r3, r0, lsr #29
	lsl	r2, r0, #3
	stm	ip, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #64
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-60]
	add	ip, r3, #64
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #4
	orr	r3, r3, r0, lsr #28
	lsl	r2, r0, #4
	stm	ip, {r2-r3}
	ldr	r3, [fp, #-60]
	add	r3, r3, #72
	ldmia	r3, {r0-r1}
	ldr	r3, [fp, #-60]
	add	ip, r3, #72
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #6
	orr	r3, r3, r0, lsr #26
	lsl	r2, r0, #6
	stm	ip, {r2-r3}
	ldr	r3, [fp, #-56]
	mov	r2, #0
	strb	r2, [r3]
	ldr	r3, [fp, #-56]
	add	r3, r3, #16
	mov	r2, #0
	strb	r2, [r3]
	ldr	r3, [fp, #-56]
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r2, r3, #255
	ldr	r3, [fp, #-56]
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #1
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #2
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #3
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #3
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #8
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #3
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #8
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #4
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #8
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #5
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #8
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #6
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #6
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #16
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #6
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #16
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #7
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #16
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #8
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #16
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #9
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #9
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #24
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #9
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #24
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #10
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #24
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #11
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #24
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #12
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #12
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #32
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #12
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #32
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #13
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #32
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #14
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #32
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #15
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #16
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #40
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #16
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #40
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #17
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #40
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #18
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #40
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #19
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #19
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #48
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #19
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #48
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #20
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #48
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #21
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #48
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #22
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #22
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #56
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #22
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #56
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #23
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #56
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #24
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #56
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #25
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #25
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #64
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #25
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #64
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #26
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #64
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #27
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #64
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #28
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-56]
	add	r3, r3, #28
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-60]
	add	r3, r3, #72
	ldmia	r3, {r2-r3}
	lsl	r3, r2, #24
	asr	r3, r3, #24
	orr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-56]
	add	r3, r3, #28
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r3, [fp, #-60]
	add	r3, r3, #72
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #8
	orr	r2, r2, r1, lsl #24
	asr	r3, r1, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #29
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #72
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #16
	orr	r2, r2, r1, lsl #16
	asr	r3, r1, #16
	ldr	r1, [fp, #-56]
	add	r1, r1, #30
	and	r3, r2, #255
	strb	r3, [r1]
	ldr	r3, [fp, #-60]
	add	r3, r3, #72
	ldmia	r3, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #24
	orr	r2, r2, r1, lsl #8
	asr	r3, r1, #24
	ldr	r1, [fp, #-56]
	add	r1, r1, #31
	and	r3, r2, #255
	strb	r3, [r1]
	nop
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	fcontract, .-fcontract
	.section	.rodata
	.align	2
.LC2:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	fmonty, %function
fmonty:
	@ args = 20, pretend = 0, frame = 1272
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #1264
	sub	sp, sp, #8
	str	r0, [fp, #-1240]
	str	r1, [fp, #-1244]
	str	r2, [fp, #-1248]
	str	r3, [fp, #-1252]
	ldr	r3, [fp, #4]
	str	r3, [fp, #-1256]
	ldr	r3, [fp, #8]
	str	r3, [fp, #-1260]
	ldr	r3, [fp, #12]
	str	r3, [fp, #-1264]
	ldr	r3, [fp, #16]
	str	r3, [fp, #-1268]
	ldr	r3, [fp, #20]
	str	r3, [fp, #-1272]
	ldr	r3, .L40
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	sub	r3, fp, #1232
	sub	r3, r3, #4
	mov	r2, #80
	ldr	r1, [fp, #-1256]
	mov	r0, r3
	bl	memcpy
	ldr	r1, [fp, #-1260]
	ldr	r0, [fp, #-1256]
	bl	fsum
	sub	r3, fp, #1232
	sub	r3, r3, #4
	mov	r1, r3
	ldr	r0, [fp, #-1260]
	bl	fdifference
	sub	r3, fp, #1152
	sub	r3, r3, #4
	mov	r2, #80
	ldr	r1, [fp, #-1264]
	mov	r0, r3
	bl	memcpy
	ldr	r1, [fp, #-1268]
	ldr	r0, [fp, #-1264]
	bl	fsum
	sub	r3, fp, #1152
	sub	r3, r3, #4
	mov	r1, r3
	ldr	r0, [fp, #-1268]
	bl	fdifference
	sub	r3, fp, #620
	ldr	r2, [fp, #-1260]
	ldr	r1, [fp, #-1264]
	mov	r0, r3
	bl	fproduct
	sub	r3, fp, #468
	ldr	r2, [fp, #-1268]
	ldr	r1, [fp, #-1256]
	mov	r0, r3
	bl	fproduct
	sub	r3, fp, #620
	mov	r0, r3
	bl	freduce_degree
	sub	r3, fp, #620
	mov	r0, r3
	bl	freduce_coefficients
	sub	r3, fp, #468
	mov	r0, r3
	bl	freduce_degree
	sub	r3, fp, #468
	mov	r0, r3
	bl	freduce_coefficients
	sub	r3, fp, #1152
	sub	r3, r3, #4
	sub	r1, fp, #620
	mov	r2, #80
	mov	r0, r3
	bl	memcpy
	sub	r2, fp, #468
	sub	r3, fp, #620
	mov	r1, r2
	mov	r0, r3
	bl	fsum
	sub	r2, fp, #1152
	sub	r2, r2, #4
	sub	r3, fp, #468
	mov	r1, r2
	mov	r0, r3
	bl	fdifference
	sub	r2, fp, #620
	sub	r3, fp, #164
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #468
	sub	r3, fp, #316
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r1, fp, #316
	sub	r3, fp, #468
	ldr	r2, [fp, #-1272]
	mov	r0, r3
	bl	fproduct
	sub	r3, fp, #468
	mov	r0, r3
	bl	freduce_degree
	sub	r3, fp, #468
	mov	r0, r3
	bl	freduce_coefficients
	sub	r3, fp, #164
	mov	r2, #80
	mov	r1, r3
	ldr	r0, [fp, #-1248]
	bl	memcpy
	sub	r3, fp, #468
	mov	r2, #80
	mov	r1, r3
	ldr	r0, [fp, #-1252]
	bl	memcpy
	sub	r3, fp, #924
	ldr	r1, [fp, #-1256]
	mov	r0, r3
	bl	fsquare
	sub	r3, fp, #772
	ldr	r1, [fp, #-1260]
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #772
	sub	r3, fp, #924
	mov	r1, r3
	ldr	r0, [fp, #-1240]
	bl	fproduct
	ldr	r0, [fp, #-1240]
	bl	freduce_degree
	ldr	r0, [fp, #-1240]
	bl	freduce_coefficients
	sub	r2, fp, #924
	sub	r3, fp, #772
	mov	r1, r2
	mov	r0, r3
	bl	fdifference
	sub	r3, fp, #1072
	sub	r3, r3, #4
	add	r3, r3, #80
	mov	r2, #72
	mov	r1, #0
	mov	r0, r3
	bl	memset
	sub	r1, fp, #772
	sub	r0, fp, #1072
	sub	r0, r0, #4
	ldr	r2, .L40+4
	mov	r3, #0
	bl	fscalar_product
	sub	r3, fp, #1072
	sub	r3, r3, #4
	mov	r0, r3
	bl	freduce_coefficients
	sub	r2, fp, #924
	sub	r3, fp, #1072
	sub	r3, r3, #4
	mov	r1, r2
	mov	r0, r3
	bl	fsum
	sub	r2, fp, #1072
	sub	r2, r2, #4
	sub	r3, fp, #772
	mov	r1, r3
	ldr	r0, [fp, #-1244]
	bl	fproduct
	ldr	r0, [fp, #-1244]
	bl	freduce_degree
	ldr	r0, [fp, #-1244]
	bl	freduce_coefficients
	nop
	ldr	r3, .L40
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L39
	bl	__stack_chk_fail
.L39:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L41:
	.align	2
.L40:
	.word	.LC2
	.word	121665
	.size	fmonty, .-fmonty
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	swap_conditional, %function
swap_conditional:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #36
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-36]
	str	r3, [fp, #-32]
	ldr	r3, [fp, #-36]
	rsb	r3, r3, #0
	str	r3, [fp, #-12]
	mov	r3, #0
	str	r3, [fp, #-16]
	b	.L43
.L44:
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	mov	r1, r2
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-28]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	mov	r3, r2
	eor	r3, r3, r1
	ldr	r2, [fp, #-12]
	and	r3, r3, r2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-8]
	eor	r3, r3, r2
	ldr	r2, [fp, #-16]
	lsl	r2, r2, #3
	ldr	r1, [fp, #-24]
	add	r1, r1, r2
	mov	r2, r3
	asr	r3, r2, #31
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #3
	ldr	r2, [fp, #-28]
	add	r3, r2, r3
	ldmia	r3, {r2-r3}
	ldr	r3, [fp, #-8]
	eor	r3, r3, r2
	ldr	r2, [fp, #-16]
	lsl	r2, r2, #3
	ldr	r1, [fp, #-28]
	add	r1, r1, r2
	mov	r2, r3
	asr	r3, r2, #31
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
.L43:
	ldr	r3, [fp, #-16]
	cmp	r3, #9
	bls	.L44
	nop
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	swap_conditional, .-swap_conditional
	.section	.rodata
	.align	2
.LC3:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	cmult, %function
cmult:
	@ args = 0, pretend = 0, frame = 1296
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #1312
	sub	sp, sp, #8
	str	r0, [fp, #-1288]
	str	r1, [fp, #-1292]
	str	r2, [fp, #-1296]
	str	r3, [fp, #-1300]
	ldr	r3, .L51
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	sub	r3, fp, #1216
	sub	r3, r3, #4
	sub	r3, r3, #8
	mov	r2, #152
	mov	r1, #0
	mov	r0, r3
	bl	memset
	sub	r3, fp, #1072
	sub	r3, r3, #4
	mov	r2, #152
	mov	r1, #0
	mov	r0, r3
	bl	memset
	mov	r2, #1
	mov	r3, #0
	str	r2, [fp, #-1076]
	str	r3, [fp, #-1072]
	sub	r3, fp, #924
	mov	r2, #152
	mov	r1, #0
	mov	r0, r3
	bl	memset
	mov	r2, #1
	mov	r3, #0
	str	r2, [fp, #-924]
	str	r3, [fp, #-920]
	sub	r3, fp, #772
	mov	r2, #152
	mov	r1, #0
	mov	r0, r3
	bl	memset
	sub	r3, fp, #1216
	sub	r3, r3, #4
	sub	r3, r3, #8
	str	r3, [fp, #-1280]
	sub	r3, fp, #1072
	sub	r3, r3, #4
	str	r3, [fp, #-1276]
	sub	r3, fp, #924
	str	r3, [fp, #-1272]
	sub	r3, fp, #772
	str	r3, [fp, #-1268]
	sub	r3, fp, #620
	mov	r2, #152
	mov	r1, #0
	mov	r0, r3
	bl	memset
	sub	r3, fp, #468
	mov	r2, #152
	mov	r1, #0
	mov	r0, r3
	bl	memset
	mov	r2, #1
	mov	r3, #0
	str	r2, [fp, #-468]
	str	r3, [fp, #-464]
	sub	r3, fp, #316
	mov	r2, #152
	mov	r1, #0
	mov	r0, r3
	bl	memset
	sub	r3, fp, #164
	mov	r2, #152
	mov	r1, #0
	mov	r0, r3
	bl	memset
	mov	r2, #1
	mov	r3, #0
	str	r2, [fp, #-164]
	str	r3, [fp, #-160]
	sub	r3, fp, #620
	str	r3, [fp, #-1264]
	sub	r3, fp, #468
	str	r3, [fp, #-1260]
	sub	r3, fp, #316
	str	r3, [fp, #-1256]
	sub	r3, fp, #164
	str	r3, [fp, #-1252]
	mov	r2, #80
	ldr	r1, [fp, #-1300]
	ldr	r0, [fp, #-1280]
	bl	memcpy
	mov	r3, #0
	str	r3, [fp, #-1248]
	b	.L46
.L49:
	ldr	r3, [fp, #-1248]
	rsb	r3, r3, #31
	ldr	r2, [fp, #-1296]
	add	r3, r2, r3
	ldrb	r3, [r3]
	strb	r3, [fp, #-1281]
	mov	r3, #0
	str	r3, [fp, #-1244]
	b	.L47
.L48:
	ldrb	r3, [fp, #-1281]	@ zero_extendqisi2
	lsr	r3, r3, #7
	and	r3, r3, #255
	and	r2, r3, #255
	mov	r3, #0
	str	r2, [fp, #-1236]
	str	r3, [fp, #-1232]
	ldr	r2, [fp, #-1236]
	ldr	r3, [fp, #-1232]
	ldr	r1, [fp, #-1280]
	ldr	r0, [fp, #-1272]
	bl	swap_conditional
	ldr	r2, [fp, #-1236]
	ldr	r3, [fp, #-1232]
	ldr	r1, [fp, #-1276]
	ldr	r0, [fp, #-1268]
	bl	swap_conditional
	ldr	r3, [fp, #-1300]
	str	r3, [sp, #16]
	ldr	r3, [fp, #-1276]
	str	r3, [sp, #12]
	ldr	r3, [fp, #-1280]
	str	r3, [sp, #8]
	ldr	r3, [fp, #-1268]
	str	r3, [sp, #4]
	ldr	r3, [fp, #-1272]
	str	r3, [sp]
	ldr	r3, [fp, #-1260]
	ldr	r2, [fp, #-1264]
	ldr	r1, [fp, #-1252]
	ldr	r0, [fp, #-1256]
	bl	fmonty
	ldr	r2, [fp, #-1236]
	ldr	r3, [fp, #-1232]
	ldr	r1, [fp, #-1264]
	ldr	r0, [fp, #-1256]
	bl	swap_conditional
	ldr	r2, [fp, #-1236]
	ldr	r3, [fp, #-1232]
	ldr	r1, [fp, #-1260]
	ldr	r0, [fp, #-1252]
	bl	swap_conditional
	ldr	r3, [fp, #-1272]
	str	r3, [fp, #-1240]
	ldr	r3, [fp, #-1256]
	str	r3, [fp, #-1272]
	ldr	r3, [fp, #-1240]
	str	r3, [fp, #-1256]
	ldr	r3, [fp, #-1268]
	str	r3, [fp, #-1240]
	ldr	r3, [fp, #-1252]
	str	r3, [fp, #-1268]
	ldr	r3, [fp, #-1240]
	str	r3, [fp, #-1252]
	ldr	r3, [fp, #-1280]
	str	r3, [fp, #-1240]
	ldr	r3, [fp, #-1264]
	str	r3, [fp, #-1280]
	ldr	r3, [fp, #-1240]
	str	r3, [fp, #-1264]
	ldr	r3, [fp, #-1276]
	str	r3, [fp, #-1240]
	ldr	r3, [fp, #-1260]
	str	r3, [fp, #-1276]
	ldr	r3, [fp, #-1240]
	str	r3, [fp, #-1260]
	ldrb	r3, [fp, #-1281]
	lsl	r3, r3, #1
	strb	r3, [fp, #-1281]
	ldr	r3, [fp, #-1244]
	add	r3, r3, #1
	str	r3, [fp, #-1244]
.L47:
	ldr	r3, [fp, #-1244]
	cmp	r3, #7
	bls	.L48
	ldr	r3, [fp, #-1248]
	add	r3, r3, #1
	str	r3, [fp, #-1248]
.L46:
	ldr	r3, [fp, #-1248]
	cmp	r3, #31
	bls	.L49
	mov	r2, #80
	ldr	r1, [fp, #-1272]
	ldr	r0, [fp, #-1288]
	bl	memcpy
	mov	r2, #80
	ldr	r1, [fp, #-1268]
	ldr	r0, [fp, #-1292]
	bl	memcpy
	nop
	ldr	r3, .L51
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L50
	bl	__stack_chk_fail
.L50:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L52:
	.align	2
.L51:
	.word	.LC3
	.size	cmult, .-cmult
	.section	.rodata
	.align	2
.LC4:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	crecip, %function
crecip:
	@ args = 0, pretend = 0, frame = 824
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #824
	str	r0, [fp, #-824]
	str	r1, [fp, #-828]
	ldr	r3, .L67
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	sub	r3, fp, #812
	ldr	r1, [fp, #-828]
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #812
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r1, fp, #172
	sub	r3, fp, #732
	ldr	r2, [fp, #-828]
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #812
	sub	r1, fp, #732
	sub	r3, fp, #652
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #652
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #732
	sub	r1, fp, #172
	sub	r3, fp, #572
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #572
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #572
	sub	r1, fp, #172
	sub	r3, fp, #492
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #492
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	mov	r3, #2
	str	r3, [fp, #-816]
	b	.L54
.L55:
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	ldr	r3, [fp, #-816]
	add	r3, r3, #2
	str	r3, [fp, #-816]
.L54:
	ldr	r3, [fp, #-816]
	cmp	r3, #9
	ble	.L55
	sub	r2, fp, #492
	sub	r1, fp, #92
	sub	r3, fp, #412
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #412
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	mov	r3, #2
	str	r3, [fp, #-816]
	b	.L56
.L57:
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	ldr	r3, [fp, #-816]
	add	r3, r3, #2
	str	r3, [fp, #-816]
.L56:
	ldr	r3, [fp, #-816]
	cmp	r3, #19
	ble	.L57
	sub	r2, fp, #412
	sub	r1, fp, #92
	sub	r3, fp, #172
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	mov	r3, #2
	str	r3, [fp, #-816]
	b	.L58
.L59:
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	ldr	r3, [fp, #-816]
	add	r3, r3, #2
	str	r3, [fp, #-816]
.L58:
	ldr	r3, [fp, #-816]
	cmp	r3, #9
	ble	.L59
	sub	r2, fp, #492
	sub	r1, fp, #172
	sub	r3, fp, #332
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #332
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	mov	r3, #2
	str	r3, [fp, #-816]
	b	.L60
.L61:
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	ldr	r3, [fp, #-816]
	add	r3, r3, #2
	str	r3, [fp, #-816]
.L60:
	ldr	r3, [fp, #-816]
	cmp	r3, #49
	ble	.L61
	sub	r2, fp, #332
	sub	r1, fp, #92
	sub	r3, fp, #252
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #252
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	mov	r3, #2
	str	r3, [fp, #-816]
	b	.L62
.L63:
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	ldr	r3, [fp, #-816]
	add	r3, r3, #2
	str	r3, [fp, #-816]
.L62:
	ldr	r3, [fp, #-816]
	cmp	r3, #99
	ble	.L63
	sub	r2, fp, #252
	sub	r1, fp, #172
	sub	r3, fp, #92
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	mov	r3, #2
	str	r3, [fp, #-816]
	b	.L64
.L65:
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	ldr	r3, [fp, #-816]
	add	r3, r3, #2
	str	r3, [fp, #-816]
.L64:
	ldr	r3, [fp, #-816]
	cmp	r3, #49
	ble	.L65
	sub	r2, fp, #332
	sub	r1, fp, #92
	sub	r3, fp, #172
	mov	r0, r3
	bl	fmul
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #92
	sub	r3, fp, #172
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #172
	sub	r3, fp, #92
	mov	r1, r2
	mov	r0, r3
	bl	fsquare
	sub	r2, fp, #652
	sub	r3, fp, #92
	mov	r1, r3
	ldr	r0, [fp, #-824]
	bl	fmul
	nop
	ldr	r3, .L67
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L66
	bl	__stack_chk_fail
.L66:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L68:
	.align	2
.L67:
	.word	.LC4
	.size	crecip, .-crecip
	.section	.rodata
	.align	2
.LC5:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	curve25519_donna
	.syntax unified
	.arm
	.fpu softvfp
	.type	curve25519_donna, %function
curve25519_donna:
	@ args = 0, pretend = 0, frame = 392
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #392
	str	r0, [fp, #-384]
	str	r1, [fp, #-388]
	str	r2, [fp, #-392]
	ldr	r3, .L74
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	mov	r3, #0
	str	r3, [fp, #-376]
	b	.L70
.L71:
	ldr	r3, [fp, #-376]
	ldr	r2, [fp, #-388]
	add	r3, r2, r3
	ldrb	r1, [r3]	@ zero_extendqisi2
	sub	r2, fp, #40
	ldr	r3, [fp, #-376]
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3]
	ldr	r3, [fp, #-376]
	add	r3, r3, #1
	str	r3, [fp, #-376]
.L70:
	ldr	r3, [fp, #-376]
	cmp	r3, #31
	ble	.L71
	ldrb	r3, [fp, #-40]	@ zero_extendqisi2
	bic	r3, r3, #7
	and	r3, r3, #255
	strb	r3, [fp, #-40]
	ldrb	r3, [fp, #-9]	@ zero_extendqisi2
	and	r3, r3, #127
	and	r3, r3, #255
	strb	r3, [fp, #-9]
	ldrb	r3, [fp, #-9]	@ zero_extendqisi2
	orr	r3, r3, #64
	and	r3, r3, #255
	strb	r3, [fp, #-9]
	sub	r3, fp, #372
	ldr	r1, [fp, #-392]
	mov	r0, r3
	bl	fexpand
	sub	r3, fp, #372
	sub	r2, fp, #40
	sub	r1, fp, #132
	sub	r0, fp, #292
	bl	cmult
	sub	r2, fp, #132
	sub	r3, fp, #212
	mov	r1, r2
	mov	r0, r3
	bl	crecip
	sub	r2, fp, #212
	sub	r1, fp, #292
	sub	r3, fp, #132
	mov	r0, r3
	bl	fmul
	sub	r3, fp, #132
	mov	r0, r3
	bl	freduce_coefficients
	sub	r3, fp, #132
	mov	r1, r3
	ldr	r0, [fp, #-384]
	bl	fcontract
	mov	r3, #0
	ldr	r2, .L74
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L73
	bl	__stack_chk_fail
.L73:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L75:
	.align	2
.L74:
	.word	.LC5
	.size	curve25519_donna, .-curve25519_donna
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
