	.file	"115766179.c"
	.intel_syntax noprefix
	.text
	.globl	avoid_zero
	.type	avoid_zero, @function
avoid_zero:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	cmp	DWORD PTR -4[rbp], 0
	jne	.L3
	call	abort@PLT
.L3:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	avoid_zero, .-avoid_zero
	.globl	Id_MCDC_104
	.bss
	.align 4
	.type	Id_MCDC_104, @object
	.size	Id_MCDC_104, 4
Id_MCDC_104:
	.zero	4
	.globl	Id_MCDC_105
	.align 2
	.type	Id_MCDC_105, @object
	.size	Id_MCDC_105, 2
Id_MCDC_105:
	.zero	2
	.globl	Id_MCDC_106
	.align 2
	.type	Id_MCDC_106, @object
	.size	Id_MCDC_106, 2
Id_MCDC_106:
	.zero	2
	.globl	Id_MCDC_107
	.align 8
	.type	Id_MCDC_107, @object
	.size	Id_MCDC_107, 8
Id_MCDC_107:
	.zero	8
	.globl	Id_MCDC_108
	.align 8
	.type	Id_MCDC_108, @object
	.size	Id_MCDC_108, 8
Id_MCDC_108:
	.zero	8
	.globl	Id_MCDC_109
	.align 8
	.type	Id_MCDC_109, @object
	.size	Id_MCDC_109, 8
Id_MCDC_109:
	.zero	8
	.globl	Id_MCDC_110
	.align 8
	.type	Id_MCDC_110, @object
	.size	Id_MCDC_110, 8
Id_MCDC_110:
	.zero	8
	.globl	Id_MCDC_111
	.align 8
	.type	Id_MCDC_111, @object
	.size	Id_MCDC_111, 8
Id_MCDC_111:
	.zero	8
	.globl	Id_MCDC_112
	.align 16
	.type	Id_MCDC_112, @object
	.size	Id_MCDC_112, 16
Id_MCDC_112:
	.zero	16
	.globl	Id_MCDC_113
	.align 32
	.type	Id_MCDC_113, @object
	.size	Id_MCDC_113, 40
Id_MCDC_113:
	.zero	40
	.globl	Id_MCDC_114
	.align 4
	.type	Id_MCDC_114, @object
	.size	Id_MCDC_114, 4
Id_MCDC_114:
	.zero	4
	.section	.rodata
.LC0:
	.string	"rsvd"
.LC1:
	.string	"wo"
	.text
	.globl	Id_MCDC_89
	.type	Id_MCDC_89, @function
Id_MCDC_89:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	eax, edi
	mov	QWORD PTR -32[rbp], rdx
	mov	QWORD PTR -40[rbp], rcx
	mov	QWORD PTR -48[rbp], r8
	mov	QWORD PTR -56[rbp], r9
	mov	edx, DWORD PTR 16[rbp]
	mov	WORD PTR -20[rbp], ax
	mov	eax, esi
	mov	BYTE PTR -24[rbp], al
	mov	eax, edx
	mov	BYTE PTR -60[rbp], al
	mov	DWORD PTR -12[rbp], -2147483648
	mov	rax, QWORD PTR Id_MCDC_111[rip]
	mov	QWORD PTR -8[rbp], rax
	cmp	QWORD PTR -8[rbp], 0
	jne	.L5
	mov	eax, 134217763
	jmp	.L6
.L5:
	movzx	eax, WORD PTR Id_MCDC_105[rip]
	cmp	WORD PTR -20[rbp], ax
	jbe	.L7
	cmp	WORD PTR -20[rbp], 6655
	jbe	.L8
.L7:
	movzx	eax, WORD PTR Id_MCDC_106[rip]
	cmp	WORD PTR -20[rbp], ax
	jbe	.L9
	cmp	WORD PTR -20[rbp], 5631
	ja	.L9
.L8:
	cmp	BYTE PTR -24[rbp], 1
	jne	.L9
	mov	eax, 0
	jmp	.L6
.L9:
	movzx	eax, WORD PTR -20[rbp]
	and	eax, 65280
	cmp	eax, 6912
	je	.L10
	cmp	eax, 6912
	jg	.L11
	cmp	eax, 6656
	je	.L10
	cmp	eax, 6656
	jg	.L11
	cmp	eax, 6400
	je	.L12
	cmp	eax, 6400
	jg	.L11
	cmp	eax, 6144
	je	.L12
	cmp	eax, 6144
	jg	.L11
	cmp	eax, 5888
	je	.L13
	cmp	eax, 5888
	jg	.L11
	cmp	eax, 5632
	je	.L13
	cmp	eax, 5632
	jg	.L11
	cmp	eax, 5120
	je	.L14
	cmp	eax, 5376
	je	.L14
	jmp	.L11
.L12:
	mov	rax, QWORD PTR Id_MCDC_107[rip]
	mov	QWORD PTR -8[rbp], rax
	jmp	.L15
.L10:
	mov	rax, QWORD PTR Id_MCDC_108[rip]
	mov	QWORD PTR -8[rbp], rax
	jmp	.L15
.L14:
	mov	rax, QWORD PTR Id_MCDC_109[rip]
	mov	QWORD PTR -8[rbp], rax
	jmp	.L15
.L13:
	mov	rax, QWORD PTR Id_MCDC_110[rip]
	mov	QWORD PTR -8[rbp], rax
	jmp	.L15
.L11:
	mov	rax, QWORD PTR Id_MCDC_111[rip]
	mov	QWORD PTR -8[rbp], rax
	nop
.L15:
	jmp	.L16
.L17:
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	QWORD PTR -8[rbp], rax
	cmp	QWORD PTR -8[rbp], 0
	jne	.L16
	mov	eax, 100794368
	jmp	.L6
.L16:
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR [rax]
	movzx	eax, WORD PTR [rax]
	cmp	WORD PTR -20[rbp], ax
	jne	.L17
	cmp	BYTE PTR -24[rbp], 0
	je	.L18
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR [rax]
	movzx	eax, BYTE PTR 3[rax]
	cmp	BYTE PTR -24[rbp], al
	jnb	.L19
.L18:
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR [rax]
	mov	rcx, QWORD PTR 8[rax]
	movzx	edx, BYTE PTR -24[rbp]
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	add	rax, 8
	lea	rsi, .LC0[rip]
	mov	rdi, rax
	call	strcmp@PLT
	test	eax, eax
	je	.L19
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR [rax]
	mov	rcx, QWORD PTR 8[rax]
	movzx	edx, BYTE PTR -24[rbp]
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	add	rax, 8
	lea	rsi, .LC1[rip]
	mov	rdi, rax
	call	strcmp@PLT
	test	eax, eax
	jne	.L21
	mov	eax, 100728833
	jmp	.L6
.L19:
	mov	eax, 101253137
	jmp	.L6
.L21:
	mov	eax, 0
.L6:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	Id_MCDC_89, .-Id_MCDC_89
	.type	Id_MCDC_92, @function
Id_MCDC_92:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	DWORD PTR -16[rbp], 0
	mov	DWORD PTR -12[rbp], 0
	mov	DWORD PTR -8[rbp], 1
	mov	DWORD PTR -4[rbp], 0
	mov	eax, DWORD PTR -20[rbp]
	cmp	eax, DWORD PTR -24[rbp]
	jbe	.L23
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -24[rbp]
	mov	DWORD PTR -12[rbp], eax
	jmp	.L27
.L23:
	mov	eax, DWORD PTR -20[rbp]
	cmp	eax, DWORD PTR -24[rbp]
	jnb	.L25
	mov	eax, DWORD PTR -24[rbp]
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -12[rbp], eax
	jmp	.L27
.L25:
	mov	eax, DWORD PTR -20[rbp]
	jmp	.L26
.L28:
	cmp	DWORD PTR -12[rbp], 0
	setne	al
	movzx	eax, al
	mov	edi, eax
	call	avoid_zero
	mov	eax, DWORD PTR -16[rbp]
	mov	edx, 0
	div	DWORD PTR -12[rbp]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	imul	eax, DWORD PTR -12[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -16[rbp]
	sub	eax, edx
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -8[rbp]
	mov	DWORD PTR -12[rbp], eax
.L27:
	cmp	DWORD PTR -8[rbp], 0
	jne	.L28
	mov	eax, DWORD PTR -16[rbp]
.L26:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	Id_MCDC_92, .-Id_MCDC_92
	.type	Id_MCDC_95, @function
Id_MCDC_95:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	DWORD PTR -20[rbp], edi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -4[rbp], 0
	mov	DWORD PTR -8[rbp], 0
	cmp	DWORD PTR -20[rbp], 1
	ja	.L30
	mov	eax, 0
	jmp	.L31
.L30:
	cmp	DWORD PTR -20[rbp], 2
	je	.L32
	mov	rax, QWORD PTR -32[rbp]
	lea	rdx, 1[rax]
	mov	eax, DWORD PTR -20[rbp]
	sub	eax, 1
	mov	rsi, rdx
	mov	edi, eax
	call	Id_MCDC_95
	mov	DWORD PTR -8[rbp], eax
	jmp	.L33
.L32:
	mov	rax, QWORD PTR -32[rbp]
	add	rax, 1
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	mov	DWORD PTR -8[rbp], eax
.L33:
	mov	rax, QWORD PTR -32[rbp]
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	mov	edx, DWORD PTR -8[rbp]
	mov	esi, edx
	mov	edi, eax
	call	Id_MCDC_92
	mov	DWORD PTR -4[rbp], eax
	cmp	DWORD PTR -4[rbp], 0
	setne	al
	movzx	eax, al
	mov	edi, eax
	call	avoid_zero
	mov	edi, 1
	call	__VERIFIER_assert
	mov	rax, QWORD PTR -32[rbp]
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	imul	eax, DWORD PTR -8[rbp]
	mov	edx, 0
	div	DWORD PTR -4[rbp]
.L31:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	Id_MCDC_95, .-Id_MCDC_95
	.globl	Id_MCDC_96
	.type	Id_MCDC_96, @function
Id_MCDC_96:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	eax, edi
	mov	QWORD PTR -32[rbp], rdx
	mov	QWORD PTR -40[rbp], rcx
	mov	QWORD PTR -48[rbp], r8
	mov	QWORD PTR -56[rbp], r9
	mov	WORD PTR -20[rbp], ax
	mov	eax, esi
	mov	BYTE PTR -24[rbp], al
	mov	rax, QWORD PTR Id_MCDC_111[rip]
	mov	QWORD PTR -8[rbp], rax
	cmp	QWORD PTR -8[rbp], 0
	jne	.L37
	mov	eax, 134217763
	jmp	.L36
.L38:
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	QWORD PTR -8[rbp], rax
	cmp	QWORD PTR -8[rbp], 0
	jne	.L37
	mov	eax, 100794368
	jmp	.L36
.L37:
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR [rax]
	movzx	eax, WORD PTR [rax]
	cmp	WORD PTR -20[rbp], ax
	jne	.L38
	cmp	BYTE PTR -24[rbp], 0
	je	.L39
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR [rax]
	movzx	eax, BYTE PTR 3[rax]
	cmp	BYTE PTR -24[rbp], al
	jnb	.L40
.L39:
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR [rax]
	mov	rcx, QWORD PTR 8[rax]
	movzx	edx, BYTE PTR -24[rbp]
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	add	rax, 8
	lea	rsi, .LC0[rip]
	mov	rdi, rax
	call	strcmp@PLT
	test	eax, eax
	je	.L40
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR [rax]
	mov	rcx, QWORD PTR 8[rax]
	movzx	edx, BYTE PTR -24[rbp]
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	add	rax, 8
	lea	rsi, .LC1[rip]
	mov	rdi, rax
	call	strcmp@PLT
	test	eax, eax
	jne	.L42
	mov	eax, 100728833
	jmp	.L36
.L40:
	mov	eax, 101253137
	jmp	.L36
.L42:
	mov	eax, 0
.L36:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	Id_MCDC_96, .-Id_MCDC_96
	.globl	Id_MCDC_97
	.type	Id_MCDC_97, @function
Id_MCDC_97:
.LFB5:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	DWORD PTR -52[rbp], 0
	mov	DWORD PTR -48[rbp], 0
	mov	DWORD PTR -44[rbp], 0
	mov	BYTE PTR -60[rbp], 0
	mov	BYTE PTR -61[rbp], 0
	mov	BYTE PTR -59[rbp], 0
	mov	BYTE PTR -58[rbp], 0
	mov	BYTE PTR -57[rbp], 0
	mov	DWORD PTR -36[rbp], 6144
	mov	BYTE PTR -61[rbp], 0
	jmp	.L44
.L45:
	movzx	eax, BYTE PTR -61[rbp]
	lea	edx, 6656[rax]
	movzx	eax, BYTE PTR -61[rbp]
	mov	ecx, edx
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, Id_MCDC_112[rip]
	mov	DWORD PTR [rdx+rax], ecx
	movzx	eax, BYTE PTR -61[rbp]
	add	eax, 1
	mov	BYTE PTR -61[rbp], al
.L44:
	cmp	BYTE PTR -61[rbp], 3
	jbe	.L45
	cmp	DWORD PTR -36[rbp], 6147
	ja	.L46
	mov	WORD PTR -56[rbp], 0
	jmp	.L47
.L56:
	mov	eax, DWORD PTR -36[rbp]
	mov	DWORD PTR -32[rbp], eax
	mov	eax, DWORD PTR -36[rbp]
	movzx	eax, ax
	lea	rdi, -52[rbp]
	lea	rsi, -40[rbp]
	lea	rcx, -48[rbp]
	lea	rdx, -44[rbp]
	sub	rsp, 8
	push	0
	mov	r9, rdi
	mov	r8, rsi
	mov	esi, 1
	mov	edi, eax
	call	Id_MCDC_89
	add	rsp, 16
	test	eax, eax
	je	.L48
	mov	eax, 65535
	jmp	.L57
.L48:
	mov	eax, DWORD PTR -36[rbp]
	movzx	eax, ax
	lea	rdi, -52[rbp]
	lea	rsi, -40[rbp]
	lea	rcx, -48[rbp]
	lea	rdx, -44[rbp]
	sub	rsp, 8
	push	0
	mov	r9, rdi
	mov	r8, rsi
	mov	esi, 2
	mov	edi, eax
	call	Id_MCDC_89
	add	rsp, 16
	test	eax, eax
	je	.L50
	mov	eax, 65535
	jmp	.L57
.L50:
	mov	edx, DWORD PTR -52[rbp]
	mov	rsi, QWORD PTR Id_MCDC_113[rip+24]
	movzx	eax, WORD PTR -56[rbp]
	mov	ecx, edx
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	sal	rax, 3
	add	rax, rsi
	add	rax, 9
	mov	BYTE PTR [rax], cl
	movzx	eax, WORD PTR -56[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, Id_MCDC_112[rip]
	mov	eax, DWORD PTR [rdx+rax]
	mov	DWORD PTR -36[rbp], eax
	mov	eax, DWORD PTR -36[rbp]
	movzx	eax, ax
	lea	rdi, -52[rbp]
	lea	rsi, -40[rbp]
	lea	rcx, -48[rbp]
	lea	rdx, -44[rbp]
	sub	rsp, 8
	push	0
	mov	r9, rdi
	mov	r8, rsi
	mov	esi, 0
	mov	edi, eax
	call	Id_MCDC_89
	add	rsp, 16
	test	eax, eax
	je	.L51
	mov	eax, 65535
	jmp	.L57
.L51:
	mov	eax, DWORD PTR -52[rbp]
	mov	BYTE PTR -60[rbp], al
	mov	BYTE PTR -61[rbp], 0
	jmp	.L52
.L55:
	movzx	eax, BYTE PTR -61[rbp]
	add	eax, 1
	movzx	esi, al
	mov	eax, DWORD PTR -36[rbp]
	movzx	eax, ax
	lea	r8, -52[rbp]
	lea	rdi, -40[rbp]
	lea	rcx, -48[rbp]
	lea	rdx, -44[rbp]
	sub	rsp, 8
	push	0
	mov	r9, r8
	mov	r8, rdi
	mov	edi, eax
	call	Id_MCDC_89
	add	rsp, 16
	test	eax, eax
	je	.L53
	mov	eax, 65535
	jmp	.L57
.L53:
	mov	eax, DWORD PTR -52[rbp]
	mov	DWORD PTR -28[rbp], eax
	shr	DWORD PTR -28[rbp], 16
	mov	eax, DWORD PTR -52[rbp]
	mov	DWORD PTR -24[rbp], eax
	mov	eax, DWORD PTR -24[rbp]
	mov	WORD PTR -54[rbp], ax
	shr	WORD PTR -54[rbp], 8
	movzx	eax, WORD PTR -54[rbp]
	mov	BYTE PTR -57[rbp], al
	movzx	esi, BYTE PTR -57[rbp]
	mov	eax, DWORD PTR -28[rbp]
	movzx	eax, ax
	lea	r8, -16[rbp]
	lea	rdi, -40[rbp]
	lea	rcx, -48[rbp]
	lea	rdx, -44[rbp]
	mov	r9, r8
	mov	r8, rdi
	mov	edi, eax
	call	Id_MCDC_96
	mov	DWORD PTR -20[rbp], eax
	cmp	DWORD PTR -20[rbp], 0
	je	.L54
	mov	eax, DWORD PTR -20[rbp]
	jmp	.L57
.L54:
	movzx	eax, BYTE PTR -61[rbp]
	add	eax, 1
	mov	BYTE PTR -61[rbp], al
.L52:
	movzx	eax, BYTE PTR -61[rbp]
	cmp	al, BYTE PTR -60[rbp]
	jb	.L55
	add	DWORD PTR -32[rbp], 1
	mov	eax, DWORD PTR -32[rbp]
	mov	DWORD PTR -36[rbp], eax
	movzx	eax, WORD PTR -56[rbp]
	add	eax, 1
	mov	WORD PTR -56[rbp], ax
.L47:
	cmp	WORD PTR -56[rbp], 3
	jbe	.L56
.L46:
	mov	eax, 0
.L57:
	mov	rdi, QWORD PTR -8[rbp]
	sub	rdi, QWORD PTR fs:40
	je	.L58
	call	__stack_chk_fail@PLT
.L58:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	Id_MCDC_97, .-Id_MCDC_97
	.globl	Id_MCDC_99
	.type	Id_MCDC_99, @function
Id_MCDC_99:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	DWORD PTR -12[rbp], 0
	mov	DWORD PTR -16[rbp], 0
	mov	edi, 372
	call	malloc@PLT
	mov	QWORD PTR Id_MCDC_113[rip+24], rax
	mov	eax, 0
	call	Id_MCDC_97
	mov	DWORD PTR -16[rbp], 0
	jmp	.L60
.L63:
	mov	rcx, QWORD PTR Id_MCDC_113[rip+24]
	mov	edx, DWORD PTR -16[rbp]
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	add	rax, 9
	movzx	eax, BYTE PTR [rax]
	cmp	al, -16
	ja	.L61
	mov	rcx, QWORD PTR Id_MCDC_113[rip+24]
	mov	edx, DWORD PTR -16[rbp]
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	add	rax, 9
	movzx	eax, BYTE PTR [rax]
	test	al, al
	je	.L61
	mov	rcx, QWORD PTR Id_MCDC_113[rip+24]
	mov	edx, DWORD PTR -16[rbp]
	mov	rax, rdx
	sal	rax, 3
	add	rax, rdx
	sal	rax, 3
	add	rax, rcx
	add	rax, 9
	movzx	eax, BYTE PTR [rax]
	mov	edx, eax
	mov	eax, DWORD PTR -16[rbp]
	mov	BYTE PTR -12[rbp+rax], dl
	jmp	.L62
.L61:
	mov	eax, DWORD PTR -16[rbp]
	mov	BYTE PTR -12[rbp+rax], 1
.L62:
	add	DWORD PTR -16[rbp], 1
.L60:
	cmp	DWORD PTR -16[rbp], 3
	jbe	.L63
	lea	rax, -12[rbp]
	mov	rsi, rax
	mov	edi, 4
	call	Id_MCDC_95
	mov	DWORD PTR Id_MCDC_114[rip], eax
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L65
	call	__stack_chk_fail@PLT
.L65:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	Id_MCDC_99, .-Id_MCDC_99
	.globl	Id_MCDC_100
	.type	Id_MCDC_100, @function
Id_MCDC_100:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, 0
	call	Id_MCDC_99
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	Id_MCDC_100, .-Id_MCDC_100
	.section	.rodata
.LC2:
	.string	"r"
.LC3:
	.string	"in.eds"
	.text
	.globl	main
	.type	main, @function
main:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	WORD PTR -12[rbp], 0
	mov	WORD PTR -10[rbp], 0
	lea	rsi, .LC2[rip]
	lea	rdi, .LC3[rip]
	call	fopen@PLT
	mov	QWORD PTR -8[rbp], rax
	cmp	QWORD PTR -8[rbp], 0
	jne	.L69
	mov	eax, 1
	jmp	.L70
.L69:
	mov	eax, 0
	call	Id_MCDC_100
	mov	eax, 0
.L70:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	main, .-main
	.globl	__VERIFIER_assert
	.type	__VERIFIER_assert, @function
__VERIFIER_assert:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	cmp	DWORD PTR -4[rbp], 0
	jne	.L75
	nop
.L73:
	mov	eax, 0
	call	__VERIFIER_error@PLT
.L75:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	__VERIFIER_assert, .-__VERIFIER_assert
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"115766179.c"
	.text
	.align	2
	.global	avoid_zero
	.syntax unified
	.arm
	.fpu softvfp
	.type	avoid_zero, %function
avoid_zero:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L3
	bl	abort
.L3:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	avoid_zero, .-avoid_zero
	.comm	Id_MCDC_104,4,4
	.comm	Id_MCDC_105,2,2
	.comm	Id_MCDC_106,2,2
	.comm	Id_MCDC_107,4,4
	.comm	Id_MCDC_108,4,4
	.comm	Id_MCDC_109,4,4
	.comm	Id_MCDC_110,4,4
	.comm	Id_MCDC_111,4,4
	.comm	Id_MCDC_112,16,4
	.comm	Id_MCDC_113,24,4
	.global	Id_MCDC_114
	.bss
	.align	2
	.type	Id_MCDC_114, %object
	.size	Id_MCDC_114, 4
Id_MCDC_114:
	.space	4
	.section	.rodata
	.align	2
.LC0:
	.ascii	"rsvd\000"
	.align	2
.LC1:
	.ascii	"wo\000"
	.text
	.align	2
	.global	Id_MCDC_89
	.syntax unified
	.arm
	.fpu softvfp
	.type	Id_MCDC_89, %function
Id_MCDC_89:
	@ args = 12, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r2, [fp, #-20]
	str	r3, [fp, #-24]
	mov	r3, r0	@ movhi
	strh	r3, [fp, #-14]	@ movhi
	mov	r3, r1
	strb	r3, [fp, #-15]
	mov	r3, #-2147483648
	str	r3, [fp, #-8]
	ldr	r3, .L22
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	bne	.L5
	ldr	r3, .L22+4
	b	.L6
.L5:
	ldr	r3, .L22+8
	ldrh	r3, [r3]
	ldrh	r2, [fp, #-14]
	cmp	r2, r3
	bls	.L7
	ldrh	r3, [fp, #-14]
	cmp	r3, #6656
	bcc	.L8
.L7:
	ldr	r3, .L22+12
	ldrh	r3, [r3]
	ldrh	r2, [fp, #-14]
	cmp	r2, r3
	bls	.L9
	ldrh	r3, [fp, #-14]
	cmp	r3, #5632
	bcs	.L9
.L8:
	ldrb	r3, [fp, #-15]	@ zero_extendqisi2
	cmp	r3, #1
	bne	.L9
	mov	r3, #0
	b	.L6
.L9:
	ldrh	r3, [fp, #-14]
	and	r3, r3, #65280
	cmp	r3, #6912
	beq	.L10
	cmp	r3, #6912
	bgt	.L11
	cmp	r3, #6656
	beq	.L10
	cmp	r3, #6656
	bgt	.L11
	cmp	r3, #6400
	beq	.L12
	cmp	r3, #6400
	bgt	.L11
	cmp	r3, #6144
	beq	.L12
	cmp	r3, #6144
	bgt	.L11
	cmp	r3, #5888
	beq	.L13
	cmp	r3, #5888
	bgt	.L11
	cmp	r3, #5632
	beq	.L13
	cmp	r3, #5632
	bgt	.L11
	cmp	r3, #5120
	beq	.L14
	cmp	r3, #5376
	beq	.L14
	b	.L11
.L12:
	ldr	r3, .L22+16
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	b	.L15
.L10:
	ldr	r3, .L22+20
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	b	.L15
.L14:
	ldr	r3, .L22+24
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	b	.L15
.L13:
	ldr	r3, .L22+28
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	b	.L15
.L11:
	ldr	r3, .L22
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	nop
.L15:
	b	.L16
.L17:
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L22+32
	b	.L6
.L16:
	ldr	r3, [fp, #-12]
	ldr	r3, [r3]
	ldrh	r3, [r3]
	ldrh	r2, [fp, #-14]
	cmp	r2, r3
	bne	.L17
	ldrb	r3, [fp, #-15]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
	ldr	r3, [fp, #-12]
	ldr	r3, [r3]
	ldrb	r3, [r3, #3]	@ zero_extendqisi2
	ldrb	r2, [fp, #-15]	@ zero_extendqisi2
	cmp	r2, r3
	bcs	.L19
.L18:
	ldr	r3, [fp, #-12]
	ldr	r3, [r3]
	ldr	r1, [r3, #4]
	ldrb	r2, [fp, #-15]	@ zero_extendqisi2
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	add	r3, r3, #8
	ldr	r1, .L22+36
	mov	r0, r3
	bl	strcmp
	mov	r3, r0
	cmp	r3, #0
	beq	.L19
	ldr	r3, [fp, #-12]
	ldr	r3, [r3]
	ldr	r1, [r3, #4]
	ldrb	r2, [fp, #-15]	@ zero_extendqisi2
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	add	r3, r3, #8
	ldr	r1, .L22+40
	mov	r0, r3
	bl	strcmp
	mov	r3, r0
	cmp	r3, #0
	bne	.L21
	ldr	r3, .L22+44
	b	.L6
.L19:
	ldr	r3, .L22+48
	b	.L6
.L21:
	mov	r3, #0
.L6:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L23:
	.align	2
.L22:
	.word	Id_MCDC_111
	.word	134217763
	.word	Id_MCDC_105
	.word	Id_MCDC_106
	.word	Id_MCDC_107
	.word	Id_MCDC_108
	.word	Id_MCDC_109
	.word	Id_MCDC_110
	.word	100794368
	.word	.LC0
	.word	.LC1
	.word	100728833
	.word	101253137
	.size	Id_MCDC_89, .-Id_MCDC_89
	.global	__aeabi_uidiv
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	Id_MCDC_92, %function
Id_MCDC_92:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	mov	r3, #0
	str	r3, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-16]
	mov	r3, #1
	str	r3, [fp, #-12]
	mov	r3, #0
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-28]
	cmp	r2, r3
	bls	.L25
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-28]
	str	r3, [fp, #-16]
	b	.L29
.L25:
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-28]
	cmp	r2, r3
	bcs	.L27
	ldr	r3, [fp, #-28]
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-16]
	b	.L29
.L27:
	ldr	r3, [fp, #-24]
	b	.L28
.L30:
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	bl	avoid_zero
	ldr	r1, [fp, #-16]
	ldr	r0, [fp, #-20]
	bl	__aeabi_uidiv
	mov	r3, r0
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r2, [fp, #-16]
	mul	r3, r2, r3
	ldr	r2, [fp, #-20]
	sub	r3, r2, r3
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-16]
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-12]
	str	r3, [fp, #-16]
.L29:
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	bne	.L30
	ldr	r3, [fp, #-20]
.L28:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	Id_MCDC_92, .-Id_MCDC_92
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	Id_MCDC_95, %function
Id_MCDC_95:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-8]
	mov	r3, #0
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-16]
	cmp	r3, #1
	bhi	.L32
	mov	r3, #0
	b	.L33
.L32:
	ldr	r3, [fp, #-16]
	cmp	r3, #2
	beq	.L34
	ldr	r3, [fp, #-16]
	sub	r2, r3, #1
	ldr	r3, [fp, #-20]
	add	r3, r3, #1
	mov	r1, r3
	mov	r0, r2
	bl	Id_MCDC_95
	str	r0, [fp, #-12]
	b	.L35
.L34:
	ldr	r3, [fp, #-20]
	add	r3, r3, #1
	ldrb	r3, [r3]	@ zero_extendqisi2
	str	r3, [fp, #-12]
.L35:
	ldr	r3, [fp, #-20]
	ldrb	r3, [r3]	@ zero_extendqisi2
	ldr	r1, [fp, #-12]
	mov	r0, r3
	bl	Id_MCDC_92
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	bl	avoid_zero
	mov	r0, #1
	bl	__VERIFIER_assert
	ldr	r3, [fp, #-20]
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r2, r3
	ldr	r3, [fp, #-12]
	mul	r3, r2, r3
	ldr	r1, [fp, #-8]
	mov	r0, r3
	bl	__aeabi_uidiv
	mov	r3, r0
.L33:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	Id_MCDC_95, .-Id_MCDC_95
	.align	2
	.global	Id_MCDC_96
	.syntax unified
	.arm
	.fpu softvfp
	.type	Id_MCDC_96, %function
Id_MCDC_96:
	@ args = 8, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r2, [fp, #-20]
	str	r3, [fp, #-24]
	mov	r3, r0	@ movhi
	strh	r3, [fp, #-14]	@ movhi
	mov	r3, r1
	strb	r3, [fp, #-15]
	ldr	r3, .L45
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L39
	ldr	r3, .L45+4
	b	.L38
.L40:
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L39
	ldr	r3, .L45+8
	b	.L38
.L39:
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	ldrh	r3, [r3]
	ldrh	r2, [fp, #-14]
	cmp	r2, r3
	bne	.L40
	ldrb	r3, [fp, #-15]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L41
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	ldrb	r3, [r3, #3]	@ zero_extendqisi2
	ldrb	r2, [fp, #-15]	@ zero_extendqisi2
	cmp	r2, r3
	bcs	.L42
.L41:
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	ldr	r1, [r3, #4]
	ldrb	r2, [fp, #-15]	@ zero_extendqisi2
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	add	r3, r3, #8
	ldr	r1, .L45+12
	mov	r0, r3
	bl	strcmp
	mov	r3, r0
	cmp	r3, #0
	beq	.L42
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	ldr	r1, [r3, #4]
	ldrb	r2, [fp, #-15]	@ zero_extendqisi2
	mov	r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	add	r3, r3, #8
	ldr	r1, .L45+16
	mov	r0, r3
	bl	strcmp
	mov	r3, r0
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L45+20
	b	.L38
.L42:
	ldr	r3, .L45+24
	b	.L38
.L44:
	mov	r3, #0
.L38:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L46:
	.align	2
.L45:
	.word	Id_MCDC_111
	.word	134217763
	.word	100794368
	.word	.LC0
	.word	.LC1
	.word	100728833
	.word	101253137
	.size	Id_MCDC_96, .-Id_MCDC_96
	.section	.rodata
	.align	2
.LC2:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	Id_MCDC_97
	.syntax unified
	.arm
	.fpu softvfp
	.type	Id_MCDC_97, %function
Id_MCDC_97:
	@ args = 0, pretend = 0, frame = 56
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #72
	ldr	r3, .L63
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	mov	r3, #0
	str	r3, [fp, #-48]
	mov	r3, #0
	str	r3, [fp, #-44]
	mov	r3, #0
	str	r3, [fp, #-40]
	mov	r3, #0
	strb	r3, [fp, #-56]
	mov	r3, #0
	strb	r3, [fp, #-57]
	mov	r3, #0
	strb	r3, [fp, #-55]
	mov	r3, #0
	strb	r3, [fp, #-54]
	mov	r3, #0
	strb	r3, [fp, #-53]
	mov	r3, #6144
	str	r3, [fp, #-28]
	mov	r3, #0
	strb	r3, [fp, #-57]
	b	.L48
.L49:
	ldrb	r3, [fp, #-57]	@ zero_extendqisi2
	add	r2, r3, #6656
	ldrb	r3, [fp, #-57]	@ zero_extendqisi2
	mov	r1, r2
	ldr	r2, .L63+4
	str	r1, [r2, r3, lsl #2]
	ldrb	r3, [fp, #-57]	@ zero_extendqisi2
	add	r3, r3, #1
	strb	r3, [fp, #-57]
.L48:
	ldrb	r3, [fp, #-57]	@ zero_extendqisi2
	cmp	r3, #3
	bls	.L49
	ldr	r3, [fp, #-28]
	ldr	r2, .L63+8
	cmp	r3, r2
	bhi	.L50
	mov	r3, #0
	strh	r3, [fp, #-52]	@ movhi
	b	.L51
.L60:
	ldr	r3, [fp, #-28]
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-28]
	lsl	r3, r3, #16
	lsr	r0, r3, #16
	sub	r1, fp, #44
	sub	r2, fp, #40
	mov	r3, #0
	str	r3, [sp, #8]
	sub	r3, fp, #48
	str	r3, [sp, #4]
	sub	r3, fp, #36
	str	r3, [sp]
	mov	r3, r1
	mov	r1, #1
	bl	Id_MCDC_89
	mov	r3, r0
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L63+12
	b	.L61
.L52:
	ldr	r3, [fp, #-28]
	lsl	r3, r3, #16
	lsr	r0, r3, #16
	sub	r1, fp, #44
	sub	r2, fp, #40
	mov	r3, #0
	str	r3, [sp, #8]
	sub	r3, fp, #48
	str	r3, [sp, #4]
	sub	r3, fp, #36
	str	r3, [sp]
	mov	r3, r1
	mov	r1, #2
	bl	Id_MCDC_89
	mov	r3, r0
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L63+12
	b	.L61
.L54:
	ldr	r3, [fp, #-48]
	ldr	r2, .L63+16
	ldr	r1, [r2, #16]
	ldrh	r2, [fp, #-52]
	and	r0, r3, #255
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r1, r3
	add	r3, r3, #5
	mov	r2, r0
	strb	r2, [r3]
	ldrh	r3, [fp, #-52]
	ldr	r2, .L63+4
	ldr	r3, [r2, r3, lsl #2]
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-28]
	lsl	r3, r3, #16
	lsr	r0, r3, #16
	sub	r1, fp, #44
	sub	r2, fp, #40
	mov	r3, #0
	str	r3, [sp, #8]
	sub	r3, fp, #48
	str	r3, [sp, #4]
	sub	r3, fp, #36
	str	r3, [sp]
	mov	r3, r1
	mov	r1, #0
	bl	Id_MCDC_89
	mov	r3, r0
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L63+12
	b	.L61
.L55:
	ldr	r3, [fp, #-48]
	strb	r3, [fp, #-56]
	mov	r3, #0
	strb	r3, [fp, #-57]
	b	.L56
.L59:
	ldr	r3, [fp, #-28]
	lsl	r3, r3, #16
	lsr	r0, r3, #16
	ldrb	r3, [fp, #-57]
	add	r3, r3, #1
	and	r1, r3, #255
	sub	ip, fp, #44
	sub	r2, fp, #40
	mov	r3, #0
	str	r3, [sp, #8]
	sub	r3, fp, #48
	str	r3, [sp, #4]
	sub	r3, fp, #36
	str	r3, [sp]
	mov	r3, ip
	bl	Id_MCDC_89
	mov	r3, r0
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L63+12
	b	.L61
.L57:
	ldr	r3, [fp, #-48]
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-20]
	lsr	r3, r3, #16
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-48]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	strh	r3, [fp, #-50]	@ movhi
	ldrh	r3, [fp, #-50]
	lsr	r3, r3, #8
	strh	r3, [fp, #-50]	@ movhi
	ldrh	r3, [fp, #-50]	@ movhi
	strb	r3, [fp, #-53]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #16
	lsr	r0, r3, #16
	sub	ip, fp, #44
	sub	r2, fp, #40
	ldrb	r1, [fp, #-53]	@ zero_extendqisi2
	sub	r3, fp, #32
	str	r3, [sp, #4]
	sub	r3, fp, #36
	str	r3, [sp]
	mov	r3, ip
	bl	Id_MCDC_96
	str	r0, [fp, #-12]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	beq	.L58
	ldr	r3, [fp, #-12]
	b	.L61
.L58:
	ldrb	r3, [fp, #-57]	@ zero_extendqisi2
	add	r3, r3, #1
	strb	r3, [fp, #-57]
.L56:
	ldrb	r2, [fp, #-57]	@ zero_extendqisi2
	ldrb	r3, [fp, #-56]	@ zero_extendqisi2
	cmp	r2, r3
	bcc	.L59
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-28]
	ldrh	r3, [fp, #-52]
	add	r3, r3, #1
	strh	r3, [fp, #-52]	@ movhi
.L51:
	ldrh	r3, [fp, #-52]
	cmp	r3, #3
	bls	.L60
.L50:
	mov	r3, #0
.L61:
	ldr	r2, .L63
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L62
	bl	__stack_chk_fail
.L62:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L64:
	.align	2
.L63:
	.word	.LC2
	.word	Id_MCDC_112
	.word	6147
	.word	65535
	.word	Id_MCDC_113
	.size	Id_MCDC_97, .-Id_MCDC_97
	.section	.rodata
	.align	2
.LC3:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	Id_MCDC_99
	.syntax unified
	.arm
	.fpu softvfp
	.type	Id_MCDC_99, %function
Id_MCDC_99:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	ldr	r3, .L72
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	mov	r3, #0
	str	r3, [fp, #-12]
	mov	r3, #0
	str	r3, [fp, #-16]
	mov	r0, #372
	bl	malloc
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L72+4
	str	r2, [r3, #16]
	bl	Id_MCDC_97
	mov	r3, #0
	str	r3, [fp, #-16]
	b	.L66
.L69:
	ldr	r3, .L72+4
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-16]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r1, r3
	add	r3, r3, #5
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #240
	bhi	.L67
	ldr	r3, .L72+4
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-16]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r1, r3
	add	r3, r3, #5
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
	ldr	r3, .L72+4
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-16]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r1, r3
	add	r3, r3, #5
	ldrb	r1, [r3]	@ zero_extendqisi2
	sub	r2, fp, #12
	ldr	r3, [fp, #-16]
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3]
	b	.L68
.L67:
	sub	r2, fp, #12
	ldr	r3, [fp, #-16]
	add	r3, r2, r3
	mov	r2, #1
	strb	r2, [r3]
.L68:
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
.L66:
	ldr	r3, [fp, #-16]
	cmp	r3, #3
	bls	.L69
	sub	r3, fp, #12
	mov	r1, r3
	mov	r0, #4
	bl	Id_MCDC_95
	mov	r3, r0
	ldr	r2, .L72+8
	str	r3, [r2]
	nop
	ldr	r3, .L72
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L71
	bl	__stack_chk_fail
.L71:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L73:
	.align	2
.L72:
	.word	.LC3
	.word	Id_MCDC_113
	.word	Id_MCDC_114
	.size	Id_MCDC_99, .-Id_MCDC_99
	.align	2
	.global	Id_MCDC_100
	.syntax unified
	.arm
	.fpu softvfp
	.type	Id_MCDC_100, %function
Id_MCDC_100:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	Id_MCDC_99
	nop
	pop	{fp, pc}
	.size	Id_MCDC_100, .-Id_MCDC_100
	.section	.rodata
	.align	2
.LC4:
	.ascii	"r\000"
	.align	2
.LC5:
	.ascii	"in.eds\000"
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	mov	r3, #0
	strh	r3, [fp, #-12]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-10]	@ movhi
	ldr	r1, .L79
	ldr	r0, .L79+4
	bl	fopen
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L77
	mov	r3, #1
	b	.L78
.L77:
	bl	Id_MCDC_100
	mov	r3, #0
.L78:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L80:
	.align	2
.L79:
	.word	.LC4
	.word	.LC5
	.size	main, .-main
	.align	2
	.global	__VERIFIER_assert
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_assert, %function
__VERIFIER_assert:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L85
	nop
.L83:
	bl	__VERIFIER_error
.L85:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__VERIFIER_assert, .-__VERIFIER_assert
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
