	.file	"467914.c"
	.intel_syntax noprefix
	.text
	.type	MXL_ControlWrite_Group, @function
MXL_ControlWrite_Group:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	QWORD PTR -40[rbp], rdi
	mov	DWORD PTR -44[rbp], esi
	mov	DWORD PTR -48[rbp], edx
	mov	DWORD PTR -52[rbp], ecx
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR [rax]
	mov	QWORD PTR -8[rbp], rax
	cmp	DWORD PTR -52[rbp], 1
	jne	.L2
	mov	DWORD PTR -28[rbp], 0
	jmp	.L3
.L11:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 32[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -44[rbp], eax
	jne	.L4
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 32[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	eax, DWORD PTR 4[rax]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR -48[rbp]
	cmp	eax, DWORD PTR -12[rbp]
	jge	.L5
	mov	DWORD PTR -24[rbp], 0
	jmp	.L6
.L7:
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, DWORD PTR -48[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	rax, QWORD PTR -8[rbp]
	mov	rcx, QWORD PTR 32[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rcx
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -24[rbp]
	cdqe
	sal	rax, 2
	add	rax, rcx
	and	edx, 1
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, DWORD PTR -48[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	cdqe
	and	eax, 1
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 32[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	rdx, QWORD PTR 16[rax]
	mov	eax, DWORD PTR -24[rbp]
	cdqe
	sal	rax, 3
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	rsi, QWORD PTR 32[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rsi
	mov	rsi, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -24[rbp]
	cdqe
	sal	rax, 3
	add	rax, rsi
	mov	rax, QWORD PTR [rax]
	mov	rsi, rax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	MXL_RegWriteBit@PLT
	add	DWORD PTR -24[rbp], 1
.L6:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 32[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	eax, DWORD PTR 4[rax]
	cmp	DWORD PTR -24[rbp], eax
	jl	.L7
	mov	DWORD PTR -16[rbp], 0
	mov	DWORD PTR -20[rbp], 0
	jmp	.L8
.L9:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 32[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	rdx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -20[rbp]
	cdqe
	sal	rax, 2
	add	rax, rdx
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	add	DWORD PTR -16[rbp], eax
	add	DWORD PTR -20[rbp], 1
.L8:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 32[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	eax, DWORD PTR 4[rax]
	cmp	DWORD PTR -20[rbp], eax
	jl	.L9
	jmp	.L4
.L5:
	mov	eax, -1
	jmp	.L10
.L4:
	add	DWORD PTR -28[rbp], 1
.L3:
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -28[rbp], eax
	jl	.L11
.L2:
	cmp	DWORD PTR -52[rbp], 2
	jne	.L12
	mov	DWORD PTR -28[rbp], 0
	jmp	.L13
.L20:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -44[rbp], eax
	jne	.L14
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	eax, DWORD PTR 4[rax]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR -48[rbp]
	cmp	eax, DWORD PTR -12[rbp]
	jge	.L15
	mov	DWORD PTR -24[rbp], 0
	jmp	.L16
.L17:
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, DWORD PTR -48[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	rax, QWORD PTR -8[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rcx
	mov	rcx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -24[rbp]
	cdqe
	sal	rax, 2
	add	rax, rcx
	and	edx, 1
	mov	DWORD PTR [rax], edx
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, DWORD PTR -48[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	cdqe
	and	eax, 1
	mov	rcx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	rdx, QWORD PTR 16[rax]
	mov	eax, DWORD PTR -24[rbp]
	cdqe
	sal	rax, 3
	add	rax, rdx
	mov	rax, QWORD PTR [rax]
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	rsi, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rsi
	mov	rsi, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -24[rbp]
	cdqe
	sal	rax, 3
	add	rax, rsi
	mov	rax, QWORD PTR [rax]
	mov	rsi, rax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	MXL_RegWriteBit@PLT
	add	DWORD PTR -24[rbp], 1
.L16:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	eax, DWORD PTR 4[rax]
	cmp	DWORD PTR -24[rbp], eax
	jl	.L17
	mov	DWORD PTR -16[rbp], 0
	mov	DWORD PTR -20[rbp], 0
	jmp	.L18
.L19:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	rdx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -20[rbp]
	cdqe
	sal	rax, 2
	add	rax, rdx
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	add	DWORD PTR -16[rbp], eax
	add	DWORD PTR -20[rbp], 1
.L18:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 5
	add	rax, rdx
	mov	eax, DWORD PTR 4[rax]
	cmp	DWORD PTR -20[rbp], eax
	jl	.L19
	jmp	.L14
.L15:
	mov	eax, -1
	jmp	.L10
.L14:
	add	DWORD PTR -28[rbp], 1
.L13:
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	cmp	DWORD PTR -28[rbp], eax
	jl	.L20
.L12:
	mov	eax, 0
.L10:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	MXL_ControlWrite_Group, .-MXL_ControlWrite_Group
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"467914.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	MXL_ControlWrite_Group, %function
MXL_ControlWrite_Group:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #40
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	str	r2, [fp, #-40]
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-32]
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-44]
	cmp	r3, #1
	bne	.L2
	mov	r3, #0
	str	r3, [fp, #-28]
	b	.L3
.L11:
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #20]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3]
	ldr	r2, [fp, #-36]
	cmp	r2, r3
	bne	.L4
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #20]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	mov	r2, #1
	lsl	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bge	.L5
	mov	r3, #0
	str	r3, [fp, #-24]
	b	.L6
.L7:
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-24]
	asr	r1, r2, r3
	ldr	r3, [fp, #-12]
	ldr	r0, [r3, #20]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #2
	add	r3, r2, r3
	and	r2, r1, #1
	str	r2, [r3]
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #20]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r2, [r3, #16]
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3]
	mov	r0, r3
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #20]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-24]
	asr	r3, r2, r3
	and	r3, r3, #1
	mov	r2, r1
	mov	r1, r0
	ldr	r0, [fp, #-32]
	bl	MXL_RegWriteBit
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	str	r3, [fp, #-24]
.L6:
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #20]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-24]
	cmp	r2, r3
	blt	.L7
	mov	r3, #0
	str	r3, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-20]
	b	.L8
.L9:
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #20]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r2, [r3]
	ldr	r3, [fp, #-20]
	lsl	r3, r2, r3
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-20]
	add	r3, r3, #1
	str	r3, [fp, #-20]
.L8:
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #20]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-20]
	cmp	r2, r3
	blt	.L9
	b	.L4
.L5:
	mvn	r3, #0
	b	.L10
.L4:
	ldr	r3, [fp, #-28]
	add	r3, r3, #1
	str	r3, [fp, #-28]
.L3:
	ldr	r3, [fp, #-12]
	ldr	r3, [r3]
	ldr	r2, [fp, #-28]
	cmp	r2, r3
	blt	.L11
.L2:
	ldr	r3, [fp, #-44]
	cmp	r3, #2
	bne	.L12
	mov	r3, #0
	str	r3, [fp, #-28]
	b	.L13
.L20:
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3]
	ldr	r2, [fp, #-36]
	cmp	r2, r3
	bne	.L14
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	mov	r2, #1
	lsl	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bge	.L15
	mov	r3, #0
	str	r3, [fp, #-24]
	b	.L16
.L17:
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-24]
	asr	r1, r2, r3
	ldr	r3, [fp, #-12]
	ldr	r0, [r3, #16]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #2
	add	r3, r2, r3
	and	r2, r1, #1
	str	r2, [r3]
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r2, [r3, #16]
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3]
	mov	r0, r3
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-24]
	asr	r3, r2, r3
	and	r3, r3, #1
	mov	r2, r1
	mov	r1, r0
	ldr	r0, [fp, #-32]
	bl	MXL_RegWriteBit
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	str	r3, [fp, #-24]
.L16:
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-24]
	cmp	r2, r3
	blt	.L17
	mov	r3, #0
	str	r3, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-20]
	b	.L18
.L19:
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r2, [r3]
	ldr	r3, [fp, #-20]
	lsl	r3, r2, r3
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-20]
	add	r3, r3, #1
	str	r3, [fp, #-20]
.L18:
	ldr	r3, [fp, #-12]
	ldr	r1, [r3, #16]
	ldr	r2, [fp, #-28]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-20]
	cmp	r2, r3
	blt	.L19
	b	.L14
.L15:
	mvn	r3, #0
	b	.L10
.L14:
	ldr	r3, [fp, #-28]
	add	r3, r3, #1
	str	r3, [fp, #-28]
.L13:
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-28]
	cmp	r2, r3
	blt	.L20
.L12:
	mov	r3, #0
.L10:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	MXL_ControlWrite_Group, .-MXL_ControlWrite_Group
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
