	.file	"134739.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	t1_l1
	.bss
	.type	t1_l1, @object
	.size	t1_l1, 1
t1_l1:
	.zero	1
	.globl	_x_t1_l1
	.type	_x_t1_l1, @object
	.size	_x_t1_l1, 1
_x_t1_l1:
	.zero	1
	.globl	t1_l0
	.type	t1_l0, @object
	.size	t1_l0, 1
t1_l0:
	.zero	1
	.globl	_x_t1_l0
	.type	_x_t1_l0, @object
	.size	_x_t1_l0, 1
_x_t1_l0:
	.zero	1
	.globl	t1_evt1
	.type	t1_evt1, @object
	.size	t1_evt1, 1
t1_evt1:
	.zero	1
	.globl	_x_t1_evt1
	.type	_x_t1_evt1, @object
	.size	_x_t1_evt1, 1
_x_t1_evt1:
	.zero	1
	.globl	t1_x
	.align 4
	.type	t1_x, @object
	.size	t1_x, 4
t1_x:
	.zero	4
	.globl	_x_t1_x
	.align 4
	.type	_x_t1_x, @object
	.size	_x_t1_x, 4
_x_t1_x:
	.zero	4
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	t0_evt1
	.type	t0_evt1, @object
	.size	t0_evt1, 1
t0_evt1:
	.zero	1
	.globl	_x_t0_evt1
	.type	_x_t0_evt1, @object
	.size	_x_t0_evt1, 1
_x_t0_evt1:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	gate_l0
	.type	gate_l0, @object
	.size	gate_l0, 1
gate_l0:
	.zero	1
	.globl	_x_gate_l0
	.type	_x_gate_l0, @object
	.size	_x_gate_l0, 1
_x_gate_l0:
	.zero	1
	.globl	controller_l0
	.type	controller_l0, @object
	.size	controller_l0, 1
controller_l0:
	.zero	1
	.globl	_x_controller_l0
	.type	_x_controller_l0, @object
	.size	_x_controller_l0, 1
_x_controller_l0:
	.zero	1
	.globl	gate_l1
	.type	gate_l1, @object
	.size	gate_l1, 1
gate_l1:
	.zero	1
	.globl	_x_gate_l1
	.type	_x_gate_l1, @object
	.size	_x_gate_l1, 1
_x_gate_l1:
	.zero	1
	.globl	t0_evt0
	.type	t0_evt0, @object
	.size	t0_evt0, 1
t0_evt0:
	.zero	1
	.globl	_x_t0_evt0
	.type	_x_t0_evt0, @object
	.size	_x_t0_evt0, 1
_x_t0_evt0:
	.zero	1
	.globl	gate_y
	.align 4
	.type	gate_y, @object
	.size	gate_y, 4
gate_y:
	.zero	4
	.globl	_x_gate_y
	.align 4
	.type	_x_gate_y, @object
	.size	_x_gate_y, 4
_x_gate_y:
	.zero	4
	.globl	controller_l1
	.type	controller_l1, @object
	.size	controller_l1, 1
controller_l1:
	.zero	1
	.globl	_x_controller_l1
	.type	_x_controller_l1, @object
	.size	_x_controller_l1, 1
_x_controller_l1:
	.zero	1
	.globl	t0_l0
	.type	t0_l0, @object
	.size	t0_l0, 1
t0_l0:
	.zero	1
	.globl	_x_t0_l0
	.type	_x_t0_l0, @object
	.size	_x_t0_l0, 1
_x_t0_l0:
	.zero	1
	.globl	gate_evt0
	.type	gate_evt0, @object
	.size	gate_evt0, 1
gate_evt0:
	.zero	1
	.globl	_x_gate_evt0
	.type	_x_gate_evt0, @object
	.size	_x_gate_evt0, 1
_x_gate_evt0:
	.zero	1
	.globl	controller_evt0
	.type	controller_evt0, @object
	.size	controller_evt0, 1
controller_evt0:
	.zero	1
	.globl	_x_controller_evt0
	.type	_x_controller_evt0, @object
	.size	_x_controller_evt0, 1
_x_controller_evt0:
	.zero	1
	.globl	t0_x
	.align 4
	.type	t0_x, @object
	.size	t0_x, 4
t0_x:
	.zero	4
	.globl	_x_t0_x
	.align 4
	.type	_x_t0_x, @object
	.size	_x_t0_x, 4
_x_t0_x:
	.zero	4
	.globl	controller_evt1
	.type	controller_evt1, @object
	.size	controller_evt1, 1
controller_evt1:
	.zero	1
	.globl	_x_controller_evt1
	.type	_x_controller_evt1, @object
	.size	_x_controller_evt1, 1
_x_controller_evt1:
	.zero	1
	.globl	t0_l1
	.type	t0_l1, @object
	.size	t0_l1, 1
t0_l1:
	.zero	1
	.globl	_x_t0_l1
	.type	_x_t0_l1, @object
	.size	_x_t0_l1, 1
_x_t0_l1:
	.zero	1
	.globl	gate_evt1
	.type	gate_evt1, @object
	.size	gate_evt1, 1
gate_evt1:
	.zero	1
	.globl	_x_gate_evt1
	.type	_x_gate_evt1, @object
	.size	_x_gate_evt1, 1
_x_gate_evt1:
	.zero	1
	.globl	controller_z
	.align 4
	.type	controller_z, @object
	.size	controller_z, 4
controller_z:
	.zero	4
	.globl	_x_controller_z
	.align 4
	.type	_x_controller_z, @object
	.size	_x_controller_z, 4
_x_controller_z:
	.zero	4
	.globl	controller_evt2
	.type	controller_evt2, @object
	.size	controller_evt2, 1
controller_evt2:
	.zero	1
	.globl	_x_controller_evt2
	.type	_x_controller_evt2, @object
	.size	_x_controller_evt2, 1
_x_controller_evt2:
	.zero	1
	.globl	t1_evt0
	.type	t1_evt0, @object
	.size	t1_evt0, 1
t1_evt0:
	.zero	1
	.globl	_x_t1_evt0
	.type	_x_t1_evt0, @object
	.size	_x_t1_evt0, 1
_x_t1_evt0:
	.zero	1
	.globl	controller_cnt
	.align 4
	.type	controller_cnt, @object
	.size	controller_cnt, 4
controller_cnt:
	.zero	4
	.globl	_x_controller_cnt
	.align 4
	.type	_x_controller_cnt, @object
	.size	_x_controller_cnt, 4
_x_controller_cnt:
	.zero	4
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR controller_cnt[rip], eax
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L4
.L7:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L11
.L10:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L12
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L11
.L12:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L11
.L13:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L4
.L11:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L15
.L14:
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L15:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L18
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L19
.L18:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L19
.L20:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L19
.L21:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L4
.L19:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L23
.L22:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L23
.L24:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L23
.L25:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L4
.L23:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L27
.L26:
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L27:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L31
.L30:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L31
.L32:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L33
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L31
.L33:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L31:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L35
.L34:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L36
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L35
.L36:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L37
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L35
.L37:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L38
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L35
.L38:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L4
.L35:
	mov	eax, DWORD PTR controller_cnt[rip]
	test	eax, eax
	je	.L39
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	je	.L39
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 2
	je	.L39
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 3
	jne	.L4
.L39:
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L40
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L41
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L41:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L40
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
.L40:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L43
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L44
.L43:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L44
.L45:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L44
.L46:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L44:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L47
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L48
.L47:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L48
.L49:
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L50
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L48
.L50:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L4
.L48:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L51
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L51
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L51:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L52
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L52
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
.L52:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L55
.L4:
	mov	eax, 0
.L55:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L56
.L228:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_controller_cnt[rip], eax
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L58
.L57:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L58
.L59:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L58
.L60:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L61
.L58:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L63
.L62:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L64
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L63
.L64:
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L63
.L65:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L61
.L63:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L66
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L67
.L66:
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L61
.L67:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L69
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L69
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L69
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L70
.L69:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L61
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L61
.L70:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L73
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L73
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L73
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L73
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L73
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L74
.L73:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L74
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L74
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L74
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L61
.L74:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L76
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L76
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L76
	ucomiss	xmm0, xmm1
	je	.L77
.L76:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L77
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L77
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L77
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L77
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L61
.L77:
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L79
	ucomiss	xmm0, xmm1
	jne	.L79
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L81
.L79:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L81
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L81
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L81
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L61
.L81:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L82
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L82
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L82
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L82
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L82
	ucomiss	xmm0, xmm1
	je	.L84
.L82:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L84
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L84
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L84
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L61
.L84:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L87
.L86:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L87
.L88:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L89
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L87
.L89:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L61
.L87:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	jne	.L90
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L91
.L90:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L91
.L92:
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L91
.L93:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L61
.L91:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L95
.L94:
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L61
.L95:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L97
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L97
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L98
.L97:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L61
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L61
.L98:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L101
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L101
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L101
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L102
.L101:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L102
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L102
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L102
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L61
.L102:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L104
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L104
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L104
	ucomiss	xmm0, xmm1
	je	.L105
.L104:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L105
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L105
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L105
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L61
.L105:
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L107
	ucomiss	xmm0, xmm1
	jne	.L107
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L109
.L107:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L109
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L109
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L109
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L61
.L109:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L110
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L110
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L110
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L110
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L110
	ucomiss	xmm0, xmm1
	je	.L112
.L110:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L112
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L112
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L112
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L112
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L61
.L112:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L115
.L114:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L115
.L116:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L115
.L117:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L61
.L115:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L119
.L118:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L120
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L119
.L120:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L121
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L121
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L119
.L121:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L122
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L119
.L122:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L61
.L119:
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	je	.L123
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	je	.L123
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 2
	je	.L123
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 3
	jne	.L61
.L123:
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L124
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L125
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L61
.L125:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L124
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L61
.L124:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L126
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L126
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR controller_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_controller_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L126
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L126
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	je	.L128
.L126:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L61
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L128
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L128
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L61
.L128:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L130
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	jne	.L130
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L130
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L131
.L130:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L131
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L131
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L131
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L61
.L131:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L133
	ucomiss	xmm0, xmm1
	jne	.L133
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L135
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L136
.L135:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L136
.L133:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L136
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L136
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L136
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L136
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L61
.L136:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L137
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L137
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L137
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L138
.L137:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L139
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L139
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L138
.L139:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L138
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L138
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L138
.L140:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L138
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L138
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L61
.L138:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L141
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	jne	.L141
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jp	.L141
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	je	.L142
.L141:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L142
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L142
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L144
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L144
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L142
.L144:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L142
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L142
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L61
.L142:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L146
.L145:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L147
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L146
.L147:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L146
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L146
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L146
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L61
.L146:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L148
	ucomiss	xmm0, xmm1
	jne	.L148
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L150
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L150
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L150
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L151
.L150:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L148
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L148
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L148
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jg	.L151
.L148:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L151
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L151
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L151
.L152:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L151
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L61
.L151:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L153
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L153
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jne	.L153
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	jne	.L153
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L153
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L154
.L153:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L154
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L154
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L154
.L156:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L61
.L154:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L157
	ucomiss	xmm0, xmm1
	jne	.L157
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L160
.L159:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L160
.L157:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L160
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L160
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L160
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L160
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L61
.L160:
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	jne	.L161
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L161
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L161
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L162
.L161:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L162
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L162
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L163
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L163
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L162
.L163:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L61
.L162:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L164
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L165
.L164:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L166
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L165
.L166:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L167
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L165
.L167:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L61
.L165:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	jne	.L168
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L169
.L168:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L170
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L169
.L170:
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L171
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L169
.L171:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L61
.L169:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L172
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L61
.L172:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L173
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L61
.L173:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L174
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L174
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR gate_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_gate_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L174
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L175
.L174:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L177
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L61
.L177:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L61
.L175:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L179
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L179
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L179
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L179
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L180
.L179:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L180
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L180
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L180
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L61
.L180:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L182
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L182
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L182
	ucomiss	xmm0, xmm1
	je	.L184
.L182:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L184
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L184
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L184
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L184
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L61
.L184:
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L186
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L186
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L188
.L186:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L188
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L188
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L188
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L61
.L188:
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L189
	ucomiss	xmm0, xmm1
	jne	.L189
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L189
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L189
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L189
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L189
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L192
.L189:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L192
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L192
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L192
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L61
.L192:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L61
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L195
.L194:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L195
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L195
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L61
.L195:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L196
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L197
.L196:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L197
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L197
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L61
.L197:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L198
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L198
	mov	eax, 1
	jmp	.L199
.L198:
	mov	eax, 0
.L199:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L200
	mov	eax, 1
	jmp	.L201
.L200:
	mov	eax, 0
.L201:
	and	eax, 1
	xor	eax, edx
	test	al, al
	jne	.L202
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L202
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L61
.L202:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L204
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L204
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L205
	mov	eax, 1
	jmp	.L206
.L205:
	mov	eax, 0
.L206:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L207
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L207
	mov	eax, 1
	jmp	.L208
.L207:
	mov	eax, 0
.L208:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L61
.L204:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L209
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L209
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L210
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L210
	mov	eax, 1
	jmp	.L211
.L210:
	mov	eax, 0
.L211:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L213
.L212:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L214
.L213:
	mov	eax, 1
	jmp	.L215
.L214:
	mov	eax, 0
.L215:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L61
.L209:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L216
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L216
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L217
	mov	eax, 1
	jmp	.L218
.L217:
	mov	eax, 0
.L218:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L220
.L219:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L221
.L220:
	mov	eax, 1
	jmp	.L222
.L221:
	mov	eax, 0
.L222:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L61
.L216:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L252
	ucomiss	xmm0, xmm1
	je	.L223
.L252:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L61
.L223:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L225
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L61
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L61
.L225:
	mov	eax, 1
	jmp	.L227
.L61:
	mov	eax, 0
.L227:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	mov	BYTE PTR t1_l1[rip], al
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	mov	BYTE PTR t1_l0[rip], al
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	mov	BYTE PTR t1_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	movss	DWORD PTR t1_x[rip], xmm0
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	mov	BYTE PTR t0_evt1[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	mov	BYTE PTR gate_l0[rip], al
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	mov	BYTE PTR controller_l0[rip], al
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	mov	BYTE PTR gate_l1[rip], al
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	mov	BYTE PTR t0_evt0[rip], al
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	movss	DWORD PTR gate_y[rip], xmm0
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	mov	BYTE PTR controller_l1[rip], al
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	mov	BYTE PTR t0_l0[rip], al
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	mov	BYTE PTR gate_evt0[rip], al
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	mov	BYTE PTR controller_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	movss	DWORD PTR t0_x[rip], xmm0
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	mov	BYTE PTR controller_evt1[rip], al
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	mov	BYTE PTR t0_l1[rip], al
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	mov	BYTE PTR gate_evt1[rip], al
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	movss	DWORD PTR controller_z[rip], xmm0
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	mov	BYTE PTR controller_evt2[rip], al
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	mov	BYTE PTR t1_evt0[rip], al
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	mov	DWORD PTR controller_cnt[rip], eax
.L56:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L228
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1084227584
	.align 4
.LC2:
	.long	1065353216
	.align 4
.LC3:
	.long	1073741824
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"134739.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	t1_l1,1,1
	.comm	_x_t1_l1,1,1
	.comm	t1_l0,1,1
	.comm	_x_t1_l0,1,1
	.comm	t1_evt1,1,1
	.comm	_x_t1_evt1,1,1
	.comm	t1_x,4,4
	.comm	_x_t1_x,4,4
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	t0_evt1,1,1
	.comm	_x_t0_evt1,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	gate_l0,1,1
	.comm	_x_gate_l0,1,1
	.comm	controller_l0,1,1
	.comm	_x_controller_l0,1,1
	.comm	gate_l1,1,1
	.comm	_x_gate_l1,1,1
	.comm	t0_evt0,1,1
	.comm	_x_t0_evt0,1,1
	.comm	gate_y,4,4
	.comm	_x_gate_y,4,4
	.comm	controller_l1,1,1
	.comm	_x_controller_l1,1,1
	.comm	t0_l0,1,1
	.comm	_x_t0_l0,1,1
	.comm	gate_evt0,1,1
	.comm	_x_gate_evt0,1,1
	.comm	controller_evt0,1,1
	.comm	_x_controller_evt0,1,1
	.comm	t0_x,4,4
	.comm	_x_t0_x,4,4
	.comm	controller_evt1,1,1
	.comm	_x_controller_evt1,1,1
	.comm	t0_l1,1,1
	.comm	_x_t0_l1,1,1
	.comm	gate_evt1,1,1
	.comm	_x_gate_evt1,1,1
	.comm	controller_z,4,4
	.comm	_x_controller_z,4,4
	.comm	controller_evt2,1,1
	.comm	_x_controller_evt2,1,1
	.comm	t1_evt0,1,1
	.comm	_x_t1_evt0,1,1
	.comm	controller_cnt,4,4
	.comm	_x_controller_cnt,4,4
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+92
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+152
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+12
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+136
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L240+44
	str	r3, [r2]
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L7:
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L10:
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L12:
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L13:
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L11:
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
.L14:
	ldr	r3, .L240+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L240+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L15:
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L18:
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L20:
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L21:
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L19:
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L22:
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L24:
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L25:
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L23:
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L26:
	ldr	r3, .L240+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L240+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L27:
	ldr	r3, .L240+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L240+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L30:
	ldr	r3, .L240+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L240+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L32:
	ldr	r3, .L240+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L240+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L33:
	ldr	r3, .L240+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L31:
	ldr	r3, .L240+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L240+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L240+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L34:
	ldr	r3, .L240+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L240+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L240+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L36:
	ldr	r3, .L240+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L240+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L240+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L37:
	ldr	r3, .L240+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L240+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
	ldr	r3, .L240+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L35
.L38:
	ldr	r3, .L240+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L35:
	ldr	r3, .L240+44
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L240+44
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L39
	ldr	r3, .L240+44
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L39
	ldr	r3, .L240+44
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L4
.L39:
	ldr	r3, .L240+36
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L40
	ldr	r3, .L240+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L41
	ldr	r3, .L240+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L41:
	ldr	r3, .L240+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L240+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L40:
	ldr	r3, .L240+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L240+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L43
	ldr	r3, .L240+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
.L43:
	ldr	r3, .L240+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L240+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
.L45:
	ldr	r3, .L240+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
	ldr	r3, .L240+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
.L46:
	ldr	r3, .L240+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L44:
	ldr	r3, .L240+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L47
	ldr	r3, .L240+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
.L47:
	ldr	r3, .L240+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L240+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
.L49:
	ldr	r3, .L240+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
	ldr	r3, .L240+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
.L50:
	ldr	r3, .L240+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L48:
	ldr	r3, .L240+12
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	ldr	r3, .L240+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
	ldr	r3, .L240+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L51:
	ldr	r3, .L240+12
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L240+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L240+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L52:
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L240
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L55
.L4:
	mov	r3, #0
.L55:
	str	r3, [fp, #-24]
	b	.L56
.L241:
	.align	2
.L240:
	.word	_diverge_delta
	.word	gate_l0
	.word	gate_l1
	.word	gate_y
	.word	controller_l1
	.word	gate_evt0
	.word	controller_evt0
	.word	controller_evt1
	.word	gate_evt1
	.word	controller_z
	.word	controller_evt2
	.word	controller_cnt
	.word	_x__diverge_delta
	.word	_x_delta
	.word	_x_gate_l0
	.word	_x_gate_l1
	.word	_x_gate_y
	.word	_x_gate_evt0
	.word	_x_gate_evt1
	.word	_x_t1_evt0
	.word	_x_t1_evt1
	.word	_x_t1_l0
	.word	_x_t1_l1
	.word	t1_x
	.word	_x_t1_x
	.word	t1_l0
	.word	t1_l1
	.word	t1_evt0
	.word	t1_evt1
	.word	_x_t0_evt0
	.word	_x_t0_evt1
	.word	_x_t0_l0
	.word	_x_t0_l1
	.word	1084227584
	.word	t0_x
	.word	_x_t0_x
	.word	t0_l0
	.word	t0_l1
	.word	delta
	.word	t0_evt0
	.word	t0_evt1
	.word	_x_controller_evt2
	.word	_x_controller_evt0
	.word	_x_controller_evt1
	.word	_x_controller_cnt
	.word	_x_controller_z
	.word	_x_controller_l0
	.word	_x_controller_l1
	.word	controller_l0
.L216:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+88
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+96
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+48
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+52
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+64
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+140
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L240+180
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L240+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L240+176
	str	r3, [r2]
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L57
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
.L57:
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
.L59:
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
.L60:
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L58:
	ldr	r3, .L240+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L240+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L62:
	ldr	r3, .L240+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L64
	ldr	r3, .L240+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L64:
	ldr	r3, .L240+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
	ldr	r3, .L240+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L65:
	ldr	r3, .L240+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L240+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L63:
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L66:
	ldr	r3, .L240+96
	ldr	r3, [r3]	@ float
	ldr	r1, .L240+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L67:
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L240+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L240+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L70
.L69:
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L70:
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L72
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L72
	ldr	r3, .L240+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L73
.L72:
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L73
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L73:
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L240+92
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L75
	mov	r3, #0
	mov	r4, r3
.L75:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
	ldr	r3, .L240+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L240+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
.L74:
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L76:
	ldr	r3, .L240+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L240+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L77
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L77
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L77
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L77
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
.L77:
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L79
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L79:
	ldr	r3, .L240+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L240+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L240+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L240+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L240+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L240+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L82
.L80:
	ldr	r3, .L240+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L240+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L240+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L82:
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
.L83:
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
.L85:
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
.L86:
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L84:
	ldr	r3, .L240+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
	ldr	r3, .L240+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
.L87:
	ldr	r3, .L240+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L240+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
.L89:
	ldr	r3, .L240+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
	ldr	r3, .L240+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
.L90:
	ldr	r3, .L240+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L240+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L88:
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L91
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
.L91:
	ldr	r3, .L240+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L240+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L92:
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L240+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L240+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
.L94:
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L95
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L95:
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L240+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L98
.L97:
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L98:
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L240+136
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L100
	mov	r3, #0
	mov	r4, r3
.L100:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L240+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L240+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L101
.L99:
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L101
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L101
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L101
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L101:
	ldr	r3, .L240+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L240+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
.L102:
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L104:
	ldr	r3, .L240+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L240+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L240+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L240+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L240+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L240+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
.L105:
	ldr	r3, .L240+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L240+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L240+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L240+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L107:
	ldr	r3, .L240+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L108
	ldr	r3, .L240+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
.L108:
	ldr	r3, .L240+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
	ldr	r3, .L240+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
.L110:
	ldr	r3, .L240+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
	ldr	r3, .L240+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
.L111:
	ldr	r3, .L240+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L240+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L109:
	ldr	r3, .L240+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L112
	ldr	r3, .L240+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L112
	ldr	r3, .L240+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L113
.L112:
	ldr	r3, .L240+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L240+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L114
	ldr	r3, .L240+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L113
.L114:
	ldr	r3, .L240+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L115
	ldr	r3, .L240+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
	ldr	r3, .L240+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L113
.L115:
	ldr	r3, .L240+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L240+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L240+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L113
.L116:
	ldr	r3, .L240+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L240+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L240+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L113:
	ldr	r3, .L240+176
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L240+176
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L117
	ldr	r3, .L240+176
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L117
	ldr	r3, .L240+176
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L61
.L117:
	ldr	r3, .L240+180
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L240+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L240+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L119:
	ldr	r3, .L240+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
	ldr	r3, .L240+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L118:
	ldr	r3, .L240+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L242+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L242+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L242+212
	ldr	r2, [r3]
	ldr	r3, .L242+208
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L122
.L120:
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L122:
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L242+208
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L124
	ldr	r3, .L242+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L125
.L124:
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L125
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L125
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L125
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L125:
	ldr	r3, .L242+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L126
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
.L128:
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
.L126:
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L129
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L129:
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L242+212
	ldr	r2, [r3]
	ldr	r3, .L242+208
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L131
.L130:
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L242+212
	ldr	r2, [r3]
	ldr	r3, .L242+208
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L131
.L132:
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L133
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L133
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L133:
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L131:
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L242+212
	ldr	r2, [r3]
	ldr	r3, .L242+208
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L134
	ldr	r3, .L242+12
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L135
.L134:
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L136
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L136
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
.L136:
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L135
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L135:
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
.L137:
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
.L139:
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L138:
	ldr	r3, .L242+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L242+212
	ldr	r2, [r3]
	ldr	r3, .L242+208
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L143
.L142:
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L242+212
	ldr	r2, [r3]
	ldr	r3, .L242+208
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L140
	ldr	r3, .L242+212
	ldr	r3, [r3]
	cmp	r3, #1
	bgt	.L143
.L140:
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L144
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L144
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L144:
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L143:
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L145
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L145
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L145
	ldr	r3, .L242+212
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L145
	ldr	r3, .L242+208
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L145
	ldr	r3, .L242+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
.L145:
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L146
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L146
.L147:
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L146
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L146
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L146:
	ldr	r3, .L242+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L150
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L150:
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L148:
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L151:
	ldr	r3, .L242+212
	ldr	r2, [r3]
	ldr	r3, .L242+208
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	bne	.L152
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L242+12
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L153
.L152:
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
.L154:
	ldr	r3, .L242+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L242
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L153
	ldr	r3, .L242+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L242+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L153:
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
.L155:
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
.L157:
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
.L158:
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L156:
	ldr	r3, .L242+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L159
	ldr	r3, .L242+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
.L159:
	ldr	r3, .L242+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L242+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
.L161:
	ldr	r3, .L242+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L162
	ldr	r3, .L242+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
.L162:
	ldr	r3, .L242+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L242+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L160:
	ldr	r3, .L242+112
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L163
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L163:
	ldr	r3, .L242+112
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L164:
	ldr	r3, .L242+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L242+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L242+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L242+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
.L165:
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L167
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
.L167:
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L166:
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L242+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L170
.L169:
	ldr	r3, .L242+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L170
	ldr	r3, .L242+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L170
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L170
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L170:
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L171
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L171
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L171
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L171
	ldr	r3, .L242+116
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L171
	ldr	r3, .L242+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L173
.L171:
	ldr	r3, .L242+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L242+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L173:
	ldr	r3, .L242+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
.L174:
	ldr	r3, .L242+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L242+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L176
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L176:
	ldr	r3, .L242+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L242+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L242+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L242+116
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L242+116
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	b	.L243
.L244:
	.align	2
.L242:
	.word	_x_controller_l0
	.word	controller_l1
	.word	_x_controller_l1
	.word	controller_z
	.word	_x_controller_z
	.word	delta
	.word	_x_t1_l1
	.word	t1_l1
	.word	_x_t1_l0
	.word	t1_l0
	.word	_x_t1_evt1
	.word	t1_evt1
	.word	_x_t1_x
	.word	t1_x
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_t0_evt1
	.word	t0_evt1
	.word	_x_delta
	.word	delta
	.word	_x_gate_l0
	.word	gate_l0
	.word	_x_controller_l0
	.word	controller_l0
	.word	_x_gate_l1
	.word	gate_l1
	.word	_x_t0_evt0
	.word	t0_evt0
	.word	_x_gate_y
	.word	gate_y
	.word	_x_controller_l1
	.word	controller_l1
	.word	_x_t0_l0
	.word	t0_l0
	.word	_x_gate_evt0
	.word	gate_evt0
	.word	_x_controller_evt0
	.word	controller_evt0
	.word	_x_t0_x
	.word	t0_x
	.word	_x_controller_evt1
	.word	controller_evt1
	.word	_x_t0_l1
	.word	t0_l1
	.word	_x_gate_evt1
	.word	gate_evt1
	.word	_x_controller_z
	.word	controller_z
	.word	_x_controller_evt2
	.word	controller_evt2
	.word	_x_t1_evt0
	.word	t1_evt0
	.word	_x_controller_cnt
	.word	controller_cnt
.L243:
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L180
.L177:
	ldr	r3, .L242+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L242+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L180:
	ldr	r3, .L242+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L242+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L242+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
.L182:
	ldr	r3, .L242+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L242+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L183:
	ldr	r3, .L242+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L242+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
.L184:
	ldr	r3, .L242+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L242+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L242+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
.L185:
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	mov	r3, #1
	b	.L187
.L186:
	mov	r3, #0
.L187:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	mov	r3, #1
	b	.L189
.L188:
	mov	r3, #0
.L189:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L242+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L61
.L190:
	ldr	r3, .L242+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L242+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L242+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	mov	r3, #1
	b	.L194
.L193:
	mov	r3, #0
.L194:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	mov	r3, #1
	b	.L196
.L195:
	mov	r3, #0
.L196:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
.L192:
	ldr	r3, .L242+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L197
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	mov	r3, #1
	b	.L199
.L198:
	mov	r3, #0
.L199:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L242+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L242+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
.L200:
	ldr	r3, .L242+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L242+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
.L201:
	mov	r3, #1
	b	.L203
.L202:
	mov	r3, #0
.L203:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
.L197:
	ldr	r3, .L242+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L242+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L242+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L242+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	mov	r3, #1
	b	.L206
.L205:
	mov	r3, #0
.L206:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L242+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L242+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
.L207:
	ldr	r3, .L242+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L242+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
.L208:
	mov	r3, #1
	b	.L210
.L209:
	mov	r3, #0
.L210:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
.L204:
	ldr	r3, .L242+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L242+60
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L212
	mov	r3, #0
	mov	r4, r3
.L212:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L61
.L211:
	ldr	r3, .L242+60
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L242+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L242+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L242+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L61
.L213:
	mov	r3, #1
	b	.L215
.L61:
	mov	r3, #0
.L215:
	str	r3, [fp, #-24]
	ldr	r3, .L242+24
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+28
	strb	r2, [r3]
	ldr	r3, .L242+32
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+36
	strb	r2, [r3]
	ldr	r3, .L242+40
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+44
	strb	r2, [r3]
	ldr	r3, .L242+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+52
	str	r3, [r2]	@ float
	ldr	r3, .L242+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+60
	str	r3, [r2]	@ float
	ldr	r3, .L242+64
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+68
	strb	r2, [r3]
	ldr	r3, .L242+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+76
	str	r3, [r2]	@ float
	ldr	r3, .L242+80
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+84
	strb	r2, [r3]
	ldr	r3, .L242+88
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+92
	strb	r2, [r3]
	ldr	r3, .L242+96
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+100
	strb	r2, [r3]
	ldr	r3, .L242+104
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+108
	strb	r2, [r3]
	ldr	r3, .L242+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+116
	str	r3, [r2]	@ float
	ldr	r3, .L242+120
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+124
	strb	r2, [r3]
	ldr	r3, .L242+128
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+132
	strb	r2, [r3]
	ldr	r3, .L242+136
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+140
	strb	r2, [r3]
	ldr	r3, .L242+144
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+148
	strb	r2, [r3]
	ldr	r3, .L242+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+156
	str	r3, [r2]	@ float
	ldr	r3, .L242+160
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+164
	strb	r2, [r3]
	ldr	r3, .L242+168
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+172
	strb	r2, [r3]
	ldr	r3, .L242+176
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+180
	strb	r2, [r3]
	ldr	r3, .L242+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L242+188
	str	r3, [r2]	@ float
	ldr	r3, .L242+192
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+196
	strb	r2, [r3]
	ldr	r3, .L242+200
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L242+204
	strb	r2, [r3]
	ldr	r3, .L242+208
	ldr	r3, [r3]
	ldr	r2, .L242+212
	str	r3, [r2]
.L56:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L216
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
