	.file	"132952219.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 208
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR -104[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -200[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -196[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -192[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -188[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -184[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -180[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -176[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -172[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -168[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -164[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -160[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -156[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -152[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -148[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -144[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -140[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -136[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -132[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -128[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -124[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -120[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -116[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -112[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -108[rbp], eax
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -164[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L4
	cmp	DWORD PTR -168[rbp], 0
	je	.L5
.L4:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -184[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L5
	cmp	DWORD PTR -188[rbp], 0
	jne	.L5
	cmp	DWORD PTR -192[rbp], 0
	jne	.L5
	cmp	DWORD PTR -196[rbp], 0
	jne	.L5
	mov	eax, 1
	jmp	.L7
.L5:
	mov	eax, 0
.L7:
	mov	DWORD PTR -100[rbp], eax
	jmp	.L8
.L454:
	cmp	DWORD PTR -192[rbp], 0
	je	.L9
	cmp	DWORD PTR -196[rbp], 0
	je	.L9
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR -104[rbp], eax
	jmp	.L10
.L9:
	sub	DWORD PTR -104[rbp], 1
.L10:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -96[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -92[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -88[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -84[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -80[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -76[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -72[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -68[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -64[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -60[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -56[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -52[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -48[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -44[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -40[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -36[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -32[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -28[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -24[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -20[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -16[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -12[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -8[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -4[rbp], eax
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L467
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L22
.L467:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L468
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L22
.L468:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L469
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L22
.L469:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L470
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L22
.L470:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L471
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L22
.L471:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L472
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L22
.L472:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L473
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L22
.L473:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L474
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L22
.L474:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L475
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L22
.L475:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jp	.L11
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jne	.L11
.L22:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L486
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L43
.L486:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L487
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L43
.L487:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L488
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L43
.L488:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L489
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L43
.L489:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L490
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L43
.L490:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L491
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L43
.L491:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L492
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L43
.L492:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L493
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L43
.L493:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L494
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L43
.L494:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jne	.L11
.L43:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L505
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L64
.L505:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L506
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L64
.L506:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L507
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L64
.L507:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L508
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L64
.L508:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L509
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L64
.L509:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L510
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L64
.L510:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L511
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L64
.L511:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L512
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L64
.L512:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L513
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L64
.L513:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jne	.L11
.L64:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L524
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L85
.L524:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L525
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L85
.L525:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L526
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L85
.L526:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L527
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L85
.L527:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L528
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L85
.L528:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L529
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L85
.L529:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L530
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L85
.L530:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L531
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L85
.L531:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L532
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L85
.L532:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jne	.L11
.L85:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jp	.L543
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	je	.L106
.L543:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L544
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L106
.L544:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L545
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L106
.L545:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L546
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L106
.L546:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L547
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L106
.L547:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L548
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L106
.L548:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L549
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L106
.L549:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L550
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L106
.L550:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L551
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L106
.L551:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jne	.L11
.L106:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L562
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L127
.L562:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L563
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L127
.L563:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L564
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L127
.L564:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L565
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L127
.L565:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L566
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L127
.L566:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L567
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L127
.L567:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L568
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L127
.L568:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L569
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L127
.L569:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L570
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L127
.L570:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jne	.L11
.L127:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC19[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC19[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L581
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L148
.L581:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L582
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L148
.L582:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jp	.L583
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	je	.L148
.L583:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L584
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L148
.L584:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L585
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L148
.L585:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L586
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L148
.L586:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L587
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L148
.L587:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jp	.L588
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	je	.L148
.L588:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L589
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L148
.L589:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jne	.L11
.L148:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC19[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L600
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L169
.L600:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jp	.L601
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	je	.L169
.L601:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L602
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L169
.L602:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L603
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L169
.L603:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L604
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L169
.L604:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L605
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L169
.L605:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L606
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L169
.L606:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jp	.L607
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	je	.L169
.L607:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L608
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L169
.L608:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jne	.L11
.L169:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L619
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L190
.L619:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L620
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L190
.L620:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L621
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L190
.L621:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L622
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L190
.L622:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L623
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L190
.L623:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L624
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L190
.L624:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L625
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L190
.L625:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L626
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L190
.L626:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L627
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L190
.L627:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jne	.L11
.L190:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -72[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L638
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L211
.L638:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L639
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L211
.L639:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L640
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L211
.L640:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L641
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L211
.L641:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L642
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L211
.L642:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L643
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L211
.L643:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L644
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L211
.L644:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jp	.L645
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	je	.L211
.L645:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L646
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L211
.L646:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -72[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jne	.L11
.L211:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC19[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jp	.L657
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	je	.L232
.L657:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L658
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L232
.L658:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L659
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L232
.L659:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L660
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L232
.L660:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L661
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L232
.L661:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L662
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L232
.L662:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L663
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L232
.L663:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L664
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L232
.L664:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jp	.L665
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	je	.L232
.L665:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jne	.L11
.L232:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC19[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L676
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L253
.L676:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L677
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L253
.L677:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L678
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L253
.L678:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L679
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L253
.L679:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L680
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L253
.L680:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L681
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L253
.L681:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L682
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L253
.L682:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L683
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L253
.L683:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jp	.L684
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	je	.L253
.L684:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jne	.L11
.L253:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -96[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L695
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L274
.L695:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L696
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L274
.L696:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L697
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L274
.L697:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L698
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L274
.L698:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L699
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L274
.L699:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jp	.L700
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	je	.L274
.L700:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L701
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L274
.L701:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L702
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L274
.L702:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L703
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L274
.L703:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -96[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jne	.L11
.L274:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L714
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L295
.L714:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L715
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L295
.L715:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L716
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L295
.L716:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L717
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L295
.L717:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L718
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L295
.L718:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L719
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L295
.L719:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L720
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L295
.L720:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L721
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L295
.L721:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L722
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L295
.L722:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jne	.L11
.L295:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L733
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L316
.L733:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L734
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L316
.L734:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L735
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L316
.L735:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L736
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L316
.L736:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L737
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L316
.L737:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L738
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L316
.L738:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L739
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L316
.L739:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L740
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L316
.L740:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L741
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L316
.L741:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -80[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jne	.L11
.L316:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -76[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC19[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L752
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L337
.L752:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L753
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L337
.L753:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L754
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L337
.L754:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L755
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L337
.L755:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L756
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L337
.L756:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jp	.L757
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	je	.L337
.L757:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L758
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L337
.L758:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L759
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L337
.L759:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L760
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L337
.L760:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -76[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jne	.L11
.L337:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L771
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L358
.L771:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L772
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L358
.L772:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L773
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L358
.L773:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L774
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L358
.L774:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L775
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L358
.L775:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L776
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L358
.L776:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L777
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L358
.L777:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L778
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L358
.L778:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L779
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L358
.L779:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jne	.L11
.L358:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L790
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L379
.L790:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L791
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L379
.L791:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	jp	.L792
	movsd	xmm1, QWORD PTR .LC7[rip]
	ucomisd	xmm0, xmm1
	je	.L379
.L792:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L793
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L379
.L793:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	jp	.L794
	ucomisd	xmm0, QWORD PTR .LC1[rip]
	je	.L379
.L794:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L795
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L379
.L795:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L796
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L379
.L796:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L797
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L379
.L797:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L798
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L379
.L798:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -152[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jne	.L11
.L379:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -172[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L809
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L400
.L809:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -180[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L810
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L400
.L810:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L811
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L400
.L811:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -200[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	jp	.L812
	ucomisd	xmm0, QWORD PTR .LC6[rip]
	je	.L400
.L812:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -164[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L813
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L400
.L813:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L814
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L400
.L814:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L815
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L400
.L815:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L816
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L400
.L816:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L817
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L400
.L817:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jne	.L11
.L400:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L828
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L421
.L828:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L829
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L421
.L829:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -184[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L830
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L421
.L830:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L831
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L421
.L831:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -140[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L832
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L421
.L832:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L833
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L421
.L833:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L834
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L421
.L834:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -148[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L835
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L421
.L835:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -156[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L836
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L421
.L836:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L11
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jne	.L11
.L421:
	cmp	DWORD PTR -64[rbp], 0
	jne	.L432
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -56[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L433
.L432:
	mov	edx, 1
	jmp	.L434
.L433:
	mov	edx, 0
.L434:
	mov	eax, DWORD PTR -168[rbp]
	cmp	edx, eax
	jne	.L11
	cmp	DWORD PTR -84[rbp], 0
	jne	.L435
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -72[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -80[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L436
.L435:
	mov	edx, 1
	jmp	.L437
.L436:
	mov	edx, 0
.L437:
	mov	eax, DWORD PTR -188[rbp]
	cmp	edx, eax
	jne	.L11
	cmp	DWORD PTR -192[rbp], 0
	je	.L438
	cmp	DWORD PTR -196[rbp], 0
	jne	.L439
.L438:
	cmp	DWORD PTR -192[rbp], 0
	je	.L440
	cmp	DWORD PTR -196[rbp], 0
	jne	.L441
.L440:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -164[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L441
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -160[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -164[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L442
	cmp	DWORD PTR -168[rbp], 0
	je	.L441
.L442:
	cmp	DWORD PTR -192[rbp], 0
	je	.L439
.L441:
	mov	edx, 1
	jmp	.L444
.L439:
	mov	edx, 0
.L444:
	mov	eax, DWORD PTR -88[rbp]
	cmp	edx, eax
	jne	.L11
	cmp	DWORD PTR -192[rbp], 0
	je	.L445
	cmp	DWORD PTR -196[rbp], 0
	jne	.L446
.L445:
	cmp	DWORD PTR -192[rbp], 0
	je	.L447
	cmp	DWORD PTR -196[rbp], 0
	jne	.L448
.L447:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -184[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L448
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -176[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -184[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L449
	cmp	DWORD PTR -188[rbp], 0
	je	.L448
.L449:
	cmp	DWORD PTR -196[rbp], 0
	je	.L446
.L448:
	mov	edx, 1
	jmp	.L451
.L446:
	mov	edx, 0
.L451:
	mov	eax, DWORD PTR -92[rbp]
	cmp	edx, eax
	jne	.L11
	mov	eax, 1
	jmp	.L452
.L11:
	mov	eax, 0
.L452:
	mov	DWORD PTR -100[rbp], eax
	movss	xmm0, DWORD PTR -96[rbp]
	movss	DWORD PTR -200[rbp], xmm0
	mov	eax, DWORD PTR -92[rbp]
	mov	DWORD PTR -196[rbp], eax
	mov	eax, DWORD PTR -88[rbp]
	mov	DWORD PTR -192[rbp], eax
	mov	eax, DWORD PTR -84[rbp]
	mov	DWORD PTR -188[rbp], eax
	movss	xmm0, DWORD PTR -80[rbp]
	movss	DWORD PTR -184[rbp], xmm0
	movss	xmm0, DWORD PTR -76[rbp]
	movss	DWORD PTR -180[rbp], xmm0
	movss	xmm0, DWORD PTR -72[rbp]
	movss	DWORD PTR -176[rbp], xmm0
	movss	xmm0, DWORD PTR -68[rbp]
	movss	DWORD PTR -172[rbp], xmm0
	mov	eax, DWORD PTR -64[rbp]
	mov	DWORD PTR -168[rbp], eax
	movss	xmm0, DWORD PTR -60[rbp]
	movss	DWORD PTR -164[rbp], xmm0
	movss	xmm0, DWORD PTR -56[rbp]
	movss	DWORD PTR -160[rbp], xmm0
	movss	xmm0, DWORD PTR -52[rbp]
	movss	DWORD PTR -156[rbp], xmm0
	movss	xmm0, DWORD PTR -48[rbp]
	movss	DWORD PTR -152[rbp], xmm0
	movss	xmm0, DWORD PTR -44[rbp]
	movss	DWORD PTR -148[rbp], xmm0
	movss	xmm0, DWORD PTR -40[rbp]
	movss	DWORD PTR -144[rbp], xmm0
	movss	xmm0, DWORD PTR -36[rbp]
	movss	DWORD PTR -140[rbp], xmm0
	movss	xmm0, DWORD PTR -32[rbp]
	movss	DWORD PTR -136[rbp], xmm0
	movss	xmm0, DWORD PTR -28[rbp]
	movss	DWORD PTR -132[rbp], xmm0
	movss	xmm0, DWORD PTR -24[rbp]
	movss	DWORD PTR -128[rbp], xmm0
	movss	xmm0, DWORD PTR -20[rbp]
	movss	DWORD PTR -124[rbp], xmm0
	movss	xmm0, DWORD PTR -16[rbp]
	movss	DWORD PTR -120[rbp], xmm0
	movss	xmm0, DWORD PTR -12[rbp]
	movss	DWORD PTR -116[rbp], xmm0
	movss	xmm0, DWORD PTR -8[rbp]
	movss	DWORD PTR -112[rbp], xmm0
	movss	xmm0, DWORD PTR -4[rbp]
	movss	DWORD PTR -108[rbp], xmm0
.L8:
	cmp	DWORD PTR -104[rbp], 0
	js	.L453
	cmp	DWORD PTR -100[rbp], 0
	jne	.L454
.L453:
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 8
.LC0:
	.long	0
	.long	1077084160
	.align 8
.LC1:
	.long	0
	.long	-1071251456
	.align 8
.LC2:
	.long	0
	.long	-1070465024
	.align 8
.LC3:
	.long	0
	.long	-1072168960
	.align 8
.LC4:
	.long	0
	.long	-1073741824
	.align 8
.LC5:
	.long	0
	.long	-1070333952
	.align 8
.LC6:
	.long	0
	.long	-1073217536
	.align 8
.LC7:
	.long	0
	.long	-1074790400
	.align 8
.LC8:
	.long	0
	.long	-1071906816
	.align 8
.LC9:
	.long	0
	.long	-1070989312
	.align 8
.LC10:
	.long	0
	.long	-1072431104
	.align 8
.LC11:
	.long	0
	.long	-1072693248
	.align 8
.LC12:
	.long	0
	.long	-1071644672
	.align 8
.LC13:
	.long	0
	.long	-1071120384
	.align 8
.LC14:
	.long	0
	.long	-1070530560
	.align 8
.LC15:
	.long	0
	.long	-1070596096
	.align 8
.LC16:
	.long	0
	.long	-1070858240
	.align 8
.LC17:
	.long	0
	.long	-1070727168
	.align 8
.LC18:
	.long	0
	.long	-1070399488
	.align 8
.LC19:
	.long	0
	.long	-1071513600
	.align 8
.LC20:
	.long	0
	.long	-1071382528
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"132952219.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dcmple
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 200
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, fp, lr}
	add	fp, sp, #12
	sub	sp, sp, #200
	bl	__VERIFIER_nondet_int
	str	r0, [fp, #-116]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-212]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-208]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-204]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-200]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-196]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-192]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-188]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-184]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-180]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-176]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-172]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-168]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-164]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-160]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-156]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-152]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-148]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-144]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-140]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-136]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-132]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-128]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-124]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-120]	@ float
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L484
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L4
	mov	r3, #0
	mov	r4, r3
.L4:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L5
	ldr	r3, [fp, #-180]
	cmp	r3, #0
	beq	.L6
.L5:
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L6
	ldr	r3, [fp, #-200]
	cmp	r3, #0
	bne	.L6
	ldr	r3, [fp, #-204]
	cmp	r3, #0
	bne	.L6
	ldr	r3, [fp, #-208]
	cmp	r3, #0
	bne	.L6
	mov	r3, #1
	b	.L8
.L6:
	mov	r3, #0
.L8:
	str	r3, [fp, #-112]
	b	.L9
.L279:
	ldr	r3, [fp, #-204]
	cmp	r3, #0
	beq	.L10
	ldr	r3, [fp, #-208]
	cmp	r3, #0
	beq	.L10
	bl	__VERIFIER_nondet_int
	str	r0, [fp, #-116]
	b	.L11
.L485:
	.align	2
.L484:
	.word	1077084160
	.word	-1074790400
	.word	-1072168960
	.word	-1070333952
	.word	-1072431104
	.word	-1073217536
	.word	-1070465024
	.word	-1072693248
	.word	-1071644672
	.word	-1071251456
	.word	-1071906816
	.word	-1070989312
.L10:
	ldr	r3, [fp, #-116]
	sub	r3, r3, #1
	str	r3, [fp, #-116]
.L11:
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-108]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-104]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-100]
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-96]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-92]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-88]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-84]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-80]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-76]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-72]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-68]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-64]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-60]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-56]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-52]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-48]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-44]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-40]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-36]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-32]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-28]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-24]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-20]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-16]	@ float
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L23
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L23:
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L35:
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L484+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L47:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L59:
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	b	.L487
.L488:
	.align	2
.L486:
	.word	-1071251456
	.word	-1071644672
	.word	-1070858240
	.word	-1070727168
	.word	-1072693248
	.word	-1070399488
	.word	-1070333952
	.word	-1073217536
	.word	-1071120384
	.word	-1071906816
	.word	-1070465024
	.word	-1070989312
	.word	-1071513600
	.word	-1070530560
	.word	-1072168960
	.word	-1070596096
	.word	-1074790400
	.word	-1071251456
.L487:
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L71
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L71:
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L83:
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L95
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L95:
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L486+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L107:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L119:
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	b	.L490
.L491:
	.align	2
.L489:
	.word	-1070989312
	.word	-1072431104
	.word	-1071251456
	.word	-1072168960
	.word	-1071120384
	.word	-1070530560
	.word	-1072693248
	.word	-1074790400
	.word	-1071644672
	.word	-1070727168
	.word	-1070596096
	.word	-1073217536
	.word	-1071382528
	.word	-1070858240
	.word	-1070465024
	.word	-1070333952
	.word	-1071513600
	.word	-1070399488
.L490:
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L131:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L143
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L143:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L489+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L155:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L167
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L167:
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L179:
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	b	.L493
.L494:
	.align	2
.L492:
	.word	-1072431104
	.word	-1070530560
	.word	-1071120384
	.word	-1071251456
	.word	-1073217536
	.word	-1070858240
	.word	-1072693248
	.word	-1074790400
	.word	-1072168960
	.word	-1072431104
	.word	-1071513600
	.word	-1070727168
	.word	-1070399488
	.word	-1071906816
	.word	-1071382528
	.word	-1070465024
	.word	-1070596096
	.word	-1070333952
	.word	-1070989312
.L493:
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L191
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L191:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-88]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L203:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L492+72
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L215
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L215:
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r0, [fp, #-164]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L227:
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-184]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-192]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-212]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L239
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L239:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	b	.L496
.L497:
	.align	2
.L495:
	.word	-1070727168
	.word	-1070333952
	.word	-1071382528
	.word	-1072431104
	.word	-1070530560
	.word	-1074790400
	.word	-1073217536
	.word	-1071251456
	.word	-1072168960
	.word	-1072693248
	.word	-1070989312
	.word	-1071906816
	.word	-1071644672
	.word	-1070858240
	.word	-1071120384
	.word	-1070465024
	.word	1077084160
.L496:
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-152]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-160]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-168]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
.L251:
	ldr	r3, [fp, #-76]
	cmp	r3, #0
	bne	.L253
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L495+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L254
	mov	r3, #0
	mov	r4, r3
.L254:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L255
.L253:
	mov	r2, #1
	b	.L256
.L255:
	mov	r2, #0
.L256:
	ldr	r3, [fp, #-180]
	cmp	r2, r3
	bne	.L12
	ldr	r3, [fp, #-96]
	cmp	r3, #0
	bne	.L257
	ldr	r0, [fp, #-84]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L495+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L258
	mov	r3, #0
	mov	r4, r3
.L258:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L259
.L257:
	mov	r2, #1
	b	.L260
.L259:
	mov	r2, #0
.L260:
	ldr	r3, [fp, #-200]
	cmp	r2, r3
	bne	.L12
	ldr	r3, [fp, #-204]
	cmp	r3, #0
	beq	.L261
	ldr	r3, [fp, #-208]
	cmp	r3, #0
	bne	.L262
.L261:
	ldr	r3, [fp, #-204]
	cmp	r3, #0
	beq	.L263
	ldr	r3, [fp, #-208]
	cmp	r3, #0
	bne	.L264
.L263:
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L495+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L265
	mov	r3, #0
	mov	r4, r3
.L265:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L264
	ldr	r0, [fp, #-172]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-176]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L266
	ldr	r3, [fp, #-180]
	cmp	r3, #0
	beq	.L264
.L266:
	ldr	r3, [fp, #-204]
	cmp	r3, #0
	beq	.L262
.L264:
	mov	r2, #1
	b	.L268
.L262:
	mov	r2, #0
.L268:
	ldr	r3, [fp, #-100]
	cmp	r2, r3
	bne	.L12
	ldr	r3, [fp, #-204]
	cmp	r3, #0
	beq	.L269
	ldr	r3, [fp, #-208]
	cmp	r3, #0
	bne	.L270
.L269:
	ldr	r3, [fp, #-204]
	cmp	r3, #0
	beq	.L271
	ldr	r3, [fp, #-208]
	cmp	r3, #0
	bne	.L272
.L271:
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L495+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L273
	mov	r3, #0
	mov	r4, r3
.L273:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L272
	ldr	r0, [fp, #-188]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-196]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L495+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L274
	ldr	r3, [fp, #-200]
	cmp	r3, #0
	beq	.L272
.L274:
	ldr	r3, [fp, #-208]
	cmp	r3, #0
	beq	.L270
.L272:
	mov	r2, #1
	b	.L276
.L270:
	mov	r2, #0
.L276:
	ldr	r3, [fp, #-104]
	cmp	r2, r3
	bne	.L12
	mov	r3, #1
	b	.L277
.L12:
	mov	r3, #0
.L277:
	str	r3, [fp, #-112]
	ldr	r3, [fp, #-108]	@ float
	str	r3, [fp, #-212]	@ float
	ldr	r3, [fp, #-104]
	str	r3, [fp, #-208]
	ldr	r3, [fp, #-100]
	str	r3, [fp, #-204]
	ldr	r3, [fp, #-96]
	str	r3, [fp, #-200]
	ldr	r3, [fp, #-92]	@ float
	str	r3, [fp, #-196]	@ float
	ldr	r3, [fp, #-88]	@ float
	str	r3, [fp, #-192]	@ float
	ldr	r3, [fp, #-84]	@ float
	str	r3, [fp, #-188]	@ float
	ldr	r3, [fp, #-80]	@ float
	str	r3, [fp, #-184]	@ float
	ldr	r3, [fp, #-76]
	str	r3, [fp, #-180]
	ldr	r3, [fp, #-72]	@ float
	str	r3, [fp, #-176]	@ float
	ldr	r3, [fp, #-68]	@ float
	str	r3, [fp, #-172]	@ float
	ldr	r3, [fp, #-64]	@ float
	str	r3, [fp, #-168]	@ float
	ldr	r3, [fp, #-60]	@ float
	str	r3, [fp, #-164]	@ float
	ldr	r3, [fp, #-56]	@ float
	str	r3, [fp, #-160]	@ float
	ldr	r3, [fp, #-52]	@ float
	str	r3, [fp, #-156]	@ float
	ldr	r3, [fp, #-48]	@ float
	str	r3, [fp, #-152]	@ float
	ldr	r3, [fp, #-44]	@ float
	str	r3, [fp, #-148]	@ float
	ldr	r3, [fp, #-40]	@ float
	str	r3, [fp, #-144]	@ float
	ldr	r3, [fp, #-36]	@ float
	str	r3, [fp, #-140]	@ float
	ldr	r3, [fp, #-32]	@ float
	str	r3, [fp, #-136]	@ float
	ldr	r3, [fp, #-28]	@ float
	str	r3, [fp, #-132]	@ float
	ldr	r3, [fp, #-24]	@ float
	str	r3, [fp, #-128]	@ float
	ldr	r3, [fp, #-20]	@ float
	str	r3, [fp, #-124]	@ float
	ldr	r3, [fp, #-16]	@ float
	str	r3, [fp, #-120]	@ float
.L9:
	ldr	r3, [fp, #-116]
	cmp	r3, #0
	blt	.L278
	ldr	r3, [fp, #-112]
	cmp	r3, #0
	bne	.L279
.L278:
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #12
	@ sp needed
	pop	{r4, r5, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
