	.file	"179830256.c"
	.intel_syntax noprefix
	.text
	.globl	advanceBiasedClockByMicroseconds
	.type	advanceBiasedClockByMicroseconds, @function
advanceBiasedClockByMicroseconds:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -56[rbp], rdi
	mov	DWORD PTR -60[rbp], esi
	mov	eax, DWORD PTR -60[rbp]
	imul	rax, rax, 180
	mov	QWORD PTR -32[rbp], rax
	mov	rax, QWORD PTR -56[rbp]
	movzx	eax, WORD PTR [rax]
	movsx	rdx, ax
	mov	eax, DWORD PTR -60[rbp]
	imul	rax, rdx
	imul	rax, rax, 180
	mov	QWORD PTR -24[rbp], rax
	mov	rax, QWORD PTR -56[rbp]
	mov	eax, DWORD PTR 16[rax]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	QWORD PTR -16[rbp], rax
	mov	rcx, QWORD PTR -16[rbp]
	movabs	rdx, 1237940039285380275
	mov	rax, rcx
	imul	rdx
	mov	rax, rdx
	sar	rax, 26
	sar	rcx, 63
	mov	rdx, rcx
	sub	rax, rdx
	mov	DWORD PTR -40[rbp], eax
	mov	rcx, QWORD PTR -16[rbp]
	movabs	rdx, 1237940039285380275
	mov	rax, rcx
	imul	rdx
	mov	rax, rdx
	sar	rax, 26
	mov	rdx, rcx
	sar	rdx, 63
	sub	rax, rdx
	imul	rdx, rax, 1000000000
	mov	rax, rcx
	sub	rax, rdx
	mov	DWORD PTR -36[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	mov	QWORD PTR 8[rax], rdx
	mov	rax, QWORD PTR -56[rbp]
	mov	edx, DWORD PTR -36[rbp]
	mov	DWORD PTR 16[rax], edx
	mov	rax, QWORD PTR -8[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	advanceBiasedClockByMicroseconds, .-advanceBiasedClockByMicroseconds
	.globl	advanceAdjustableClockByCycles
	.type	advanceAdjustableClockByCycles, @function
advanceAdjustableClockByCycles:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 80
	mov	QWORD PTR -72[rbp], rdi
	mov	QWORD PTR -80[rbp], rsi
	jmp	.L4
.L5:
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, 180000
	mov	rdi, rax
	call	advanceAdjustableClockByCycles
	sub	QWORD PTR -80[rbp], 180000
.L4:
	cmp	QWORD PTR -80[rbp], 180000
	ja	.L5
	mov	rax, QWORD PTR -72[rbp]
	movzx	eax, WORD PTR 18[rax]
	movsx	rdx, ax
	mov	rax, QWORD PTR -80[rbp]
	add	rax, rdx
	mov	QWORD PTR -32[rbp], rax
	mov	rax, QWORD PTR -72[rbp]
	movzx	eax, WORD PTR 16[rax]
	movsx	rdx, ax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	movabs	rdx, 3279421168659475843
	mul	rdx
	mov	rax, rdx
	shr	rax, 5
	mov	QWORD PTR -24[rbp], rax
	mov	rax, QWORD PTR -72[rbp]
	movzx	eax, WORD PTR 16[rax]
	movsx	rdx, ax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	rcx, rax
	movabs	rdx, 3279421168659475843
	mov	rax, rcx
	mul	rdx
	mov	rax, rdx
	shr	rax, 5
	imul	rdx, rax, 180
	mov	rax, rcx
	sub	rax, rdx
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -72[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -8[rbp]
	movabs	rdx, 3777893186295716171
	mul	rdx
	mov	rcx, rdx
	shr	rcx, 11
	mov	rax, rcx
	shr	rax, 2
	movabs	rdx, 2951479051793528259
	mul	rdx
	shr	rdx, 2
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, 0[0+rax*4]
	add	rax, rdx
	sal	rax, 2
	sub	rcx, rax
	mov	rdx, rcx
	mov	BYTE PTR -55[rbp], dl
	mov	rax, QWORD PTR -72[rbp]
	mov	rax, QWORD PTR 8[rax]
	movabs	rdx, 3777893186295716171
	mul	rdx
	mov	rcx, rdx
	shr	rcx, 11
	mov	rax, rcx
	shr	rax, 2
	movabs	rdx, 2951479051793528259
	mul	rdx
	shr	rdx, 2
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, 0[0+rax*4]
	add	rax, rdx
	sal	rax, 2
	sub	rcx, rax
	mov	rdx, rcx
	mov	DWORD PTR -40[rbp], edx
	mov	rax, QWORD PTR -72[rbp]
	movzx	eax, WORD PTR [rax]
	cwde
	mov	DWORD PTR -36[rbp], eax
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	imul	rdx, rdx, 1374389535
	shr	rdx, 32
	sar	edx, 5
	sar	eax, 31
	mov	ecx, eax
	mov	eax, edx
	sub	eax, ecx
	mov	DWORD PTR -52[rbp], eax
	mov	eax, DWORD PTR -52[rbp]
	imul	edx, eax, -100
	mov	eax, DWORD PTR -36[rbp]
	add	eax, edx
	mov	DWORD PTR -48[rbp], eax
	cmp	DWORD PTR -48[rbp], 0
	jns	.L6
	sub	DWORD PTR -52[rbp], 1
	add	DWORD PTR -48[rbp], 100
.L6:
	mov	eax, DWORD PTR -48[rbp]
	movsx	rdx, eax
	imul	rdx, rdx, 1717986919
	shr	rdx, 32
	sar	edx, 2
	sar	eax, 31
	mov	ecx, eax
	mov	eax, edx
	sub	eax, ecx
	mov	BYTE PTR -54[rbp], al
	mov	ecx, DWORD PTR -48[rbp]
	movsx	rax, ecx
	imul	rax, rax, 1717986919
	shr	rax, 32
	sar	eax, 2
	mov	esi, ecx
	sar	esi, 31
	sub	eax, esi
	mov	edx, eax
	mov	eax, edx
	sal	eax, 2
	add	eax, edx
	add	eax, eax
	sub	ecx, eax
	mov	edx, ecx
	mov	BYTE PTR -53[rbp], dl
	movzx	eax, BYTE PTR -55[rbp]
	cmp	DWORD PTR -40[rbp], eax
	je	.L7
	mov	eax, DWORD PTR -52[rbp]
	mov	DWORD PTR -44[rbp], eax
	movzx	ecx, BYTE PTR -55[rbp]
	movzx	edx, cl
	mov	eax, edx
	sal	eax, 2
	add	eax, edx
	sal	eax, 3
	add	eax, edx
	lea	edx, 0[0+rax*4]
	add	eax, edx
	shr	ax, 8
	mov	edx, eax
	shr	dl, 3
	mov	eax, edx
	sal	eax, 2
	add	eax, edx
	add	eax, eax
	sub	ecx, eax
	mov	edx, ecx
	cmp	BYTE PTR -54[rbp], dl
	jbe	.L8
	add	DWORD PTR -44[rbp], 1
.L8:
	movzx	ecx, BYTE PTR -55[rbp]
	movzx	edx, cl
	mov	eax, edx
	sal	eax, 2
	add	eax, edx
	sal	eax, 3
	add	eax, edx
	lea	edx, 0[0+rax*4]
	add	eax, edx
	shr	ax, 8
	mov	edx, eax
	shr	dl, 3
	mov	eax, edx
	sal	eax, 2
	add	eax, edx
	add	eax, eax
	sub	ecx, eax
	mov	edx, ecx
	cmp	dl, 9
	jne	.L9
	movzx	eax, BYTE PTR -55[rbp]
	movzx	edx, al
	mov	eax, edx
	sal	eax, 2
	add	eax, edx
	sal	eax, 3
	add	eax, edx
	lea	edx, 0[0+rax*4]
	add	eax, edx
	shr	ax, 8
	shr	al, 3
	cmp	BYTE PTR -53[rbp], al
	jbe	.L9
	add	DWORD PTR -44[rbp], 1
	jmp	.L9
.L7:
	mov	DWORD PTR -44[rbp], 0
.L9:
	mov	eax, DWORD PTR -44[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -72[rbp]
	mov	WORD PTR 18[rax], dx
	mov	rax, QWORD PTR -72[rbp]
	mov	rdx, QWORD PTR -8[rbp]
	mov	QWORD PTR 8[rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -72[rbp]
	mov	WORD PTR 16[rax], dx
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	advanceAdjustableClockByCycles, .-advanceAdjustableClockByCycles
	.section	.rodata
	.align 8
.LC0:
	.string	"CrystalSim test 1, before timeCycles: %ld\n"
	.align 8
.LC1:
	.string	"CrystalSim test 1, after, timeCycles %ld\n"
	.align 8
.LC2:
	.string	"CrystalSim test 2, before timeCycles: %ld\n"
	.align 8
.LC3:
	.string	"CrystalSim test 2, after, timeCycles %ld\n"
	.align 8
.LC4:
	.string	"CrystalSim test 3, before timeCycles: %ld\n"
	.align 8
.LC5:
	.string	"CrystalSim test 3, after, timeCycles %ld\n"
	.align 8
.LC6:
	.string	"AdjustableClock test 1, before, timeMicroseconds %ld\n"
	.align 8
.LC7:
	.string	"AdjustableClock test 1, after, timeMicroseconds %ld\n"
	.align 8
.LC8:
	.string	"AdjustableClock test 2, before, timeMicroseconds %ld\n"
	.align 8
.LC9:
	.string	"AdjustableClock test 2, after, timeMicroseconds %ld\n"
	.text
	.globl	main
	.type	main, @function
main:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	QWORD PTR -32[rbp], 0
	mov	QWORD PTR -24[rbp], 0
	mov	QWORD PTR -16[rbp], 0
	mov	WORD PTR -32[rbp], 1000
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC0[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rax, -32[rbp]
	mov	esi, 1000000
	mov	rdi, rax
	call	advanceBiasedClockByMicroseconds
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC1[rip]
	mov	eax, 0
	call	printf@PLT
	mov	QWORD PTR -32[rbp], 0
	mov	QWORD PTR -24[rbp], 0
	mov	QWORD PTR -16[rbp], 0
	mov	WORD PTR -32[rbp], 1000
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC2[rip]
	mov	eax, 0
	call	printf@PLT
	mov	QWORD PTR -56[rbp], 0
	jmp	.L11
.L12:
	lea	rax, -32[rbp]
	mov	esi, 100
	mov	rdi, rax
	call	advanceBiasedClockByMicroseconds
	add	QWORD PTR -56[rbp], 1
.L11:
	cmp	QWORD PTR -56[rbp], 9999
	jbe	.L12
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC3[rip]
	mov	eax, 0
	call	printf@PLT
	mov	QWORD PTR -32[rbp], 0
	mov	QWORD PTR -24[rbp], 0
	mov	QWORD PTR -16[rbp], 0
	mov	WORD PTR -32[rbp], 1000
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC4[rip]
	mov	eax, 0
	call	printf@PLT
	mov	QWORD PTR -48[rbp], 0
	jmp	.L13
.L14:
	lea	rax, -32[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	advanceBiasedClockByMicroseconds
	add	QWORD PTR -48[rbp], 1
.L13:
	cmp	QWORD PTR -48[rbp], 999999
	jbe	.L14
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC5[rip]
	mov	eax, 0
	call	printf@PLT
	mov	QWORD PTR -32[rbp], 0
	mov	QWORD PTR -24[rbp], 0
	mov	QWORD PTR -16[rbp], 0
	mov	WORD PTR -32[rbp], 180
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC6[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rax, -32[rbp]
	mov	esi, 1800000000
	mov	rdi, rax
	call	advanceAdjustableClockByCycles
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC7[rip]
	mov	eax, 0
	call	printf@PLT
	mov	QWORD PTR -32[rbp], 0
	mov	QWORD PTR -24[rbp], 0
	mov	QWORD PTR -16[rbp], 0
	mov	WORD PTR -32[rbp], 180
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC8[rip]
	mov	eax, 0
	call	printf@PLT
	mov	QWORD PTR -40[rbp], 0
	jmp	.L15
.L16:
	lea	rax, -32[rbp]
	mov	esi, 100
	mov	rdi, rax
	call	advanceAdjustableClockByCycles
	add	QWORD PTR -40[rbp], 1
.L15:
	cmp	QWORD PTR -40[rbp], 17999999
	jbe	.L16
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	lea	rdi, .LC9[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, 0
	mov	rdx, QWORD PTR -8[rbp]
	sub	rdx, QWORD PTR fs:40
	je	.L18
	call	__stack_chk_fail@PLT
.L18:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"179830256.c"
	.text
	.global	__aeabi_ldivmod
	.align	2
	.global	advanceBiasedClockByMicroseconds
	.syntax unified
	.arm
	.fpu softvfp
	.type	advanceBiasedClockByMicroseconds, %function
advanceBiasedClockByMicroseconds:
	@ args = 0, pretend = 0, frame = 64
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #64
	str	r0, [fp, #-72]
	str	r1, [fp, #-76]
	ldr	r3, [fp, #-76]
	mov	r2, r3
	mov	r3, #0
	mov	r0, r2
	mov	r1, r3
	adds	r4, r0, r0
	adc	r5, r1, r1
	mov	r0, r4
	mov	r1, r5
	adds	r0, r0, r2
	adc	r1, r1, r3
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #4
	orr	r3, r3, r0, lsr #28
	lsl	r2, r0, #4
	subs	r2, r2, r0
	sbc	r3, r3, r1
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #2
	orr	r1, r1, r2, lsr #30
	lsl	r0, r2, #2
	mov	r2, r0
	mov	r3, r1
	str	r2, [fp, #-60]
	str	r3, [fp, #-56]
	ldr	r3, [fp, #-72]
	ldrsh	r3, [r3]
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-76]
	mov	r2, r3
	mov	r3, #0
	mul	r0, r2, r5
	mul	r1, r4, r3
	add	ip, r0, r1
	umull	r0, r1, r4, r2
	add	r3, ip, r1
	mov	r1, r3
	mov	r2, r0
	mov	r3, r1
	adds	ip, r2, r2
	str	ip, [fp, #-84]
	adc	r3, r3, r3
	str	r3, [fp, #-80]
	sub	r3, fp, #84
	ldmia	r3, {r2-r3}
	adds	r2, r2, r0
	adc	r3, r3, r1
	mov	r0, #0
	mov	r1, #0
	lsl	r1, r3, #4
	orr	r1, r1, r2, lsr #28
	lsl	r0, r2, #4
	subs	r0, r0, r2
	sbc	r1, r1, r3
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #2
	orr	r3, r3, r0, lsr #30
	lsl	r2, r0, #2
	mov	r0, r2
	mov	r1, r3
	mov	r2, r0
	mov	r3, r1
	str	r2, [fp, #-52]
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-72]
	ldr	r3, [r3, #16]
	mov	r2, r3
	asr	r3, r2, #31
	sub	r1, fp, #52
	ldmia	r1, {r0-r1}
	adds	ip, r0, r2
	str	ip, [fp, #-92]
	adc	r3, r1, r3
	str	r3, [fp, #-88]
	sub	r4, fp, #92
	ldmia	r4, {r3-r4}
	str	r3, [fp, #-44]
	str	r4, [fp, #-40]
	sub	r1, fp, #44
	ldmia	r1, {r0-r1}
	adr	r3, .L3
	ldmia	r3, {r2-r3}
	bl	__aeabi_ldivmod
	mov	r2, r0
	mov	r3, r1
	mov	r3, r2
	str	r3, [fp, #-68]
	sub	r1, fp, #44
	ldmia	r1, {r0-r1}
	adr	r3, .L3
	ldmia	r3, {r2-r3}
	bl	__aeabi_ldivmod
	mov	r3, r2
	str	r3, [fp, #-64]
	ldr	r3, [fp, #-68]
	mov	r2, r3
	asr	r3, r2, #31
	sub	r1, fp, #60
	ldmia	r1, {r0-r1}
	adds	r8, r0, r2
	adc	r9, r1, r3
	str	r8, [fp, #-36]
	str	r9, [fp, #-32]
	ldr	r3, [fp, #-72]
	add	r1, r3, #8
	ldmia	r1, {r0-r1}
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	adds	r6, r0, r2
	adc	r7, r1, r3
	ldr	r3, [fp, #-72]
	str	r6, [r3, #8]
	str	r7, [r3, #12]
	ldr	r3, [fp, #-72]
	ldr	r2, [fp, #-64]
	str	r2, [r3, #16]
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
.L4:
	.align	3
.L3:
	.word	1000000000
	.word	0
	.size	advanceBiasedClockByMicroseconds, .-advanceBiasedClockByMicroseconds
	.global	__aeabi_uldivmod
	.align	2
	.global	advanceAdjustableClockByCycles
	.syntax unified
	.arm
	.fpu softvfp
	.type	advanceAdjustableClockByCycles, %function
advanceAdjustableClockByCycles:
	@ args = 0, pretend = 0, frame = 88
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #88
	str	r0, [fp, #-88]
	str	r2, [fp, #-100]
	str	r3, [fp, #-96]
	b	.L6
.L7:
	ldr	r2, .L12+8
	mov	r3, #0
	ldr	r0, [fp, #-88]
	bl	advanceAdjustableClockByCycles
	sub	r3, fp, #100
	ldmia	r3, {r2-r3}
	adr	r1, .L12
	ldmia	r1, {r0-r1}
	adds	r8, r2, r0
	adc	r9, r3, r1
	str	r8, [fp, #-100]
	str	r9, [fp, #-96]
.L6:
	sub	r3, fp, #100
	ldmia	r3, {r2-r3}
	ldr	r0, .L12+8
	mov	r1, #0
	cmp	r3, r1
	cmpeq	r2, r0
	bhi	.L7
	ldr	r3, [fp, #-88]
	ldrsh	r3, [r3, #18]
	mov	r0, r3
	asr	r1, r0, #31
	sub	r3, fp, #100
	ldmia	r3, {r2-r3}
	adds	r6, r0, r2
	adc	r7, r1, r3
	str	r6, [fp, #-60]
	str	r7, [fp, #-56]
	ldr	r3, [fp, #-88]
	ldrsh	r3, [r3, #16]
	mov	r0, r3
	asr	r1, r0, #31
	sub	r3, fp, #60
	ldmia	r3, {r2-r3}
	adds	ip, r0, r2
	str	ip, [fp, #-108]
	adc	r3, r1, r3
	str	r3, [fp, #-104]
	sub	r1, fp, #108
	ldmia	r1, {r0-r1}
	mov	r2, #180
	mov	r3, #0
	bl	__aeabi_uldivmod
	mov	r2, r0
	mov	r3, r1
	str	r2, [fp, #-52]
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-88]
	ldrsh	r3, [r3, #16]
	mov	r0, r3
	asr	r1, r0, #31
	sub	r3, fp, #60
	ldmia	r3, {r2-r3}
	adds	ip, r0, r2
	str	ip, [fp, #-116]
	adc	r3, r1, r3
	str	r3, [fp, #-112]
	sub	r1, fp, #116
	ldmia	r1, {r0-r1}
	mov	r2, #180
	mov	r3, #0
	bl	__aeabi_uldivmod
	str	r2, [fp, #-44]
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-88]
	add	r1, r3, #8
	ldmia	r1, {r0-r1}
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	adds	r4, r0, r2
	adc	r5, r1, r3
	str	r4, [fp, #-36]
	str	r5, [fp, #-32]
	sub	r1, fp, #36
	ldmia	r1, {r0-r1}
	ldr	r2, .L12+12
	mov	r3, #0
	bl	__aeabi_uldivmod
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #100
	mov	r3, #0
	bl	__aeabi_uldivmod
	mov	r3, r2
	strb	r3, [fp, #-83]
	ldr	r3, [fp, #-88]
	add	r1, r3, #8
	ldmia	r1, {r0-r1}
	ldr	r2, .L12+12
	mov	r3, #0
	bl	__aeabi_uldivmod
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #100
	mov	r3, #0
	bl	__aeabi_uldivmod
	mov	r3, r2
	str	r3, [fp, #-68]
	ldr	r3, [fp, #-88]
	ldrsh	r3, [r3]
	str	r3, [fp, #-64]
	ldr	r3, [fp, #-64]
	ldr	r2, .L12+16
	smull	r1, r2, r3, r2
	asr	r2, r2, #5
	asr	r3, r3, #31
	sub	r3, r2, r3
	str	r3, [fp, #-80]
	ldr	r3, [fp, #-80]
	mvn	r2, #99
	mul	r3, r2, r3
	ldr	r2, [fp, #-64]
	add	r3, r2, r3
	str	r3, [fp, #-76]
	ldr	r3, [fp, #-76]
	cmp	r3, #0
	bge	.L8
	ldr	r3, [fp, #-80]
	sub	r3, r3, #1
	str	r3, [fp, #-80]
	ldr	r3, [fp, #-76]
	add	r3, r3, #100
	str	r3, [fp, #-76]
.L8:
	ldr	r3, [fp, #-76]
	ldr	r2, .L12+20
	smull	r1, r2, r3, r2
	asr	r2, r2, #2
	asr	r3, r3, #31
	sub	r3, r2, r3
	strb	r3, [fp, #-82]
	ldr	r2, [fp, #-76]
	ldr	r3, .L12+20
	smull	r1, r3, r2, r3
	asr	r1, r3, #2
	asr	r3, r2, #31
	sub	r1, r1, r3
	mov	r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r1
	lsl	r3, r3, #1
	sub	r1, r2, r3
	mov	r3, r1
	strb	r3, [fp, #-81]
	ldrb	r3, [fp, #-83]	@ zero_extendqisi2
	ldr	r2, [fp, #-68]
	cmp	r2, r3
	beq	.L9
	ldr	r3, [fp, #-80]
	str	r3, [fp, #-72]
	ldrb	r2, [fp, #-83]	@ zero_extendqisi2
	ldr	r3, .L12+24
	umull	r1, r3, r2, r3
	lsr	r1, r3, #3
	mov	r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r1
	lsl	r3, r3, #1
	sub	r3, r2, r3
	and	r3, r3, #255
	ldrb	r2, [fp, #-82]	@ zero_extendqisi2
	cmp	r2, r3
	bls	.L10
	ldr	r3, [fp, #-72]
	add	r3, r3, #1
	str	r3, [fp, #-72]
.L10:
	ldrb	r2, [fp, #-83]	@ zero_extendqisi2
	ldr	r3, .L12+24
	umull	r1, r3, r2, r3
	lsr	r1, r3, #3
	mov	r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r1
	lsl	r3, r3, #1
	sub	r3, r2, r3
	and	r3, r3, #255
	cmp	r3, #9
	bne	.L11
	ldrb	r3, [fp, #-83]	@ zero_extendqisi2
	ldr	r2, .L12+24
	umull	r1, r3, r2, r3
	lsr	r3, r3, #3
	and	r3, r3, #255
	ldrb	r2, [fp, #-81]	@ zero_extendqisi2
	cmp	r2, r3
	bls	.L11
	ldr	r3, [fp, #-72]
	add	r3, r3, #1
	str	r3, [fp, #-72]
	b	.L11
.L9:
	mov	r3, #0
	str	r3, [fp, #-72]
.L11:
	ldr	r3, [fp, #-72]
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-88]
	strh	r2, [r3, #18]	@ movhi
	ldr	r1, [fp, #-88]
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	str	r2, [r1, #8]
	str	r3, [r1, #12]
	ldrsh	r2, [fp, #-44]
	ldr	r3, [fp, #-88]
	strh	r2, [r3, #16]	@ movhi
	nop
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
.L13:
	.align	3
.L12:
	.word	-180000
	.word	-1
	.word	180000
	.word	10000
	.word	1374389535
	.word	1717986919
	.word	-858993459
	.size	advanceAdjustableClockByCycles, .-advanceAdjustableClockByCycles
	.section	.rodata
	.align	2
.LC0:
	.ascii	"CrystalSim test 1, before timeCycles: %lld\012\000"
	.align	2
.LC1:
	.ascii	"CrystalSim test 1, after, timeCycles %lld\012\000"
	.align	2
.LC2:
	.ascii	"CrystalSim test 2, before timeCycles: %lld\012\000"
	.align	2
.LC3:
	.ascii	"CrystalSim test 2, after, timeCycles %lld\012\000"
	.align	2
.LC4:
	.ascii	"CrystalSim test 3, before timeCycles: %lld\012\000"
	.align	2
.LC5:
	.ascii	"CrystalSim test 3, after, timeCycles %lld\012\000"
	.align	2
.LC6:
	.ascii	"AdjustableClock test 1, before, timeMicroseconds %l"
	.ascii	"ld\012\000"
	.align	2
.LC7:
	.ascii	"AdjustableClock test 1, after, timeMicroseconds %ll"
	.ascii	"d\012\000"
	.align	2
.LC8:
	.ascii	"AdjustableClock test 2, before, timeMicroseconds %l"
	.ascii	"ld\012\000"
	.align	2
.LC9:
	.ascii	"AdjustableClock test 2, after, timeMicroseconds %ll"
	.ascii	"d\012\000"
	.align	2
.LC10:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 56
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #56
	ldr	r3, .L23+16
	ldr	r3, [r3]
	str	r3, [fp, #-32]
	mov	r3,#0
	sub	r3, fp, #60
	mov	r2, #0
	str	r2, [r3]
	str	r2, [r3, #4]
	str	r2, [r3, #8]
	str	r2, [r3, #12]
	str	r2, [r3, #16]
	str	r2, [r3, #20]
	mov	r3, #1000
	strh	r3, [fp, #-60]	@ movhi
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+20
	bl	printf
	sub	r3, fp, #60
	ldr	r1, .L23+24
	mov	r0, r3
	bl	advanceBiasedClockByMicroseconds
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+28
	bl	printf
	sub	r3, fp, #60
	mov	r2, #0
	str	r2, [r3]
	str	r2, [r3, #4]
	str	r2, [r3, #8]
	str	r2, [r3, #12]
	str	r2, [r3, #16]
	str	r2, [r3, #20]
	mov	r3, #1000
	strh	r3, [fp, #-60]	@ movhi
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+32
	bl	printf
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-84]
	str	r3, [fp, #-80]
	b	.L15
.L16:
	sub	r3, fp, #60
	mov	r1, #100
	mov	r0, r3
	bl	advanceBiasedClockByMicroseconds
	sub	r3, fp, #84
	ldmia	r3, {r2-r3}
	adds	r8, r2, #1
	adc	r9, r3, #0
	str	r8, [fp, #-84]
	str	r9, [fp, #-80]
.L15:
	sub	r3, fp, #84
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+36
	mov	r1, #0
	cmp	r3, r1
	cmpeq	r2, r0
	bls	.L16
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+40
	bl	printf
	sub	r3, fp, #60
	mov	r2, #0
	str	r2, [r3]
	str	r2, [r3, #4]
	str	r2, [r3, #8]
	str	r2, [r3, #12]
	str	r2, [r3, #16]
	str	r2, [r3, #20]
	mov	r3, #1000
	strh	r3, [fp, #-60]	@ movhi
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+44
	bl	printf
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-76]
	str	r3, [fp, #-72]
	b	.L17
.L18:
	sub	r3, fp, #60
	mov	r1, #1
	mov	r0, r3
	bl	advanceBiasedClockByMicroseconds
	sub	r3, fp, #76
	ldmia	r3, {r2-r3}
	adds	r6, r2, #1
	adc	r7, r3, #0
	str	r6, [fp, #-76]
	str	r7, [fp, #-72]
.L17:
	sub	r3, fp, #76
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+24
	mov	r1, #0
	cmp	r3, r1
	cmpeq	r2, r0
	bcc	.L18
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+48
	bl	printf
	sub	r3, fp, #60
	mov	r2, #0
	str	r2, [r3]
	str	r2, [r3, #4]
	str	r2, [r3, #8]
	str	r2, [r3, #12]
	str	r2, [r3, #16]
	str	r2, [r3, #20]
	mov	r3, #180
	strh	r3, [fp, #-60]	@ movhi
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+52
	bl	printf
	sub	r1, fp, #60
	adr	r3, .L23
	ldmia	r3, {r2-r3}
	mov	r0, r1
	bl	advanceAdjustableClockByCycles
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+56
	bl	printf
	sub	r3, fp, #60
	mov	r2, #0
	str	r2, [r3]
	str	r2, [r3, #4]
	str	r2, [r3, #8]
	str	r2, [r3, #12]
	str	r2, [r3, #16]
	str	r2, [r3, #20]
	mov	r3, #180
	strh	r3, [fp, #-60]	@ movhi
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+60
	bl	printf
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-68]
	str	r3, [fp, #-64]
	b	.L19
.L20:
	sub	r1, fp, #60
	mov	r2, #100
	mov	r3, #0
	mov	r0, r1
	bl	advanceAdjustableClockByCycles
	sub	r3, fp, #68
	ldmia	r3, {r2-r3}
	adds	r4, r2, #1
	adc	r5, r3, #0
	str	r4, [fp, #-68]
	str	r5, [fp, #-64]
.L19:
	sub	r3, fp, #68
	ldmia	r3, {r2-r3}
	adr	r1, .L23+8
	ldmia	r1, {r0-r1}
	cmp	r3, r1
	cmpeq	r2, r0
	bls	.L20
	sub	r3, fp, #52
	ldmia	r3, {r2-r3}
	ldr	r0, .L23+64
	bl	printf
	mov	r3, #0
	ldr	r2, .L23+16
	ldr	r1, [r2]
	ldr	r2, [fp, #-32]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L22
	bl	__stack_chk_fail
.L22:
	mov	r0, r3
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
.L24:
	.align	3
.L23:
	.word	1800000000
	.word	0
	.word	17999999
	.word	0
	.word	.LC10
	.word	.LC0
	.word	1000000
	.word	.LC1
	.word	.LC2
	.word	9999
	.word	.LC3
	.word	.LC4
	.word	.LC5
	.word	.LC6
	.word	.LC7
	.word	.LC8
	.word	.LC9
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
