	.file	"895907.c"
	.intel_syntax noprefix
	.text
	.type	ssim_4x4x2_core, @function
ssim_4x4x2_core:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -56[rbp], rdi
	mov	QWORD PTR -64[rbp], rsi
	mov	QWORD PTR -72[rbp], rdx
	mov	QWORD PTR -80[rbp], rcx
	mov	QWORD PTR -88[rbp], r8
	mov	DWORD PTR -28[rbp], 0
	jmp	.L2
.L7:
	mov	DWORD PTR -24[rbp], 0
	mov	DWORD PTR -20[rbp], 0
	mov	DWORD PTR -16[rbp], 0
	mov	DWORD PTR -12[rbp], 0
	mov	DWORD PTR -32[rbp], 0
	jmp	.L3
.L6:
	mov	DWORD PTR -36[rbp], 0
	jmp	.L4
.L5:
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -32[rbp]
	cdqe
	imul	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -32[rbp]
	cdqe
	imul	rax, QWORD PTR -80[rbp]
	add	rax, rdx
	mov	rdx, rax
	mov	rax, QWORD PTR -72[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -8[rbp]
	add	DWORD PTR -24[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	add	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR -8[rbp]
	imul	eax, eax
	add	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	imul	eax, eax
	add	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -8[rbp]
	imul	eax, DWORD PTR -4[rbp]
	add	DWORD PTR -12[rbp], eax
	add	DWORD PTR -36[rbp], 1
.L4:
	cmp	DWORD PTR -36[rbp], 3
	jle	.L5
	add	DWORD PTR -32[rbp], 1
.L3:
	cmp	DWORD PTR -32[rbp], 3
	jle	.L6
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -88[rbp]
	add	rdx, rax
	mov	eax, DWORD PTR -24[rbp]
	mov	DWORD PTR [rdx], eax
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -88[rbp]
	add	rdx, rax
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR 4[rdx], eax
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -88[rbp]
	add	rdx, rax
	mov	eax, DWORD PTR -16[rbp]
	mov	DWORD PTR 8[rdx], eax
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -88[rbp]
	add	rdx, rax
	mov	eax, DWORD PTR -12[rbp]
	mov	DWORD PTR 12[rdx], eax
	add	QWORD PTR -56[rbp], 4
	add	QWORD PTR -72[rbp], 4
	add	DWORD PTR -28[rbp], 1
.L2:
	cmp	DWORD PTR -28[rbp], 1
	jle	.L7
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	ssim_4x4x2_core, .-ssim_4x4x2_core
	.type	ssim_end1, @function
ssim_end1:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -36[rbp], edi
	mov	DWORD PTR -40[rbp], esi
	mov	DWORD PTR -44[rbp], edx
	mov	DWORD PTR -48[rbp], ecx
	mov	eax, DWORD PTR -36[rbp]
	mov	DWORD PTR -24[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	mov	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR -44[rbp]
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -48[rbp]
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR -16[rbp]
	sal	eax, 6
	mov	edx, eax
	mov	eax, DWORD PTR -24[rbp]
	imul	eax, eax
	sub	edx, eax
	mov	eax, DWORD PTR -20[rbp]
	imul	eax, eax
	mov	ecx, eax
	mov	eax, edx
	sub	eax, ecx
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	sal	eax, 6
	mov	edx, eax
	mov	eax, DWORD PTR -24[rbp]
	imul	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	mov	eax, edx
	sub	eax, ecx
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -24[rbp]
	imul	eax, DWORD PTR -20[rbp]
	lea	edx, [rax+rax]
	mov	eax, DWORD PTR ssim_c1.1[rip]
	add	eax, edx
	pxor	xmm1, xmm1
	cvtsi2ss	xmm1, eax
	mov	eax, DWORD PTR -4[rbp]
	lea	edx, [rax+rax]
	mov	eax, DWORD PTR ssim_c2.0[rip]
	add	eax, edx
	pxor	xmm0, xmm0
	cvtsi2ss	xmm0, eax
	mulss	xmm0, xmm1
	mov	eax, DWORD PTR -24[rbp]
	imul	eax, eax
	mov	edx, eax
	mov	eax, DWORD PTR -20[rbp]
	imul	eax, eax
	add	edx, eax
	mov	eax, DWORD PTR ssim_c1.1[rip]
	add	eax, edx
	pxor	xmm2, xmm2
	cvtsi2ss	xmm2, eax
	mov	edx, DWORD PTR ssim_c2.0[rip]
	mov	eax, DWORD PTR -8[rbp]
	add	eax, edx
	pxor	xmm1, xmm1
	cvtsi2ss	xmm1, eax
	mulss	xmm1, xmm2
	divss	xmm0, xmm1
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	ssim_end1, .-ssim_end1
	.type	ssim_end4, @function
ssim_end4:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 40
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -36[rbp], edx
	pxor	xmm0, xmm0
	movss	DWORD PTR -8[rbp], xmm0
	mov	DWORD PTR -4[rbp], 0
	jmp	.L11
.L12:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	sal	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	edx, DWORD PTR 12[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 1
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rcx
	mov	eax, DWORD PTR 12[rax]
	add	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rcx
	mov	eax, DWORD PTR 12[rax]
	add	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 1
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rcx
	mov	eax, DWORD PTR 12[rax]
	lea	ecx, [rdx+rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	sal	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	edx, DWORD PTR 8[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 1
	sal	rax, 4
	mov	rsi, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rsi
	mov	eax, DWORD PTR 8[rax]
	add	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	sal	rax, 4
	mov	rsi, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rsi
	mov	eax, DWORD PTR 8[rax]
	add	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 1
	sal	rax, 4
	mov	rsi, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rsi
	mov	eax, DWORD PTR 8[rax]
	add	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	sal	rax, 4
	mov	rsi, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rsi
	mov	esi, DWORD PTR 4[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 1
	sal	rax, 4
	mov	rdi, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdi
	mov	eax, DWORD PTR 4[rax]
	add	esi, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	sal	rax, 4
	mov	rdi, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdi
	mov	eax, DWORD PTR 4[rax]
	add	esi, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 1
	sal	rax, 4
	mov	rdi, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdi
	mov	eax, DWORD PTR 4[rax]
	add	esi, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	sal	rax, 4
	mov	rdi, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdi
	mov	edi, DWORD PTR [rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 1
	sal	rax, 4
	mov	r8, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, r8
	mov	eax, DWORD PTR [rax]
	add	edi, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	sal	rax, 4
	mov	r8, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, r8
	mov	eax, DWORD PTR [rax]
	add	edi, eax
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 1
	sal	rax, 4
	mov	r8, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, r8
	mov	eax, DWORD PTR [rax]
	add	eax, edi
	mov	edi, eax
	call	ssim_end1
	movss	xmm1, DWORD PTR -8[rbp]
	addss	xmm0, xmm1
	movss	DWORD PTR -8[rbp], xmm0
	add	DWORD PTR -4[rbp], 1
.L11:
	mov	eax, DWORD PTR -4[rbp]
	cmp	eax, DWORD PTR -36[rbp]
	jl	.L12
	movss	xmm0, DWORD PTR -8[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	ssim_end4, .-ssim_end4
	.globl	ssim_plane
	.type	ssim_plane, @function
ssim_plane:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 88
	mov	QWORD PTR -56[rbp], rdi
	mov	QWORD PTR -64[rbp], rsi
	mov	QWORD PTR -72[rbp], rdx
	mov	QWORD PTR -80[rbp], rcx
	mov	DWORD PTR -84[rbp], r8d
	mov	DWORD PTR -88[rbp], r9d
	mov	DWORD PTR -40[rbp], 0
	pxor	xmm0, xmm0
	movss	DWORD PTR -28[rbp], xmm0
	mov	rax, QWORD PTR 16[rbp]
	mov	QWORD PTR -24[rbp], rax
	mov	eax, DWORD PTR -84[rbp]
	sar	eax, 2
	cdqe
	add	rax, 3
	sal	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	QWORD PTR -16[rbp], rax
	sar	DWORD PTR -84[rbp], 2
	sar	DWORD PTR -88[rbp], 2
	mov	DWORD PTR -32[rbp], 1
	jmp	.L15
.L19:
	mov	rax, QWORD PTR -16[rbp]
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -24[rbp]
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR -24[rbp], rax
	mov	DWORD PTR -36[rbp], 0
	jmp	.L17
.L18:
	mov	eax, DWORD PTR -36[rbp]
	cdqe
	sal	rax, 4
	mov	rdx, rax
	mov	rax, QWORD PTR -24[rbp]
	lea	rcx, [rdx+rax]
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	imul	rax, QWORD PTR -80[rbp]
	add	rax, rdx
	sal	rax, 2
	mov	rdx, rax
	mov	rax, QWORD PTR -72[rbp]
	lea	rsi, [rdx+rax]
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	imul	rax, QWORD PTR -64[rbp]
	add	rax, rdx
	sal	rax, 2
	mov	rdx, rax
	mov	rax, QWORD PTR -56[rbp]
	lea	rdi, [rdx+rax]
	mov	rdx, QWORD PTR -80[rbp]
	mov	rax, QWORD PTR -64[rbp]
	mov	r8, rcx
	mov	rcx, rdx
	mov	rdx, rsi
	mov	rsi, rax
	call	ssim_4x4x2_core
	add	DWORD PTR -36[rbp], 2
.L17:
	mov	eax, DWORD PTR -36[rbp]
	cmp	eax, DWORD PTR -84[rbp]
	jl	.L18
	add	DWORD PTR -40[rbp], 1
.L16:
	mov	eax, DWORD PTR -40[rbp]
	cmp	eax, DWORD PTR -32[rbp]
	jle	.L19
	mov	DWORD PTR -36[rbp], 0
	jmp	.L20
.L21:
	mov	eax, DWORD PTR -84[rbp]
	sub	eax, DWORD PTR -36[rbp]
	mov	edx, 5
	cmp	eax, 5
	cmovg	eax, edx
	lea	edx, -1[rax]
	mov	eax, DWORD PTR -36[rbp]
	cdqe
	sal	rax, 4
	mov	rcx, rax
	mov	rax, QWORD PTR -16[rbp]
	add	rcx, rax
	mov	eax, DWORD PTR -36[rbp]
	cdqe
	sal	rax, 4
	mov	rsi, rax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rsi
	mov	rsi, rcx
	mov	rdi, rax
	call	ssim_end4
	movss	xmm1, DWORD PTR -28[rbp]
	addss	xmm0, xmm1
	movss	DWORD PTR -28[rbp], xmm0
	add	DWORD PTR -36[rbp], 4
.L20:
	mov	eax, DWORD PTR -84[rbp]
	sub	eax, 1
	cmp	DWORD PTR -36[rbp], eax
	jl	.L21
	add	DWORD PTR -32[rbp], 1
.L15:
	mov	eax, DWORD PTR -32[rbp]
	cmp	eax, DWORD PTR -88[rbp]
	jl	.L16
	mov	eax, DWORD PTR -88[rbp]
	lea	edx, -1[rax]
	mov	eax, DWORD PTR -84[rbp]
	sub	eax, 1
	imul	eax, edx
	pxor	xmm1, xmm1
	cvtsi2ss	xmm1, eax
	movss	xmm0, DWORD PTR -28[rbp]
	divss	xmm0, xmm1
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	ssim_plane, .-ssim_plane
	.globl	ssd_plane
	.type	ssd_plane, @function
ssd_plane:
.LFB10:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -36[rbp], edx
	mov	QWORD PTR -8[rbp], 0
	mov	DWORD PTR -16[rbp], 0
	jmp	.L25
.L26:
	mov	eax, DWORD PTR -16[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	edx, DWORD PTR -16[rbp]
	movsx	rcx, edx
	mov	rdx, QWORD PTR -32[rbp]
	add	rdx, rcx
	movzx	edx, BYTE PTR [rdx]
	movzx	edx, dl
	sub	eax, edx
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	imul	eax, eax
	cdqe
	add	QWORD PTR -8[rbp], rax
	add	DWORD PTR -16[rbp], 1
.L25:
	mov	eax, DWORD PTR -16[rbp]
	cmp	eax, DWORD PTR -36[rbp]
	jl	.L26
	mov	rax, QWORD PTR -8[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE10:
	.size	ssd_plane, .-ssd_plane
	.globl	ssd_to_psnr
	.type	ssd_to_psnr, @function
ssd_to_psnr:
.LFB11:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -8[rbp]
	test	rax, rax
	js	.L29
	pxor	xmm0, xmm0
	cvtsi2sd	xmm0, rax
	jmp	.L30
.L29:
	mov	rdx, rax
	shr	rdx
	and	eax, 1
	or	rdx, rax
	pxor	xmm0, xmm0
	cvtsi2sd	xmm0, rdx
	addsd	xmm0, xmm0
.L30:
	mov	rax, QWORD PTR -16[rbp]
	imul	rax, rax, 65025
	test	rax, rax
	js	.L31
	pxor	xmm1, xmm1
	cvtsi2sd	xmm1, rax
	jmp	.L32
.L31:
	mov	rdx, rax
	shr	rdx
	and	eax, 1
	or	rdx, rax
	pxor	xmm1, xmm1
	cvtsi2sd	xmm1, rdx
	addsd	xmm1, xmm1
.L32:
	divsd	xmm0, xmm1
	movq	rax, xmm0
	movq	xmm0, rax
	call	log@PLT
	movsd	xmm1, QWORD PTR .LC1[rip]
	mulsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC2[rip]
	divsd	xmm0, xmm1
	movq	rax, xmm0
	movq	xmm0, rax
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE11:
	.size	ssd_to_psnr, .-ssd_to_psnr
	.section	.rodata
.LC4:
	.string	"%dx%d"
	.align 8
.LC5:
	.string	"tiny_ssim <file1.yuv> <file2.yuv> <width>x<height> [<seek>]"
.LC6:
	.string	"rb"
	.align 8
.LC7:
	.string	"PSNR Y:%.3f  U:%.3f  V:%.3f  All:%.3f\n"
	.align 8
.LC9:
	.string	"SSIM Y:%.5f U:%.5f V:%.5f All:%.5f\n"
	.text
	.globl	main
	.type	main, @function
main:
.LFB12:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	push	r13
	push	r12
	push	rbx
	sub	rsp, 216
	.cfi_offset 13, -24
	.cfi_offset 12, -32
	.cfi_offset 3, -40
	mov	DWORD PTR -228[rbp], edi
	mov	QWORD PTR -240[rbp], rsi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -40[rbp], rax
	xor	eax, eax
	mov	QWORD PTR -160[rbp], 0
	mov	QWORD PTR -152[rbp], 0
	mov	QWORD PTR -144[rbp], 0
	pxor	xmm0, xmm0
	movsd	QWORD PTR -128[rbp], xmm0
	pxor	xmm0, xmm0
	movsd	QWORD PTR -120[rbp], xmm0
	pxor	xmm0, xmm0
	movsd	QWORD PTR -112[rbp], xmm0
	cmp	DWORD PTR -228[rbp], 3
	jle	.L35
	mov	rax, QWORD PTR -240[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	lea	rcx, -220[rbp]
	lea	rdx, -224[rbp]
	lea	rsi, .LC4[rip]
	mov	rdi, rax
	mov	eax, 0
	call	__isoc99_sscanf@PLT
	cmp	eax, 2
	je	.L36
.L35:
	lea	rdi, .LC5[rip]
	call	puts@PLT
	mov	eax, -1
	jmp	.L51
.L36:
	mov	rax, QWORD PTR -240[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	lea	rsi, .LC6[rip]
	mov	rdi, rax
	call	fopen@PLT
	mov	QWORD PTR -192[rbp], rax
	mov	rax, QWORD PTR -240[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	lea	rsi, .LC6[rip]
	mov	rdi, rax
	call	fopen@PLT
	mov	QWORD PTR -184[rbp], rax
	mov	rax, QWORD PTR -240[rbp]
	add	rax, 24
	mov	rax, QWORD PTR [rax]
	lea	rcx, -220[rbp]
	lea	rdx, -224[rbp]
	lea	rsi, .LC4[rip]
	mov	rdi, rax
	mov	eax, 0
	call	__isoc99_sscanf@PLT
	mov	edx, DWORD PTR -224[rbp]
	mov	eax, DWORD PTR -220[rbp]
	imul	edx, eax
	mov	eax, edx
	add	eax, eax
	add	eax, edx
	mov	edx, eax
	shr	edx, 31
	add	eax, edx
	sar	eax
	mov	DWORD PTR -208[rbp], eax
	mov	DWORD PTR -212[rbp], 0
	jmp	.L38
.L39:
	mov	eax, DWORD PTR -208[rbp]
	cdqe
	mov	rdi, rax
	call	malloc@PLT
	mov	rdx, rax
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	mov	QWORD PTR -176[rbp+rax*8], rdx
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	mov	rdx, QWORD PTR -176[rbp+rax*8]
	mov	eax, DWORD PTR -212[rbp]
	movsx	rcx, eax
	mov	rax, rcx
	add	rax, rax
	add	rax, rcx
	sal	rax, 3
	lea	rax, -32[rax]
	add	rax, rbp
	sub	rax, 64
	mov	QWORD PTR [rax], rdx
	mov	eax, DWORD PTR -212[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	sal	rax, 3
	lea	rax, -32[rax]
	add	rax, rbp
	sub	rax, 64
	mov	rcx, QWORD PTR [rax]
	mov	edx, DWORD PTR -224[rbp]
	mov	eax, DWORD PTR -220[rbp]
	imul	eax, edx
	cdqe
	add	rcx, rax
	mov	eax, DWORD PTR -212[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	sal	rax, 3
	lea	rax, -32[rax]
	add	rax, rbp
	sub	rax, 56
	mov	QWORD PTR [rax], rcx
	mov	eax, DWORD PTR -212[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	sal	rax, 3
	lea	rax, -32[rax]
	add	rax, rbp
	sub	rax, 56
	mov	rcx, QWORD PTR [rax]
	mov	edx, DWORD PTR -224[rbp]
	mov	eax, DWORD PTR -220[rbp]
	imul	eax, edx
	lea	edx, 3[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 2
	cdqe
	add	rcx, rax
	mov	eax, DWORD PTR -212[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	sal	rax, 3
	lea	rax, -32[rax]
	add	rax, rbp
	sub	rax, 48
	mov	QWORD PTR [rax], rcx
	add	DWORD PTR -212[rbp], 1
.L38:
	cmp	DWORD PTR -212[rbp], 1
	jle	.L39
	mov	eax, DWORD PTR -224[rbp]
	add	eax, 6
	add	eax, eax
	cdqe
	sal	rax, 2
	mov	rdi, rax
	call	malloc@PLT
	mov	QWORD PTR -200[rbp], rax
	cmp	DWORD PTR -228[rbp], 4
	jle	.L40
	mov	rax, QWORD PTR -240[rbp]
	add	rax, 32
	mov	rax, QWORD PTR [rax]
	mov	rdi, rax
	call	atoi@PLT
	jmp	.L41
.L40:
	mov	eax, 0
.L41:
	mov	DWORD PTR -204[rbp], eax
	mov	eax, DWORD PTR -204[rbp]
	cdq
	mov	eax, edx
	xor	eax, DWORD PTR -204[rbp]
	sub	eax, edx
	movsx	rcx, eax
	mov	eax, DWORD PTR -204[rbp]
	shr	eax, 31
	movzx	eax, al
	cdqe
	mov	rax, QWORD PTR -192[rbp+rax*8]
	mov	edx, 0
	mov	rsi, rcx
	mov	rdi, rax
	call	fseek@PLT
	mov	DWORD PTR -216[rbp], 0
.L49:
	mov	rdx, QWORD PTR -192[rbp]
	mov	eax, DWORD PTR -208[rbp]
	movsx	rsi, eax
	mov	rax, QWORD PTR -176[rbp]
	mov	rcx, rdx
	mov	edx, 1
	mov	rdi, rax
	call	fread@PLT
	cmp	rax, 1
	jne	.L53
	mov	rdx, QWORD PTR -184[rbp]
	mov	eax, DWORD PTR -208[rbp]
	movsx	rsi, eax
	mov	rax, QWORD PTR -168[rbp]
	mov	rcx, rdx
	mov	edx, 1
	mov	rdi, rax
	call	fread@PLT
	cmp	rax, 1
	jne	.L54
	mov	DWORD PTR -212[rbp], 0
	jmp	.L45
.L48:
	mov	edx, DWORD PTR -224[rbp]
	mov	eax, DWORD PTR -220[rbp]
	imul	eax, edx
	cmp	DWORD PTR -212[rbp], 0
	je	.L46
	mov	edx, 2
	jmp	.L47
.L46:
	mov	edx, 0
.L47:
	mov	ecx, edx
	sar	eax, cl
	mov	edx, eax
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	add	rax, 3
	mov	rcx, QWORD PTR -96[rbp+rax*8]
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	mov	rax, QWORD PTR -96[rbp+rax*8]
	mov	rsi, rcx
	mov	rdi, rax
	call	ssd_plane
	mov	rdx, rax
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	mov	rax, QWORD PTR -160[rbp+rax*8]
	add	rdx, rax
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	mov	QWORD PTR -160[rbp+rax*8], rdx
	mov	edx, DWORD PTR -220[rbp]
	cmp	DWORD PTR -212[rbp], 0
	setne	al
	movzx	eax, al
	mov	ecx, eax
	sar	edx, cl
	mov	r9d, edx
	mov	edx, DWORD PTR -224[rbp]
	cmp	DWORD PTR -212[rbp], 0
	setne	al
	movzx	eax, al
	mov	ecx, eax
	sar	edx, cl
	mov	r8d, edx
	mov	edx, DWORD PTR -224[rbp]
	cmp	DWORD PTR -212[rbp], 0
	setne	al
	movzx	eax, al
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	movsx	rdi, eax
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	add	rax, 3
	mov	rdx, QWORD PTR -96[rbp+rax*8]
	mov	esi, DWORD PTR -224[rbp]
	cmp	DWORD PTR -212[rbp], 0
	setne	al
	movzx	eax, al
	mov	ecx, eax
	sar	esi, cl
	mov	eax, esi
	movsx	rsi, eax
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	mov	rax, QWORD PTR -96[rbp+rax*8]
	push	0
	push	QWORD PTR -200[rbp]
	mov	rcx, rdi
	mov	rdi, rax
	call	ssim_plane
	add	rsp, 16
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	movsd	xmm1, QWORD PTR -128[rbp+rax*8]
	cvtss2sd	xmm0, xmm0
	addsd	xmm0, xmm1
	mov	eax, DWORD PTR -212[rbp]
	cdqe
	movsd	QWORD PTR -128[rbp+rax*8], xmm0
	add	DWORD PTR -212[rbp], 1
.L45:
	cmp	DWORD PTR -212[rbp], 2
	jle	.L48
	add	DWORD PTR -216[rbp], 1
	jmp	.L49
.L53:
	nop
	jmp	.L43
.L54:
	nop
.L43:
	cmp	DWORD PTR -216[rbp], 0
	jne	.L50
	mov	eax, 0
	jmp	.L51
.L50:
	mov	eax, DWORD PTR -216[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -224[rbp]
	cdqe
	imul	rdx, rax
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	imul	rdx, rax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	shr	rax
	mov	rdx, rax
	mov	rcx, QWORD PTR -160[rbp]
	mov	rax, QWORD PTR -152[rbp]
	add	rcx, rax
	mov	rax, QWORD PTR -144[rbp]
	add	rax, rcx
	mov	rsi, rdx
	mov	rdi, rax
	call	ssd_to_psnr
	movq	r13, xmm0
	mov	eax, DWORD PTR -216[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -224[rbp]
	cdqe
	imul	rdx, rax
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	imul	rax, rdx
	shr	rax, 2
	mov	rdx, rax
	mov	rax, QWORD PTR -144[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	ssd_to_psnr
	movq	r12, xmm0
	mov	eax, DWORD PTR -216[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -224[rbp]
	cdqe
	imul	rdx, rax
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	imul	rax, rdx
	shr	rax, 2
	mov	rdx, rax
	mov	rax, QWORD PTR -152[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	ssd_to_psnr
	movq	rbx, xmm0
	mov	eax, DWORD PTR -216[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -224[rbp]
	cdqe
	imul	rdx, rax
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	imul	rdx, rax
	mov	rax, QWORD PTR -160[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	ssd_to_psnr
	movq	rax, xmm0
	movq	xmm3, r13
	movq	xmm2, r12
	movq	xmm1, rbx
	movq	xmm0, rax
	lea	rdi, .LC7[rip]
	mov	eax, 4
	call	printf@PLT
	movsd	xmm1, QWORD PTR -128[rbp]
	movsd	xmm0, QWORD PTR .LC8[rip]
	mulsd	xmm1, xmm0
	movsd	xmm0, QWORD PTR -120[rbp]
	addsd	xmm1, xmm0
	movsd	xmm0, QWORD PTR -112[rbp]
	addsd	xmm0, xmm1
	mov	edx, DWORD PTR -216[rbp]
	mov	eax, edx
	add	eax, eax
	add	eax, edx
	add	eax, eax
	pxor	xmm1, xmm1
	cvtsi2sd	xmm1, eax
	movapd	xmm3, xmm0
	divsd	xmm3, xmm1
	movsd	xmm0, QWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtsi2sd	xmm1, DWORD PTR -216[rbp]
	movapd	xmm2, xmm0
	divsd	xmm2, xmm1
	movsd	xmm0, QWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtsi2sd	xmm1, DWORD PTR -216[rbp]
	movapd	xmm4, xmm0
	divsd	xmm4, xmm1
	movsd	xmm0, QWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtsi2sd	xmm1, DWORD PTR -216[rbp]
	divsd	xmm0, xmm1
	movq	rax, xmm0
	movapd	xmm1, xmm4
	movq	xmm0, rax
	lea	rdi, .LC9[rip]
	mov	eax, 4
	call	printf@PLT
	mov	eax, 0
.L51:
	mov	rbx, QWORD PTR -40[rbp]
	sub	rbx, QWORD PTR fs:40
	je	.L52
	call	__stack_chk_fail@PLT
.L52:
	lea	rsp, -24[rbp]
	pop	rbx
	pop	r12
	pop	r13
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE12:
	.size	main, .-main
	.section	.rodata
	.align 4
	.type	ssim_c1.1, @object
	.size	ssim_c1.1, 4
ssim_c1.1:
	.long	416
	.align 4
	.type	ssim_c2.0, @object
	.size	ssim_c2.0, 4
ssim_c2.0:
	.long	235963
	.align 8
.LC1:
	.long	0
	.long	-1071382528
	.align 8
.LC2:
	.long	-1145744106
	.long	1073900465
	.align 8
.LC8:
	.long	0
	.long	1074790400
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"895907.c"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ssim_4x4x2_core, %function
ssim_4x4x2_core:
	@ args = 4, pretend = 0, frame = 56
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #60
	str	r0, [fp, #-48]
	str	r1, [fp, #-52]
	str	r2, [fp, #-56]
	str	r3, [fp, #-60]
	mov	r3, #0
	str	r3, [fp, #-32]
	b	.L2
.L7:
	mov	r3, #0
	str	r3, [fp, #-28]
	mov	r3, #0
	str	r3, [fp, #-24]
	mov	r3, #0
	str	r3, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-36]
	b	.L3
.L6:
	mov	r3, #0
	str	r3, [fp, #-40]
	b	.L4
.L5:
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-52]
	mul	r2, r3, r2
	ldr	r3, [fp, #-40]
	add	r3, r2, r3
	mov	r2, r3
	ldr	r3, [fp, #-48]
	add	r3, r3, r2
	ldrb	r3, [r3]	@ zero_extendqisi2
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-60]
	mul	r2, r3, r2
	ldr	r3, [fp, #-40]
	add	r3, r2, r3
	mov	r2, r3
	ldr	r3, [fp, #-56]
	add	r3, r3, r2
	ldrb	r3, [r3]	@ zero_extendqisi2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-12]
	ldr	r2, [fp, #-28]
	add	r3, r2, r3
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-8]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-12]
	mov	r2, r3
	mul	r2, r3, r2
	mov	r3, r2
	mov	r2, r3
	ldr	r3, [fp, #-20]
	add	r3, r3, r2
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-8]
	mov	r2, r3
	mul	r2, r3, r2
	mov	r3, r2
	mov	r2, r3
	ldr	r3, [fp, #-20]
	add	r3, r3, r2
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-12]
	ldr	r2, [fp, #-8]
	mul	r3, r2, r3
	mov	r2, r3
	ldr	r3, [fp, #-16]
	add	r3, r3, r2
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-40]
	add	r3, r3, #1
	str	r3, [fp, #-40]
.L4:
	ldr	r3, [fp, #-40]
	cmp	r3, #3
	ble	.L5
	ldr	r3, [fp, #-36]
	add	r3, r3, #1
	str	r3, [fp, #-36]
.L3:
	ldr	r3, [fp, #-36]
	cmp	r3, #3
	ble	.L6
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #4
	ldr	r2, [fp, #4]
	add	r3, r2, r3
	ldr	r2, [fp, #-28]
	str	r2, [r3]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #4
	ldr	r2, [fp, #4]
	add	r3, r2, r3
	ldr	r2, [fp, #-24]
	str	r2, [r3, #4]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #4
	ldr	r2, [fp, #4]
	add	r3, r2, r3
	ldr	r2, [fp, #-20]
	str	r2, [r3, #8]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #4
	ldr	r2, [fp, #4]
	add	r3, r2, r3
	ldr	r2, [fp, #-16]
	str	r2, [r3, #12]
	ldr	r3, [fp, #-48]
	add	r3, r3, #4
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-56]
	add	r3, r3, #4
	str	r3, [fp, #-56]
	ldr	r3, [fp, #-32]
	add	r3, r3, #1
	str	r3, [fp, #-32]
.L2:
	ldr	r3, [fp, #-32]
	cmp	r3, #1
	ble	.L7
	nop
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	ssim_4x4x2_core, .-ssim_4x4x2_core
	.global	__aeabi_i2f
	.global	__aeabi_fmul
	.global	__aeabi_fdiv
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ssim_end1, %function
ssim_end1:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, fp, lr}
	add	fp, sp, #12
	sub	sp, sp, #40
	str	r0, [fp, #-40]
	str	r1, [fp, #-44]
	str	r2, [fp, #-48]
	str	r3, [fp, #-52]
	ldr	r3, [fp, #-40]
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-44]
	str	r3, [fp, #-32]
	ldr	r3, [fp, #-48]
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-52]
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-28]
	lsl	r2, r3, #6
	ldr	r3, [fp, #-36]
	mov	r1, r3
	mul	r1, r3, r1
	mov	r3, r1
	sub	r2, r2, r3
	ldr	r3, [fp, #-32]
	mov	r1, r3
	mul	r1, r3, r1
	mov	r3, r1
	sub	r3, r2, r3
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-24]
	lsl	r2, r3, #6
	ldr	r3, [fp, #-36]
	ldr	r1, [fp, #-32]
	mul	r3, r1, r3
	sub	r3, r2, r3
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-32]
	mul	r3, r2, r3
	lsl	r2, r3, #1
	ldr	r3, .L10
	ldr	r3, [r3]
	add	r3, r2, r3
	mov	r0, r3
	bl	__aeabi_i2f
	mov	r4, r0
	ldr	r3, [fp, #-16]
	lsl	r2, r3, #1
	ldr	r3, .L10+4
	ldr	r3, [r3]
	add	r3, r2, r3
	mov	r0, r3
	bl	__aeabi_i2f
	mov	r3, r0
	mov	r1, r3
	mov	r0, r4
	bl	__aeabi_fmul
	mov	r3, r0
	mov	r5, r3
	ldr	r3, [fp, #-36]
	mul	r2, r3, r3
	ldr	r3, [fp, #-32]
	mov	r1, r3
	mul	r1, r3, r1
	mov	r3, r1
	add	r2, r2, r3
	ldr	r3, .L10
	ldr	r3, [r3]
	add	r3, r2, r3
	mov	r0, r3
	bl	__aeabi_i2f
	mov	r4, r0
	ldr	r3, .L10+4
	ldr	r2, [r3]
	ldr	r3, [fp, #-20]
	add	r3, r2, r3
	mov	r0, r3
	bl	__aeabi_i2f
	mov	r3, r0
	mov	r1, r3
	mov	r0, r4
	bl	__aeabi_fmul
	mov	r3, r0
	mov	r1, r3
	mov	r0, r5
	bl	__aeabi_fdiv
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #12
	@ sp needed
	pop	{r4, r5, fp, pc}
.L11:
	.align	2
.L10:
	.word	ssim_c1.6235
	.word	ssim_c2.6236
	.size	ssim_end1, .-ssim_end1
	.global	__aeabi_fadd
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	ssim_end4, %function
ssim_end4:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	mov	r3, #0
	str	r3, [fp, #-12]	@ float
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L13
.L14:
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #4
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	lsl	r3, r3, #4
	ldr	r1, [fp, #-16]
	add	r3, r1, r3
	ldr	r3, [r3]
	add	r2, r2, r3
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #4
	ldr	r1, [fp, #-20]
	add	r3, r1, r3
	ldr	r3, [r3]
	add	r2, r2, r3
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	lsl	r3, r3, #4
	ldr	r1, [fp, #-20]
	add	r3, r1, r3
	ldr	r3, [r3]
	add	r0, r2, r3
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #4
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	lsl	r3, r3, #4
	ldr	r1, [fp, #-16]
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	add	r2, r2, r3
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #4
	ldr	r1, [fp, #-20]
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	add	r2, r2, r3
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	lsl	r3, r3, #4
	ldr	r1, [fp, #-20]
	add	r3, r1, r3
	ldr	r3, [r3, #4]
	add	ip, r2, r3
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #4
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	lsl	r3, r3, #4
	ldr	r1, [fp, #-16]
	add	r3, r1, r3
	ldr	r3, [r3, #8]
	add	r2, r2, r3
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #4
	ldr	r1, [fp, #-20]
	add	r3, r1, r3
	ldr	r3, [r3, #8]
	add	r2, r2, r3
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	lsl	r3, r3, #4
	ldr	r1, [fp, #-20]
	add	r3, r1, r3
	ldr	r3, [r3, #8]
	add	lr, r2, r3
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #4
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	lsl	r3, r3, #4
	ldr	r1, [fp, #-16]
	add	r3, r1, r3
	ldr	r3, [r3, #12]
	add	r2, r2, r3
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #4
	ldr	r1, [fp, #-20]
	add	r3, r1, r3
	ldr	r3, [r3, #12]
	add	r2, r2, r3
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	lsl	r3, r3, #4
	ldr	r1, [fp, #-20]
	add	r3, r1, r3
	ldr	r3, [r3, #12]
	add	r3, r2, r3
	mov	r2, lr
	mov	r1, ip
	bl	ssim_end1
	mov	r3, r0
	mov	r1, r3
	ldr	r0, [fp, #-12]	@ float
	bl	__aeabi_fadd
	mov	r3, r0
	str	r3, [fp, #-12]	@ float
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L13:
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-24]
	cmp	r2, r3
	blt	.L14
	ldr	r3, [fp, #-12]	@ float
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	ssim_end4, .-ssim_end4
	.align	2
	.global	ssim_plane
	.syntax unified
	.arm
	.fpu softvfp
	.type	ssim_plane, %function
ssim_plane:
	@ args = 16, pretend = 0, frame = 48
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #56
	str	r0, [fp, #-40]
	str	r1, [fp, #-44]
	str	r2, [fp, #-48]
	str	r3, [fp, #-52]
	mov	r3, #0
	str	r3, [fp, #-32]
	mov	r3, #0
	str	r3, [fp, #-20]	@ float
	ldr	r3, [fp, #12]
	str	r3, [fp, #-16]
	ldr	r3, [fp, #4]
	asr	r3, r3, #2
	add	r3, r3, #3
	lsl	r3, r3, #4
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	str	r3, [fp, #-12]
	ldr	r3, [fp, #4]
	asr	r3, r3, #2
	str	r3, [fp, #4]
	ldr	r3, [fp, #8]
	asr	r3, r3, #2
	str	r3, [fp, #8]
	mov	r3, #1
	str	r3, [fp, #-24]
	b	.L17
.L21:
	ldr	r3, [fp, #-12]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-16]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-8]
	str	r3, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-28]
	b	.L19
.L20:
	ldr	r3, [fp, #-32]
	ldr	r2, [fp, #-44]
	mul	r2, r3, r2
	ldr	r3, [fp, #-28]
	add	r3, r2, r3
	lsl	r3, r3, #2
	mov	r2, r3
	ldr	r3, [fp, #-40]
	add	r0, r3, r2
	ldr	r3, [fp, #-32]
	ldr	r2, [fp, #-52]
	mul	r2, r3, r2
	ldr	r3, [fp, #-28]
	add	r3, r2, r3
	lsl	r3, r3, #2
	mov	r2, r3
	ldr	r3, [fp, #-48]
	add	r1, r3, r2
	ldr	r3, [fp, #-28]
	lsl	r3, r3, #4
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	str	r3, [sp]
	ldr	r3, [fp, #-52]
	mov	r2, r1
	ldr	r1, [fp, #-44]
	bl	ssim_4x4x2_core
	ldr	r3, [fp, #-28]
	add	r3, r3, #2
	str	r3, [fp, #-28]
.L19:
	ldr	r2, [fp, #-28]
	ldr	r3, [fp, #4]
	cmp	r2, r3
	blt	.L20
	ldr	r3, [fp, #-32]
	add	r3, r3, #1
	str	r3, [fp, #-32]
.L18:
	ldr	r2, [fp, #-32]
	ldr	r3, [fp, #-24]
	cmp	r2, r3
	ble	.L21
	mov	r3, #0
	str	r3, [fp, #-28]
	b	.L22
.L23:
	ldr	r3, [fp, #-28]
	lsl	r3, r3, #4
	ldr	r2, [fp, #-16]
	add	r0, r2, r3
	ldr	r3, [fp, #-28]
	lsl	r3, r3, #4
	ldr	r2, [fp, #-12]
	add	r1, r2, r3
	ldr	r2, [fp, #4]
	ldr	r3, [fp, #-28]
	sub	r3, r2, r3
	cmp	r3, #5
	movlt	r3, r3
	movge	r3, #5
	sub	r3, r3, #1
	mov	r2, r3
	bl	ssim_end4
	mov	r3, r0
	mov	r1, r3
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_fadd
	mov	r3, r0
	str	r3, [fp, #-20]	@ float
	ldr	r3, [fp, #-28]
	add	r3, r3, #4
	str	r3, [fp, #-28]
.L22:
	ldr	r3, [fp, #4]
	sub	r3, r3, #1
	ldr	r2, [fp, #-28]
	cmp	r2, r3
	blt	.L23
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	str	r3, [fp, #-24]
.L17:
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #8]
	cmp	r2, r3
	blt	.L18
	ldr	r3, [fp, #8]
	sub	r3, r3, #1
	ldr	r2, [fp, #4]
	sub	r2, r2, #1
	mul	r3, r2, r3
	mov	r0, r3
	bl	__aeabi_i2f
	mov	r3, r0
	mov	r1, r3
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_fdiv
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	ssim_plane, .-ssim_plane
	.align	2
	.global	ssd_plane
	.syntax unified
	.arm
	.fpu softvfp
	.type	ssd_plane, %function
ssd_plane:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	push	{r4, r5, fp}
	add	fp, sp, #8
	sub	sp, sp, #36
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	str	r2, [fp, #-40]
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-20]
	str	r3, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-28]
	b	.L27
.L28:
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-32]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r1, r3
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-36]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r3, r1, r3
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-24]
	mov	r2, r3
	mul	r2, r3, r2
	mov	r3, r2
	mov	r2, r3
	asr	r3, r2, #31
	sub	r1, fp, #20
	ldmia	r1, {r0-r1}
	adds	r4, r0, r2
	adc	r5, r1, r3
	str	r4, [fp, #-20]
	str	r5, [fp, #-16]
	ldr	r3, [fp, #-28]
	add	r3, r3, #1
	str	r3, [fp, #-28]
.L27:
	ldr	r2, [fp, #-28]
	ldr	r3, [fp, #-40]
	cmp	r2, r3
	blt	.L28
	sub	r3, fp, #20
	ldmia	r3, {r2-r3}
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, r5, fp}
	bx	lr
	.size	ssd_plane, .-ssd_plane
	.global	__aeabi_ul2d
	.global	__aeabi_ddiv
	.global	__aeabi_dmul
	.align	2
	.global	ssd_to_psnr
	.syntax unified
	.arm
	.fpu softvfp
	.type	ssd_to_psnr, %function
ssd_to_psnr:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #16
	str	r0, [fp, #-36]
	str	r1, [fp, #-32]
	str	r2, [fp, #-44]
	str	r3, [fp, #-40]
	sub	r1, fp, #36
	ldmia	r1, {r0-r1}
	bl	__aeabi_ul2d
	mov	r8, r0
	mov	r9, r1
	sub	r1, fp, #44
	ldmia	r1, {r0-r1}
	mov	r2, r0
	mov	r3, r1
	mov	r4, #0
	mov	r5, #0
	lsl	r5, r3, #7
	orr	r5, r5, r2, lsr #25
	lsl	r4, r2, #7
	mov	r2, r4
	mov	r3, r5
	subs	r2, r2, r0
	sbc	r3, r3, r1
	mov	r4, #0
	mov	r5, #0
	lsl	r5, r3, #9
	orr	r5, r5, r2, lsr #23
	lsl	r4, r2, #9
	mov	r2, r4
	mov	r3, r5
	adds	r6, r2, r0
	adc	r7, r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_ul2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r8
	mov	r1, r9
	bl	__aeabi_ddiv
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	bl	log
	mov	r2, #0
	ldr	r3, .L32
	bl	__aeabi_dmul
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	ldr	r2, .L32+4
	ldr	r3, .L32+8
	bl	__aeabi_ddiv
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
.L33:
	.align	2
.L32:
	.word	-1071382528
	.word	-1145744106
	.word	1073900465
	.size	ssd_to_psnr, .-ssd_to_psnr
	.section	.rodata
	.align	2
.LC0:
	.ascii	"%dx%d\000"
	.align	2
.LC1:
	.ascii	"tiny_ssim <file1.yuv> <file2.yuv> <width>x<height> "
	.ascii	"[<seek>]\000"
	.align	2
.LC2:
	.ascii	"rb\000"
	.global	__aeabi_f2d
	.global	__aeabi_dadd
	.align	2
.LC3:
	.ascii	"PSNR Y:%.3f  U:%.3f  V:%.3f  All:%.3f\012\000"
	.global	__aeabi_i2d
	.align	2
.LC4:
	.ascii	"SSIM Y:%.5f U:%.5f V:%.5f All:%.5f\012\000"
	.align	2
.LC5:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 184
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #208
	str	r0, [fp, #-160]
	str	r1, [fp, #-164]
	ldr	r3, .L55
	ldr	r3, [r3]
	str	r3, [fp, #-32]
	mov	r3,#0
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-108]
	str	r3, [fp, #-104]
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-100]
	str	r3, [fp, #-96]
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-92]
	str	r3, [fp, #-88]
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-84]
	str	r3, [fp, #-80]
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-76]
	str	r3, [fp, #-72]
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-68]
	str	r3, [fp, #-64]
	ldr	r3, [fp, #-160]
	cmp	r3, #3
	ble	.L35
	ldr	r3, [fp, #-164]
	add	r3, r3, #12
	ldr	r0, [r3]
	sub	r3, fp, #148
	sub	r2, fp, #152
	ldr	r1, .L55+4
	bl	__isoc99_sscanf
	mov	r3, r0
	cmp	r3, #2
	beq	.L36
.L35:
	ldr	r0, .L55+8
	bl	puts
	mvn	r3, #0
	b	.L51
.L36:
	ldr	r3, [fp, #-164]
	add	r3, r3, #4
	ldr	r3, [r3]
	ldr	r1, .L55+12
	mov	r0, r3
	bl	fopen
	mov	r3, r0
	str	r3, [fp, #-124]
	ldr	r3, [fp, #-164]
	add	r3, r3, #8
	ldr	r3, [r3]
	ldr	r1, .L55+12
	mov	r0, r3
	bl	fopen
	mov	r3, r0
	str	r3, [fp, #-120]
	ldr	r3, [fp, #-164]
	add	r3, r3, #12
	ldr	r0, [r3]
	sub	r3, fp, #148
	sub	r2, fp, #152
	ldr	r1, .L55+4
	bl	__isoc99_sscanf
	ldr	r3, [fp, #-152]
	ldr	r2, [fp, #-148]
	mul	r2, r3, r2
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsr	r2, r3, #31
	add	r3, r2, r3
	asr	r3, r3, #1
	str	r3, [fp, #-136]
	mov	r3, #0
	str	r3, [fp, #-140]
	b	.L38
.L39:
	ldr	r3, [fp, #-136]
	mov	r0, r3
	bl	malloc
	mov	r3, r0
	mov	r2, r3
	ldr	r3, [fp, #-140]
	lsl	r3, r3, #2
	sub	r1, fp, #28
	add	r3, r1, r3
	str	r2, [r3, #-88]
	ldr	r3, [fp, #-140]
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	ldr	r1, [r3, #-88]
	ldr	r2, [fp, #-140]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	sub	r3, r3, #28
	str	r1, [r3]
	ldr	r2, [fp, #-140]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	sub	r3, r3, #28
	ldr	r3, [r3]
	ldr	r2, [fp, #-152]
	ldr	r1, [fp, #-148]
	mul	r2, r1, r2
	add	r1, r3, r2
	ldr	r2, [fp, #-140]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	sub	r3, r3, #24
	str	r1, [r3]
	ldr	r2, [fp, #-140]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	sub	r3, r3, #24
	ldr	r2, [r3]
	ldr	r3, [fp, #-152]
	ldr	r1, [fp, #-148]
	mul	r3, r1, r3
	add	r1, r3, #3
	cmp	r3, #0
	movlt	r3, r1
	movge	r3, r3
	asr	r3, r3, #2
	add	r1, r2, r3
	ldr	r2, [fp, #-140]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	sub	r3, r3, #20
	str	r1, [r3]
	ldr	r3, [fp, #-140]
	add	r3, r3, #1
	str	r3, [fp, #-140]
.L38:
	ldr	r3, [fp, #-140]
	cmp	r3, #1
	ble	.L39
	ldr	r3, [fp, #-152]
	add	r3, r3, #6
	lsl	r3, r3, #3
	mov	r0, r3
	bl	malloc
	mov	r3, r0
	str	r3, [fp, #-132]
	ldr	r3, [fp, #-160]
	cmp	r3, #4
	ble	.L40
	ldr	r3, [fp, #-164]
	add	r3, r3, #16
	ldr	r3, [r3]
	mov	r0, r3
	bl	atoi
	mov	r3, r0
	b	.L41
.L40:
	mov	r3, #0
.L41:
	str	r3, [fp, #-128]
	ldr	r3, [fp, #-128]
	lsr	r3, r3, #31
	and	r3, r3, #255
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	ldr	r0, [r3, #-96]
	ldr	r3, [fp, #-128]
	cmp	r3, #0
	rsblt	r3, r3, #0
	mov	r2, #0
	mov	r1, r3
	bl	fseek
	mov	r3, #0
	str	r3, [fp, #-144]
.L49:
	ldr	r0, [fp, #-116]
	ldr	r1, [fp, #-136]
	ldr	r3, [fp, #-124]
	mov	r2, #1
	bl	fread
	mov	r3, r0
	cmp	r3, #1
	bne	.L53
	ldr	r0, [fp, #-112]
	ldr	r1, [fp, #-136]
	ldr	r3, [fp, #-120]
	mov	r2, #1
	bl	fread
	mov	r3, r0
	cmp	r3, #1
	bne	.L54
	mov	r3, #0
	str	r3, [fp, #-140]
	b	.L45
.L48:
	ldr	r3, [fp, #-140]
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	ldr	r0, [r3, #-28]
	ldr	r3, [fp, #-140]
	add	r3, r3, #3
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	ldr	r1, [r3, #-28]
	ldr	r3, [fp, #-152]
	ldr	r2, [fp, #-148]
	mul	r2, r3, r2
	ldr	r3, [fp, #-140]
	cmp	r3, #0
	beq	.L46
	mov	r3, #2
	b	.L47
.L46:
	mov	r3, #0
.L47:
	asr	r3, r2, r3
	mov	r2, r3
	bl	ssd_plane
	ldr	r3, [fp, #-140]
	lsl	r3, r3, #3
	sub	r2, fp, #28
	add	r3, r2, r3
	sub	r3, r3, #80
	ldmia	r3, {r2-r3}
	adds	r6, r0, r2
	adc	r7, r1, r3
	ldr	r3, [fp, #-140]
	lsl	r3, r3, #3
	sub	r2, fp, #28
	add	r3, r2, r3
	sub	r3, r3, #80
	stm	r3, {r6-r7}
	ldr	r3, [fp, #-140]
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	ldr	r4, [r3, #-28]
	ldr	r3, [fp, #-152]
	ldr	r2, [fp, #-140]
	cmp	r2, #0
	movne	r2, #1
	moveq	r2, #0
	and	r2, r2, #255
	asr	lr, r3, r2
	ldr	r3, [fp, #-140]
	add	r3, r3, #3
	lsl	r3, r3, #2
	sub	r2, fp, #28
	add	r3, r2, r3
	ldr	ip, [r3, #-28]
	ldr	r2, [fp, #-152]
	ldr	r3, [fp, #-140]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	asr	r0, r2, r3
	ldr	r2, [fp, #-152]
	ldr	r3, [fp, #-140]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	asr	r1, r2, r3
	ldr	r2, [fp, #-148]
	ldr	r3, [fp, #-140]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	asr	r2, r2, r3
	mov	r3, #0
	str	r3, [sp, #12]
	ldr	r3, [fp, #-132]
	str	r3, [sp, #8]
	str	r2, [sp, #4]
	str	r1, [sp]
	mov	r3, r0
	mov	r2, ip
	mov	r1, lr
	mov	r0, r4
	bl	ssim_plane
	mov	r2, r0
	ldr	r3, [fp, #-140]
	lsl	r3, r3, #3
	sub	r1, fp, #28
	add	r3, r1, r3
	sub	r3, r3, #56
	ldmia	r3, {r4-r5}
	mov	r0, r2
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	ldr	r1, [fp, #-140]
	lsl	r1, r1, #3
	sub	r0, fp, #28
	add	r1, r0, r1
	sub	r1, r1, #56
	stm	r1, {r2-r3}
	ldr	r3, [fp, #-140]
	add	r3, r3, #1
	str	r3, [fp, #-140]
.L45:
	ldr	r3, [fp, #-140]
	cmp	r3, #2
	ble	.L48
	ldr	r3, [fp, #-144]
	add	r3, r3, #1
	str	r3, [fp, #-144]
	b	.L49
.L53:
	nop
	b	.L43
.L54:
	nop
.L43:
	ldr	r3, [fp, #-144]
	cmp	r3, #0
	bne	.L50
	mov	r3, #0
	b	.L51
.L50:
	sub	r7, fp, #108
	ldmia	r7, {r6-r7}
	ldr	r3, [fp, #-144]
	mov	r2, r3
	asr	r3, r2, #31
	ldr	r1, [fp, #-152]
	mov	r4, r1
	asr	r5, r4, #31
	mul	r0, r4, r3
	mul	r1, r2, r5
	add	ip, r0, r1
	umull	r0, r1, r2, r4
	add	r3, ip, r1
	mov	r1, r3
	ldr	r3, [fp, #-148]
	mov	r4, r3
	asr	r5, r4, #31
	mul	r2, r4, r1
	mul	r3, r0, r5
	add	ip, r2, r3
	umull	r2, r3, r0, r4
	add	r1, ip, r3
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	ssd_to_psnr
	str	r0, [fp, #-204]
	str	r1, [fp, #-200]
	sub	r9, fp, #100
	ldmia	r9, {r8-r9}
	ldr	r3, [fp, #-144]
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-152]
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-148]
	mov	r4, r3
	asr	r5, r4, #31
	mul	r2, r4, r7
	mul	r3, r6, r5
	add	r3, r2, r3
	umull	r0, r1, r6, r4
	add	r3, r3, r1
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #2
	orr	r2, r2, r1, lsl #30
	lsr	r3, r1, #2
	mov	r0, r8
	mov	r1, r9
	bl	ssd_to_psnr
	str	r0, [fp, #-212]
	str	r1, [fp, #-208]
	sub	r9, fp, #92
	ldmia	r9, {r8-r9}
	ldr	r3, [fp, #-144]
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-152]
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-148]
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r7
	mul	r3, r6, r1
	add	r3, r2, r3
	umull	r4, r5, r6, r0
	add	r3, r3, r5
	mov	r5, r3
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r4, #2
	orr	r2, r2, r5, lsl #30
	lsr	r3, r5, #2
	mov	r0, r8
	mov	r1, r9
	bl	ssd_to_psnr
	mov	r8, r0
	mov	r9, r1
	sub	r1, fp, #108
	ldmia	r1, {r0-r1}
	sub	r3, fp, #100
	ldmia	r3, {r2-r3}
	adds	ip, r0, r2
	str	ip, [fp, #-172]
	adc	r1, r1, r3
	str	r1, [fp, #-168]
	sub	r3, fp, #92
	ldmia	r3, {r2-r3}
	sub	r5, fp, #172
	ldmia	r5, {r4-r5}
	mov	r1, r4
	adds	r1, r1, r2
	str	r1, [fp, #-180]
	mov	r1, r5
	adc	r1, r1, r3
	str	r1, [fp, #-176]
	ldr	r3, [fp, #-144]
	mov	r4, r3
	asr	r5, r4, #31
	ldr	r3, [fp, #-152]
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r5
	mul	r3, r4, r1
	add	r3, r2, r3
	umull	r6, r7, r4, r0
	add	r3, r3, r7
	mov	r7, r3
	ldr	r3, [fp, #-148]
	mov	r0, r3
	asr	r1, r0, #31
	mul	r2, r0, r7
	mul	r3, r6, r1
	add	r3, r2, r3
	umull	r4, r5, r6, r0
	add	r3, r3, r5
	mov	r5, r3
	mov	r2, r4
	mov	r3, r5
	adds	r1, r2, r2
	str	r1, [fp, #-196]
	adc	r1, r3, r3
	str	r1, [fp, #-192]
	sub	r3, fp, #196
	ldmia	r3, {r2-r3}
	adds	r1, r2, r4
	str	r1, [fp, #-188]
	adc	r1, r3, r5
	str	r1, [fp, #-184]
	mov	r2, #0
	mov	r3, #0
	sub	r5, fp, #188
	ldmia	r5, {r4-r5}
	mov	r1, r4
	lsr	r2, r1, #1
	mov	r1, r5
	orr	r2, r2, r1, lsl #31
	mov	r1, r5
	lsr	r3, r1, #1
	sub	r1, fp, #180
	ldmia	r1, {r0-r1}
	bl	ssd_to_psnr
	mov	r2, r0
	mov	r3, r1
	str	r2, [sp, #16]
	str	r3, [sp, #20]
	str	r8, [sp, #8]
	str	r9, [sp, #12]
	sub	r4, fp, #212
	ldmia	r4, {r3-r4}
	stm	sp, {r3-r4}
	sub	r3, fp, #204
	ldmia	r3, {r2-r3}
	ldr	r0, .L55+16
	bl	printf
	sub	r5, fp, #84
	ldmia	r5, {r4-r5}
	ldr	r0, [fp, #-144]
	bl	__aeabi_i2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_ddiv
	mov	r2, r0
	mov	r3, r1
	mov	r8, r2
	mov	r9, r3
	sub	r5, fp, #76
	ldmia	r5, {r4-r5}
	ldr	r0, [fp, #-144]
	bl	__aeabi_i2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_ddiv
	mov	r2, r0
	mov	r3, r1
	mov	r6, r2
	mov	r7, r3
	sub	r5, fp, #68
	ldmia	r5, {r4-r5}
	ldr	r0, [fp, #-144]
	bl	__aeabi_i2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_ddiv
	mov	r2, r0
	mov	r3, r1
	mov	r4, r2
	mov	r5, r3
	sub	r1, fp, #84
	ldmia	r1, {r0-r1}
	mov	r2, #0
	ldr	r3, .L55+20
	bl	__aeabi_dmul
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	sub	r3, fp, #76
	ldmia	r3, {r2-r3}
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	sub	r3, fp, #68
	ldmia	r3, {r2-r3}
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	str	r2, [fp, #-172]
	str	r3, [fp, #-168]
	ldr	r2, [fp, #-144]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #1
	mov	r0, r3
	bl	__aeabi_i2d
	mov	r2, r0
	mov	r3, r1
	sub	r1, fp, #172
	ldmia	r1, {r0-r1}
	bl	__aeabi_ddiv
	mov	r2, r0
	mov	r3, r1
	str	r2, [sp, #16]
	str	r3, [sp, #20]
	str	r4, [sp, #8]
	str	r5, [sp, #12]
	stm	sp, {r6-r7}
	mov	r2, r8
	mov	r3, r9
	ldr	r0, .L55+24
	bl	printf
	mov	r3, #0
.L51:
	ldr	r2, .L55
	ldr	r1, [r2]
	ldr	r2, [fp, #-32]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L52
	bl	__stack_chk_fail
.L52:
	mov	r0, r3
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
.L56:
	.align	2
.L55:
	.word	.LC5
	.word	.LC0
	.word	.LC1
	.word	.LC2
	.word	.LC3
	.word	1074790400
	.word	.LC4
	.size	main, .-main
	.section	.rodata
	.align	2
	.type	ssim_c1.6235, %object
	.size	ssim_c1.6235, 4
ssim_c1.6235:
	.word	416
	.align	2
	.type	ssim_c2.6236, %object
	.size	ssim_c2.6236, 4
ssim_c2.6236:
	.word	235963
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
