	.file	"82951538.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_assert
	.type	__VERIFIER_assert, @function
__VERIFIER_assert:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	cmp	DWORD PTR -4[rbp], 0
	jne	.L5
	nop
.L3:
	mov	eax, 0
	call	__VERIFIER_error@PLT
.L5:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_assert, .-__VERIFIER_assert
	.globl	__global_lock
	.bss
	.align 4
	.type	__global_lock, @object
	.size	__global_lock, 4
__global_lock:
	.zero	4
	.text
	.globl	__VERIFIER_atomic_begin
	.type	__VERIFIER_atomic_begin, @function
__VERIFIER_atomic_begin:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR __global_lock[rip]
	test	eax, eax
	sete	al
	movzx	eax, al
	mov	edi, eax
	mov	eax, 0
	call	__VERIFIER_assume@PLT
	mov	DWORD PTR __global_lock[rip], 1
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	__VERIFIER_atomic_begin, .-__VERIFIER_atomic_begin
	.globl	__VERIFIER_atomic_end
	.type	__VERIFIER_atomic_end, @function
__VERIFIER_atomic_end:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR __global_lock[rip]
	cmp	eax, 1
	sete	al
	movzx	eax, al
	mov	edi, eax
	mov	eax, 0
	call	__VERIFIER_assume@PLT
	mov	DWORD PTR __global_lock[rip], 0
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	__VERIFIER_atomic_end, .-__VERIFIER_atomic_end
	.globl	__unbuffered_cnt
	.bss
	.align 4
	.type	__unbuffered_cnt, @object
	.size	__unbuffered_cnt, 4
__unbuffered_cnt:
	.zero	4
	.globl	__unbuffered_p0_EAX
	.align 4
	.type	__unbuffered_p0_EAX, @object
	.size	__unbuffered_p0_EAX, 4
__unbuffered_p0_EAX:
	.zero	4
	.globl	__unbuffered_p0_EAX$flush_delayed
	.type	__unbuffered_p0_EAX$flush_delayed, @object
	.size	__unbuffered_p0_EAX$flush_delayed, 1
__unbuffered_p0_EAX$flush_delayed:
	.zero	1
	.globl	__unbuffered_p0_EAX$mem_tmp
	.align 4
	.type	__unbuffered_p0_EAX$mem_tmp, @object
	.size	__unbuffered_p0_EAX$mem_tmp, 4
__unbuffered_p0_EAX$mem_tmp:
	.zero	4
	.globl	__unbuffered_p0_EAX$r_buff0_thd0
	.type	__unbuffered_p0_EAX$r_buff0_thd0, @object
	.size	__unbuffered_p0_EAX$r_buff0_thd0, 1
__unbuffered_p0_EAX$r_buff0_thd0:
	.zero	1
	.globl	__unbuffered_p0_EAX$r_buff0_thd1
	.type	__unbuffered_p0_EAX$r_buff0_thd1, @object
	.size	__unbuffered_p0_EAX$r_buff0_thd1, 1
__unbuffered_p0_EAX$r_buff0_thd1:
	.zero	1
	.globl	__unbuffered_p0_EAX$r_buff0_thd2
	.type	__unbuffered_p0_EAX$r_buff0_thd2, @object
	.size	__unbuffered_p0_EAX$r_buff0_thd2, 1
__unbuffered_p0_EAX$r_buff0_thd2:
	.zero	1
	.globl	__unbuffered_p0_EAX$r_buff0_thd3
	.type	__unbuffered_p0_EAX$r_buff0_thd3, @object
	.size	__unbuffered_p0_EAX$r_buff0_thd3, 1
__unbuffered_p0_EAX$r_buff0_thd3:
	.zero	1
	.globl	__unbuffered_p0_EAX$r_buff1_thd0
	.type	__unbuffered_p0_EAX$r_buff1_thd0, @object
	.size	__unbuffered_p0_EAX$r_buff1_thd0, 1
__unbuffered_p0_EAX$r_buff1_thd0:
	.zero	1
	.globl	__unbuffered_p0_EAX$r_buff1_thd1
	.type	__unbuffered_p0_EAX$r_buff1_thd1, @object
	.size	__unbuffered_p0_EAX$r_buff1_thd1, 1
__unbuffered_p0_EAX$r_buff1_thd1:
	.zero	1
	.globl	__unbuffered_p0_EAX$r_buff1_thd2
	.type	__unbuffered_p0_EAX$r_buff1_thd2, @object
	.size	__unbuffered_p0_EAX$r_buff1_thd2, 1
__unbuffered_p0_EAX$r_buff1_thd2:
	.zero	1
	.globl	__unbuffered_p0_EAX$r_buff1_thd3
	.type	__unbuffered_p0_EAX$r_buff1_thd3, @object
	.size	__unbuffered_p0_EAX$r_buff1_thd3, 1
__unbuffered_p0_EAX$r_buff1_thd3:
	.zero	1
	.globl	__unbuffered_p0_EAX$read_delayed
	.type	__unbuffered_p0_EAX$read_delayed, @object
	.size	__unbuffered_p0_EAX$read_delayed, 1
__unbuffered_p0_EAX$read_delayed:
	.zero	1
	.globl	__unbuffered_p0_EAX$read_delayed_var
	.align 8
	.type	__unbuffered_p0_EAX$read_delayed_var, @object
	.size	__unbuffered_p0_EAX$read_delayed_var, 8
__unbuffered_p0_EAX$read_delayed_var:
	.zero	8
	.globl	__unbuffered_p0_EAX$w_buff0
	.align 4
	.type	__unbuffered_p0_EAX$w_buff0, @object
	.size	__unbuffered_p0_EAX$w_buff0, 4
__unbuffered_p0_EAX$w_buff0:
	.zero	4
	.globl	__unbuffered_p0_EAX$w_buff0_used
	.type	__unbuffered_p0_EAX$w_buff0_used, @object
	.size	__unbuffered_p0_EAX$w_buff0_used, 1
__unbuffered_p0_EAX$w_buff0_used:
	.zero	1
	.globl	__unbuffered_p0_EAX$w_buff1
	.align 4
	.type	__unbuffered_p0_EAX$w_buff1, @object
	.size	__unbuffered_p0_EAX$w_buff1, 4
__unbuffered_p0_EAX$w_buff1:
	.zero	4
	.globl	__unbuffered_p0_EAX$w_buff1_used
	.type	__unbuffered_p0_EAX$w_buff1_used, @object
	.size	__unbuffered_p0_EAX$w_buff1_used, 1
__unbuffered_p0_EAX$w_buff1_used:
	.zero	1
	.globl	__unbuffered_p1_EAX
	.align 4
	.type	__unbuffered_p1_EAX, @object
	.size	__unbuffered_p1_EAX, 4
__unbuffered_p1_EAX:
	.zero	4
	.globl	__unbuffered_p2_EAX
	.align 4
	.type	__unbuffered_p2_EAX, @object
	.size	__unbuffered_p2_EAX, 4
__unbuffered_p2_EAX:
	.zero	4
	.globl	main$tmp_guard0
	.type	main$tmp_guard0, @object
	.size	main$tmp_guard0, 1
main$tmp_guard0:
	.zero	1
	.globl	main$tmp_guard1
	.type	main$tmp_guard1, @object
	.size	main$tmp_guard1, 1
main$tmp_guard1:
	.zero	1
	.globl	x
	.align 4
	.type	x, @object
	.size	x, 4
x:
	.zero	4
	.globl	y
	.align 4
	.type	y, @object
	.size	y, 4
y:
	.zero	4
	.globl	y$flush_delayed
	.type	y$flush_delayed, @object
	.size	y$flush_delayed, 1
y$flush_delayed:
	.zero	1
	.globl	y$mem_tmp
	.align 4
	.type	y$mem_tmp, @object
	.size	y$mem_tmp, 4
y$mem_tmp:
	.zero	4
	.globl	y$r_buff0_thd0
	.type	y$r_buff0_thd0, @object
	.size	y$r_buff0_thd0, 1
y$r_buff0_thd0:
	.zero	1
	.globl	y$r_buff0_thd1
	.type	y$r_buff0_thd1, @object
	.size	y$r_buff0_thd1, 1
y$r_buff0_thd1:
	.zero	1
	.globl	y$r_buff0_thd2
	.type	y$r_buff0_thd2, @object
	.size	y$r_buff0_thd2, 1
y$r_buff0_thd2:
	.zero	1
	.globl	y$r_buff0_thd3
	.type	y$r_buff0_thd3, @object
	.size	y$r_buff0_thd3, 1
y$r_buff0_thd3:
	.zero	1
	.globl	y$r_buff1_thd0
	.type	y$r_buff1_thd0, @object
	.size	y$r_buff1_thd0, 1
y$r_buff1_thd0:
	.zero	1
	.globl	y$r_buff1_thd1
	.type	y$r_buff1_thd1, @object
	.size	y$r_buff1_thd1, 1
y$r_buff1_thd1:
	.zero	1
	.globl	y$r_buff1_thd2
	.type	y$r_buff1_thd2, @object
	.size	y$r_buff1_thd2, 1
y$r_buff1_thd2:
	.zero	1
	.globl	y$r_buff1_thd3
	.type	y$r_buff1_thd3, @object
	.size	y$r_buff1_thd3, 1
y$r_buff1_thd3:
	.zero	1
	.globl	y$read_delayed
	.type	y$read_delayed, @object
	.size	y$read_delayed, 1
y$read_delayed:
	.zero	1
	.globl	y$read_delayed_var
	.align 8
	.type	y$read_delayed_var, @object
	.size	y$read_delayed_var, 8
y$read_delayed_var:
	.zero	8
	.globl	y$w_buff0
	.align 4
	.type	y$w_buff0, @object
	.size	y$w_buff0, 4
y$w_buff0:
	.zero	4
	.globl	y$w_buff0_used
	.type	y$w_buff0_used, @object
	.size	y$w_buff0_used, 1
y$w_buff0_used:
	.zero	1
	.globl	y$w_buff1
	.align 4
	.type	y$w_buff1, @object
	.size	y$w_buff1, 4
y$w_buff1:
	.zero	4
	.globl	y$w_buff1_used
	.type	y$w_buff1_used, @object
	.size	y$w_buff1_used, 1
y$w_buff1_used:
	.zero	1
	.globl	weak$$choice0
	.type	weak$$choice0, @object
	.size	weak$$choice0, 1
weak$$choice0:
	.zero	1
	.globl	weak$$choice1
	.type	weak$$choice1, @object
	.size	weak$$choice1, 1
weak$$choice1:
	.zero	1
	.globl	weak$$choice2
	.type	weak$$choice2, @object
	.size	weak$$choice2, 1
weak$$choice2:
	.zero	1
	.text
	.globl	P0
	.type	P0, @function
P0:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, 0
	call	nondet_0@PLT
	test	eax, eax
	setne	al
	mov	BYTE PTR weak$$choice0[rip], al
	mov	eax, 0
	call	nondet_0@PLT
	test	eax, eax
	setne	al
	mov	BYTE PTR weak$$choice2[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	mov	BYTE PTR y$flush_delayed[rip], al
	mov	eax, DWORD PTR y[rip]
	mov	DWORD PTR y$mem_tmp[rip], eax
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L11
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L11
.L12:
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	test	al, al
	jne	.L13
	movzx	eax, BYTE PTR y$r_buff1_thd1[rip]
	test	al, al
	je	.L11
.L13:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L14
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	test	al, al
	je	.L14
	mov	eax, DWORD PTR y$w_buff0[rip]
	jmp	.L16
.L14:
	mov	eax, DWORD PTR y$w_buff1[rip]
	jmp	.L16
.L11:
	mov	eax, DWORD PTR y[rip]
.L16:
	mov	DWORD PTR y[rip], eax
	mov	eax, DWORD PTR y$w_buff0[rip]
	mov	DWORD PTR y$w_buff0[rip], eax
	mov	eax, DWORD PTR y$w_buff1[rip]
	mov	DWORD PTR y$w_buff1[rip], eax
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L17
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L18
.L17:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L19
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L19
.L20:
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR y$r_buff1_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L21
.L19:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L18
.L21:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L23
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	test	al, al
	jne	.L24
.L23:
	mov	eax, 1
	jmp	.L25
.L24:
	mov	eax, 0
.L25:
	and	eax, 1
	test	al, al
	je	.L26
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L26
	mov	eax, 1
	jmp	.L18
.L26:
	mov	eax, 0
.L18:
	mov	BYTE PTR y$w_buff0_used[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L29
.L28:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L31
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L30
.L31:
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR y$r_buff1_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L32
.L30:
	mov	eax, 1
	jmp	.L33
.L32:
	mov	eax, 0
.L33:
	and	eax, 1
	test	al, al
	je	.L34
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L34
	mov	eax, 1
	jmp	.L29
.L34:
	mov	eax, 0
.L29:
	mov	BYTE PTR y$w_buff1_used[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L37
.L36:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L38
.L39:
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L40
	movzx	eax, BYTE PTR y$r_buff1_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L40
.L38:
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L37
.L40:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L42
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	test	al, al
	jne	.L43
.L42:
	mov	eax, 1
	jmp	.L44
.L43:
	mov	eax, 0
.L44:
	and	eax, 1
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	movzx	eax, al
	test	eax, eax
	je	.L45
	mov	eax, 1
	jmp	.L37
.L45:
	mov	eax, 0
.L37:
	mov	BYTE PTR y$r_buff0_thd1[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L47
	movzx	eax, BYTE PTR y$r_buff1_thd1[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L48
.L47:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L49
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L50
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L49
.L50:
	movzx	eax, BYTE PTR y$r_buff0_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L51
	movzx	eax, BYTE PTR y$r_buff1_thd1[rip]
	xor	eax, 1
	test	al, al
	je	.L51
.L49:
	mov	eax, 1
	jmp	.L52
.L51:
	mov	eax, 0
.L52:
	and	eax, 1
	test	al, al
	je	.L53
	movzx	eax, BYTE PTR y$r_buff1_thd1[rip]
	movzx	eax, al
	test	eax, eax
	je	.L53
	mov	eax, 1
	jmp	.L48
.L53:
	mov	eax, 0
.L48:
	mov	BYTE PTR y$r_buff1_thd1[rip], al
	mov	BYTE PTR __unbuffered_p0_EAX$read_delayed[rip], 1
	lea	rax, y[rip]
	mov	QWORD PTR __unbuffered_p0_EAX$read_delayed_var[rip], rax
	mov	eax, DWORD PTR y[rip]
	mov	DWORD PTR __unbuffered_p0_EAX[rip], eax
	movzx	eax, BYTE PTR y$flush_delayed[rip]
	test	al, al
	je	.L55
	mov	eax, DWORD PTR y$mem_tmp[rip]
	jmp	.L56
.L55:
	mov	eax, DWORD PTR y[rip]
.L56:
	mov	DWORD PTR y[rip], eax
	mov	BYTE PTR y$flush_delayed[rip], 0
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	DWORD PTR x[rip], 1
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, DWORD PTR __unbuffered_cnt[rip]
	add	eax, 1
	mov	DWORD PTR __unbuffered_cnt[rip], eax
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	nondet_1@PLT
	cdqe
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	P0, .-P0
	.globl	P1
	.type	P1, @function
P1:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, DWORD PTR x[rip]
	mov	DWORD PTR __unbuffered_p1_EAX[rip], eax
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	DWORD PTR y[rip], 1
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR y$r_buff0_thd2[rip]
	test	al, al
	jne	.L60
.L59:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR y$r_buff1_thd2[rip]
	test	al, al
	je	.L61
	mov	eax, DWORD PTR y$w_buff1[rip]
	jmp	.L63
.L61:
	mov	eax, DWORD PTR y[rip]
	jmp	.L63
.L60:
	mov	eax, DWORD PTR y$w_buff0[rip]
.L63:
	mov	DWORD PTR y[rip], eax
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L64
	movzx	eax, BYTE PTR y$r_buff0_thd2[rip]
	test	al, al
	jne	.L65
.L64:
	mov	eax, 1
	jmp	.L66
.L65:
	mov	eax, 0
.L66:
	and	eax, 1
	test	al, al
	je	.L67
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L67
	mov	eax, 1
	jmp	.L68
.L67:
	mov	eax, 0
.L68:
	mov	BYTE PTR y$w_buff0_used[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L69
	movzx	eax, BYTE PTR y$r_buff0_thd2[rip]
	test	al, al
	jne	.L70
.L69:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L71
	movzx	eax, BYTE PTR y$r_buff1_thd2[rip]
	test	al, al
	jne	.L70
.L71:
	mov	eax, 1
	jmp	.L72
.L70:
	mov	eax, 0
.L72:
	and	eax, 1
	test	al, al
	je	.L73
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L73
	mov	eax, 1
	jmp	.L74
.L73:
	mov	eax, 0
.L74:
	mov	BYTE PTR y$w_buff1_used[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L75
	movzx	eax, BYTE PTR y$r_buff0_thd2[rip]
	test	al, al
	jne	.L76
.L75:
	mov	eax, 1
	jmp	.L77
.L76:
	mov	eax, 0
.L77:
	and	eax, 1
	test	al, al
	je	.L78
	movzx	eax, BYTE PTR y$r_buff0_thd2[rip]
	movzx	eax, al
	test	eax, eax
	je	.L78
	mov	eax, 1
	jmp	.L79
.L78:
	mov	eax, 0
.L79:
	mov	BYTE PTR y$r_buff0_thd2[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L80
	movzx	eax, BYTE PTR y$r_buff0_thd2[rip]
	test	al, al
	jne	.L81
.L80:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L82
	movzx	eax, BYTE PTR y$r_buff1_thd2[rip]
	test	al, al
	jne	.L81
.L82:
	mov	eax, 1
	jmp	.L83
.L81:
	mov	eax, 0
.L83:
	and	eax, 1
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR y$r_buff1_thd2[rip]
	movzx	eax, al
	test	eax, eax
	je	.L84
	mov	eax, 1
	jmp	.L85
.L84:
	mov	eax, 0
.L85:
	mov	BYTE PTR y$r_buff1_thd2[rip], al
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, DWORD PTR __unbuffered_cnt[rip]
	add	eax, 1
	mov	DWORD PTR __unbuffered_cnt[rip], eax
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	nondet_1@PLT
	cdqe
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	P1, .-P1
	.globl	P2
	.type	P2, @function
P2:
.LFB5:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, 0
	call	nondet_0@PLT
	test	eax, eax
	setne	al
	mov	BYTE PTR weak$$choice0[rip], al
	mov	eax, 0
	call	nondet_0@PLT
	test	eax, eax
	setne	al
	mov	BYTE PTR weak$$choice2[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	mov	BYTE PTR y$flush_delayed[rip], al
	mov	eax, DWORD PTR y[rip]
	mov	DWORD PTR y$mem_tmp[rip], eax
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L88
.L89:
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L90
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	test	al, al
	je	.L88
.L90:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	je	.L91
	mov	eax, DWORD PTR y$w_buff0[rip]
	jmp	.L93
.L91:
	mov	eax, DWORD PTR y$w_buff1[rip]
	jmp	.L93
.L88:
	mov	eax, DWORD PTR y[rip]
.L93:
	mov	DWORD PTR y[rip], eax
	mov	eax, DWORD PTR y$w_buff0[rip]
	mov	DWORD PTR y$w_buff0[rip], eax
	mov	eax, DWORD PTR y$w_buff1[rip]
	mov	DWORD PTR y$w_buff1[rip], eax
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L94
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L95
.L94:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L96
.L97:
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L98
.L96:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L95
.L98:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L101
.L100:
	mov	eax, 1
	jmp	.L102
.L101:
	mov	eax, 0
.L102:
	and	eax, 1
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L103
	mov	eax, 1
	jmp	.L95
.L103:
	mov	eax, 0
.L95:
	mov	BYTE PTR y$w_buff0_used[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L106
.L105:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L107
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L107
.L108:
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L109
.L107:
	mov	eax, 1
	jmp	.L110
.L109:
	mov	eax, 0
.L110:
	and	eax, 1
	test	al, al
	je	.L111
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L111
	mov	eax, 1
	jmp	.L106
.L111:
	mov	eax, 0
.L106:
	mov	BYTE PTR y$w_buff1_used[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L113
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L114
.L113:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L115
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L115
.L116:
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L117
.L115:
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L114
.L117:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L120
.L119:
	mov	eax, 1
	jmp	.L121
.L120:
	mov	eax, 0
.L121:
	and	eax, 1
	test	al, al
	je	.L122
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	movzx	eax, al
	test	eax, eax
	je	.L122
	mov	eax, 1
	jmp	.L114
.L122:
	mov	eax, 0
.L114:
	mov	BYTE PTR y$r_buff0_thd3[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L124
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L125
.L124:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L127
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L126
.L127:
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	xor	eax, 1
	test	al, al
	je	.L128
.L126:
	mov	eax, 1
	jmp	.L129
.L128:
	mov	eax, 0
.L129:
	and	eax, 1
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	movzx	eax, al
	test	eax, eax
	je	.L130
	mov	eax, 1
	jmp	.L125
.L130:
	mov	eax, 0
.L125:
	mov	BYTE PTR y$r_buff1_thd3[rip], al
	mov	eax, DWORD PTR y[rip]
	mov	DWORD PTR __unbuffered_p2_EAX[rip], eax
	movzx	eax, BYTE PTR y$flush_delayed[rip]
	test	al, al
	je	.L132
	mov	eax, DWORD PTR y$mem_tmp[rip]
	jmp	.L133
.L132:
	mov	eax, DWORD PTR y[rip]
.L133:
	mov	DWORD PTR y[rip], eax
	mov	BYTE PTR y$flush_delayed[rip], 0
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	DWORD PTR y[rip], 2
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L134
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L135
.L134:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L136
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	test	al, al
	je	.L136
	mov	eax, DWORD PTR y$w_buff1[rip]
	jmp	.L138
.L136:
	mov	eax, DWORD PTR y[rip]
	jmp	.L138
.L135:
	mov	eax, DWORD PTR y$w_buff0[rip]
.L138:
	mov	DWORD PTR y[rip], eax
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L139
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L140
.L139:
	mov	eax, 1
	jmp	.L141
.L140:
	mov	eax, 0
.L141:
	and	eax, 1
	test	al, al
	je	.L142
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L142
	mov	eax, 1
	jmp	.L143
.L142:
	mov	eax, 0
.L143:
	mov	BYTE PTR y$w_buff0_used[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L145
.L144:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	test	al, al
	jne	.L145
.L146:
	mov	eax, 1
	jmp	.L147
.L145:
	mov	eax, 0
.L147:
	and	eax, 1
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L148
	mov	eax, 1
	jmp	.L149
.L148:
	mov	eax, 0
.L149:
	mov	BYTE PTR y$w_buff1_used[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L150
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L151
.L150:
	mov	eax, 1
	jmp	.L152
.L151:
	mov	eax, 0
.L152:
	and	eax, 1
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	movzx	eax, al
	test	eax, eax
	je	.L153
	mov	eax, 1
	jmp	.L154
.L153:
	mov	eax, 0
.L154:
	mov	BYTE PTR y$r_buff0_thd3[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L155
	movzx	eax, BYTE PTR y$r_buff0_thd3[rip]
	test	al, al
	jne	.L156
.L155:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	test	al, al
	jne	.L156
.L157:
	mov	eax, 1
	jmp	.L158
.L156:
	mov	eax, 0
.L158:
	and	eax, 1
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR y$r_buff1_thd3[rip]
	movzx	eax, al
	test	eax, eax
	je	.L159
	mov	eax, 1
	jmp	.L160
.L159:
	mov	eax, 0
.L160:
	mov	BYTE PTR y$r_buff1_thd3[rip], al
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, DWORD PTR __unbuffered_cnt[rip]
	add	eax, 1
	mov	DWORD PTR __unbuffered_cnt[rip], eax
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	nondet_1@PLT
	cdqe
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	P2, .-P2
	.globl	fence
	.type	fence, @function
fence:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	fence, .-fence
	.globl	isync
	.type	isync, @function
isync:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	isync, .-isync
	.globl	lwfence
	.type	lwfence, @function
lwfence:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	lwfence, .-lwfence
	.globl	main
	.type	main, @function
main:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	ecx, 0
	lea	rdx, P0[rip]
	mov	esi, 0
	mov	edi, 0
	call	pthread_create@PLT
	mov	ecx, 0
	lea	rdx, P1[rip]
	mov	esi, 0
	mov	edi, 0
	call	pthread_create@PLT
	mov	ecx, 0
	lea	rdx, P2[rip]
	mov	esi, 0
	mov	edi, 0
	call	pthread_create@PLT
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, DWORD PTR __unbuffered_cnt[rip]
	cmp	eax, 3
	sete	al
	mov	BYTE PTR main$tmp_guard0[rip], al
	mov	eax, 0
	call	__VERIFIER_atomic_end
	movzx	eax, BYTE PTR main$tmp_guard0[rip]
	movzx	eax, al
	mov	edi, eax
	mov	eax, 0
	call	__VERIFIER_assume@PLT
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L166
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L167
.L166:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	test	al, al
	je	.L168
	mov	eax, DWORD PTR y$w_buff1[rip]
	jmp	.L170
.L168:
	mov	eax, DWORD PTR y[rip]
	jmp	.L170
.L167:
	mov	eax, DWORD PTR y$w_buff0[rip]
.L170:
	mov	DWORD PTR y[rip], eax
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L171
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L172
.L171:
	mov	eax, 1
	jmp	.L173
.L172:
	mov	eax, 0
.L173:
	and	eax, 1
	test	al, al
	je	.L174
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L174
	mov	eax, 1
	jmp	.L175
.L174:
	mov	eax, 0
.L175:
	mov	BYTE PTR y$w_buff0_used[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L177
.L176:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L178
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	test	al, al
	jne	.L177
.L178:
	mov	eax, 1
	jmp	.L179
.L177:
	mov	eax, 0
.L179:
	and	eax, 1
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L180
	mov	eax, 1
	jmp	.L181
.L180:
	mov	eax, 0
.L181:
	mov	BYTE PTR y$w_buff1_used[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L183
.L182:
	mov	eax, 1
	jmp	.L184
.L183:
	mov	eax, 0
.L184:
	and	eax, 1
	test	al, al
	je	.L185
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	movzx	eax, al
	test	eax, eax
	je	.L185
	mov	eax, 1
	jmp	.L186
.L185:
	mov	eax, 0
.L186:
	mov	BYTE PTR y$r_buff0_thd0[rip], al
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L188
.L187:
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	test	al, al
	jne	.L188
.L189:
	mov	eax, 1
	jmp	.L190
.L188:
	mov	eax, 0
.L190:
	and	eax, 1
	test	al, al
	je	.L191
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	movzx	eax, al
	test	eax, eax
	je	.L191
	mov	eax, 1
	jmp	.L192
.L191:
	mov	eax, 0
.L192:
	mov	BYTE PTR y$r_buff1_thd0[rip], al
	mov	eax, 0
	call	__VERIFIER_atomic_end
	mov	eax, 0
	call	__VERIFIER_atomic_begin
	mov	eax, 0
	call	nondet_0@PLT
	test	eax, eax
	setne	al
	mov	BYTE PTR weak$$choice0[rip], al
	mov	eax, 0
	call	nondet_0@PLT
	test	eax, eax
	setne	al
	mov	BYTE PTR weak$$choice2[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	mov	BYTE PTR y$flush_delayed[rip], al
	mov	eax, DWORD PTR y[rip]
	mov	DWORD PTR y$mem_tmp[rip], eax
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	test	al, al
	je	.L193
.L194:
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L195
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	test	al, al
	je	.L193
.L195:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	je	.L196
	mov	eax, DWORD PTR y$w_buff0[rip]
	jmp	.L198
.L196:
	mov	eax, DWORD PTR y$w_buff1[rip]
	jmp	.L198
.L193:
	mov	eax, DWORD PTR y[rip]
.L198:
	mov	DWORD PTR y[rip], eax
	mov	eax, DWORD PTR y$w_buff0[rip]
	mov	DWORD PTR y$w_buff0[rip], eax
	mov	eax, DWORD PTR y$w_buff1[rip]
	mov	DWORD PTR y$w_buff1[rip], eax
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L199
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L200
.L199:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L202
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L201
.L202:
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L203
.L201:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L200
.L203:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L206
.L205:
	mov	eax, 1
	jmp	.L207
.L206:
	mov	eax, 0
.L207:
	and	eax, 1
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L208
	mov	eax, 1
	jmp	.L200
.L208:
	mov	eax, 0
.L200:
	mov	BYTE PTR y$w_buff0_used[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L210
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L211
.L210:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L212
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L213
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L212
.L213:
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L214
.L212:
	mov	eax, 1
	jmp	.L215
.L214:
	mov	eax, 0
.L215:
	and	eax, 1
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	movzx	eax, al
	test	eax, eax
	je	.L216
	mov	eax, 1
	jmp	.L211
.L216:
	mov	eax, 0
.L211:
	mov	BYTE PTR y$w_buff1_used[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L218
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L219
.L218:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L220
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L220
.L221:
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L222
.L220:
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L219
.L222:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	test	al, al
	jne	.L225
.L224:
	mov	eax, 1
	jmp	.L226
.L225:
	mov	eax, 0
.L226:
	and	eax, 1
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	movzx	eax, al
	test	eax, eax
	je	.L227
	mov	eax, 1
	jmp	.L219
.L227:
	mov	eax, 0
.L219:
	mov	BYTE PTR y$r_buff0_thd0[rip], al
	movzx	eax, BYTE PTR weak$$choice2[rip]
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	movzx	eax, al
	test	eax, eax
	setne	al
	jmp	.L230
.L229:
	movzx	eax, BYTE PTR y$w_buff0_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L231
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR y$w_buff1_used[rip]
	xor	eax, 1
	test	al, al
	jne	.L231
.L232:
	movzx	eax, BYTE PTR y$r_buff0_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	xor	eax, 1
	test	al, al
	je	.L233
.L231:
	mov	eax, 1
	jmp	.L234
.L233:
	mov	eax, 0
.L234:
	and	eax, 1
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR y$r_buff1_thd0[rip]
	movzx	eax, al
	test	eax, eax
	je	.L235
	mov	eax, 1
	jmp	.L230
.L235:
	mov	eax, 0
.L230:
	mov	BYTE PTR y$r_buff1_thd0[rip], al
	mov	eax, 0
	call	nondet_0@PLT
	test	eax, eax
	setne	al
	mov	BYTE PTR weak$$choice1[rip], al
	movzx	eax, BYTE PTR __unbuffered_p0_EAX$read_delayed[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR weak$$choice1[rip]
	test	al, al
	je	.L238
	mov	rax, QWORD PTR __unbuffered_p0_EAX$read_delayed_var[rip]
	mov	eax, DWORD PTR [rax]
	jmp	.L240
.L238:
	mov	eax, DWORD PTR __unbuffered_p0_EAX[rip]
	jmp	.L240
.L237:
	mov	eax, DWORD PTR __unbuffered_p0_EAX[rip]
.L240:
	mov	DWORD PTR __unbuffered_p0_EAX[rip], eax
	mov	eax, DWORD PTR y[rip]
	cmp	eax, 2
	jne	.L241
	mov	eax, DWORD PTR __unbuffered_p0_EAX[rip]
	cmp	eax, 2
	jne	.L241
	mov	eax, DWORD PTR __unbuffered_p1_EAX[rip]
	cmp	eax, 1
	jne	.L241
	mov	eax, DWORD PTR __unbuffered_p2_EAX[rip]
	cmp	eax, 1
	je	.L242
.L241:
	mov	eax, 1
	jmp	.L243
.L242:
	mov	eax, 0
.L243:
	and	eax, 1
	mov	BYTE PTR main$tmp_guard1[rip], al
	movzx	eax, BYTE PTR y$flush_delayed[rip]
	test	al, al
	je	.L244
	mov	eax, DWORD PTR y$mem_tmp[rip]
	jmp	.L245
.L244:
	mov	eax, DWORD PTR y[rip]
.L245:
	mov	DWORD PTR y[rip], eax
	mov	BYTE PTR y$flush_delayed[rip], 0
	mov	eax, 0
	call	__VERIFIER_atomic_end
	movzx	eax, BYTE PTR main$tmp_guard1[rip]
	movzx	eax, al
	mov	edi, eax
	call	__VERIFIER_assert
	mov	eax, 0
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"82951538.c"
	.text
	.align	2
	.global	__VERIFIER_assert
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_assert, %function
__VERIFIER_assert:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L5
	nop
.L3:
	bl	__VERIFIER_error
.L5:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__VERIFIER_assert, .-__VERIFIER_assert
	.comm	__global_lock,4,4
	.align	2
	.global	__VERIFIER_atomic_begin
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_atomic_begin, %function
__VERIFIER_atomic_begin:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	ldr	r3, .L8
	ldr	r3, [r3]
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	bl	__VERIFIER_assume
	ldr	r3, .L8
	mov	r2, #1
	str	r2, [r3]
	nop
	pop	{fp, pc}
.L9:
	.align	2
.L8:
	.word	__global_lock
	.size	__VERIFIER_atomic_begin, .-__VERIFIER_atomic_begin
	.align	2
	.global	__VERIFIER_atomic_end
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_atomic_end, %function
__VERIFIER_atomic_end:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	ldr	r3, .L12
	ldr	r3, [r3]
	cmp	r3, #1
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	bl	__VERIFIER_assume
	ldr	r3, .L12
	mov	r2, #0
	str	r2, [r3]
	nop
	pop	{fp, pc}
.L13:
	.align	2
.L12:
	.word	__global_lock
	.size	__VERIFIER_atomic_end, .-__VERIFIER_atomic_end
	.global	__unbuffered_cnt
	.bss
	.align	2
	.type	__unbuffered_cnt, %object
	.size	__unbuffered_cnt, 4
__unbuffered_cnt:
	.space	4
	.global	__unbuffered_p0_EAX
	.align	2
	.type	__unbuffered_p0_EAX, %object
	.size	__unbuffered_p0_EAX, 4
__unbuffered_p0_EAX:
	.space	4
	.comm	__unbuffered_p0_EAX$flush_delayed,1,1
	.comm	__unbuffered_p0_EAX$mem_tmp,4,4
	.comm	__unbuffered_p0_EAX$r_buff0_thd0,1,1
	.comm	__unbuffered_p0_EAX$r_buff0_thd1,1,1
	.comm	__unbuffered_p0_EAX$r_buff0_thd2,1,1
	.comm	__unbuffered_p0_EAX$r_buff0_thd3,1,1
	.comm	__unbuffered_p0_EAX$r_buff1_thd0,1,1
	.comm	__unbuffered_p0_EAX$r_buff1_thd1,1,1
	.comm	__unbuffered_p0_EAX$r_buff1_thd2,1,1
	.comm	__unbuffered_p0_EAX$r_buff1_thd3,1,1
	.comm	__unbuffered_p0_EAX$read_delayed,1,1
	.comm	__unbuffered_p0_EAX$read_delayed_var,4,4
	.comm	__unbuffered_p0_EAX$w_buff0,4,4
	.comm	__unbuffered_p0_EAX$w_buff0_used,1,1
	.comm	__unbuffered_p0_EAX$w_buff1,4,4
	.comm	__unbuffered_p0_EAX$w_buff1_used,1,1
	.global	__unbuffered_p1_EAX
	.align	2
	.type	__unbuffered_p1_EAX, %object
	.size	__unbuffered_p1_EAX, 4
__unbuffered_p1_EAX:
	.space	4
	.global	__unbuffered_p2_EAX
	.align	2
	.type	__unbuffered_p2_EAX, %object
	.size	__unbuffered_p2_EAX, 4
__unbuffered_p2_EAX:
	.space	4
	.comm	main$tmp_guard0,1,1
	.comm	main$tmp_guard1,1,1
	.global	x
	.align	2
	.type	x, %object
	.size	x, 4
x:
	.space	4
	.global	y
	.align	2
	.type	y, %object
	.size	y, 4
y:
	.space	4
	.comm	y$flush_delayed,1,1
	.comm	y$mem_tmp,4,4
	.comm	y$r_buff0_thd0,1,1
	.comm	y$r_buff0_thd1,1,1
	.comm	y$r_buff0_thd2,1,1
	.comm	y$r_buff0_thd3,1,1
	.comm	y$r_buff1_thd0,1,1
	.comm	y$r_buff1_thd1,1,1
	.comm	y$r_buff1_thd2,1,1
	.comm	y$r_buff1_thd3,1,1
	.comm	y$read_delayed,1,1
	.comm	y$read_delayed_var,4,4
	.comm	y$w_buff0,4,4
	.comm	y$w_buff0_used,1,1
	.comm	y$w_buff1,4,4
	.comm	y$w_buff1_used,1,1
	.comm	weak$$choice0,1,1
	.comm	weak$$choice1,1,1
	.comm	weak$$choice2,1,1
	.text
	.align	2
	.global	P0
	.syntax unified
	.arm
	.fpu softvfp
	.type	P0, %function
P0:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	bl	__VERIFIER_atomic_begin
	bl	nondet_0
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L62
	strb	r2, [r3]
	bl	nondet_0
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L62+4
	strb	r2, [r3]
	ldr	r3, .L62+4
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L62+8
	strb	r2, [r3]
	ldr	r3, .L62+12
	ldr	r3, [r3]
	ldr	r2, .L62+16
	str	r3, [r2]
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L62+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
.L16:
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L17
	ldr	r3, .L62+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
.L17:
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
	ldr	r3, .L62+36
	ldr	r3, [r3]
	b	.L20
.L18:
	ldr	r3, .L62+40
	ldr	r3, [r3]
	b	.L20
.L15:
	ldr	r3, .L62+12
	ldr	r3, [r3]
.L20:
	ldr	r2, .L62+12
	str	r3, [r2]
	ldr	r3, .L62+36
	ldr	r3, [r3]
	ldr	r2, .L62+36
	str	r3, [r2]
	ldr	r3, .L62+40
	ldr	r3, [r3]
	ldr	r2, .L62+40
	str	r3, [r2]
	ldr	r3, .L62+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L22
.L21:
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L23
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L62+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L23
.L24:
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L62+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L25
.L23:
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L22
.L25:
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L28
.L27:
	mov	r3, #1
	b	.L29
.L28:
	mov	r3, #0
.L29:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L30
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
	mov	r3, #1
	b	.L22
.L30:
	mov	r3, #0
.L22:
	ldr	r2, .L62+20
	strb	r3, [r2]
	ldr	r3, .L62+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L62+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L33
.L32:
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L35
	ldr	r3, .L62+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L34
.L35:
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L62+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L36
.L34:
	mov	r3, #1
	b	.L37
.L36:
	mov	r3, #0
.L37:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L38
	ldr	r3, .L62+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
	mov	r3, #1
	b	.L33
.L38:
	mov	r3, #0
.L33:
	ldr	r2, .L62+28
	strb	r3, [r2]
	ldr	r3, .L62+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L41
.L40:
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L62+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L42
.L43:
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L62+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L44
.L42:
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L41
.L44:
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L47
.L46:
	mov	r3, #1
	b	.L48
.L47:
	mov	r3, #0
.L48:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	mov	r3, #1
	b	.L41
.L49:
	mov	r3, #0
.L41:
	ldr	r2, .L62+24
	strb	r3, [r2]
	ldr	r3, .L62+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
	ldr	r3, .L62+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L52
.L51:
	ldr	r3, .L62+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L53
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L62+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L53
.L54:
	ldr	r3, .L62+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L62+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L55
.L53:
	mov	r3, #1
	b	.L56
.L55:
	mov	r3, #0
.L56:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L62+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	mov	r3, #1
	b	.L52
.L57:
	mov	r3, #0
.L52:
	ldr	r2, .L62+32
	strb	r3, [r2]
	ldr	r3, .L62+44
	mov	r2, #1
	strb	r2, [r3]
	ldr	r3, .L62+48
	ldr	r2, .L62+12
	str	r2, [r3]
	ldr	r3, .L62+12
	ldr	r3, [r3]
	ldr	r2, .L62+52
	str	r3, [r2]
	ldr	r3, .L62+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L62+16
	ldr	r3, [r3]
	b	.L60
.L59:
	ldr	r3, .L62+12
	ldr	r3, [r3]
.L60:
	ldr	r2, .L62+12
	str	r3, [r2]
	ldr	r3, .L62+8
	mov	r2, #0
	strb	r2, [r3]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L62+56
	mov	r2, #1
	str	r2, [r3]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L62+60
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L62+60
	str	r3, [r2]
	bl	__VERIFIER_atomic_end
	bl	nondet_1
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L63:
	.align	2
.L62:
	.word	weak$$choice0
	.word	weak$$choice2
	.word	y$flush_delayed
	.word	y
	.word	y$mem_tmp
	.word	y$w_buff0_used
	.word	y$r_buff0_thd1
	.word	y$w_buff1_used
	.word	y$r_buff1_thd1
	.word	y$w_buff0
	.word	y$w_buff1
	.word	__unbuffered_p0_EAX$read_delayed
	.word	__unbuffered_p0_EAX$read_delayed_var
	.word	__unbuffered_p0_EAX
	.word	x
	.word	__unbuffered_cnt
	.size	P0, .-P0
	.align	2
	.global	P1
	.syntax unified
	.arm
	.fpu softvfp
	.type	P1, %function
P1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L93
	ldr	r3, [r3]
	ldr	r2, .L93+4
	str	r3, [r2]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L93+8
	mov	r2, #1
	str	r2, [r3]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L93+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
	ldr	r3, .L93+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
.L65:
	ldr	r3, .L93+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
	ldr	r3, .L93+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
	ldr	r3, .L93+28
	ldr	r3, [r3]
	b	.L69
.L67:
	ldr	r3, .L93+8
	ldr	r3, [r3]
	b	.L69
.L66:
	ldr	r3, .L93+32
	ldr	r3, [r3]
.L69:
	ldr	r2, .L93+8
	str	r3, [r2]
	ldr	r3, .L93+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L93+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L71
.L70:
	mov	r3, #1
	b	.L72
.L71:
	mov	r3, #0
.L72:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L73
	ldr	r3, .L93+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L73
	mov	r2, #1
	b	.L74
.L73:
	mov	r2, #0
.L74:
	ldr	r3, .L93+12
	strb	r2, [r3]
	ldr	r3, .L93+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
	ldr	r3, .L93+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
.L75:
	ldr	r3, .L93+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L77
	ldr	r3, .L93+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
.L77:
	mov	r3, #1
	b	.L78
.L76:
	mov	r3, #0
.L78:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L93+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	mov	r2, #1
	b	.L80
.L79:
	mov	r2, #0
.L80:
	ldr	r3, .L93+20
	strb	r2, [r3]
	ldr	r3, .L93+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L93+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
.L81:
	mov	r3, #1
	b	.L83
.L82:
	mov	r3, #0
.L83:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L93+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	mov	r2, #1
	b	.L85
.L84:
	mov	r2, #0
.L85:
	ldr	r3, .L93+16
	strb	r2, [r3]
	ldr	r3, .L93+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
	ldr	r3, .L93+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
.L86:
	ldr	r3, .L93+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L93+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L87
.L88:
	mov	r3, #1
	b	.L89
.L87:
	mov	r3, #0
.L89:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L90
	ldr	r3, .L93+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
	mov	r2, #1
	b	.L91
.L90:
	mov	r2, #0
.L91:
	ldr	r3, .L93+24
	strb	r2, [r3]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L93+36
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L93+36
	str	r3, [r2]
	bl	__VERIFIER_atomic_end
	bl	nondet_1
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L94:
	.align	2
.L93:
	.word	x
	.word	__unbuffered_p1_EAX
	.word	y
	.word	y$w_buff0_used
	.word	y$r_buff0_thd2
	.word	y$w_buff1_used
	.word	y$r_buff1_thd2
	.word	y$w_buff1
	.word	y$w_buff0
	.word	__unbuffered_cnt
	.size	P1, .-P1
	.align	2
	.global	P2
	.syntax unified
	.arm
	.fpu softvfp
	.type	P2, %function
P2:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	bl	__VERIFIER_atomic_begin
	bl	nondet_0
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L170
	strb	r2, [r3]
	bl	nondet_0
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L170+4
	strb	r2, [r3]
	ldr	r3, .L170+4
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L170+8
	strb	r2, [r3]
	ldr	r3, .L170+12
	ldr	r3, [r3]
	ldr	r2, .L170+16
	str	r3, [r2]
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
.L97:
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
.L98:
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L170+36
	ldr	r3, [r3]
	b	.L101
.L99:
	ldr	r3, .L170+40
	ldr	r3, [r3]
	b	.L101
.L96:
	ldr	r3, .L170+12
	ldr	r3, [r3]
.L101:
	ldr	r2, .L170+12
	str	r3, [r2]
	ldr	r3, .L170+36
	ldr	r3, [r3]
	ldr	r2, .L170+36
	str	r3, [r2]
	ldr	r3, .L170+40
	ldr	r3, [r3]
	ldr	r2, .L170+40
	str	r3, [r2]
	ldr	r3, .L170+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L103
.L102:
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L104
.L105:
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L106
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L106
.L104:
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L103
.L106:
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
.L108:
	mov	r3, #1
	b	.L110
.L109:
	mov	r3, #0
.L110:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L111
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
	mov	r3, #1
	b	.L103
.L111:
	mov	r3, #0
.L103:
	ldr	r2, .L170+20
	strb	r3, [r2]
	ldr	r3, .L170+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L113
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L114
.L113:
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L115
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L115
.L116:
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L117
.L115:
	mov	r3, #1
	b	.L118
.L117:
	mov	r3, #0
.L118:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	mov	r3, #1
	b	.L114
.L119:
	mov	r3, #0
.L114:
	ldr	r2, .L170+28
	strb	r3, [r2]
	ldr	r3, .L170+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L122
.L121:
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L123
.L124:
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L125
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L125
.L123:
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L122
.L125:
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
.L127:
	mov	r3, #1
	b	.L129
.L128:
	mov	r3, #0
.L129:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
	mov	r3, #1
	b	.L122
.L130:
	mov	r3, #0
.L122:
	ldr	r2, .L170+24
	strb	r3, [r2]
	ldr	r3, .L170+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L133
.L132:
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L134
.L135:
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L136
.L134:
	mov	r3, #1
	b	.L137
.L136:
	mov	r3, #0
.L137:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	mov	r3, #1
	b	.L133
.L138:
	mov	r3, #0
.L133:
	ldr	r2, .L170+32
	strb	r3, [r2]
	ldr	r3, .L170+12
	ldr	r3, [r3]
	ldr	r2, .L170+44
	str	r3, [r2]
	ldr	r3, .L170+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L170+16
	ldr	r3, [r3]
	b	.L141
.L140:
	ldr	r3, .L170+12
	ldr	r3, [r3]
.L141:
	ldr	r2, .L170+12
	str	r3, [r2]
	ldr	r3, .L170+8
	mov	r2, #0
	strb	r2, [r3]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L170+12
	mov	r2, #2
	str	r2, [r3]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
.L142:
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L170+40
	ldr	r3, [r3]
	b	.L146
.L144:
	ldr	r3, .L170+12
	ldr	r3, [r3]
	b	.L146
.L143:
	ldr	r3, .L170+36
	ldr	r3, [r3]
.L146:
	ldr	r2, .L170+12
	str	r3, [r2]
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
.L147:
	mov	r3, #1
	b	.L149
.L148:
	mov	r3, #0
.L149:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L150
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
	mov	r2, #1
	b	.L151
.L150:
	mov	r2, #0
.L151:
	ldr	r3, .L170+20
	strb	r2, [r3]
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L153
.L152:
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L153
.L154:
	mov	r3, #1
	b	.L155
.L153:
	mov	r3, #0
.L155:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	mov	r2, #1
	b	.L157
.L156:
	mov	r2, #0
.L157:
	ldr	r3, .L170+28
	strb	r2, [r3]
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L159
.L158:
	mov	r3, #1
	b	.L160
.L159:
	mov	r3, #0
.L160:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L161
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L161
	mov	r2, #1
	b	.L162
.L161:
	mov	r2, #0
.L162:
	ldr	r3, .L170+24
	strb	r2, [r3]
	ldr	r3, .L170+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
	ldr	r3, .L170+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L164
.L163:
	ldr	r3, .L170+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L164
.L165:
	mov	r3, #1
	b	.L166
.L164:
	mov	r3, #0
.L166:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L167
	ldr	r3, .L170+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
	mov	r2, #1
	b	.L168
.L167:
	mov	r2, #0
.L168:
	ldr	r3, .L170+32
	strb	r2, [r3]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L170+48
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L170+48
	str	r3, [r2]
	bl	__VERIFIER_atomic_end
	bl	nondet_1
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L171:
	.align	2
.L170:
	.word	weak$$choice0
	.word	weak$$choice2
	.word	y$flush_delayed
	.word	y
	.word	y$mem_tmp
	.word	y$w_buff0_used
	.word	y$r_buff0_thd3
	.word	y$w_buff1_used
	.word	y$r_buff1_thd3
	.word	y$w_buff0
	.word	y$w_buff1
	.word	__unbuffered_p2_EAX
	.word	__unbuffered_cnt
	.size	P2, .-P2
	.align	2
	.global	fence
	.syntax unified
	.arm
	.fpu softvfp
	.type	fence, %function
fence:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	fence, .-fence
	.align	2
	.global	isync
	.syntax unified
	.arm
	.fpu softvfp
	.type	isync, %function
isync:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	isync, .-isync
	.align	2
	.global	lwfence
	.syntax unified
	.arm
	.fpu softvfp
	.type	lwfence, %function
lwfence:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	lwfence, .-lwfence
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	mov	r3, #0
	ldr	r2, .L257
	mov	r1, #0
	mov	r0, #0
	bl	pthread_create
	mov	r3, #0
	ldr	r2, .L257+4
	mov	r1, #0
	mov	r0, #0
	bl	pthread_create
	mov	r3, #0
	ldr	r2, .L257+8
	mov	r1, #0
	mov	r0, #0
	bl	pthread_create
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L257+12
	ldr	r3, [r3]
	cmp	r3, #3
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+16
	strb	r2, [r3]
	bl	__VERIFIER_atomic_end
	ldr	r3, .L257+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r0, r3
	bl	__VERIFIER_assume
	bl	__VERIFIER_atomic_begin
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
.L176:
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L257+36
	ldr	r3, [r3]
	b	.L180
.L178:
	ldr	r3, .L257+40
	ldr	r3, [r3]
	b	.L180
.L177:
	ldr	r3, .L257+44
	ldr	r3, [r3]
.L180:
	ldr	r2, .L257+40
	str	r3, [r2]
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
.L181:
	mov	r3, #1
	b	.L183
.L182:
	mov	r3, #0
.L183:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	mov	r2, #1
	b	.L185
.L184:
	mov	r2, #0
.L185:
	ldr	r3, .L257+20
	strb	r2, [r3]
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L187
.L186:
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L187
.L188:
	mov	r3, #1
	b	.L189
.L187:
	mov	r3, #0
.L189:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	mov	r2, #1
	b	.L191
.L190:
	mov	r2, #0
.L191:
	ldr	r3, .L257+28
	strb	r2, [r3]
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
.L192:
	mov	r3, #1
	b	.L194
.L193:
	mov	r3, #0
.L194:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	mov	r2, #1
	b	.L196
.L195:
	mov	r2, #0
.L196:
	ldr	r3, .L257+24
	strb	r2, [r3]
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
.L197:
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
.L199:
	mov	r3, #1
	b	.L200
.L198:
	mov	r3, #0
.L200:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	mov	r2, #1
	b	.L202
.L201:
	mov	r2, #0
.L202:
	ldr	r3, .L257+32
	strb	r2, [r3]
	bl	__VERIFIER_atomic_end
	bl	__VERIFIER_atomic_begin
	bl	nondet_0
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+48
	strb	r2, [r3]
	bl	nondet_0
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+52
	strb	r2, [r3]
	ldr	r3, .L257+52
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L257+56
	strb	r2, [r3]
	ldr	r3, .L257+40
	ldr	r3, [r3]
	ldr	r2, .L257+60
	str	r3, [r2]
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
.L204:
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
.L205:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L257+44
	ldr	r3, [r3]
	b	.L208
.L206:
	ldr	r3, .L257+36
	ldr	r3, [r3]
	b	.L208
.L203:
	ldr	r3, .L257+40
	ldr	r3, [r3]
.L208:
	ldr	r2, .L257+40
	str	r3, [r2]
	ldr	r3, .L257+44
	ldr	r3, [r3]
	ldr	r2, .L257+44
	str	r3, [r2]
	ldr	r3, .L257+36
	ldr	r3, [r3]
	ldr	r2, .L257+36
	str	r3, [r2]
	ldr	r3, .L257+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L210
.L209:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L211
.L212:
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L213
.L211:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L210
.L213:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
.L215:
	mov	r3, #1
	b	.L217
.L216:
	mov	r3, #0
.L217:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	mov	r3, #1
	b	.L210
.L218:
	mov	r3, #0
.L210:
	ldr	r2, .L257+20
	strb	r3, [r2]
	ldr	r3, .L257+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L221
.L220:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L222
.L223:
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L224
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L224
.L222:
	mov	r3, #1
	b	.L225
.L224:
	mov	r3, #0
.L225:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	mov	r3, #1
	b	.L221
.L226:
	mov	r3, #0
.L221:
	ldr	r2, .L257+28
	strb	r3, [r2]
	ldr	r3, .L257+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L229
.L228:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L230
.L231:
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L232
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L232
.L230:
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L229
.L232:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
.L234:
	mov	r3, #1
	b	.L236
.L235:
	mov	r3, #0
.L236:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
	mov	r3, #1
	b	.L229
.L237:
	mov	r3, #0
.L229:
	ldr	r2, .L257+24
	strb	r3, [r2]
	ldr	r3, .L257+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	b	.L240
.L239:
	ldr	r3, .L257+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L242
	ldr	r3, .L257+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L241
.L242:
	ldr	r3, .L257+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L243
.L241:
	mov	r3, #1
	b	.L244
.L243:
	mov	r3, #0
.L244:
	and	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L257+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	mov	r3, #1
	b	.L240
.L245:
	mov	r3, #0
.L240:
	ldr	r2, .L257+32
	strb	r3, [r2]
	bl	nondet_0
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r2, r3, #255
	ldr	r3, .L257+64
	strb	r2, [r3]
	ldr	r3, .L257+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L257+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L248
	ldr	r3, .L257+72
	ldr	r3, [r3]
	ldr	r3, [r3]
	b	.L250
.L248:
	ldr	r3, .L257+76
	ldr	r3, [r3]
	b	.L250
.L247:
	ldr	r3, .L257+76
	ldr	r3, [r3]
.L250:
	ldr	r2, .L257+76
	str	r3, [r2]
	ldr	r3, .L257+40
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L251
	ldr	r3, .L257+76
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L251
	ldr	r3, .L257+80
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L251
	ldr	r3, .L257+84
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L252
.L251:
	mov	r3, #1
	b	.L253
.L252:
	mov	r3, #0
.L253:
	and	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L257+88
	strb	r2, [r3]
	ldr	r3, .L257+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L257+60
	ldr	r3, [r3]
	b	.L255
.L254:
	ldr	r3, .L257+40
	ldr	r3, [r3]
.L255:
	ldr	r2, .L257+40
	str	r3, [r2]
	ldr	r3, .L257+56
	mov	r2, #0
	strb	r2, [r3]
	bl	__VERIFIER_atomic_end
	ldr	r3, .L257+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r0, r3
	bl	__VERIFIER_assert
	mov	r3, #0
	mov	r0, r3
	pop	{fp, pc}
.L258:
	.align	2
.L257:
	.word	P0
	.word	P1
	.word	P2
	.word	__unbuffered_cnt
	.word	main$tmp_guard0
	.word	y$w_buff0_used
	.word	y$r_buff0_thd0
	.word	y$w_buff1_used
	.word	y$r_buff1_thd0
	.word	y$w_buff1
	.word	y
	.word	y$w_buff0
	.word	weak$$choice0
	.word	weak$$choice2
	.word	y$flush_delayed
	.word	y$mem_tmp
	.word	weak$$choice1
	.word	__unbuffered_p0_EAX$read_delayed
	.word	__unbuffered_p0_EAX$read_delayed_var
	.word	__unbuffered_p0_EAX
	.word	__unbuffered_p1_EAX
	.word	__unbuffered_p2_EAX
	.word	main$tmp_guard1
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
