	.file	"1073310.c"
	.intel_syntax noprefix
	.text
	.globl	map
	.bss
	.align 32
	.type	map, @object
	.size	map, 11881
map:
	.zero	11881
	.globl	num
	.align 32
	.type	num, @object
	.size	num, 47524
num:
	.zero	47524
	.globl	n
	.align 4
	.type	n, @object
	.size	n, 4
n:
	.zero	4
	.globl	m
	.align 4
	.type	m, @object
	.size	m, 4
m:
	.zero	4
	.section	.rodata
.LC0:
	.string	"%d%d"
.LC1:
	.string	"%s"
	.text
	.globl	main
	.type	main, @function
main:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	lea	rdx, m[rip]
	lea	rsi, n[rip]
	lea	rdi, .LC0[rip]
	mov	eax, 0
	call	__isoc99_scanf@PLT
	mov	DWORD PTR -8[rbp], 0
	jmp	.L2
.L3:
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rcx, 0[0+rax*8]
	add	rax, rcx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, map[rip]
	add	rax, rdx
	mov	rsi, rax
	lea	rdi, .LC1[rip]
	mov	eax, 0
	call	__isoc99_scanf@PLT
	add	DWORD PTR -8[rbp], 1
.L2:
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jl	.L3
	mov	DWORD PTR -8[rbp], 0
	jmp	.L4
.L25:
	mov	DWORD PTR -4[rbp], 0
	jmp	.L5
.L24:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], 0
	jle	.L6
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jg	.L6
	cmp	DWORD PTR -4[rbp], 0
	jle	.L6
	mov	eax, DWORD PTR m[rip]
	cmp	DWORD PTR -4[rbp], eax
	jg	.L6
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, -1[rax]
	mov	eax, DWORD PTR -4[rbp]
	sub	eax, 1
	movsx	rsi, eax
	movsx	rdx, edx
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L6
	mov	eax, 1
	jmp	.L7
.L6:
	mov	eax, 0
.L7:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], 0
	jle	.L8
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jg	.L8
	cmp	DWORD PTR -4[rbp], 0
	js	.L8
	mov	eax, DWORD PTR m[rip]
	cmp	DWORD PTR -4[rbp], eax
	jge	.L8
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, -1[rax]
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	movsx	rdx, edx
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L8
	mov	eax, 1
	jmp	.L9
.L8:
	mov	eax, 0
.L9:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], 0
	jle	.L10
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jg	.L10
	cmp	DWORD PTR -4[rbp], -1
	jl	.L10
	mov	eax, DWORD PTR -4[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR m[rip]
	cmp	edx, eax
	jge	.L10
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, -1[rax]
	mov	eax, DWORD PTR -4[rbp]
	add	eax, 1
	movsx	rsi, eax
	movsx	rdx, edx
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L10
	mov	eax, 1
	jmp	.L11
.L10:
	mov	eax, 0
.L11:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], 0
	js	.L12
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jge	.L12
	cmp	DWORD PTR -4[rbp], 0
	jle	.L12
	mov	eax, DWORD PTR m[rip]
	cmp	DWORD PTR -4[rbp], eax
	jg	.L12
	mov	eax, DWORD PTR -4[rbp]
	sub	eax, 1
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L12
	mov	eax, 1
	jmp	.L13
.L12:
	mov	eax, 0
.L13:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], 0
	js	.L14
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jge	.L14
	cmp	DWORD PTR -4[rbp], 0
	js	.L14
	mov	eax, DWORD PTR m[rip]
	cmp	DWORD PTR -4[rbp], eax
	jge	.L14
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L14
	mov	eax, 1
	jmp	.L15
.L14:
	mov	eax, 0
.L15:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], 0
	js	.L16
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jge	.L16
	cmp	DWORD PTR -4[rbp], -1
	jl	.L16
	mov	eax, DWORD PTR -4[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR m[rip]
	cmp	edx, eax
	jge	.L16
	mov	eax, DWORD PTR -4[rbp]
	add	eax, 1
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L16
	mov	eax, 1
	jmp	.L17
.L16:
	mov	eax, 0
.L17:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], -1
	jl	.L18
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR n[rip]
	cmp	edx, eax
	jge	.L18
	cmp	DWORD PTR -4[rbp], 0
	jle	.L18
	mov	eax, DWORD PTR m[rip]
	cmp	DWORD PTR -4[rbp], eax
	jg	.L18
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR -4[rbp]
	sub	eax, 1
	movsx	rsi, eax
	movsx	rdx, edx
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L18
	mov	eax, 1
	jmp	.L19
.L18:
	mov	eax, 0
.L19:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], -1
	jl	.L20
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR n[rip]
	cmp	edx, eax
	jge	.L20
	cmp	DWORD PTR -4[rbp], 0
	js	.L20
	mov	eax, DWORD PTR m[rip]
	cmp	DWORD PTR -4[rbp], eax
	jge	.L20
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	movsx	rdx, edx
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L20
	mov	eax, 1
	jmp	.L21
.L20:
	mov	eax, 0
.L21:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	ecx, DWORD PTR [rdx+rax]
	cmp	DWORD PTR -8[rbp], -1
	jl	.L22
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR n[rip]
	cmp	edx, eax
	jge	.L22
	cmp	DWORD PTR -4[rbp], -1
	jl	.L22
	mov	eax, DWORD PTR -4[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR m[rip]
	cmp	edx, eax
	jge	.L22
	mov	eax, DWORD PTR -8[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR -4[rbp]
	add	eax, 1
	movsx	rsi, eax
	movsx	rdx, edx
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rsi]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	jne	.L22
	mov	eax, 1
	jmp	.L23
.L22:
	mov	eax, 0
.L23:
	add	ecx, eax
	mov	eax, DWORD PTR -4[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rdi, 0[0+rax*8]
	add	rax, rdi
	sal	rax, 2
	add	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	DWORD PTR [rdx+rax], ecx
	add	DWORD PTR -4[rbp], 1
.L5:
	mov	eax, DWORD PTR m[rip]
	cmp	DWORD PTR -4[rbp], eax
	jl	.L24
	add	DWORD PTR -8[rbp], 1
.L4:
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jl	.L25
	mov	DWORD PTR -8[rbp], 0
	jmp	.L26
.L31:
	mov	DWORD PTR -4[rbp], 0
	jmp	.L27
.L30:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	lea	rdx, [rax+rcx]
	lea	rax, map[rip]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 42
	je	.L28
	mov	eax, DWORD PTR -4[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -8[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	lea	rsi, 0[0+rax*8]
	add	rax, rsi
	sal	rax, 2
	add	rax, rdx
	add	rax, rcx
	lea	rdx, 0[0+rax*4]
	lea	rax, num[rip]
	mov	eax, DWORD PTR [rdx+rax]
	add	eax, 48
	jmp	.L29
.L28:
	mov	eax, 42
.L29:
	mov	edi, eax
	call	putchar@PLT
	add	DWORD PTR -4[rbp], 1
.L27:
	mov	eax, DWORD PTR m[rip]
	cmp	DWORD PTR -4[rbp], eax
	jl	.L30
	mov	edi, 10
	call	putchar@PLT
	add	DWORD PTR -8[rbp], 1
.L26:
	mov	eax, DWORD PTR n[rip]
	cmp	DWORD PTR -8[rbp], eax
	jl	.L31
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"1073310.c"
	.text
	.comm	map,11881,4
	.comm	num,47524,4
	.comm	n,4,4
	.comm	m,4,4
	.section	.rodata
	.align	2
.LC0:
	.ascii	"%d%d\000"
	.align	2
.LC1:
	.ascii	"%s\000"
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	ldr	r2, .L33
	ldr	r1, .L33+4
	ldr	r0, .L33+8
	bl	__isoc99_scanf
	mov	r3, #0
	str	r3, [fp, #-12]
	b	.L2
.L3:
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, .L33+12
	add	r3, r3, r2
	mov	r1, r3
	ldr	r0, .L33+16
	bl	__isoc99_scanf
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
.L2:
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	blt	.L3
	mov	r3, #0
	str	r3, [fp, #-12]
	b	.L4
.L25:
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L5
.L24:
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	ble	.L6
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bgt	.L6
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	ble	.L6
	ldr	r3, .L33
	ldr	r3, [r3]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	bgt	.L6
	ldr	r3, [fp, #-12]
	sub	r2, r3, #1
	ldr	r3, [fp, #-8]
	sub	r0, r3, #1
	ldr	lr, .L33+12
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	ip, r3, #3
	add	r3, r3, ip
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r3, lr, r3
	add	r3, r3, r0
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L6
	mov	r3, #1
	b	.L7
.L6:
	mov	r3, #0
.L7:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	ble	.L8
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bgt	.L8
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	blt	.L8
	ldr	r3, .L33
	ldr	r3, [r3]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	bge	.L8
	ldr	r3, [fp, #-12]
	sub	r2, r3, #1
	ldr	ip, .L33+12
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r2, ip, r3
	ldr	r3, [fp, #-8]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L8
	mov	r3, #1
	b	.L9
.L8:
	mov	r3, #0
.L9:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	ble	.L10
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bgt	.L10
	ldr	r3, [fp, #-8]
	cmn	r3, #1
	blt	.L10
	ldr	r3, [fp, #-8]
	add	r2, r3, #1
	ldr	r3, .L33
	ldr	r3, [r3]
	cmp	r2, r3
	bge	.L10
	ldr	r3, [fp, #-12]
	sub	r2, r3, #1
	ldr	r3, [fp, #-8]
	add	r0, r3, #1
	ldr	lr, .L33+12
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	ip, r3, #3
	add	r3, r3, ip
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r3, lr, r3
	add	r3, r3, r0
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L10
	mov	r3, #1
	b	.L11
.L10:
	mov	r3, #0
.L11:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	blt	.L12
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bge	.L12
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	ble	.L12
	ldr	r3, .L33
	ldr	r3, [r3]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	bgt	.L12
	ldr	r3, [fp, #-8]
	sub	r0, r3, #1
	ldr	lr, .L33+12
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	ip, r3, #3
	add	r3, r3, ip
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r3, lr, r3
	add	r3, r3, r0
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L12
	mov	r3, #1
	b	.L13
.L12:
	mov	r3, #0
.L13:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	blt	.L14
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bge	.L14
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	blt	.L14
	ldr	r3, .L33
	ldr	r3, [r3]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	bge	.L14
	ldr	ip, .L33+12
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r2, ip, r3
	ldr	r3, [fp, #-8]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L14
	mov	r3, #1
	b	.L15
.L14:
	mov	r3, #0
.L15:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	blt	.L16
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bge	.L16
	ldr	r3, [fp, #-8]
	cmn	r3, #1
	blt	.L16
	ldr	r3, [fp, #-8]
	add	r2, r3, #1
	ldr	r3, .L33
	ldr	r3, [r3]
	cmp	r2, r3
	bge	.L16
	ldr	r3, [fp, #-8]
	add	r0, r3, #1
	ldr	lr, .L33+12
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	ip, r3, #3
	add	r3, r3, ip
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r3, lr, r3
	add	r3, r3, r0
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L16
	mov	r3, #1
	b	.L17
.L16:
	mov	r3, #0
.L17:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmn	r3, #1
	blt	.L18
	ldr	r3, [fp, #-12]
	add	r2, r3, #1
	ldr	r3, .L33+4
	ldr	r3, [r3]
	cmp	r2, r3
	bge	.L18
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	ble	.L18
	ldr	r3, .L33
	ldr	r3, [r3]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	bgt	.L18
	ldr	r3, [fp, #-12]
	add	r2, r3, #1
	ldr	r3, [fp, #-8]
	sub	r0, r3, #1
	ldr	lr, .L33+12
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	ip, r3, #3
	add	r3, r3, ip
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r3, lr, r3
	add	r3, r3, r0
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L18
	mov	r3, #1
	b	.L19
.L18:
	mov	r3, #0
.L19:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmn	r3, #1
	blt	.L20
	ldr	r3, [fp, #-12]
	add	r2, r3, #1
	ldr	r3, .L33+4
	ldr	r3, [r3]
	cmp	r2, r3
	bge	.L20
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	blt	.L20
	ldr	r3, .L33
	ldr	r3, [r3]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	bge	.L20
	ldr	r3, [fp, #-12]
	add	r2, r3, #1
	ldr	ip, .L33+12
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r2, ip, r3
	ldr	r3, [fp, #-8]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L20
	mov	r3, #1
	b	.L21
.L20:
	mov	r3, #0
.L21:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r1, [r0, r3, lsl #2]
	ldr	r3, [fp, #-12]
	cmn	r3, #1
	blt	.L22
	ldr	r3, [fp, #-12]
	add	r2, r3, #1
	ldr	r3, .L33+4
	ldr	r3, [r3]
	cmp	r2, r3
	bge	.L22
	ldr	r3, [fp, #-8]
	cmn	r3, #1
	blt	.L22
	ldr	r3, [fp, #-8]
	add	r2, r3, #1
	ldr	r3, .L33
	ldr	r3, [r3]
	cmp	r2, r3
	bge	.L22
	ldr	r3, [fp, #-12]
	add	r2, r3, #1
	ldr	r3, [fp, #-8]
	add	r0, r3, #1
	ldr	lr, .L33+12
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	ip, r3, #3
	add	r3, r3, ip
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r3, lr, r3
	add	r3, r3, r0
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	bne	.L22
	mov	r3, #1
	b	.L23
.L22:
	mov	r3, #0
.L23:
	add	r1, r3, r1
	ldr	ip, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r0, r3, #3
	add	r3, r3, r0
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	str	r1, [ip, r3, lsl #2]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L5:
	ldr	r3, .L33
	ldr	r3, [r3]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	blt	.L24
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
.L4:
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	blt	.L25
	mov	r3, #0
	str	r3, [fp, #-12]
	b	.L26
.L31:
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L27
.L30:
	ldr	r0, .L33+12
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	add	r2, r0, r3
	ldr	r3, [fp, #-8]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #42
	beq	.L28
	ldr	r0, .L33+20
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r1, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r2
	ldr	r2, [fp, #-8]
	add	r3, r3, r2
	ldr	r3, [r0, r3, lsl #2]
	add	r3, r3, #48
	b	.L29
.L28:
	mov	r3, #42
.L29:
	mov	r0, r3
	bl	putchar
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L27:
	ldr	r3, .L33
	ldr	r3, [r3]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	blt	.L30
	mov	r0, #10
	bl	putchar
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
.L26:
	ldr	r3, .L33+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	blt	.L31
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L34:
	.align	2
.L33:
	.word	m
	.word	n
	.word	.LC0
	.word	map
	.word	.LC1
	.word	num
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
