	.file	"154828402.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	s13_z
	.bss
	.align 4
	.type	s13_z, @object
	.size	s13_z, 4
s13_z:
	.zero	4
	.globl	_x_s13_z
	.align 4
	.type	_x_s13_z, @object
	.size	_x_s13_z, 4
_x_s13_z:
	.zero	4
	.globl	s13_y
	.align 4
	.type	s13_y, @object
	.size	s13_y, 4
s13_y:
	.zero	4
	.globl	_x_s13_y
	.align 4
	.type	_x_s13_y, @object
	.size	_x_s13_y, 4
_x_s13_y:
	.zero	4
	.globl	s13_x
	.align 4
	.type	s13_x, @object
	.size	s13_x, 4
s13_x:
	.zero	4
	.globl	_x_s13_x
	.align 4
	.type	_x_s13_x, @object
	.size	_x_s13_x, 4
_x_s13_x:
	.zero	4
	.globl	s12_z
	.align 4
	.type	s12_z, @object
	.size	s12_z, 4
s12_z:
	.zero	4
	.globl	_x_s12_z
	.align 4
	.type	_x_s12_z, @object
	.size	_x_s12_z, 4
_x_s12_z:
	.zero	4
	.globl	s12_y
	.align 4
	.type	s12_y, @object
	.size	s12_y, 4
s12_y:
	.zero	4
	.globl	_x_s12_y
	.align 4
	.type	_x_s12_y, @object
	.size	_x_s12_y, 4
_x_s12_y:
	.zero	4
	.globl	s12_x
	.align 4
	.type	s12_x, @object
	.size	s12_x, 4
s12_x:
	.zero	4
	.globl	_x_s12_x
	.align 4
	.type	_x_s12_x, @object
	.size	_x_s12_x, 4
_x_s12_x:
	.zero	4
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	s11_z
	.align 4
	.type	s11_z, @object
	.size	s11_z, 4
s11_z:
	.zero	4
	.globl	_x_s11_z
	.align 4
	.type	_x_s11_z, @object
	.size	_x_s11_z, 4
_x_s11_z:
	.zero	4
	.globl	s11_y
	.align 4
	.type	s11_y, @object
	.size	s11_y, 4
s11_y:
	.zero	4
	.globl	_x_s11_y
	.align 4
	.type	_x_s11_y, @object
	.size	_x_s11_y, 4
_x_s11_y:
	.zero	4
	.globl	s11_x
	.align 4
	.type	s11_x, @object
	.size	s11_x, 4
s11_x:
	.zero	4
	.globl	_x_s11_x
	.align 4
	.type	_x_s11_x, @object
	.size	_x_s11_x, 4
_x_s11_x:
	.zero	4
	.globl	s10_z
	.align 4
	.type	s10_z, @object
	.size	s10_z, 4
s10_z:
	.zero	4
	.globl	_x_s10_z
	.align 4
	.type	_x_s10_z, @object
	.size	_x_s10_z, 4
_x_s10_z:
	.zero	4
	.globl	s10_y
	.align 4
	.type	s10_y, @object
	.size	s10_y, 4
s10_y:
	.zero	4
	.globl	_x_s10_y
	.align 4
	.type	_x_s10_y, @object
	.size	_x_s10_y, 4
_x_s10_y:
	.zero	4
	.globl	s10_x
	.align 4
	.type	s10_x, @object
	.size	s10_x, 4
s10_x:
	.zero	4
	.globl	_x_s10_x
	.align 4
	.type	_x_s10_x, @object
	.size	_x_s10_x, 4
_x_s10_x:
	.zero	4
	.globl	s9_z
	.align 4
	.type	s9_z, @object
	.size	s9_z, 4
s9_z:
	.zero	4
	.globl	_x_s9_z
	.align 4
	.type	_x_s9_z, @object
	.size	_x_s9_z, 4
_x_s9_z:
	.zero	4
	.globl	s9_y
	.align 4
	.type	s9_y, @object
	.size	s9_y, 4
s9_y:
	.zero	4
	.globl	_x_s9_y
	.align 4
	.type	_x_s9_y, @object
	.size	_x_s9_y, 4
_x_s9_y:
	.zero	4
	.globl	s9_x
	.align 4
	.type	s9_x, @object
	.size	s9_x, 4
s9_x:
	.zero	4
	.globl	_x_s9_x
	.align 4
	.type	_x_s9_x, @object
	.size	_x_s9_x, 4
_x_s9_x:
	.zero	4
	.globl	s8_z
	.align 4
	.type	s8_z, @object
	.size	s8_z, 4
s8_z:
	.zero	4
	.globl	_x_s8_z
	.align 4
	.type	_x_s8_z, @object
	.size	_x_s8_z, 4
_x_s8_z:
	.zero	4
	.globl	s8_y
	.align 4
	.type	s8_y, @object
	.size	s8_y, 4
s8_y:
	.zero	4
	.globl	_x_s8_y
	.align 4
	.type	_x_s8_y, @object
	.size	_x_s8_y, 4
_x_s8_y:
	.zero	4
	.globl	s8_x
	.align 4
	.type	s8_x, @object
	.size	s8_x, 4
s8_x:
	.zero	4
	.globl	_x_s8_x
	.align 4
	.type	_x_s8_x, @object
	.size	_x_s8_x, 4
_x_s8_x:
	.zero	4
	.globl	s13_l2
	.type	s13_l2, @object
	.size	s13_l2, 1
s13_l2:
	.zero	1
	.globl	_x_s13_l2
	.type	_x_s13_l2, @object
	.size	_x_s13_l2, 1
_x_s13_l2:
	.zero	1
	.globl	s7_z
	.align 4
	.type	s7_z, @object
	.size	s7_z, 4
s7_z:
	.zero	4
	.globl	_x_s7_z
	.align 4
	.type	_x_s7_z, @object
	.size	_x_s7_z, 4
_x_s7_z:
	.zero	4
	.globl	s13_l1
	.type	s13_l1, @object
	.size	s13_l1, 1
s13_l1:
	.zero	1
	.globl	_x_s13_l1
	.type	_x_s13_l1, @object
	.size	_x_s13_l1, 1
_x_s13_l1:
	.zero	1
	.globl	s7_y
	.align 4
	.type	s7_y, @object
	.size	s7_y, 4
s7_y:
	.zero	4
	.globl	_x_s7_y
	.align 4
	.type	_x_s7_y, @object
	.size	_x_s7_y, 4
_x_s7_y:
	.zero	4
	.globl	s13_l0
	.type	s13_l0, @object
	.size	s13_l0, 1
s13_l0:
	.zero	1
	.globl	_x_s13_l0
	.type	_x_s13_l0, @object
	.size	_x_s13_l0, 1
_x_s13_l0:
	.zero	1
	.globl	s7_x
	.align 4
	.type	s7_x, @object
	.size	s7_x, 4
s7_x:
	.zero	4
	.globl	_x_s7_x
	.align 4
	.type	_x_s7_x, @object
	.size	_x_s7_x, 4
_x_s7_x:
	.zero	4
	.globl	r_event1
	.type	r_event1, @object
	.size	r_event1, 1
r_event1:
	.zero	1
	.globl	_x_r_event1
	.type	_x_r_event1, @object
	.size	_x_r_event1, 1
_x_r_event1:
	.zero	1
	.globl	s8_l2
	.type	s8_l2, @object
	.size	s8_l2, 1
s8_l2:
	.zero	1
	.globl	_x_s8_l2
	.type	_x_s8_l2, @object
	.size	_x_s8_l2, 1
_x_s8_l2:
	.zero	1
	.globl	s2_z
	.align 4
	.type	s2_z, @object
	.size	s2_z, 4
s2_z:
	.zero	4
	.globl	_x_s2_z
	.align 4
	.type	_x_s2_z, @object
	.size	_x_s2_z, 4
_x_s2_z:
	.zero	4
	.globl	s11_l1
	.type	s11_l1, @object
	.size	s11_l1, 1
s11_l1:
	.zero	1
	.globl	_x_s11_l1
	.type	_x_s11_l1, @object
	.size	_x_s11_l1, 1
_x_s11_l1:
	.zero	1
	.globl	s5_y
	.align 4
	.type	s5_y, @object
	.size	s5_y, 4
s5_y:
	.zero	4
	.globl	_x_s5_y
	.align 4
	.type	_x_s5_y, @object
	.size	_x_s5_y, 4
_x_s5_y:
	.zero	4
	.globl	s1_l2
	.type	s1_l2, @object
	.size	s1_l2, 1
s1_l2:
	.zero	1
	.globl	_x_s1_l2
	.type	_x_s1_l2, @object
	.size	_x_s1_l2, 1
_x_s1_l2:
	.zero	1
	.globl	s7_evt1
	.type	s7_evt1, @object
	.size	s7_evt1, 1
s7_evt1:
	.zero	1
	.globl	_x_s7_evt1
	.type	_x_s7_evt1, @object
	.size	_x_s7_evt1, 1
_x_s7_evt1:
	.zero	1
	.globl	s4_l1
	.type	s4_l1, @object
	.size	s4_l1, 1
s4_l1:
	.zero	1
	.globl	_x_s4_l1
	.type	_x_s4_l1, @object
	.size	_x_s4_l1, 1
_x_s4_l1:
	.zero	1
	.globl	s7_evt0
	.type	s7_evt0, @object
	.size	s7_evt0, 1
s7_evt0:
	.zero	1
	.globl	_x_s7_evt0
	.type	_x_s7_evt0, @object
	.size	_x_s7_evt0, 1
_x_s7_evt0:
	.zero	1
	.globl	s4_l0
	.type	s4_l0, @object
	.size	s4_l0, 1
s4_l0:
	.zero	1
	.globl	_x_s4_l0
	.type	_x_s4_l0, @object
	.size	_x_s4_l0, 1
_x_s4_l0:
	.zero	1
	.globl	s12_l2
	.type	s12_l2, @object
	.size	s12_l2, 1
s12_l2:
	.zero	1
	.globl	_x_s12_l2
	.type	_x_s12_l2, @object
	.size	_x_s12_l2, 1
_x_s12_l2:
	.zero	1
	.globl	s6_z
	.align 4
	.type	s6_z, @object
	.size	s6_z, 4
s6_z:
	.zero	4
	.globl	_x_s6_z
	.align 4
	.type	_x_s6_z, @object
	.size	_x_s6_z, 4
_x_s6_z:
	.zero	4
	.globl	s1_evt0
	.type	s1_evt0, @object
	.size	s1_evt0, 1
s1_evt0:
	.zero	1
	.globl	_x_s1_evt0
	.type	_x_s1_evt0, @object
	.size	_x_s1_evt0, 1
_x_s1_evt0:
	.zero	1
	.globl	s7_l2
	.type	s7_l2, @object
	.size	s7_l2, 1
s7_l2:
	.zero	1
	.globl	_x_s7_l2
	.type	_x_s7_l2, @object
	.size	_x_s7_l2, 1
_x_s7_l2:
	.zero	1
	.globl	s1_z
	.align 4
	.type	s1_z, @object
	.size	s1_z, 4
s1_z:
	.zero	4
	.globl	_x_s1_z
	.align 4
	.type	_x_s1_z, @object
	.size	_x_s1_z, 4
_x_s1_z:
	.zero	4
	.globl	r_l
	.type	r_l, @object
	.size	r_l, 1
r_l:
	.zero	1
	.globl	_x_r_l
	.type	_x_r_l, @object
	.size	_x_r_l, 1
_x_r_l:
	.zero	1
	.globl	s13_evt1
	.type	s13_evt1, @object
	.size	s13_evt1, 1
s13_evt1:
	.zero	1
	.globl	_x_s13_evt1
	.type	_x_s13_evt1, @object
	.size	_x_s13_evt1, 1
_x_s13_evt1:
	.zero	1
	.globl	s10_l1
	.type	s10_l1, @object
	.size	s10_l1, 1
s10_l1:
	.zero	1
	.globl	_x_s10_l1
	.type	_x_s10_l1, @object
	.size	_x_s10_l1, 1
_x_s10_l1:
	.zero	1
	.globl	s4_y
	.align 4
	.type	s4_y, @object
	.size	s4_y, 4
s4_y:
	.zero	4
	.globl	_x_s4_y
	.align 4
	.type	_x_s4_y, @object
	.size	_x_s4_y, 4
_x_s4_y:
	.zero	4
	.globl	s11_evt1
	.type	s11_evt1, @object
	.size	s11_evt1, 1
s11_evt1:
	.zero	1
	.globl	_x_s11_evt1
	.type	_x_s11_evt1, @object
	.size	_x_s11_evt1, 1
_x_s11_evt1:
	.zero	1
	.globl	s8_l1
	.type	s8_l1, @object
	.size	s8_l1, 1
s8_l1:
	.zero	1
	.globl	_x_s8_l1
	.type	_x_s8_l1, @object
	.size	_x_s8_l1, 1
_x_s8_l1:
	.zero	1
	.globl	s2_y
	.align 4
	.type	s2_y, @object
	.size	s2_y, 4
s2_y:
	.zero	4
	.globl	_x_s2_y
	.align 4
	.type	_x_s2_y, @object
	.size	_x_s2_y, 4
_x_s2_y:
	.zero	4
	.globl	s11_l0
	.type	s11_l0, @object
	.size	s11_l0, 1
s11_l0:
	.zero	1
	.globl	_x_s11_l0
	.type	_x_s11_l0, @object
	.size	_x_s11_l0, 1
_x_s11_l0:
	.zero	1
	.globl	s5_x
	.align 4
	.type	s5_x, @object
	.size	s5_x, 4
s5_x:
	.zero	4
	.globl	_x_s5_x
	.align 4
	.type	_x_s5_x, @object
	.size	_x_s5_x, 4
_x_s5_x:
	.zero	4
	.globl	s0_l2
	.type	s0_l2, @object
	.size	s0_l2, 1
s0_l2:
	.zero	1
	.globl	_x_s0_l2
	.type	_x_s0_l2, @object
	.size	_x_s0_l2, 1
_x_s0_l2:
	.zero	1
	.globl	s6_evt1
	.type	s6_evt1, @object
	.size	s6_evt1, 1
s6_evt1:
	.zero	1
	.globl	_x_s6_evt1
	.type	_x_s6_evt1, @object
	.size	_x_s6_evt1, 1
_x_s6_evt1:
	.zero	1
	.globl	s3_l1
	.type	s3_l1, @object
	.size	s3_l1, 1
s3_l1:
	.zero	1
	.globl	_x_s3_l1
	.type	_x_s3_l1, @object
	.size	_x_s3_l1, 1
_x_s3_l1:
	.zero	1
	.globl	s11_evt0
	.type	s11_evt0, @object
	.size	s11_evt0, 1
s11_evt0:
	.zero	1
	.globl	_x_s11_evt0
	.type	_x_s11_evt0, @object
	.size	_x_s11_evt0, 1
_x_s11_evt0:
	.zero	1
	.globl	s8_l0
	.type	s8_l0, @object
	.size	s8_l0, 1
s8_l0:
	.zero	1
	.globl	_x_s8_l0
	.type	_x_s8_l0, @object
	.size	_x_s8_l0, 1
_x_s8_l0:
	.zero	1
	.globl	s2_x
	.align 4
	.type	s2_x, @object
	.size	s2_x, 4
s2_x:
	.zero	4
	.globl	_x_s2_x
	.align 4
	.type	_x_s2_x, @object
	.size	_x_s2_x, 4
_x_s2_x:
	.zero	4
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	s0_evt1
	.type	s0_evt1, @object
	.size	s0_evt1, 1
s0_evt1:
	.zero	1
	.globl	_x_s0_evt1
	.type	_x_s0_evt1, @object
	.size	_x_s0_evt1, 1
_x_s0_evt1:
	.zero	1
	.globl	s2_evt0
	.type	s2_evt0, @object
	.size	s2_evt0, 1
s2_evt0:
	.zero	1
	.globl	_x_s2_evt0
	.type	_x_s2_evt0, @object
	.size	_x_s2_evt0, 1
_x_s2_evt0:
	.zero	1
	.globl	r_evt_id
	.align 4
	.type	r_evt_id, @object
	.size	r_evt_id, 4
r_evt_id:
	.zero	4
	.globl	_x_r_evt_id
	.align 4
	.type	_x_r_evt_id, @object
	.size	_x_r_evt_id, 4
_x_r_evt_id:
	.zero	4
	.globl	s10_l2
	.type	s10_l2, @object
	.size	s10_l2, 1
s10_l2:
	.zero	1
	.globl	_x_s10_l2
	.type	_x_s10_l2, @object
	.size	_x_s10_l2, 1
_x_s10_l2:
	.zero	1
	.globl	s4_z
	.align 4
	.type	s4_z, @object
	.size	s4_z, 4
s4_z:
	.zero	4
	.globl	_x_s4_z
	.align 4
	.type	_x_s4_z, @object
	.size	_x_s4_z, 4
_x_s4_z:
	.zero	4
	.globl	s10_evt0
	.type	s10_evt0, @object
	.size	s10_evt0, 1
s10_evt0:
	.zero	1
	.globl	_x_s10_evt0
	.type	_x_s10_evt0, @object
	.size	_x_s10_evt0, 1
_x_s10_evt0:
	.zero	1
	.globl	s7_l0
	.type	s7_l0, @object
	.size	s7_l0, 1
s7_l0:
	.zero	1
	.globl	_x_s7_l0
	.type	_x_s7_l0, @object
	.size	_x_s7_l0, 1
_x_s7_l0:
	.zero	1
	.globl	s1_x
	.align 4
	.type	s1_x, @object
	.size	s1_x, 4
s1_x:
	.zero	4
	.globl	_x_s1_x
	.align 4
	.type	_x_s1_x, @object
	.size	_x_s1_x, 4
_x_s1_x:
	.zero	4
	.globl	s2_evt1
	.type	s2_evt1, @object
	.size	s2_evt1, 1
s2_evt1:
	.zero	1
	.globl	_x_s2_evt1
	.type	_x_s2_evt1, @object
	.size	_x_s2_evt1, 1
_x_s2_evt1:
	.zero	1
	.globl	r_counter
	.align 4
	.type	r_counter, @object
	.size	r_counter, 4
r_counter:
	.zero	4
	.globl	_x_r_counter
	.align 4
	.type	_x_r_counter, @object
	.size	_x_r_counter, 4
_x_r_counter:
	.zero	4
	.globl	s5_evt0
	.type	s5_evt0, @object
	.size	s5_evt0, 1
s5_evt0:
	.zero	1
	.globl	_x_s5_evt0
	.type	_x_s5_evt0, @object
	.size	_x_s5_evt0, 1
_x_s5_evt0:
	.zero	1
	.globl	s2_l0
	.type	s2_l0, @object
	.size	s2_l0, 1
s2_l0:
	.zero	1
	.globl	_x_s2_l0
	.type	_x_s2_l0, @object
	.size	_x_s2_l0, 1
_x_s2_l0:
	.zero	1
	.globl	s9_evt0
	.type	s9_evt0, @object
	.size	s9_evt0, 1
s9_evt0:
	.zero	1
	.globl	_x_s9_evt0
	.type	_x_s9_evt0, @object
	.size	_x_s9_evt0, 1
_x_s9_evt0:
	.zero	1
	.globl	s6_l0
	.type	s6_l0, @object
	.size	s6_l0, 1
s6_l0:
	.zero	1
	.globl	_x_s6_l0
	.type	_x_s6_l0, @object
	.size	_x_s6_l0, 1
_x_s6_l0:
	.zero	1
	.globl	s0_x
	.align 4
	.type	s0_x, @object
	.size	s0_x, 4
s0_x:
	.zero	4
	.globl	_x_s0_x
	.align 4
	.type	_x_s0_x, @object
	.size	_x_s0_x, 4
_x_s0_x:
	.zero	4
	.globl	s10_evt1
	.type	s10_evt1, @object
	.size	s10_evt1, 1
s10_evt1:
	.zero	1
	.globl	_x_s10_evt1
	.type	_x_s10_evt1, @object
	.size	_x_s10_evt1, 1
_x_s10_evt1:
	.zero	1
	.globl	s7_l1
	.type	s7_l1, @object
	.size	s7_l1, 1
s7_l1:
	.zero	1
	.globl	_x_s7_l1
	.type	_x_s7_l1, @object
	.size	_x_s7_l1, 1
_x_s7_l1:
	.zero	1
	.globl	s1_y
	.align 4
	.type	s1_y, @object
	.size	s1_y, 4
s1_y:
	.zero	4
	.globl	_x_s1_y
	.align 4
	.type	_x_s1_y, @object
	.size	_x_s1_y, 4
_x_s1_y:
	.zero	4
	.globl	s13_evt0
	.type	s13_evt0, @object
	.size	s13_evt0, 1
s13_evt0:
	.zero	1
	.globl	_x_s13_evt0
	.type	_x_s13_evt0, @object
	.size	_x_s13_evt0, 1
_x_s13_evt0:
	.zero	1
	.globl	s10_l0
	.type	s10_l0, @object
	.size	s10_l0, 1
s10_l0:
	.zero	1
	.globl	_x_s10_l0
	.type	_x_s10_l0, @object
	.size	_x_s10_l0, 1
_x_s10_l0:
	.zero	1
	.globl	s4_x
	.align 4
	.type	s4_x, @object
	.size	s4_x, 4
s4_x:
	.zero	4
	.globl	_x_s4_x
	.align 4
	.type	_x_s4_x, @object
	.size	_x_s4_x, 4
_x_s4_x:
	.zero	4
	.globl	r_x
	.align 4
	.type	r_x, @object
	.size	r_x, 4
r_x:
	.zero	4
	.globl	_x_r_x
	.align 4
	.type	_x_r_x, @object
	.size	_x_r_x, 4
_x_r_x:
	.zero	4
	.globl	s8_evt0
	.type	s8_evt0, @object
	.size	s8_evt0, 1
s8_evt0:
	.zero	1
	.globl	_x_s8_evt0
	.type	_x_s8_evt0, @object
	.size	_x_s8_evt0, 1
_x_s8_evt0:
	.zero	1
	.globl	s5_l0
	.type	s5_l0, @object
	.size	s5_l0, 1
s5_l0:
	.zero	1
	.globl	_x_s5_l0
	.type	_x_s5_l0, @object
	.size	_x_s5_l0, 1
_x_s5_l0:
	.zero	1
	.globl	s9_evt1
	.type	s9_evt1, @object
	.size	s9_evt1, 1
s9_evt1:
	.zero	1
	.globl	_x_s9_evt1
	.type	_x_s9_evt1, @object
	.size	_x_s9_evt1, 1
_x_s9_evt1:
	.zero	1
	.globl	s6_l1
	.type	s6_l1, @object
	.size	s6_l1, 1
s6_l1:
	.zero	1
	.globl	_x_s6_l1
	.type	_x_s6_l1, @object
	.size	_x_s6_l1, 1
_x_s6_l1:
	.zero	1
	.globl	s0_y
	.align 4
	.type	s0_y, @object
	.size	s0_y, 4
s0_y:
	.zero	4
	.globl	_x_s0_y
	.align 4
	.type	_x_s0_y, @object
	.size	_x_s0_y, 4
_x_s0_y:
	.zero	4
	.globl	s12_evt0
	.type	s12_evt0, @object
	.size	s12_evt0, 1
s12_evt0:
	.zero	1
	.globl	_x_s12_evt0
	.type	_x_s12_evt0, @object
	.size	_x_s12_evt0, 1
_x_s12_evt0:
	.zero	1
	.globl	s9_l0
	.type	s9_l0, @object
	.size	s9_l0, 1
s9_l0:
	.zero	1
	.globl	_x_s9_l0
	.type	_x_s9_l0, @object
	.size	_x_s9_l0, 1
_x_s9_l0:
	.zero	1
	.globl	s3_x
	.align 4
	.type	s3_x, @object
	.size	s3_x, 4
s3_x:
	.zero	4
	.globl	_x_s3_x
	.align 4
	.type	_x_s3_x, @object
	.size	_x_s3_x, 4
_x_s3_x:
	.zero	4
	.globl	r_event0
	.type	r_event0, @object
	.size	r_event0, 1
r_event0:
	.zero	1
	.globl	_x_r_event0
	.type	_x_r_event0, @object
	.size	_x_r_event0, 1
_x_r_event0:
	.zero	1
	.globl	s6_l2
	.type	s6_l2, @object
	.size	s6_l2, 1
s6_l2:
	.zero	1
	.globl	_x_s6_l2
	.type	_x_s6_l2, @object
	.size	_x_s6_l2, 1
_x_s6_l2:
	.zero	1
	.globl	s0_z
	.align 4
	.type	s0_z, @object
	.size	s0_z, 4
s0_z:
	.zero	4
	.globl	_x_s0_z
	.align 4
	.type	_x_s0_z, @object
	.size	_x_s0_z, 4
_x_s0_z:
	.zero	4
	.globl	s12_evt1
	.type	s12_evt1, @object
	.size	s12_evt1, 1
s12_evt1:
	.zero	1
	.globl	_x_s12_evt1
	.type	_x_s12_evt1, @object
	.size	_x_s12_evt1, 1
_x_s12_evt1:
	.zero	1
	.globl	s9_l1
	.type	s9_l1, @object
	.size	s9_l1, 1
s9_l1:
	.zero	1
	.globl	_x_s9_l1
	.type	_x_s9_l1, @object
	.size	_x_s9_l1, 1
_x_s9_l1:
	.zero	1
	.globl	s3_y
	.align 4
	.type	s3_y, @object
	.size	s3_y, 4
s3_y:
	.zero	4
	.globl	_x_s3_y
	.align 4
	.type	_x_s3_y, @object
	.size	_x_s3_y, 4
_x_s3_y:
	.zero	4
	.globl	s12_l0
	.type	s12_l0, @object
	.size	s12_l0, 1
s12_l0:
	.zero	1
	.globl	_x_s12_l0
	.type	_x_s12_l0, @object
	.size	_x_s12_l0, 1
_x_s12_l0:
	.zero	1
	.globl	s6_x
	.align 4
	.type	s6_x, @object
	.size	s6_x, 4
s6_x:
	.zero	4
	.globl	_x_s6_x
	.align 4
	.type	_x_s6_x, @object
	.size	_x_s6_x, 4
_x_s6_x:
	.zero	4
	.globl	s0_evt0
	.type	s0_evt0, @object
	.size	s0_evt0, 1
s0_evt0:
	.zero	1
	.globl	_x_s0_evt0
	.type	_x_s0_evt0, @object
	.size	_x_s0_evt0, 1
_x_s0_evt0:
	.zero	1
	.globl	s1_evt1
	.type	s1_evt1, @object
	.size	s1_evt1, 1
s1_evt1:
	.zero	1
	.globl	_x_s1_evt1
	.type	_x_s1_evt1, @object
	.size	_x_s1_evt1, 1
_x_s1_evt1:
	.zero	1
	.globl	s1_l0
	.type	s1_l0, @object
	.size	s1_l0, 1
s1_l0:
	.zero	1
	.globl	_x_s1_l0
	.type	_x_s1_l0, @object
	.size	_x_s1_l0, 1
_x_s1_l0:
	.zero	1
	.globl	s4_evt0
	.type	s4_evt0, @object
	.size	s4_evt0, 1
s4_evt0:
	.zero	1
	.globl	_x_s4_evt0
	.type	_x_s4_evt0, @object
	.size	_x_s4_evt0, 1
_x_s4_evt0:
	.zero	1
	.globl	s3_evt0
	.type	s3_evt0, @object
	.size	s3_evt0, 1
s3_evt0:
	.zero	1
	.globl	_x_s3_evt0
	.type	_x_s3_evt0, @object
	.size	_x_s3_evt0, 1
_x_s3_evt0:
	.zero	1
	.globl	s0_l0
	.type	s0_l0, @object
	.size	s0_l0, 1
s0_l0:
	.zero	1
	.globl	_x_s0_l0
	.type	_x_s0_l0, @object
	.size	_x_s0_l0, 1
_x_s0_l0:
	.zero	1
	.globl	s11_l2
	.type	s11_l2, @object
	.size	s11_l2, 1
s11_l2:
	.zero	1
	.globl	_x_s11_l2
	.type	_x_s11_l2, @object
	.size	_x_s11_l2, 1
_x_s11_l2:
	.zero	1
	.globl	s5_z
	.align 4
	.type	s5_z, @object
	.size	s5_z, 4
s5_z:
	.zero	4
	.globl	_x_s5_z
	.align 4
	.type	_x_s5_z, @object
	.size	_x_s5_z, 4
_x_s5_z:
	.zero	4
	.globl	s2_l2
	.type	s2_l2, @object
	.size	s2_l2, 1
s2_l2:
	.zero	1
	.globl	_x_s2_l2
	.type	_x_s2_l2, @object
	.size	_x_s2_l2, 1
_x_s2_l2:
	.zero	1
	.globl	s8_evt1
	.type	s8_evt1, @object
	.size	s8_evt1, 1
s8_evt1:
	.zero	1
	.globl	_x_s8_evt1
	.type	_x_s8_evt1, @object
	.size	_x_s8_evt1, 1
_x_s8_evt1:
	.zero	1
	.globl	s5_l1
	.type	s5_l1, @object
	.size	s5_l1, 1
s5_l1:
	.zero	1
	.globl	_x_s5_l1
	.type	_x_s5_l1, @object
	.size	_x_s5_l1, 1
_x_s5_l1:
	.zero	1
	.globl	s9_l2
	.type	s9_l2, @object
	.size	s9_l2, 1
s9_l2:
	.zero	1
	.globl	_x_s9_l2
	.type	_x_s9_l2, @object
	.size	_x_s9_l2, 1
_x_s9_l2:
	.zero	1
	.globl	s3_z
	.align 4
	.type	s3_z, @object
	.size	s3_z, 4
s3_z:
	.zero	4
	.globl	_x_s3_z
	.align 4
	.type	_x_s3_z, @object
	.size	_x_s3_z, 4
_x_s3_z:
	.zero	4
	.globl	s12_l1
	.type	s12_l1, @object
	.size	s12_l1, 1
s12_l1:
	.zero	1
	.globl	_x_s12_l1
	.type	_x_s12_l1, @object
	.size	_x_s12_l1, 1
_x_s12_l1:
	.zero	1
	.globl	s6_y
	.align 4
	.type	s6_y, @object
	.size	s6_y, 4
s6_y:
	.zero	4
	.globl	_x_s6_y
	.align 4
	.type	_x_s6_y, @object
	.size	_x_s6_y, 4
_x_s6_y:
	.zero	4
	.globl	s0_l1
	.type	s0_l1, @object
	.size	s0_l1, 1
s0_l1:
	.zero	1
	.globl	_x_s0_l1
	.type	_x_s0_l1, @object
	.size	_x_s0_l1, 1
_x_s0_l1:
	.zero	1
	.globl	s3_evt1
	.type	s3_evt1, @object
	.size	s3_evt1, 1
s3_evt1:
	.zero	1
	.globl	_x_s3_evt1
	.type	_x_s3_evt1, @object
	.size	_x_s3_evt1, 1
_x_s3_evt1:
	.zero	1
	.globl	s3_l0
	.type	s3_l0, @object
	.size	s3_l0, 1
s3_l0:
	.zero	1
	.globl	_x_s3_l0
	.type	_x_s3_l0, @object
	.size	_x_s3_l0, 1
_x_s3_l0:
	.zero	1
	.globl	s6_evt0
	.type	s6_evt0, @object
	.size	s6_evt0, 1
s6_evt0:
	.zero	1
	.globl	_x_s6_evt0
	.type	_x_s6_evt0, @object
	.size	_x_s6_evt0, 1
_x_s6_evt0:
	.zero	1
	.globl	s3_l2
	.type	s3_l2, @object
	.size	s3_l2, 1
s3_l2:
	.zero	1
	.globl	_x_s3_l2
	.type	_x_s3_l2, @object
	.size	_x_s3_l2, 1
_x_s3_l2:
	.zero	1
	.globl	s1_l1
	.type	s1_l1, @object
	.size	s1_l1, 1
s1_l1:
	.zero	1
	.globl	_x_s1_l1
	.type	_x_s1_l1, @object
	.size	_x_s1_l1, 1
_x_s1_l1:
	.zero	1
	.globl	s4_evt1
	.type	s4_evt1, @object
	.size	s4_evt1, 1
s4_evt1:
	.zero	1
	.globl	_x_s4_evt1
	.type	_x_s4_evt1, @object
	.size	_x_s4_evt1, 1
_x_s4_evt1:
	.zero	1
	.globl	s4_l2
	.type	s4_l2, @object
	.size	s4_l2, 1
s4_l2:
	.zero	1
	.globl	_x_s4_l2
	.type	_x_s4_l2, @object
	.size	_x_s4_l2, 1
_x_s4_l2:
	.zero	1
	.globl	s2_l1
	.type	s2_l1, @object
	.size	s2_l1, 1
s2_l1:
	.zero	1
	.globl	_x_s2_l1
	.type	_x_s2_l1, @object
	.size	_x_s2_l1, 1
_x_s2_l1:
	.zero	1
	.globl	s5_evt1
	.type	s5_evt1, @object
	.size	s5_evt1, 1
s5_evt1:
	.zero	1
	.globl	_x_s5_evt1
	.type	_x_s5_evt1, @object
	.size	_x_s5_evt1, 1
_x_s5_evt1:
	.zero	1
	.globl	s5_l2
	.type	s5_l2, @object
	.size	s5_l2, 1
s5_l2:
	.zero	1
	.globl	_x_s5_l2
	.type	_x_s5_l2, @object
	.size	_x_s5_l2, 1
_x_s5_l2:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s13_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s13_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s13_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s12_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s12_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s12_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s11_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s11_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s11_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s10_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s10_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s10_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s9_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s9_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s9_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s8_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s8_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s7_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s7_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR r_event1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s5_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s6_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR r_l[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s4_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR r_evt_id[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s4_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_evt1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR r_counter[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s4_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR r_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR r_event0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s3_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s5_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s3_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s6_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_l2[rip], al
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L5
.L4:
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L6
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L5
.L6:
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L7
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L5
.L7:
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L8
.L5:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L9
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L9
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L10
.L9:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L11
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L11
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L10
.L11:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L12
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L10
.L12:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L13
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L10
.L13:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	je	.L14
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L10
.L14:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L8
.L10:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s13_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s13_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L18
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L18
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L18
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L8
.L18:
	movss	xmm1, DWORD PTR s13_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L19
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L19
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L19
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L8
.L19:
	movss	xmm1, DWORD PTR s13_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L20
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L8
.L20:
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L21
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L22
.L21:
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L23
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L22
.L23:
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L22
.L24:
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L8
.L22:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L25
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L25
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L26
.L25:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L27
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L27
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L26
.L27:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L28
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L26
.L28:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L29
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L29
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L26
.L29:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	je	.L30
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L26
.L30:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L8
.L26:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s12_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s12_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L34
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L34
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L8
.L34:
	movss	xmm1, DWORD PTR s12_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L35
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L35
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L35
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L8
.L35:
	movss	xmm1, DWORD PTR s12_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L36
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L8
.L36:
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L37
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L38
.L37:
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L38
.L39:
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L40
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L38
.L40:
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L8
.L38:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L42
.L41:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L43
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L43
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L42
.L43:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L44
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L44
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L42
.L44:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L45
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L42
.L45:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L46
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L42
.L46:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L8
.L42:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s11_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s11_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L50
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L50
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L50
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L8
.L50:
	movss	xmm1, DWORD PTR s11_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L51
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L51
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L51
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L8
.L51:
	movss	xmm1, DWORD PTR s11_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L52
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	je	.L52
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L52
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L8
.L52:
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L53
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L54
.L53:
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L55
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L54
.L55:
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L54
.L56:
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L8
.L54:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L58
.L57:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L58
.L59:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L58
.L60:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L58
.L61:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	je	.L62
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L58
.L62:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L8
.L58:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s10_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s10_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L66
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L66
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L66
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L8
.L66:
	movss	xmm1, DWORD PTR s10_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L67
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L67
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L67
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L8
.L67:
	movss	xmm1, DWORD PTR s10_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L68
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	je	.L68
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L68
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L8
.L68:
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L69
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L70
.L69:
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L71
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L70
.L71:
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L70
.L72:
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L8
.L70:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L73
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L73
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L74
.L73:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L75
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L75
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L74
.L75:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L76
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L74
.L76:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L77
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L74
.L77:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	je	.L78
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L78
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L74
.L78:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L8
.L74:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s9_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s9_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L82
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L82
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L8
.L82:
	movss	xmm1, DWORD PTR s9_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L83
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L83
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L83
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L8
.L83:
	movss	xmm1, DWORD PTR s9_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L84
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L8
.L84:
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L86
.L85:
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L87
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L86
.L87:
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L86
.L88:
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L8
.L86:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L90
.L89:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L91
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L90
.L91:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L92
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L90
.L92:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L93
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L90
.L93:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	je	.L94
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L90
.L94:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L8
.L90:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s8_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s8_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L98
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L8
.L98:
	movss	xmm1, DWORD PTR s8_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L99
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L99
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L99
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L8
.L99:
	movss	xmm1, DWORD PTR s8_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L100
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L8
.L100:
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L101
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L102
.L101:
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L102
.L103:
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L102
.L104:
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L8
.L102:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L105
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L105
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L106
.L105:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L107
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L106
.L107:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L108
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L106
.L108:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L109
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L106
.L109:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	je	.L110
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L106
.L110:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L8
.L106:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s7_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s7_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L114
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L114
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L8
.L114:
	movss	xmm1, DWORD PTR s7_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L115
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L115
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L115
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L8
.L115:
	movss	xmm1, DWORD PTR s7_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L116
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L8
.L116:
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L117
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L118
.L117:
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L118
.L119:
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L118
.L120:
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L8
.L118:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L121
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L121
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L122
.L121:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L123
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L123
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L122
.L123:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L124
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L124
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L122
.L124:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L125
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L125
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L122
.L125:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	je	.L126
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L122
.L126:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L8
.L122:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s6_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s6_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L130
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L8
.L130:
	movss	xmm1, DWORD PTR s6_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L131
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L131
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L8
.L131:
	movss	xmm1, DWORD PTR s6_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L132
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	je	.L132
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L132
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L8
.L132:
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L134
.L133:
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L135
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L134
.L135:
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L136
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L134
.L136:
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L8
.L134:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L137
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L137
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L138
.L137:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L139
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L139
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L138
.L139:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L138
.L140:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L138
.L141:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	je	.L142
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L138
.L142:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L8
.L138:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s5_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s5_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L146
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L8
.L146:
	movss	xmm1, DWORD PTR s5_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L147
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L147
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L147
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L8
.L147:
	movss	xmm1, DWORD PTR s5_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L148
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L8
.L148:
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L150
.L149:
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L150
.L151:
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L150
.L152:
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L8
.L150:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L153
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L153
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L154
.L153:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L155
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L155
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L154
.L155:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L154
.L156:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L157
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L154
.L157:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L154
.L158:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L8
.L154:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s4_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s4_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L162
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L8
.L162:
	movss	xmm1, DWORD PTR s4_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L163
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L163
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L163
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L8
.L163:
	movss	xmm1, DWORD PTR s4_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L164
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L8
.L164:
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L165
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L166
.L165:
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L167
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L166
.L167:
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L166
.L168:
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L8
.L166:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L170
.L169:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L171
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L171
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L170
.L171:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L172
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L170
.L172:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L173
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L170
.L173:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	je	.L174
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L170
.L174:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L8
.L170:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s3_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s3_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L178
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L178
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L8
.L178:
	movss	xmm1, DWORD PTR s3_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L179
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L179
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L8
.L179:
	movss	xmm1, DWORD PTR s3_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L180
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L8
.L180:
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L182
.L181:
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L183
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L182
.L183:
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L184
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L182
.L184:
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L8
.L182:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L186
.L185:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L187
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L186
.L187:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L186
.L188:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L189
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L186
.L189:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L186
.L190:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L8
.L186:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s2_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s2_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L194
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L8
.L194:
	movss	xmm1, DWORD PTR s2_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L195
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L195
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L195
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L8
.L195:
	movss	xmm1, DWORD PTR s2_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L196
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L8
.L196:
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L197
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L198
.L197:
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L199
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L198
.L199:
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L198
.L200:
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L8
.L198:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L202
.L201:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L202
.L203:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L204
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L202
.L204:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L202
.L205:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	je	.L206
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L202
.L206:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L8
.L202:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s1_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s1_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L210
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L210
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L8
.L210:
	movss	xmm1, DWORD PTR s1_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L211
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L8
.L211:
	movss	xmm1, DWORD PTR s1_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L212
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L8
.L212:
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L213
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L214
.L213:
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L215
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L214
.L215:
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L214
.L216:
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L8
.L214:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L218
.L217:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L219
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L218
.L219:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L220
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L218
.L220:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L221
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L218
.L221:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L218
.L222:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L8
.L218:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L8
	movss	xmm0, DWORD PTR s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s0_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm0, DWORD PTR s0_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movss	xmm1, DWORD PTR s0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L226
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L8
.L226:
	movss	xmm1, DWORD PTR s0_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L227
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L227
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L8
.L227:
	movss	xmm1, DWORD PTR s0_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L228
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L8
.L228:
	movzx	eax, BYTE PTR r_l[rip]
	test	al, al
	je	.L8
	mov	eax, DWORD PTR r_counter[rip]
	test	eax, eax
	jne	.L8
	movss	xmm0, DWORD PTR r_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L8
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L8
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L231
.L230:
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L231
.L232:
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L8
.L231:
	mov	eax, DWORD PTR r_evt_id[rip]
	test	eax, eax
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 1
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 2
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 3
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 4
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 5
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 6
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 7
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 8
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 9
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 10
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 11
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 12
	je	.L233
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 13
	jne	.L8
.L233:
	mov	eax, DWORD PTR r_counter[rip]
	test	eax, eax
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 1
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 2
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 3
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 4
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 5
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 6
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 7
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 8
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 9
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 10
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 11
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 12
	je	.L234
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 13
	jne	.L8
.L234:
	movzx	eax, BYTE PTR r_l[rip]
	test	al, al
	je	.L235
	movss	xmm1, DWORD PTR r_x[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L8
.L235:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L8
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L8
	ucomiss	xmm0, xmm1
	jne	.L8
	mov	eax, 1
	jmp	.L239
.L8:
	mov	eax, 0
.L239:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L240
.L1407:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s13_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s13_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s13_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s12_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s12_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s12_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s11_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s11_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s11_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s10_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s10_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s10_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s9_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s9_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s9_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s8_z[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s8_y[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s7_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s7_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_r_event1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s5_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s6_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_r_l[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s4_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_r_evt_id[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s4_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_evt1[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_r_counter[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s4_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_r_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_r_event0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s3_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s5_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_l2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s3_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s6_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_l2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_l2[rip], al
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L242
.L241:
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	je	.L243
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L242
.L243:
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L244
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	je	.L242
.L244:
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L245
.L242:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L247
.L246:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L248
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L247
.L248:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L249
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L247
.L249:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L250
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L250
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L247
.L250:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	je	.L251
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L251
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L247
.L251:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L245
.L247:
	movss	xmm1, DWORD PTR _x_s13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L252
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L252
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L252
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L245
.L252:
	movss	xmm1, DWORD PTR _x_s13_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L253
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L245
.L253:
	movss	xmm1, DWORD PTR _x_s13_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L254
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L245
.L254:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L255
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s13_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s13_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s13_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s13_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s13_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s13_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L255:
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L259
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L259
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L259
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s13_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s13_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L259
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L259
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s13_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s13_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L259
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L259
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s13_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s13_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L259
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L262
.L259:
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L262
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L245
.L262:
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L264
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L264
	movss	xmm0, DWORD PTR _x_s13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L264
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L264
	movss	xmm0, DWORD PTR _x_s13_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L264
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L264
	movss	xmm0, DWORD PTR s13_z[rip]
	movss	xmm1, DWORD PTR _x_s13_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L264
	ucomiss	xmm0, xmm1
	je	.L267
.L264:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L267
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L267
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L267
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L267
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L267
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L245
.L267:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L269
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L269
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L270
.L269:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L271
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L271
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L271
.L270:
	movss	xmm0, DWORD PTR s13_x[rip]
	movss	xmm1, DWORD PTR _x_s13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L271
	ucomiss	xmm0, xmm1
	jne	.L271
	movss	xmm0, DWORD PTR s13_z[rip]
	movss	xmm1, DWORD PTR _x_s13_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L271
	ucomiss	xmm0, xmm1
	jne	.L271
	movss	xmm0, DWORD PTR s13_y[rip]
	movss	xmm1, DWORD PTR _x_s13_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L271
	ucomiss	xmm0, xmm1
	je	.L274
.L271:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L274
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L274
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L274
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L274
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L245
.L274:
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L276
	movss	xmm0, DWORD PTR s13_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L276
	movss	xmm0, DWORD PTR s13_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L278
.L276:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L278
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L278
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L279
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L278
.L279:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L278
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L278
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L245
.L278:
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L280
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L280
	movss	xmm0, DWORD PTR s13_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L280
	movss	xmm0, DWORD PTR s13_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L282
.L280:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L282
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L282
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L283
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L282
.L283:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L282
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L282
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L282
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L282
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L282
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L245
.L282:
	movss	xmm0, DWORD PTR s13_z[rip]
	movss	xmm1, DWORD PTR _x_s13_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L284
	ucomiss	xmm0, xmm1
	jne	.L284
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L284
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L284
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L284
	movss	xmm0, DWORD PTR s13_x[rip]
	movss	xmm1, DWORD PTR _x_s13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L284
	ucomiss	xmm0, xmm1
	jne	.L284
	movss	xmm0, DWORD PTR s13_y[rip]
	movss	xmm1, DWORD PTR _x_s13_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L284
	ucomiss	xmm0, xmm1
	je	.L287
.L284:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L287
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L287
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L287
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L287
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L287
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L245
.L287:
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L289
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L289
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	je	.L289
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L289
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L289
	movss	xmm0, DWORD PTR _x_s13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L289
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L289
	movss	xmm0, DWORD PTR s13_y[rip]
	movss	xmm1, DWORD PTR _x_s13_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L289
	ucomiss	xmm0, xmm1
	jne	.L289
	movss	xmm0, DWORD PTR _x_s13_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L289
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L292
.L289:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	jne	.L292
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L292
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L292
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L292
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L245
.L292:
	movss	xmm0, DWORD PTR s13_x[rip]
	movss	xmm1, DWORD PTR _x_s13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L294
	ucomiss	xmm0, xmm1
	jne	.L294
	movss	xmm0, DWORD PTR s13_y[rip]
	movss	xmm1, DWORD PTR _x_s13_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L294
	ucomiss	xmm0, xmm1
	jne	.L294
	movss	xmm0, DWORD PTR s13_z[rip]
	movss	xmm1, DWORD PTR _x_s13_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L294
	ucomiss	xmm0, xmm1
	jne	.L294
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L299
.L298:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	je	.L294
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L294
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L299
.L294:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L299
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L299
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L299
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L245
.L299:
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L300
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L300
	movss	xmm0, DWORD PTR s13_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L300
	movss	xmm0, DWORD PTR s13_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L302
.L300:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L302
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L302
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L303
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L302
.L303:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L302
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L302
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L245
.L302:
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L304
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L304
	movss	xmm0, DWORD PTR s13_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L304
	movss	xmm0, DWORD PTR s13_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L306
.L304:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L306
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L306
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L307
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L306
.L307:
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	je	.L306
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L245
.L306:
	movss	xmm0, DWORD PTR s13_z[rip]
	movss	xmm1, DWORD PTR _x_s13_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L308
	ucomiss	xmm0, xmm1
	jne	.L308
	movss	xmm0, DWORD PTR s13_x[rip]
	movss	xmm1, DWORD PTR _x_s13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L308
	ucomiss	xmm0, xmm1
	jne	.L308
	movss	xmm0, DWORD PTR s13_y[rip]
	movss	xmm1, DWORD PTR _x_s13_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L308
	ucomiss	xmm0, xmm1
	jne	.L308
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L308
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L308
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	test	al, al
	jne	.L308
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L308
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L312
.L308:
	movzx	eax, BYTE PTR s13_l2[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L312
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L312
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L312
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L245
.L312:
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	jne	.L313
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L314
.L313:
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L314
.L315:
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L316
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	je	.L314
.L316:
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L245
.L314:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L317
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L317
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L318
.L317:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L319
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L319
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L318
.L319:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L320
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L320
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L318
.L320:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L321
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L318
.L321:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	je	.L322
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L322
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L318
.L322:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L245
.L318:
	movss	xmm1, DWORD PTR _x_s12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L323
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L323
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L323
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L245
.L323:
	movss	xmm1, DWORD PTR _x_s12_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L324
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L324
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L324
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L245
.L324:
	movss	xmm1, DWORD PTR _x_s12_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L325
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L245
.L325:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L326
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s12_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s12_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s12_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s12_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L326:
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L330
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L330
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L330
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L330
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L330
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s12_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s12_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L330
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L330
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s12_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s12_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L330
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L333
.L330:
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L333
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L245
.L333:
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L335
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L335
	movss	xmm0, DWORD PTR _x_s12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L335
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L335
	movss	xmm0, DWORD PTR _x_s12_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L335
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L335
	movss	xmm0, DWORD PTR s12_z[rip]
	movss	xmm1, DWORD PTR _x_s12_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L335
	ucomiss	xmm0, xmm1
	je	.L338
.L335:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L338
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L338
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L338
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L338
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L338
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L245
.L338:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L340
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L340
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L341
.L340:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L342
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L342
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L342
.L341:
	movss	xmm0, DWORD PTR s12_x[rip]
	movss	xmm1, DWORD PTR _x_s12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L342
	ucomiss	xmm0, xmm1
	jne	.L342
	movss	xmm0, DWORD PTR s12_z[rip]
	movss	xmm1, DWORD PTR _x_s12_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L342
	ucomiss	xmm0, xmm1
	jne	.L342
	movss	xmm0, DWORD PTR s12_y[rip]
	movss	xmm1, DWORD PTR _x_s12_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L342
	ucomiss	xmm0, xmm1
	je	.L345
.L342:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L345
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L345
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L345
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L345
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L245
.L345:
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L347
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L347
	movss	xmm0, DWORD PTR s12_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L347
	movss	xmm0, DWORD PTR s12_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L349
.L347:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L349
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L349
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L350
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L349
.L350:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L349
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L349
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L349
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L245
.L349:
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L351
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L351
	movss	xmm0, DWORD PTR s12_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L351
	movss	xmm0, DWORD PTR s12_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L353
.L351:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L353
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L353
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L354
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L353
.L354:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L353
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L353
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L353
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L353
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L353
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L245
.L353:
	movss	xmm0, DWORD PTR s12_z[rip]
	movss	xmm1, DWORD PTR _x_s12_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L355
	ucomiss	xmm0, xmm1
	jne	.L355
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L355
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L355
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L355
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L355
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L355
	movss	xmm0, DWORD PTR s12_x[rip]
	movss	xmm1, DWORD PTR _x_s12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L355
	ucomiss	xmm0, xmm1
	jne	.L355
	movss	xmm0, DWORD PTR s12_y[rip]
	movss	xmm1, DWORD PTR _x_s12_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L355
	ucomiss	xmm0, xmm1
	je	.L358
.L355:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L358
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L358
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L358
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L358
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L358
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L245
.L358:
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L360
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L360
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	je	.L360
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L360
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L360
	movss	xmm0, DWORD PTR _x_s12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L360
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L360
	movss	xmm0, DWORD PTR s12_y[rip]
	movss	xmm1, DWORD PTR _x_s12_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L360
	ucomiss	xmm0, xmm1
	jne	.L360
	movss	xmm0, DWORD PTR _x_s12_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L360
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L363
.L360:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	jne	.L363
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L363
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L363
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L363
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L363
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L245
.L363:
	movss	xmm0, DWORD PTR s12_x[rip]
	movss	xmm1, DWORD PTR _x_s12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L365
	ucomiss	xmm0, xmm1
	jne	.L365
	movss	xmm0, DWORD PTR s12_y[rip]
	movss	xmm1, DWORD PTR _x_s12_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L365
	ucomiss	xmm0, xmm1
	jne	.L365
	movss	xmm0, DWORD PTR s12_z[rip]
	movss	xmm1, DWORD PTR _x_s12_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L365
	ucomiss	xmm0, xmm1
	jne	.L365
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L369
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L369
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L370
.L369:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L370
.L365:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	je	.L370
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L370
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L370
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L370
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L370
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L245
.L370:
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L371
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L371
	movss	xmm0, DWORD PTR s12_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L371
	movss	xmm0, DWORD PTR s12_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L373
.L371:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L373
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L373
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L374
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L373
.L374:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L373
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L373
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L245
.L373:
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L375
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L375
	movss	xmm0, DWORD PTR s12_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L375
	movss	xmm0, DWORD PTR s12_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L377
.L375:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L377
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L377
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L378
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L377
.L378:
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L377
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L377
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L377
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	je	.L377
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L377
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L245
.L377:
	movss	xmm0, DWORD PTR s12_z[rip]
	movss	xmm1, DWORD PTR _x_s12_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L379
	ucomiss	xmm0, xmm1
	jne	.L379
	movss	xmm0, DWORD PTR s12_x[rip]
	movss	xmm1, DWORD PTR _x_s12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L379
	ucomiss	xmm0, xmm1
	jne	.L379
	movss	xmm0, DWORD PTR s12_y[rip]
	movss	xmm1, DWORD PTR _x_s12_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L379
	ucomiss	xmm0, xmm1
	jne	.L379
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L379
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L379
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	test	al, al
	jne	.L379
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L379
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L383
.L379:
	movzx	eax, BYTE PTR s12_l2[rip]
	test	al, al
	je	.L383
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L383
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L383
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L383
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L383
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L245
.L383:
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	jne	.L384
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L385
.L384:
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	je	.L386
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L385
.L386:
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L387
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	je	.L385
.L387:
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L245
.L385:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L388
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L388
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L389
.L388:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L390
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L390
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L389
.L390:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L391
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L391
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L389
.L391:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L392
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L392
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L389
.L392:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L393
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L389
.L393:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L245
.L389:
	movss	xmm1, DWORD PTR _x_s11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L394
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L394
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L394
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L245
.L394:
	movss	xmm1, DWORD PTR _x_s11_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L395
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L395
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L395
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L245
.L395:
	movss	xmm1, DWORD PTR _x_s11_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L396
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	je	.L396
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L396
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L245
.L396:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L397
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s11_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s11_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s11_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s11_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L397:
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L401
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L401
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L401
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s11_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s11_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L401
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L401
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s11_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s11_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L401
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L404
.L401:
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L404
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L245
.L404:
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L406
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L406
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L406
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L406
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L406
	movss	xmm0, DWORD PTR _x_s11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L406
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L406
	movss	xmm0, DWORD PTR _x_s11_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L406
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L406
	movss	xmm0, DWORD PTR s11_z[rip]
	movss	xmm1, DWORD PTR _x_s11_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L406
	ucomiss	xmm0, xmm1
	je	.L409
.L406:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L409
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L409
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L409
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L409
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L409
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L245
.L409:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L411
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L411
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L412
.L411:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L413
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L413
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L413
.L412:
	movss	xmm0, DWORD PTR s11_x[rip]
	movss	xmm1, DWORD PTR _x_s11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L413
	ucomiss	xmm0, xmm1
	jne	.L413
	movss	xmm0, DWORD PTR s11_z[rip]
	movss	xmm1, DWORD PTR _x_s11_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L413
	ucomiss	xmm0, xmm1
	jne	.L413
	movss	xmm0, DWORD PTR s11_y[rip]
	movss	xmm1, DWORD PTR _x_s11_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L413
	ucomiss	xmm0, xmm1
	je	.L416
.L413:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L416
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L416
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L416
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L416
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L416
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L245
.L416:
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L418
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L418
	movss	xmm0, DWORD PTR s11_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L418
	movss	xmm0, DWORD PTR s11_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L420
.L418:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L420
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L420
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L421
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L420
.L421:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L420
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L420
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L420
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L420
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L420
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L245
.L420:
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L422
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L422
	movss	xmm0, DWORD PTR s11_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L422
	movss	xmm0, DWORD PTR s11_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L424
.L422:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L424
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L424
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L425
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L424
.L425:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L424
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L424
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L424
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L424
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L424
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L245
.L424:
	movss	xmm0, DWORD PTR s11_z[rip]
	movss	xmm1, DWORD PTR _x_s11_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L426
	ucomiss	xmm0, xmm1
	jne	.L426
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L426
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L426
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L426
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L426
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L426
	movss	xmm0, DWORD PTR s11_x[rip]
	movss	xmm1, DWORD PTR _x_s11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L426
	ucomiss	xmm0, xmm1
	jne	.L426
	movss	xmm0, DWORD PTR s11_y[rip]
	movss	xmm1, DWORD PTR _x_s11_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L426
	ucomiss	xmm0, xmm1
	je	.L429
.L426:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L429
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L429
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L429
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L429
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L245
.L429:
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L431
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L431
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	je	.L431
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L431
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L431
	movss	xmm0, DWORD PTR _x_s11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L431
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L431
	movss	xmm0, DWORD PTR s11_y[rip]
	movss	xmm1, DWORD PTR _x_s11_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L431
	ucomiss	xmm0, xmm1
	jne	.L431
	movss	xmm0, DWORD PTR _x_s11_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L431
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L434
.L431:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	jne	.L434
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L434
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L434
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L434
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L434
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L245
.L434:
	movss	xmm0, DWORD PTR s11_x[rip]
	movss	xmm1, DWORD PTR _x_s11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L436
	ucomiss	xmm0, xmm1
	jne	.L436
	movss	xmm0, DWORD PTR s11_y[rip]
	movss	xmm1, DWORD PTR _x_s11_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L436
	ucomiss	xmm0, xmm1
	jne	.L436
	movss	xmm0, DWORD PTR s11_z[rip]
	movss	xmm1, DWORD PTR _x_s11_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L436
	ucomiss	xmm0, xmm1
	jne	.L436
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L440
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L440
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L441
.L440:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	je	.L436
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L436
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L441
.L436:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	je	.L441
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L441
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L441
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L441
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L441
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L245
.L441:
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L442
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L442
	movss	xmm0, DWORD PTR s11_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L442
	movss	xmm0, DWORD PTR s11_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L444
.L442:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L444
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L444
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L445
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L444
.L445:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L444
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L444
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L245
.L444:
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L446
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L446
	movss	xmm0, DWORD PTR s11_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L446
	movss	xmm0, DWORD PTR s11_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L448
.L446:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L448
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L448
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L449
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L448
.L449:
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L448
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L448
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L448
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	je	.L448
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L448
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L245
.L448:
	movss	xmm0, DWORD PTR s11_z[rip]
	movss	xmm1, DWORD PTR _x_s11_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L450
	ucomiss	xmm0, xmm1
	jne	.L450
	movss	xmm0, DWORD PTR s11_x[rip]
	movss	xmm1, DWORD PTR _x_s11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L450
	ucomiss	xmm0, xmm1
	jne	.L450
	movss	xmm0, DWORD PTR s11_y[rip]
	movss	xmm1, DWORD PTR _x_s11_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L450
	ucomiss	xmm0, xmm1
	jne	.L450
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L450
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L454
.L450:
	movzx	eax, BYTE PTR s11_l2[rip]
	test	al, al
	je	.L454
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L454
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L454
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L454
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L454
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L245
.L454:
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	jne	.L455
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L456
.L455:
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L456
.L457:
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L458
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	je	.L456
.L458:
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L245
.L456:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L459
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L459
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L460
.L459:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L461
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L461
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L460
.L461:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L462
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L462
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L460
.L462:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L463
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L463
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L460
.L463:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	je	.L464
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L464
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L460
.L464:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L245
.L460:
	movss	xmm1, DWORD PTR _x_s10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L465
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L465
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L245
.L465:
	movss	xmm1, DWORD PTR _x_s10_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L466
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L466
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L466
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L245
.L466:
	movss	xmm1, DWORD PTR _x_s10_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L467
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	je	.L467
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L467
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L245
.L467:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L468
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s10_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s10_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s10_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s10_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L468:
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L472
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L472
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L472
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s10_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s10_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L472
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L472
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s10_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s10_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L472
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L475
.L472:
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L475
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L245
.L475:
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L477
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L477
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L477
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L477
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L477
	movss	xmm0, DWORD PTR _x_s10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L477
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L477
	movss	xmm0, DWORD PTR _x_s10_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L477
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L477
	movss	xmm0, DWORD PTR s10_z[rip]
	movss	xmm1, DWORD PTR _x_s10_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L477
	ucomiss	xmm0, xmm1
	je	.L480
.L477:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L480
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L480
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L480
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L480
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L480
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L245
.L480:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L482
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L482
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L483
.L482:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L484
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L484
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L484
.L483:
	movss	xmm0, DWORD PTR s10_x[rip]
	movss	xmm1, DWORD PTR _x_s10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L484
	ucomiss	xmm0, xmm1
	jne	.L484
	movss	xmm0, DWORD PTR s10_z[rip]
	movss	xmm1, DWORD PTR _x_s10_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L484
	ucomiss	xmm0, xmm1
	jne	.L484
	movss	xmm0, DWORD PTR s10_y[rip]
	movss	xmm1, DWORD PTR _x_s10_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L484
	ucomiss	xmm0, xmm1
	je	.L487
.L484:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L487
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L487
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L487
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L487
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L487
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L245
.L487:
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L489
	movss	xmm0, DWORD PTR s10_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L489
	movss	xmm0, DWORD PTR s10_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L491
.L489:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L491
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L491
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L492
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L491
.L492:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L491
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L491
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L491
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L491
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L491
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L245
.L491:
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L493
	movss	xmm0, DWORD PTR s10_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L493
	movss	xmm0, DWORD PTR s10_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L495
.L493:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L495
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L495
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L496
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L495
.L496:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L495
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L495
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L495
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L245
.L495:
	movss	xmm0, DWORD PTR s10_z[rip]
	movss	xmm1, DWORD PTR _x_s10_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L497
	ucomiss	xmm0, xmm1
	jne	.L497
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L497
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L497
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L497
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L497
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L497
	movss	xmm0, DWORD PTR s10_x[rip]
	movss	xmm1, DWORD PTR _x_s10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L497
	ucomiss	xmm0, xmm1
	jne	.L497
	movss	xmm0, DWORD PTR s10_y[rip]
	movss	xmm1, DWORD PTR _x_s10_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L497
	ucomiss	xmm0, xmm1
	je	.L500
.L497:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L500
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L500
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L500
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L500
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L500
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L245
.L500:
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L502
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L502
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	je	.L502
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L502
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L502
	movss	xmm0, DWORD PTR _x_s10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L502
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L502
	movss	xmm0, DWORD PTR s10_y[rip]
	movss	xmm1, DWORD PTR _x_s10_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L502
	ucomiss	xmm0, xmm1
	jne	.L502
	movss	xmm0, DWORD PTR _x_s10_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L502
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L505
.L502:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	jne	.L505
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L505
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L505
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L505
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L245
.L505:
	movss	xmm0, DWORD PTR s10_x[rip]
	movss	xmm1, DWORD PTR _x_s10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L507
	ucomiss	xmm0, xmm1
	jne	.L507
	movss	xmm0, DWORD PTR s10_y[rip]
	movss	xmm1, DWORD PTR _x_s10_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L507
	ucomiss	xmm0, xmm1
	jne	.L507
	movss	xmm0, DWORD PTR s10_z[rip]
	movss	xmm1, DWORD PTR _x_s10_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L507
	ucomiss	xmm0, xmm1
	jne	.L507
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L511
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L511
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L512
.L511:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	je	.L507
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L507
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L512
.L507:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L512
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L512
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L512
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L512
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L245
.L512:
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L513
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L513
	movss	xmm0, DWORD PTR s10_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L513
	movss	xmm0, DWORD PTR s10_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L515
.L513:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L515
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L515
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L516
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L515
.L516:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	je	.L515
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L515
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L515
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	je	.L515
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L515
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L245
.L515:
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L517
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L517
	movss	xmm0, DWORD PTR s10_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L517
	movss	xmm0, DWORD PTR s10_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L519
.L517:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L519
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L519
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L520
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L519
.L520:
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L519
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L519
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L519
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	je	.L519
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L519
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L245
.L519:
	movss	xmm0, DWORD PTR s10_z[rip]
	movss	xmm1, DWORD PTR _x_s10_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L521
	ucomiss	xmm0, xmm1
	jne	.L521
	movss	xmm0, DWORD PTR s10_x[rip]
	movss	xmm1, DWORD PTR _x_s10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L521
	ucomiss	xmm0, xmm1
	jne	.L521
	movss	xmm0, DWORD PTR s10_y[rip]
	movss	xmm1, DWORD PTR _x_s10_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L521
	ucomiss	xmm0, xmm1
	jne	.L521
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L521
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L521
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	test	al, al
	jne	.L521
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L521
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L525
.L521:
	movzx	eax, BYTE PTR s10_l2[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L525
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L525
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L525
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L245
.L525:
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L527
.L526:
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	je	.L528
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L527
.L528:
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	je	.L527
.L529:
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L245
.L527:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L530
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L530
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L531
.L530:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L532
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L532
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L531
.L532:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L533
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L533
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L531
.L533:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L534
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L531
.L534:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	je	.L535
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L535
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L531
.L535:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L245
.L531:
	movss	xmm1, DWORD PTR _x_s9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L536
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L536
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L245
.L536:
	movss	xmm1, DWORD PTR _x_s9_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L537
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L537
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L245
.L537:
	movss	xmm1, DWORD PTR _x_s9_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L538
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	je	.L538
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L538
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L245
.L538:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L539
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s9_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s9_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s9_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s9_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L539:
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L543
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L543
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L543
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L543
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L543
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s9_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s9_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L543
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L543
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s9_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s9_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L543
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L546
.L543:
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L546
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L245
.L546:
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L548
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L548
	movss	xmm0, DWORD PTR _x_s9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L548
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L548
	movss	xmm0, DWORD PTR _x_s9_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L548
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L548
	movss	xmm0, DWORD PTR s9_z[rip]
	movss	xmm1, DWORD PTR _x_s9_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L548
	ucomiss	xmm0, xmm1
	je	.L551
.L548:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L551
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L551
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L551
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L551
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L551
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L245
.L551:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L553
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L553
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L554
.L553:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L555
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L555
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L555
.L554:
	movss	xmm0, DWORD PTR s9_x[rip]
	movss	xmm1, DWORD PTR _x_s9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L555
	ucomiss	xmm0, xmm1
	jne	.L555
	movss	xmm0, DWORD PTR s9_z[rip]
	movss	xmm1, DWORD PTR _x_s9_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L555
	ucomiss	xmm0, xmm1
	jne	.L555
	movss	xmm0, DWORD PTR s9_y[rip]
	movss	xmm1, DWORD PTR _x_s9_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L555
	ucomiss	xmm0, xmm1
	je	.L558
.L555:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L558
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L558
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L558
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L558
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L558
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L245
.L558:
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L560
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L560
	movss	xmm0, DWORD PTR s9_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L560
	movss	xmm0, DWORD PTR s9_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L562
.L560:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L562
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L562
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L563
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L562
.L563:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L562
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L562
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L245
.L562:
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L564
	movss	xmm0, DWORD PTR s9_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L564
	movss	xmm0, DWORD PTR s9_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L566
.L564:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L566
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L566
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L567
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L566
.L567:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L566
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L566
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L566
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L566
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L566
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L245
.L566:
	movss	xmm0, DWORD PTR s9_z[rip]
	movss	xmm1, DWORD PTR _x_s9_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L568
	ucomiss	xmm0, xmm1
	jne	.L568
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L568
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L568
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L568
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L568
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L568
	movss	xmm0, DWORD PTR s9_x[rip]
	movss	xmm1, DWORD PTR _x_s9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L568
	ucomiss	xmm0, xmm1
	jne	.L568
	movss	xmm0, DWORD PTR s9_y[rip]
	movss	xmm1, DWORD PTR _x_s9_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L568
	ucomiss	xmm0, xmm1
	je	.L571
.L568:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L571
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L571
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L571
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L571
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L571
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L245
.L571:
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L573
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L573
	movss	xmm0, DWORD PTR _x_s9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L573
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L573
	movss	xmm0, DWORD PTR s9_y[rip]
	movss	xmm1, DWORD PTR _x_s9_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L573
	ucomiss	xmm0, xmm1
	jne	.L573
	movss	xmm0, DWORD PTR _x_s9_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L573
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L576
.L573:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	jne	.L576
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L576
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L576
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L576
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L576
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L245
.L576:
	movss	xmm0, DWORD PTR s9_x[rip]
	movss	xmm1, DWORD PTR _x_s9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L578
	ucomiss	xmm0, xmm1
	jne	.L578
	movss	xmm0, DWORD PTR s9_y[rip]
	movss	xmm1, DWORD PTR _x_s9_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L578
	ucomiss	xmm0, xmm1
	jne	.L578
	movss	xmm0, DWORD PTR s9_z[rip]
	movss	xmm1, DWORD PTR _x_s9_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L578
	ucomiss	xmm0, xmm1
	jne	.L578
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L582
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L582
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L583
.L582:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L583
.L578:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	je	.L583
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L583
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L583
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L583
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L583
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L245
.L583:
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L584
	movss	xmm0, DWORD PTR s9_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L584
	movss	xmm0, DWORD PTR s9_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L586
.L584:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L586
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L586
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L587
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L586
.L587:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	je	.L586
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L586
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L586
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	je	.L586
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L586
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L245
.L586:
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L588
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L588
	movss	xmm0, DWORD PTR s9_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L588
	movss	xmm0, DWORD PTR s9_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L590
.L588:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L590
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L590
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L591
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L590
.L591:
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L590
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L590
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L590
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L590
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L245
.L590:
	movss	xmm0, DWORD PTR s9_z[rip]
	movss	xmm1, DWORD PTR _x_s9_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L592
	ucomiss	xmm0, xmm1
	jne	.L592
	movss	xmm0, DWORD PTR s9_x[rip]
	movss	xmm1, DWORD PTR _x_s9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L592
	ucomiss	xmm0, xmm1
	jne	.L592
	movss	xmm0, DWORD PTR s9_y[rip]
	movss	xmm1, DWORD PTR _x_s9_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L592
	ucomiss	xmm0, xmm1
	jne	.L592
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L592
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L592
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	test	al, al
	jne	.L592
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L592
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L596
.L592:
	movzx	eax, BYTE PTR s9_l2[rip]
	test	al, al
	je	.L596
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L596
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L596
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L596
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L596
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L245
.L596:
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	jne	.L597
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L598
.L597:
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	je	.L599
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L598
.L599:
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L600
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	je	.L598
.L600:
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L245
.L598:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L601
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L601
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L602
.L601:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L603
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L603
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L602
.L603:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L604
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L604
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L602
.L604:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L605
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L605
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L602
.L605:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	je	.L606
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L606
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L602
.L606:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L245
.L602:
	movss	xmm1, DWORD PTR _x_s8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L607
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L607
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L607
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L245
.L607:
	movss	xmm1, DWORD PTR _x_s8_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L608
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L608
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L608
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L245
.L608:
	movss	xmm1, DWORD PTR _x_s8_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L609
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L245
.L609:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L610
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s8_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s8_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s8_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s8_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L610:
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L614
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L614
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s8_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s8_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L614
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L614
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s8_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s8_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L614
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L617
.L614:
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L245
.L617:
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L619
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L619
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L619
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L619
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L619
	movss	xmm0, DWORD PTR _x_s8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L619
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L619
	movss	xmm0, DWORD PTR _x_s8_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L619
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L619
	movss	xmm0, DWORD PTR s8_z[rip]
	movss	xmm1, DWORD PTR _x_s8_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L619
	ucomiss	xmm0, xmm1
	je	.L622
.L619:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L622
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L622
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L622
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L622
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L622
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L245
.L622:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L624
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L624
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L625
.L624:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L626
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L626
.L625:
	movss	xmm0, DWORD PTR s8_x[rip]
	movss	xmm1, DWORD PTR _x_s8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L626
	ucomiss	xmm0, xmm1
	jne	.L626
	movss	xmm0, DWORD PTR s8_z[rip]
	movss	xmm1, DWORD PTR _x_s8_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L626
	ucomiss	xmm0, xmm1
	jne	.L626
	movss	xmm0, DWORD PTR s8_y[rip]
	movss	xmm1, DWORD PTR _x_s8_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L626
	ucomiss	xmm0, xmm1
	je	.L629
.L626:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L629
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L629
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L629
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L629
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L629
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L245
.L629:
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L631
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L631
	movss	xmm0, DWORD PTR s8_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L631
	movss	xmm0, DWORD PTR s8_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L633
.L631:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L633
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L633
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L634
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L633
.L634:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L633
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L633
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L633
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L245
.L633:
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L635
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L635
	movss	xmm0, DWORD PTR s8_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L635
	movss	xmm0, DWORD PTR s8_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L637
.L635:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L637
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L637
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L638
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L637
.L638:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L637
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L637
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L637
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L245
.L637:
	movss	xmm0, DWORD PTR s8_z[rip]
	movss	xmm1, DWORD PTR _x_s8_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L639
	ucomiss	xmm0, xmm1
	jne	.L639
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L639
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L639
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L639
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L639
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L639
	movss	xmm0, DWORD PTR s8_x[rip]
	movss	xmm1, DWORD PTR _x_s8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L639
	ucomiss	xmm0, xmm1
	jne	.L639
	movss	xmm0, DWORD PTR s8_y[rip]
	movss	xmm1, DWORD PTR _x_s8_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L639
	ucomiss	xmm0, xmm1
	je	.L642
.L639:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L642
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L642
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L642
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L642
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L245
.L642:
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L644
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L644
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	je	.L644
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L644
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L644
	movss	xmm0, DWORD PTR _x_s8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L644
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L644
	movss	xmm0, DWORD PTR s8_y[rip]
	movss	xmm1, DWORD PTR _x_s8_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L644
	ucomiss	xmm0, xmm1
	jne	.L644
	movss	xmm0, DWORD PTR _x_s8_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L644
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L647
.L644:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	jne	.L647
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L647
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L647
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L647
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L647
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L245
.L647:
	movss	xmm0, DWORD PTR s8_x[rip]
	movss	xmm1, DWORD PTR _x_s8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L649
	ucomiss	xmm0, xmm1
	jne	.L649
	movss	xmm0, DWORD PTR s8_y[rip]
	movss	xmm1, DWORD PTR _x_s8_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L649
	ucomiss	xmm0, xmm1
	jne	.L649
	movss	xmm0, DWORD PTR s8_z[rip]
	movss	xmm1, DWORD PTR _x_s8_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L649
	ucomiss	xmm0, xmm1
	jne	.L649
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L654
.L653:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	je	.L649
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L649
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L654
.L649:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	je	.L654
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L654
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L654
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L654
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L654
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L245
.L654:
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L655
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L655
	movss	xmm0, DWORD PTR s8_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L655
	movss	xmm0, DWORD PTR s8_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L657
.L655:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L657
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L657
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L658
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L657
.L658:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	je	.L657
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L657
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L657
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	je	.L657
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L657
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L245
.L657:
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L659
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L659
	movss	xmm0, DWORD PTR s8_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L659
	movss	xmm0, DWORD PTR s8_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L661
.L659:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L661
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L661
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L662
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L661
.L662:
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L661
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L661
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L661
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	je	.L661
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L661
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L245
.L661:
	movss	xmm0, DWORD PTR s8_z[rip]
	movss	xmm1, DWORD PTR _x_s8_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L663
	ucomiss	xmm0, xmm1
	jne	.L663
	movss	xmm0, DWORD PTR s8_x[rip]
	movss	xmm1, DWORD PTR _x_s8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L663
	ucomiss	xmm0, xmm1
	jne	.L663
	movss	xmm0, DWORD PTR s8_y[rip]
	movss	xmm1, DWORD PTR _x_s8_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L663
	ucomiss	xmm0, xmm1
	jne	.L663
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L663
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L663
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	test	al, al
	jne	.L663
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L663
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L667
.L663:
	movzx	eax, BYTE PTR s8_l2[rip]
	test	al, al
	je	.L667
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L667
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L667
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L667
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L667
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L245
.L667:
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	jne	.L668
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L669
.L668:
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	je	.L670
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L669
.L670:
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L671
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	je	.L669
.L671:
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L245
.L669:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L672
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L672
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L673
.L672:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L674
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L674
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L673
.L674:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L675
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L675
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L673
.L675:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L676
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L676
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L673
.L676:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	je	.L677
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L677
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L673
.L677:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L245
.L673:
	movss	xmm1, DWORD PTR _x_s7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L678
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L678
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L678
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L245
.L678:
	movss	xmm1, DWORD PTR _x_s7_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L679
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L679
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L679
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L245
.L679:
	movss	xmm1, DWORD PTR _x_s7_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L680
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	je	.L680
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L680
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L245
.L680:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L681
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s7_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s7_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s7_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s7_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L681:
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L685
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L685
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L685
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s7_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s7_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L685
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L685
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s7_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s7_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L685
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L688
.L685:
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L688
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L245
.L688:
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L690
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L690
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L690
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L690
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L690
	movss	xmm0, DWORD PTR _x_s7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L690
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L690
	movss	xmm0, DWORD PTR _x_s7_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L690
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L690
	movss	xmm0, DWORD PTR s7_z[rip]
	movss	xmm1, DWORD PTR _x_s7_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L690
	ucomiss	xmm0, xmm1
	je	.L693
.L690:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L693
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L693
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L693
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L693
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L693
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L245
.L693:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L695
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L695
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L696
.L695:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L697
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L697
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L697
.L696:
	movss	xmm0, DWORD PTR s7_x[rip]
	movss	xmm1, DWORD PTR _x_s7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L697
	ucomiss	xmm0, xmm1
	jne	.L697
	movss	xmm0, DWORD PTR s7_z[rip]
	movss	xmm1, DWORD PTR _x_s7_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L697
	ucomiss	xmm0, xmm1
	jne	.L697
	movss	xmm0, DWORD PTR s7_y[rip]
	movss	xmm1, DWORD PTR _x_s7_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L697
	ucomiss	xmm0, xmm1
	je	.L700
.L697:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L700
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L700
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L700
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L700
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L700
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L245
.L700:
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L702
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L702
	movss	xmm0, DWORD PTR s7_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L702
	movss	xmm0, DWORD PTR s7_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L704
.L702:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L704
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L704
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L705
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L704
.L705:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L704
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L704
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L704
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L245
.L704:
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L706
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L706
	movss	xmm0, DWORD PTR s7_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L706
	movss	xmm0, DWORD PTR s7_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L708
.L706:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L708
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L708
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L709
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L708
.L709:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L708
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L708
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L708
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L708
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L708
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L245
.L708:
	movss	xmm0, DWORD PTR s7_z[rip]
	movss	xmm1, DWORD PTR _x_s7_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L710
	ucomiss	xmm0, xmm1
	jne	.L710
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L710
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L710
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L710
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L710
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L710
	movss	xmm0, DWORD PTR s7_x[rip]
	movss	xmm1, DWORD PTR _x_s7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L710
	ucomiss	xmm0, xmm1
	jne	.L710
	movss	xmm0, DWORD PTR s7_y[rip]
	movss	xmm1, DWORD PTR _x_s7_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L710
	ucomiss	xmm0, xmm1
	je	.L713
.L710:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L713
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L713
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L713
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L713
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L713
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L245
.L713:
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L715
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L715
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	je	.L715
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L715
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L715
	movss	xmm0, DWORD PTR _x_s7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L715
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L715
	movss	xmm0, DWORD PTR s7_y[rip]
	movss	xmm1, DWORD PTR _x_s7_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L715
	ucomiss	xmm0, xmm1
	jne	.L715
	movss	xmm0, DWORD PTR _x_s7_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L715
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L718
.L715:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	jne	.L718
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L718
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L718
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L718
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L718
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L245
.L718:
	movss	xmm0, DWORD PTR s7_x[rip]
	movss	xmm1, DWORD PTR _x_s7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L720
	ucomiss	xmm0, xmm1
	jne	.L720
	movss	xmm0, DWORD PTR s7_y[rip]
	movss	xmm1, DWORD PTR _x_s7_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L720
	ucomiss	xmm0, xmm1
	jne	.L720
	movss	xmm0, DWORD PTR s7_z[rip]
	movss	xmm1, DWORD PTR _x_s7_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L720
	ucomiss	xmm0, xmm1
	jne	.L720
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L724
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L724
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L725
.L724:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	je	.L720
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L720
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L725
.L720:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	je	.L725
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L725
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L725
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L725
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L725
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L245
.L725:
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L726
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L726
	movss	xmm0, DWORD PTR s7_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L726
	movss	xmm0, DWORD PTR s7_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L728
.L726:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L728
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L728
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L729
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L728
.L729:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L728
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L728
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L245
.L728:
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L730
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L730
	movss	xmm0, DWORD PTR s7_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L730
	movss	xmm0, DWORD PTR s7_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L732
.L730:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L732
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L732
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L733
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L732
.L733:
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L732
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L732
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L732
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	je	.L732
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L732
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L245
.L732:
	movss	xmm0, DWORD PTR s7_z[rip]
	movss	xmm1, DWORD PTR _x_s7_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L734
	ucomiss	xmm0, xmm1
	jne	.L734
	movss	xmm0, DWORD PTR s7_x[rip]
	movss	xmm1, DWORD PTR _x_s7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L734
	ucomiss	xmm0, xmm1
	jne	.L734
	movss	xmm0, DWORD PTR s7_y[rip]
	movss	xmm1, DWORD PTR _x_s7_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L734
	ucomiss	xmm0, xmm1
	jne	.L734
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L734
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L734
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	test	al, al
	jne	.L734
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L734
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L738
.L734:
	movzx	eax, BYTE PTR s7_l2[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L738
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L738
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L738
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L245
.L738:
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	jne	.L739
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L740
.L739:
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L740
.L741:
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L742
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	je	.L740
.L742:
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L245
.L740:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L743
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L743
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L744
.L743:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L745
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L745
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L744
.L745:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L746
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L746
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L744
.L746:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L747
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L744
.L747:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	je	.L748
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L748
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L744
.L748:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L245
.L744:
	movss	xmm1, DWORD PTR _x_s6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L749
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L749
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L749
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L245
.L749:
	movss	xmm1, DWORD PTR _x_s6_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L750
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L750
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L750
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L245
.L750:
	movss	xmm1, DWORD PTR _x_s6_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L751
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	je	.L751
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L751
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L245
.L751:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L752
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s6_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s6_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s6_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s6_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L752:
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L756
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L756
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L756
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L756
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L756
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s6_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s6_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L756
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L756
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s6_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s6_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L756
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L759
.L756:
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L759
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L245
.L759:
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L761
	movss	xmm0, DWORD PTR _x_s6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L761
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L761
	movss	xmm0, DWORD PTR _x_s6_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L761
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L761
	movss	xmm0, DWORD PTR s6_z[rip]
	movss	xmm1, DWORD PTR _x_s6_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L761
	ucomiss	xmm0, xmm1
	je	.L764
.L761:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L764
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L764
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L764
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L764
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L764
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L245
.L764:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L766
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L766
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L767
.L766:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L768
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L768
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L768
.L767:
	movss	xmm0, DWORD PTR s6_x[rip]
	movss	xmm1, DWORD PTR _x_s6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L768
	ucomiss	xmm0, xmm1
	jne	.L768
	movss	xmm0, DWORD PTR s6_z[rip]
	movss	xmm1, DWORD PTR _x_s6_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L768
	ucomiss	xmm0, xmm1
	jne	.L768
	movss	xmm0, DWORD PTR s6_y[rip]
	movss	xmm1, DWORD PTR _x_s6_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L768
	ucomiss	xmm0, xmm1
	je	.L771
.L768:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L771
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L771
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L771
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L771
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L771
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L245
.L771:
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L773
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L773
	movss	xmm0, DWORD PTR s6_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L773
	movss	xmm0, DWORD PTR s6_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L775
.L773:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L775
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L775
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L776
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L775
.L776:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L775
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L775
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L775
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L775
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L775
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L245
.L775:
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L777
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L777
	movss	xmm0, DWORD PTR s6_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L777
	movss	xmm0, DWORD PTR s6_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L779
.L777:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L779
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L779
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L780
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L779
.L780:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L779
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L779
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L779
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L779
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L779
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L245
.L779:
	movss	xmm0, DWORD PTR s6_z[rip]
	movss	xmm1, DWORD PTR _x_s6_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L781
	ucomiss	xmm0, xmm1
	jne	.L781
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L781
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L781
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L781
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L781
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L781
	movss	xmm0, DWORD PTR s6_x[rip]
	movss	xmm1, DWORD PTR _x_s6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L781
	ucomiss	xmm0, xmm1
	jne	.L781
	movss	xmm0, DWORD PTR s6_y[rip]
	movss	xmm1, DWORD PTR _x_s6_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L781
	ucomiss	xmm0, xmm1
	je	.L784
.L781:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L784
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L784
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L784
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L784
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L784
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L245
.L784:
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L786
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L786
	movss	xmm0, DWORD PTR _x_s6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L786
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L786
	movss	xmm0, DWORD PTR s6_y[rip]
	movss	xmm1, DWORD PTR _x_s6_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L786
	ucomiss	xmm0, xmm1
	jne	.L786
	movss	xmm0, DWORD PTR _x_s6_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L786
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L789
.L786:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	jne	.L789
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L789
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L789
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L789
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L789
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L245
.L789:
	movss	xmm0, DWORD PTR s6_x[rip]
	movss	xmm1, DWORD PTR _x_s6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L791
	ucomiss	xmm0, xmm1
	jne	.L791
	movss	xmm0, DWORD PTR s6_y[rip]
	movss	xmm1, DWORD PTR _x_s6_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L791
	ucomiss	xmm0, xmm1
	jne	.L791
	movss	xmm0, DWORD PTR s6_z[rip]
	movss	xmm1, DWORD PTR _x_s6_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L791
	ucomiss	xmm0, xmm1
	jne	.L791
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L795
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L795
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L796
.L795:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	je	.L791
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L791
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L796
.L791:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	je	.L796
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L796
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L796
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L796
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L796
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L245
.L796:
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L797
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L797
	movss	xmm0, DWORD PTR s6_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L797
	movss	xmm0, DWORD PTR s6_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L799
.L797:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L799
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L799
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L800
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L799
.L800:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	je	.L799
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L799
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L799
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	je	.L799
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L799
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L245
.L799:
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L801
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L801
	movss	xmm0, DWORD PTR s6_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L801
	movss	xmm0, DWORD PTR s6_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L803
.L801:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L803
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L803
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L804
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L803
.L804:
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	je	.L803
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L245
.L803:
	movss	xmm0, DWORD PTR s6_z[rip]
	movss	xmm1, DWORD PTR _x_s6_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L805
	ucomiss	xmm0, xmm1
	jne	.L805
	movss	xmm0, DWORD PTR s6_x[rip]
	movss	xmm1, DWORD PTR _x_s6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L805
	ucomiss	xmm0, xmm1
	jne	.L805
	movss	xmm0, DWORD PTR s6_y[rip]
	movss	xmm1, DWORD PTR _x_s6_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L805
	ucomiss	xmm0, xmm1
	jne	.L805
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L805
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L805
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	test	al, al
	jne	.L805
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L805
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L809
.L805:
	movzx	eax, BYTE PTR s6_l2[rip]
	test	al, al
	je	.L809
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L809
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L809
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L809
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L809
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L245
.L809:
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	jne	.L810
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L811
.L810:
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	je	.L812
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L811
.L812:
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L813
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	je	.L811
.L813:
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L245
.L811:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L814
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L814
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L815
.L814:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L816
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L816
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L815
.L816:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L817
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L817
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L815
.L817:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L818
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L818
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L815
.L818:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	je	.L819
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L819
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L815
.L819:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L245
.L815:
	movss	xmm1, DWORD PTR _x_s5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L820
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L820
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L820
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L245
.L820:
	movss	xmm1, DWORD PTR _x_s5_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L821
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L821
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L821
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L245
.L821:
	movss	xmm1, DWORD PTR _x_s5_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L822
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L245
.L822:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L823
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s5_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s5_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s5_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s5_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L823:
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L827
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L827
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L827
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L827
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L827
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s5_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s5_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L827
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L827
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s5_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s5_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L827
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L830
.L827:
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L830
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L245
.L830:
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L832
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L832
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L832
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L832
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L832
	movss	xmm0, DWORD PTR _x_s5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L832
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L832
	movss	xmm0, DWORD PTR _x_s5_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L832
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L832
	movss	xmm0, DWORD PTR s5_z[rip]
	movss	xmm1, DWORD PTR _x_s5_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L832
	ucomiss	xmm0, xmm1
	je	.L835
.L832:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L835
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L835
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L835
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L835
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L835
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L245
.L835:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L837
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L837
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L838
.L837:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L839
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L839
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L839
.L838:
	movss	xmm0, DWORD PTR s5_x[rip]
	movss	xmm1, DWORD PTR _x_s5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L839
	ucomiss	xmm0, xmm1
	jne	.L839
	movss	xmm0, DWORD PTR s5_z[rip]
	movss	xmm1, DWORD PTR _x_s5_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L839
	ucomiss	xmm0, xmm1
	jne	.L839
	movss	xmm0, DWORD PTR s5_y[rip]
	movss	xmm1, DWORD PTR _x_s5_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L839
	ucomiss	xmm0, xmm1
	je	.L842
.L839:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L842
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L842
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L842
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L842
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L842
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L245
.L842:
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L844
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L844
	movss	xmm0, DWORD PTR s5_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L844
	movss	xmm0, DWORD PTR s5_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L846
.L844:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L846
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L846
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L847
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L846
.L847:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L846
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L846
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L846
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L846
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L846
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L245
.L846:
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L848
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L848
	movss	xmm0, DWORD PTR s5_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L848
	movss	xmm0, DWORD PTR s5_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L850
.L848:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L850
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L850
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L851
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L850
.L851:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L850
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L850
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L850
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L850
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L850
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L245
.L850:
	movss	xmm0, DWORD PTR s5_z[rip]
	movss	xmm1, DWORD PTR _x_s5_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L852
	ucomiss	xmm0, xmm1
	jne	.L852
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L852
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L852
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L852
	movss	xmm0, DWORD PTR s5_x[rip]
	movss	xmm1, DWORD PTR _x_s5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L852
	ucomiss	xmm0, xmm1
	jne	.L852
	movss	xmm0, DWORD PTR s5_y[rip]
	movss	xmm1, DWORD PTR _x_s5_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L852
	ucomiss	xmm0, xmm1
	je	.L855
.L852:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L855
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L855
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L855
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L855
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L855
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L245
.L855:
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L857
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L857
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	je	.L857
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L857
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L857
	movss	xmm0, DWORD PTR _x_s5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L857
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L857
	movss	xmm0, DWORD PTR s5_y[rip]
	movss	xmm1, DWORD PTR _x_s5_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L857
	ucomiss	xmm0, xmm1
	jne	.L857
	movss	xmm0, DWORD PTR _x_s5_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L857
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L860
.L857:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	jne	.L860
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L860
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L860
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L860
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L860
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L245
.L860:
	movss	xmm0, DWORD PTR s5_x[rip]
	movss	xmm1, DWORD PTR _x_s5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L862
	ucomiss	xmm0, xmm1
	jne	.L862
	movss	xmm0, DWORD PTR s5_y[rip]
	movss	xmm1, DWORD PTR _x_s5_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L862
	ucomiss	xmm0, xmm1
	jne	.L862
	movss	xmm0, DWORD PTR s5_z[rip]
	movss	xmm1, DWORD PTR _x_s5_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L862
	ucomiss	xmm0, xmm1
	jne	.L862
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L866
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L866
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L867
.L866:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	je	.L862
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L862
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L867
.L862:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	je	.L867
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L867
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L867
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L867
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L867
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L245
.L867:
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L868
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L868
	movss	xmm0, DWORD PTR s5_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L868
	movss	xmm0, DWORD PTR s5_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L870
.L868:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L870
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L870
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L871
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L870
.L871:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	je	.L870
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L870
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L870
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	je	.L870
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L870
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L245
.L870:
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L872
	movss	xmm0, DWORD PTR s5_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L872
	movss	xmm0, DWORD PTR s5_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L874
.L872:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L874
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L874
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L875
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L874
.L875:
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L874
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L874
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L874
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	je	.L874
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L874
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L245
.L874:
	movss	xmm0, DWORD PTR s5_z[rip]
	movss	xmm1, DWORD PTR _x_s5_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L876
	ucomiss	xmm0, xmm1
	jne	.L876
	movss	xmm0, DWORD PTR s5_x[rip]
	movss	xmm1, DWORD PTR _x_s5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L876
	ucomiss	xmm0, xmm1
	jne	.L876
	movss	xmm0, DWORD PTR s5_y[rip]
	movss	xmm1, DWORD PTR _x_s5_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L876
	ucomiss	xmm0, xmm1
	jne	.L876
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L876
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L876
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	test	al, al
	jne	.L876
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L876
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L880
.L876:
	movzx	eax, BYTE PTR s5_l2[rip]
	test	al, al
	je	.L880
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L880
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L880
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L880
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L880
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L245
.L880:
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	jne	.L881
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L882
.L881:
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	je	.L883
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L882
.L883:
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L884
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	je	.L882
.L884:
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L245
.L882:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L885
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L885
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L886
.L885:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L887
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L887
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L886
.L887:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L888
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L888
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L886
.L888:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L889
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L889
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L886
.L889:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	je	.L890
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L890
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L886
.L890:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L245
.L886:
	movss	xmm1, DWORD PTR _x_s4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L891
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L891
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L891
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L245
.L891:
	movss	xmm1, DWORD PTR _x_s4_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L892
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L892
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L892
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L245
.L892:
	movss	xmm1, DWORD PTR _x_s4_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L893
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	je	.L893
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L893
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L245
.L893:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L894
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s4_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s4_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s4_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s4_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L894:
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L898
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L898
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L898
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L898
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L898
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s4_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s4_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L898
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L898
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s4_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s4_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L898
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L901
.L898:
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L901
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L245
.L901:
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L903
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L903
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L903
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L903
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L903
	movss	xmm0, DWORD PTR _x_s4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L903
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L903
	movss	xmm0, DWORD PTR _x_s4_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L903
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L903
	movss	xmm0, DWORD PTR s4_z[rip]
	movss	xmm1, DWORD PTR _x_s4_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L903
	ucomiss	xmm0, xmm1
	je	.L906
.L903:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L906
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L906
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L906
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L906
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L906
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L245
.L906:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L908
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L908
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L909
.L908:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L910
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L910
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L910
.L909:
	movss	xmm0, DWORD PTR s4_x[rip]
	movss	xmm1, DWORD PTR _x_s4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L910
	ucomiss	xmm0, xmm1
	jne	.L910
	movss	xmm0, DWORD PTR s4_z[rip]
	movss	xmm1, DWORD PTR _x_s4_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L910
	ucomiss	xmm0, xmm1
	jne	.L910
	movss	xmm0, DWORD PTR s4_y[rip]
	movss	xmm1, DWORD PTR _x_s4_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L910
	ucomiss	xmm0, xmm1
	je	.L913
.L910:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L913
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L913
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L913
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L913
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L913
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L245
.L913:
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L915
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L915
	movss	xmm0, DWORD PTR s4_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L915
	movss	xmm0, DWORD PTR s4_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L917
.L915:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L917
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L917
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L918
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L917
.L918:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L917
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L917
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L917
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L917
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L917
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L245
.L917:
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L919
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L919
	movss	xmm0, DWORD PTR s4_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L919
	movss	xmm0, DWORD PTR s4_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L921
.L919:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L921
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L921
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L922
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L921
.L922:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L921
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L921
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L921
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L245
.L921:
	movss	xmm0, DWORD PTR s4_z[rip]
	movss	xmm1, DWORD PTR _x_s4_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L923
	ucomiss	xmm0, xmm1
	jne	.L923
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L923
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L923
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L923
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L923
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L923
	movss	xmm0, DWORD PTR s4_x[rip]
	movss	xmm1, DWORD PTR _x_s4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L923
	ucomiss	xmm0, xmm1
	jne	.L923
	movss	xmm0, DWORD PTR s4_y[rip]
	movss	xmm1, DWORD PTR _x_s4_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L923
	ucomiss	xmm0, xmm1
	je	.L926
.L923:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L926
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L926
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L926
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L926
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L926
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L245
.L926:
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L928
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L928
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	je	.L928
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L928
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L928
	movss	xmm0, DWORD PTR _x_s4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L928
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L928
	movss	xmm0, DWORD PTR s4_y[rip]
	movss	xmm1, DWORD PTR _x_s4_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L928
	ucomiss	xmm0, xmm1
	jne	.L928
	movss	xmm0, DWORD PTR _x_s4_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L928
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L931
.L928:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	jne	.L931
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L931
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L931
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L931
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L931
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L245
.L931:
	movss	xmm0, DWORD PTR s4_x[rip]
	movss	xmm1, DWORD PTR _x_s4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L933
	ucomiss	xmm0, xmm1
	jne	.L933
	movss	xmm0, DWORD PTR s4_y[rip]
	movss	xmm1, DWORD PTR _x_s4_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L933
	ucomiss	xmm0, xmm1
	jne	.L933
	movss	xmm0, DWORD PTR s4_z[rip]
	movss	xmm1, DWORD PTR _x_s4_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L933
	ucomiss	xmm0, xmm1
	jne	.L933
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L937
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L937
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L938
.L937:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	je	.L933
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L933
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L938
.L933:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	je	.L938
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L938
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L938
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L938
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L938
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L245
.L938:
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L939
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L939
	movss	xmm0, DWORD PTR s4_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L939
	movss	xmm0, DWORD PTR s4_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L941
.L939:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L941
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L941
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L942
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L941
.L942:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	je	.L941
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	je	.L941
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L941
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L245
.L941:
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L943
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L943
	movss	xmm0, DWORD PTR s4_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L943
	movss	xmm0, DWORD PTR s4_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L945
.L943:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L945
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L945
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L946
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L945
.L946:
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L945
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L945
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L945
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	je	.L945
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L945
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L245
.L945:
	movss	xmm0, DWORD PTR s4_z[rip]
	movss	xmm1, DWORD PTR _x_s4_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L947
	ucomiss	xmm0, xmm1
	jne	.L947
	movss	xmm0, DWORD PTR s4_x[rip]
	movss	xmm1, DWORD PTR _x_s4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L947
	ucomiss	xmm0, xmm1
	jne	.L947
	movss	xmm0, DWORD PTR s4_y[rip]
	movss	xmm1, DWORD PTR _x_s4_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L947
	ucomiss	xmm0, xmm1
	jne	.L947
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L947
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L947
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	test	al, al
	jne	.L947
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L947
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L951
.L947:
	movzx	eax, BYTE PTR s4_l2[rip]
	test	al, al
	je	.L951
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L951
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L951
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L951
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L951
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L245
.L951:
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	jne	.L952
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L953
.L952:
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	je	.L954
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L953
.L954:
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L955
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	je	.L953
.L955:
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L245
.L953:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L956
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L956
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L957
.L956:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L958
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L958
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L957
.L958:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L959
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L959
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L957
.L959:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L960
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L960
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L957
.L960:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	je	.L961
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L961
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L957
.L961:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L245
.L957:
	movss	xmm1, DWORD PTR _x_s3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L962
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L962
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L962
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L245
.L962:
	movss	xmm1, DWORD PTR _x_s3_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L963
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L963
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L963
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L245
.L963:
	movss	xmm1, DWORD PTR _x_s3_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L964
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	je	.L964
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L964
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L245
.L964:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L965
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s3_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s3_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s3_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s3_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L965:
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L969
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L969
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L969
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L969
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L969
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s3_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s3_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L969
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L969
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s3_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s3_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L969
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L972
.L969:
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L972
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L245
.L972:
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L974
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L974
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L974
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L974
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L974
	movss	xmm0, DWORD PTR _x_s3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L974
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L974
	movss	xmm0, DWORD PTR _x_s3_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L974
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L974
	movss	xmm0, DWORD PTR s3_z[rip]
	movss	xmm1, DWORD PTR _x_s3_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L974
	ucomiss	xmm0, xmm1
	je	.L977
.L974:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L977
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L977
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L977
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L245
.L977:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L979
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L979
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L980
.L979:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L981
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L981
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L981
.L980:
	movss	xmm0, DWORD PTR s3_x[rip]
	movss	xmm1, DWORD PTR _x_s3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L981
	ucomiss	xmm0, xmm1
	jne	.L981
	movss	xmm0, DWORD PTR s3_z[rip]
	movss	xmm1, DWORD PTR _x_s3_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L981
	ucomiss	xmm0, xmm1
	jne	.L981
	movss	xmm0, DWORD PTR s3_y[rip]
	movss	xmm1, DWORD PTR _x_s3_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L981
	ucomiss	xmm0, xmm1
	je	.L984
.L981:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L984
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L984
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L984
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L984
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L984
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L245
.L984:
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L986
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L986
	movss	xmm0, DWORD PTR s3_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L986
	movss	xmm0, DWORD PTR s3_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L988
.L986:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L988
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L988
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L989
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L988
.L989:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L988
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L988
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L988
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L988
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L988
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L245
.L988:
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L990
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L990
	movss	xmm0, DWORD PTR s3_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L990
	movss	xmm0, DWORD PTR s3_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L992
.L990:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L992
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L992
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L993
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L992
.L993:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L992
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L992
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L992
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L992
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L992
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L245
.L992:
	movss	xmm0, DWORD PTR s3_z[rip]
	movss	xmm1, DWORD PTR _x_s3_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L994
	ucomiss	xmm0, xmm1
	jne	.L994
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L994
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L994
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L994
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L994
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L994
	movss	xmm0, DWORD PTR s3_x[rip]
	movss	xmm1, DWORD PTR _x_s3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L994
	ucomiss	xmm0, xmm1
	jne	.L994
	movss	xmm0, DWORD PTR s3_y[rip]
	movss	xmm1, DWORD PTR _x_s3_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L994
	ucomiss	xmm0, xmm1
	je	.L997
.L994:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L997
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L997
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L997
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L997
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L997
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L245
.L997:
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L999
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L999
	movss	xmm0, DWORD PTR _x_s3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L999
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L999
	movss	xmm0, DWORD PTR s3_y[rip]
	movss	xmm1, DWORD PTR _x_s3_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L999
	ucomiss	xmm0, xmm1
	jne	.L999
	movss	xmm0, DWORD PTR _x_s3_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L999
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1002
.L999:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	jne	.L1002
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L1002
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L1002
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1002
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1002
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L245
.L1002:
	movss	xmm0, DWORD PTR s3_x[rip]
	movss	xmm1, DWORD PTR _x_s3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1004
	ucomiss	xmm0, xmm1
	jne	.L1004
	movss	xmm0, DWORD PTR s3_y[rip]
	movss	xmm1, DWORD PTR _x_s3_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1004
	ucomiss	xmm0, xmm1
	jne	.L1004
	movss	xmm0, DWORD PTR s3_z[rip]
	movss	xmm1, DWORD PTR _x_s3_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1004
	ucomiss	xmm0, xmm1
	jne	.L1004
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L1008
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L1008
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L1009
.L1008:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	je	.L1004
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L1004
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L1009
.L1004:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	je	.L1009
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L1009
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L1009
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1009
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1009
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L245
.L1009:
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L1010
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L1010
	movss	xmm0, DWORD PTR s3_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1010
	movss	xmm0, DWORD PTR s3_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1012
.L1010:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1012
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1012
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1013
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1012
.L1013:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	je	.L1012
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L1012
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L1012
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	je	.L1012
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L1012
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L245
.L1012:
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1014
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1014
	movss	xmm0, DWORD PTR s3_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1014
	movss	xmm0, DWORD PTR s3_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L1016
.L1014:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1016
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1016
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1017
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1016
.L1017:
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L1016
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L1016
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L1016
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	je	.L1016
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L1016
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L245
.L1016:
	movss	xmm0, DWORD PTR s3_z[rip]
	movss	xmm1, DWORD PTR _x_s3_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1018
	ucomiss	xmm0, xmm1
	jne	.L1018
	movss	xmm0, DWORD PTR s3_x[rip]
	movss	xmm1, DWORD PTR _x_s3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1018
	ucomiss	xmm0, xmm1
	jne	.L1018
	movss	xmm0, DWORD PTR s3_y[rip]
	movss	xmm1, DWORD PTR _x_s3_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1018
	ucomiss	xmm0, xmm1
	jne	.L1018
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1018
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1018
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	test	al, al
	jne	.L1018
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L1018
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L1022
.L1018:
	movzx	eax, BYTE PTR s3_l2[rip]
	test	al, al
	je	.L1022
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L1022
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L1022
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1022
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1022
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L245
.L1022:
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	jne	.L1023
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L1024
.L1023:
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	je	.L1025
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L1024
.L1025:
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L1026
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	je	.L1024
.L1026:
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L245
.L1024:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1027
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L1027
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1028
.L1027:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1029
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1028
.L1029:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1030
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1030
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1028
.L1030:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1031
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1031
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L1028
.L1031:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	je	.L1032
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L1032
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1028
.L1032:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L245
.L1028:
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L1033
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1033
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1033
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L245
.L1033:
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L1034
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1034
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1034
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L245
.L1034:
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L1035
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	je	.L1035
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1035
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L245
.L1035:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L1036
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s2_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s2_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s2_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s2_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L1036:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1040
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1040
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1040
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1040
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1040
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s2_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s2_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1040
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1040
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s2_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s2_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1040
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L1043
.L1040:
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1043
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L245
.L1043:
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1045
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1045
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1045
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1045
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L1045
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1045
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1045
	movss	xmm0, DWORD PTR _x_s2_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1045
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1045
	movss	xmm0, DWORD PTR s2_z[rip]
	movss	xmm1, DWORD PTR _x_s2_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1045
	ucomiss	xmm0, xmm1
	je	.L1048
.L1045:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L1048
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L1048
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L1048
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1048
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1048
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L245
.L1048:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1050
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1050
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1051
.L1050:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1052
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1052
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1052
.L1051:
	movss	xmm0, DWORD PTR s2_x[rip]
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1052
	ucomiss	xmm0, xmm1
	jne	.L1052
	movss	xmm0, DWORD PTR s2_z[rip]
	movss	xmm1, DWORD PTR _x_s2_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1052
	ucomiss	xmm0, xmm1
	jne	.L1052
	movss	xmm0, DWORD PTR s2_y[rip]
	movss	xmm1, DWORD PTR _x_s2_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1052
	ucomiss	xmm0, xmm1
	je	.L1055
.L1052:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L1055
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L1055
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L1055
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1055
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1055
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L245
.L1055:
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1057
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L1057
	movss	xmm0, DWORD PTR s2_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1057
	movss	xmm0, DWORD PTR s2_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1059
.L1057:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1059
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1059
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1060
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1059
.L1060:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L1059
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L1059
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L1059
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1059
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1059
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L245
.L1059:
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1061
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1061
	movss	xmm0, DWORD PTR s2_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1061
	movss	xmm0, DWORD PTR s2_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L1063
.L1061:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1063
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1063
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1064
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1063
.L1064:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L1063
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L1063
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L1063
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1063
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1063
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L245
.L1063:
	movss	xmm0, DWORD PTR s2_z[rip]
	movss	xmm1, DWORD PTR _x_s2_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1065
	ucomiss	xmm0, xmm1
	jne	.L1065
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1065
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1065
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1065
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1065
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1065
	movss	xmm0, DWORD PTR s2_x[rip]
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1065
	ucomiss	xmm0, xmm1
	jne	.L1065
	movss	xmm0, DWORD PTR s2_y[rip]
	movss	xmm1, DWORD PTR _x_s2_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1065
	ucomiss	xmm0, xmm1
	je	.L1068
.L1065:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L1068
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L1068
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L1068
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1068
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1068
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L245
.L1068:
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1070
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1070
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	je	.L1070
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L1070
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L1070
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1070
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1070
	movss	xmm0, DWORD PTR s2_y[rip]
	movss	xmm1, DWORD PTR _x_s2_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1070
	ucomiss	xmm0, xmm1
	jne	.L1070
	movss	xmm0, DWORD PTR _x_s2_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1070
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1073
.L1070:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	jne	.L1073
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L1073
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L1073
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1073
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1073
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L245
.L1073:
	movss	xmm0, DWORD PTR s2_x[rip]
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1075
	ucomiss	xmm0, xmm1
	jne	.L1075
	movss	xmm0, DWORD PTR s2_y[rip]
	movss	xmm1, DWORD PTR _x_s2_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1075
	ucomiss	xmm0, xmm1
	jne	.L1075
	movss	xmm0, DWORD PTR s2_z[rip]
	movss	xmm1, DWORD PTR _x_s2_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1075
	ucomiss	xmm0, xmm1
	jne	.L1075
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1079
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L1079
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1080
.L1079:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	je	.L1075
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1075
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1080
.L1075:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	je	.L1080
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L1080
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L1080
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1080
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1080
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L245
.L1080:
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1081
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L1081
	movss	xmm0, DWORD PTR s2_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1081
	movss	xmm0, DWORD PTR s2_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1083
.L1081:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1083
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1083
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1084
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1083
.L1084:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	je	.L1083
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L1083
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L1083
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	je	.L1083
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L1083
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L245
.L1083:
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1085
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1085
	movss	xmm0, DWORD PTR s2_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1085
	movss	xmm0, DWORD PTR s2_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L1087
.L1085:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1087
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1087
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1088
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1087
.L1088:
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1087
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L1087
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L1087
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	je	.L1087
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L1087
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L245
.L1087:
	movss	xmm0, DWORD PTR s2_z[rip]
	movss	xmm1, DWORD PTR _x_s2_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1089
	ucomiss	xmm0, xmm1
	jne	.L1089
	movss	xmm0, DWORD PTR s2_x[rip]
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1089
	ucomiss	xmm0, xmm1
	jne	.L1089
	movss	xmm0, DWORD PTR s2_y[rip]
	movss	xmm1, DWORD PTR _x_s2_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1089
	ucomiss	xmm0, xmm1
	jne	.L1089
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1089
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1089
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	test	al, al
	jne	.L1089
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L1089
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L1093
.L1089:
	movzx	eax, BYTE PTR s2_l2[rip]
	test	al, al
	je	.L1093
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L1093
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L1093
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1093
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1093
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L245
.L1093:
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	jne	.L1094
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L1095
.L1094:
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	je	.L1096
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L1095
.L1096:
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L1097
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	je	.L1095
.L1097:
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L245
.L1095:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1098
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L1098
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1099
.L1098:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1100
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1100
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1099
.L1100:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1101
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1101
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1099
.L1101:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1102
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1102
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L1099
.L1102:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	je	.L1103
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L1103
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1099
.L1103:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L245
.L1099:
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L1104
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1104
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1104
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L245
.L1104:
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L1105
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1105
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1105
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L245
.L1105:
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L1106
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	je	.L1106
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1106
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L245
.L1106:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L1107
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s1_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s1_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s1_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s1_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L1107:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1111
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1111
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1111
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1111
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1111
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s1_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s1_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1111
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1111
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s1_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s1_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1111
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L1114
.L1111:
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1114
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L245
.L1114:
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L1116
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1116
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1116
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1116
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L1116
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1116
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1116
	movss	xmm0, DWORD PTR _x_s1_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1116
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1116
	movss	xmm0, DWORD PTR s1_z[rip]
	movss	xmm1, DWORD PTR _x_s1_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1116
	ucomiss	xmm0, xmm1
	je	.L1119
.L1116:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L1119
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L1119
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L1119
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1119
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1119
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L245
.L1119:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1121
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1121
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1122
.L1121:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1123
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1123
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1123
.L1122:
	movss	xmm0, DWORD PTR s1_x[rip]
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1123
	ucomiss	xmm0, xmm1
	jne	.L1123
	movss	xmm0, DWORD PTR s1_z[rip]
	movss	xmm1, DWORD PTR _x_s1_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1123
	ucomiss	xmm0, xmm1
	jne	.L1123
	movss	xmm0, DWORD PTR s1_y[rip]
	movss	xmm1, DWORD PTR _x_s1_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1123
	ucomiss	xmm0, xmm1
	je	.L1126
.L1123:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L1126
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L1126
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L1126
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1126
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1126
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L245
.L1126:
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L1128
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L1128
	movss	xmm0, DWORD PTR s1_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1128
	movss	xmm0, DWORD PTR s1_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1130
.L1128:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1130
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1130
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1131
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1130
.L1131:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L1130
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L1130
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L1130
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1130
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1130
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L245
.L1130:
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1132
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1132
	movss	xmm0, DWORD PTR s1_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1132
	movss	xmm0, DWORD PTR s1_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L1134
.L1132:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1134
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1134
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1135
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1134
.L1135:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L1134
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L1134
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L1134
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1134
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1134
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L245
.L1134:
	movss	xmm0, DWORD PTR s1_z[rip]
	movss	xmm1, DWORD PTR _x_s1_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1136
	ucomiss	xmm0, xmm1
	jne	.L1136
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1136
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1136
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1136
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1136
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1136
	movss	xmm0, DWORD PTR s1_x[rip]
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1136
	ucomiss	xmm0, xmm1
	jne	.L1136
	movss	xmm0, DWORD PTR s1_y[rip]
	movss	xmm1, DWORD PTR _x_s1_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1136
	ucomiss	xmm0, xmm1
	je	.L1139
.L1136:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L1139
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L1139
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L1139
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1139
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1139
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L245
.L1139:
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L1141
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1141
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	je	.L1141
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L1141
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L1141
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1141
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1141
	movss	xmm0, DWORD PTR s1_y[rip]
	movss	xmm1, DWORD PTR _x_s1_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1141
	ucomiss	xmm0, xmm1
	jne	.L1141
	movss	xmm0, DWORD PTR _x_s1_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1141
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1144
.L1141:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	jne	.L1144
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L1144
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L1144
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1144
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1144
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L245
.L1144:
	movss	xmm0, DWORD PTR s1_x[rip]
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1146
	ucomiss	xmm0, xmm1
	jne	.L1146
	movss	xmm0, DWORD PTR s1_y[rip]
	movss	xmm1, DWORD PTR _x_s1_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1146
	ucomiss	xmm0, xmm1
	jne	.L1146
	movss	xmm0, DWORD PTR s1_z[rip]
	movss	xmm1, DWORD PTR _x_s1_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1146
	ucomiss	xmm0, xmm1
	jne	.L1146
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1150
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L1150
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1151
.L1150:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	je	.L1146
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1146
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1151
.L1146:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	je	.L1151
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L1151
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L1151
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1151
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1151
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L245
.L1151:
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L1152
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L1152
	movss	xmm0, DWORD PTR s1_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1152
	movss	xmm0, DWORD PTR s1_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1154
.L1152:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1154
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1154
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1155
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1154
.L1155:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	je	.L1154
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L1154
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L1154
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	je	.L1154
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L1154
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L245
.L1154:
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1156
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1156
	movss	xmm0, DWORD PTR s1_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1156
	movss	xmm0, DWORD PTR s1_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L1158
.L1156:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1158
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1158
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1159
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1158
.L1159:
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1158
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L1158
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L1158
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	je	.L1158
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L1158
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L245
.L1158:
	movss	xmm0, DWORD PTR s1_z[rip]
	movss	xmm1, DWORD PTR _x_s1_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1160
	ucomiss	xmm0, xmm1
	jne	.L1160
	movss	xmm0, DWORD PTR s1_x[rip]
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1160
	ucomiss	xmm0, xmm1
	jne	.L1160
	movss	xmm0, DWORD PTR s1_y[rip]
	movss	xmm1, DWORD PTR _x_s1_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1160
	ucomiss	xmm0, xmm1
	jne	.L1160
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1160
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1160
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	test	al, al
	jne	.L1160
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L1160
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L1164
.L1160:
	movzx	eax, BYTE PTR s1_l2[rip]
	test	al, al
	je	.L1164
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L1164
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L1164
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1164
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1164
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L245
.L1164:
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	jne	.L1165
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L1166
.L1165:
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	je	.L1167
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L1166
.L1167:
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L1168
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	je	.L1166
.L1168:
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L245
.L1166:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1169
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L1169
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1170
.L1169:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1171
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1171
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1170
.L1171:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1172
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1172
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1170
.L1172:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1173
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1173
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L1170
.L1173:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	je	.L1174
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L1174
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1170
.L1174:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L245
.L1170:
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jnb	.L1175
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1175
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1175
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L245
.L1175:
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L1176
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1176
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1176
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L245
.L1176:
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L1177
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	je	.L1177
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1177
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L245
.L1177:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L1178
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s0_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s0_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s0_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s0_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L1178:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1182
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1182
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1182
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1182
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1182
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s0_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s0_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1182
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1182
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s0_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s0_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1182
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L1185
.L1182:
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1185
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L245
.L1185:
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1187
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1187
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1187
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1187
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L1187
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1187
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1187
	movss	xmm0, DWORD PTR _x_s0_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1187
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1187
	movss	xmm0, DWORD PTR s0_z[rip]
	movss	xmm1, DWORD PTR _x_s0_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1187
	ucomiss	xmm0, xmm1
	je	.L1190
.L1187:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L1190
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L1190
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L1190
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1190
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1190
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L245
.L1190:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1192
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1192
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1193
.L1192:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1194
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1194
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1194
.L1193:
	movss	xmm0, DWORD PTR s0_x[rip]
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1194
	ucomiss	xmm0, xmm1
	jne	.L1194
	movss	xmm0, DWORD PTR s0_z[rip]
	movss	xmm1, DWORD PTR _x_s0_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1194
	ucomiss	xmm0, xmm1
	jne	.L1194
	movss	xmm0, DWORD PTR s0_y[rip]
	movss	xmm1, DWORD PTR _x_s0_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1194
	ucomiss	xmm0, xmm1
	je	.L1197
.L1194:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L1197
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L1197
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L1197
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1197
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1197
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L245
.L1197:
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1199
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L1199
	movss	xmm0, DWORD PTR s0_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1199
	movss	xmm0, DWORD PTR s0_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1201
.L1199:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1201
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1201
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1202
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1201
.L1202:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L1201
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L1201
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L1201
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1201
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1201
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L245
.L1201:
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1203
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1203
	movss	xmm0, DWORD PTR s0_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1203
	movss	xmm0, DWORD PTR s0_z[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L1205
.L1203:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1205
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1205
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1206
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1205
.L1206:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L1205
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L1205
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L1205
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1205
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1205
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L245
.L1205:
	movss	xmm0, DWORD PTR s0_z[rip]
	movss	xmm1, DWORD PTR _x_s0_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1207
	ucomiss	xmm0, xmm1
	jne	.L1207
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1207
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1207
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1207
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1207
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1207
	movss	xmm0, DWORD PTR s0_x[rip]
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1207
	ucomiss	xmm0, xmm1
	jne	.L1207
	movss	xmm0, DWORD PTR s0_y[rip]
	movss	xmm1, DWORD PTR _x_s0_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1207
	ucomiss	xmm0, xmm1
	je	.L1210
.L1207:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L1210
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L1210
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L1210
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1210
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1210
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L245
.L1210:
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1212
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1212
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	je	.L1212
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L1212
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L1212
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1212
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1212
	movss	xmm0, DWORD PTR s0_y[rip]
	movss	xmm1, DWORD PTR _x_s0_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1212
	ucomiss	xmm0, xmm1
	jne	.L1212
	movss	xmm0, DWORD PTR _x_s0_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1212
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1215
.L1212:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	jne	.L1215
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L1215
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L1215
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1215
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1215
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L245
.L1215:
	movss	xmm0, DWORD PTR s0_x[rip]
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1217
	ucomiss	xmm0, xmm1
	jne	.L1217
	movss	xmm0, DWORD PTR s0_y[rip]
	movss	xmm1, DWORD PTR _x_s0_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1217
	ucomiss	xmm0, xmm1
	jne	.L1217
	movss	xmm0, DWORD PTR s0_z[rip]
	movss	xmm1, DWORD PTR _x_s0_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1217
	ucomiss	xmm0, xmm1
	jne	.L1217
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1221
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L1221
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1222
.L1221:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	je	.L1217
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1217
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1222
.L1217:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	je	.L1222
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L1222
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L1222
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1222
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1222
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L245
.L1222:
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1223
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L1223
	movss	xmm0, DWORD PTR s0_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1223
	movss	xmm0, DWORD PTR s0_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1225
.L1223:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1225
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1225
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1226
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1225
.L1226:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	je	.L1225
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L1225
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L1225
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	je	.L1225
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L1225
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L245
.L1225:
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1227
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1227
	movss	xmm0, DWORD PTR s0_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L1227
	movss	xmm0, DWORD PTR s0_y[rip]
	comiss	xmm0, DWORD PTR .LC2[rip]
	jnb	.L1229
.L1227:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1229
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1229
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1230
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1229
.L1230:
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1229
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L1229
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L1229
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	je	.L1229
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L1229
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L245
.L1229:
	movss	xmm0, DWORD PTR s0_z[rip]
	movss	xmm1, DWORD PTR _x_s0_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L1231
	ucomiss	xmm0, xmm1
	jne	.L1231
	movss	xmm0, DWORD PTR s0_x[rip]
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1231
	ucomiss	xmm0, xmm1
	jne	.L1231
	movss	xmm0, DWORD PTR s0_y[rip]
	movss	xmm1, DWORD PTR _x_s0_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L1231
	ucomiss	xmm0, xmm1
	jne	.L1231
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1231
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1231
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	test	al, al
	jne	.L1231
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L1231
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L1235
.L1231:
	movzx	eax, BYTE PTR s0_l2[rip]
	test	al, al
	je	.L1235
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L1235
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L1235
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1235
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1235
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L245
.L1235:
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	test	eax, eax
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 1
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 2
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 3
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 4
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 5
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 6
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 7
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 8
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 9
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 10
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 11
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 12
	je	.L1236
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	cmp	eax, 13
	jne	.L245
.L1236:
	mov	eax, DWORD PTR _x_r_counter[rip]
	test	eax, eax
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 1
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 2
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 3
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 4
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 5
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 6
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 7
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 8
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 9
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 10
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 11
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 12
	je	.L1237
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	eax, 13
	jne	.L245
.L1237:
	movzx	eax, BYTE PTR _x_r_l[rip]
	test	al, al
	je	.L1238
	movss	xmm1, DWORD PTR _x_r_x[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L245
.L1238:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L1240
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR r_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_r_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR r_l[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_r_l[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L245
	mov	edx, DWORD PTR r_counter[rip]
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	edx, eax
	jne	.L245
.L1240:
	movzx	eax, BYTE PTR r_l[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_r_l[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1242
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR r_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_r_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1242
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1242
	mov	edx, DWORD PTR r_counter[rip]
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	edx, eax
	je	.L1244
.L1242:
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1244
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L245
.L1244:
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1245
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1245
	movss	xmm1, DWORD PTR r_x[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L1245
	movzx	eax, BYTE PTR _x_r_l[rip]
	test	al, al
	jne	.L1245
	mov	edx, DWORD PTR r_evt_id[rip]
	mov	eax, DWORD PTR r_counter[rip]
	cmp	edx, eax
	jne	.L1245
	mov	edx, DWORD PTR r_counter[rip]
	mov	eax, DWORD PTR _x_r_counter[rip]
	cmp	edx, eax
	jne	.L1245
	movss	xmm0, DWORD PTR r_x[rip]
	movss	xmm1, DWORD PTR _x_r_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1245
	ucomiss	xmm0, xmm1
	je	.L1247
.L1245:
	movzx	eax, BYTE PTR r_l[rip]
	test	al, al
	je	.L1247
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1249
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1247
.L1249:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1247
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L245
.L1247:
	movzx	eax, BYTE PTR _x_r_l[rip]
	test	al, al
	je	.L1251
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1251
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1251
	mov	edx, DWORD PTR r_evt_id[rip]
	mov	eax, DWORD PTR r_counter[rip]
	cmp	edx, eax
	jne	.L1251
	movss	xmm0, DWORD PTR _x_r_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1251
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1251
	mov	eax, DWORD PTR r_counter[rip]
	mov	edx, DWORD PTR _x_r_counter[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L1253
.L1251:
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1254
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1253
.L1254:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1253
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1253
	movzx	eax, BYTE PTR r_l[rip]
	test	al, al
	jne	.L1253
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 12
	jle	.L245
.L1253:
	movzx	eax, BYTE PTR _x_r_l[rip]
	test	al, al
	je	.L1255
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1255
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1255
	mov	edx, DWORD PTR r_evt_id[rip]
	mov	eax, DWORD PTR r_counter[rip]
	cmp	edx, eax
	jne	.L1255
	mov	eax, DWORD PTR _x_r_counter[rip]
	test	eax, eax
	jne	.L1255
	movss	xmm0, DWORD PTR _x_r_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1255
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1256
.L1255:
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1258
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1256
.L1258:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1256
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1256
	movzx	eax, BYTE PTR r_l[rip]
	test	al, al
	jne	.L1256
	mov	eax, DWORD PTR r_counter[rip]
	cmp	eax, 13
	je	.L245
.L1256:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L245
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L1260
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1260
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L245
.L1260:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1262
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1262
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1263
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1263
	mov	eax, 1
	jmp	.L1264
.L1263:
	mov	eax, 0
.L1264:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1265
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1265
	mov	eax, DWORD PTR r_evt_id[rip]
	test	eax, eax
	jne	.L1265
	mov	eax, 1
	jmp	.L1266
.L1265:
	mov	eax, 0
.L1266:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1262:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1267
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1267
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1268
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1268
	mov	eax, 1
	jmp	.L1269
.L1268:
	mov	eax, 0
.L1269:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1270
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1270
	mov	eax, DWORD PTR r_evt_id[rip]
	test	eax, eax
	jne	.L1270
	mov	eax, 1
	jmp	.L1271
.L1270:
	mov	eax, 0
.L1271:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1267:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1272
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1272
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1273
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1273
	mov	eax, 1
	jmp	.L1274
.L1273:
	mov	eax, 0
.L1274:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1275
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1275
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 1
	jne	.L1275
	mov	eax, 1
	jmp	.L1276
.L1275:
	mov	eax, 0
.L1276:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1272:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1277
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1277
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L1278
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1278
	mov	eax, 1
	jmp	.L1279
.L1278:
	mov	eax, 0
.L1279:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1280
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1280
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 1
	jne	.L1280
	mov	eax, 1
	jmp	.L1281
.L1280:
	mov	eax, 0
.L1281:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1277:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1282
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1282
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1283
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1283
	mov	eax, 1
	jmp	.L1284
.L1283:
	mov	eax, 0
.L1284:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1285
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1285
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 2
	jne	.L1285
	mov	eax, 1
	jmp	.L1286
.L1285:
	mov	eax, 0
.L1286:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1282:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1287
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1287
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1288
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1288
	mov	eax, 1
	jmp	.L1289
.L1288:
	mov	eax, 0
.L1289:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1290
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1290
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 2
	jne	.L1290
	mov	eax, 1
	jmp	.L1291
.L1290:
	mov	eax, 0
.L1291:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1287:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1292
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1292
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1293
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1293
	mov	eax, 1
	jmp	.L1294
.L1293:
	mov	eax, 0
.L1294:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1295
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1295
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 3
	jne	.L1295
	mov	eax, 1
	jmp	.L1296
.L1295:
	mov	eax, 0
.L1296:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1292:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1297
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1297
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L1298
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1298
	mov	eax, 1
	jmp	.L1299
.L1298:
	mov	eax, 0
.L1299:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1300
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1300
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 3
	jne	.L1300
	mov	eax, 1
	jmp	.L1301
.L1300:
	mov	eax, 0
.L1301:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1297:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1302
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1302
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1303
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1303
	mov	eax, 1
	jmp	.L1304
.L1303:
	mov	eax, 0
.L1304:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1305
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1305
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 4
	jne	.L1305
	mov	eax, 1
	jmp	.L1306
.L1305:
	mov	eax, 0
.L1306:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1302:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1307
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1307
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L1308
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1308
	mov	eax, 1
	jmp	.L1309
.L1308:
	mov	eax, 0
.L1309:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1310
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1310
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 4
	jne	.L1310
	mov	eax, 1
	jmp	.L1311
.L1310:
	mov	eax, 0
.L1311:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1307:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1312
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1312
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1313
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1313
	mov	eax, 1
	jmp	.L1314
.L1313:
	mov	eax, 0
.L1314:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1315
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1315
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 5
	jne	.L1315
	mov	eax, 1
	jmp	.L1316
.L1315:
	mov	eax, 0
.L1316:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1312:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1317
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1317
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L1318
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1318
	mov	eax, 1
	jmp	.L1319
.L1318:
	mov	eax, 0
.L1319:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1320
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1320
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 5
	jne	.L1320
	mov	eax, 1
	jmp	.L1321
.L1320:
	mov	eax, 0
.L1321:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1317:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1322
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1322
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1323
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1323
	mov	eax, 1
	jmp	.L1324
.L1323:
	mov	eax, 0
.L1324:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1325
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1325
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 6
	jne	.L1325
	mov	eax, 1
	jmp	.L1326
.L1325:
	mov	eax, 0
.L1326:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1322:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1327
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1327
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L1328
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1328
	mov	eax, 1
	jmp	.L1329
.L1328:
	mov	eax, 0
.L1329:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1330
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1330
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 6
	jne	.L1330
	mov	eax, 1
	jmp	.L1331
.L1330:
	mov	eax, 0
.L1331:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1327:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1332
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1332
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1333
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1333
	mov	eax, 1
	jmp	.L1334
.L1333:
	mov	eax, 0
.L1334:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1335
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1335
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 7
	jne	.L1335
	mov	eax, 1
	jmp	.L1336
.L1335:
	mov	eax, 0
.L1336:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1332:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1337
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1337
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L1338
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1338
	mov	eax, 1
	jmp	.L1339
.L1338:
	mov	eax, 0
.L1339:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1340
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1340
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 7
	jne	.L1340
	mov	eax, 1
	jmp	.L1341
.L1340:
	mov	eax, 0
.L1341:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1337:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1342
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1342
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1343
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1343
	mov	eax, 1
	jmp	.L1344
.L1343:
	mov	eax, 0
.L1344:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1345
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1345
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 8
	jne	.L1345
	mov	eax, 1
	jmp	.L1346
.L1345:
	mov	eax, 0
.L1346:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1342:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1347
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1347
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L1348
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1348
	mov	eax, 1
	jmp	.L1349
.L1348:
	mov	eax, 0
.L1349:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1350
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1350
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 8
	jne	.L1350
	mov	eax, 1
	jmp	.L1351
.L1350:
	mov	eax, 0
.L1351:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1347:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1352
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1352
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1353
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L1353
	mov	eax, 1
	jmp	.L1354
.L1353:
	mov	eax, 0
.L1354:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1355
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1355
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 9
	jne	.L1355
	mov	eax, 1
	jmp	.L1356
.L1355:
	mov	eax, 0
.L1356:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1352:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1357
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1357
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L1358
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1358
	mov	eax, 1
	jmp	.L1359
.L1358:
	mov	eax, 0
.L1359:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1360
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1360
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 9
	jne	.L1360
	mov	eax, 1
	jmp	.L1361
.L1360:
	mov	eax, 0
.L1361:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1357:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1362
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1362
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1363
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L1363
	mov	eax, 1
	jmp	.L1364
.L1363:
	mov	eax, 0
.L1364:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1365
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1365
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 10
	jne	.L1365
	mov	eax, 1
	jmp	.L1366
.L1365:
	mov	eax, 0
.L1366:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1362:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1367
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1367
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L1368
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1368
	mov	eax, 1
	jmp	.L1369
.L1368:
	mov	eax, 0
.L1369:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1370
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1370
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 10
	jne	.L1370
	mov	eax, 1
	jmp	.L1371
.L1370:
	mov	eax, 0
.L1371:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1367:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1372
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1372
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L1373
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L1373
	mov	eax, 1
	jmp	.L1374
.L1373:
	mov	eax, 0
.L1374:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1375
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1375
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 11
	jne	.L1375
	mov	eax, 1
	jmp	.L1376
.L1375:
	mov	eax, 0
.L1376:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1372:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1377
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1377
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L1378
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L1378
	mov	eax, 1
	jmp	.L1379
.L1378:
	mov	eax, 0
.L1379:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1380
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1380
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 11
	jne	.L1380
	mov	eax, 1
	jmp	.L1381
.L1380:
	mov	eax, 0
.L1381:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1377:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1382
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1382
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L1383
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L1383
	mov	eax, 1
	jmp	.L1384
.L1383:
	mov	eax, 0
.L1384:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1385
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1385
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 12
	jne	.L1385
	mov	eax, 1
	jmp	.L1386
.L1385:
	mov	eax, 0
.L1386:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1382:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1387
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1387
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L1388
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L1388
	mov	eax, 1
	jmp	.L1389
.L1388:
	mov	eax, 0
.L1389:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1390
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1390
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 12
	jne	.L1390
	mov	eax, 1
	jmp	.L1391
.L1390:
	mov	eax, 0
.L1391:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1387:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1392
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1392
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L1393
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L1393
	mov	eax, 1
	jmp	.L1394
.L1393:
	mov	eax, 0
.L1394:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	je	.L1395
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	jne	.L1395
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 13
	jne	.L1395
	mov	eax, 1
	jmp	.L1396
.L1395:
	mov	eax, 0
.L1396:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1392:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1397
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1397
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L1398
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L1398
	mov	eax, 1
	jmp	.L1399
.L1398:
	mov	eax, 0
.L1399:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR r_event1[rip]
	test	al, al
	je	.L1400
	movzx	eax, BYTE PTR r_event0[rip]
	test	al, al
	jne	.L1400
	mov	eax, DWORD PTR r_evt_id[rip]
	cmp	eax, 13
	jne	.L1400
	mov	eax, 1
	jmp	.L1401
.L1400:
	mov	eax, 0
.L1401:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L245
.L1397:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L1767
	ucomiss	xmm0, xmm1
	je	.L1402
.L1767:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L245
.L1402:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jnb	.L1404
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L245
.L1404:
	mov	eax, 1
	jmp	.L1406
.L245:
	mov	eax, 0
.L1406:
	mov	DWORD PTR -4[rbp], eax
	movss	xmm0, DWORD PTR _x_s13_z[rip]
	movss	DWORD PTR s13_z[rip], xmm0
	movss	xmm0, DWORD PTR _x_s13_y[rip]
	movss	DWORD PTR s13_y[rip], xmm0
	movss	xmm0, DWORD PTR _x_s13_x[rip]
	movss	DWORD PTR s13_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s12_z[rip]
	movss	DWORD PTR s12_z[rip], xmm0
	movss	xmm0, DWORD PTR _x_s12_y[rip]
	movss	DWORD PTR s12_y[rip], xmm0
	movss	xmm0, DWORD PTR _x_s12_x[rip]
	movss	DWORD PTR s12_x[rip], xmm0
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movss	xmm0, DWORD PTR _x_s11_z[rip]
	movss	DWORD PTR s11_z[rip], xmm0
	movss	xmm0, DWORD PTR _x_s11_y[rip]
	movss	DWORD PTR s11_y[rip], xmm0
	movss	xmm0, DWORD PTR _x_s11_x[rip]
	movss	DWORD PTR s11_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s10_z[rip]
	movss	DWORD PTR s10_z[rip], xmm0
	movss	xmm0, DWORD PTR _x_s10_y[rip]
	movss	DWORD PTR s10_y[rip], xmm0
	movss	xmm0, DWORD PTR _x_s10_x[rip]
	movss	DWORD PTR s10_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s9_z[rip]
	movss	DWORD PTR s9_z[rip], xmm0
	movss	xmm0, DWORD PTR _x_s9_y[rip]
	movss	DWORD PTR s9_y[rip], xmm0
	movss	xmm0, DWORD PTR _x_s9_x[rip]
	movss	DWORD PTR s9_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s8_z[rip]
	movss	DWORD PTR s8_z[rip], xmm0
	movss	xmm0, DWORD PTR _x_s8_y[rip]
	movss	DWORD PTR s8_y[rip], xmm0
	movss	xmm0, DWORD PTR _x_s8_x[rip]
	movss	DWORD PTR s8_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s13_l2[rip]
	mov	BYTE PTR s13_l2[rip], al
	movss	xmm0, DWORD PTR _x_s7_z[rip]
	movss	DWORD PTR s7_z[rip], xmm0
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	mov	BYTE PTR s13_l1[rip], al
	movss	xmm0, DWORD PTR _x_s7_y[rip]
	movss	DWORD PTR s7_y[rip], xmm0
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	mov	BYTE PTR s13_l0[rip], al
	movss	xmm0, DWORD PTR _x_s7_x[rip]
	movss	DWORD PTR s7_x[rip], xmm0
	movzx	eax, BYTE PTR _x_r_event1[rip]
	mov	BYTE PTR r_event1[rip], al
	movzx	eax, BYTE PTR _x_s8_l2[rip]
	mov	BYTE PTR s8_l2[rip], al
	movss	xmm0, DWORD PTR _x_s2_z[rip]
	movss	DWORD PTR s2_z[rip], xmm0
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	mov	BYTE PTR s11_l1[rip], al
	movss	xmm0, DWORD PTR _x_s5_y[rip]
	movss	DWORD PTR s5_y[rip], xmm0
	movzx	eax, BYTE PTR _x_s1_l2[rip]
	mov	BYTE PTR s1_l2[rip], al
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	mov	BYTE PTR s7_evt1[rip], al
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	mov	BYTE PTR s4_l1[rip], al
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	mov	BYTE PTR s7_evt0[rip], al
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	mov	BYTE PTR s4_l0[rip], al
	movzx	eax, BYTE PTR _x_s12_l2[rip]
	mov	BYTE PTR s12_l2[rip], al
	movss	xmm0, DWORD PTR _x_s6_z[rip]
	movss	DWORD PTR s6_z[rip], xmm0
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	mov	BYTE PTR s1_evt0[rip], al
	movzx	eax, BYTE PTR _x_s7_l2[rip]
	mov	BYTE PTR s7_l2[rip], al
	movss	xmm0, DWORD PTR _x_s1_z[rip]
	movss	DWORD PTR s1_z[rip], xmm0
	movzx	eax, BYTE PTR _x_r_l[rip]
	mov	BYTE PTR r_l[rip], al
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	mov	BYTE PTR s13_evt1[rip], al
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	mov	BYTE PTR s10_l1[rip], al
	movss	xmm0, DWORD PTR _x_s4_y[rip]
	movss	DWORD PTR s4_y[rip], xmm0
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	mov	BYTE PTR s11_evt1[rip], al
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	mov	BYTE PTR s8_l1[rip], al
	movss	xmm0, DWORD PTR _x_s2_y[rip]
	movss	DWORD PTR s2_y[rip], xmm0
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	mov	BYTE PTR s11_l0[rip], al
	movss	xmm0, DWORD PTR _x_s5_x[rip]
	movss	DWORD PTR s5_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_l2[rip]
	mov	BYTE PTR s0_l2[rip], al
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	mov	BYTE PTR s6_evt1[rip], al
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	mov	BYTE PTR s3_l1[rip], al
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	mov	BYTE PTR s11_evt0[rip], al
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	mov	BYTE PTR s8_l0[rip], al
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	movss	DWORD PTR s2_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	mov	BYTE PTR s0_evt1[rip], al
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	mov	BYTE PTR s2_evt0[rip], al
	mov	eax, DWORD PTR _x_r_evt_id[rip]
	mov	DWORD PTR r_evt_id[rip], eax
	movzx	eax, BYTE PTR _x_s10_l2[rip]
	mov	BYTE PTR s10_l2[rip], al
	movss	xmm0, DWORD PTR _x_s4_z[rip]
	movss	DWORD PTR s4_z[rip], xmm0
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	mov	BYTE PTR s10_evt0[rip], al
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	mov	BYTE PTR s7_l0[rip], al
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	movss	DWORD PTR s1_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	mov	BYTE PTR s2_evt1[rip], al
	mov	eax, DWORD PTR _x_r_counter[rip]
	mov	DWORD PTR r_counter[rip], eax
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	mov	BYTE PTR s5_evt0[rip], al
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	mov	BYTE PTR s2_l0[rip], al
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	mov	BYTE PTR s9_evt0[rip], al
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	mov	BYTE PTR s6_l0[rip], al
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	movss	DWORD PTR s0_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	mov	BYTE PTR s10_evt1[rip], al
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	mov	BYTE PTR s7_l1[rip], al
	movss	xmm0, DWORD PTR _x_s1_y[rip]
	movss	DWORD PTR s1_y[rip], xmm0
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	mov	BYTE PTR s13_evt0[rip], al
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	mov	BYTE PTR s10_l0[rip], al
	movss	xmm0, DWORD PTR _x_s4_x[rip]
	movss	DWORD PTR s4_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_r_x[rip]
	movss	DWORD PTR r_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	mov	BYTE PTR s8_evt0[rip], al
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	mov	BYTE PTR s5_l0[rip], al
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	mov	BYTE PTR s9_evt1[rip], al
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	mov	BYTE PTR s6_l1[rip], al
	movss	xmm0, DWORD PTR _x_s0_y[rip]
	movss	DWORD PTR s0_y[rip], xmm0
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	mov	BYTE PTR s12_evt0[rip], al
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	mov	BYTE PTR s9_l0[rip], al
	movss	xmm0, DWORD PTR _x_s3_x[rip]
	movss	DWORD PTR s3_x[rip], xmm0
	movzx	eax, BYTE PTR _x_r_event0[rip]
	mov	BYTE PTR r_event0[rip], al
	movzx	eax, BYTE PTR _x_s6_l2[rip]
	mov	BYTE PTR s6_l2[rip], al
	movss	xmm0, DWORD PTR _x_s0_z[rip]
	movss	DWORD PTR s0_z[rip], xmm0
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	mov	BYTE PTR s12_evt1[rip], al
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	mov	BYTE PTR s9_l1[rip], al
	movss	xmm0, DWORD PTR _x_s3_y[rip]
	movss	DWORD PTR s3_y[rip], xmm0
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	mov	BYTE PTR s12_l0[rip], al
	movss	xmm0, DWORD PTR _x_s6_x[rip]
	movss	DWORD PTR s6_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	mov	BYTE PTR s0_evt0[rip], al
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	mov	BYTE PTR s1_evt1[rip], al
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	mov	BYTE PTR s1_l0[rip], al
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	mov	BYTE PTR s4_evt0[rip], al
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	mov	BYTE PTR s3_evt0[rip], al
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	mov	BYTE PTR s0_l0[rip], al
	movzx	eax, BYTE PTR _x_s11_l2[rip]
	mov	BYTE PTR s11_l2[rip], al
	movss	xmm0, DWORD PTR _x_s5_z[rip]
	movss	DWORD PTR s5_z[rip], xmm0
	movzx	eax, BYTE PTR _x_s2_l2[rip]
	mov	BYTE PTR s2_l2[rip], al
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	mov	BYTE PTR s8_evt1[rip], al
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	mov	BYTE PTR s5_l1[rip], al
	movzx	eax, BYTE PTR _x_s9_l2[rip]
	mov	BYTE PTR s9_l2[rip], al
	movss	xmm0, DWORD PTR _x_s3_z[rip]
	movss	DWORD PTR s3_z[rip], xmm0
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	mov	BYTE PTR s12_l1[rip], al
	movss	xmm0, DWORD PTR _x_s6_y[rip]
	movss	DWORD PTR s6_y[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	mov	BYTE PTR s0_l1[rip], al
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	mov	BYTE PTR s3_evt1[rip], al
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	mov	BYTE PTR s3_l0[rip], al
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	mov	BYTE PTR s6_evt0[rip], al
	movzx	eax, BYTE PTR _x_s3_l2[rip]
	mov	BYTE PTR s3_l2[rip], al
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	mov	BYTE PTR s1_l1[rip], al
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	mov	BYTE PTR s4_evt1[rip], al
	movzx	eax, BYTE PTR _x_s4_l2[rip]
	mov	BYTE PTR s4_l2[rip], al
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	mov	BYTE PTR s2_l1[rip], al
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	mov	BYTE PTR s5_evt1[rip], al
	movzx	eax, BYTE PTR _x_s5_l2[rip]
	mov	BYTE PTR s5_l2[rip], al
.L240:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L1407
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1101004800
	.align 4
.LC2:
	.long	1123024896
	.align 4
.LC4:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"154828402.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	s13_z,4,4
	.comm	_x_s13_z,4,4
	.comm	s13_y,4,4
	.comm	_x_s13_y,4,4
	.comm	s13_x,4,4
	.comm	_x_s13_x,4,4
	.comm	s12_z,4,4
	.comm	_x_s12_z,4,4
	.comm	s12_y,4,4
	.comm	_x_s12_y,4,4
	.comm	s12_x,4,4
	.comm	_x_s12_x,4,4
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	s11_z,4,4
	.comm	_x_s11_z,4,4
	.comm	s11_y,4,4
	.comm	_x_s11_y,4,4
	.comm	s11_x,4,4
	.comm	_x_s11_x,4,4
	.comm	s10_z,4,4
	.comm	_x_s10_z,4,4
	.comm	s10_y,4,4
	.comm	_x_s10_y,4,4
	.comm	s10_x,4,4
	.comm	_x_s10_x,4,4
	.comm	s9_z,4,4
	.comm	_x_s9_z,4,4
	.comm	s9_y,4,4
	.comm	_x_s9_y,4,4
	.comm	s9_x,4,4
	.comm	_x_s9_x,4,4
	.comm	s8_z,4,4
	.comm	_x_s8_z,4,4
	.comm	s8_y,4,4
	.comm	_x_s8_y,4,4
	.comm	s8_x,4,4
	.comm	_x_s8_x,4,4
	.comm	s13_l2,1,1
	.comm	_x_s13_l2,1,1
	.comm	s7_z,4,4
	.comm	_x_s7_z,4,4
	.comm	s13_l1,1,1
	.comm	_x_s13_l1,1,1
	.comm	s7_y,4,4
	.comm	_x_s7_y,4,4
	.comm	s13_l0,1,1
	.comm	_x_s13_l0,1,1
	.comm	s7_x,4,4
	.comm	_x_s7_x,4,4
	.comm	r_event1,1,1
	.comm	_x_r_event1,1,1
	.comm	s8_l2,1,1
	.comm	_x_s8_l2,1,1
	.comm	s2_z,4,4
	.comm	_x_s2_z,4,4
	.comm	s11_l1,1,1
	.comm	_x_s11_l1,1,1
	.comm	s5_y,4,4
	.comm	_x_s5_y,4,4
	.comm	s1_l2,1,1
	.comm	_x_s1_l2,1,1
	.comm	s7_evt1,1,1
	.comm	_x_s7_evt1,1,1
	.comm	s4_l1,1,1
	.comm	_x_s4_l1,1,1
	.comm	s7_evt0,1,1
	.comm	_x_s7_evt0,1,1
	.comm	s4_l0,1,1
	.comm	_x_s4_l0,1,1
	.comm	s12_l2,1,1
	.comm	_x_s12_l2,1,1
	.comm	s6_z,4,4
	.comm	_x_s6_z,4,4
	.comm	s1_evt0,1,1
	.comm	_x_s1_evt0,1,1
	.comm	s7_l2,1,1
	.comm	_x_s7_l2,1,1
	.comm	s1_z,4,4
	.comm	_x_s1_z,4,4
	.comm	r_l,1,1
	.comm	_x_r_l,1,1
	.comm	s13_evt1,1,1
	.comm	_x_s13_evt1,1,1
	.comm	s10_l1,1,1
	.comm	_x_s10_l1,1,1
	.comm	s4_y,4,4
	.comm	_x_s4_y,4,4
	.comm	s11_evt1,1,1
	.comm	_x_s11_evt1,1,1
	.comm	s8_l1,1,1
	.comm	_x_s8_l1,1,1
	.comm	s2_y,4,4
	.comm	_x_s2_y,4,4
	.comm	s11_l0,1,1
	.comm	_x_s11_l0,1,1
	.comm	s5_x,4,4
	.comm	_x_s5_x,4,4
	.comm	s0_l2,1,1
	.comm	_x_s0_l2,1,1
	.comm	s6_evt1,1,1
	.comm	_x_s6_evt1,1,1
	.comm	s3_l1,1,1
	.comm	_x_s3_l1,1,1
	.comm	s11_evt0,1,1
	.comm	_x_s11_evt0,1,1
	.comm	s8_l0,1,1
	.comm	_x_s8_l0,1,1
	.comm	s2_x,4,4
	.comm	_x_s2_x,4,4
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	s0_evt1,1,1
	.comm	_x_s0_evt1,1,1
	.comm	s2_evt0,1,1
	.comm	_x_s2_evt0,1,1
	.comm	r_evt_id,4,4
	.comm	_x_r_evt_id,4,4
	.comm	s10_l2,1,1
	.comm	_x_s10_l2,1,1
	.comm	s4_z,4,4
	.comm	_x_s4_z,4,4
	.comm	s10_evt0,1,1
	.comm	_x_s10_evt0,1,1
	.comm	s7_l0,1,1
	.comm	_x_s7_l0,1,1
	.comm	s1_x,4,4
	.comm	_x_s1_x,4,4
	.comm	s2_evt1,1,1
	.comm	_x_s2_evt1,1,1
	.comm	r_counter,4,4
	.comm	_x_r_counter,4,4
	.comm	s5_evt0,1,1
	.comm	_x_s5_evt0,1,1
	.comm	s2_l0,1,1
	.comm	_x_s2_l0,1,1
	.comm	s9_evt0,1,1
	.comm	_x_s9_evt0,1,1
	.comm	s6_l0,1,1
	.comm	_x_s6_l0,1,1
	.comm	s0_x,4,4
	.comm	_x_s0_x,4,4
	.comm	s10_evt1,1,1
	.comm	_x_s10_evt1,1,1
	.comm	s7_l1,1,1
	.comm	_x_s7_l1,1,1
	.comm	s1_y,4,4
	.comm	_x_s1_y,4,4
	.comm	s13_evt0,1,1
	.comm	_x_s13_evt0,1,1
	.comm	s10_l0,1,1
	.comm	_x_s10_l0,1,1
	.comm	s4_x,4,4
	.comm	_x_s4_x,4,4
	.comm	r_x,4,4
	.comm	_x_r_x,4,4
	.comm	s8_evt0,1,1
	.comm	_x_s8_evt0,1,1
	.comm	s5_l0,1,1
	.comm	_x_s5_l0,1,1
	.comm	s9_evt1,1,1
	.comm	_x_s9_evt1,1,1
	.comm	s6_l1,1,1
	.comm	_x_s6_l1,1,1
	.comm	s0_y,4,4
	.comm	_x_s0_y,4,4
	.comm	s12_evt0,1,1
	.comm	_x_s12_evt0,1,1
	.comm	s9_l0,1,1
	.comm	_x_s9_l0,1,1
	.comm	s3_x,4,4
	.comm	_x_s3_x,4,4
	.comm	r_event0,1,1
	.comm	_x_r_event0,1,1
	.comm	s6_l2,1,1
	.comm	_x_s6_l2,1,1
	.comm	s0_z,4,4
	.comm	_x_s0_z,4,4
	.comm	s12_evt1,1,1
	.comm	_x_s12_evt1,1,1
	.comm	s9_l1,1,1
	.comm	_x_s9_l1,1,1
	.comm	s3_y,4,4
	.comm	_x_s3_y,4,4
	.comm	s12_l0,1,1
	.comm	_x_s12_l0,1,1
	.comm	s6_x,4,4
	.comm	_x_s6_x,4,4
	.comm	s0_evt0,1,1
	.comm	_x_s0_evt0,1,1
	.comm	s1_evt1,1,1
	.comm	_x_s1_evt1,1,1
	.comm	s1_l0,1,1
	.comm	_x_s1_l0,1,1
	.comm	s4_evt0,1,1
	.comm	_x_s4_evt0,1,1
	.comm	s3_evt0,1,1
	.comm	_x_s3_evt0,1,1
	.comm	s0_l0,1,1
	.comm	_x_s0_l0,1,1
	.comm	s11_l2,1,1
	.comm	_x_s11_l2,1,1
	.comm	s5_z,4,4
	.comm	_x_s5_z,4,4
	.comm	s2_l2,1,1
	.comm	_x_s2_l2,1,1
	.comm	s8_evt1,1,1
	.comm	_x_s8_evt1,1,1
	.comm	s5_l1,1,1
	.comm	_x_s5_l1,1,1
	.comm	s9_l2,1,1
	.comm	_x_s9_l2,1,1
	.comm	s3_z,4,4
	.comm	_x_s3_z,4,4
	.comm	s12_l1,1,1
	.comm	_x_s12_l1,1,1
	.comm	s6_y,4,4
	.comm	_x_s6_y,4,4
	.comm	s0_l1,1,1
	.comm	_x_s0_l1,1,1
	.comm	s3_evt1,1,1
	.comm	_x_s3_evt1,1,1
	.comm	s3_l0,1,1
	.comm	_x_s3_l0,1,1
	.comm	s6_evt0,1,1
	.comm	_x_s6_evt0,1,1
	.comm	s3_l2,1,1
	.comm	_x_s3_l2,1,1
	.comm	s1_l1,1,1
	.comm	_x_s1_l1,1,1
	.comm	s4_evt1,1,1
	.comm	_x_s4_evt1,1,1
	.comm	s4_l2,1,1
	.comm	_x_s4_l2,1,1
	.comm	s2_l1,1,1
	.comm	_x_s2_l1,1,1
	.comm	s5_evt1,1,1
	.comm	_x_s5_evt1,1,1
	.comm	s5_l2,1,1
	.comm	_x_s5_l2,1,1
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+4
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+8
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+12
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+16
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+20
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+24
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+28
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+32
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+40
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+44
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+48
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+52
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+56
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+60
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+64
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+68
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+72
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+80
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+88
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+96
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+108
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+116
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+500
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+140
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+528
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+148
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+432
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+160
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+496
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+168
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+396
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+172
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+544
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+492
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+188
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+192
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L1723+204
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+424
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+208
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+404
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+532
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+212
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L1723+220
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+228
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+436
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+548
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+232
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+408
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+536
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+236
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+428
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+244
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+248
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+468
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+440
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+552
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+256
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+260
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+460
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+264
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+556
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+272
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+464
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+280
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+288
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+292
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+300
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+308
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+316
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+320
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+472
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+324
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+456
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+328
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+332
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1723+336
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+340
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+540
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+356
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+360
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+364
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+368
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1723+376
	strb	r2, [r3]
	ldr	r3, .L1723+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1723+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L5
.L4:
	ldr	r3, .L1723+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
	ldr	r3, .L1723+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L5
.L6:
	ldr	r3, .L1723+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
	ldr	r3, .L1723+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L5
.L7:
	ldr	r3, .L1723+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L5:
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L9
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L9
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
.L9:
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L11
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
.L11:
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
.L12:
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L13
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
.L13:
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
.L14:
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L10:
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+8
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L18:
	ldr	r3, .L1723+8
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L19
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L19
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L19:
	ldr	r3, .L1723+8
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L1723+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L1723+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L1723+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L20:
	ldr	r3, .L1723+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L21
	ldr	r3, .L1723+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L21:
	ldr	r3, .L1723+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
	ldr	r3, .L1723+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L23:
	ldr	r3, .L1723+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L1723+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L24:
	ldr	r3, .L1723+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L22:
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L25
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L25
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
.L25:
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L27
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
.L27:
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
.L28:
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L29
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L29
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
.L29:
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L26
.L30:
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L26:
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L34:
	ldr	r3, .L1723+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L35
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L35:
	ldr	r3, .L1723+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L1723+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L1723+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L1723+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L36:
	ldr	r3, .L1723+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L1723+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L37:
	ldr	r3, .L1723+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L1723+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L39:
	ldr	r3, .L1723+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L1723+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L40:
	ldr	r3, .L1723+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L38:
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L1723+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L41:
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L43
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L1723+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L43:
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L1723+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L44:
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L45
	b	.L1724
.L1725:
	.align	2
.L1723:
	.word	s13_z
	.word	s13_y
	.word	s13_x
	.word	s12_z
	.word	s12_y
	.word	s12_x
	.word	_diverge_delta
	.word	s11_z
	.word	s11_y
	.word	s11_x
	.word	s10_z
	.word	s10_y
	.word	s10_x
	.word	s9_z
	.word	s9_y
	.word	s9_x
	.word	s8_z
	.word	s8_y
	.word	s8_x
	.word	s13_l2
	.word	s7_z
	.word	s13_l1
	.word	s7_y
	.word	s13_l0
	.word	s7_x
	.word	r_event1
	.word	s8_l2
	.word	s2_z
	.word	s11_l1
	.word	s5_y
	.word	s1_l2
	.word	s7_evt1
	.word	s4_l1
	.word	s4_l0
	.word	s12_l2
	.word	s6_z
	.word	s1_evt0
	.word	s1_z
	.word	r_l
	.word	s13_evt1
	.word	s4_y
	.word	s11_evt1
	.word	s2_y
	.word	s5_x
	.word	s0_l2
	.word	s3_l1
	.word	s11_evt0
	.word	s2_x
	.word	delta
	.word	s0_evt1
	.word	s2_evt0
	.word	r_evt_id
	.word	s4_z
	.word	s1_x
	.word	s2_evt1
	.word	r_counter
	.word	s5_evt0
	.word	s2_l0
	.word	s0_x
	.word	s1_y
	.word	s13_evt0
	.word	s4_x
	.word	r_x
	.word	s5_l0
	.word	s0_y
	.word	s12_evt0
	.word	s3_x
	.word	r_event0
	.word	s0_z
	.word	s12_evt1
	.word	s3_y
	.word	s12_l0
	.word	s6_x
	.word	s0_evt0
	.word	s1_evt1
	.word	s1_l0
	.word	s4_evt0
	.word	s3_evt0
	.word	s0_l0
	.word	s5_z
	.word	s2_l2
	.word	s5_l1
	.word	s3_z
	.word	s12_l1
	.word	s6_y
	.word	s0_l1
	.word	s3_evt1
	.word	s3_l0
	.word	s3_l2
	.word	s1_l1
	.word	s4_evt1
	.word	s4_l2
	.word	s2_l1
	.word	s5_evt1
	.word	s5_l2
	.word	s11_y
	.word	s11_z
	.word	s11_x
	.word	s11_l2
	.word	s11_l0
	.word	s11_l1
	.word	s10_evt0
	.word	s10_evt1
	.word	s10_y
	.word	s10_z
	.word	s10_x
	.word	s10_l2
	.word	s10_l0
	.word	s10_l1
	.word	s9_evt0
	.word	s9_evt1
	.word	s9_y
	.word	s9_z
	.word	s9_x
	.word	s9_l2
	.word	s9_l0
	.word	s9_l1
	.word	s8_evt0
	.word	s8_evt1
	.word	s8_y
	.word	s8_z
	.word	s8_x
	.word	s8_l2
	.word	s8_l0
	.word	s8_l1
	.word	s7_evt0
	.word	s7_evt1
	.word	s7_y
	.word	s7_z
	.word	1101004800
	.word	s7_x
	.word	1123024896
	.word	s7_l2
	.word	s7_l0
	.word	s7_l1
	.word	s6_evt0
	.word	s6_evt1
	.word	s6_l0
	.word	s6_l1
	.word	s6_l2
.L1724:
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L1723+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
.L45:
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L46
	ldr	r3, .L1723+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L46:
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L42:
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+388
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+380
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+384
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+388
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L50
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L50
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L50
	ldr	r3, .L1723+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L50:
	ldr	r3, .L1723+388
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L51
	ldr	r3, .L1723+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L51:
	ldr	r3, .L1723+388
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L1723+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L1723+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L1723+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L52:
	ldr	r3, .L1723+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L53
	ldr	r3, .L1723+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L53:
	ldr	r3, .L1723+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L1723+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L55:
	ldr	r3, .L1723+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L1723+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L56:
	ldr	r3, .L1723+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L54:
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L57
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L57
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
.L57:
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
.L59:
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
.L60:
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
.L61:
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
.L62:
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L58:
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+420
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+412
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+416
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+420
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L66
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L66:
	ldr	r3, .L1723+420
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L67
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L67
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L67:
	ldr	r3, .L1723+420
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L68
	ldr	r3, .L1723+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L1723+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L1723+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L68:
	ldr	r3, .L1723+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L69
	ldr	r3, .L1723+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L69:
	ldr	r3, .L1723+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
	ldr	r3, .L1723+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L71:
	ldr	r3, .L1723+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L1723+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L72:
	ldr	r3, .L1723+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L70:
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
.L73:
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L75
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
.L75:
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
.L76:
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L77
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L77
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
.L77:
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L74
.L78:
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L74:
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+452
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+448
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+452
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L82:
	ldr	r3, .L1723+452
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L83:
	ldr	r3, .L1723+452
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L1723+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L1723+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L1723+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L84:
	ldr	r3, .L1723+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L1723+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L85:
	ldr	r3, .L1723+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L1723+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L87:
	ldr	r3, .L1723+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L1723+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L88:
	ldr	r3, .L1723+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L86:
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L89
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
.L89:
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L91
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
.L91:
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L92
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
.L92:
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L93
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
.L93:
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
.L94:
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L90:
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+484
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+476
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+480
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+484
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L98:
	ldr	r3, .L1723+484
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L99:
	ldr	r3, .L1723+484
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L1723+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L1723+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L1723+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L100:
	ldr	r3, .L1723+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L101
	ldr	r3, .L1723+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L101:
	ldr	r3, .L1723+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
	ldr	r3, .L1723+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L103:
	ldr	r3, .L1723+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L1723+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L104:
	ldr	r3, .L1723+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L102:
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L105:
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L107
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L107:
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L108
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L108:
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
.L109:
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L110:
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L106:
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1723+520
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+508
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+512
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+520
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L114
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L114:
	ldr	r3, .L1723+520
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L115
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L115
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L115:
	ldr	r3, .L1723+520
	ldr	r3, [r3]	@ float
	ldr	r1, .L1723+524
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L1723+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L1723+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L1723+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L116:
	ldr	r3, .L1723+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L117
	ldr	r3, .L1723+544
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L117:
	ldr	r3, .L1723+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L1723+544
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L119:
	ldr	r3, .L1723+544
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L1723+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L120:
	ldr	r3, .L1723+540
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1723+544
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L118:
	ldr	r3, .L1723+556
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L121
	ldr	r3, .L1723+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L121
	ldr	r3, .L1723+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L122
.L121:
	ldr	r3, .L1723+556
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L1723+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
	ldr	r3, .L1723+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L122
.L123:
	ldr	r3, .L1723+556
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L1723+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L1723+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L122
.L124:
	ldr	r3, .L1723+556
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L125
	ldr	r3, .L1723+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L125
	ldr	r3, .L1723+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
.L125:
	ldr	r3, .L1723+556
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
	ldr	r3, .L1723+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L1723+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L122
.L126:
	ldr	r3, .L1723+556
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L122:
	ldr	r3, .L1726+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+24
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L1726+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L1726
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L1726+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L130:
	ldr	r3, .L1726+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L1726+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L1726+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L1726
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L131:
	ldr	r3, .L1726+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L1726+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L1726
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L1726+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L132:
	ldr	r3, .L1726+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L133
	ldr	r3, .L1726+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L133:
	ldr	r3, .L1726+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L1726+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L135:
	ldr	r3, .L1726+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L1726+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L136:
	ldr	r3, .L1726+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L134:
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L137
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L137
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
.L137:
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L139
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
.L139:
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
.L140:
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
.L141:
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
.L142:
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L138:
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+56
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+24
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L146
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L146:
	ldr	r3, .L1726+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L147:
	ldr	r3, .L1726+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L1726+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L1726+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L1726+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L148:
	ldr	r3, .L1726+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L1726+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L149:
	ldr	r3, .L1726+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L1726+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L151:
	ldr	r3, .L1726+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L1726+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L152:
	ldr	r3, .L1726+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L150:
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L153
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L153
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
.L153:
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
.L155:
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L156
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
.L156:
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L157
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
.L157:
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
.L158:
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L154:
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+80
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+24
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L162
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L162:
	ldr	r3, .L1726+80
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L163
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L163
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L163:
	ldr	r3, .L1726+80
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L1726+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L1726+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L1726+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L164:
	ldr	r3, .L1726+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L165
	ldr	r3, .L1726+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L165:
	ldr	r3, .L1726+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
	ldr	r3, .L1726+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L167:
	ldr	r3, .L1726+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L1726+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L168:
	ldr	r3, .L1726+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L166:
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L170
.L169:
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L171
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L171
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L170
.L171:
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L170
.L172:
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L170
.L173:
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L170
.L174:
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L170:
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+116
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+112
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+24
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L178:
	ldr	r3, .L1726+112
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L179
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L179:
	ldr	r3, .L1726+112
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L1726+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L1726+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L1726+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L180:
	ldr	r3, .L1726+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L1726+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
.L181:
	ldr	r3, .L1726+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L1726+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
.L183:
	ldr	r3, .L1726+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L1726+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
.L184:
	ldr	r3, .L1726+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L182:
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L185
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L185
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
.L185:
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L187
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
.L187:
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
.L188:
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L189
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
.L189:
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
.L190:
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L186:
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+144
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+24
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L194:
	ldr	r3, .L1726+144
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L195:
	ldr	r3, .L1726+144
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L1726+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L1726+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L1726+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L196:
	ldr	r3, .L1726+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L1726+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
.L197:
	ldr	r3, .L1726+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L1726+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
.L199:
	ldr	r3, .L1726+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L1726+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
.L200:
	ldr	r3, .L1726+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L198:
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L201:
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L203:
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L204:
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
.L205:
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L206:
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L202:
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	b	.L1727
.L1728:
	.align	2
.L1726:
	.word	s6_l0
	.word	s6_l1
	.word	s6_l2
	.word	s6_x
	.word	s6_y
	.word	s6_z
	.word	1101004800
	.word	s5_evt0
	.word	s5_evt1
	.word	s5_l2
	.word	s5_l0
	.word	s5_l1
	.word	s5_x
	.word	s5_y
	.word	s5_z
	.word	s4_evt0
	.word	s4_evt1
	.word	s4_l2
	.word	s4_l0
	.word	s4_l1
	.word	s4_x
	.word	s4_y
	.word	s4_z
	.word	s3_evt0
	.word	s3_evt1
	.word	s3_l2
	.word	s3_l0
	.word	s3_l1
	.word	s3_x
	.word	s3_y
	.word	s3_z
	.word	s2_evt0
	.word	s2_evt1
	.word	s2_l2
	.word	s2_l0
	.word	s2_l1
	.word	s2_x
	.word	s2_y
	.word	s2_z
	.word	s1_evt0
	.word	s1_evt1
	.word	s1_y
	.word	s1_z
	.word	s1_x
	.word	s1_l2
	.word	s1_l0
	.word	s1_l1
	.word	s0_evt0
	.word	s0_evt1
	.word	s0_y
	.word	s0_z
	.word	1101004800
	.word	s0_x
	.word	1123024896
	.word	s0_l2
	.word	s0_l0
	.word	s0_l1
	.word	r_event1
	.word	r_event0
	.word	r_evt_id
	.word	r_counter
	.word	r_l
	.word	r_x
	.word	delta
	.word	_diverge_delta
	.word	_x_s13_z
	.word	_x_s13_y
	.word	_x_s13_x
	.word	_x_s12_z
	.word	_x_s12_y
	.word	_x_s12_x
	.word	_x__diverge_delta
	.word	_x_s11_z
	.word	_x_s11_y
	.word	_x_s11_x
	.word	_x_s10_z
	.word	_x_s10_y
	.word	_x_s10_x
	.word	_x_s9_z
	.word	_x_s9_y
	.word	_x_s9_x
	.word	_x_s8_z
	.word	_x_s8_y
	.word	_x_s8_x
	.word	_x_s13_l2
	.word	_x_s7_z
	.word	_x_s13_l1
	.word	_x_s7_y
	.word	_x_s13_l0
	.word	_x_s7_x
	.word	_x_r_event1
	.word	_x_s8_l2
	.word	_x_s2_z
	.word	_x_s11_l1
	.word	_x_s5_y
	.word	_x_s1_l2
	.word	_x_s7_evt1
	.word	_x_s4_l1
	.word	_x_s7_evt0
	.word	_x_s4_l0
	.word	_x_s12_l2
	.word	_x_s6_z
	.word	_x_s1_evt0
	.word	_x_s7_l2
	.word	_x_s1_z
	.word	_x_r_l
	.word	_x_s13_evt1
	.word	_x_s10_l1
	.word	_x_s4_y
	.word	_x_s11_evt1
	.word	_x_s8_l1
	.word	_x_s2_y
	.word	_x_s11_l0
	.word	_x_s5_x
	.word	_x_s0_l2
	.word	_x_s6_evt1
	.word	_x_s3_l1
	.word	_x_s11_evt0
	.word	_x_s8_l0
	.word	_x_s2_x
	.word	_x_delta
	.word	_x_s0_evt1
	.word	_x_s2_evt0
	.word	_x_r_evt_id
	.word	_x_s10_l2
	.word	_x_s4_z
	.word	_x_s10_evt0
	.word	_x_s7_l0
	.word	_x_s1_x
	.word	_x_s2_evt1
	.word	_x_r_counter
	.word	_x_s5_evt0
	.word	_x_s2_l0
	.word	_x_s9_evt0
	.word	_x_s6_l0
	.word	_x_s0_x
	.word	_x_s10_evt1
	.word	_x_s7_l1
	.word	_x_s1_y
	.word	_x_s13_evt0
	.word	_x_s10_l0
	.word	_x_s4_x
	.word	_x_r_x
	.word	_x_s8_evt0
	.word	_x_s5_l0
	.word	_x_s9_evt1
	.word	_x_s6_l1
	.word	_x_s0_y
	.word	_x_s12_evt0
	.word	_x_s9_l0
	.word	_x_s3_x
	.word	_x_r_event0
	.word	_x_s6_l2
	.word	_x_s0_z
	.word	_x_s12_evt1
	.word	_x_s9_l1
	.word	_x_s3_y
	.word	_x_s12_l0
	.word	_x_s6_x
	.word	_x_s0_evt0
	.word	_x_s1_evt1
	.word	_x_s1_l0
	.word	_x_s4_evt0
	.word	_x_s3_evt0
	.word	_x_s0_l0
	.word	_x_s11_l2
	.word	_x_s5_z
	.word	_x_s2_l2
	.word	_x_s8_evt1
	.word	_x_s5_l1
	.word	_x_s9_l2
	.word	_x_s3_z
	.word	_x_s12_l1
	.word	_x_s6_y
	.word	_x_s0_l1
	.word	_x_s3_evt1
	.word	_x_s3_l0
	.word	_x_s6_evt0
	.word	_x_s3_l2
	.word	_x_s1_l1
	.word	_x_s4_evt1
	.word	_x_s4_l2
	.word	_x_s2_l1
	.word	_x_s5_evt1
	.word	_x_s5_l2
.L1727:
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L210:
	ldr	r3, .L1726+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L211:
	ldr	r3, .L1726+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L1726+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L1726+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L1726+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L212:
	ldr	r3, .L1726+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L1726+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L213:
	ldr	r3, .L1726+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L1726+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L215:
	ldr	r3, .L1726+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L1726+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L216:
	ldr	r3, .L1726+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L214:
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
.L217:
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L219
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
.L219:
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
.L220:
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L218
.L221:
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
.L222:
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L218:
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+208
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L226:
	ldr	r3, .L1726+208
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L227
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L227:
	ldr	r3, .L1726+208
	ldr	r3, [r3]	@ float
	ldr	r1, .L1726+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L228
	ldr	r3, .L1726+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L1726+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L1726+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
.L228:
	ldr	r3, .L1726+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1726+248
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L1726+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
.L230:
	ldr	r3, .L1726+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
	ldr	r3, .L1726+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
.L232:
	ldr	r3, .L1726+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
.L231:
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L233
	ldr	r3, .L1726+236
	ldr	r3, [r3]
	cmp	r3, #13
	bne	.L8
.L233:
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L234
	ldr	r3, .L1726+240
	ldr	r3, [r3]
	cmp	r3, #13
	bne	.L8
.L234:
	ldr	r3, .L1726+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L1726+248
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
.L235:
	ldr	r3, .L1726+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1726+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1726+256
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	mov	r3, #1
	b	.L239
.L8:
	mov	r3, #0
.L239:
	str	r3, [fp, #-24]
	b	.L240
.L1363:
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+264
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+268
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+272
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+276
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+280
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+284
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+288
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+292
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+296
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+300
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+304
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+308
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+312
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+316
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+320
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+324
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+328
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+332
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+336
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+340
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+348
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+356
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+360
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+364
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+368
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+376
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+380
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+384
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+388
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+396
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+400
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+404
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+408
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+412
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+416
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+420
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+424
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+428
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+432
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+436
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+440
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+444
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+448
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+452
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+456
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+460
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+464
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+468
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+472
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+476
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+480
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+484
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+488
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L1726+492
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+496
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+500
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+504
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+508
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+512
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+516
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L1726+520
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+524
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+528
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+532
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+536
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+540
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+544
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+548
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+552
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+556
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+560
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+564
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+568
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+572
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+576
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+580
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+584
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+588
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+592
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+596
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+600
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+604
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+608
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+612
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+616
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+620
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+624
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+628
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+632
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+636
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+640
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+644
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+648
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+652
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+656
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+660
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+664
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+668
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+672
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+676
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+680
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+684
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+688
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1726+692
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+696
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+700
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+704
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+708
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+712
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+716
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+720
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+724
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+728
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+732
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1726+736
	strb	r2, [r3]
	ldr	r3, .L1729
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L1729+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
.L241:
	ldr	r3, .L1729
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L1729+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
.L243:
	ldr	r3, .L1729+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
	ldr	r3, .L1729
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
.L244:
	ldr	r3, .L1729
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L242:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L246
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L246
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L246:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L248
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L248
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L248:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L249
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L249:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L250
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L250:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L251
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L251:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L247:
	ldr	r3, .L1729+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+88
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L252
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L252
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L252:
	ldr	r3, .L1729+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L253:
	ldr	r3, .L1729+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L254:
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L255
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L255:
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L262
.L259:
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L262:
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1729+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1729+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L266
.L263:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L266:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L267
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L267
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
.L267:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L269
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
.L268:
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L272
.L269:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L272
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L272
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L272
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L272
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L272:
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L273
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L273
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+88
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L273
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L275
	mov	r3, #0
	mov	r4, r3
.L275:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L276
.L273:
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
.L277:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L276
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L276
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L276
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L276:
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+88
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L280
.L278:
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L281
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
.L281:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L280:
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L282
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L282
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L285
.L282:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L285
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L285
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L285:
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L286
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L286
	ldr	r3, .L1729+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L1729+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L289
.L286:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L289
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L289:
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L294
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L294
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
.L294:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
.L290:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L295
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L295:
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	b	.L1730
.L1731:
	.align	2
.L1729:
	.word	_x_s13_evt0
	.word	_x_s13_evt1
	.word	s13_z
	.word	_x_s13_z
	.word	s13_x
	.word	_x_s13_x
	.word	s13_y
	.word	_x_s13_y
	.word	_x_s13_l2
	.word	_x_s13_l0
	.word	_x_s13_l1
	.word	s13_l2
	.word	s13_l0
	.word	s13_l1
	.word	s13_evt0
	.word	s13_evt1
	.word	_x_s12_evt0
	.word	_x_s12_evt1
	.word	_x_s12_x
	.word	s12_y
	.word	_x_s12_y
	.word	s12_x
	.word	1101004800
	.word	1123024896
	.word	delta
	.word	s12_l2
	.word	s12_l0
	.word	s12_l1
	.word	_x_s12_l1
	.word	s12_z
	.word	_x_s12_z
	.word	s12_evt1
	.word	s12_evt0
	.word	_x_s12_l2
	.word	_x_s12_l0
.L1730:
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L296
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+88
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L298
	mov	r3, #0
	mov	r4, r3
.L298:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L299
.L296:
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L300
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
.L300:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L299:
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L301
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+88
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L303
.L301:
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L303
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L303
.L304:
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L303
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L303
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L303
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L303
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L303
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L303:
	ldr	r3, .L1729+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L1729+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L1729+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L1729+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L1729+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L1729+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
.L305:
	ldr	r3, .L1729+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L1729+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L1729+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L309
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L1729+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1729+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L309:
	ldr	r3, .L1729+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L1729+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
.L310:
	ldr	r3, .L1729+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L1729+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
.L312:
	ldr	r3, .L1729+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L1729+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
.L313:
	ldr	r3, .L1729+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L311:
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
.L314:
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
.L316:
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L317
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
.L317:
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L318
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
.L318:
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L319
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L319
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
.L319:
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L315:
	ldr	r3, .L1729+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+88
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L320
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L320
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L320:
	ldr	r3, .L1729+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L321
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L321
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L321:
	ldr	r3, .L1729+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L322
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L322
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L322
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L322:
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L323
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L323:
	ldr	r3, .L1729+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L327
	ldr	r3, .L1729+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L327
	ldr	r3, .L1729+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L327
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L327
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L327
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1729+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1729+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L330
.L327:
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L330
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L330:
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L331
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L331
	ldr	r3, .L1729+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1729+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1729+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L334
.L331:
	ldr	r3, .L1729+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L334
	ldr	r3, .L1729+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L334
	ldr	r3, .L1729+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L334
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L334:
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L335
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L336
.L335:
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
.L336:
	ldr	r3, .L1729+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1729+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1729+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L340
.L337:
	ldr	r3, .L1729+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L340
	ldr	r3, .L1729+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L340
	ldr	r3, .L1729+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L340
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L340
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L340:
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L341
	ldr	r3, .L1729+84
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+88
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L1729+116
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L343
	mov	r3, #0
	mov	r4, r3
.L343:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L344
.L341:
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L345
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
.L345:
	ldr	r3, .L1729+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L344
	ldr	r3, .L1729+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L1729+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L344
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L344
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L344:
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L1729+84
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+88
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L1729+116
	ldr	r3, [r3]	@ float
	ldr	r1, .L1729+92
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L348
.L346:
	ldr	r3, .L1729+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L349
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
.L349:
	ldr	r3, .L1729+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L1729+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1729+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1729+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L348:
	ldr	r3, .L1729+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1729+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L350
	ldr	r3, .L1729+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L350
	ldr	r3, .L1729+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L350
	ldr	r3, .L1729+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L350
	ldr	r3, .L1729+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L350
	ldr	r3, .L1732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L350
	ldr	r3, .L1732+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L350
	ldr	r3, .L1732+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L353
.L350:
	ldr	r3, .L1732+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L353
	ldr	r3, .L1732+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1732+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L353
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L353:
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1732+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1732+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L354
	ldr	r3, .L1732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L354
	ldr	r3, .L1732+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1732+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1732+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L357
.L354:
	ldr	r3, .L1732+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1732+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1732+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L357:
	ldr	r3, .L1732+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L358
	ldr	r3, .L1732+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L358
	ldr	r3, .L1732+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L358
	ldr	r3, .L1732+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L1732+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L1732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L363
.L362:
	ldr	r3, .L1732+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L358
	ldr	r3, .L1732+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L358
	ldr	r3, .L1732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L363
.L358:
	ldr	r3, .L1732+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L1732+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L363
	ldr	r3, .L1732+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L363
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L363:
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L364
	ldr	r3, .L1732+4
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1732+12
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L366
	mov	r3, #0
	mov	r4, r3
.L366:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L367
.L364:
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L368
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L367
.L368:
	ldr	r3, .L1732+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L1732+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L367
	ldr	r3, .L1732+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L367
	ldr	r3, .L1732+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L1732+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L1732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L367:
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L369
	ldr	r3, .L1732+4
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L1732+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L371
.L369:
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L372
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L371
.L372:
	ldr	r3, .L1732+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L371
	ldr	r3, .L1732+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L371
	ldr	r3, .L1732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L371
	ldr	r3, .L1732+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1732+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L371
	ldr	r3, .L1732+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L371:
	ldr	r3, .L1732+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L373
	ldr	r3, .L1732+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L373
	ldr	r3, .L1732+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L373
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L373
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L373
	ldr	r3, .L1732+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L373
	ldr	r3, .L1732+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L373
	ldr	r3, .L1732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
.L373:
	ldr	r3, .L1732+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
	ldr	r3, .L1732+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
	ldr	r3, .L1732+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L377
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L377
	ldr	r3, .L1732+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L377:
	ldr	r3, .L1732+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L378
	ldr	r3, .L1732+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
.L378:
	ldr	r3, .L1732+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L380
	ldr	r3, .L1732+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
.L380:
	ldr	r3, .L1732+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1732+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
.L381:
	ldr	r3, .L1732+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L379:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L382
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L382
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L383
.L382:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L384
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L383
.L384:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L385
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L385
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L383
.L385:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L386
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L383
.L386:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L387
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L383
.L387:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L383:
	ldr	r3, .L1732+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L388
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L388
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L388
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L388:
	ldr	r3, .L1732+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L389:
	ldr	r3, .L1732+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L390:
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L391
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L391:
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L398
.L395:
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L398
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L398:
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L399
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L399
	ldr	r3, .L1732+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L1732+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L402
.L399:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L402
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L402
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L402
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L402
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L402:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L403
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L404
.L403:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L405
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L405
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L405
.L404:
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L405
	b	.L1733
.L1734:
	.align	2
.L1732:
	.word	_x_s12_l1
	.word	s12_x
	.word	_x_s12_x
	.word	s12_y
	.word	_x_s12_y
	.word	s12_l2
	.word	s12_l1
	.word	s12_l0
	.word	s12_evt0
	.word	s12_evt1
	.word	_x_s12_l2
	.word	_x_s12_l0
	.word	_x_s12_z
	.word	s12_z
	.word	_x_s11_evt0
	.word	_x_s11_evt1
	.word	s11_z
	.word	_x_s11_z
	.word	s11_x
	.word	_x_s11_x
	.word	s11_y
	.word	_x_s11_y
	.word	_x_s11_l2
	.word	_x_s11_l0
	.word	_x_s11_l1
	.word	s11_l2
	.word	s11_l0
	.word	s11_l1
	.word	delta
	.word	s11_evt0
	.word	s11_evt1
	.word	_x_s10_evt0
	.word	_x_s10_evt1
	.word	1101004800
	.word	1123024896
	.word	_x_s10_x
	.word	s10_y
	.word	_x_s10_y
	.word	s10_z
	.word	_x_s10_z
	.word	s10_l0
	.word	_x_s10_l0
	.word	s10_l1
	.word	_x_s10_l1
	.word	s10_l2
	.word	_x_s10_l2
	.word	delta
	.word	s10_x
.L1733:
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L405
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L408
.L405:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L408
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L408
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L408
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L408
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L408:
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L409
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L411
	mov	r3, #0
	mov	r4, r3
.L411:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L412
.L409:
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L413
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
.L413:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L412:
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L416
.L414:
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L417
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
.L417:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L416:
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L418
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L418
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L421
.L418:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L421
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L421
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L421:
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L422
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L422
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L422
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L422
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L422
	ldr	r3, .L1732+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L422
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L422
	ldr	r3, .L1732+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L425
.L422:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L425:
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L430
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L430
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
.L430:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
.L426:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L431
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L431
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L431:
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L432
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L432
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L434
	mov	r3, #0
	mov	r4, r3
.L434:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L435
.L432:
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L435
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L436
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L435
.L436:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L435
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L435
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L435
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L435
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L435
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L435:
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L437
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L439
.L437:
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L439
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L440
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
.L440:
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L439:
	ldr	r3, .L1732+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L1732+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L1732+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1732+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L441
	ldr	r3, .L1732+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L441
	ldr	r3, .L1732+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L441
	ldr	r3, .L1732+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
.L441:
	ldr	r3, .L1732+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L1732+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L1732+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L445
	ldr	r3, .L1732+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L1732+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1732+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L445:
	ldr	r3, .L1732+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L446
	ldr	r3, .L1732+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
.L446:
	ldr	r3, .L1732+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L448
	ldr	r3, .L1732+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
.L448:
	ldr	r3, .L1732+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L449
	ldr	r3, .L1732+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
.L449:
	ldr	r3, .L1732+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L447:
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L450
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L450
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
.L450:
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L452
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
.L452:
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L453
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
.L453:
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L454
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L454
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L451
.L454:
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L455
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L455
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
.L455:
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L451:
	ldr	r3, .L1732+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L456:
	ldr	r3, .L1732+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L457
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L457
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L457:
	ldr	r3, .L1732+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1732+136
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L458:
	ldr	r3, .L1732+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L459
	ldr	r3, .L1732+184
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+188
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+184
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1732+184
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1732+156
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L459:
	ldr	r3, .L1732+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1732+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1732+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1732+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1732+184
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1732+188
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1735+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1735+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L466
.L463:
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L466:
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L1735
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1735+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1735+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L470
.L467:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L470
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L470
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L470
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L470:
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L471
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L472
.L471:
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L473
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L473
.L472:
	ldr	r3, .L1735+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L1735+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L1735+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L476
.L473:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L476
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L476
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L476:
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L477
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L477
	ldr	r3, .L1735+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L477
	ldr	r3, .L1735+12
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L479
	mov	r3, #0
	mov	r4, r3
.L479:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L480
.L477:
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L481
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
.L481:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L480:
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L482
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L482
	ldr	r3, .L1735+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L482
	ldr	r3, .L1735+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L484
.L482:
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L485
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
.L485:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L484
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L484
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L484
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L484:
	ldr	r3, .L1735+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L486
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L486
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1735+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1735+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L489
.L486:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L489:
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L490
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L490
	ldr	r3, .L1735
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L1735+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L1735+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L493
.L490:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L493
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L493:
	ldr	r3, .L1735+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1735+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1735+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L498
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L498
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L499
.L498:
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L499
.L494:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L499
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L499
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L499:
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L500
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L500
	ldr	r3, .L1735+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L500
	ldr	r3, .L1735+4
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L502
	mov	r3, #0
	mov	r4, r3
.L502:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L503
.L500:
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L504
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L503
.L504:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L503
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L503
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L503:
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L505
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L505
	ldr	r3, .L1735+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L505
	ldr	r3, .L1735+4
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L507
.L505:
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L507
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L508
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
.L508:
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L507
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L507
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L507
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L507
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L507:
	ldr	r3, .L1735+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L1735+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L1735+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L509
	ldr	r3, .L1735+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L509
	ldr	r3, .L1735+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L509
	ldr	r3, .L1735+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
.L509:
	ldr	r3, .L1735+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1735+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1735+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L513
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1735+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L513:
	ldr	r3, .L1735+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L514
	ldr	r3, .L1735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L515
.L514:
	ldr	r3, .L1735+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L1735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L515
.L516:
	ldr	r3, .L1735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L517
	ldr	r3, .L1735+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L515
.L517:
	ldr	r3, .L1735+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1735+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L515:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L518
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L518
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
.L518:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L520
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
.L520:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L521
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
.L521:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L519
.L522:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L523
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L523
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
.L523:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L519:
	ldr	r3, .L1735+112
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L524:
	ldr	r3, .L1735+112
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L525
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L525
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L525
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L525:
	ldr	r3, .L1735+112
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L526
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L526:
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L527
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	b	.L1736
.L1737:
	.align	2
.L1735:
	.word	_x_s10_x
	.word	s10_y
	.word	_x_s10_y
	.word	s10_z
	.word	_x_s10_z
	.word	s10_evt0
	.word	s10_evt1
	.word	_x_s10_l2
	.word	_x_s10_l0
	.word	_x_s10_l1
	.word	s10_l2
	.word	s10_l0
	.word	s10_l1
	.word	s10_x
	.word	_x_s9_evt0
	.word	_x_s9_evt1
	.word	delta
	.word	1101004800
	.word	1123024896
	.word	delta
	.word	_x_s9_l0
	.word	_x_s9_l1
	.word	s9_l2
	.word	s9_l0
	.word	s9_l1
	.word	s9_z
	.word	_x_s9_z
	.word	s9_x
	.word	_x_s9_x
	.word	s9_y
	.word	_x_s9_y
	.word	s9_evt1
	.word	s9_evt0
	.word	_x_s9_l2
.L1736:
	mov	r5, r1
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1735+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L527:
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1735+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L534
.L531:
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L534
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L534:
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L1735+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1735+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L538
.L535:
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L538
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L538
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L538
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L538:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L540
.L539:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L541
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
.L540:
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L544
.L541:
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L544
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L544
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L544:
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L545
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L545
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L545
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L547
	mov	r3, #0
	mov	r4, r3
.L547:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L548
.L545:
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L548
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L548
.L549:
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L548
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L548
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L548
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L548
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L548
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L548:
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L550
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L550
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L550
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L552
.L550:
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L553
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L552
.L553:
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L552:
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L554
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L554
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L557
.L554:
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L557:
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L558
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L558
	ldr	r3, .L1735+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L558
	ldr	r3, .L1735+104
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L561
.L558:
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L561
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L561:
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L567
.L566:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L567
.L562:
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L567
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L567
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L567
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L567
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L567:
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L570
	mov	r3, #0
	mov	r4, r3
.L570:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L571
.L568:
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L572
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L571
.L572:
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L571
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L571
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L571:
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L573
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L573
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+68
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L573
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	ldr	r1, .L1735+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L575
.L573:
	ldr	r3, .L1735+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L575
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L576
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
.L576:
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L575
	ldr	r3, .L1735+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L575
	ldr	r3, .L1735+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L575
	ldr	r3, .L1735+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
	ldr	r3, .L1735+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L575
	ldr	r3, .L1735+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L575:
	ldr	r3, .L1735+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L1735+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L1735+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1735+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L1735+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L1735+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L1735+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L1738
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L1738+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
.L577:
	ldr	r3, .L1738+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L1738+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L1738+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L581
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L1738+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L581:
	ldr	r3, .L1738+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L582
	ldr	r3, .L1738+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L583
.L582:
	ldr	r3, .L1738+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1738+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L583
.L584:
	ldr	r3, .L1738+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1738+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L583
.L585:
	ldr	r3, .L1738+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L583:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L586
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L586
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
.L586:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
.L588:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L589
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
.L589:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L587
.L590:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L591
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L591
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
.L591:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L587:
	ldr	r3, .L1738+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L592
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L592
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L592
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L592:
	ldr	r3, .L1738+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L593
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L593:
	ldr	r3, .L1738+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L594
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L594:
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L595
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L595:
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L602
.L599:
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L602
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L602:
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L603
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L603
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L603
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L603
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L603
	ldr	r3, .L1738+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L603
	ldr	r3, .L1738+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L603
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L606
.L603:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L606
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L606
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L606
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L606
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L606:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L607
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L608
.L607:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L609
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L609
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L609
.L608:
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L609
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L609
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L612
.L609:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L612:
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L613
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L615
	mov	r3, #0
	mov	r4, r3
.L615:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L616
.L613:
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L617
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
.L617:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L616
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L616
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L616
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L616:
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L618
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L620
.L618:
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L620
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
.L621:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L620:
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L622
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L622
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L622
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L622
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L622
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L622
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L622
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L625
.L622:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L625
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L625
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L625
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L625
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L625:
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L1738+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1738+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L629
.L626:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L629
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L1738+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L629:
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L630
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L630
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L630
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L635
.L634:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
	b	.L1739
.L1740:
	.align	2
.L1738:
	.word	_x_s9_l0
	.word	_x_s9_l1
	.word	s9_l2
	.word	s9_l0
	.word	s9_l1
	.word	delta
	.word	s9_evt0
	.word	s9_evt1
	.word	_x_s8_evt0
	.word	_x_s8_evt1
	.word	s8_z
	.word	_x_s8_z
	.word	s8_x
	.word	_x_s8_x
	.word	s8_y
	.word	_x_s8_y
	.word	_x_s8_l2
	.word	_x_s8_l0
	.word	_x_s8_l1
	.word	s8_l2
	.word	s8_l0
	.word	s8_l1
	.word	s8_evt0
	.word	s8_evt1
	.word	_x_s7_evt0
	.word	_x_s7_evt1
	.word	_x_s7_x
	.word	_x_s7_z
	.word	s7_y
	.word	_x_s7_y
	.word	_x_s7_l1
	.word	_x_s7_l0
	.word	s7_x
	.word	1101004800
	.word	s7_z
	.word	1123024896
	.word	delta
	.word	s7_evt0
	.word	s7_evt1
	.word	s7_l2
	.word	s7_l0
	.word	s7_l1
	.word	_x_s7_l2
.L1739:
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L635
.L630:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L635
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L635
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L635:
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L636
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L636
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L636
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L638
	mov	r3, #0
	mov	r4, r3
.L638:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L639
.L636:
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L640
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
.L640:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L639
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L639
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L639:
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L641
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L643
.L641:
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L644
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
.L644:
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L643:
	ldr	r3, .L1738+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1738+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1738+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L645
	ldr	r3, .L1738+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L645
	ldr	r3, .L1738+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L645
	ldr	r3, .L1738+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L649
.L645:
	ldr	r3, .L1738+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L1738+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L1738+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L649
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L1738+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L649:
	ldr	r3, .L1738+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L650
	ldr	r3, .L1738+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
.L650:
	ldr	r3, .L1738+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L1738+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
.L652:
	ldr	r3, .L1738+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L653
	ldr	r3, .L1738+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
.L653:
	ldr	r3, .L1738+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L651:
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L655
.L654:
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L655
.L656:
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L657
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L657
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L655
.L657:
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L658
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L658
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L655
.L658:
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L659
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L655
.L659:
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L655:
	ldr	r3, .L1738+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L660
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L660
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L660:
	ldr	r3, .L1738+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L661
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L661
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L661:
	ldr	r3, .L1738+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L662
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L662
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L662
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L662:
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L663
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+108
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L663:
	ldr	r3, .L1738+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1738+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1738+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1738+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1738+108
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L670
.L667:
	ldr	r3, .L1738+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L670
	ldr	r3, .L1738+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L670:
	ldr	r3, .L1738+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1738+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
	ldr	r3, .L1738+104
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1738+116
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1738+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+108
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L674
.L671:
	ldr	r3, .L1738+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L674
	ldr	r3, .L1738+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L674
	ldr	r3, .L1738+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L674
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L674
	ldr	r3, .L1738+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L674:
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L675
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L675
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
.L675:
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L677
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L677
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L677
.L676:
	ldr	r3, .L1738+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L677
	ldr	r3, .L1738+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+108
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L677
	ldr	r3, .L1738+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1738+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L680
.L677:
	ldr	r3, .L1738+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L680
	ldr	r3, .L1738+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L680
	ldr	r3, .L1738+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L680
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L680
	ldr	r3, .L1738+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1738+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L680:
	ldr	r3, .L1738+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1738+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L681
	ldr	r3, .L1738+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1738+136
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L683
	mov	r3, #0
	mov	r4, r3
.L683:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L684
.L681:
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1738+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L685
	ldr	r3, .L1738+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
.L685:
	ldr	r3, .L1738+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L684
	ldr	r3, .L1738+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1738+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L684
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L684
	ldr	r3, .L1738+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1738+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L684:
	ldr	r3, .L1738+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L1738+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L686
	ldr	r3, .L1738+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L1738+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L1738+140
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L688
.L686:
	ldr	r3, .L1738+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L688
	ldr	r3, .L1738+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1738+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L689:
	ldr	r3, .L1738+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L688
	ldr	r3, .L1738+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
	ldr	r3, .L1738+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L688
	ldr	r3, .L1738+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L688
	ldr	r3, .L1741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
	ldr	r3, .L1741+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L688:
	ldr	r3, .L1741+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L690
	ldr	r3, .L1741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L690
	ldr	r3, .L1741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L1741+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L1741+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L1741+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L693
.L690:
	ldr	r3, .L1741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
	ldr	r3, .L1741+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L1741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L693:
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L694
	ldr	r3, .L1741+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L694
	ldr	r3, .L1741+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1741+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1741+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L697
.L694:
	ldr	r3, .L1741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L697
	ldr	r3, .L1741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L697
	ldr	r3, .L1741+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L697
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L697
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L697:
	ldr	r3, .L1741+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1741+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1741+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L702
	ldr	r3, .L1741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L702
	ldr	r3, .L1741+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L703
.L702:
	ldr	r3, .L1741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1741+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L703
.L698:
	ldr	r3, .L1741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L703
	ldr	r3, .L1741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L703
	ldr	r3, .L1741+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L703
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L703
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L703:
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L704
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L704
	ldr	r3, .L1741+28
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L704
	ldr	r3, .L1741+36
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L706
	mov	r3, #0
	mov	r4, r3
.L706:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L707
.L704:
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L707
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L708
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
.L708:
	ldr	r3, .L1741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
	ldr	r3, .L1741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L707
	ldr	r3, .L1741+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L707
	ldr	r3, .L1741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
	ldr	r3, .L1741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
	ldr	r3, .L1741+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L707:
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L709
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L709
	ldr	r3, .L1741+28
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L709
	ldr	r3, .L1741+36
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L711
.L709:
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L712
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
.L712:
	ldr	r3, .L1741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L711
	ldr	r3, .L1741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L711
	ldr	r3, .L1741+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L711
	ldr	r3, .L1741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L711
	ldr	r3, .L1741+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L711:
	ldr	r3, .L1741+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L713
	ldr	r3, .L1741+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L713
	ldr	r3, .L1741+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L713
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L713
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L713
	ldr	r3, .L1741+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L713
	ldr	r3, .L1741
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L713
	ldr	r3, .L1741+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L717
.L713:
	ldr	r3, .L1741+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1741+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1741+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L717
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1741+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L717:
	ldr	r3, .L1741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L718
	ldr	r3, .L1741+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L719
.L718:
	ldr	r3, .L1741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1741+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L719
.L720:
	ldr	r3, .L1741+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L721
	ldr	r3, .L1741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L719
.L721:
	ldr	r3, .L1741+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L719:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L723
.L722:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L724
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L724
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L723
.L724:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L725
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L723
.L725:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L726
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L723
.L726:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L727
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L723
.L727:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L723:
	ldr	r3, .L1741+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+128
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L728
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L728:
	ldr	r3, .L1741+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L729
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L729
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L729:
	ldr	r3, .L1741+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L730
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L730
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L730
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L730:
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L731
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L731:
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L738
.L735:
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L738
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L738:
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L1741+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1741+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L742
.L739:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L742
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	b	.L1742
.L1743:
	.align	2
.L1741:
	.word	_x_s7_l0
	.word	_x_s7_l1
	.word	s7_z
	.word	_x_s7_z
	.word	s7_evt1
	.word	s7_evt0
	.word	_x_s7_l2
	.word	s7_x
	.word	_x_s7_x
	.word	s7_y
	.word	_x_s7_y
	.word	s7_l2
	.word	s7_l1
	.word	s7_l0
	.word	_x_s6_evt0
	.word	_x_s6_evt1
	.word	s6_z
	.word	_x_s6_z
	.word	s6_x
	.word	_x_s6_x
	.word	s6_y
	.word	_x_s6_y
	.word	_x_s6_l2
	.word	_x_s6_l0
	.word	_x_s6_l1
	.word	s6_l2
	.word	s6_l0
	.word	s6_l1
	.word	s6_evt0
	.word	s6_evt1
	.word	_x_s5_evt0
	.word	_x_s5_evt1
	.word	1101004800
	.word	1123024896
	.word	s5_x
	.word	_x_s5_x
	.word	s5_y
	.word	_x_s5_y
	.word	s5_l2
	.word	_x_s5_l2
	.word	delta
	.word	s5_z
	.word	_x_s5_z
	.word	s5_l0
	.word	_x_s5_l0
	.word	s5_l1
	.word	_x_s5_l1
.L1742:
.L742:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L743
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L743
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L744
.L743:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L745
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L745
.L744:
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L748
.L745:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L748
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L748
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L748
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L748
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L748:
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L749
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L751
	mov	r3, #0
	mov	r4, r3
.L751:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L752
.L749:
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L752
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L752
.L753:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L752
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L752
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L752
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L752
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L752
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L752:
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L754
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L754
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L754
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L756
.L754:
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L756
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L757
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L756
.L757:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L756
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L756
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L756
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L756
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L756
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L756:
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L758
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L758
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L761
.L758:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L761
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L761
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L761
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L761
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L761:
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L762
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L762
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L762
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L762
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L762
	ldr	r3, .L1741+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L762
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L762
	ldr	r3, .L1741+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L765
.L762:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L765
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L765
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L765
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L765
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L765:
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L770
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L770
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L771
.L770:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L771
.L766:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L771
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L771
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L771
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L771
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L771:
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L772
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L774
	mov	r3, #0
	mov	r4, r3
.L774:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L775
.L772:
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L776
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
.L776:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L775
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L775
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L775:
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L777
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L779
.L777:
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L779
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L779
.L780:
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L779
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L779
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L779
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L779
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L779
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L779:
	ldr	r3, .L1741+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L781
	ldr	r3, .L1741+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L781
	ldr	r3, .L1741+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1741+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L781
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L781
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L781
	ldr	r3, .L1741+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L781
	ldr	r3, .L1741+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L781
	ldr	r3, .L1741+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L785
.L781:
	ldr	r3, .L1741+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L785
	ldr	r3, .L1741+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L785
	ldr	r3, .L1741+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L785
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L785
	ldr	r3, .L1741+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1741+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L785:
	ldr	r3, .L1741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L787
.L786:
	ldr	r3, .L1741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L787
.L788:
	ldr	r3, .L1741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L789
	ldr	r3, .L1741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L787
.L789:
	ldr	r3, .L1741+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L787:
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L790
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L790
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
.L790:
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L792
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
.L792:
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L793
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
.L793:
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L794
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L794
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L791
.L794:
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L795
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L795
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
.L795:
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L791:
	ldr	r3, .L1741+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+128
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L796
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L796
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L796
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L796:
	ldr	r3, .L1741+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L797
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L797
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L797
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L797:
	ldr	r3, .L1741+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1741+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L798
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L798
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L798
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L798:
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L799
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1741+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1741+164
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1741+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L799:
	ldr	r3, .L1741+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L1741+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1741+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+32
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L806
.L803:
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L806
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L806:
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L807
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L807
	ldr	r3, .L1744+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L1744+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L1744+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L810
.L807:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L810:
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L811
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L811
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L812
.L811:
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L813
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L813
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L813
.L812:
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L813
	ldr	r3, .L1744+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L813
	ldr	r3, .L1744+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L816
.L813:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L816
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L816
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L816:
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L817
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L817
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L817
	ldr	r3, .L1744+28
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L819
	mov	r3, #0
	mov	r4, r3
.L819:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L820
.L817:
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L820
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L820
.L821:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L820
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L820
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L820
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L820
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L820
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L820:
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L822
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L822
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L822
	ldr	r3, .L1744+28
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L824
.L822:
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L824
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L825
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L824
.L825:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L824
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L824
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L824:
	ldr	r3, .L1744+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L826
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L826
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1744+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L829
.L826:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L829
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L829
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L829
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L829
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L829:
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L830
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L830
	ldr	r3, .L1744+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1744+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1744+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L833
.L830:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L833
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L833:
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L834
	ldr	r3, .L1744+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L834
	ldr	r3, .L1744+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L834
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L838
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L838
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L839
.L838:
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L834
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L834
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L839
.L834:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L839
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L839
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L839
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L839
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L839:
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L840
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L840
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L840
	ldr	r3, .L1744+20
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L842
	mov	r3, #0
	mov	r4, r3
.L842:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L843
.L840:
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L844
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L843
.L844:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L843:
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L845
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L845
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L845
	ldr	r3, .L1744+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L847
.L845:
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L847
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L848
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L847
.L848:
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L847
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L847
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L847
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L847
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L847
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L847:
	ldr	r3, .L1744+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1744+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1744+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L849
	ldr	r3, .L1744+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L849
	ldr	r3, .L1744+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L849
	ldr	r3, .L1744+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L853
.L849:
	ldr	r3, .L1744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L853
	ldr	r3, .L1744+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L853
	ldr	r3, .L1744+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L853
	ldr	r3, .L1744+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L853
	ldr	r3, .L1744+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L853:
	ldr	r3, .L1744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1744+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L855
.L854:
	ldr	r3, .L1744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L856
	ldr	r3, .L1744+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L855
.L856:
	ldr	r3, .L1744+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L857
	ldr	r3, .L1744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L855
.L857:
	ldr	r3, .L1744+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1744+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L855:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L858
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L858
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L859
.L858:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L860
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L860
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L859
.L860:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L861
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L861
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L859
.L861:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L862
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L862
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L859
.L862:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L863
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L863
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L859
.L863:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L859:
	ldr	r3, .L1744+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L864
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L864
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L864
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L864:
	ldr	r3, .L1744+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L865
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L865
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L865:
	ldr	r3, .L1744+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmple
	b	.L1745
.L1746:
	.align	2
.L1744:
	.word	s5_l2
	.word	_x_s5_l2
	.word	delta
	.word	s5_x
	.word	_x_s5_x
	.word	s5_y
	.word	_x_s5_y
	.word	s5_z
	.word	_x_s5_z
	.word	s5_evt0
	.word	s5_evt1
	.word	_x_s5_l0
	.word	_x_s5_l1
	.word	s5_l0
	.word	s5_l1
	.word	_x_s4_evt0
	.word	_x_s4_evt1
	.word	_x_s4_y
	.word	1101004800
	.word	s4_y
	.word	1123024896
	.word	delta
	.word	s4_evt0
	.word	s4_evt1
	.word	_x_s4_l2
	.word	_x_s4_l0
	.word	_x_s4_l1
	.word	s4_l2
	.word	s4_l0
	.word	s4_l1
	.word	s4_z
	.word	_x_s4_z
	.word	s4_x
	.word	_x_s4_x
.L1745:
	mov	r3, r0
	cmp	r3, #0
	bne	.L866
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L866
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L866
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L866:
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L867
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L867:
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1744+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L874
.L871:
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L874
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L874:
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L875
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L875
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L875
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L875
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L875
	ldr	r3, .L1744+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L875
	ldr	r3, .L1744+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L875
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L878
.L875:
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L878
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L878
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L878
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L878
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L878:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L879
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L879
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L880
.L879:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L881
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L881
.L880:
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1744+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L884
.L881:
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L884
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L884
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L884
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L884
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L884:
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L885
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L885
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L887
	mov	r3, #0
	mov	r4, r3
.L887:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L888
.L885:
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L888
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L889
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L888
.L889:
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L888
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L888
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L888
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L888
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L888
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L888:
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L890
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L890
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L890
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L892
.L890:
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L893
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
.L893:
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L892
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L892
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L892
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L892:
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L894
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L894
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L894
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L894
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L894
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L894
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L894
	ldr	r3, .L1744+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L897
.L894:
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L897
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L897
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L897
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L897
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L897:
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L898
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L898
	ldr	r3, .L1744+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1744+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1744+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L901
.L898:
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L901
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L901
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L901
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L901
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L901:
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1744+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L906
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L906
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L907
.L906:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L907
.L902:
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L907
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L907
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L907
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L907
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L907:
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L908
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L908
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L908
	ldr	r3, .L1744+76
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L910
	mov	r3, #0
	mov	r4, r3
.L910:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L911
.L908:
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L911
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L912
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L911
.L912:
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L911
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L911
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L911
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L911
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L911
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L911:
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L913
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L913
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+72
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L913
	ldr	r3, .L1744+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1744+80
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L915
.L913:
	ldr	r3, .L1744+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1744+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L916
	ldr	r3, .L1744+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L915
.L916:
	ldr	r3, .L1744+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L915
	ldr	r3, .L1744+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L915
	ldr	r3, .L1744+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L915
	ldr	r3, .L1744+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1744+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L915
	ldr	r3, .L1744+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L915:
	ldr	r3, .L1744+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L917
	ldr	r3, .L1744+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1744+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L917
	ldr	r3, .L1747
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L917
	ldr	r3, .L1747+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L917
	ldr	r3, .L1747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L917
	ldr	r3, .L1747+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L917
	ldr	r3, .L1747+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L917
	ldr	r3, .L1747+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L921
.L917:
	ldr	r3, .L1747+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L921
	ldr	r3, .L1747+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L921
	ldr	r3, .L1747+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L921
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L921
	ldr	r3, .L1747+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L921:
	ldr	r3, .L1747+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L922
	ldr	r3, .L1747+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L923
.L922:
	ldr	r3, .L1747+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L924
	ldr	r3, .L1747+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L923
.L924:
	ldr	r3, .L1747+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1747+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L923
.L925:
	ldr	r3, .L1747+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L923:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L926
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L926
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L927
.L926:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L928
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L928
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L927
.L928:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L929
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L927
.L929:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L930
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L930
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L927
.L930:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L931
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L927
.L931:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L927:
	ldr	r3, .L1747+60
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+168
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L932
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L932
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L932
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L932:
	ldr	r3, .L1747+60
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L933
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L933
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L933
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L933:
	ldr	r3, .L1747+60
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L934
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L934
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L934
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L934:
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L935
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L935:
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L939
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L939
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L939
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L939
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L939
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L942
.L939:
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L942
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L942:
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L943
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L943
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L943
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L943
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L943
	ldr	r3, .L1747+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L943
	ldr	r3, .L1747+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L943
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L946
.L943:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L946
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L946
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L946
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L946
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L946:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L947
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L948
.L947:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L949
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L949
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L949
.L948:
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L949
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L949
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L952
.L949:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L952
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L952
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L952
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L952
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L952:
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+168
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L955
	mov	r3, #0
	mov	r4, r3
.L955:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L956
.L953:
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L956
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L956
.L957:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L956
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L956
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L956
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L956
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L956
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L956:
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L958
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L958
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+168
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L958
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L960
.L958:
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L960
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L961
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L961:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L960
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L960
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L960
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L960:
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L962
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L962
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L962
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L962
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L962
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L962
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L962
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L965
.L962:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L965
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L965
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L965:
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L966
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L966
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L966
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L966
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L966
	ldr	r3, .L1747+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L966
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L966
	ldr	r3, .L1747+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L969
.L966:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L969
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L969
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L969
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L969
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L969:
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	b	.L1748
.L1749:
	.align	2
.L1747:
	.word	s4_y
	.word	_x_s4_y
	.word	s4_evt1
	.word	s4_evt0
	.word	_x_s4_l2
	.word	_x_s4_l0
	.word	_x_s4_l1
	.word	s4_l2
	.word	s4_l0
	.word	s4_l1
	.word	_x_s3_evt0
	.word	_x_s3_evt1
	.word	s3_z
	.word	_x_s3_z
	.word	s3_x
	.word	_x_s3_x
	.word	s3_y
	.word	_x_s3_y
	.word	_x_s3_l2
	.word	_x_s3_l0
	.word	_x_s3_l1
	.word	s3_l2
	.word	s3_l0
	.word	s3_l1
	.word	s3_evt0
	.word	s3_evt1
	.word	_x_s2_evt0
	.word	_x_s2_evt1
	.word	delta
	.word	_x_s2_x
	.word	_x_s2_z
	.word	s2_y
	.word	_x_s2_y
	.word	s2_l2
	.word	s2_l0
	.word	s2_l1
	.word	_x_s2_l2
	.word	_x_s2_l1
	.word	_x_s2_l0
	.word	s2_evt1
	.word	s2_evt0
	.word	s2_x
	.word	1101004800
	.word	s2_z
	.word	1123024896
	.word	delta
.L1748:
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L974
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L974
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L975
.L974:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L975
.L970:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L975:
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L976
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L976
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+168
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L976
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L978
	mov	r3, #0
	mov	r4, r3
.L978:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L979
.L976:
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L979
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L980
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L979
.L980:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L979
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L979
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L979
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L979
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L979
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L979:
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L981
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L981
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+168
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L981
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L983
.L981:
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L983
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L984
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L983
.L984:
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L983
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L983
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L983
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L983
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L983
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L983:
	ldr	r3, .L1747+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L985
	ldr	r3, .L1747+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L985
	ldr	r3, .L1747+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L985
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L985
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L985
	ldr	r3, .L1747+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L985
	ldr	r3, .L1747+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L985
	ldr	r3, .L1747+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L989
.L985:
	ldr	r3, .L1747+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L989
	ldr	r3, .L1747+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L989
	ldr	r3, .L1747+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L989
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L989
	ldr	r3, .L1747+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L989:
	ldr	r3, .L1747+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L990
	ldr	r3, .L1747+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L991
.L990:
	ldr	r3, .L1747+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L992
	ldr	r3, .L1747+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L991
.L992:
	ldr	r3, .L1747+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L993
	ldr	r3, .L1747+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L991
.L993:
	ldr	r3, .L1747+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L991:
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L994
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L994
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L995
.L994:
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L996
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L996
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L995
.L996:
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L997
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L997
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L995
.L997:
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L998
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L998
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L995
.L998:
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L999
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L999
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L995
.L999:
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L995:
	ldr	r3, .L1747+116
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+168
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1000
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1000
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1000
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1000:
	ldr	r3, .L1747+116
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1001
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1001
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1001
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1001:
	ldr	r3, .L1747+116
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1002
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1002
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1002
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1002:
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+164
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1747+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L1003:
	ldr	r3, .L1747+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1007
	ldr	r3, .L1747+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1007
	ldr	r3, .L1747+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1007
	ldr	r3, .L1747+180
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+164
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1007
	ldr	r3, .L1747+180
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1007
	ldr	r3, .L1747+180
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1747+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1747+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1010
.L1007:
	ldr	r3, .L1747+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1010
	ldr	r3, .L1747+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1010:
	ldr	r3, .L1747+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1011
	ldr	r3, .L1747+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1011
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1011
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1747+116
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1011
	ldr	r3, .L1747+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1011
	ldr	r3, .L1747+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1014
.L1011:
	ldr	r3, .L1747+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1014
	ldr	r3, .L1747+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1014
	ldr	r3, .L1747+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1014
	ldr	r3, .L1747+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1014
	ldr	r3, .L1747+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1014:
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1015
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1015
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1016
.L1015:
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1017
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1017
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1017
.L1016:
	ldr	r3, .L1747+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1017
	ldr	r3, .L1747+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1017
	ldr	r3, .L1747+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1747+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1020
.L1017:
	ldr	r3, .L1747+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1020
	ldr	r3, .L1747+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1020
	ldr	r3, .L1747+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1020
	ldr	r3, .L1747+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1020
	ldr	r3, .L1747+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1747+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1020:
	ldr	r3, .L1747+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1021
	ldr	r3, .L1747+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1021
	ldr	r3, .L1747+164
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+168
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1021
	ldr	r3, .L1747+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1023
	mov	r3, #0
	mov	r4, r3
.L1023:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1024
.L1021:
	ldr	r3, .L1747+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1024
	ldr	r3, .L1747+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1025
	ldr	r3, .L1747+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1024
.L1025:
	ldr	r3, .L1747+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1024
	ldr	r3, .L1747+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1024
	ldr	r3, .L1747+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1024
	ldr	r3, .L1747+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1024
	ldr	r3, .L1747+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1024
	ldr	r3, .L1747+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1024:
	ldr	r3, .L1747+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1026
	ldr	r3, .L1747+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1026
	ldr	r3, .L1747+164
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+168
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1026
	ldr	r3, .L1747+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L1747+176
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1028
.L1026:
	ldr	r3, .L1747+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1028
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1029
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1028
.L1029:
	ldr	r3, .L1750+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1028
	ldr	r3, .L1750+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1028
	ldr	r3, .L1750+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1028
	ldr	r3, .L1750+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1028
	ldr	r3, .L1750+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1028
	ldr	r3, .L1750+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1028:
	ldr	r3, .L1750+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1030
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1030
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1030
	ldr	r3, .L1750+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1030
	ldr	r3, .L1750+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1030
	ldr	r3, .L1750+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1030
	ldr	r3, .L1750+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1030
	ldr	r3, .L1750+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1033
.L1030:
	ldr	r3, .L1750+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1033
	ldr	r3, .L1750+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1033
	ldr	r3, .L1750+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1033
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1033
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1033:
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1034
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1034
	ldr	r3, .L1750+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1034
	ldr	r3, .L1750+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1034
	ldr	r3, .L1750+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1034
	ldr	r3, .L1750+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1034
	ldr	r3, .L1750+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1034
	ldr	r3, .L1750+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1037
.L1034:
	ldr	r3, .L1750+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1037
	ldr	r3, .L1750+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1037
	ldr	r3, .L1750+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1037
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1037
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1037:
	ldr	r3, .L1750+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1038
	ldr	r3, .L1750+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1038
	ldr	r3, .L1750+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1038
	ldr	r3, .L1750+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1042
	ldr	r3, .L1750+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1042
	ldr	r3, .L1750+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1043
.L1042:
	ldr	r3, .L1750+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1038
	ldr	r3, .L1750+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1038
	ldr	r3, .L1750+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1043
.L1038:
	ldr	r3, .L1750+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1043
	ldr	r3, .L1750+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1043
	ldr	r3, .L1750+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1043
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1043
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1043:
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1044
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1044
	ldr	r3, .L1750+40
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1044
	ldr	r3, .L1750+48
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1046
	mov	r3, #0
	mov	r4, r3
.L1046:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1047
.L1044:
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1047
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1048
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1047
.L1048:
	ldr	r3, .L1750+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1047
	ldr	r3, .L1750+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1047
	ldr	r3, .L1750+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1047
	ldr	r3, .L1750+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1047
	ldr	r3, .L1750+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1047
	ldr	r3, .L1750+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1047:
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1049
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1049
	ldr	r3, .L1750+40
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1049
	ldr	r3, .L1750+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1051
.L1049:
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1051
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1052
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1051
.L1052:
	ldr	r3, .L1750+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1051
	ldr	r3, .L1750+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1051
	ldr	r3, .L1750+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1051
	ldr	r3, .L1750+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1051
	ldr	r3, .L1750+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1051
	ldr	r3, .L1750+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1051:
	ldr	r3, .L1750+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1053
	ldr	r3, .L1750+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1053
	ldr	r3, .L1750+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1053
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1053
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1053
	ldr	r3, .L1750+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1053
	ldr	r3, .L1750+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1053
	ldr	r3, .L1750+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1057
.L1053:
	ldr	r3, .L1750+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1057
	ldr	r3, .L1750+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1057
	ldr	r3, .L1750+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1057
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1057
	ldr	r3, .L1750
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1057:
	ldr	r3, .L1750+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1058
	ldr	r3, .L1750+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1059
.L1058:
	ldr	r3, .L1750+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1060
	ldr	r3, .L1750+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1059
.L1060:
	ldr	r3, .L1750+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1061
	ldr	r3, .L1750+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1059
.L1061:
	ldr	r3, .L1750+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1059:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1062
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1062
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1063
.L1062:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1064
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1064
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1063
.L1064:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1065
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1065
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1063
.L1065:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1066
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1066
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1063
.L1066:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1067
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1067
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1063
.L1067:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1063:
	ldr	r3, .L1750+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+128
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1068
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1068
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1068
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1068:
	ldr	r3, .L1750+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1069
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1069
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1069:
	ldr	r3, .L1750+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1070
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1070
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1070
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1070:
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1071
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L1071:
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1075
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1075
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1075
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1075
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1075
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1078
.L1075:
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1078
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1078:
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1079
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1079
	ldr	r3, .L1750+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1750+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1082
.L1079:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1082
	b	.L1751
.L1752:
	.align	2
.L1750:
	.word	s2_evt0
	.word	s2_evt1
	.word	s2_l2
	.word	s2_l0
	.word	s2_l1
	.word	_x_s2_l2
	.word	_x_s2_l0
	.word	_x_s2_l1
	.word	s2_z
	.word	_x_s2_z
	.word	s2_x
	.word	_x_s2_x
	.word	s2_y
	.word	_x_s2_y
	.word	_x_s1_evt0
	.word	_x_s1_evt1
	.word	s1_z
	.word	_x_s1_z
	.word	s1_x
	.word	_x_s1_x
	.word	s1_y
	.word	_x_s1_y
	.word	_x_s1_l2
	.word	_x_s1_l0
	.word	_x_s1_l1
	.word	s1_l2
	.word	s1_l0
	.word	s1_l1
	.word	s1_evt0
	.word	s1_evt1
	.word	_x_s0_evt0
	.word	_x_s0_evt1
	.word	1101004800
	.word	1123024896
	.word	s0_x
	.word	_x_s0_x
	.word	s0_y
	.word	_x_s0_y
	.word	_x_s0_l0
	.word	s0_l1
	.word	_x_s0_l1
	.word	s0_l2
	.word	_x_s0_l2
	.word	delta
	.word	s0_z
	.word	_x_s0_z
	.word	s0_l0
.L1751:
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1082
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1082
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1082
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1082:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1083
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1083
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1084
.L1083:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1085
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1085
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1085
.L1084:
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1085
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1085
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1088
.L1085:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1088
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1088
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1088
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1088
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1088:
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1089
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1089
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1089
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1091
	mov	r3, #0
	mov	r4, r3
.L1091:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1092
.L1089:
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1092
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1093
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1092
.L1093:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1092
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1092
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1092
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1092
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1092
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1092:
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1094
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1094
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1094
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1096
.L1094:
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1096
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1097
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1096
.L1097:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1096
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1096
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1096
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1096
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1096
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1096:
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1098
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1098
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1098
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1098
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1098
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1098
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1098
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1101
.L1098:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1101
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1101
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1101
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1101
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1101:
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1102
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1102
	ldr	r3, .L1750+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1750+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1105
.L1102:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1105
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1105
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1105
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1105:
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1106
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1106
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1106
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1110
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1110
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1111
.L1110:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1106
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1106
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1111
.L1106:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1111
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1111
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1111
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1111
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1111:
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1112
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1114
	mov	r3, #0
	mov	r4, r3
.L1114:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1115
.L1112:
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1115
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1116
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1115
.L1116:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1115
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1115
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1115
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1115
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1115
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1115:
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1117
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1117
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+128
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1117
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1119
.L1117:
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1119
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1120
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1119
.L1120:
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1119
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1119
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1119
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1119
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1119
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1119:
	ldr	r3, .L1750+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1121
	ldr	r3, .L1750+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1121
	ldr	r3, .L1750+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1750+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1121
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1121
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1121
	ldr	r3, .L1750+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1121
	ldr	r3, .L1750+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1121
	ldr	r3, .L1750+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1125
.L1121:
	ldr	r3, .L1750+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1125
	ldr	r3, .L1750+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1125
	ldr	r3, .L1750+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1125
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1125
	ldr	r3, .L1750+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1750+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1125:
	ldr	r3, .L1750+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1126
	ldr	r3, .L1750+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1126:
	ldr	r3, .L1750+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1128
	ldr	r3, .L1750+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1128:
	ldr	r3, .L1750+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1129
	ldr	r3, .L1750+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1129:
	ldr	r3, .L1750+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1127:
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1130
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1130
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1131
.L1130:
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1132
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1132
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1131
.L1132:
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1133
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1133
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1131
.L1133:
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1134
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1134
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1131
.L1134:
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1135
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1131
.L1135:
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1131:
	ldr	r3, .L1750+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+128
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1136
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1136
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1136
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1136:
	ldr	r3, .L1750+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1137
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1137
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1137
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1137:
	ldr	r3, .L1750+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L1750+132
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1138
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1138
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1138:
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1139
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1750+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1750+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1750+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1750+180
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L1139:
	ldr	r3, .L1750+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1143
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1143
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1143
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1753+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1143
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1753+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1753+32
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1143
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1753+36
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1753+40
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1146
.L1143:
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1146
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1146:
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1147
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1147
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1147
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1147
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1147
	ldr	r3, .L1753+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1147
	ldr	r3, .L1753+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1147
	ldr	r3, .L1753+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1150
.L1147:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1150
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1150
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1150
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1150
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1150:
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1151
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1151
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1152
.L1151:
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1153
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1153
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1153
.L1152:
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1153
	ldr	r3, .L1753+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1153
	ldr	r3, .L1753+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1156
.L1153:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1156
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1156
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1156
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1156
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1156:
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1157
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1157
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1753+48
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1157
	ldr	r3, .L1753+36
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1753+52
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1159
	mov	r3, #0
	mov	r4, r3
.L1159:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1160
.L1157:
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1160
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1161
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1160
.L1161:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1160
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1160
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1160
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1160
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1160
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1160:
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1162
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1162
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1753+48
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1162
	ldr	r3, .L1753+36
	ldr	r3, [r3]	@ float
	ldr	r1, .L1753+52
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1164
.L1162:
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1164
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1165
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1164
.L1165:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1164
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1164
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1164
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1164
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1164
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1164:
	ldr	r3, .L1753+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1166
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1166
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1753+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1169
.L1166:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1169
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1169
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1169
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1169
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1169:
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1170
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1170
	ldr	r3, .L1753+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1753+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1753+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1173
.L1170:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1173
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1173
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1173
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1173
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1173:
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1753+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1753+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1178
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1178
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1179
.L1178:
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1179
.L1174:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1179
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1179
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1179
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1179
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1179:
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1180
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1180
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1753+48
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1180
	ldr	r3, .L1753+28
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1753+52
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1182
	mov	r3, #0
	mov	r4, r3
.L1182:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1183
.L1180:
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1183
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1184
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1183
.L1184:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1183
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1183
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1183
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1183
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1183
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1183:
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1185
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1753+48
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L1185
	ldr	r3, .L1753+28
	ldr	r3, [r3]	@ float
	ldr	r1, .L1753+52
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1187
.L1185:
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1187
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1188
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1187
.L1188:
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1187
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1187
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1187
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1187
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1187
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1187:
	ldr	r3, .L1753+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1189
	ldr	r3, .L1753+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1189
	ldr	r3, .L1753+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1189
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1189
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1189
	ldr	r3, .L1753+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1189
	ldr	r3, .L1753
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1189
	ldr	r3, .L1753+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1193
.L1189:
	ldr	r3, .L1753+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1193
	ldr	r3, .L1753+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1193
	ldr	r3, .L1753+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1193
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1193
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
.L1193:
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L1194
	ldr	r3, .L1753+56
	ldr	r3, [r3]
	cmp	r3, #13
	bne	.L245
.L1194:
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L1195
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #13
	bne	.L245
.L1195:
	ldr	r3, .L1753+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1196
	ldr	r3, .L1753+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	b	.L1754
.L1755:
	.align	2
.L1753:
	.word	_x_s0_l0
	.word	s0_l1
	.word	_x_s0_l1
	.word	s0_l2
	.word	_x_s0_l2
	.word	s0_x
	.word	_x_s0_x
	.word	s0_y
	.word	_x_s0_y
	.word	s0_z
	.word	_x_s0_z
	.word	s0_l0
	.word	1101004800
	.word	1123024896
	.word	_x_r_evt_id
	.word	r_x
	.word	_x_r_l
	.word	_x_r_counter
	.word	_x_r_x
	.word	delta
	.word	r_l
	.word	r_counter
	.word	_x_delta
	.word	s13_evt0
	.word	s13_evt1
	.word	s12_evt0
	.word	s12_evt1
	.word	s11_evt0
	.word	s11_evt1
	.word	s10_evt0
	.word	s10_evt1
	.word	s9_evt0
	.word	s9_evt1
	.word	s8_evt0
	.word	s8_evt1
	.word	s7_evt0
	.word	s7_evt1
	.word	s0_evt0
	.word	s0_evt1
	.word	s1_evt0
	.word	s1_evt1
	.word	s2_evt0
	.word	s2_evt1
	.word	s3_evt0
	.word	s3_evt1
	.word	s4_evt0
	.word	s4_evt1
	.word	s5_evt0
	.word	s5_evt1
	.word	s6_evt1
	.word	s6_evt0
	.word	r_event0
	.word	r_event1
	.word	r_evt_id
	.word	delta
.L1754:
	beq	.L245
.L1196:
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1198
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1753+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1753+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1753+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1753+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1753+84
	ldr	r2, [r3]
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L245
.L1198:
	ldr	r3, .L1753+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1753+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1200
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1753+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1753+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1200
	ldr	r3, .L1753+84
	ldr	r2, [r3]
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L1202
.L1200:
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1202
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
.L1202:
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1203
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1203
	ldr	r3, .L1753+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L1203
	ldr	r3, .L1753+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1203
	ldr	r3, .L1753+212
	ldr	r2, [r3]
	ldr	r3, .L1753+84
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L1203
	ldr	r3, .L1753+84
	ldr	r2, [r3]
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L1203
	ldr	r3, .L1753+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1753+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1205
.L1203:
	ldr	r3, .L1753+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1205
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1206
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1205
.L1206:
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L245
.L1205:
	ldr	r3, .L1753+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1208
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1208
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1208
	ldr	r3, .L1753+212
	ldr	r2, [r3]
	ldr	r3, .L1753+84
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L1208
	ldr	r3, .L1753+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1208
	ldr	r3, .L1753+84
	ldr	r2, [r3]
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L1210
.L1208:
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1211
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1210
.L1211:
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1210
	ldr	r3, .L1753+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1210
	ldr	r3, .L1753+84
	ldr	r3, [r3]
	cmp	r3, #12
	ble	.L245
.L1210:
	ldr	r3, .L1753+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1212
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1212
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1212
	ldr	r3, .L1753+212
	ldr	r2, [r3]
	ldr	r3, .L1753+84
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L1212
	ldr	r3, .L1753+68
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L1212
	ldr	r3, .L1753+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1213
.L1212:
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1214
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1213
.L1214:
	ldr	r3, .L1753+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1213
	ldr	r3, .L1753+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1213
	ldr	r3, .L1753+84
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L245
.L1213:
	ldr	r3, .L1753+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1753+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1216
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L245
.L1216:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1218
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1219
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1219
	mov	r3, #1
	b	.L1220
.L1219:
	mov	r3, #0
.L1220:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1221
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1221
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L1221
	mov	r3, #1
	b	.L1222
.L1221:
	mov	r3, #0
.L1222:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1218:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1223
	ldr	r3, .L1753+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1224
	ldr	r3, .L1753+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1224
	mov	r3, #1
	b	.L1225
.L1224:
	mov	r3, #0
.L1225:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1226
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1226
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L1226
	mov	r3, #1
	b	.L1227
.L1226:
	mov	r3, #0
.L1227:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1223:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1228
	ldr	r3, .L1753+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1229
	ldr	r3, .L1753+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1229
	mov	r3, #1
	b	.L1230
.L1229:
	mov	r3, #0
.L1230:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1231
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1231
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L1231
	mov	r3, #1
	b	.L1232
.L1231:
	mov	r3, #0
.L1232:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1228:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1233
	ldr	r3, .L1753+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1234
	ldr	r3, .L1753+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1234
	mov	r3, #1
	b	.L1235
.L1234:
	mov	r3, #0
.L1235:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1236
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1236
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L1236
	mov	r3, #1
	b	.L1237
.L1236:
	mov	r3, #0
.L1237:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1233:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1238
	ldr	r3, .L1753+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1239
	ldr	r3, .L1753+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1239
	mov	r3, #1
	b	.L1240
.L1239:
	mov	r3, #0
.L1240:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1241
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1241
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L1241
	mov	r3, #1
	b	.L1242
.L1241:
	mov	r3, #0
.L1242:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1238:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1243
	ldr	r3, .L1753+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1244
	ldr	r3, .L1753+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1244
	mov	r3, #1
	b	.L1245
.L1244:
	mov	r3, #0
.L1245:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1246
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1246
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L1246
	mov	r3, #1
	b	.L1247
.L1246:
	mov	r3, #0
.L1247:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1243:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1248
	ldr	r3, .L1753+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1249
	ldr	r3, .L1753+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1249
	mov	r3, #1
	b	.L1250
.L1249:
	mov	r3, #0
.L1250:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1251
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1251
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L1251
	mov	r3, #1
	b	.L1252
.L1251:
	mov	r3, #0
.L1252:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1248:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1253
	ldr	r3, .L1753+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1254
	ldr	r3, .L1753+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1254
	mov	r3, #1
	b	.L1255
.L1254:
	mov	r3, #0
.L1255:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1256
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1256
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L1256
	mov	r3, #1
	b	.L1257
.L1256:
	mov	r3, #0
.L1257:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1253:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1258
	ldr	r3, .L1753+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1259
	ldr	r3, .L1753+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1259
	mov	r3, #1
	b	.L1260
.L1259:
	mov	r3, #0
.L1260:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1261
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1261
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #4
	bne	.L1261
	mov	r3, #1
	b	.L1262
.L1261:
	mov	r3, #0
.L1262:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1258:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1263
	ldr	r3, .L1753+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1264
	ldr	r3, .L1753+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1264
	mov	r3, #1
	b	.L1265
.L1264:
	mov	r3, #0
.L1265:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1266
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1266
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #4
	bne	.L1266
	mov	r3, #1
	b	.L1267
.L1266:
	mov	r3, #0
.L1267:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1263:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1268
	ldr	r3, .L1753+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1269
	ldr	r3, .L1753+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1269
	mov	r3, #1
	b	.L1270
.L1269:
	mov	r3, #0
.L1270:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1271
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1271
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #5
	bne	.L1271
	mov	r3, #1
	b	.L1272
.L1271:
	mov	r3, #0
.L1272:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1268:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1273
	ldr	r3, .L1753+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1274
	ldr	r3, .L1753+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1274
	mov	r3, #1
	b	.L1275
.L1274:
	mov	r3, #0
.L1275:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1276
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1276
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #5
	bne	.L1276
	mov	r3, #1
	b	.L1277
.L1276:
	mov	r3, #0
.L1277:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1273:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1278
	ldr	r3, .L1753+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1279
	ldr	r3, .L1753+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1279
	mov	r3, #1
	b	.L1280
.L1279:
	mov	r3, #0
.L1280:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1753+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1281
	ldr	r3, .L1753+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1281
	ldr	r3, .L1753+212
	ldr	r3, [r3]
	cmp	r3, #6
	bne	.L1281
	mov	r3, #1
	b	.L1282
.L1281:
	mov	r3, #0
.L1282:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1278:
	ldr	r3, .L1753+216
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1283
	ldr	r3, .L1756+900
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1284
	ldr	r3, .L1756+404
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1284
	mov	r3, #1
	b	.L1285
.L1284:
	mov	r3, #0
.L1285:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1286
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1286
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #6
	bne	.L1286
	mov	r3, #1
	b	.L1287
.L1286:
	mov	r3, #0
.L1287:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1283:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1288
	ldr	r3, .L1756+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1289
	ldr	r3, .L1756+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1289
	mov	r3, #1
	b	.L1290
.L1289:
	mov	r3, #0
.L1290:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1291
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1291
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L1291
	mov	r3, #1
	b	.L1292
.L1291:
	mov	r3, #0
.L1292:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1288:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1293
	ldr	r3, .L1756+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1294
	ldr	r3, .L1756+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1294
	mov	r3, #1
	b	.L1295
.L1294:
	mov	r3, #0
.L1295:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1296
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1296
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L1296
	mov	r3, #1
	b	.L1297
.L1296:
	mov	r3, #0
.L1297:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1293:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1298
	ldr	r3, .L1756+828
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1299
	ldr	r3, .L1756+628
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1299
	mov	r3, #1
	b	.L1300
.L1299:
	mov	r3, #0
.L1300:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1301
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1301
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #8
	bne	.L1301
	mov	r3, #1
	b	.L1302
.L1301:
	mov	r3, #0
.L1302:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1298:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1303
	ldr	r3, .L1756+628
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1304
	ldr	r3, .L1756+828
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1304
	mov	r3, #1
	b	.L1305
.L1304:
	mov	r3, #0
.L1305:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1306
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1306
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #8
	bne	.L1306
	mov	r3, #1
	b	.L1307
.L1306:
	mov	r3, #0
.L1307:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1303:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1308
	ldr	r3, .L1756+644
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1309
	ldr	r3, .L1756+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1309
	mov	r3, #1
	b	.L1310
.L1309:
	mov	r3, #0
.L1310:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1311
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1311
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #9
	bne	.L1311
	mov	r3, #1
	b	.L1312
.L1311:
	mov	r3, #0
.L1312:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1308:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1313
	ldr	r3, .L1756+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1314
	ldr	r3, .L1756+644
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1314
	mov	r3, #1
	b	.L1315
.L1314:
	mov	r3, #0
.L1315:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1316
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1316
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #9
	bne	.L1316
	mov	r3, #1
	b	.L1317
.L1316:
	mov	r3, #0
.L1317:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1313:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1318
	ldr	r3, .L1756+572
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1319
	ldr	r3, .L1756+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1319
	mov	r3, #1
	b	.L1320
.L1319:
	mov	r3, #0
.L1320:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1321
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1321
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #10
	bne	.L1321
	mov	r3, #1
	b	.L1322
.L1321:
	mov	r3, #0
.L1322:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1318:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1323
	ldr	r3, .L1756+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1324
	ldr	r3, .L1756+572
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1324
	mov	r3, #1
	b	.L1325
.L1324:
	mov	r3, #0
.L1325:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1326
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1326
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #10
	bne	.L1326
	mov	r3, #1
	b	.L1327
.L1326:
	mov	r3, #0
.L1327:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1323:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1328
	ldr	r3, .L1756+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1329
	ldr	r3, .L1756+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1329
	mov	r3, #1
	b	.L1330
.L1329:
	mov	r3, #0
.L1330:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1331
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1331
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #11
	bne	.L1331
	mov	r3, #1
	b	.L1332
.L1331:
	mov	r3, #0
.L1332:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1328:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1333
	ldr	r3, .L1756+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1334
	ldr	r3, .L1756+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1334
	mov	r3, #1
	b	.L1335
.L1334:
	mov	r3, #0
.L1335:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1336
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1336
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #11
	bne	.L1336
	mov	r3, #1
	b	.L1337
.L1336:
	mov	r3, #0
.L1337:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1333:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1338
	ldr	r3, .L1756+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1339
	ldr	r3, .L1756+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1339
	mov	r3, #1
	b	.L1340
.L1339:
	mov	r3, #0
.L1340:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1341
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1341
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #12
	bne	.L1341
	mov	r3, #1
	b	.L1342
.L1341:
	mov	r3, #0
.L1342:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1338:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1343
	ldr	r3, .L1756+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1344
	ldr	r3, .L1756+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1344
	mov	r3, #1
	b	.L1345
.L1344:
	mov	r3, #0
.L1345:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1346
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1346
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #12
	bne	.L1346
	mov	r3, #1
	b	.L1347
.L1346:
	mov	r3, #0
.L1347:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1343:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1348
	ldr	r3, .L1756+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1349
	ldr	r3, .L1756+596
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1349
	mov	r3, #1
	b	.L1350
.L1349:
	mov	r3, #0
.L1350:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1351
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1351
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #13
	bne	.L1351
	mov	r3, #1
	b	.L1352
.L1351:
	mov	r3, #0
.L1352:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1348:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1353
	ldr	r3, .L1756+596
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1354
	ldr	r3, .L1756+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1354
	mov	r3, #1
	b	.L1355
.L1354:
	mov	r3, #0
.L1355:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1756+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1356
	ldr	r3, .L1756+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1356
	ldr	r3, .L1756+468
	ldr	r3, [r3]
	cmp	r3, #13
	bne	.L1356
	mov	r3, #1
	b	.L1357
.L1356:
	mov	r3, #0
.L1357:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1353:
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1358
	ldr	r3, .L1756+52
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1359
	mov	r3, #0
	mov	r4, r3
.L1359:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L245
.L1358:
	ldr	r3, .L1756+52
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1360
	ldr	r3, .L1756+444
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1756+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1756+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L245
.L1360:
	mov	r3, #1
	b	.L1362
.L1757:
	.align	2
.L1756:
	.word	_x_s13_z
	.word	s13_z
	.word	_x_s13_y
	.word	s13_y
	.word	_x_s13_x
	.word	s13_x
	.word	_x_s12_z
	.word	s12_z
	.word	_x_s12_y
	.word	s12_y
	.word	_x_s12_x
	.word	s12_x
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_s11_z
	.word	s11_z
	.word	_x_s11_y
	.word	s11_y
	.word	_x_s11_x
	.word	s11_x
	.word	_x_s10_z
	.word	s10_z
	.word	_x_s10_y
	.word	s10_y
	.word	_x_s10_x
	.word	s10_x
	.word	_x_s9_z
	.word	s9_z
	.word	_x_s9_y
	.word	s9_y
	.word	_x_s9_x
	.word	s9_x
	.word	_x_s8_z
	.word	s8_z
	.word	_x_s8_y
	.word	s8_y
	.word	_x_s8_x
	.word	s8_x
	.word	_x_s13_l2
	.word	s13_l2
	.word	_x_s7_z
	.word	s7_z
	.word	_x_s13_l1
	.word	s13_l1
	.word	_x_s7_y
	.word	s7_y
	.word	_x_s13_l0
	.word	s13_l0
	.word	_x_s7_x
	.word	s7_x
	.word	_x_r_event1
	.word	r_event1
	.word	_x_s8_l2
	.word	s8_l2
	.word	_x_s2_z
	.word	s2_z
	.word	_x_s11_l1
	.word	s11_l1
	.word	_x_s5_y
	.word	s5_y
	.word	_x_s1_l2
	.word	s1_l2
	.word	_x_s7_evt1
	.word	s7_evt1
	.word	_x_s4_l1
	.word	s4_l1
	.word	_x_s7_evt0
	.word	s7_evt0
	.word	_x_s4_l0
	.word	s4_l0
	.word	_x_s12_l2
	.word	s12_l2
	.word	_x_s6_z
	.word	s6_z
	.word	_x_s1_evt0
	.word	s1_evt0
	.word	_x_s7_l2
	.word	s7_l2
	.word	_x_s1_z
	.word	s1_z
	.word	_x_r_l
	.word	r_l
	.word	_x_s13_evt1
	.word	s13_evt1
	.word	_x_s10_l1
	.word	s10_l1
	.word	_x_s4_y
	.word	s4_y
	.word	_x_s11_evt1
	.word	s11_evt1
	.word	_x_s8_l1
	.word	s8_l1
	.word	_x_s2_y
	.word	s2_y
	.word	_x_s11_l0
	.word	s11_l0
	.word	_x_s5_x
	.word	s5_x
	.word	_x_s0_l2
	.word	s0_l2
	.word	_x_s6_evt1
	.word	s6_evt1
	.word	_x_s3_l1
	.word	s3_l1
	.word	_x_s11_evt0
	.word	s11_evt0
	.word	_x_s8_l0
	.word	s8_l0
	.word	_x_s2_x
	.word	s2_x
	.word	_x_delta
	.word	delta
	.word	_x_s0_evt1
	.word	s0_evt1
	.word	_x_s2_evt0
	.word	s2_evt0
	.word	_x_r_evt_id
	.word	r_evt_id
	.word	_x_s10_l2
	.word	s10_l2
	.word	_x_s4_z
	.word	s4_z
	.word	_x_s10_evt0
	.word	s10_evt0
	.word	_x_s7_l0
	.word	s7_l0
	.word	_x_s1_x
	.word	s1_x
	.word	_x_s2_evt1
	.word	s2_evt1
	.word	_x_r_counter
	.word	r_counter
	.word	_x_s5_evt0
	.word	s5_evt0
	.word	_x_s2_l0
	.word	s2_l0
	.word	_x_s9_evt0
	.word	s9_evt0
	.word	_x_s6_l0
	.word	s6_l0
	.word	_x_s0_x
	.word	s0_x
	.word	_x_s10_evt1
	.word	s10_evt1
	.word	_x_s7_l1
	.word	s7_l1
	.word	_x_s1_y
	.word	s1_y
	.word	_x_s13_evt0
	.word	s13_evt0
	.word	_x_s10_l0
	.word	s10_l0
	.word	_x_s4_x
	.word	s4_x
	.word	_x_r_x
	.word	r_x
	.word	_x_s8_evt0
	.word	s8_evt0
	.word	_x_s5_l0
	.word	s5_l0
	.word	_x_s9_evt1
	.word	s9_evt1
	.word	_x_s6_l1
	.word	s6_l1
	.word	_x_s0_y
	.word	s0_y
	.word	_x_s12_evt0
	.word	s12_evt0
	.word	_x_s9_l0
	.word	s9_l0
	.word	_x_s3_x
	.word	s3_x
	.word	_x_r_event0
	.word	r_event0
	.word	_x_s6_l2
	.word	s6_l2
	.word	_x_s0_z
	.word	s0_z
	.word	_x_s12_evt1
	.word	s12_evt1
	.word	_x_s9_l1
	.word	s9_l1
	.word	_x_s3_y
	.word	s3_y
	.word	_x_s12_l0
	.word	s12_l0
	.word	_x_s6_x
	.word	s6_x
	.word	_x_s0_evt0
	.word	s0_evt0
	.word	_x_s1_evt1
	.word	s1_evt1
	.word	_x_s1_l0
	.word	s1_l0
	.word	_x_s4_evt0
	.word	s4_evt0
	.word	_x_s3_evt0
	.word	s3_evt0
	.word	_x_s0_l0
	.word	s0_l0
	.word	_x_s11_l2
	.word	s11_l2
	.word	_x_s5_z
	.word	s5_z
	.word	_x_s2_l2
	.word	s2_l2
	.word	_x_s8_evt1
	.word	s8_evt1
	.word	_x_s5_l1
	.word	s5_l1
	.word	_x_s9_l2
	.word	s9_l2
	.word	_x_s3_z
	.word	s3_z
	.word	_x_s12_l1
	.word	s12_l1
	.word	_x_s6_y
	.word	s6_y
	.word	_x_s0_l1
	.word	s0_l1
	.word	_x_s3_evt1
	.word	s3_evt1
	.word	_x_s3_l0
	.word	s3_l0
	.word	_x_s6_evt0
	.word	s6_evt0
	.word	_x_s3_l2
	.word	s3_l2
	.word	_x_s1_l1
	.word	s1_l1
	.word	_x_s4_evt1
	.word	s4_evt1
	.word	_x_s4_l2
	.word	s4_l2
	.word	_x_s2_l1
	.word	s2_l1
	.word	_x_s5_evt1
	.word	s5_evt1
	.word	_x_s5_l2
	.word	s5_l2
.L245:
	mov	r3, #0
.L1362:
	str	r3, [fp, #-24]
	ldr	r3, .L1756
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+4
	str	r3, [r2]	@ float
	ldr	r3, .L1756+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+12
	str	r3, [r2]	@ float
	ldr	r3, .L1756+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+20
	str	r3, [r2]	@ float
	ldr	r3, .L1756+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+28
	str	r3, [r2]	@ float
	ldr	r3, .L1756+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+36
	str	r3, [r2]	@ float
	ldr	r3, .L1756+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+44
	str	r3, [r2]	@ float
	ldr	r3, .L1756+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+52
	str	r3, [r2]	@ float
	ldr	r3, .L1756+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+60
	str	r3, [r2]	@ float
	ldr	r3, .L1756+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+68
	str	r3, [r2]	@ float
	ldr	r3, .L1756+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+76
	str	r3, [r2]	@ float
	ldr	r3, .L1756+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+84
	str	r3, [r2]	@ float
	ldr	r3, .L1756+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+92
	str	r3, [r2]	@ float
	ldr	r3, .L1756+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+100
	str	r3, [r2]	@ float
	ldr	r3, .L1756+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+108
	str	r3, [r2]	@ float
	ldr	r3, .L1756+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+116
	str	r3, [r2]	@ float
	ldr	r3, .L1756+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+124
	str	r3, [r2]	@ float
	ldr	r3, .L1756+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+132
	str	r3, [r2]	@ float
	ldr	r3, .L1756+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+140
	str	r3, [r2]	@ float
	ldr	r3, .L1756+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+148
	str	r3, [r2]	@ float
	ldr	r3, .L1756+152
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+156
	strb	r2, [r3]
	ldr	r3, .L1756+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+164
	str	r3, [r2]	@ float
	ldr	r3, .L1756+168
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+172
	strb	r2, [r3]
	ldr	r3, .L1756+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+180
	str	r3, [r2]	@ float
	ldr	r3, .L1756+184
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+188
	strb	r2, [r3]
	ldr	r3, .L1756+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+196
	str	r3, [r2]	@ float
	ldr	r3, .L1756+200
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+204
	strb	r2, [r3]
	ldr	r3, .L1756+208
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+212
	strb	r2, [r3]
	ldr	r3, .L1756+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+220
	str	r3, [r2]	@ float
	ldr	r3, .L1756+224
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+228
	strb	r2, [r3]
	ldr	r3, .L1756+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+236
	str	r3, [r2]	@ float
	ldr	r3, .L1756+240
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+244
	strb	r2, [r3]
	ldr	r3, .L1756+248
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+252
	strb	r2, [r3]
	ldr	r3, .L1756+256
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+260
	strb	r2, [r3]
	ldr	r3, .L1756+264
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+268
	strb	r2, [r3]
	ldr	r3, .L1756+272
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+276
	strb	r2, [r3]
	ldr	r3, .L1756+280
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+284
	strb	r2, [r3]
	ldr	r3, .L1756+288
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+292
	str	r3, [r2]	@ float
	ldr	r3, .L1756+296
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+300
	strb	r2, [r3]
	ldr	r3, .L1756+304
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+308
	strb	r2, [r3]
	ldr	r3, .L1756+312
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+316
	str	r3, [r2]	@ float
	ldr	r3, .L1756+320
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+324
	strb	r2, [r3]
	ldr	r3, .L1756+328
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+332
	strb	r2, [r3]
	ldr	r3, .L1756+336
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+340
	strb	r2, [r3]
	ldr	r3, .L1756+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+348
	str	r3, [r2]	@ float
	ldr	r3, .L1756+352
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+356
	strb	r2, [r3]
	ldr	r3, .L1756+360
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+364
	strb	r2, [r3]
	ldr	r3, .L1756+368
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+372
	str	r3, [r2]	@ float
	ldr	r3, .L1756+376
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+380
	strb	r2, [r3]
	ldr	r3, .L1756+384
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+388
	str	r3, [r2]	@ float
	ldr	r3, .L1756+392
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+396
	strb	r2, [r3]
	ldr	r3, .L1756+400
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+404
	strb	r2, [r3]
	ldr	r3, .L1756+408
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+412
	strb	r2, [r3]
	ldr	r3, .L1756+416
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+420
	strb	r2, [r3]
	ldr	r3, .L1756+424
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+428
	strb	r2, [r3]
	ldr	r3, .L1756+432
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+436
	str	r3, [r2]	@ float
	ldr	r3, .L1756+440
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+444
	str	r3, [r2]	@ float
	ldr	r3, .L1756+448
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+452
	strb	r2, [r3]
	ldr	r3, .L1756+456
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+460
	strb	r2, [r3]
	ldr	r3, .L1756+464
	ldr	r3, [r3]
	ldr	r2, .L1756+468
	str	r3, [r2]
	ldr	r3, .L1756+472
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+476
	strb	r2, [r3]
	ldr	r3, .L1756+480
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+484
	str	r3, [r2]	@ float
	ldr	r3, .L1756+488
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+492
	strb	r2, [r3]
	ldr	r3, .L1756+496
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+500
	strb	r2, [r3]
	ldr	r3, .L1756+504
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+508
	str	r3, [r2]	@ float
	ldr	r3, .L1756+512
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+516
	strb	r2, [r3]
	ldr	r3, .L1756+520
	ldr	r3, [r3]
	ldr	r2, .L1756+524
	str	r3, [r2]
	ldr	r3, .L1756+528
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+532
	strb	r2, [r3]
	ldr	r3, .L1756+536
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+540
	strb	r2, [r3]
	ldr	r3, .L1756+544
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+548
	strb	r2, [r3]
	ldr	r3, .L1756+552
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+556
	strb	r2, [r3]
	ldr	r3, .L1756+560
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+564
	str	r3, [r2]	@ float
	ldr	r3, .L1756+568
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+572
	strb	r2, [r3]
	ldr	r3, .L1756+576
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+580
	strb	r2, [r3]
	ldr	r3, .L1756+584
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+588
	str	r3, [r2]	@ float
	ldr	r3, .L1756+592
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+596
	strb	r2, [r3]
	ldr	r3, .L1756+600
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+604
	strb	r2, [r3]
	ldr	r3, .L1756+608
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+612
	str	r3, [r2]	@ float
	ldr	r3, .L1756+616
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+620
	str	r3, [r2]	@ float
	ldr	r3, .L1756+624
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+628
	strb	r2, [r3]
	ldr	r3, .L1756+632
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+636
	strb	r2, [r3]
	ldr	r3, .L1756+640
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+644
	strb	r2, [r3]
	ldr	r3, .L1756+648
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+652
	strb	r2, [r3]
	ldr	r3, .L1756+656
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+660
	str	r3, [r2]	@ float
	ldr	r3, .L1756+664
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+668
	strb	r2, [r3]
	ldr	r3, .L1756+672
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+676
	strb	r2, [r3]
	ldr	r3, .L1756+680
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+684
	str	r3, [r2]	@ float
	ldr	r3, .L1756+688
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+692
	strb	r2, [r3]
	ldr	r3, .L1756+696
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+700
	strb	r2, [r3]
	ldr	r3, .L1756+704
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+708
	str	r3, [r2]	@ float
	ldr	r3, .L1756+712
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+716
	strb	r2, [r3]
	ldr	r3, .L1756+720
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+724
	strb	r2, [r3]
	ldr	r3, .L1756+728
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+732
	str	r3, [r2]	@ float
	ldr	r3, .L1756+736
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+740
	strb	r2, [r3]
	ldr	r3, .L1756+744
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+748
	str	r3, [r2]	@ float
	ldr	r3, .L1756+752
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+756
	strb	r2, [r3]
	ldr	r3, .L1756+760
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+764
	strb	r2, [r3]
	ldr	r3, .L1756+768
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+772
	strb	r2, [r3]
	ldr	r3, .L1756+776
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+780
	strb	r2, [r3]
	ldr	r3, .L1756+784
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+788
	strb	r2, [r3]
	ldr	r3, .L1756+792
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+796
	strb	r2, [r3]
	ldr	r3, .L1756+800
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+804
	strb	r2, [r3]
	ldr	r3, .L1756+808
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+812
	str	r3, [r2]	@ float
	ldr	r3, .L1756+816
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+820
	strb	r2, [r3]
	ldr	r3, .L1756+824
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+828
	strb	r2, [r3]
	ldr	r3, .L1756+832
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+836
	strb	r2, [r3]
	ldr	r3, .L1756+840
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+844
	strb	r2, [r3]
	ldr	r3, .L1756+848
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+852
	str	r3, [r2]	@ float
	ldr	r3, .L1756+856
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+860
	strb	r2, [r3]
	ldr	r3, .L1756+864
	ldr	r3, [r3]	@ float
	ldr	r2, .L1756+868
	str	r3, [r2]	@ float
	ldr	r3, .L1756+872
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+876
	strb	r2, [r3]
	ldr	r3, .L1756+880
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+884
	strb	r2, [r3]
	ldr	r3, .L1756+888
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+892
	strb	r2, [r3]
	ldr	r3, .L1756+896
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+900
	strb	r2, [r3]
	ldr	r3, .L1756+904
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+908
	strb	r2, [r3]
	ldr	r3, .L1756+912
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+916
	strb	r2, [r3]
	ldr	r3, .L1756+920
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+924
	strb	r2, [r3]
	ldr	r3, .L1756+928
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+932
	strb	r2, [r3]
	ldr	r3, .L1756+936
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+940
	strb	r2, [r3]
	ldr	r3, .L1756+944
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+948
	strb	r2, [r3]
	ldr	r3, .L1756+952
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1756+956
	strb	r2, [r3]
.L240:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L1363
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
