	.file	"154827632.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	__ok
	.bss
	.align 4
	.type	__ok, @object
	.size	__ok, 4
__ok:
	.zero	4
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	r2s
	.align 4
	.type	r2s, @object
	.size	r2s, 4
r2s:
	.zero	4
	.globl	_x_r2s
	.align 4
	.type	_x_r2s, @object
	.size	_x_r2s, 4
_x_r2s:
	.zero	4
	.globl	r_l
	.align 4
	.type	r_l, @object
	.size	r_l, 4
r_l:
	.zero	4
	.globl	_x_r_l
	.align 4
	.type	_x_r_l, @object
	.size	_x_r_l, 4
_x_r_l:
	.zero	4
	.globl	s_timeout
	.align 4
	.type	s_timeout, @object
	.size	s_timeout, 4
s_timeout:
	.zero	4
	.globl	_x_s_timeout
	.align 4
	.type	_x_s_timeout, @object
	.size	_x_s_timeout, 4
_x_s_timeout:
	.zero	4
	.globl	s_c
	.align 4
	.type	s_c, @object
	.size	s_c, 4
s_c:
	.zero	4
	.globl	_x_s_c
	.align 4
	.type	_x_s_c, @object
	.size	_x_s_c, 4
_x_s_c:
	.zero	4
	.globl	s2r
	.align 4
	.type	s2r, @object
	.size	s2r, 4
s2r:
	.zero	4
	.globl	_x_s2r
	.align 4
	.type	_x_s2r, @object
	.size	_x_s2r, 4
_x_s2r:
	.zero	4
	.globl	s_l
	.align 4
	.type	s_l, @object
	.size	s_l, 4
s_l:
	.zero	4
	.globl	_x_s_l
	.align 4
	.type	_x_s_l, @object
	.size	_x_s_l, 4
_x_s_l:
	.zero	4
	.globl	s_msg_id
	.align 4
	.type	s_msg_id, @object
	.size	s_msg_id, 4
s_msg_id:
	.zero	4
	.globl	_x_s_msg_id
	.align 4
	.type	_x_s_msg_id, @object
	.size	_x_s_msg_id, 4
_x_s_msg_id:
	.zero	4
	.globl	s_evt
	.align 4
	.type	s_evt, @object
	.size	s_evt, 4
s_evt:
	.zero	4
	.globl	_x_s_evt
	.align 4
	.type	_x_s_evt, @object
	.size	_x_s_evt, 4
_x_s_evt:
	.zero	4
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR r2s[rip], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR r_l[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s_timeout[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s_c[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR s2r[rip], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR s_l[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR s_msg_id[rip], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR s_evt[rip], eax
	mov	eax, DWORD PTR s_l[rip]
	test	eax, eax
	je	.L4
	movss	xmm0, DWORD PTR s_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, DWORD PTR s_msg_id[rip]
	test	eax, eax
	jne	.L4
	mov	eax, DWORD PTR s_l[rip]
	test	eax, eax
	jne	.L6
	movss	xmm1, DWORD PTR s_c[rip]
	movss	xmm0, DWORD PTR s_timeout[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L6:
	mov	eax, DWORD PTR r_l[rip]
	test	eax, eax
	je	.L4
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L10
.L4:
	mov	eax, 0
.L10:
	mov	DWORD PTR __ok[rip], eax
	jmp	.L11
.L53:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_r2s[rip], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR _x_r_l[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s_timeout[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s_c[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_s2r[rip], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR _x_s_l[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_s_msg_id[rip], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR _x_s_evt[rip], eax
	mov	eax, DWORD PTR _x_s_l[rip]
	test	eax, eax
	jne	.L12
	movss	xmm1, DWORD PTR _x_s_c[rip]
	movss	xmm0, DWORD PTR _x_s_timeout[rip]
	comiss	xmm0, xmm1
	jb	.L13
.L12:
	mov	edx, DWORD PTR s_l[rip]
	mov	eax, DWORD PTR _x_s_l[rip]
	cmp	edx, eax
	jne	.L15
	mov	edx, DWORD PTR s_msg_id[rip]
	mov	eax, DWORD PTR _x_s_msg_id[rip]
	cmp	edx, eax
	jne	.L15
	movss	xmm0, DWORD PTR s_timeout[rip]
	movss	xmm1, DWORD PTR _x_s_timeout[rip]
	ucomiss	xmm0, xmm1
	jp	.L15
	ucomiss	xmm0, xmm1
	jne	.L15
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s_c[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s_c[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L15
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L15
	mov	edx, DWORD PTR s2r[rip]
	mov	eax, DWORD PTR _x_s2r[rip]
	cmp	edx, eax
	je	.L18
.L15:
	mov	eax, DWORD PTR s_evt[rip]
	test	eax, eax
	je	.L13
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L13
.L18:
	mov	edx, DWORD PTR s_msg_id[rip]
	mov	eax, DWORD PTR _x_s_msg_id[rip]
	cmp	edx, eax
	jne	.L20
	movss	xmm0, DWORD PTR _x_s_timeout[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jp	.L20
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jne	.L20
	mov	edx, DWORD PTR s2r[rip]
	mov	eax, DWORD PTR _x_s2r[rip]
	cmp	edx, eax
	jne	.L20
	movss	xmm0, DWORD PTR _x_s_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L20
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L22
.L20:
	mov	eax, DWORD PTR s_evt[rip]
	test	eax, eax
	je	.L22
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L22
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L22
	mov	eax, DWORD PTR s_l[rip]
	test	eax, eax
	je	.L22
	mov	eax, DWORD PTR _x_s_l[rip]
	test	eax, eax
	jne	.L13
.L22:
	mov	edx, DWORD PTR s2r[rip]
	mov	eax, DWORD PTR _x_s2r[rip]
	cmp	edx, eax
	jne	.L24
	movss	xmm0, DWORD PTR _x_s_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L24
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L24
	movss	xmm0, DWORD PTR _x_s_timeout[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jp	.L24
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jne	.L24
	mov	eax, DWORD PTR s_msg_id[rip]
	mov	edx, DWORD PTR _x_s_msg_id[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L27
.L24:
	mov	eax, DWORD PTR s_evt[rip]
	test	eax, eax
	je	.L27
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L27
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L27
	mov	eax, DWORD PTR s_l[rip]
	test	eax, eax
	je	.L27
	mov	eax, DWORD PTR _x_s_l[rip]
	test	eax, eax
	je	.L13
.L27:
	mov	edx, DWORD PTR s2r[rip]
	mov	eax, DWORD PTR _x_s2r[rip]
	cmp	edx, eax
	jne	.L28
	movss	xmm0, DWORD PTR _x_s_c[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L28
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L28
	mov	eax, DWORD PTR _x_s_l[rip]
	test	eax, eax
	setne	cl
	mov	edx, DWORD PTR r2s[rip]
	mov	eax, DWORD PTR s_msg_id[rip]
	cmp	edx, eax
	je	.L30
	movss	xmm1, DWORD PTR s_timeout[rip]
	movss	xmm0, DWORD PTR s_c[rip]
	comiss	xmm0, xmm1
	jb	.L30
	mov	eax, 1
	jmp	.L32
.L30:
	mov	eax, 0
.L32:
	and	eax, 1
	xor	eax, ecx
	test	al, al
	jne	.L33
.L28:
	mov	eax, DWORD PTR s_l[rip]
	test	eax, eax
	jne	.L33
	mov	eax, DWORD PTR s_evt[rip]
	test	eax, eax
	je	.L33
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L33
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L13
.L33:
	movss	xmm1, DWORD PTR _x_s_timeout[rip]
	movss	xmm0, DWORD PTR s_timeout[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L35
	mov	eax, DWORD PTR s_evt[rip]
	test	eax, eax
	je	.L35
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L35
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L35
	mov	eax, DWORD PTR s_l[rip]
	test	eax, eax
	jne	.L35
	mov	eax, DWORD PTR _x_s_l[rip]
	test	eax, eax
	je	.L13
.L35:
	mov	eax, DWORD PTR s_l[rip]
	test	eax, eax
	jne	.L36
	mov	eax, DWORD PTR s_evt[rip]
	test	eax, eax
	je	.L36
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L36
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L36
	mov	edx, DWORD PTR r2s[rip]
	mov	eax, DWORD PTR s_msg_id[rip]
	cmp	edx, eax
	jne	.L37
	movss	xmm1, DWORD PTR s_timeout[rip]
	movss	xmm0, DWORD PTR s_c[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L37
	mov	edx, 1
	jmp	.L38
.L37:
	mov	edx, 0
.L38:
	mov	eax, DWORD PTR _x_s_l[rip]
	cmp	edx, eax
	jne	.L13
.L36:
	movss	xmm0, DWORD PTR _x_s_timeout[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jp	.L65
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	je	.L39
.L65:
	mov	eax, DWORD PTR s_evt[rip]
	test	eax, eax
	je	.L39
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L39
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L39
	mov	eax, DWORD PTR _x_s_l[rip]
	test	eax, eax
	je	.L39
	mov	eax, DWORD PTR s_l[rip]
	test	eax, eax
	je	.L13
.L39:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L41
	mov	edx, DWORD PTR r_l[rip]
	mov	eax, DWORD PTR _x_r_l[rip]
	cmp	edx, eax
	jne	.L13
	mov	edx, DWORD PTR r2s[rip]
	mov	eax, DWORD PTR _x_r2s[rip]
	cmp	edx, eax
	jne	.L13
.L41:
	mov	edx, DWORD PTR r2s[rip]
	mov	eax, DWORD PTR s2r[rip]
	cmp	edx, eax
	sete	al
	movzx	edx, al
	mov	eax, DWORD PTR _x_r_l[rip]
	cmp	edx, eax
	je	.L42
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L42
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L42
	mov	eax, DWORD PTR r_l[rip]
	test	eax, eax
	jne	.L13
.L42:
	mov	edx, DWORD PTR r2s[rip]
	mov	eax, DWORD PTR _x_r2s[rip]
	cmp	edx, eax
	je	.L43
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L43
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L43
	mov	eax, DWORD PTR r_l[rip]
	test	eax, eax
	je	.L43
	mov	eax, DWORD PTR _x_r_l[rip]
	test	eax, eax
	jne	.L13
.L43:
	mov	edx, DWORD PTR _x_r2s[rip]
	mov	eax, DWORD PTR s2r[rip]
	cmp	edx, eax
	je	.L44
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L44
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L44
	mov	eax, DWORD PTR r_l[rip]
	test	eax, eax
	je	.L44
	mov	eax, DWORD PTR _x_r_l[rip]
	test	eax, eax
	je	.L13
.L44:
	mov	edx, DWORD PTR r2s[rip]
	mov	eax, DWORD PTR _x_r2s[rip]
	cmp	edx, eax
	je	.L45
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L45
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L45
	mov	eax, DWORD PTR r_l[rip]
	test	eax, eax
	je	.L13
.L45:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L13
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L47
	mov	edx, DWORD PTR s2r[rip]
	mov	eax, DWORD PTR _x_s2r[rip]
	cmp	edx, eax
	jne	.L13
	mov	edx, DWORD PTR r2s[rip]
	mov	eax, DWORD PTR _x_r2s[rip]
	cmp	edx, eax
	jne	.L13
.L47:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L67
	ucomiss	xmm0, xmm1
	je	.L48
.L67:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L13
.L48:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L50
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L13
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L13
.L50:
	mov	eax, 1
	jmp	.L52
.L13:
	mov	eax, 0
.L52:
	mov	DWORD PTR __ok[rip], eax
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	mov	eax, DWORD PTR _x_r2s[rip]
	mov	DWORD PTR r2s[rip], eax
	mov	eax, DWORD PTR _x_r_l[rip]
	mov	DWORD PTR r_l[rip], eax
	movss	xmm0, DWORD PTR _x_s_timeout[rip]
	movss	DWORD PTR s_timeout[rip], xmm0
	movss	xmm0, DWORD PTR _x_s_c[rip]
	movss	DWORD PTR s_c[rip], xmm0
	mov	eax, DWORD PTR _x_s2r[rip]
	mov	DWORD PTR s2r[rip], eax
	mov	eax, DWORD PTR _x_s_l[rip]
	mov	DWORD PTR s_l[rip], eax
	mov	eax, DWORD PTR _x_s_msg_id[rip]
	mov	DWORD PTR s_msg_id[rip], eax
	mov	eax, DWORD PTR _x_s_evt[rip]
	mov	DWORD PTR s_evt[rip], eax
.L11:
	mov	eax, DWORD PTR __ok[rip]
	test	eax, eax
	jne	.L53
	mov	eax, 0
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC2:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"154827632.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	__ok,4,4
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	r2s,4,4
	.comm	_x_r2s,4,4
	.comm	r_l,4,4
	.comm	_x_r_l,4,4
	.comm	s_timeout,4,4
	.comm	_x_s_timeout,4,4
	.comm	s_c,4,4
	.comm	_x_s_c,4,4
	.comm	s2r,4,4
	.comm	_x_s2r,4,4
	.comm	s_l,4,4
	.comm	_x_s_l,4,4
	.comm	s_msg_id,4,4
	.comm	_x_s_msg_id,4,4
	.comm	s_evt,4,4
	.comm	_x_s_evt,4,4
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L66
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L66+4
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L66+8
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	ldr	r2, .L66+12
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L66+16
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L66+20
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L66+24
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	ldr	r2, .L66+28
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L66+32
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	ldr	r2, .L66+36
	str	r3, [r2]
	ldr	r3, .L66+28
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L66+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L66+32
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L66+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L66+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L6:
	ldr	r3, .L66+12
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L66
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L10
.L4:
	mov	r3, #0
.L10:
	mov	r2, r3
	ldr	r3, .L66+40
	str	r2, [r3]
	b	.L11
.L53:
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L66+44
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L66+48
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L66+52
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	ldr	r2, .L66+56
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L66+60
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L66+64
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L66+68
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	ldr	r2, .L66+72
	str	r3, [r2]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L66+76
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	ldr	r2, .L66+80
	str	r3, [r2]
	ldr	r3, .L66+72
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L66+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L13
.L12:
	ldr	r3, .L66+28
	ldr	r2, [r3]
	ldr	r3, .L66+72
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L15
	ldr	r3, .L66+32
	ldr	r2, [r3]
	ldr	r3, .L66+76
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L15
	ldr	r3, .L66+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L66+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L66+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L66+24
	ldr	r2, [r3]
	ldr	r3, .L66+68
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L18
.L15:
	ldr	r3, .L66+36
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L13
.L18:
	ldr	r3, .L66+32
	ldr	r2, [r3]
	ldr	r3, .L66+76
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L20
	ldr	r3, .L66+60
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L66+24
	ldr	r2, [r3]
	ldr	r3, .L66+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L20
	ldr	r3, .L66+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L22
.L20:
	ldr	r3, .L66+36
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L66+28
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L66+72
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L13
.L22:
	ldr	r3, .L66+24
	ldr	r2, [r3]
	ldr	r3, .L66+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L23
	ldr	r3, .L66+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L23
	ldr	r3, .L66+60
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L23
	ldr	r3, .L66+32
	ldr	r2, [r3]
	ldr	r3, .L66+76
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L26
.L23:
	ldr	r3, .L66+36
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L26
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L26
	ldr	r3, .L66+28
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L26
	ldr	r3, .L66+72
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L13
.L26:
	ldr	r3, .L66+24
	ldr	r2, [r3]
	ldr	r3, .L66+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L27
	ldr	r3, .L66+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L27
	ldr	r3, .L66+72
	ldr	r3, [r3]
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r4, r3, #255
	ldr	r3, .L66+8
	ldr	r2, [r3]
	ldr	r3, .L66+32
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L29
	ldr	r3, .L66+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L29
	mov	r3, #1
	b	.L31
.L29:
	mov	r3, #0
.L31:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r4
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L32
.L27:
	ldr	r3, .L66+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L32
	ldr	r3, .L66+36
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L13
.L32:
	ldr	r3, .L66+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+16
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L34
	mov	r3, #0
	mov	r4, r3
.L34:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L35
	ldr	r3, .L66+36
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L35
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L35
	ldr	r3, .L66+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L35
	ldr	r3, .L66+72
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L13
.L35:
	ldr	r3, .L66+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L66+36
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L66+8
	ldr	r2, [r3]
	ldr	r3, .L66+32
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L37
	ldr	r3, .L66+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+20
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L38
	mov	r3, #0
	mov	r4, r3
.L38:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L37
	mov	r3, #1
	b	.L39
.L37:
	mov	r3, #0
.L39:
	ldr	r2, .L66+72
	ldr	r2, [r2]
	cmp	r3, r2
	bne	.L13
.L36:
	ldr	r3, .L66+60
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L40
	ldr	r3, .L66+36
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L66+72
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L66+28
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L13
.L40:
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L66+12
	ldr	r2, [r3]
	ldr	r3, .L66+56
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L13
	ldr	r3, .L66+8
	ldr	r2, [r3]
	ldr	r3, .L66+52
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L13
.L41:
	ldr	r3, .L66+8
	ldr	r2, [r3]
	ldr	r3, .L66+24
	ldr	r3, [r3]
	cmp	r2, r3
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r2, r3
	ldr	r3, .L66+56
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L42
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L42
	ldr	r3, .L66+12
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L13
.L42:
	ldr	r3, .L66+8
	ldr	r2, [r3]
	ldr	r3, .L66+52
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L43
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L66+12
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L66+56
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L13
.L43:
	ldr	r3, .L66+52
	ldr	r2, [r3]
	ldr	r3, .L66+24
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L44
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L66+12
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L66+56
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L13
.L44:
	ldr	r3, .L66+8
	ldr	r2, [r3]
	ldr	r3, .L66+52
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L45
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L66+12
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L13
.L45:
	ldr	r3, .L66+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L47
	ldr	r3, .L66+24
	ldr	r2, [r3]
	ldr	r3, .L66+68
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L13
	ldr	r3, .L66+8
	ldr	r2, [r3]
	ldr	r3, .L66+52
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L13
.L47:
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L48
	ldr	r3, .L66
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L49
	mov	r3, #0
	mov	r4, r3
.L49:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L13
.L48:
	ldr	r3, .L66
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L50
	ldr	r3, .L66+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L66
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L66+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L13
.L50:
	mov	r3, #1
	b	.L52
.L13:
	mov	r3, #0
.L52:
	mov	r2, r3
	ldr	r3, .L66+40
	str	r2, [r3]
	ldr	r3, .L66+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L66
	str	r3, [r2]	@ float
	ldr	r3, .L66+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+4
	str	r3, [r2]	@ float
	ldr	r3, .L66+52
	ldr	r3, [r3]
	ldr	r2, .L66+8
	str	r3, [r2]
	ldr	r3, .L66+56
	ldr	r3, [r3]
	ldr	r2, .L66+12
	str	r3, [r2]
	ldr	r3, .L66+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+16
	str	r3, [r2]	@ float
	ldr	r3, .L66+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L66+20
	str	r3, [r2]	@ float
	ldr	r3, .L66+68
	ldr	r3, [r3]
	ldr	r2, .L66+24
	str	r3, [r2]
	ldr	r3, .L66+72
	ldr	r3, [r3]
	ldr	r2, .L66+28
	str	r3, [r2]
	ldr	r3, .L66+76
	ldr	r3, [r3]
	ldr	r2, .L66+32
	str	r3, [r2]
	ldr	r3, .L66+80
	ldr	r3, [r3]
	ldr	r2, .L66+36
	str	r3, [r2]
.L11:
	ldr	r3, .L66+40
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L53
	mov	r3, #0
	mov	r0, r3
	pop	{r4, r5, r6, r7, fp, pc}
.L67:
	.align	2
.L66:
	.word	_diverge_delta
	.word	delta
	.word	r2s
	.word	r_l
	.word	s_timeout
	.word	s_c
	.word	s2r
	.word	s_l
	.word	s_msg_id
	.word	s_evt
	.word	__ok
	.word	_x__diverge_delta
	.word	_x_delta
	.word	_x_r2s
	.word	_x_r_l
	.word	_x_s_timeout
	.word	_x_s_c
	.word	_x_s2r
	.word	_x_s_l
	.word	_x_s_msg_id
	.word	_x_s_evt
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
