	.file	"1085913.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	movzx	eax, al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 144
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR -76[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -144[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -140[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -136[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -132[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -128[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -124[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -120[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -116[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -112[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -108[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -104[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -100[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -96[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -92[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -88[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -84[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -80[rbp], eax
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -88[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -104[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L5
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -136[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	jnb	.L7
.L5:
	cmp	DWORD PTR -140[rbp], 0
	jne	.L4
.L7:
	mov	eax, 1
	jmp	.L8
.L4:
	mov	eax, 0
.L8:
	mov	DWORD PTR -72[rbp], eax
	jmp	.L9
.L295:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -88[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	jnb	.L10
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -88[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L11
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -104[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	jb	.L12
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -136[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	jnb	.L10
.L12:
	cmp	DWORD PTR -140[rbp], 0
	jne	.L11
.L10:
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR -76[rbp], eax
	jmp	.L14
.L11:
	sub	DWORD PTR -76[rbp], 1
.L14:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -68[rbp], eax
	call	__VERIFIER_nondet_bool
	mov	DWORD PTR -64[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -60[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -56[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -52[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -48[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -44[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -40[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -36[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -32[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -28[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -24[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -20[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -16[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -12[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -8[rbp], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR -4[rbp], eax
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -36[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L307
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L24
.L307:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L308
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L24
.L308:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L309
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L24
.L309:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L310
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L24
.L310:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jp	.L311
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	je	.L24
.L311:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L312
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L24
.L312:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L313
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	je	.L24
.L313:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -36[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jp	.L15
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jne	.L15
.L24:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -24[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L322
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L41
.L322:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L323
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L41
.L323:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L324
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L41
.L324:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L325
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L41
.L325:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jp	.L326
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	je	.L41
.L326:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L327
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L41
.L327:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L328
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L41
.L328:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -24[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jne	.L15
.L41:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -56[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L337
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L58
.L337:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L338
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L58
.L338:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L339
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L58
.L339:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L340
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L58
.L340:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L341
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L58
.L341:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L342
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L58
.L342:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L343
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L58
.L343:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -56[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jne	.L15
.L58:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC19[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -8[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L352
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L75
.L352:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L353
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L75
.L353:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jp	.L354
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	je	.L75
.L354:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L355
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L75
.L355:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L356
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L75
.L356:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L357
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L75
.L357:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L358
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	je	.L75
.L358:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -8[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jne	.L15
.L75:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -12[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L367
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L92
.L367:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L368
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L92
.L368:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L369
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L92
.L369:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L370
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L92
.L370:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L371
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L92
.L371:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L372
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L92
.L372:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L373
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L92
.L373:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jne	.L15
.L92:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -52[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L382
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	je	.L109
.L382:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L383
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L109
.L383:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L384
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L109
.L384:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L385
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L109
.L385:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L386
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L109
.L386:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L387
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L109
.L387:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L388
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L109
.L388:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -52[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jne	.L15
.L109:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -4[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L397
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L126
.L397:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L398
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L126
.L398:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L399
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L126
.L399:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L400
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L126
.L400:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L401
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L126
.L401:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L402
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L126
.L402:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L403
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L126
.L403:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -4[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jne	.L15
.L126:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -44[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC14[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L412
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L143
.L412:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L413
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L143
.L413:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L414
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L143
.L414:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L415
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L143
.L415:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L416
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L143
.L416:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L417
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L143
.L417:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L418
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L143
.L418:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -44[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC14[rip]
	jne	.L15
.L143:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -68[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L427
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L160
.L427:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L428
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L160
.L428:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L429
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L160
.L429:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L430
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L160
.L430:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L431
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L160
.L431:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L432
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L160
.L432:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L433
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L160
.L433:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -68[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jne	.L15
.L160:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC19[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -48[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	jp	.L442
	ucomisd	xmm0, QWORD PTR .LC19[rip]
	je	.L177
.L442:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L443
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L177
.L443:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L444
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L177
.L444:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L445
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L177
.L445:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L446
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	je	.L177
.L446:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L447
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	je	.L177
.L447:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L448
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L177
.L448:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -48[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jne	.L15
.L177:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC5[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -32[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -136[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L457
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L194
.L457:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L458
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L194
.L458:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L459
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L194
.L459:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L460
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L194
.L460:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L461
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L194
.L461:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	jp	.L462
	ucomisd	xmm0, QWORD PTR .LC5[rip]
	je	.L194
.L462:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L463
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L194
.L463:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -32[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jne	.L15
.L194:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC13[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -20[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L472
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L211
.L472:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L473
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L211
.L473:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L474
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L211
.L474:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	jp	.L475
	ucomisd	xmm0, QWORD PTR .LC13[rip]
	je	.L211
.L475:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L476
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L211
.L476:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L477
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	je	.L211
.L477:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L478
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L211
.L478:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -20[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jp	.L15
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jne	.L15
.L211:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC20[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC11[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -16[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -92[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L487
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L228
.L487:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	jp	.L488
	ucomisd	xmm0, QWORD PTR .LC20[rip]
	je	.L228
.L488:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L489
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L228
.L489:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L490
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L228
.L490:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	jp	.L491
	ucomisd	xmm0, QWORD PTR .LC11[rip]
	je	.L228
.L491:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L492
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L228
.L492:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -100[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L493
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L228
.L493:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -16[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jne	.L15
.L228:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC10[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC16[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L502
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L245
.L502:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L503
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L245
.L503:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -144[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L504
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L245
.L504:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L505
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L245
.L505:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L506
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L245
.L506:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jp	.L507
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	je	.L245
.L507:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	jp	.L508
	ucomisd	xmm0, QWORD PTR .LC10[rip]
	je	.L245
.L508:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -28[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC16[rip]
	jne	.L15
.L245:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC0[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC15[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC12[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC9[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC6[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -40[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -116[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	jp	.L517
	ucomisd	xmm0, QWORD PTR .LC0[rip]
	je	.L262
.L517:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -104[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	jp	.L518
	ucomisd	xmm0, QWORD PTR .LC15[rip]
	je	.L262
.L518:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -96[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jp	.L519
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	je	.L262
.L519:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -108[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	jp	.L520
	ucomisd	xmm0, QWORD PTR .LC12[rip]
	je	.L262
.L520:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L521
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L262
.L521:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	jp	.L522
	ucomisd	xmm0, QWORD PTR .LC9[rip]
	je	.L262
.L522:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	jp	.L523
	movsd	xmm1, QWORD PTR .LC6[rip]
	ucomisd	xmm0, xmm1
	je	.L262
.L523:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -40[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jne	.L15
.L262:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC8[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC4[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC2[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC18[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC7[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -60[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC17[rip]
	comisd	xmm0, xmm1
	jb	.L15
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -124[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	jp	.L532
	ucomisd	xmm0, QWORD PTR .LC8[rip]
	je	.L279
.L532:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -120[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	jp	.L533
	ucomisd	xmm0, QWORD PTR .LC4[rip]
	je	.L279
.L533:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -80[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	jp	.L534
	ucomisd	xmm0, QWORD PTR .LC2[rip]
	je	.L279
.L534:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -128[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	jp	.L535
	ucomisd	xmm0, QWORD PTR .LC3[rip]
	je	.L279
.L535:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -88[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L536
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	je	.L279
.L536:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -84[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	jp	.L537
	ucomisd	xmm0, QWORD PTR .LC18[rip]
	je	.L279
.L537:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -112[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	jp	.L538
	ucomisd	xmm0, QWORD PTR .LC7[rip]
	je	.L279
.L538:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -132[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jp	.L15
	ucomisd	xmm0, QWORD PTR .LC17[rip]
	jne	.L15
.L279:
	cmp	DWORD PTR -64[rbp], 0
	je	.L288
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -44[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -60[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC2[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L289
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -24[rbp]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, DWORD PTR -28[rbp]
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC1[rip]
	comisd	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L289
.L288:
	pxor	xmm0, xmm0
	cvtss2sd	xmm0, DWORD PTR -8[rbp]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, DWORD PTR -12[rbp]
	subsd	xmm0, xmm1
	comisd	xmm0, QWORD PTR .LC0[rip]
	jb	.L539
.L289:
	mov	edx, 1
	jmp	.L292
.L539:
	mov	edx, 0
.L292:
	mov	eax, DWORD PTR -140[rbp]
	cmp	edx, eax
	jne	.L15
	mov	eax, 1
	jmp	.L293
.L15:
	mov	eax, 0
.L293:
	mov	DWORD PTR -72[rbp], eax
	movss	xmm0, DWORD PTR -68[rbp]
	movss	DWORD PTR -144[rbp], xmm0
	mov	eax, DWORD PTR -64[rbp]
	mov	DWORD PTR -140[rbp], eax
	movss	xmm0, DWORD PTR -60[rbp]
	movss	DWORD PTR -136[rbp], xmm0
	movss	xmm0, DWORD PTR -56[rbp]
	movss	DWORD PTR -132[rbp], xmm0
	movss	xmm0, DWORD PTR -52[rbp]
	movss	DWORD PTR -128[rbp], xmm0
	movss	xmm0, DWORD PTR -48[rbp]
	movss	DWORD PTR -124[rbp], xmm0
	movss	xmm0, DWORD PTR -44[rbp]
	movss	DWORD PTR -120[rbp], xmm0
	movss	xmm0, DWORD PTR -40[rbp]
	movss	DWORD PTR -116[rbp], xmm0
	movss	xmm0, DWORD PTR -36[rbp]
	movss	DWORD PTR -112[rbp], xmm0
	movss	xmm0, DWORD PTR -32[rbp]
	movss	DWORD PTR -108[rbp], xmm0
	movss	xmm0, DWORD PTR -28[rbp]
	movss	DWORD PTR -104[rbp], xmm0
	movss	xmm0, DWORD PTR -24[rbp]
	movss	DWORD PTR -100[rbp], xmm0
	movss	xmm0, DWORD PTR -20[rbp]
	movss	DWORD PTR -96[rbp], xmm0
	movss	xmm0, DWORD PTR -16[rbp]
	movss	DWORD PTR -92[rbp], xmm0
	movss	xmm0, DWORD PTR -12[rbp]
	movss	DWORD PTR -88[rbp], xmm0
	movss	xmm0, DWORD PTR -8[rbp]
	movss	DWORD PTR -84[rbp], xmm0
	movss	xmm0, DWORD PTR -4[rbp]
	movss	DWORD PTR -80[rbp], xmm0
.L9:
	cmp	DWORD PTR -76[rbp], 0
	js	.L294
	cmp	DWORD PTR -72[rbp], 0
	jne	.L295
.L294:
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 8
.LC0:
	.long	0
	.long	-1072693248
	.align 8
.LC1:
	.long	0
	.long	1076101120
	.align 8
.LC2:
	.long	0
	.long	-1070530560
	.align 8
.LC3:
	.long	0
	.long	-1071906816
	.align 8
.LC4:
	.long	0
	.long	-1070727168
	.align 8
.LC5:
	.long	0
	.long	-1070596096
	.align 8
.LC6:
	.long	0
	.long	-1074790400
	.align 8
.LC7:
	.long	0
	.long	-1071382528
	.align 8
.LC8:
	.long	0
	.long	-1071644672
	.align 8
.LC9:
	.long	0
	.long	-1070858240
	.align 8
.LC10:
	.long	0
	.long	-1072168960
	.align 8
.LC11:
	.long	0
	.long	-1071513600
	.align 8
.LC12:
	.long	0
	.long	-1070399488
	.align 8
.LC13:
	.long	0
	.long	-1070989312
	.align 8
.LC14:
	.long	0
	.long	-1071120384
	.align 8
.LC15:
	.long	0
	.long	-1070333952
	.align 8
.LC16:
	.long	0
	.long	-1071251456
	.align 8
.LC17:
	.long	0
	.long	-1073741824
	.align 8
.LC18:
	.long	0
	.long	-1072431104
	.align 8
.LC19:
	.long	0
	.long	-1073217536
	.align 8
.LC20:
	.long	0
	.long	-1070465024
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"1085913.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dcmpge
	.global	__aeabi_dcmple
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 144
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, fp, lr}
	add	fp, sp, #12
	sub	sp, sp, #144
	bl	__VERIFIER_nondet_int
	str	r0, [fp, #-88]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-156]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-152]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-148]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-144]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-140]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-136]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-132]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-128]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-124]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-120]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-116]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-112]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-108]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-104]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-100]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-96]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-92]	@ float
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L320+8
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L4
	mov	r3, #0
	mov	r4, r3
.L4:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L5
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L6
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+32
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L8
.L6:
	ldr	r3, [fp, #-152]
	cmp	r3, #0
	bne	.L5
.L8:
	mov	r3, #1
	b	.L9
.L5:
	mov	r3, #0
.L9:
	str	r3, [fp, #-84]
	b	.L10
.L187:
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+8
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L11
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L320+8
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L12
	mov	r3, #0
	mov	r4, r3
.L12:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L13
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L14
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+32
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L11
.L14:
	ldr	r3, [fp, #-152]
	cmp	r3, #0
	bne	.L13
.L11:
	bl	__VERIFIER_nondet_int
	str	r0, [fp, #-88]
	b	.L16
.L321:
	.align	2
.L320:
	.word	1076101120
	.word	-1071906816
	.word	-1072693248
	.word	-1070596096
	.word	-1070727168
	.word	-1071382528
	.word	-1071644672
	.word	-1072168960
	.word	-1070530560
	.word	-1074790400
	.word	-1071513600
	.word	-1070399488
	.word	-1072431104
	.word	-1070858240
	.word	-1071120384
	.word	-1070333952
	.word	-1071251456
	.word	-1070989312
.L13:
	ldr	r3, [fp, #-88]
	sub	r3, r3, #1
	str	r3, [fp, #-88]
.L16:
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-80]	@ float
	bl	__VERIFIER_nondet_bool
	str	r0, [fp, #-76]
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-72]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-68]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-64]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-60]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-56]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-52]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-48]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-44]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-40]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-36]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-32]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-28]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-24]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-20]	@ float
	bl	__VERIFIER_nondet_float
	str	r0, [fp, #-16]	@ float
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L26
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-48]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L26:
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L36:
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L46
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L46
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L46
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L46
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L46
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L320+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L46
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L46
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-68]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L46:
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L56:
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L66
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L66:
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-64]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	b	.L323
.L324:
	.align	2
.L322:
	.word	-1072431104
	.word	-1073217536
	.word	-1070465024
	.word	-1071382528
	.word	-1072693248
	.word	-1070399488
	.word	-1070858240
	.word	-1070727168
	.word	-1072168960
	.word	-1071513600
	.word	-1071120384
	.word	-1071906816
	.word	-1070596096
	.word	-1070333952
	.word	-1071644672
	.word	-1070989312
.L323:
.L76:
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L86
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L86
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L86
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L86
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L86
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L86
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L86
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-16]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L86:
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L96
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L96
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L96
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L96
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L96
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L96
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L96
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L96:
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L106
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L106
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L106
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L106
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L106
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L106
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L106
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-80]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L322+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L106:
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-60]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L116:
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-148]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L126
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L126
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L126
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L126
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L126
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L126
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L126
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-44]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L126:
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L136
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L136
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L136
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L136
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L136
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L136
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L136
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-32]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L136:
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	b	.L326
.L327:
	.align	2
.L325:
	.word	-1073217536
	.word	-1070596096
	.word	-1071382528
	.word	-1072431104
	.word	-1070989312
	.word	-1070465024
	.word	-1071513600
	.word	-1071906816
	.word	-1070530560
	.word	-1072168960
	.word	-1071251456
	.word	-1072693248
	.word	-1070333952
	.word	-1070399488
	.word	-1070727168
	.word	-1070858240
	.word	-1074790400
	.word	-1071644672
.L326:
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+20
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+28
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-104]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+24
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
	ldr	r0, [fp, #-112]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-28]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+28
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L146:
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+32
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+36
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+40
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r0, [fp, #-156]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+32
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+36
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+40
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L156:
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+44
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+48
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+52
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+60
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-128]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+44
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
	ldr	r0, [fp, #-116]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+48
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
	ldr	r0, [fp, #-108]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
	ldr	r0, [fp, #-120]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+52
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+56
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+60
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+64
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L166
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-52]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+68
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L166:
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L325+68
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+4
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+8
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+12
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+16
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
	ldr	r0, [fp, #-136]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+20
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L176
	ldr	r0, [fp, #-132]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L176
	ldr	r0, [fp, #-92]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+4
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L176
	ldr	r0, [fp, #-140]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+8
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L176
	ldr	r0, [fp, #-100]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L176
	ldr	r0, [fp, #-96]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+12
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L176
	ldr	r0, [fp, #-124]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+16
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L176
	ldr	r0, [fp, #-144]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #-1073741824
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L17
.L176:
	ldr	r3, [fp, #-76]
	cmp	r3, #0
	beq	.L178
	ldr	r0, [fp, #-56]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-72]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L328+4
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	mov	r3, #0
	mov	r4, r3
.L179:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L180
	ldr	r0, [fp, #-36]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-40]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r3, #1
	mov	r4, r3
	mov	r2, #0
	ldr	r3, .L328+24
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L181
	mov	r3, #0
	mov	r4, r3
.L181:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L180
.L178:
	ldr	r0, [fp, #-20]	@ float
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r0, [fp, #-24]	@ float
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L328+28
	bl	__aeabi_dcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L319
.L180:
	mov	r2, #1
	b	.L184
.L319:
	mov	r2, #0
.L184:
	ldr	r3, [fp, #-152]
	cmp	r2, r3
	bne	.L17
	mov	r3, #1
	b	.L185
.L17:
	mov	r3, #0
.L185:
	str	r3, [fp, #-84]
	ldr	r3, [fp, #-80]	@ float
	str	r3, [fp, #-156]	@ float
	ldr	r3, [fp, #-76]
	str	r3, [fp, #-152]
	ldr	r3, [fp, #-72]	@ float
	str	r3, [fp, #-148]	@ float
	ldr	r3, [fp, #-68]	@ float
	str	r3, [fp, #-144]	@ float
	ldr	r3, [fp, #-64]	@ float
	str	r3, [fp, #-140]	@ float
	ldr	r3, [fp, #-60]	@ float
	str	r3, [fp, #-136]	@ float
	ldr	r3, [fp, #-56]	@ float
	str	r3, [fp, #-132]	@ float
	ldr	r3, [fp, #-52]	@ float
	str	r3, [fp, #-128]	@ float
	ldr	r3, [fp, #-48]	@ float
	str	r3, [fp, #-124]	@ float
	ldr	r3, [fp, #-44]	@ float
	str	r3, [fp, #-120]	@ float
	ldr	r3, [fp, #-40]	@ float
	str	r3, [fp, #-116]	@ float
	ldr	r3, [fp, #-36]	@ float
	str	r3, [fp, #-112]	@ float
	ldr	r3, [fp, #-32]	@ float
	str	r3, [fp, #-108]	@ float
	ldr	r3, [fp, #-28]	@ float
	str	r3, [fp, #-104]	@ float
	ldr	r3, [fp, #-24]	@ float
	str	r3, [fp, #-100]	@ float
	ldr	r3, [fp, #-20]	@ float
	str	r3, [fp, #-96]	@ float
	ldr	r3, [fp, #-16]	@ float
	str	r3, [fp, #-92]	@ float
.L10:
	ldr	r3, [fp, #-88]
	cmp	r3, #0
	blt	.L186
	ldr	r3, [fp, #-84]
	cmp	r3, #0
	bne	.L187
.L186:
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #12
	@ sp needed
	pop	{r4, r5, fp, pc}
.L329:
	.align	2
.L328:
	.word	-1070727168
	.word	-1070530560
	.word	-1071906816
	.word	-1072431104
	.word	-1071382528
	.word	-1071644672
	.word	1076101120
	.word	-1072693248
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
