	.file	"61075763.c"
	.intel_syntax noprefix
	.text
	.section	.rodata
	.type	const_vecval_zero, @object
	.size	const_vecval_zero, 2
const_vecval_zero:
	.zero	2
	.type	const_vecval_one, @object
	.size	const_vecval_one, 2
const_vecval_one:
	.byte	1
	.byte	0
	.type	const_vecval_minus_one, @object
	.size	const_vecval_minus_one, 2
const_vecval_minus_one:
	.byte	-1
	.byte	0
	.section	.data.rel.ro.local,"aw"
	.align 32
	.type	vec4state_const_zero, @object
	.size	vec4state_const_zero, 32
vec4state_const_zero:
	.quad	1
	.quad	1
	.long	0
	.zero	4
	.quad	const_vecval_zero
	.align 32
	.type	vec4state_const_one, @object
	.size	vec4state_const_one, 32
vec4state_const_one:
	.quad	32
	.quad	1
	.long	0
	.zero	4
	.quad	const_vecval_one
	.align 32
	.type	vec4state_const_minus_one, @object
	.size	vec4state_const_minus_one, 32
vec4state_const_minus_one:
	.quad	32
	.quad	1
	.long	1
	.zero	4
	.quad	const_vecval_minus_one
	.text
	.type	vec4state_clear_padding_bits, @function
vec4state_clear_padding_bits:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	lea	rdx, [rax+rax]
	sub	rdx, 2
	add	rdx, rcx
	movzx	esi, BYTE PTR [rdx]
	mov	rdx, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 8[rdx]
	neg	edx
	and	edx, 7
	mov	edi, 255
	mov	ecx, edx
	sar	edi, cl
	mov	edx, edi
	mov	ecx, edx
	mov	rdx, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 24[rdx]
	add	rax, rax
	sub	rax, 2
	add	rax, rdx
	and	esi, ecx
	mov	edx, esi
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -8[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	lea	rdx, [rax+rax]
	sub	rdx, 2
	add	rdx, rcx
	movzx	esi, BYTE PTR 1[rdx]
	mov	rdx, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 8[rdx]
	neg	edx
	and	edx, 7
	mov	edi, 255
	mov	ecx, edx
	sar	edi, cl
	mov	edx, edi
	mov	ecx, edx
	mov	rdx, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR 24[rdx]
	add	rax, rax
	sub	rax, 2
	add	rax, rdx
	and	esi, ecx
	mov	edx, esi
	mov	BYTE PTR 1[rax], dl
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	vec4state_clear_padding_bits, .-vec4state_clear_padding_bits
	.type	vec4state_bit_test, @function
vec4state_bit_test:
.LFB7:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	eax, DWORD PTR -28[rbp]
	shr	eax, 3
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -28[rbp]
	and	eax, 7
	mov	DWORD PTR -12[rbp], eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -16[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	edx, al
	mov	eax, DWORD PTR -12[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	and	eax, 1
	mov	DWORD PTR -8[rbp], eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -16[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	movsx	edx, al
	mov	eax, DWORD PTR -12[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	and	eax, 1
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	add	eax, eax
	or	eax, DWORD PTR -8[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	vec4state_bit_test, .-vec4state_bit_test
	.type	vec4state_bit_set, @function
vec4state_bit_set:
.LFB8:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	DWORD PTR -32[rbp], edx
	mov	eax, DWORD PTR -28[rbp]
	shr	eax, 3
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -28[rbp]
	and	eax, 7
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -32[rbp]
	and	eax, 1
	mov	BYTE PTR -13[rbp], al
	mov	eax, DWORD PTR -32[rbp]
	sar	eax
	and	eax, 1
	mov	BYTE PTR -12[rbp], al
	movsx	edx, BYTE PTR -13[rbp]
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	BYTE PTR -11[rbp], al
	movsx	edx, BYTE PTR -12[rbp]
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	BYTE PTR -10[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	not	eax
	mov	BYTE PTR -9[rbp], al
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -8[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	and	al, BYTE PTR -9[rbp]
	mov	rdx, QWORD PTR -24[rbp]
	mov	rcx, QWORD PTR 24[rdx]
	mov	edx, DWORD PTR -8[rbp]
	add	rdx, rdx
	add	rdx, rcx
	or	al, BYTE PTR -11[rbp]
	mov	BYTE PTR [rdx], al
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -8[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	and	al, BYTE PTR -9[rbp]
	mov	rdx, QWORD PTR -24[rbp]
	mov	rcx, QWORD PTR 24[rdx]
	mov	edx, DWORD PTR -8[rbp]
	add	rdx, rdx
	add	rdx, rcx
	or	al, BYTE PTR -10[rbp]
	mov	BYTE PTR 1[rdx], al
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	vec4state_bit_set, .-vec4state_bit_set
	.type	vec4state_bitfield_set, @function
vec4state_bitfield_set:
.LFB9:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	DWORD PTR -32[rbp], edx
	mov	DWORD PTR -36[rbp], ecx
	mov	eax, DWORD PTR -28[rbp]
	shr	eax, 3
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -32[rbp]
	shr	eax, 3
	mov	DWORD PTR -4[rbp], eax
	cmp	DWORD PTR -36[rbp], 0
	je	.L6
	cmp	DWORD PTR -36[rbp], 2
	jne	.L7
.L6:
	mov	eax, 0
	jmp	.L8
.L7:
	mov	eax, -1
.L8:
	mov	BYTE PTR -14[rbp], al
	cmp	DWORD PTR -36[rbp], 0
	je	.L9
	cmp	DWORD PTR -36[rbp], 1
	jne	.L10
.L9:
	mov	eax, 0
	jmp	.L11
.L10:
	mov	eax, -1
.L11:
	mov	BYTE PTR -13[rbp], al
	mov	eax, DWORD PTR -8[rbp]
	mov	DWORD PTR -12[rbp], eax
	jmp	.L12
.L17:
	mov	eax, DWORD PTR -12[rbp]
	cmp	DWORD PTR -8[rbp], eax
	je	.L13
	mov	eax, DWORD PTR -12[rbp]
	cmp	DWORD PTR -4[rbp], eax
	je	.L13
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rdx, rax
	movzx	eax, BYTE PTR -14[rbp]
	mov	BYTE PTR [rdx], al
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rdx, rax
	movzx	eax, BYTE PTR -13[rbp]
	mov	BYTE PTR 1[rdx], al
	jmp	.L14
.L13:
	mov	BYTE PTR -15[rbp], -1
	mov	eax, DWORD PTR -12[rbp]
	cmp	DWORD PTR -8[rbp], eax
	jne	.L15
	mov	eax, DWORD PTR -28[rbp]
	and	eax, 7
	mov	edx, -1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	edx, eax
	movzx	eax, BYTE PTR -15[rbp]
	and	eax, edx
	mov	BYTE PTR -15[rbp], al
.L15:
	mov	eax, DWORD PTR -12[rbp]
	cmp	DWORD PTR -4[rbp], eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR [rax]
	movzx	eax, BYTE PTR -15[rbp]
	not	eax
	mov	ecx, edx
	and	ecx, eax
	movzx	eax, BYTE PTR -14[rbp]
	and	al, BYTE PTR -15[rbp]
	mov	esi, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	or	ecx, esi
	mov	edx, ecx
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR 1[rax]
	movzx	eax, BYTE PTR -15[rbp]
	not	eax
	mov	ecx, edx
	and	ecx, eax
	movzx	eax, BYTE PTR -13[rbp]
	and	al, BYTE PTR -15[rbp]
	mov	esi, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	or	ecx, esi
	mov	edx, ecx
	mov	BYTE PTR 1[rax], dl
.L14:
	add	DWORD PTR -12[rbp], 1
.L12:
	mov	eax, DWORD PTR -12[rbp]
	cmp	DWORD PTR -4[rbp], eax
	jnb	.L17
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	vec4state_bitfield_set, .-vec4state_bitfield_set
	.type	vec4state_set, @function
vec4state_set:
.LFB10:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	cmp	DWORD PTR -28[rbp], 0
	je	.L19
	cmp	DWORD PTR -28[rbp], 1
	jne	.L20
	mov	eax, 1
	jmp	.L22
.L20:
	mov	eax, -1
	jmp	.L22
.L19:
	mov	eax, 0
.L22:
	mov	BYTE PTR -7[rbp], al
	cmp	DWORD PTR -28[rbp], 0
	je	.L23
	cmp	DWORD PTR -28[rbp], 1
	jne	.L24
.L23:
	mov	eax, 0
	jmp	.L25
.L24:
	mov	eax, -1
.L25:
	mov	BYTE PTR -6[rbp], al
	cmp	DWORD PTR -28[rbp], 3
	je	.L26
	cmp	DWORD PTR -28[rbp], 2
	jne	.L27
.L26:
	mov	eax, -1
	jmp	.L28
.L27:
	mov	eax, 0
.L28:
	mov	BYTE PTR -5[rbp], al
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 24[rax]
	movzx	edx, BYTE PTR -7[rbp]
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 24[rax]
	movzx	edx, BYTE PTR -5[rbp]
	mov	BYTE PTR 1[rax], dl
	mov	DWORD PTR -4[rbp], 1
	jmp	.L29
.L30:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rdx, rax
	movzx	eax, BYTE PTR -6[rbp]
	mov	BYTE PTR [rdx], al
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rdx, rax
	movzx	eax, BYTE PTR -5[rbp]
	mov	BYTE PTR 1[rdx], al
	add	DWORD PTR -4[rbp], 1
.L29:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L30
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE10:
	.size	vec4state_set, .-vec4state_set
	.type	vec4state_any_bit_is_X_or_Z, @function
vec4state_any_bit_is_X_or_Z:
.LFB11:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L32
.L35:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	test	al, al
	je	.L33
	mov	eax, 1
	jmp	.L34
.L33:
	add	DWORD PTR -4[rbp], 1
.L32:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L35
	mov	eax, 0
.L34:
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE11:
	.size	vec4state_any_bit_is_X_or_Z, .-vec4state_any_bit_is_X_or_Z
	.section	.rodata
	.align 8
.LC0:
	.string	"FATAL: memory allocation for vec4state failed!"
	.align 8
.LC1:
	.string	"FATAL: failed allocating %lu bytes for vec4state!"
	.text
	.globl	vec4state_new
	.type	vec4state_new, @function
vec4state_new:
.LFB12:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	edi, 32
	call	malloc@PLT
	mov	QWORD PTR -8[rbp], rax
	cmp	QWORD PTR -8[rbp], 0
	jne	.L37
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 46
	mov	esi, 1
	lea	rdi, .LC0[rip]
	call	fwrite@PLT
	call	abort@PLT
.L37:
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR [rax], 0
	mov	rax, QWORD PTR -8[rbp]
	mov	rdx, QWORD PTR -24[rbp]
	mov	QWORD PTR 8[rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, DWORD PTR -28[rbp]
	mov	DWORD PTR 16[rax], edx
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 7
	shr	rax, 3
	add	rax, rax
	mov	rdi, rax
	call	malloc@PLT
	mov	rdx, rax
	mov	rax, QWORD PTR -8[rbp]
	mov	QWORD PTR 24[rax], rdx
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR 24[rax]
	test	rax, rax
	jne	.L38
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -24[rbp]
	add	rax, 7
	shr	rax, 3
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR stderr[rip]
	lea	rsi, .LC1[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	call	abort@PLT
.L38:
	mov	rax, QWORD PTR -8[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	mov	rax, QWORD PTR -8[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE12:
	.size	vec4state_new, .-vec4state_new
	.section	.rodata
	.align 8
.LC2:
	.string	"FATAL: failed re-allocating %lu bytes for vec4state!"
	.text
	.globl	vec4state_resize
	.type	vec4state_resize, @function
vec4state_resize:
.LFB13:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 48
	mov	QWORD PTR -40[rbp], rdi
	mov	QWORD PTR -48[rbp], rsi
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 7
	shr	rax, 3
	mov	rdx, rax
	mov	rax, QWORD PTR -48[rbp]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	je	.L41
	mov	rax, QWORD PTR -48[rbp]
	add	rax, 7
	shr	rax, 3
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 24[rax]
	mov	rsi, rdx
	mov	rdi, rax
	call	realloc@PLT
	mov	QWORD PTR -8[rbp], rax
	cmp	QWORD PTR -8[rbp], 0
	jne	.L42
	mov	rax, QWORD PTR -48[rbp]
	add	rax, 7
	shr	rax, 3
	lea	rdx, [rax+rax]
	mov	rax, QWORD PTR stderr[rip]
	lea	rsi, .LC2[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	call	abort@PLT
.L42:
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR -8[rbp]
	mov	QWORD PTR 24[rax], rdx
.L41:
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR -48[rbp]
	mov	QWORD PTR 8[rax], rdx
	mov	rax, QWORD PTR -16[rbp]
	cmp	rax, QWORD PTR -48[rbp]
	jnb	.L43
	mov	rax, QWORD PTR -16[rbp]
	lea	edx, -1[rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_bit_test
	mov	DWORD PTR -20[rbp], eax
	mov	rax, QWORD PTR -40[rbp]
	mov	eax, DWORD PTR 16[rax]
	test	eax, eax
	jne	.L44
	cmp	DWORD PTR -20[rbp], 1
	jne	.L44
	mov	DWORD PTR -20[rbp], 0
.L44:
	mov	rax, QWORD PTR -48[rbp]
	lea	esi, -1[rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	edi, eax
	mov	edx, DWORD PTR -20[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, edx
	mov	edx, esi
	mov	esi, edi
	mov	rdi, rax
	call	vec4state_bitfield_set
.L43:
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
	mov	eax, 1
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE13:
	.size	vec4state_resize, .-vec4state_resize
	.globl	vec4state_free
	.type	vec4state_free, @function
vec4state_free:
.LFB14:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	cmp	QWORD PTR -8[rbp], 0
	je	.L48
	mov	rax, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR 24[rax]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	free@PLT
.L48:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE14:
	.size	vec4state_free, .-vec4state_free
	.type	vec4state_copy, @function
vec4state_copy:
.LFB15:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L50
.L55:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L51
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L52
.L51:
	mov	eax, 0
.L52:
	mov	rdx, QWORD PTR -32[rbp]
	mov	rcx, QWORD PTR 24[rdx]
	mov	edx, DWORD PTR -4[rbp]
	movsx	rdx, edx
	add	rdx, rdx
	add	rdx, rcx
	mov	BYTE PTR [rdx], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L53
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L54
.L53:
	mov	eax, 0
.L54:
	mov	rdx, QWORD PTR -32[rbp]
	mov	rcx, QWORD PTR 24[rdx]
	mov	edx, DWORD PTR -4[rbp]
	movsx	rdx, edx
	add	rdx, rdx
	add	rdx, rcx
	mov	BYTE PTR 1[rdx], al
	add	DWORD PTR -4[rbp], 1
.L50:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L55
	mov	rax, QWORD PTR -32[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE15:
	.size	vec4state_copy, .-vec4state_copy
	.type	vec4state_padded_signed_word_a, @function
vec4state_padded_signed_word_a:
.LFB16:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	eax, DWORD PTR -28[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	sub	rax, 1
	cmp	rdx, rax
	jnb	.L57
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L58
.L57:
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	lea	edx, -1[rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_bit_test
	test	eax, eax
	jne	.L59
	mov	eax, 0
	jmp	.L60
.L59:
	mov	eax, -1
.L60:
	mov	BYTE PTR -1[rbp], al
	mov	eax, DWORD PTR -28[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	sub	rax, 1
	cmp	rdx, rax
	jne	.L61
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	neg	eax
	and	eax, 7
	mov	edx, 255
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	not	eax
	and	al, BYTE PTR -1[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	movzx	eax, BYTE PTR [rax]
	or	eax, edx
	mov	BYTE PTR -1[rbp], al
.L61:
	movzx	eax, BYTE PTR -1[rbp]
.L58:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE16:
	.size	vec4state_padded_signed_word_a, .-vec4state_padded_signed_word_a
	.globl	vec4state_cmp
	.type	vec4state_cmp, @function
vec4state_cmp:
.LFB17:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	jne	.L63
	mov	rax, QWORD PTR -32[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	je	.L64
.L63:
	mov	eax, 3
	jmp	.L65
.L64:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	je	.L66
	mov	rax, QWORD PTR -24[rbp]
	mov	eax, DWORD PTR 16[rax]
	test	eax, eax
	je	.L67
	mov	rax, QWORD PTR -32[rbp]
	mov	eax, DWORD PTR 16[rax]
	test	eax, eax
	jne	.L66
.L67:
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	cmovnb	rax, rdx
	add	rax, 7
	shr	rax, 3
	sub	eax, 1
	mov	DWORD PTR -4[rbp], eax
	jmp	.L68
.L75:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L69
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L70
.L69:
	mov	eax, 0
.L70:
	mov	BYTE PTR -8[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L71
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L72
.L71:
	mov	eax, 0
.L72:
	mov	BYTE PTR -7[rbp], al
	movzx	eax, BYTE PTR -8[rbp]
	cmp	al, BYTE PTR -7[rbp]
	jnb	.L73
	mov	eax, -1
	jmp	.L65
.L73:
	movzx	eax, BYTE PTR -8[rbp]
	cmp	al, BYTE PTR -7[rbp]
	jbe	.L74
	mov	eax, 1
	jmp	.L65
.L74:
	sub	DWORD PTR -4[rbp], 1
.L68:
	cmp	DWORD PTR -4[rbp], 0
	jns	.L75
	jmp	.L76
.L66:
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	cmovnb	rax, rdx
	add	rax, 7
	shr	rax, 3
	sub	eax, 1
	mov	DWORD PTR -4[rbp], eax
	jmp	.L77
.L80:
	mov	edx, DWORD PTR -4[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_padded_signed_word_a
	mov	BYTE PTR -6[rbp], al
	mov	edx, DWORD PTR -4[rbp]
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_padded_signed_word_a
	mov	BYTE PTR -5[rbp], al
	movzx	eax, BYTE PTR -6[rbp]
	cmp	al, BYTE PTR -5[rbp]
	jge	.L78
	mov	eax, -1
	jmp	.L65
.L78:
	movzx	eax, BYTE PTR -6[rbp]
	cmp	al, BYTE PTR -5[rbp]
	jle	.L79
	mov	eax, 1
	jmp	.L65
.L79:
	sub	DWORD PTR -4[rbp], 1
.L77:
	cmp	DWORD PTR -4[rbp], 0
	jns	.L80
.L76:
	mov	eax, 0
.L65:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE17:
	.size	vec4state_cmp, .-vec4state_cmp
	.globl	vec4state_case_equality
	.type	vec4state_case_equality, @function
vec4state_case_equality:
.LFB18:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	je	.L82
	mov	eax, 0
	jmp	.L83
.L82:
	mov	DWORD PTR -4[rbp], 0
	jmp	.L84
.L87:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR [rax]
	mov	rax, QWORD PTR -32[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	movzx	eax, BYTE PTR [rax]
	cmp	dl, al
	jne	.L85
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR 1[rax]
	mov	rax, QWORD PTR -32[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	movzx	eax, BYTE PTR 1[rax]
	cmp	dl, al
	je	.L86
.L85:
	mov	eax, 0
	jmp	.L83
.L86:
	add	DWORD PTR -4[rbp], 1
.L84:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L87
	mov	eax, 1
.L83:
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE18:
	.size	vec4state_case_equality, .-vec4state_case_equality
	.globl	vec4state_bitwise_binary_and
	.type	vec4state_bitwise_binary_and, @function
vec4state_bitwise_binary_and:
.LFB19:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	QWORD PTR -40[rbp], rdx
	mov	DWORD PTR -4[rbp], 0
	jmp	.L89
.L98:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L90
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L91
.L90:
	mov	eax, 0
.L91:
	mov	BYTE PTR -8[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L92
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L93
.L92:
	mov	eax, 0
.L93:
	mov	BYTE PTR -7[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L94
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L95
.L94:
	mov	eax, 0
.L95:
	mov	BYTE PTR -6[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L96
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L97
.L96:
	mov	eax, 0
.L97:
	mov	BYTE PTR -5[rbp], al
	movzx	eax, BYTE PTR -5[rbp]
	or	al, BYTE PTR -6[rbp]
	and	al, BYTE PTR -7[rbp]
	mov	edx, eax
	movzx	eax, BYTE PTR -8[rbp]
	and	al, BYTE PTR -5[rbp]
	or	edx, eax
	movzx	eax, BYTE PTR -8[rbp]
	and	al, BYTE PTR -6[rbp]
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR [rax], dl
	movzx	eax, BYTE PTR -5[rbp]
	or	al, BYTE PTR -6[rbp]
	and	al, BYTE PTR -7[rbp]
	mov	edx, eax
	movzx	eax, BYTE PTR -8[rbp]
	and	al, BYTE PTR -5[rbp]
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR 1[rax], dl
	add	DWORD PTR -4[rbp], 1
.L89:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L98
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE19:
	.size	vec4state_bitwise_binary_and, .-vec4state_bitwise_binary_and
	.globl	vec4state_bitwise_binary_or
	.type	vec4state_bitwise_binary_or, @function
vec4state_bitwise_binary_or:
.LFB20:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	QWORD PTR -40[rbp], rdx
	mov	DWORD PTR -4[rbp], 0
	jmp	.L100
.L109:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L101
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L102
.L101:
	mov	eax, 0
.L102:
	mov	BYTE PTR -8[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L103
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L104
.L103:
	mov	eax, 0
.L104:
	mov	BYTE PTR -7[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L105
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L106
.L105:
	mov	eax, 0
.L106:
	mov	BYTE PTR -6[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L107
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L108
.L107:
	mov	eax, 0
.L108:
	mov	BYTE PTR -5[rbp], al
	movzx	eax, BYTE PTR -8[rbp]
	or	al, BYTE PTR -7[rbp]
	or	al, BYTE PTR -6[rbp]
	or	al, BYTE PTR -5[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	mov	BYTE PTR [rax], dl
	movzx	eax, BYTE PTR -8[rbp]
	not	eax
	mov	edx, eax
	movzx	eax, BYTE PTR -5[rbp]
	and	edx, eax
	movzx	eax, BYTE PTR -6[rbp]
	not	eax
	mov	ecx, eax
	movzx	eax, BYTE PTR -7[rbp]
	and	eax, ecx
	mov	ecx, edx
	or	ecx, eax
	movzx	eax, BYTE PTR -7[rbp]
	and	al, BYTE PTR -5[rbp]
	mov	esi, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	or	ecx, esi
	mov	edx, ecx
	mov	BYTE PTR 1[rax], dl
	add	DWORD PTR -4[rbp], 1
.L100:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L109
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE20:
	.size	vec4state_bitwise_binary_or, .-vec4state_bitwise_binary_or
	.globl	vec4state_bitwise_binary_xor
	.type	vec4state_bitwise_binary_xor, @function
vec4state_bitwise_binary_xor:
.LFB21:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	QWORD PTR -40[rbp], rdx
	mov	DWORD PTR -4[rbp], 0
	jmp	.L111
.L120:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L112
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L113
.L112:
	mov	eax, 0
.L113:
	mov	BYTE PTR -8[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L114
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L115
.L114:
	mov	eax, 0
.L115:
	mov	BYTE PTR -7[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L116
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L117
.L116:
	mov	eax, 0
.L117:
	mov	BYTE PTR -6[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L118
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L119
.L118:
	mov	eax, 0
.L119:
	mov	BYTE PTR -5[rbp], al
	movzx	eax, BYTE PTR -5[rbp]
	or	al, BYTE PTR -7[rbp]
	mov	ecx, eax
	movzx	eax, BYTE PTR -8[rbp]
	not	eax
	mov	edx, eax
	movzx	eax, BYTE PTR -6[rbp]
	and	eax, edx
	mov	esi, ecx
	or	esi, eax
	movzx	eax, BYTE PTR -6[rbp]
	not	eax
	mov	edx, eax
	movzx	eax, BYTE PTR -8[rbp]
	mov	ecx, edx
	and	ecx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	or	esi, ecx
	mov	edx, esi
	mov	BYTE PTR [rax], dl
	movzx	eax, BYTE PTR -5[rbp]
	or	al, BYTE PTR -7[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	mov	BYTE PTR 1[rax], dl
	add	DWORD PTR -4[rbp], 1
.L111:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L120
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE21:
	.size	vec4state_bitwise_binary_xor, .-vec4state_bitwise_binary_xor
	.globl	vec4state_bitwise_unary_negation
	.type	vec4state_bitwise_unary_negation, @function
vec4state_bitwise_unary_negation:
.LFB22:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L122
.L127:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L123
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L124
.L123:
	mov	eax, 0
.L124:
	mov	BYTE PTR -6[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L125
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L126
.L125:
	mov	eax, 0
.L126:
	mov	BYTE PTR -5[rbp], al
	movzx	eax, BYTE PTR -6[rbp]
	not	eax
	mov	esi, eax
	movzx	edx, BYTE PTR -5[rbp]
	mov	rax, QWORD PTR -32[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	or	edx, esi
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rdx, rax
	movzx	eax, BYTE PTR -5[rbp]
	mov	BYTE PTR 1[rdx], al
	add	DWORD PTR -4[rbp], 1
.L122:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L127
	mov	rax, QWORD PTR -32[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE22:
	.size	vec4state_bitwise_unary_negation, .-vec4state_bitwise_unary_negation
	.globl	vec4state_reduction_unary_and
	.type	vec4state_reduction_unary_and, @function
vec4state_reduction_unary_and:
.LFB23:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L129
.L132:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR [rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	movzx	eax, BYTE PTR 1[rax]
	or	eax, edx
	cmp	al, -1
	je	.L130
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_set
	jmp	.L128
.L130:
	add	DWORD PTR -4[rbp], 1
.L129:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	sub	rax, 1
	cmp	rdx, rax
	jb	.L132
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	add	rax, rax
	sub	rax, 2
	add	rax, rdx
	movzx	edx, BYTE PTR [rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	add	rax, rax
	sub	rax, 2
	add	rax, rcx
	movzx	eax, BYTE PTR 1[rax]
	or	eax, edx
	movsx	edx, al
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	neg	eax
	and	eax, 7
	mov	esi, 255
	mov	ecx, eax
	sar	esi, cl
	mov	eax, esi
	cmp	edx, eax
	je	.L133
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_set
	jmp	.L128
.L133:
	mov	DWORD PTR -4[rbp], 0
	jmp	.L134
.L136:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	test	al, al
	je	.L135
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L128
.L135:
	add	DWORD PTR -4[rbp], 1
.L134:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L136
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_set
.L128:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE23:
	.size	vec4state_reduction_unary_and, .-vec4state_reduction_unary_and
	.globl	vec4state_reduction_unary_or
	.type	vec4state_reduction_unary_or, @function
vec4state_reduction_unary_or:
.LFB24:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L138
.L141:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	edx, al
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	movzx	eax, BYTE PTR 1[rax]
	movsx	eax, al
	not	eax
	and	eax, edx
	test	eax, eax
	je	.L139
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_set
	jmp	.L137
.L139:
	add	DWORD PTR -4[rbp], 1
.L138:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L141
	mov	DWORD PTR -4[rbp], 0
	jmp	.L142
.L144:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	test	al, al
	je	.L143
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L137
.L143:
	add	DWORD PTR -4[rbp], 1
.L142:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L144
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_set
.L137:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE24:
	.size	vec4state_reduction_unary_or, .-vec4state_reduction_unary_or
	.type	count_bits, @function
count_bits:
.LFB25:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	BYTE PTR -20[rbp], al
	mov	DWORD PTR -4[rbp], 0
	jmp	.L146
.L147:
	movzx	eax, BYTE PTR -20[rbp]
	sub	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR -20[rbp]
	and	eax, edx
	mov	BYTE PTR -20[rbp], al
	add	DWORD PTR -4[rbp], 1
.L146:
	cmp	BYTE PTR -20[rbp], 0
	jne	.L147
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE25:
	.size	count_bits, .-count_bits
	.globl	vec4state_reduction_unary_xor
	.type	vec4state_reduction_unary_xor, @function
vec4state_reduction_unary_xor:
.LFB26:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -8[rbp], 0
	mov	DWORD PTR -4[rbp], 0
	jmp	.L150
.L153:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	test	al, al
	je	.L151
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L149
.L151:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	edi, eax
	call	count_bits
	add	DWORD PTR -8[rbp], eax
	add	DWORD PTR -4[rbp], 1
.L150:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L153
	mov	eax, DWORD PTR -8[rbp]
	and	eax, 1
	mov	edx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_set
.L149:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE26:
	.size	vec4state_reduction_unary_xor, .-vec4state_reduction_unary_xor
	.globl	vec4state_shift_right
	.type	vec4state_shift_right, @function
vec4state_shift_right:
.LFB27:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 56
	mov	QWORD PTR -40[rbp], rdi
	mov	DWORD PTR -44[rbp], esi
	mov	QWORD PTR -56[rbp], rdx
	mov	DWORD PTR -48[rbp], ecx
	mov	WORD PTR -24[rbp], 0
	mov	WORD PTR -22[rbp], 0
	cmp	DWORD PTR -44[rbp], 0
	jle	.L155
	mov	eax, DWORD PTR -44[rbp]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -44[rbp]
	cdq
	shr	edx, 29
	add	eax, edx
	and	eax, 7
	sub	eax, edx
	mov	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	mov	DWORD PTR -12[rbp], eax
	jmp	.L156
.L155:
	mov	eax, DWORD PTR -44[rbp]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	neg	eax
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -44[rbp]
	neg	eax
	cdq
	shr	edx, 29
	add	eax, edx
	and	eax, 7
	sub	eax, edx
	mov	edx, eax
	mov	eax, 8
	sub	eax, edx
	mov	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR -8[rbp]
	sub	eax, 1
	mov	DWORD PTR -12[rbp], eax
.L156:
	cmp	DWORD PTR -12[rbp], 0
	js	.L157
	mov	eax, DWORD PTR -12[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L157
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	WORD PTR -24[rbp], ax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	movzx	eax, al
	mov	WORD PTR -22[rbp], ax
.L157:
	mov	DWORD PTR -16[rbp], 0
	jmp	.L158
.L160:
	add	DWORD PTR -12[rbp], 1
	cmp	DWORD PTR -12[rbp], 0
	js	.L159
	mov	eax, DWORD PTR -12[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L159
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 8
	mov	edx, eax
	movzx	eax, WORD PTR -24[rbp]
	or	eax, edx
	mov	WORD PTR -24[rbp], ax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	movzx	eax, al
	sal	eax, 8
	mov	edx, eax
	movzx	eax, WORD PTR -22[rbp]
	or	eax, edx
	mov	WORD PTR -22[rbp], ax
.L159:
	movzx	edx, WORD PTR -24[rbp]
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	ecx, edx
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -16[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR [rax], dl
	movzx	edx, WORD PTR -22[rbp]
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	ecx, edx
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -16[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR 1[rax], dl
	shr	WORD PTR -24[rbp], 8
	shr	WORD PTR -22[rbp], 8
	add	DWORD PTR -16[rbp], 1
.L158:
	mov	eax, DWORD PTR -16[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L160
	cmp	DWORD PTR -48[rbp], 0
	je	.L161
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	lea	edx, -1[rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_bit_test
	mov	DWORD PTR -4[rbp], eax
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	lea	edi, -1[rax]
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, DWORD PTR -44[rbp]
	sub	eax, edx
	lea	esi, -1[rax]
	mov	edx, DWORD PTR -4[rbp]
	mov	rax, QWORD PTR -56[rbp]
	mov	ecx, edx
	mov	edx, edi
	mov	rdi, rax
	call	vec4state_bitfield_set
.L161:
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE27:
	.size	vec4state_shift_right, .-vec4state_shift_right
	.globl	vec4state_shift_left
	.type	vec4state_shift_left, @function
vec4state_shift_left:
.LFB28:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 24
	mov	QWORD PTR -8[rbp], rdi
	mov	DWORD PTR -12[rbp], esi
	mov	QWORD PTR -24[rbp], rdx
	mov	eax, DWORD PTR -12[rbp]
	neg	eax
	mov	esi, eax
	mov	rdx, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR -8[rbp]
	mov	ecx, 0
	mov	rdi, rax
	call	vec4state_shift_right
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE28:
	.size	vec4state_shift_left, .-vec4state_shift_left
	.globl	vec4state_add_unsigned_word
	.type	vec4state_add_unsigned_word, @function
vec4state_add_unsigned_word:
.LFB29:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 40
	mov	QWORD PTR -24[rbp], rdi
	mov	eax, esi
	mov	QWORD PTR -40[rbp], rdx
	mov	BYTE PTR -28[rbp], al
	movzx	eax, BYTE PTR -28[rbp]
	mov	WORD PTR -6[rbp], ax
	mov	DWORD PTR -4[rbp], 0
	jmp	.L164
.L167:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	test	al, al
	je	.L165
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L163
.L165:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	add	WORD PTR -6[rbp], ax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, WORD PTR -6[rbp]
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	BYTE PTR 1[rax], 0
	shr	WORD PTR -6[rbp], 8
	add	DWORD PTR -4[rbp], 1
.L164:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L167
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
.L163:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE29:
	.size	vec4state_add_unsigned_word, .-vec4state_add_unsigned_word
	.globl	vec4state_add
	.type	vec4state_add, @function
vec4state_add:
.LFB30:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 40
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	QWORD PTR -40[rbp], rdx
	mov	WORD PTR -6[rbp], 0
	mov	DWORD PTR -4[rbp], 0
	jmp	.L169
.L181:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L170
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L171
.L170:
	mov	eax, 0
.L171:
	mov	BYTE PTR -10[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L172
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L173
.L172:
	mov	eax, 0
.L173:
	mov	BYTE PTR -9[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L174
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L175
.L174:
	mov	eax, 0
.L175:
	mov	BYTE PTR -8[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L176
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L177
.L176:
	mov	eax, 0
.L177:
	mov	BYTE PTR -7[rbp], al
	cmp	BYTE PTR -9[rbp], 0
	jne	.L178
	cmp	BYTE PTR -7[rbp], 0
	je	.L179
.L178:
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L168
.L179:
	movzx	eax, WORD PTR -6[rbp]
	shr	ax, 8
	mov	edx, eax
	movzx	eax, BYTE PTR -10[rbp]
	add	edx, eax
	movzx	eax, BYTE PTR -8[rbp]
	add	eax, edx
	mov	WORD PTR -6[rbp], ax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, WORD PTR -6[rbp]
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	BYTE PTR 1[rax], 0
	add	DWORD PTR -4[rbp], 1
.L169:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L181
.L168:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE30:
	.size	vec4state_add, .-vec4state_add
	.globl	vec4state_sub
	.type	vec4state_sub, @function
vec4state_sub:
.LFB31:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 40
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	QWORD PTR -40[rbp], rdx
	mov	WORD PTR -6[rbp], 0
	mov	DWORD PTR -4[rbp], 0
	jmp	.L183
.L195:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L184
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L185
.L184:
	mov	eax, 0
.L185:
	mov	BYTE PTR -10[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L186
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L187
.L186:
	mov	eax, 0
.L187:
	mov	BYTE PTR -9[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L188
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L189
.L188:
	mov	eax, 0
.L189:
	mov	BYTE PTR -8[rbp], al
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L190
	mov	rax, QWORD PTR -32[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	jmp	.L191
.L190:
	mov	eax, 0
.L191:
	mov	BYTE PTR -7[rbp], al
	cmp	BYTE PTR -9[rbp], 0
	jne	.L192
	cmp	BYTE PTR -7[rbp], 0
	je	.L193
.L192:
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L182
.L193:
	movzx	eax, WORD PTR -6[rbp]
	shr	ax, 8
	mov	edx, eax
	movzx	eax, BYTE PTR -10[rbp]
	add	eax, edx
	movzx	edx, BYTE PTR -8[rbp]
	sub	eax, edx
	mov	WORD PTR -6[rbp], ax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, WORD PTR -6[rbp]
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	BYTE PTR 1[rax], 0
	add	DWORD PTR -4[rbp], 1
.L183:
	mov	eax, DWORD PTR -4[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L195
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
.L182:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE31:
	.size	vec4state_sub, .-vec4state_sub
	.type	add3, @function
add3:
.LFB32:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	ecx, edi
	mov	eax, esi
	mov	QWORD PTR -32[rbp], rdx
	mov	edx, ecx
	mov	WORD PTR -20[rbp], dx
	mov	WORD PTR -24[rbp], ax
	mov	rax, QWORD PTR -32[rbp]
	movzx	eax, WORD PTR [rax]
	mov	WORD PTR -6[rbp], ax
	movzx	edx, WORD PTR -20[rbp]
	movzx	eax, WORD PTR -24[rbp]
	add	eax, edx
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	movzx	eax, WORD PTR -6[rbp]
	add	eax, edx
	mov	WORD PTR -2[rbp], ax
	mov	WORD PTR -6[rbp], 0
	movzx	eax, WORD PTR -4[rbp]
	cmp	ax, WORD PTR -24[rbp]
	jnb	.L197
	movzx	eax, WORD PTR -6[rbp]
	add	eax, 1
	mov	WORD PTR -6[rbp], ax
.L197:
	movzx	eax, WORD PTR -2[rbp]
	cmp	ax, WORD PTR -4[rbp]
	jnb	.L198
	movzx	eax, WORD PTR -6[rbp]
	add	eax, 1
	mov	WORD PTR -6[rbp], ax
.L198:
	movzx	eax, WORD PTR -2[rbp]
	cmp	ax, WORD PTR -20[rbp]
	jnb	.L199
	movzx	eax, WORD PTR -6[rbp]
	add	eax, 1
	mov	WORD PTR -6[rbp], ax
.L199:
	mov	rax, QWORD PTR -32[rbp]
	movzx	edx, WORD PTR -6[rbp]
	mov	WORD PTR [rax], dx
	movzx	eax, WORD PTR -2[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE32:
	.size	add3, .-add3
	.globl	vec4state_mul_unsigned_word
	.type	vec4state_mul_unsigned_word, @function
vec4state_mul_unsigned_word:
.LFB33:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	QWORD PTR -40[rbp], rdi
	mov	eax, esi
	mov	QWORD PTR -56[rbp], rdx
	mov	BYTE PTR -44[rbp], al
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	je	.L202
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L201
.L202:
	mov	WORD PTR -16[rbp], 0
	mov	WORD PTR -18[rbp], 0
	mov	DWORD PTR -12[rbp], 0
	jmp	.L204
.L207:
	mov	eax, DWORD PTR -12[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L205
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	jmp	.L206
.L205:
	mov	eax, 0
.L206:
	mov	BYTE PTR -19[rbp], al
	movzx	edx, BYTE PTR -19[rbp]
	movzx	eax, BYTE PTR -44[rbp]
	imul	eax, edx
	mov	WORD PTR -14[rbp], ax
	movzx	ecx, WORD PTR -14[rbp]
	movzx	eax, WORD PTR -16[rbp]
	lea	rdx, -18[rbp]
	mov	esi, ecx
	mov	edi, eax
	call	add3
	mov	WORD PTR -16[rbp], ax
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, WORD PTR -16[rbp]
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	BYTE PTR 1[rax], 0
	shr	WORD PTR -16[rbp], 8
	add	DWORD PTR -12[rbp], 1
.L204:
	mov	eax, DWORD PTR -12[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L207
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
.L201:
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L208
	call	__stack_chk_fail@PLT
.L208:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE33:
	.size	vec4state_mul_unsigned_word, .-vec4state_mul_unsigned_word
	.globl	vec4state_mul
	.type	vec4state_mul, @function
vec4state_mul:
.LFB34:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	QWORD PTR -40[rbp], rdi
	mov	QWORD PTR -48[rbp], rsi
	mov	QWORD PTR -56[rbp], rdx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	jne	.L210
	mov	rax, QWORD PTR -48[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	je	.L211
.L210:
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L209
.L211:
	mov	WORD PTR -28[rbp], 0
	mov	WORD PTR -30[rbp], 0
	mov	DWORD PTR -24[rbp], 0
	jmp	.L213
.L217:
	mov	DWORD PTR -20[rbp], 0
	jmp	.L214
.L216:
	mov	eax, DWORD PTR -24[rbp]
	sub	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -12[rbp], eax
	mov	edx, DWORD PTR -16[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L215
	mov	edx, DWORD PTR -12[rbp]
	mov	rax, QWORD PTR -48[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L215
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -16[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -48[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	add	rax, rax
	add	rax, rcx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	imul	eax, edx
	mov	WORD PTR -26[rbp], ax
	movzx	ecx, WORD PTR -26[rbp]
	movzx	eax, WORD PTR -28[rbp]
	lea	rdx, -30[rbp]
	mov	esi, ecx
	mov	edi, eax
	call	add3
	mov	WORD PTR -28[rbp], ax
.L215:
	add	DWORD PTR -20[rbp], 1
.L214:
	mov	eax, DWORD PTR -20[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -48[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L216
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -24[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, WORD PTR -28[rbp]
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -24[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	BYTE PTR 1[rax], 0
	shr	WORD PTR -28[rbp], 8
	add	DWORD PTR -24[rbp], 1
.L213:
	mov	eax, DWORD PTR -24[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L217
.L209:
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L218
	call	__stack_chk_fail@PLT
.L218:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE34:
	.size	vec4state_mul, .-vec4state_mul
	.globl	vec4state_div_unsigned_word
	.type	vec4state_div_unsigned_word, @function
vec4state_div_unsigned_word:
.LFB35:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 40
	mov	QWORD PTR -24[rbp], rdi
	mov	eax, esi
	mov	QWORD PTR -40[rbp], rdx
	mov	BYTE PTR -28[rbp], al
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	je	.L220
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	mov	eax, 0
	jmp	.L221
.L220:
	mov	WORD PTR -10[rbp], 0
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	sub	eax, 1
	mov	DWORD PTR -4[rbp], eax
	jmp	.L222
.L223:
	movzx	eax, WORD PTR -10[rbp]
	sal	eax, 8
	mov	ecx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	or	eax, ecx
	mov	WORD PTR -8[rbp], ax
	movzx	eax, WORD PTR -8[rbp]
	movzx	ecx, BYTE PTR -28[rbp]
	cdq
	idiv	ecx
	mov	eax, edx
	mov	WORD PTR -10[rbp], ax
	movzx	eax, WORD PTR -8[rbp]
	movzx	esi, BYTE PTR -28[rbp]
	cdq
	idiv	esi
	mov	WORD PTR -6[rbp], ax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, WORD PTR -6[rbp]
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -40[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	BYTE PTR 1[rax], 0
	sub	DWORD PTR -4[rbp], 1
.L222:
	cmp	DWORD PTR -4[rbp], 0
	jns	.L223
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
	movzx	eax, WORD PTR -10[rbp]
.L221:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE35:
	.size	vec4state_div_unsigned_word, .-vec4state_div_unsigned_word
	.globl	vec4state_div_unsigned
	.type	vec4state_div_unsigned, @function
vec4state_div_unsigned:
.LFB36:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	push	r15
	push	r14
	push	r13
	push	r12
	push	rbx
	sub	rsp, 200
	.cfi_offset 15, -24
	.cfi_offset 14, -32
	.cfi_offset 13, -40
	.cfi_offset 12, -48
	.cfi_offset 3, -56
	mov	QWORD PTR -152[rbp], rdi
	mov	QWORD PTR -160[rbp], rsi
	mov	QWORD PTR -168[rbp], rdx
	mov	QWORD PTR -176[rbp], rcx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -56[rbp], rax
	xor	eax, eax
	mov	rax, QWORD PTR -160[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	mov	DWORD PTR -112[rbp], eax
	jmp	.L225
.L227:
	sub	DWORD PTR -112[rbp], 1
.L225:
	cmp	DWORD PTR -112[rbp], 0
	jle	.L226
	mov	rax, QWORD PTR -160[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -112[rbp]
	cdqe
	add	rax, rax
	sub	rax, 2
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	test	al, al
	je	.L227
.L226:
	cmp	DWORD PTR -112[rbp], 0
	je	.L228
	mov	rax, QWORD PTR -152[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	jne	.L228
	mov	rax, QWORD PTR -160[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	je	.L229
.L228:
	mov	rax, QWORD PTR -168[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	mov	rax, QWORD PTR -176[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L230
.L229:
	mov	rax, rsp
	mov	rbx, rax
	mov	rax, QWORD PTR -168[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	mov	DWORD PTR -108[rbp], eax
	mov	eax, DWORD PTR -108[rbp]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR -112[rbp]
	add	eax, edx
	lea	edx, 1[rax]
	movsx	rax, edx
	sub	rax, 1
	mov	QWORD PTR -104[rbp], rax
	movsx	rax, edx
	mov	QWORD PTR -192[rbp], rax
	mov	QWORD PTR -184[rbp], 0
	movsx	rax, edx
	mov	QWORD PTR -208[rbp], rax
	mov	QWORD PTR -200[rbp], 0
	movsx	rax, edx
	mov	edx, 16
	sub	rdx, 1
	add	rax, rdx
	mov	edi, 16
	mov	edx, 0
	div	rdi
	imul	rax, rax, 16
	mov	rcx, rax
	and	rcx, -4096
	mov	rdx, rsp
	sub	rdx, rcx
.L231:
	cmp	rsp, rdx
	je	.L232
	sub	rsp, 4096
	or	QWORD PTR 4088[rsp], 0
	jmp	.L231
.L232:
	mov	rdx, rax
	and	edx, 4095
	sub	rsp, rdx
	mov	rdx, rax
	and	edx, 4095
	test	rdx, rdx
	je	.L233
	and	eax, 4095
	sub	rax, 8
	add	rax, rsp
	or	QWORD PTR [rax], 0
.L233:
	mov	rax, rsp
	add	rax, 0
	mov	QWORD PTR -96[rbp], rax
	mov	eax, DWORD PTR -112[rbp]
	add	eax, 2
	movsx	rdx, eax
	sub	rdx, 1
	mov	QWORD PTR -88[rbp], rdx
	movsx	rdx, eax
	mov	QWORD PTR -224[rbp], rdx
	mov	QWORD PTR -216[rbp], 0
	movsx	rdx, eax
	mov	QWORD PTR -240[rbp], rdx
	mov	QWORD PTR -232[rbp], 0
	cdqe
	mov	edx, 16
	sub	rdx, 1
	add	rax, rdx
	mov	esi, 16
	mov	edx, 0
	div	rsi
	imul	rax, rax, 16
	mov	rcx, rax
	and	rcx, -4096
	mov	rdx, rsp
	sub	rdx, rcx
.L234:
	cmp	rsp, rdx
	je	.L235
	sub	rsp, 4096
	or	QWORD PTR 4088[rsp], 0
	jmp	.L234
.L235:
	mov	rdx, rax
	and	edx, 4095
	sub	rsp, rdx
	mov	rdx, rax
	and	edx, 4095
	test	rdx, rdx
	je	.L236
	and	eax, 4095
	sub	rax, 8
	add	rax, rsp
	or	QWORD PTR [rax], 0
.L236:
	mov	rax, rsp
	add	rax, 0
	mov	QWORD PTR -80[rbp], rax
	mov	eax, DWORD PTR -108[rbp]
	add	eax, 1
	movsx	rdx, eax
	sub	rdx, 1
	mov	QWORD PTR -72[rbp], rdx
	movsx	rdx, eax
	mov	r14, rdx
	mov	r15d, 0
	movsx	rdx, eax
	mov	r12, rdx
	mov	r13d, 0
	cdqe
	mov	edx, 16
	sub	rdx, 1
	add	rax, rdx
	mov	edi, 16
	mov	edx, 0
	div	rdi
	imul	rax, rax, 16
	mov	rcx, rax
	and	rcx, -4096
	mov	rdx, rsp
	sub	rdx, rcx
.L237:
	cmp	rsp, rdx
	je	.L238
	sub	rsp, 4096
	or	QWORD PTR 4088[rsp], 0
	jmp	.L237
.L238:
	mov	rdx, rax
	and	edx, 4095
	sub	rsp, rdx
	mov	rdx, rax
	and	edx, 4095
	test	rdx, rdx
	je	.L239
	and	eax, 4095
	sub	rax, 8
	add	rax, rsp
	or	QWORD PTR [rax], 0
.L239:
	mov	rax, rsp
	add	rax, 0
	mov	QWORD PTR -64[rbp], rax
	mov	DWORD PTR -116[rbp], 1
	jmp	.L240
.L241:
	mov	rax, QWORD PTR -152[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	ecx, DWORD PTR -108[rbp]
	mov	eax, DWORD PTR -112[rbp]
	add	eax, ecx
	sub	eax, DWORD PTR -116[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	mov	ecx, eax
	mov	rdx, QWORD PTR -96[rbp]
	mov	eax, DWORD PTR -116[rbp]
	cdqe
	mov	BYTE PTR [rdx+rax], cl
	add	DWORD PTR -116[rbp], 1
.L240:
	mov	edx, DWORD PTR -108[rbp]
	mov	eax, DWORD PTR -112[rbp]
	add	eax, edx
	cmp	DWORD PTR -116[rbp], eax
	jle	.L241
	mov	edx, DWORD PTR -108[rbp]
	mov	eax, DWORD PTR -112[rbp]
	add	eax, edx
	add	eax, 1
	mov	rdx, QWORD PTR -80[rbp]
	cdqe
	mov	BYTE PTR [rdx+rax], 0
	mov	DWORD PTR -116[rbp], 1
	jmp	.L242
.L243:
	mov	rax, QWORD PTR -160[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -112[rbp]
	sub	eax, DWORD PTR -116[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	mov	ecx, eax
	mov	rdx, QWORD PTR -80[rbp]
	mov	eax, DWORD PTR -116[rbp]
	cdqe
	mov	BYTE PTR [rdx+rax], cl
	add	DWORD PTR -116[rbp], 1
.L242:
	mov	eax, DWORD PTR -116[rbp]
	cmp	eax, DWORD PTR -112[rbp]
	jle	.L243
	mov	eax, DWORD PTR -112[rbp]
	add	eax, 1
	mov	rdx, QWORD PTR -80[rbp]
	cdqe
	mov	BYTE PTR [rdx+rax], 0
	mov	DWORD PTR -120[rbp], 1
	jmp	.L244
.L252:
	mov	rdx, QWORD PTR -96[rbp]
	mov	eax, DWORD PTR -120[rbp]
	cdqe
	movzx	edx, BYTE PTR [rdx+rax]
	mov	rax, QWORD PTR -80[rbp]
	movzx	eax, BYTE PTR 1[rax]
	cmp	dl, al
	jne	.L245
	mov	WORD PTR -128[rbp], 255
	jmp	.L249
.L245:
	mov	rdx, QWORD PTR -96[rbp]
	mov	eax, DWORD PTR -120[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	movzx	eax, al
	sal	eax, 8
	mov	ecx, eax
	mov	eax, DWORD PTR -120[rbp]
	add	eax, 1
	mov	rdx, QWORD PTR -96[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	movzx	eax, al
	or	ecx, eax
	mov	rax, QWORD PTR -80[rbp]
	movzx	eax, BYTE PTR 1[rax]
	movzx	esi, al
	mov	eax, ecx
	cdq
	idiv	esi
	mov	WORD PTR -128[rbp], ax
.L249:
	mov	rdx, QWORD PTR -96[rbp]
	mov	eax, DWORD PTR -120[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	movzx	eax, al
	sal	eax, 8
	mov	ecx, eax
	mov	eax, DWORD PTR -120[rbp]
	add	eax, 1
	mov	rdx, QWORD PTR -96[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	movzx	eax, al
	or	eax, ecx
	mov	ecx, eax
	mov	rax, QWORD PTR -80[rbp]
	movzx	eax, BYTE PTR 1[rax]
	movzx	eax, al
	imul	ax, WORD PTR -128[rbp]
	mov	edx, eax
	mov	eax, ecx
	sub	eax, edx
	mov	WORD PTR -124[rbp], ax
	mov	rax, QWORD PTR -80[rbp]
	movzx	eax, BYTE PTR 2[rax]
	movzx	eax, al
	movzx	edx, WORD PTR -128[rbp]
	imul	eax, edx
	mov	WORD PTR -122[rbp], ax
	movzx	eax, WORD PTR -122[rbp]
	cmp	ax, WORD PTR -124[rbp]
	jb	.L247
	cmp	WORD PTR -124[rbp], 255
	ja	.L247
	movzx	ecx, WORD PTR -122[rbp]
	movzx	eax, WORD PTR -124[rbp]
	sal	eax, 8
	mov	esi, eax
	mov	eax, DWORD PTR -120[rbp]
	add	eax, 2
	mov	rdx, QWORD PTR -96[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	movzx	eax, al
	or	eax, esi
	cmp	ecx, eax
	jle	.L264
	sub	WORD PTR -128[rbp], 1
	jmp	.L249
.L264:
	nop
.L247:
	mov	WORD PTR -126[rbp], 0
	mov	WORD PTR -130[rbp], 0
	mov	eax, DWORD PTR -112[rbp]
	mov	DWORD PTR -116[rbp], eax
	jmp	.L250
.L251:
	movzx	eax, WORD PTR -128[rbp]
	neg	eax
	mov	ecx, eax
	mov	rdx, QWORD PTR -80[rbp]
	mov	eax, DWORD PTR -116[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	movzx	eax, al
	imul	eax, ecx
	movzx	ecx, ax
	mov	edx, DWORD PTR -120[rbp]
	mov	eax, DWORD PTR -116[rbp]
	add	eax, edx
	mov	rdx, QWORD PTR -96[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	movzx	edx, al
	movzx	eax, WORD PTR -126[rbp]
	add	eax, edx
	movzx	eax, ax
	lea	rdx, -130[rbp]
	mov	esi, ecx
	mov	edi, eax
	call	add3
	mov	WORD PTR -126[rbp], ax
	mov	edx, DWORD PTR -120[rbp]
	mov	eax, DWORD PTR -116[rbp]
	add	eax, edx
	movzx	edx, WORD PTR -126[rbp]
	mov	ecx, edx
	mov	rdx, QWORD PTR -96[rbp]
	cdqe
	mov	BYTE PTR [rdx+rax], cl
	shr	WORD PTR -126[rbp], 8
	sub	DWORD PTR -116[rbp], 1
.L250:
	cmp	DWORD PTR -116[rbp], 0
	jg	.L251
	movzx	eax, WORD PTR -128[rbp]
	mov	ecx, eax
	mov	rdx, QWORD PTR -64[rbp]
	mov	eax, DWORD PTR -120[rbp]
	cdqe
	mov	BYTE PTR [rdx+rax], cl
	add	DWORD PTR -120[rbp], 1
.L244:
	mov	eax, DWORD PTR -120[rbp]
	cmp	eax, DWORD PTR -108[rbp]
	jle	.L252
	cmp	QWORD PTR -168[rbp], 0
	je	.L253
	mov	DWORD PTR -116[rbp], 0
	jmp	.L254
.L257:
	mov	eax, DWORD PTR -116[rbp]
	cmp	eax, DWORD PTR -108[rbp]
	jge	.L255
	mov	eax, DWORD PTR -108[rbp]
	sub	eax, DWORD PTR -116[rbp]
	mov	rdx, QWORD PTR -64[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	mov	edx, eax
	jmp	.L256
.L255:
	mov	edx, 0
.L256:
	mov	rax, QWORD PTR -168[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -116[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -168[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -116[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	BYTE PTR 1[rax], 0
	add	DWORD PTR -116[rbp], 1
.L254:
	mov	eax, DWORD PTR -116[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -168[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L257
.L253:
	cmp	QWORD PTR -176[rbp], 0
	je	.L258
	mov	DWORD PTR -116[rbp], 0
	jmp	.L259
.L262:
	mov	eax, DWORD PTR -116[rbp]
	cmp	eax, DWORD PTR -112[rbp]
	jge	.L260
	mov	edx, DWORD PTR -108[rbp]
	mov	eax, DWORD PTR -112[rbp]
	add	eax, edx
	sub	eax, DWORD PTR -116[rbp]
	mov	rdx, QWORD PTR -96[rbp]
	cdqe
	movzx	eax, BYTE PTR [rdx+rax]
	mov	edx, eax
	jmp	.L261
.L260:
	mov	edx, 0
.L261:
	mov	rax, QWORD PTR -176[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -116[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -176[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -116[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	BYTE PTR 1[rax], 0
	add	DWORD PTR -116[rbp], 1
.L259:
	mov	eax, DWORD PTR -116[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -176[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L262
.L258:
	mov	rsp, rbx
.L230:
	nop
	mov	rax, QWORD PTR -56[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L263
	call	__stack_chk_fail@PLT
.L263:
	lea	rsp, -40[rbp]
	pop	rbx
	pop	r12
	pop	r13
	pop	r14
	pop	r15
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE36:
	.size	vec4state_div_unsigned, .-vec4state_div_unsigned
	.section	.rodata
	.align 8
.LC3:
	.string	"FATAL: vec4state_pow(): exponent overflow! (runtime may exceed your lifetime.)!\n"
	.text
	.globl	vec4state_pow
	.type	vec4state_pow, @function
vec4state_pow:
.LFB37:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	QWORD PTR -40[rbp], rdi
	mov	QWORD PTR -48[rbp], rsi
	mov	QWORD PTR -56[rbp], rdx
	mov	rax, QWORD PTR -40[rbp]
	lea	rsi, vec4state_const_zero[rip]
	mov	rdi, rax
	call	vec4state_cmp
	mov	DWORD PTR -24[rbp], eax
	mov	rax, QWORD PTR -48[rbp]
	lea	rsi, vec4state_const_zero[rip]
	mov	rdi, rax
	call	vec4state_cmp
	mov	DWORD PTR -20[rbp], eax
	mov	rax, QWORD PTR -40[rbp]
	lea	rsi, vec4state_const_one[rip]
	mov	rdi, rax
	call	vec4state_cmp
	mov	DWORD PTR -16[rbp], eax
	mov	rax, QWORD PTR -40[rbp]
	lea	rsi, vec4state_const_minus_one[rip]
	mov	rdi, rax
	call	vec4state_cmp
	mov	DWORD PTR -12[rbp], eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	jne	.L266
	mov	rax, QWORD PTR -48[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	je	.L267
.L266:
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L268
.L267:
	cmp	DWORD PTR -20[rbp], 0
	je	.L269
	cmp	DWORD PTR -16[rbp], 0
	jne	.L270
.L269:
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_set
	jmp	.L268
.L270:
	cmp	DWORD PTR -12[rbp], 0
	jne	.L271
	mov	rax, QWORD PTR -48[rbp]
	mov	rax, QWORD PTR 24[rax]
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	and	eax, 1
	test	eax, eax
	je	.L272
	mov	edx, -1
	jmp	.L273
.L272:
	mov	edx, 1
.L273:
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_set
	jmp	.L281
.L271:
	cmp	DWORD PTR -20[rbp], 0
	jns	.L274
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_set
	jmp	.L281
.L274:
	cmp	DWORD PTR -24[rbp], 0
	jne	.L275
	cmp	DWORD PTR -20[rbp], 0
	jns	.L276
	mov	edx, 3
	jmp	.L277
.L276:
	mov	edx, 0
.L277:
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_set
	jmp	.L281
.L275:
	mov	rax, QWORD PTR -48[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rax, 32
	jbe	.L278
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 80
	mov	esi, 1
	lea	rdi, .LC3[rip]
	call	fwrite@PLT
	call	abort@PLT
.L278:
	mov	rax, QWORD PTR -56[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -48[rbp]
	mov	rax, QWORD PTR 24[rax]
	movzx	eax, BYTE PTR [rax]
	mov	BYTE PTR -29[rbp], al
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_set
	mov	DWORD PTR -28[rbp], 0
	jmp	.L279
.L280:
	mov	rdx, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR -56[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_copy
	mov	rdx, QWORD PTR -56[rbp]
	mov	rcx, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR -8[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_mul
	add	DWORD PTR -28[rbp], 1
.L279:
	movzx	eax, BYTE PTR -29[rbp]
	cmp	DWORD PTR -28[rbp], eax
	jl	.L280
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	vec4state_free
	jmp	.L281
.L268:
.L281:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE37:
	.size	vec4state_pow, .-vec4state_pow
	.type	word_reverse_bits, @function
word_reverse_bits:
.LFB38:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	BYTE PTR -20[rbp], al
	mov	DWORD PTR -4[rbp], 8
	mov	BYTE PTR -5[rbp], -1
	jmp	.L283
.L284:
	movzx	edx, BYTE PTR -5[rbp]
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	edx, eax
	movzx	eax, BYTE PTR -5[rbp]
	xor	eax, edx
	mov	BYTE PTR -5[rbp], al
	movzx	edx, BYTE PTR -20[rbp]
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	edx, eax
	movzx	eax, BYTE PTR -5[rbp]
	mov	esi, edx
	and	esi, eax
	movzx	edx, BYTE PTR -20[rbp]
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	edx, eax
	movzx	eax, BYTE PTR -5[rbp]
	not	eax
	and	eax, edx
	or	eax, esi
	mov	BYTE PTR -20[rbp], al
.L283:
	shr	DWORD PTR -4[rbp]
	cmp	DWORD PTR -4[rbp], 0
	jne	.L284
	movzx	eax, BYTE PTR -20[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE38:
	.size	word_reverse_bits, .-word_reverse_bits
	.type	vec4state_get_word_at_bitpos, @function
vec4state_get_word_at_bitpos:
.LFB39:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	QWORD PTR -40[rbp], rdx
	mov	QWORD PTR -48[rbp], rcx
	mov	eax, DWORD PTR -28[rbp]
	sar	eax, 3
	mov	DWORD PTR -12[rbp], eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	DWORD PTR -12[rbp], eax
	jl	.L287
	mov	rax, QWORD PTR -40[rbp]
	mov	BYTE PTR [rax], 0
	mov	rax, QWORD PTR -48[rbp]
	mov	BYTE PTR [rax], 0
	jmp	.L292
.L287:
	mov	eax, DWORD PTR -28[rbp]
	and	eax, 7
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	add	eax, 1
	mov	DWORD PTR -4[rbp], eax
	cmp	DWORD PTR -12[rbp], 0
	jns	.L289
	mov	WORD PTR -16[rbp], 0
	mov	WORD PTR -14[rbp], 0
	jmp	.L290
.L289:
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	WORD PTR -16[rbp], ax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	movzx	eax, al
	mov	WORD PTR -14[rbp], ax
.L290:
	cmp	DWORD PTR -4[rbp], 0
	js	.L291
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	DWORD PTR -4[rbp], eax
	jge	.L291
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 8
	mov	edx, eax
	movzx	eax, WORD PTR -16[rbp]
	or	eax, edx
	mov	WORD PTR -16[rbp], ax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	movzx	eax, al
	sal	eax, 8
	mov	edx, eax
	movzx	eax, WORD PTR -14[rbp]
	or	eax, edx
	mov	WORD PTR -14[rbp], ax
.L291:
	movzx	edx, WORD PTR -16[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	WORD PTR -16[rbp], ax
	movzx	edx, WORD PTR -14[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	WORD PTR -14[rbp], ax
	movzx	eax, WORD PTR -16[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	BYTE PTR [rax], dl
	movzx	eax, WORD PTR -14[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -48[rbp]
	mov	BYTE PTR [rax], dl
.L292:
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE39:
	.size	vec4state_get_word_at_bitpos, .-vec4state_get_word_at_bitpos
	.globl	vec4state_bitselect_get
	.type	vec4state_bitselect_get, @function
vec4state_bitselect_get:
.LFB40:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 48
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	QWORD PTR -40[rbp], rdx
	mov	DWORD PTR -32[rbp], ecx
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	cmp	DWORD PTR -32[rbp], 0
	jne	.L294
	mov	esi, DWORD PTR -28[rbp]
	mov	rdx, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	ecx, 0
	mov	rdi, rax
	call	vec4state_shift_right
	jmp	.L295
.L294:
	mov	DWORD PTR -12[rbp], 0
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, eax
	mov	eax, DWORD PTR -28[rbp]
	add	eax, edx
	sub	eax, 8
	mov	DWORD PTR -28[rbp], eax
	jmp	.L296
.L297:
	mov	esi, DWORD PTR -28[rbp]
	lea	rcx, -13[rbp]
	lea	rdx, -14[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	vec4state_get_word_at_bitpos
	movzx	eax, BYTE PTR -14[rbp]
	movzx	eax, al
	mov	edi, eax
	call	word_reverse_bits
	mov	edx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	mov	BYTE PTR [rax], dl
	movzx	eax, BYTE PTR -13[rbp]
	movzx	eax, al
	mov	edi, eax
	call	word_reverse_bits
	mov	edx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rcx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	add	rax, rax
	add	rax, rcx
	mov	BYTE PTR 1[rax], dl
	add	DWORD PTR -12[rbp], 1
	sub	DWORD PTR -28[rbp], 8
.L296:
	mov	eax, DWORD PTR -12[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jb	.L297
.L295:
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L298
	call	__stack_chk_fail@PLT
.L298:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE40:
	.size	vec4state_bitselect_get, .-vec4state_bitselect_get
	.globl	vec4state_bitselect_set
	.type	vec4state_bitselect_set, @function
vec4state_bitselect_set:
.LFB41:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 88
	mov	QWORD PTR -72[rbp], rdi
	mov	DWORD PTR -76[rbp], esi
	mov	DWORD PTR -80[rbp], edx
	mov	QWORD PTR -88[rbp], rcx
	mov	eax, DWORD PTR -76[rbp]
	cmp	eax, DWORD PTR -80[rbp]
	jnb	.L300
	mov	eax, DWORD PTR -76[rbp]
	and	eax, 7
	mov	edx, eax
	mov	eax, 8
	sub	eax, edx
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR -76[rbp]
	shr	eax, 3
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -80[rbp]
	shr	eax, 3
	mov	DWORD PTR -4[rbp], eax
	mov	WORD PTR -48[rbp], 0
	mov	WORD PTR -46[rbp], 0
	mov	DWORD PTR -40[rbp], 0
	mov	eax, DWORD PTR -8[rbp]
	mov	DWORD PTR -36[rbp], eax
	jmp	.L301
.L307:
	mov	edx, DWORD PTR -40[rbp]
	mov	rax, QWORD PTR -72[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L302
	mov	rax, QWORD PTR -72[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -40[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	sal	eax, 8
	mov	edx, eax
	movzx	eax, WORD PTR -48[rbp]
	or	eax, edx
	mov	WORD PTR -48[rbp], ax
	mov	rax, QWORD PTR -72[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -40[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	movzx	eax, al
	sal	eax, 8
	mov	edx, eax
	movzx	eax, WORD PTR -46[rbp]
	or	eax, edx
	mov	WORD PTR -46[rbp], ax
.L302:
	mov	eax, DWORD PTR -36[rbp]
	cmp	eax, DWORD PTR -8[rbp]
	je	.L303
	mov	eax, DWORD PTR -36[rbp]
	cmp	eax, DWORD PTR -4[rbp]
	je	.L303
	movzx	edx, WORD PTR -48[rbp]
	mov	eax, DWORD PTR -12[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	ecx, edx
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -36[rbp]
	add	rax, rax
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR [rax], dl
	movzx	edx, WORD PTR -46[rbp]
	mov	eax, DWORD PTR -12[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	ecx, edx
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -36[rbp]
	add	rax, rax
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR 1[rax], dl
	jmp	.L304
.L303:
	mov	BYTE PTR -50[rbp], -1
	mov	eax, DWORD PTR -36[rbp]
	cmp	eax, DWORD PTR -8[rbp]
	jne	.L305
	mov	eax, DWORD PTR -76[rbp]
	and	eax, 7
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	neg	eax
	mov	edx, eax
	movzx	eax, BYTE PTR -50[rbp]
	and	eax, edx
	mov	BYTE PTR -50[rbp], al
.L305:
	mov	eax, DWORD PTR -36[rbp]
	cmp	eax, DWORD PTR -4[rbp]
	jne	.L306
	mov	eax, DWORD PTR -80[rbp]
	add	eax, 1
	and	eax, 7
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	sub	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR -50[rbp]
	and	eax, edx
	mov	BYTE PTR -50[rbp], al
.L306:
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -36[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR [rax]
	movzx	eax, BYTE PTR -50[rbp]
	not	eax
	mov	esi, edx
	and	esi, eax
	movzx	edx, WORD PTR -48[rbp]
	mov	eax, DWORD PTR -12[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	edx, eax
	movzx	eax, BYTE PTR -50[rbp]
	mov	ecx, edx
	and	ecx, eax
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -36[rbp]
	add	rax, rax
	add	rax, rdx
	or	esi, ecx
	mov	edx, esi
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -36[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR 1[rax]
	movzx	eax, BYTE PTR -50[rbp]
	not	eax
	mov	esi, edx
	and	esi, eax
	movzx	edx, WORD PTR -46[rbp]
	mov	eax, DWORD PTR -12[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	edx, eax
	movzx	eax, BYTE PTR -50[rbp]
	mov	ecx, edx
	and	ecx, eax
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -36[rbp]
	add	rax, rax
	add	rax, rdx
	or	esi, ecx
	mov	edx, esi
	mov	BYTE PTR 1[rax], dl
.L304:
	shr	WORD PTR -48[rbp], 8
	shr	WORD PTR -46[rbp], 8
	add	DWORD PTR -40[rbp], 1
	add	DWORD PTR -36[rbp], 1
.L301:
	mov	eax, DWORD PTR -36[rbp]
	cmp	eax, DWORD PTR -4[rbp]
	jbe	.L307
	jmp	.L308
.L300:
	mov	eax, DWORD PTR -76[rbp]
	add	eax, 1
	and	eax, 7
	mov	edx, eax
	mov	eax, 8
	sub	eax, edx
	mov	DWORD PTR -24[rbp], eax
	mov	eax, DWORD PTR -76[rbp]
	shr	eax, 3
	mov	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR -80[rbp]
	shr	eax, 3
	mov	DWORD PTR -16[rbp], eax
	mov	WORD PTR -44[rbp], 0
	mov	WORD PTR -42[rbp], 0
	mov	DWORD PTR -32[rbp], 0
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR -28[rbp], eax
	jmp	.L309
.L315:
	mov	edx, DWORD PTR -32[rbp]
	mov	rax, QWORD PTR -72[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	cmp	rdx, rax
	jnb	.L310
	mov	rax, QWORD PTR -72[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -32[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	eax, al
	mov	edi, eax
	call	word_reverse_bits
	movzx	eax, al
	or	WORD PTR -44[rbp], ax
	mov	rax, QWORD PTR -72[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -32[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	movzx	eax, al
	mov	edi, eax
	call	word_reverse_bits
	movzx	eax, al
	or	WORD PTR -42[rbp], ax
.L310:
	mov	eax, DWORD PTR -28[rbp]
	cmp	eax, DWORD PTR -20[rbp]
	je	.L311
	mov	eax, DWORD PTR -28[rbp]
	cmp	eax, DWORD PTR -16[rbp]
	je	.L311
	movzx	edx, WORD PTR -44[rbp]
	mov	eax, DWORD PTR -24[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	ecx, edx
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR [rax], dl
	movzx	edx, WORD PTR -42[rbp]
	mov	eax, DWORD PTR -24[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	ecx, edx
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR 1[rax], dl
	jmp	.L312
.L311:
	mov	BYTE PTR -49[rbp], -1
	mov	eax, DWORD PTR -28[rbp]
	cmp	eax, DWORD PTR -16[rbp]
	jne	.L313
	mov	eax, DWORD PTR -80[rbp]
	and	eax, 7
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	neg	eax
	mov	edx, eax
	movzx	eax, BYTE PTR -49[rbp]
	and	eax, edx
	mov	BYTE PTR -49[rbp], al
.L313:
	mov	eax, DWORD PTR -28[rbp]
	cmp	eax, DWORD PTR -20[rbp]
	jne	.L314
	mov	eax, DWORD PTR -76[rbp]
	add	eax, 1
	and	eax, 7
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	sub	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR -49[rbp]
	and	eax, edx
	mov	BYTE PTR -49[rbp], al
.L314:
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR [rax]
	movzx	eax, BYTE PTR -49[rbp]
	not	eax
	mov	esi, edx
	and	esi, eax
	movzx	edx, WORD PTR -44[rbp]
	mov	eax, DWORD PTR -24[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	edx, eax
	movzx	eax, BYTE PTR -49[rbp]
	mov	ecx, edx
	and	ecx, eax
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	or	esi, ecx
	mov	edx, esi
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	movzx	edx, BYTE PTR 1[rax]
	movzx	eax, BYTE PTR -49[rbp]
	not	eax
	mov	esi, edx
	and	esi, eax
	movzx	edx, WORD PTR -42[rbp]
	mov	eax, DWORD PTR -24[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	edx, eax
	movzx	eax, BYTE PTR -49[rbp]
	mov	ecx, edx
	and	ecx, eax
	mov	rax, QWORD PTR -88[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	add	rax, rax
	add	rax, rdx
	or	esi, ecx
	mov	edx, esi
	mov	BYTE PTR 1[rax], dl
.L312:
	sal	WORD PTR -44[rbp], 8
	sal	WORD PTR -42[rbp], 8
	add	DWORD PTR -32[rbp], 1
	sub	DWORD PTR -28[rbp], 1
.L309:
	mov	eax, DWORD PTR -28[rbp]
	cmp	eax, DWORD PTR -16[rbp]
	jge	.L315
.L308:
	mov	rax, QWORD PTR -88[rbp]
	mov	rdi, rax
	call	vec4state_clear_padding_bits
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE41:
	.size	vec4state_bitselect_set, .-vec4state_bitselect_set
	.section	.rodata
	.align 8
.LC6:
	.string	"FATAL: vec4state_to_real(): impossible double float word order?!\n"
	.text
	.globl	vec4state_to_real
	.type	vec4state_to_real, @function
vec4state_to_real:
.LFB42:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	QWORD PTR -56[rbp], rdi
	mov	rax, QWORD PTR -56[rbp]
	mov	eax, DWORD PTR 16[rax]
	test	eax, eax
	je	.L317
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	lea	edx, -1[rax]
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_bit_test
	cmp	eax, 1
	jne	.L317
	mov	eax, 1
	jmp	.L318
.L317:
	mov	eax, 0
.L318:
	mov	DWORD PTR -28[rbp], eax
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	je	.L319
	pxor	xmm0, xmm0
	jmp	.L320
.L319:
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	sub	eax, 1
	mov	DWORD PTR -40[rbp], eax
	jmp	.L321
.L329:
	mov	eax, DWORD PTR -40[rbp]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	mov	DWORD PTR -24[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	cdq
	shr	edx, 29
	add	eax, edx
	and	eax, 7
	sub	eax, edx
	mov	DWORD PTR -20[rbp], eax
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	eax, DWORD PTR -24[rbp]
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	edx, al
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	and	eax, 1
	cmp	DWORD PTR -28[rbp], eax
	je	.L322
	movsd	xmm0, QWORD PTR .LC5[rip]
	movsd	QWORD PTR -16[rbp], xmm0
	mov	QWORD PTR -8[rbp], 0
	mov	eax, DWORD PTR -40[rbp]
	cdq
	shr	edx, 29
	add	eax, edx
	and	eax, 7
	sub	eax, edx
	mov	edx, eax
	mov	eax, 63
	sub	eax, edx
	mov	DWORD PTR -32[rbp], eax
	mov	DWORD PTR -36[rbp], 0
	jmp	.L323
.L325:
	mov	eax, DWORD PTR -36[rbp]
	cmp	DWORD PTR -24[rbp], eax
	jb	.L324
	cmp	DWORD PTR -32[rbp], 63
	ja	.L324
	mov	rsi, QWORD PTR -8[rbp]
	mov	rax, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	ecx, DWORD PTR -36[rbp]
	mov	eax, DWORD PTR -24[rbp]
	sub	eax, ecx
	mov	eax, eax
	add	rax, rax
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	eax, DWORD PTR -32[rbp]
	mov	ecx, eax
	sal	rdx, cl
	mov	rax, rdx
	or	rax, rsi
	mov	QWORD PTR -8[rbp], rax
	sub	DWORD PTR -32[rbp], 8
	add	DWORD PTR -36[rbp], 1
.L323:
	cmp	DWORD PTR -36[rbp], 7
	jle	.L325
.L324:
	cmp	DWORD PTR -28[rbp], 0
	je	.L326
	mov	rax, QWORD PTR -8[rbp]
	neg	rax
	mov	QWORD PTR -8[rbp], rax
.L326:
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rax
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 2048
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -8[rbp]
	shr	rax, 12
	mov	QWORD PTR -8[rbp], rax
	mov	rdx, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR -40[rbp]
	add	eax, 1023
	cdqe
	sal	rax, 52
	mov	rcx, rax
	movabs	rax, 9218868437227405312
	and	rax, rcx
	or	rax, rdx
	mov	QWORD PTR -8[rbp], rax
	mov	rdx, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	sal	rax, 63
	or	rax, rdx
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -16[rbp]
	movabs	rdx, 4607182418800017408
	cmp	rax, rdx
	je	.L327
	mov	rax, QWORD PTR -16[rbp]
	cmp	rax, 1072693248
	jne	.L328
	mov	rax, QWORD PTR -8[rbp]
	rol	rax, 32
	mov	QWORD PTR -8[rbp], rax
	jmp	.L327
.L328:
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 65
	mov	esi, 1
	lea	rdi, .LC6[rip]
	call	fwrite@PLT
	call	abort@PLT
.L327:
	movsd	xmm0, QWORD PTR -8[rbp]
	jmp	.L320
.L322:
	sub	DWORD PTR -40[rbp], 1
.L321:
	cmp	DWORD PTR -40[rbp], 0
	jns	.L329
	pxor	xmm0, xmm0
.L320:
	movq	rax, xmm0
	movq	xmm0, rax
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE42:
	.size	vec4state_to_real, .-vec4state_to_real
	.type	count_vpiBinOctHexStr_digits, @function
count_vpiBinOctHexStr_digits:
.LFB43:
	.cfi_startproc
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -8[rbp], 0
	jmp	.L331
.L335:
	mov	rax, QWORD PTR -24[rbp]
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	sub	eax, 48
	cmp	eax, 74
	ja	.L332
	mov	eax, eax
	lea	rdx, 0[0+rax*4]
	lea	rax, .L334[rip]
	mov	eax, DWORD PTR [rdx+rax]
	cdqe
	lea	rdx, .L334[rip]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L334:
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L333-.L334
	.long	.L332-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L333-.L334
	.long	.L332-.L334
	.long	.L333-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L333-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L332-.L334
	.long	.L333-.L334
	.long	.L332-.L334
	.long	.L333-.L334
	.text
.L333:
	add	QWORD PTR -8[rbp], 1
	nop
.L332:
	add	QWORD PTR -24[rbp], 1
.L331:
	mov	rax, QWORD PTR -24[rbp]
	movzx	eax, BYTE PTR [rax]
	test	al, al
	jne	.L335
	mov	rax, QWORD PTR -8[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE43:
	.size	count_vpiBinOctHexStr_digits, .-count_vpiBinOctHexStr_digits
	.section	.rodata
	.align 8
.LC7:
	.string	"ERROR: scan_size_and_base(): invalid size field (overflow or zero?)\n"
	.align 8
.LC8:
	.string	"ERROR: scan_size_and_base(): no base-'tick found!\n"
	.align 8
.LC9:
	.string	"ERROR: scan_size_and_base(): invalid base character 0x%02x!\n"
	.align 8
.LC10:
	.string	"ERROR: scan_size_and_base(): base character not matching format!\n"
	.text
	.type	scan_size_and_base, @function
scan_size_and_base:
.LFB44:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 80
	mov	QWORD PTR -40[rbp], rdi
	mov	QWORD PTR -48[rbp], rsi
	mov	QWORD PTR -56[rbp], rdx
	mov	QWORD PTR -64[rbp], rcx
	mov	QWORD PTR -72[rbp], r8
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rax, QWORD PTR -40[rbp]
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -40[rbp]
	movzx	eax, BYTE PTR [rax]
	cmp	al, 47
	jle	.L338
	mov	rax, QWORD PTR -40[rbp]
	movzx	eax, BYTE PTR [rax]
	cmp	al, 57
	jle	.L339
.L338:
	mov	rax, QWORD PTR -56[rbp]
	mov	QWORD PTR [rax], 0
	jmp	.L340
.L339:
	lea	rcx, -16[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	edx, 10
	mov	rsi, rcx
	mov	rdi, rax
	call	strtoul@PLT
	mov	rdx, QWORD PTR -56[rbp]
	mov	QWORD PTR [rdx], rax
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR [rax]
	test	rax, rax
	je	.L341
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR [rax]
	cmp	rax, -1
	jne	.L345
.L341:
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 3
	je	.L343
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, -1
	je	.L343
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 68
	mov	esi, 1
	lea	rdi, .LC7[rip]
	call	fwrite@PLT
	mov	eax, 0
	jmp	.L366
.L343:
	mov	rax, QWORD PTR -48[rbp]
	mov	DWORD PTR [rax], 3
	mov	rax, QWORD PTR -56[rbp]
	mov	QWORD PTR [rax], 0
	mov	rax, QWORD PTR -64[rbp]
	mov	DWORD PTR [rax], 4
	mov	rax, QWORD PTR -72[rbp]
	mov	DWORD PTR [rax], 1
	mov	rax, QWORD PTR -40[rbp]
	jmp	.L366
.L346:
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 1
	mov	QWORD PTR -16[rbp], rax
.L345:
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, BYTE PTR [rax]
	cmp	al, 32
	je	.L346
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, BYTE PTR [rax]
	cmp	al, 9
	je	.L346
.L340:
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, BYTE PTR [rax]
	cmp	al, 39
	je	.L347
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 3
	je	.L348
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, -1
	je	.L348
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 50
	mov	esi, 1
	lea	rdi, .LC8[rip]
	call	fwrite@PLT
	mov	eax, 0
	jmp	.L366
.L348:
	mov	rax, QWORD PTR -48[rbp]
	mov	DWORD PTR [rax], 3
	mov	rax, QWORD PTR -56[rbp]
	mov	QWORD PTR [rax], 0
	mov	rax, QWORD PTR -64[rbp]
	mov	DWORD PTR [rax], 4
	mov	rax, QWORD PTR -72[rbp]
	mov	DWORD PTR [rax], 1
	mov	rax, QWORD PTR -40[rbp]
	jmp	.L366
.L347:
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 1
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, BYTE PTR [rax]
	cmp	al, 115
	je	.L349
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, BYTE PTR [rax]
	cmp	al, 83
	jne	.L350
.L349:
	mov	rax, QWORD PTR -72[rbp]
	mov	DWORD PTR [rax], 1
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 1
	mov	QWORD PTR -16[rbp], rax
	jmp	.L351
.L350:
	mov	rax, QWORD PTR -72[rbp]
	mov	DWORD PTR [rax], 0
.L351:
	mov	rax, QWORD PTR -16[rbp]
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	mov	edi, eax
	call	tolower@PLT
	mov	BYTE PTR -17[rbp], al
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 1
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, -1
	jne	.L352
	cmp	BYTE PTR -17[rbp], 98
	jne	.L353
	mov	rax, QWORD PTR -48[rbp]
	mov	DWORD PTR [rax], 1
	jmp	.L352
.L353:
	cmp	BYTE PTR -17[rbp], 111
	jne	.L354
	mov	rax, QWORD PTR -48[rbp]
	mov	DWORD PTR [rax], 2
	jmp	.L352
.L354:
	cmp	BYTE PTR -17[rbp], 104
	jne	.L355
	mov	rax, QWORD PTR -48[rbp]
	mov	DWORD PTR [rax], 4
	jmp	.L352
.L355:
	cmp	BYTE PTR -17[rbp], 100
	jne	.L356
	mov	rax, QWORD PTR -48[rbp]
	mov	DWORD PTR [rax], 3
	jmp	.L352
.L356:
	movsx	edx, BYTE PTR -17[rbp]
	mov	rax, QWORD PTR stderr[rip]
	lea	rsi, .LC9[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	eax, 0
	jmp	.L366
.L352:
	cmp	BYTE PTR -17[rbp], 98
	jne	.L357
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 1
	jne	.L358
.L357:
	cmp	BYTE PTR -17[rbp], 111
	jne	.L359
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 2
	jne	.L358
.L359:
	cmp	BYTE PTR -17[rbp], 104
	jne	.L360
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 4
	jne	.L358
.L360:
	cmp	BYTE PTR -17[rbp], 100
	jne	.L361
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 3
	je	.L361
.L358:
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 65
	mov	esi, 1
	lea	rdi, .LC10[rip]
	call	fwrite@PLT
	mov	eax, 0
	jmp	.L366
.L361:
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 1
	je	.L362
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 2
	jne	.L363
	mov	eax, 3
	jmp	.L365
.L363:
	mov	eax, 4
	jmp	.L365
.L362:
	mov	eax, 1
.L365:
	mov	rdx, QWORD PTR -64[rbp]
	mov	DWORD PTR [rdx], eax
	mov	rax, QWORD PTR -16[rbp]
.L366:
	mov	rcx, QWORD PTR -8[rbp]
	sub	rcx, QWORD PTR fs:40
	je	.L367
	call	__stack_chk_fail@PLT
.L367:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE44:
	.size	scan_size_and_base, .-scan_size_and_base
	.section	.rodata
	.align 8
.LC11:
	.string	"ERROR: vec4state_from_vpiBinOctHexStr(): too many digits for defined size (%u > %ubits)!\n"
	.align 8
.LC12:
	.string	"ERROR: vec4state_from_vpiBinOctHexStr(): Invalid character 0x%02x!\n"
	.align 8
.LC13:
	.string	"FATAL: vec4state_resize failed!\n"
	.text
	.globl	vec4state_from_vpiBinOctHexStr
	.type	vec4state_from_vpiBinOctHexStr, @function
vec4state_from_vpiBinOctHexStr:
.LFB45:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 80
	mov	QWORD PTR -56[rbp], rdi
	mov	QWORD PTR -64[rbp], rsi
	mov	DWORD PTR -68[rbp], edx
	mov	DWORD PTR -72[rbp], ecx
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	count_vpiBinOctHexStr_digits
	mov	QWORD PTR -24[rbp], rax
	mov	eax, DWORD PTR -68[rbp]
	cdqe
	mov	rdx, QWORD PTR -24[rbp]
	imul	rax, rdx
	mov	QWORD PTR -16[rbp], rax
	cmp	QWORD PTR -64[rbp], 0
	je	.L369
	mov	rax, QWORD PTR -16[rbp]
	cmp	rax, QWORD PTR -64[rbp]
	jbe	.L369
	mov	rax, QWORD PTR -64[rbp]
	mov	ecx, eax
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR stderr[rip]
	lea	rsi, .LC11[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	eax, 0
	jmp	.L370
.L369:
	mov	edx, DWORD PTR -72[rbp]
	mov	rax, QWORD PTR -16[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -8[rbp], rax
	mov	DWORD PTR -40[rbp], 0
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	strlen@PLT
	sub	eax, 1
	mov	DWORD PTR -36[rbp], eax
	jmp	.L371
.L388:
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 95
	je	.L391
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 120
	je	.L374
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 88
	jne	.L375
.L374:
	mov	DWORD PTR -32[rbp], 0
	jmp	.L376
.L377:
	mov	eax, DWORD PTR -40[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -40[rbp], edx
	mov	ecx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, 3
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_bit_set
	add	DWORD PTR -32[rbp], 1
.L376:
	mov	eax, DWORD PTR -32[rbp]
	cmp	eax, DWORD PTR -68[rbp]
	jl	.L377
	jmp	.L373
.L375:
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 122
	je	.L378
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 90
	je	.L378
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 63
	jne	.L379
.L378:
	mov	DWORD PTR -32[rbp], 0
	jmp	.L380
.L381:
	mov	eax, DWORD PTR -40[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -40[rbp], edx
	mov	ecx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, 2
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_bit_set
	add	DWORD PTR -32[rbp], 1
.L380:
	mov	eax, DWORD PTR -32[rbp]
	cmp	eax, DWORD PTR -68[rbp]
	jl	.L381
	jmp	.L373
.L379:
	mov	DWORD PTR -28[rbp], 2147483647
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 47
	jle	.L382
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 57
	jg	.L382
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	sub	eax, 48
	mov	DWORD PTR -28[rbp], eax
	jmp	.L383
.L382:
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 96
	jle	.L384
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 102
	jg	.L384
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	sub	eax, 87
	mov	DWORD PTR -28[rbp], eax
	jmp	.L383
.L384:
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 64
	jle	.L383
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 70
	jg	.L383
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	sub	eax, 55
	mov	DWORD PTR -28[rbp], eax
.L383:
	mov	eax, DWORD PTR -68[rbp]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	cmp	DWORD PTR -28[rbp], eax
	jl	.L385
	mov	eax, DWORD PTR -36[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	eax, al
	movzx	edx, al
	mov	rax, QWORD PTR stderr[rip]
	lea	rsi, .LC12[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
.L385:
	mov	DWORD PTR -32[rbp], 0
	jmp	.L386
.L387:
	mov	eax, DWORD PTR -32[rbp]
	mov	edx, DWORD PTR -28[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	and	eax, 1
	mov	BYTE PTR -41[rbp], al
	movsx	edx, BYTE PTR -41[rbp]
	mov	eax, DWORD PTR -40[rbp]
	lea	ecx, 1[rax]
	mov	DWORD PTR -40[rbp], ecx
	mov	ecx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_bit_set
	add	DWORD PTR -32[rbp], 1
.L386:
	mov	eax, DWORD PTR -32[rbp]
	cmp	eax, DWORD PTR -68[rbp]
	jl	.L387
	jmp	.L373
.L391:
	nop
.L373:
	sub	DWORD PTR -36[rbp], 1
.L371:
	cmp	DWORD PTR -36[rbp], 0
	jns	.L388
	cmp	QWORD PTR -64[rbp], 0
	jne	.L389
	mov	rax, QWORD PTR -16[rbp]
	mov	QWORD PTR -64[rbp], rax
.L389:
	mov	rdx, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR -8[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_resize
	test	eax, eax
	jne	.L390
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 32
	mov	esi, 1
	lea	rdi, .LC13[rip]
	call	fwrite@PLT
	call	abort@PLT
.L390:
	mov	rax, QWORD PTR -8[rbp]
.L370:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE45:
	.size	vec4state_from_vpiBinOctHexStr, .-vec4state_from_vpiBinOctHexStr
	.section	.rodata
	.align 8
.LC14:
	.string	"ERROR: vec4state_from_vpiDecStr(): invalid character in decimal digit string: 0x%02x\n"
	.align 8
.LC15:
	.string	"ERROR: vec4state_from_vpiDecStr(): number '%s' too large to fit in %zd bits!\n"
	.align 8
.LC16:
	.ascii	"WARNING: vec4state_from_vpiDecStr(): integer > 32bit (actual"
	.ascii	"ly %d, use %ubits).\n   IEEE1364-2005 is ambiguous about the"
	.ascii	" wrap-around of unsized integers:\n   In sec. 3.9 an impleme"
	.ascii	"ntation-dependend minimum size of 32bit is sp"
	.string	"ecified,\n   but in sec. 4.1.3, the examples assume a fixed 32bit-wrap-around.\n   We follow sec. 3.9 and won't limit integers to 32bits, to avoid unexpected wraparound effects.\n   Please keep in mind that other Verilog Tools may expose different behaviour.\n"
	.text
	.globl	vec4state_from_vpiDecStr
	.type	vec4state_from_vpiDecStr, @function
vec4state_from_vpiDecStr:
.LFB46:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	push	rbx
	sub	rsp, 72
	.cfi_offset 3, -24
	mov	QWORD PTR -56[rbp], rdi
	mov	QWORD PTR -64[rbp], rsi
	mov	DWORD PTR -68[rbp], edx
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	strlen@PLT
	lea	rdx, 0[0+rax*4]
	mov	eax, DWORD PTR -68[rbp]
	mov	esi, eax
	mov	rdi, rdx
	call	vec4state_new
	mov	QWORD PTR -24[rbp], rax
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_set
	mov	DWORD PTR -32[rbp], 0
	jmp	.L393
.L403:
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 95
	je	.L413
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 47
	jle	.L396
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 57
	jg	.L396
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	sub	eax, 48
	mov	BYTE PTR -33[rbp], al
	mov	rdx, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, 10
	mov	rdi, rax
	call	vec4state_mul_unsigned_word
	movzx	eax, BYTE PTR -33[rbp]
	movzx	ecx, al
	mov	rdx, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_add_unsigned_word
	jmp	.L395
.L396:
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 120
	je	.L397
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 88
	jne	.L398
.L397:
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, 3
	mov	rdi, rax
	call	vec4state_set
	jmp	.L399
.L398:
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 122
	je	.L400
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 90
	je	.L400
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	cmp	al, 63
	jne	.L401
.L400:
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, 2
	mov	rdi, rax
	call	vec4state_set
	jmp	.L399
.L401:
	mov	eax, DWORD PTR -32[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -56[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	edx, al
	mov	rax, QWORD PTR stderr[rip]
	lea	rsi, .LC14[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	eax, 0
	jmp	.L402
.L413:
	nop
.L395:
	add	DWORD PTR -32[rbp], 1
.L393:
	mov	eax, DWORD PTR -32[rbp]
	movsx	rbx, eax
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	strlen@PLT
	cmp	rbx, rax
	jb	.L403
.L399:
	cmp	QWORD PTR -64[rbp], 0
	je	.L404
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	sub	eax, 1
	mov	DWORD PTR -32[rbp], eax
	jmp	.L405
.L407:
	mov	edx, DWORD PTR -32[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_bit_test
	test	eax, eax
	je	.L406
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, QWORD PTR -64[rbp]
	mov	rdx, QWORD PTR -56[rbp]
	lea	rsi, .LC15[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	eax, 0
	jmp	.L402
.L406:
	sub	DWORD PTR -32[rbp], 1
.L405:
	mov	eax, DWORD PTR -32[rbp]
	cdqe
	cmp	QWORD PTR -64[rbp], rax
	jbe	.L407
	mov	rdx, QWORD PTR -64[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_resize
	test	eax, eax
	jne	.L408
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 32
	mov	esi, 1
	lea	rdi, .LC13[rip]
	call	fwrite@PLT
	call	abort@PLT
.L404:
	mov	DWORD PTR -28[rbp], 32
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rax, 31
	jbe	.L409
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	sub	eax, 1
	mov	DWORD PTR -32[rbp], eax
	jmp	.L410
.L412:
	mov	edx, DWORD PTR -32[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_bit_test
	cmp	eax, 1
	jne	.L411
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	ecx, eax
	mov	rax, QWORD PTR stderr[rip]
	mov	edx, DWORD PTR -32[rbp]
	lea	rsi, .LC16[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	DWORD PTR -28[rbp], eax
	jmp	.L409
.L411:
	sub	DWORD PTR -32[rbp], 1
.L410:
	cmp	DWORD PTR -32[rbp], 31
	jg	.L412
.L409:
	mov	eax, DWORD PTR -28[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_resize
	test	eax, eax
	jne	.L408
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 32
	mov	esi, 1
	lea	rdi, .LC13[rip]
	call	fwrite@PLT
	call	abort@PLT
.L408:
	mov	rax, QWORD PTR -24[rbp]
.L402:
	mov	rbx, QWORD PTR -8[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE46:
	.size	vec4state_from_vpiDecStr, .-vec4state_from_vpiDecStr
	.section	.rodata
	.align 8
.LC17:
	.string	"ERROR: vec4state_from_string(): Failed parsing size and base!\n"
	.text
	.globl	vec4state_from_string
	.type	vec4state_from_string, @function
vec4state_from_string:
.LFB47:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 48
	mov	QWORD PTR -40[rbp], rdi
	mov	DWORD PTR -44[rbp], esi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	lea	rdi, -28[rbp]
	lea	rcx, -32[rbp]
	lea	rdx, -24[rbp]
	lea	rsi, -44[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	r8, rdi
	mov	rdi, rax
	call	scan_size_and_base
	mov	QWORD PTR -40[rbp], rax
	cmp	QWORD PTR -40[rbp], 0
	jne	.L415
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 62
	mov	esi, 1
	lea	rdi, .LC17[rip]
	call	fwrite@PLT
	mov	eax, 0
	jmp	.L419
.L415:
	mov	eax, DWORD PTR -44[rbp]
	cmp	eax, 3
	jne	.L417
	mov	edx, DWORD PTR -28[rbp]
	mov	rcx, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_from_vpiDecStr
	mov	QWORD PTR -16[rbp], rax
	jmp	.L418
.L417:
	mov	ecx, DWORD PTR -28[rbp]
	mov	edx, DWORD PTR -32[rbp]
	mov	rsi, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_from_vpiBinOctHexStr
	mov	QWORD PTR -16[rbp], rax
.L418:
	mov	rax, QWORD PTR -16[rbp]
.L419:
	mov	rdi, QWORD PTR -8[rbp]
	sub	rdi, QWORD PTR fs:40
	je	.L420
	call	__stack_chk_fail@PLT
.L420:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE47:
	.size	vec4state_from_string, .-vec4state_from_string
	.section	.rodata
.LC18:
	.string	"s"
.LC19:
	.string	""
.LC20:
	.string	"%d'%s%c"
	.align 8
.LC21:
	.string	"ERROR: vec4state_to_vpiBinOctHexStr(): overflow of size/base field!\n"
	.align 8
.LC22:
	.string	"FATAL: vec4state_to_vpiBinOctHexStr(): failed to allocate %lu bytes for output string!\n"
	.text
	.globl	vec4state_to_vpiBinOctHexStr
	.type	vec4state_to_vpiBinOctHexStr, @function
vec4state_to_vpiBinOctHexStr:
.LFB48:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 112
	mov	QWORD PTR -104[rbp], rdi
	mov	DWORD PTR -108[rbp], esi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	cmp	DWORD PTR -108[rbp], 4
	je	.L422
	cmp	DWORD PTR -108[rbp], 2
	jne	.L423
	mov	eax, 111
	jmp	.L425
.L423:
	mov	eax, 98
	jmp	.L425
.L422:
	mov	eax, 104
.L425:
	mov	BYTE PTR -81[rbp], al
	movsx	ecx, BYTE PTR -81[rbp]
	mov	rax, QWORD PTR -104[rbp]
	mov	eax, DWORD PTR 16[rax]
	test	eax, eax
	je	.L426
	lea	rax, .LC18[rip]
	jmp	.L427
.L426:
	lea	rax, .LC19[rip]
.L427:
	mov	rdx, QWORD PTR -104[rbp]
	mov	rdx, QWORD PTR 8[rdx]
	lea	rdi, -22[rbp]
	mov	r9d, ecx
	mov	r8, rax
	mov	ecx, edx
	lea	rdx, .LC20[rip]
	mov	esi, 14
	mov	eax, 0
	call	snprintf@PLT
	cdqe
	mov	QWORD PTR -48[rbp], rax
	cmp	DWORD PTR -108[rbp], 4
	je	.L428
	cmp	DWORD PTR -108[rbp], 2
	jne	.L429
	mov	eax, 3
	jmp	.L431
.L429:
	mov	eax, 1
	jmp	.L431
.L428:
	mov	eax, 4
.L431:
	mov	DWORD PTR -56[rbp], eax
	mov	rax, QWORD PTR -104[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	eax, DWORD PTR -56[rbp]
	cdqe
	add	rax, rdx
	sub	rax, 1
	mov	edx, DWORD PTR -56[rbp]
	movsx	rsi, edx
	mov	edx, 0
	div	rsi
	mov	QWORD PTR -40[rbp], rax
	mov	DWORD PTR -80[rbp], 0
	cmp	QWORD PTR -48[rbp], 12
	jbe	.L432
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 68
	mov	esi, 1
	lea	rdi, .LC21[rip]
	call	fwrite@PLT
	mov	eax, 0
	jmp	.L450
.L432:
	mov	rdx, QWORD PTR -48[rbp]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	add	rax, 1
	mov	rdi, rax
	call	malloc@PLT
	mov	QWORD PTR -32[rbp], rax
	cmp	QWORD PTR -32[rbp], 0
	jne	.L434
	mov	rdx, QWORD PTR -48[rbp]
	mov	rax, QWORD PTR -40[rbp]
	add	rax, rdx
	lea	rdx, 1[rax]
	mov	rax, QWORD PTR stderr[rip]
	lea	rsi, .LC22[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	call	abort@PLT
.L434:
	mov	rdx, QWORD PTR -48[rbp]
	lea	rcx, -22[rbp]
	mov	rax, QWORD PTR -32[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	strncpy@PLT
	mov	rdx, QWORD PTR -48[rbp]
	mov	rax, QWORD PTR -40[rbp]
	add	rdx, rax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	BYTE PTR [rax], 0
	mov	rax, QWORD PTR -48[rbp]
	mov	edx, eax
	mov	rax, QWORD PTR -40[rbp]
	add	eax, edx
	sub	eax, 1
	mov	DWORD PTR -76[rbp], eax
	jmp	.L435
.L449:
	mov	DWORD PTR -68[rbp], 0
	mov	DWORD PTR -64[rbp], 0
	mov	DWORD PTR -60[rbp], 0
	mov	DWORD PTR -72[rbp], 0
	jmp	.L436
.L442:
	mov	edx, DWORD PTR -80[rbp]
	mov	rax, QWORD PTR -104[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_bit_test
	mov	DWORD PTR -52[rbp], eax
	cmp	DWORD PTR -52[rbp], 1
	jne	.L437
	mov	eax, DWORD PTR -72[rbp]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	DWORD PTR -60[rbp], eax
	jmp	.L438
.L437:
	cmp	DWORD PTR -52[rbp], 3
	jne	.L439
	add	DWORD PTR -68[rbp], 1
	jmp	.L438
.L439:
	cmp	DWORD PTR -52[rbp], 2
	jne	.L438
	add	DWORD PTR -64[rbp], 1
.L438:
	add	DWORD PTR -80[rbp], 1
	mov	eax, DWORD PTR -80[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -104[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	jnb	.L452
	add	DWORD PTR -72[rbp], 1
.L436:
	mov	eax, DWORD PTR -72[rbp]
	cmp	eax, DWORD PTR -56[rbp]
	jl	.L442
	jmp	.L441
.L452:
	nop
.L441:
	mov	eax, DWORD PTR -68[rbp]
	cmp	eax, DWORD PTR -56[rbp]
	jne	.L443
	mov	eax, DWORD PTR -76[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	BYTE PTR [rax], 120
	jmp	.L444
.L443:
	cmp	DWORD PTR -68[rbp], 0
	je	.L445
	mov	eax, DWORD PTR -76[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	BYTE PTR [rax], 88
	jmp	.L444
.L445:
	mov	eax, DWORD PTR -64[rbp]
	cmp	eax, DWORD PTR -56[rbp]
	jne	.L446
	mov	eax, DWORD PTR -76[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	BYTE PTR [rax], 122
	jmp	.L444
.L446:
	cmp	DWORD PTR -64[rbp], 0
	je	.L447
	mov	eax, DWORD PTR -76[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	BYTE PTR [rax], 90
	jmp	.L444
.L447:
	cmp	DWORD PTR -60[rbp], 9
	jg	.L448
	mov	eax, DWORD PTR -60[rbp]
	lea	ecx, 48[rax]
	mov	eax, DWORD PTR -76[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR [rax], dl
	jmp	.L444
.L448:
	mov	eax, DWORD PTR -60[rbp]
	lea	ecx, 87[rax]
	mov	eax, DWORD PTR -76[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR [rax], dl
.L444:
	sub	DWORD PTR -76[rbp], 1
.L435:
	mov	eax, DWORD PTR -76[rbp]
	cdqe
	cmp	QWORD PTR -48[rbp], rax
	jbe	.L449
	mov	rax, QWORD PTR -32[rbp]
.L450:
	mov	rsi, QWORD PTR -8[rbp]
	sub	rsi, QWORD PTR fs:40
	je	.L451
	call	__stack_chk_fail@PLT
.L451:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE48:
	.size	vec4state_to_vpiBinOctHexStr, .-vec4state_to_vpiBinOctHexStr
	.section	.rodata
.LC23:
	.string	"%d'%sd"
	.text
	.globl	vec4state_to_vpiDecStr
	.type	vec4state_to_vpiDecStr, @function
vec4state_to_vpiDecStr:
.LFB49:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	QWORD PTR -56[rbp], rdi
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -24[rbp], rax
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	shr	rax
	add	rax, 15
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	malloc@PLT
	mov	QWORD PTR -8[rbp], rax
	mov	DWORD PTR -44[rbp], 0
	mov	rax, QWORD PTR -56[rbp]
	mov	eax, DWORD PTR 16[rax]
	test	eax, eax
	je	.L454
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	lea	edx, -1[rax]
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_bit_test
	cmp	eax, 1
	jne	.L454
	mov	rdx, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR -56[rbp]
	mov	rsi, rax
	lea	rdi, vec4state_const_zero[rip]
	call	vec4state_sub
	mov	eax, DWORD PTR -44[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -44[rbp], edx
	movsx	rdx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rdx
	mov	BYTE PTR [rax], 45
	jmp	.L455
.L454:
	mov	rdx, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR -56[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_copy
.L455:
	mov	rax, QWORD PTR -56[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rax, 32
	jne	.L456
	mov	rax, QWORD PTR -56[rbp]
	mov	eax, DWORD PTR 16[rax]
	test	eax, eax
	jne	.L457
.L456:
	mov	rax, QWORD PTR -56[rbp]
	mov	eax, DWORD PTR 16[rax]
	test	eax, eax
	je	.L458
	lea	rax, .LC18[rip]
	jmp	.L459
.L458:
	lea	rax, .LC19[rip]
.L459:
	mov	rdx, QWORD PTR -56[rbp]
	mov	rdx, QWORD PTR 8[rdx]
	mov	ecx, edx
	mov	edx, DWORD PTR -44[rbp]
	movsx	rdi, edx
	mov	rdx, QWORD PTR -16[rbp]
	mov	rsi, rdx
	sub	rsi, rdi
	mov	edx, DWORD PTR -44[rbp]
	movsx	rdi, edx
	mov	rdx, QWORD PTR -8[rbp]
	add	rdi, rdx
	mov	r8, rax
	lea	rdx, .LC23[rip]
	mov	eax, 0
	call	snprintf@PLT
	add	DWORD PTR -44[rbp], eax
.L457:
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	vec4state_any_bit_is_X_or_Z
	test	eax, eax
	je	.L460
	mov	eax, DWORD PTR -44[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -44[rbp], edx
	movsx	rdx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rdx
	mov	BYTE PTR [rax], 120
	jmp	.L461
.L460:
	mov	eax, DWORD PTR -44[rbp]
	mov	DWORD PTR -36[rbp], eax
.L463:
	mov	rdx, QWORD PTR -24[rbp]
	mov	rax, QWORD PTR -24[rbp]
	mov	esi, 10
	mov	rdi, rax
	call	vec4state_div_unsigned_word
	movzx	eax, al
	mov	DWORD PTR -32[rbp], eax
	mov	eax, DWORD PTR -32[rbp]
	lea	ecx, 48[rax]
	mov	eax, DWORD PTR -44[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -44[rbp], edx
	movsx	rdx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rdx
	mov	edx, ecx
	mov	BYTE PTR [rax], dl
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, vec4state_const_zero[rip]
	mov	rdi, rax
	call	vec4state_cmp
	mov	DWORD PTR -28[rbp], eax
	cmp	DWORD PTR -28[rbp], 0
	je	.L462
	cmp	DWORD PTR -28[rbp], 3
	je	.L462
	cmp	DWORD PTR -28[rbp], 2
	je	.L462
	jmp	.L463
.L462:
	mov	DWORD PTR -40[rbp], 0
	jmp	.L464
.L465:
	mov	edx, DWORD PTR -36[rbp]
	mov	eax, DWORD PTR -40[rbp]
	add	eax, edx
	movsx	rdx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	mov	BYTE PTR -45[rbp], al
	mov	eax, DWORD PTR -44[rbp]
	sub	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, -1[rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rdx
	mov	ecx, DWORD PTR -36[rbp]
	mov	edx, DWORD PTR -40[rbp]
	add	edx, ecx
	movsx	rcx, edx
	mov	rdx, QWORD PTR -8[rbp]
	add	rdx, rcx
	movzx	eax, BYTE PTR [rax]
	mov	BYTE PTR [rdx], al
	mov	eax, DWORD PTR -44[rbp]
	sub	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, -1[rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rdx, rax
	movzx	eax, BYTE PTR -45[rbp]
	mov	BYTE PTR [rdx], al
	add	DWORD PTR -40[rbp], 1
.L464:
	mov	eax, DWORD PTR -44[rbp]
	sub	eax, DWORD PTR -36[rbp]
	mov	edx, eax
	shr	edx, 31
	add	eax, edx
	sar	eax
	cmp	DWORD PTR -40[rbp], eax
	jl	.L465
.L461:
	mov	eax, DWORD PTR -44[rbp]
	movsx	rdx, eax
	mov	rax, QWORD PTR -8[rbp]
	add	rax, rdx
	mov	BYTE PTR [rax], 0
	mov	eax, DWORD PTR -44[rbp]
	add	eax, 1
	movsx	rdx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	realloc@PLT
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -8[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE49:
	.size	vec4state_to_vpiDecStr, .-vec4state_to_vpiDecStr
	.section	.rodata
	.align 8
.LC24:
	.string	"FATAL: padding error (a) (vec4state %s, bits 0x%08x, mask 0x%08x)!\n"
	.align 8
.LC25:
	.string	"FATAL: padding error (b) (vec4state %s, bits 0x%08x, mask 0x%08x)!\n"
	.text
	.type	__check_padding, @function
__check_padding:
.LFB50:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	add	rax, rax
	sub	rax, 2
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	neg	eax
	and	eax, 7
	mov	esi, 255
	mov	ecx, eax
	sar	esi, cl
	mov	eax, esi
	not	eax
	and	eax, edx
	test	eax, eax
	je	.L468
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	neg	eax
	and	eax, 7
	mov	edx, 255
	mov	esi, edx
	mov	ecx, eax
	sar	esi, cl
	mov	rax, QWORD PTR -16[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	add	rax, rax
	sub	rax, 2
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	ecx, al
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -8[rbp]
	mov	r8d, esi
	lea	rsi, .LC24[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	call	abort@PLT
.L468:
	mov	rax, QWORD PTR -16[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	add	rax, rax
	sub	rax, 2
	add	rax, rdx
	movzx	eax, BYTE PTR 1[rax]
	movzx	edx, al
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	neg	eax
	and	eax, 7
	mov	esi, 255
	mov	ecx, eax
	sar	esi, cl
	mov	eax, esi
	not	eax
	and	eax, edx
	test	eax, eax
	je	.L470
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	neg	eax
	and	eax, 7
	mov	edx, 255
	mov	esi, edx
	mov	ecx, eax
	sar	esi, cl
	mov	rax, QWORD PTR -16[rbp]
	mov	rdx, QWORD PTR 24[rax]
	mov	rax, QWORD PTR -16[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, 7
	shr	rax, 3
	add	rax, rax
	sub	rax, 2
	add	rax, rdx
	movzx	eax, BYTE PTR [rax]
	movsx	ecx, al
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -8[rbp]
	mov	r8d, esi
	lea	rsi, .LC25[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	call	abort@PLT
.L470:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE50:
	.size	__check_padding, .-__check_padding
	.section	.rodata
.LC26:
	.string	"3"
.LC27:
	.string	"a"
.LC28:
	.string	"b"
.LC29:
	.string	"three"
.LC30:
	.string	"a = %s\n"
.LC31:
	.string	"b = %s\n"
.LC32:
	.string	"a = %g\n"
.LC33:
	.string	"b = %g\n"
	.align 8
.LC34:
	.string	"vec4state_shift_left(b, 5, c):\n"
.LC35:
	.string	"c = %s\n"
.LC36:
	.string	"c"
	.align 8
.LC37:
	.string	"vec4state_shift_right(b, 5, c, 0):\n"
	.align 8
.LC38:
	.string	"vec4state_shift_right(b, 5, c, 1):\n"
	.align 8
.LC39:
	.string	"vec4state_bitwise_binary_and(a, b, c):\n"
	.align 8
.LC40:
	.string	"vec4state_bitwise_binary_or(a, b, c):\n"
	.align 8
.LC41:
	.string	"vec4state_bitwise_binary_xor(a, b, c):\n"
	.align 8
.LC42:
	.string	"vec4state_bitwise_unary_negation(b, c):\n"
.LC43:
	.string	"vec4state_add(a, b, c):\n"
.LC44:
	.string	"vec4state_sub(a, b, c):\n"
	.align 8
.LC45:
	.string	"vec4state_mul_unsigned_word(a, 10, c):\n"
.LC46:
	.string	"vec4state_mul(a, b, c):\n"
	.align 8
.LC47:
	.string	"vec4state_div_unsigned_word(b, 2, c):\n"
	.align 8
.LC48:
	.string	"vec4state_reduction_unary_and(b, c):\n"
	.align 8
.LC49:
	.string	"vec4state_reduction_unary_or(b, c):\n"
	.align 8
.LC50:
	.string	"vec4state_reduction_unary_xor(b, c):\n"
	.align 8
.LC51:
	.string	"vec4state_bitselect_get(b, 0, c, 0):\n"
	.align 8
.LC52:
	.string	"vec4state_bitselect_get(b, 0, c, 1):\n"
	.align 8
.LC53:
	.string	"vec4state_bitselect_get(b, 1, c, 0):\n"
	.align 8
.LC54:
	.string	"vec4state_bitselect_get(b, 1, c, 1):\n"
	.align 8
.LC55:
	.string	"vec4state_bitselect_set(b, min(1, b->size), max(0, (int) b->size - 7), c):\n"
	.align 8
.LC56:
	.string	"vec4state_bitselect_set(b, min(3, b->size), max(0, (int) b->size - 7), c):\n"
	.align 8
.LC57:
	.string	"vec4state_bitselect_set(b, max(0, (int) b->size - 7), min(1, b->size), c):\n"
	.align 8
.LC58:
	.string	"vec4state_bitselect_set(b, max(0, (int) b->size - 7), min(3, b->size), c):\n"
.LC59:
	.string	"vec4state_pow(a, three, c):\n"
	.align 8
.LC60:
	.string	"vec4state_div_unsigned(a, b, c, d):\n"
.LC61:
	.string	"d = %s\n"
.LC62:
	.string	"d"
	.text
	.globl	main
	.type	main, @function
main:
.LFB51:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 736
	mov	DWORD PTR -724[rbp], edi
	mov	QWORD PTR -736[rbp], rsi
	mov	rax, QWORD PTR -736[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	mov	esi, -1
	mov	rdi, rax
	call	vec4state_from_string
	mov	QWORD PTR -712[rbp], rax
	mov	rax, QWORD PTR -736[rbp]
	add	rax, 16
	mov	rax, QWORD PTR [rax]
	mov	esi, -1
	mov	rdi, rax
	call	vec4state_from_string
	mov	QWORD PTR -704[rbp], rax
	mov	esi, -1
	lea	rdi, .LC26[rip]
	call	vec4state_from_string
	mov	QWORD PTR -696[rbp], rax
	cmp	QWORD PTR -712[rbp], 0
	je	.L472
	cmp	QWORD PTR -704[rbp], 0
	je	.L472
	cmp	QWORD PTR -696[rbp], 0
	je	.L472
	mov	rax, QWORD PTR -712[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -688[rbp], rax
	mov	rax, QWORD PTR -712[rbp]
	mov	esi, 2
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -680[rbp], rax
	mov	rax, QWORD PTR -712[rbp]
	mov	esi, 4
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -672[rbp], rax
	mov	rax, QWORD PTR -712[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -664[rbp], rax
	mov	rax, QWORD PTR -704[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -656[rbp], rax
	mov	rax, QWORD PTR -704[rbp]
	mov	esi, 2
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -648[rbp], rax
	mov	rax, QWORD PTR -704[rbp]
	mov	esi, 4
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -640[rbp], rax
	mov	rax, QWORD PTR -704[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -632[rbp], rax
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -696[rbp]
	mov	rsi, rax
	lea	rdi, .LC29[rip]
	call	__check_padding
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -672[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -640[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -680[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -648[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -664[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -632[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rdi, rax
	call	vec4state_to_real
	movq	rax, xmm0
	mov	rdx, QWORD PTR stderr[rip]
	movq	xmm0, rax
	lea	rsi, .LC32[rip]
	mov	rdi, rdx
	mov	eax, 1
	call	fprintf@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	rdi, rax
	call	vec4state_to_real
	movq	rax, xmm0
	mov	rdx, QWORD PTR stderr[rip]
	movq	xmm0, rax
	lea	rsi, .LC33[rip]
	mov	rdi, rdx
	mov	eax, 1
	call	fprintf@PLT
	mov	rax, QWORD PTR -680[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -672[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -664[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -648[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -640[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -632[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -624[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 31
	mov	esi, 1
	lea	rdi, .LC34[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -624[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	esi, 5
	mov	rdi, rax
	call	vec4state_shift_left
	mov	rax, QWORD PTR -624[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -616[rbp], rax
	mov	rax, QWORD PTR -624[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -608[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -616[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -608[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -624[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -624[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -616[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -608[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -600[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 35
	mov	esi, 1
	lea	rdi, .LC37[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -600[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	ecx, 0
	mov	esi, 5
	mov	rdi, rax
	call	vec4state_shift_right
	mov	rax, QWORD PTR -600[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -592[rbp], rax
	mov	rax, QWORD PTR -600[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -584[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -592[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -584[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -600[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -600[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -592[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -584[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -576[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 35
	mov	esi, 1
	lea	rdi, .LC38[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -576[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	ecx, 1
	mov	esi, 5
	mov	rdi, rax
	call	vec4state_shift_right
	mov	rax, QWORD PTR -576[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -568[rbp], rax
	mov	rax, QWORD PTR -576[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -560[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -568[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -560[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -576[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -576[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -568[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -560[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -712[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	cmovnb	rax, rdx
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -552[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 39
	mov	esi, 1
	lea	rdi, .LC39[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -552[rbp]
	mov	rcx, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_bitwise_binary_and
	mov	rax, QWORD PTR -552[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -544[rbp], rax
	mov	rax, QWORD PTR -552[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -536[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -544[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -536[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -552[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -552[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -544[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -536[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -712[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	cmovnb	rax, rdx
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -528[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 38
	mov	esi, 1
	lea	rdi, .LC40[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -528[rbp]
	mov	rcx, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_bitwise_binary_or
	mov	rax, QWORD PTR -528[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -520[rbp], rax
	mov	rax, QWORD PTR -528[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -512[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -520[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -512[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -528[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -528[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -520[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -512[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -712[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	cmovnb	rax, rdx
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -504[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 39
	mov	esi, 1
	lea	rdi, .LC41[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -504[rbp]
	mov	rcx, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_bitwise_binary_xor
	mov	rax, QWORD PTR -504[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -496[rbp], rax
	mov	rax, QWORD PTR -504[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -488[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -496[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -488[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -504[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -504[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -496[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -488[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -480[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 40
	mov	esi, 1
	lea	rdi, .LC42[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -480[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_bitwise_unary_negation
	mov	rax, QWORD PTR -480[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -472[rbp], rax
	mov	rax, QWORD PTR -480[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -464[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -472[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -464[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -480[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -480[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -472[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -464[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -712[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	cmovnb	rax, rdx
	add	rax, 1
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -456[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 24
	mov	esi, 1
	lea	rdi, .LC43[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -456[rbp]
	mov	rcx, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_add
	mov	rax, QWORD PTR -456[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -448[rbp], rax
	mov	rax, QWORD PTR -456[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -440[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -448[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -440[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -456[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -456[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -448[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -440[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rdx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -712[rbp]
	mov	rax, QWORD PTR 8[rax]
	cmp	rdx, rax
	cmovnb	rax, rdx
	add	rax, 1
	mov	esi, ecx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -432[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 24
	mov	esi, 1
	lea	rdi, .LC44[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -432[rbp]
	mov	rcx, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_sub
	mov	rax, QWORD PTR -432[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -424[rbp], rax
	mov	rax, QWORD PTR -432[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -416[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -424[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -416[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -432[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -432[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -424[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -416[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	rdx, QWORD PTR -712[rbp]
	mov	rdx, QWORD PTR 8[rdx]
	add	rdx, 8
	mov	esi, eax
	mov	rdi, rdx
	call	vec4state_new
	mov	QWORD PTR -408[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 39
	mov	esi, 1
	lea	rdi, .LC45[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -408[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	esi, 10
	mov	rdi, rax
	call	vec4state_mul_unsigned_word
	mov	rax, QWORD PTR -408[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -400[rbp], rax
	mov	rax, QWORD PTR -408[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -392[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -400[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -392[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -408[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -408[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -400[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -392[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	or	edx, eax
	mov	rax, QWORD PTR -712[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	add	rax, rcx
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -384[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 24
	mov	esi, 1
	lea	rdi, .LC46[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -384[rbp]
	mov	rcx, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_mul
	mov	rax, QWORD PTR -384[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -376[rbp], rax
	mov	rax, QWORD PTR -384[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -368[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -376[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -368[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -384[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -384[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -376[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -368[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -360[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 38
	mov	esi, 1
	lea	rdi, .LC47[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -360[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	esi, 2
	mov	rdi, rax
	call	vec4state_div_unsigned_word
	mov	rax, QWORD PTR -360[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -352[rbp], rax
	mov	rax, QWORD PTR -360[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -344[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -352[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -344[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -360[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -360[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -352[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -344[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	esi, 0
	mov	edi, 1
	call	vec4state_new
	mov	QWORD PTR -336[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 37
	mov	esi, 1
	lea	rdi, .LC48[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -336[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_reduction_unary_and
	mov	rax, QWORD PTR -336[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -328[rbp], rax
	mov	rax, QWORD PTR -336[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -320[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -328[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -320[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -336[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -336[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -328[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -320[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	esi, 0
	mov	edi, 1
	call	vec4state_new
	mov	QWORD PTR -312[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 36
	mov	esi, 1
	lea	rdi, .LC49[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -312[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_reduction_unary_or
	mov	rax, QWORD PTR -312[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -304[rbp], rax
	mov	rax, QWORD PTR -312[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -296[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -304[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -296[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -312[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -312[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -304[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -296[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	esi, 0
	mov	edi, 1
	call	vec4state_new
	mov	QWORD PTR -288[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 37
	mov	esi, 1
	lea	rdi, .LC50[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -288[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	vec4state_reduction_unary_xor
	mov	rax, QWORD PTR -288[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -280[rbp], rax
	mov	rax, QWORD PTR -288[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -272[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -280[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -272[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -288[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -288[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -280[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -272[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	esi, eax
	mov	edi, 8
	call	vec4state_new
	mov	QWORD PTR -264[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 37
	mov	esi, 1
	lea	rdi, .LC51[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -264[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	ecx, 0
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_bitselect_get
	mov	rax, QWORD PTR -264[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -256[rbp], rax
	mov	rax, QWORD PTR -264[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -248[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -256[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -248[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -264[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -264[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -256[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -248[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	esi, eax
	mov	edi, 8
	call	vec4state_new
	mov	QWORD PTR -240[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 37
	mov	esi, 1
	lea	rdi, .LC52[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -240[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	ecx, 1
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_bitselect_get
	mov	rax, QWORD PTR -240[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -232[rbp], rax
	mov	rax, QWORD PTR -240[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -224[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -232[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -224[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -240[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -240[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -232[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -224[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	esi, eax
	mov	edi, 35
	call	vec4state_new
	mov	QWORD PTR -216[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 37
	mov	esi, 1
	lea	rdi, .LC53[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -216[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	ecx, 0
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_bitselect_get
	mov	rax, QWORD PTR -216[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -208[rbp], rax
	mov	rax, QWORD PTR -216[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -200[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -208[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -200[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -216[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -216[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -208[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -200[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	eax, DWORD PTR 16[rax]
	mov	esi, eax
	mov	edi, 35
	call	vec4state_new
	mov	QWORD PTR -192[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 37
	mov	esi, 1
	lea	rdi, .LC54[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -192[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	ecx, 1
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_bitselect_get
	mov	rax, QWORD PTR -192[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -184[rbp], rax
	mov	rax, QWORD PTR -192[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -176[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -184[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -176[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -192[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -192[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -184[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -176[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -168[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 75
	mov	esi, 1
	lea	rdi, .LC55[rip]
	call	fwrite@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, 7
	cmp	eax, 7
	cmovl	eax, edx
	sub	eax, 7
	mov	edi, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, 1
	test	rax, rax
	cmovne	rax, rdx
	mov	esi, eax
	mov	rdx, QWORD PTR -168[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	rcx, rdx
	mov	edx, edi
	mov	rdi, rax
	call	vec4state_bitselect_set
	mov	rax, QWORD PTR -168[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -160[rbp], rax
	mov	rax, QWORD PTR -168[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -152[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -160[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -152[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -168[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -168[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -160[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -152[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -144[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 75
	mov	esi, 1
	lea	rdi, .LC56[rip]
	call	fwrite@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, 7
	cmp	eax, 7
	cmovl	eax, edx
	sub	eax, 7
	mov	edi, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, 3
	cmp	rax, 3
	cmova	rax, rdx
	mov	esi, eax
	mov	rdx, QWORD PTR -144[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	rcx, rdx
	mov	edx, edi
	mov	rdi, rax
	call	vec4state_bitselect_set
	mov	rax, QWORD PTR -144[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -136[rbp], rax
	mov	rax, QWORD PTR -144[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -128[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -136[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -128[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -144[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -144[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -136[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -128[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -120[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 75
	mov	esi, 1
	lea	rdi, .LC57[rip]
	call	fwrite@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, 1
	test	rax, rax
	cmovne	rax, rdx
	mov	edi, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, 7
	cmp	eax, 7
	cmovl	eax, edx
	sub	eax, 7
	mov	esi, eax
	mov	rdx, QWORD PTR -120[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	rcx, rdx
	mov	edx, edi
	mov	rdi, rax
	call	vec4state_bitselect_set
	mov	rax, QWORD PTR -120[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -112[rbp], rax
	mov	rax, QWORD PTR -120[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -104[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -112[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -104[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -120[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -120[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -112[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -104[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -96[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 75
	mov	esi, 1
	lea	rdi, .LC58[rip]
	call	fwrite@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, 3
	cmp	rax, 3
	cmova	rax, rdx
	mov	edi, eax
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	edx, 7
	cmp	eax, 7
	cmovl	eax, edx
	sub	eax, 7
	mov	esi, eax
	mov	rdx, QWORD PTR -96[rbp]
	mov	rax, QWORD PTR -704[rbp]
	mov	rcx, rdx
	mov	edx, edi
	mov	rdi, rax
	call	vec4state_bitselect_set
	mov	rax, QWORD PTR -96[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -88[rbp], rax
	mov	rax, QWORD PTR -96[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -80[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -88[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -80[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -96[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -96[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -88[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -80[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -712[rbp]
	mov	rcx, QWORD PTR 8[rax]
	mov	rax, rcx
	add	rax, rax
	add	rax, rcx
	mov	esi, edx
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -72[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 28
	mov	esi, 1
	lea	rdi, .LC59[rip]
	call	fwrite@PLT
	mov	rdx, QWORD PTR -72[rbp]
	mov	rcx, QWORD PTR -696[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rcx
	mov	rdi, rax
	call	vec4state_pow
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -64[rbp], rax
	mov	rax, QWORD PTR -72[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -56[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -64[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -56[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -72[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -72[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -64[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -48[rbp], rax
	mov	rax, QWORD PTR -712[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	esi, 0
	mov	rdi, rax
	call	vec4state_new
	mov	QWORD PTR -40[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rcx, rax
	mov	edx, 36
	mov	esi, 1
	lea	rdi, .LC60[rip]
	call	fwrite@PLT
	mov	rcx, QWORD PTR -48[rbp]
	mov	rdx, QWORD PTR -40[rbp]
	mov	rsi, QWORD PTR -704[rbp]
	mov	rax, QWORD PTR -712[rbp]
	mov	rdi, rax
	call	vec4state_div_unsigned
	mov	rax, QWORD PTR -40[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -32[rbp], rax
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -24[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -688[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -656[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -32[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -24[rbp]
	lea	rsi, .LC35[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -712[rbp]
	mov	rsi, rax
	lea	rdi, .LC27[rip]
	call	__check_padding
	mov	rax, QWORD PTR -704[rbp]
	mov	rsi, rax
	lea	rdi, .LC28[rip]
	call	__check_padding
	mov	rax, QWORD PTR -40[rbp]
	mov	rsi, rax
	lea	rdi, .LC36[rip]
	call	__check_padding
	mov	rax, QWORD PTR -40[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -32[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -48[rbp]
	mov	esi, 1
	mov	rdi, rax
	call	vec4state_to_vpiBinOctHexStr
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -48[rbp]
	mov	rdi, rax
	call	vec4state_to_vpiDecStr
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -16[rbp]
	lea	rsi, .LC61[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR stderr[rip]
	mov	rdx, QWORD PTR -8[rbp]
	lea	rsi, .LC61[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -48[rbp]
	mov	rsi, rax
	lea	rdi, .LC62[rip]
	call	__check_padding
	mov	rax, QWORD PTR -48[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -688[rbp]
	mov	rdi, rax
	call	free@PLT
	mov	rax, QWORD PTR -656[rbp]
	mov	rdi, rax
	call	free@PLT
.L472:
	mov	rax, QWORD PTR -712[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -704[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	rax, QWORD PTR -696[rbp]
	mov	rdi, rax
	call	vec4state_free
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE51:
	.size	main, .-main
	.section	.rodata
	.align 8
.LC5:
	.long	0
	.long	1072693248
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"61075763.c"
	.text
	.section	.rodata
	.align	2
	.type	const_vecval_zero, %object
	.size	const_vecval_zero, 2
const_vecval_zero:
	.space	2
	.align	2
	.type	const_vecval_one, %object
	.size	const_vecval_one, 2
const_vecval_one:
	.byte	1
	.byte	0
	.align	2
	.type	const_vecval_minus_one, %object
	.size	const_vecval_minus_one, 2
const_vecval_minus_one:
	.byte	-1
	.byte	0
	.align	2
	.type	vec4state_const_zero, %object
	.size	vec4state_const_zero, 16
vec4state_const_zero:
	.word	1
	.word	1
	.word	0
	.word	const_vecval_zero
	.align	2
	.type	vec4state_const_one, %object
	.size	vec4state_const_one, 16
vec4state_const_one:
	.word	32
	.word	1
	.word	0
	.word	const_vecval_one
	.align	2
	.type	vec4state_const_minus_one, %object
	.size	vec4state_const_minus_one, 16
vec4state_const_minus_one:
	.word	32
	.word	1
	.word	1
	.word	const_vecval_minus_one
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_clear_padding_bits, %function
vec4state_clear_padding_bits:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r2, r3, #-2147483647
	lsl	r2, r2, #1
	add	r2, r1, r2
	ldrsb	r1, [r2]
	ldr	r2, [fp, #-8]
	ldr	r2, [r2, #4]
	rsb	r2, r2, #0
	and	r2, r2, #7
	mov	r0, #255
	asr	r2, r0, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	ldr	r0, [fp, #-8]
	ldr	r0, [r0, #12]
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r0, r3
	and	r2, r2, r1
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-8]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r2, r3, #-2147483647
	lsl	r2, r2, #1
	add	r2, r1, r2
	ldrsb	r1, [r2, #1]
	ldr	r2, [fp, #-8]
	ldr	r2, [r2, #4]
	rsb	r2, r2, #0
	and	r2, r2, #7
	mov	r0, #255
	asr	r2, r0, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	ldr	r0, [fp, #-8]
	ldr	r0, [r0, #12]
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r0, r3
	and	r2, r2, r1
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_clear_padding_bits, .-vec4state_clear_padding_bits
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bit_test, %function
vec4state_bit_test:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	ldr	r3, [fp, #-28]
	lsr	r3, r3, #3
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-28]
	and	r3, r3, #7
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	mov	r2, r3
	ldr	r3, [fp, #-16]
	asr	r3, r2, r3
	and	r3, r3, #1
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	mov	r2, r3
	ldr	r3, [fp, #-16]
	asr	r3, r2, r3
	and	r3, r3, #1
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	lsl	r2, r3, #1
	ldr	r3, [fp, #-12]
	orr	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_bit_test, .-vec4state_bit_test
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bit_set, %function
vec4state_bit_set:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #36
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-32]
	ldr	r3, [fp, #-28]
	lsr	r3, r3, #3
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-28]
	and	r3, r3, #7
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #1
	strb	r3, [fp, #-17]
	ldr	r3, [fp, #-32]
	asr	r3, r3, #1
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #1
	strb	r3, [fp, #-16]
	ldrsb	r2, [fp, #-17]
	ldr	r3, [fp, #-8]
	lsl	r3, r2, r3
	strb	r3, [fp, #-15]
	ldrsb	r2, [fp, #-16]
	ldr	r3, [fp, #-8]
	lsl	r3, r2, r3
	strb	r3, [fp, #-14]
	mov	r2, #1
	ldr	r3, [fp, #-8]
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	mvn	r3, r3
	strb	r3, [fp, #-13]
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3]
	ldrb	r3, [fp, #-13]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrb	r2, [fp, #-15]
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3, #1]
	ldrb	r3, [fp, #-13]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrb	r2, [fp, #-14]
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_bit_set, .-vec4state_bit_set
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bitfield_set, %function
vec4state_bitfield_set:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #36
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-32]
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-28]
	lsr	r3, r3, #3
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-32]
	lsr	r3, r3, #3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	beq	.L6
	ldr	r3, [fp, #-36]
	cmp	r3, #2
	bne	.L7
.L6:
	mov	r3, #0
	b	.L8
.L7:
	mov	r3, #255
.L8:
	strb	r3, [fp, #-18]
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	beq	.L9
	ldr	r3, [fp, #-36]
	cmp	r3, #1
	bne	.L10
.L9:
	mov	r3, #0
	b	.L11
.L10:
	mov	r3, #255
.L11:
	strb	r3, [fp, #-17]
	ldr	r3, [fp, #-12]
	str	r3, [fp, #-16]
	b	.L12
.L17:
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	beq	.L13
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	beq	.L13
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [fp, #-18]
	strb	r2, [r3]
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [fp, #-17]
	strb	r2, [r3, #1]
	b	.L14
.L13:
	mvn	r3, #0
	strb	r3, [fp, #-19]
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bne	.L15
	ldr	r3, [fp, #-28]
	and	r3, r3, #7
	mvn	r2, #0
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-19]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	strb	r3, [fp, #-19]
.L15:
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3]
	ldrsb	r3, [fp, #-19]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrb	r2, [fp, #-18]
	ldrb	r3, [fp, #-19]
	and	r3, r3, r2
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-24]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3, #1]
	ldrsb	r3, [fp, #-19]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrb	r2, [fp, #-17]
	ldrb	r3, [fp, #-19]
	and	r3, r3, r2
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-24]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
.L14:
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
.L12:
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	bcs	.L17
	nop
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_bitfield_set, .-vec4state_bitfield_set
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_set, %function
vec4state_set:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-20]
	cmp	r3, #0
	beq	.L19
	ldr	r3, [fp, #-20]
	cmp	r3, #1
	bne	.L20
	mov	r3, #1
	b	.L22
.L20:
	mvn	r3, #0
	b	.L22
.L19:
	mov	r3, #0
.L22:
	strb	r3, [fp, #-11]
	ldr	r3, [fp, #-20]
	cmp	r3, #0
	beq	.L23
	ldr	r3, [fp, #-20]
	cmp	r3, #1
	bne	.L24
.L23:
	mov	r3, #0
	b	.L25
.L24:
	mvn	r3, #0
.L25:
	strb	r3, [fp, #-10]
	ldr	r3, [fp, #-20]
	cmp	r3, #3
	beq	.L26
	ldr	r3, [fp, #-20]
	cmp	r3, #2
	bne	.L27
.L26:
	mvn	r3, #0
	b	.L28
.L27:
	mov	r3, #0
.L28:
	strb	r3, [fp, #-9]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #12]
	ldrb	r2, [fp, #-11]
	strb	r2, [r3]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #12]
	ldrb	r2, [fp, #-9]
	strb	r2, [r3, #1]
	mov	r3, #1
	str	r3, [fp, #-8]
	b	.L29
.L30:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrb	r2, [fp, #-10]
	strb	r2, [r3]
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrb	r2, [fp, #-9]
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L29:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L30
	ldr	r0, [fp, #-16]
	bl	vec4state_clear_padding_bits
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_set, .-vec4state_set
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_any_bit_is_X_or_Z, %function
vec4state_any_bit_is_X_or_Z:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L32
.L35:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	cmp	r3, #0
	beq	.L33
	mov	r3, #1
	b	.L34
.L33:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L32:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L35
	mov	r3, #0
.L34:
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_any_bit_is_X_or_Z, .-vec4state_any_bit_is_X_or_Z
	.section	.rodata
	.align	2
.LC0:
	.ascii	"FATAL: memory allocation for vec4state failed!\000"
	.align	2
.LC1:
	.ascii	"FATAL: failed allocating %lu bytes for vec4state!\000"
	.text
	.align	2
	.global	vec4state_new
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_new, %function
vec4state_new:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r0, #16
	bl	malloc
	mov	r3, r0
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L40
	ldr	r3, [r3]
	mov	r2, #46
	mov	r1, #1
	ldr	r0, .L40+4
	bl	fwrite
	bl	abort
.L37:
	ldr	r3, [fp, #-8]
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	ldr	r2, [fp, #-16]
	str	r2, [r3, #4]
	ldr	r3, [fp, #-8]
	ldr	r2, [fp, #-20]
	str	r2, [r3, #8]
	ldr	r3, [fp, #-16]
	add	r3, r3, #7
	lsr	r3, r3, #3
	lsl	r3, r3, #1
	mov	r0, r3
	bl	malloc
	mov	r3, r0
	mov	r2, r3
	ldr	r3, [fp, #-8]
	str	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #12]
	cmp	r3, #0
	bne	.L38
	ldr	r0, [fp, #-8]
	bl	free
	ldr	r3, .L40
	ldr	r0, [r3]
	ldr	r3, [fp, #-16]
	add	r3, r3, #7
	lsr	r3, r3, #3
	lsl	r3, r3, #1
	mov	r2, r3
	ldr	r1, .L40+8
	bl	fprintf
	bl	abort
.L38:
	mov	r1, #3
	ldr	r0, [fp, #-8]
	bl	vec4state_set
	ldr	r3, [fp, #-8]
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L41:
	.align	2
.L40:
	.word	stderr
	.word	.LC0
	.word	.LC1
	.size	vec4state_new, .-vec4state_new
	.section	.rodata
	.align	2
.LC2:
	.ascii	"FATAL: failed re-allocating %lu bytes for vec4state"
	.ascii	"!\000"
	.text
	.align	2
	.global	vec4state_resize
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_resize, %function
vec4state_resize:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-12]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-28]
	add	r3, r3, #7
	lsr	r3, r3, #3
	cmp	r2, r3
	beq	.L43
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-28]
	add	r3, r3, #7
	lsr	r3, r3, #3
	lsl	r3, r3, #1
	mov	r1, r3
	mov	r0, r2
	bl	realloc
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L48
	ldr	r0, [r3]
	ldr	r3, [fp, #-28]
	add	r3, r3, #7
	lsr	r3, r3, #3
	lsl	r3, r3, #1
	mov	r2, r3
	ldr	r1, .L48+4
	bl	fprintf
	bl	abort
.L44:
	ldr	r3, [fp, #-24]
	ldr	r2, [fp, #-8]
	str	r2, [r3, #12]
.L43:
	ldr	r3, [fp, #-24]
	ldr	r2, [fp, #-28]
	str	r2, [r3, #4]
	ldr	r2, [fp, #-12]
	ldr	r3, [fp, #-28]
	cmp	r2, r3
	bcs	.L45
	ldr	r3, [fp, #-12]
	sub	r3, r3, #1
	mov	r1, r3
	ldr	r0, [fp, #-24]
	bl	vec4state_bit_test
	str	r0, [fp, #-16]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #8]
	cmp	r3, #0
	bne	.L46
	ldr	r3, [fp, #-16]
	cmp	r3, #1
	bne	.L46
	mov	r3, #0
	str	r3, [fp, #-16]
.L46:
	ldr	r3, [fp, #-28]
	sub	r2, r3, #1
	ldr	r3, [fp, #-16]
	ldr	r1, [fp, #-12]
	ldr	r0, [fp, #-24]
	bl	vec4state_bitfield_set
.L45:
	ldr	r0, [fp, #-24]
	bl	vec4state_clear_padding_bits
	mov	r3, #1
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L49:
	.align	2
.L48:
	.word	stderr
	.word	.LC2
	.size	vec4state_resize, .-vec4state_resize
	.align	2
	.global	vec4state_free
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_free, %function
vec4state_free:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	beq	.L52
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #12]
	mov	r0, r3
	bl	free
	ldr	r0, [fp, #-8]
	bl	free
.L52:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_free, .-vec4state_free
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_copy, %function
vec4state_copy:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L54
.L59:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L55
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r1, [r3]
	b	.L56
.L55:
	mov	r1, #0
.L56:
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L57
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r1, [r3, #1]
	b	.L58
.L57:
	mov	r1, #0
.L58:
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L54:
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L59
	ldr	r0, [fp, #-20]
	bl	vec4state_clear_padding_bits
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_copy, .-vec4state_copy
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_padded_signed_word_a, %function
vec4state_padded_signed_word_a:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r2, r3, #1
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	bls	.L61
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	b	.L62
.L61:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	sub	r3, r3, #1
	mov	r1, r3
	ldr	r0, [fp, #-16]
	bl	vec4state_bit_test
	mov	r3, r0
	cmp	r3, #0
	bne	.L63
	mov	r3, #0
	b	.L64
.L63:
	mvn	r3, #0
.L64:
	strb	r3, [fp, #-5]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r2, r3, #1
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	bne	.L65
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	rsb	r3, r3, #0
	and	r3, r3, #7
	mov	r2, #255
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r3, [fp, #-5]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-16]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #1
	add	r3, r1, r3
	ldrsb	r3, [r3]
	orr	r3, r2, r3
	strb	r3, [fp, #-5]
.L65:
	ldrsb	r3, [fp, #-5]
.L62:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_padded_signed_word_a, .-vec4state_padded_signed_word_a
	.align	2
	.global	vec4state_cmp
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_cmp, %function
vec4state_cmp:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r0, [fp, #-16]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	bne	.L67
	ldr	r0, [fp, #-20]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	beq	.L68
.L67:
	mov	r3, #3
	b	.L69
.L68:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	beq	.L70
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #8]
	cmp	r3, #0
	beq	.L71
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #8]
	cmp	r3, #0
	bne	.L70
.L71:
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	movcs	r3, r2
	movcc	r3, r3
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #1
	str	r3, [fp, #-8]
	b	.L72
.L79:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L73
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L74
.L73:
	mov	r3, #0
.L74:
	strb	r3, [fp, #-12]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L75
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L76
.L75:
	mov	r3, #0
.L76:
	strb	r3, [fp, #-11]
	ldrb	r2, [fp, #-12]	@ zero_extendqisi2
	ldrb	r3, [fp, #-11]	@ zero_extendqisi2
	cmp	r2, r3
	bcs	.L77
	mvn	r3, #0
	b	.L69
.L77:
	ldrb	r2, [fp, #-12]	@ zero_extendqisi2
	ldrb	r3, [fp, #-11]	@ zero_extendqisi2
	cmp	r2, r3
	bls	.L78
	mov	r3, #1
	b	.L69
.L78:
	ldr	r3, [fp, #-8]
	sub	r3, r3, #1
	str	r3, [fp, #-8]
.L72:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bge	.L79
	b	.L80
.L70:
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	movcs	r3, r2
	movcc	r3, r3
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #1
	str	r3, [fp, #-8]
	b	.L81
.L84:
	ldr	r1, [fp, #-8]
	ldr	r0, [fp, #-16]
	bl	vec4state_padded_signed_word_a
	mov	r3, r0
	strb	r3, [fp, #-10]
	ldr	r1, [fp, #-8]
	ldr	r0, [fp, #-20]
	bl	vec4state_padded_signed_word_a
	mov	r3, r0
	strb	r3, [fp, #-9]
	ldrsb	r2, [fp, #-10]
	ldrsb	r3, [fp, #-9]
	cmp	r2, r3
	bge	.L82
	mvn	r3, #0
	b	.L69
.L82:
	ldrsb	r2, [fp, #-10]
	ldrsb	r3, [fp, #-9]
	cmp	r2, r3
	ble	.L83
	mov	r3, #1
	b	.L69
.L83:
	ldr	r3, [fp, #-8]
	sub	r3, r3, #1
	str	r3, [fp, #-8]
.L81:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bge	.L84
.L80:
	mov	r3, #0
.L69:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_cmp, .-vec4state_cmp
	.align	2
	.global	vec4state_case_equality
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_case_equality, %function
vec4state_case_equality:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	beq	.L86
	mov	r3, #0
	b	.L87
.L86:
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L88
.L91:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3]
	ldr	r3, [fp, #-20]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r1, r3
	ldrsb	r3, [r3]
	cmp	r2, r3
	bne	.L89
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3, #1]
	ldr	r3, [fp, #-20]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r1, r3
	ldrsb	r3, [r3, #1]
	cmp	r2, r3
	beq	.L90
.L89:
	mov	r3, #0
	b	.L87
.L90:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L88:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L91
	mov	r3, #1
.L87:
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_case_equality, .-vec4state_case_equality
	.align	2
	.global	vec4state_bitwise_binary_and
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bitwise_binary_and, %function
vec4state_bitwise_binary_and:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L93
.L102:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L94
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L95
.L94:
	mov	r3, #0
.L95:
	strb	r3, [fp, #-12]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L96
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L97
.L96:
	mov	r3, #0
.L97:
	strb	r3, [fp, #-11]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L98
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L99
.L98:
	mov	r3, #0
.L99:
	strb	r3, [fp, #-10]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L100
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L101
.L100:
	mov	r3, #0
.L101:
	strb	r3, [fp, #-9]
	ldrb	r2, [fp, #-9]
	ldrb	r3, [fp, #-10]
	orr	r3, r2, r3
	and	r2, r3, #255
	ldrb	r3, [fp, #-11]
	and	r3, r3, r2
	and	r2, r3, #255
	ldrb	r1, [fp, #-12]
	ldrb	r3, [fp, #-9]
	and	r3, r3, r1
	and	r3, r3, #255
	orr	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-12]
	ldrb	r3, [fp, #-10]
	and	r3, r3, r1
	and	r3, r3, #255
	orr	r3, r2, r3
	and	r2, r3, #255
	ldr	r3, [fp, #-24]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldrb	r2, [fp, #-9]
	ldrb	r3, [fp, #-10]
	orr	r3, r2, r3
	and	r2, r3, #255
	ldrb	r3, [fp, #-11]
	and	r3, r3, r2
	and	r2, r3, #255
	ldrb	r1, [fp, #-12]
	ldrb	r3, [fp, #-9]
	and	r3, r3, r1
	and	r3, r3, #255
	orr	r3, r2, r3
	and	r2, r3, #255
	ldr	r3, [fp, #-24]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L93:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L102
	nop
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_bitwise_binary_and, .-vec4state_bitwise_binary_and
	.align	2
	.global	vec4state_bitwise_binary_or
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bitwise_binary_or, %function
vec4state_bitwise_binary_or:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L104
.L113:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L105
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L106
.L105:
	mov	r3, #0
.L106:
	strb	r3, [fp, #-12]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L107
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L108
.L107:
	mov	r3, #0
.L108:
	strb	r3, [fp, #-11]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L109
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L110
.L109:
	mov	r3, #0
.L110:
	strb	r3, [fp, #-10]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L111
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L112
.L111:
	mov	r3, #0
.L112:
	strb	r3, [fp, #-9]
	ldrb	r2, [fp, #-12]
	ldrb	r3, [fp, #-11]
	orr	r3, r2, r3
	and	r2, r3, #255
	ldrb	r3, [fp, #-10]
	orr	r3, r2, r3
	and	r2, r3, #255
	ldrb	r3, [fp, #-9]
	orr	r3, r2, r3
	and	r2, r3, #255
	ldr	r3, [fp, #-24]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldrsb	r3, [fp, #-12]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-9]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-10]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrsb	r3, [fp, #-11]
	and	r3, r3, r1
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrb	r2, [fp, #-11]
	ldrb	r3, [fp, #-9]
	and	r3, r3, r2
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-24]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L104:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L113
	nop
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_bitwise_binary_or, .-vec4state_bitwise_binary_or
	.align	2
	.global	vec4state_bitwise_binary_xor
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bitwise_binary_xor, %function
vec4state_bitwise_binary_xor:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L115
.L124:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L116
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L117
.L116:
	mov	r3, #0
.L117:
	strb	r3, [fp, #-12]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L118
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L119
.L118:
	mov	r3, #0
.L119:
	strb	r3, [fp, #-11]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L120
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L121
.L120:
	mov	r3, #0
.L121:
	strb	r3, [fp, #-10]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L122
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L123
.L122:
	mov	r3, #0
.L123:
	strb	r3, [fp, #-9]
	ldrb	r2, [fp, #-9]
	ldrb	r3, [fp, #-11]
	orr	r3, r2, r3
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-12]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrsb	r3, [fp, #-10]
	and	r3, r3, r1
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrsb	r3, [fp, #-10]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-12]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-24]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldrb	r2, [fp, #-9]
	ldrb	r3, [fp, #-11]
	orr	r3, r2, r3
	and	r2, r3, #255
	ldr	r3, [fp, #-24]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L115:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L124
	nop
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_bitwise_binary_xor, .-vec4state_bitwise_binary_xor
	.align	2
	.global	vec4state_bitwise_unary_negation
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bitwise_unary_negation, %function
vec4state_bitwise_unary_negation:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L126
.L131:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L127
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L128
.L127:
	mov	r3, #0
.L128:
	strb	r3, [fp, #-10]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L129
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L130
.L129:
	mov	r3, #0
.L130:
	strb	r3, [fp, #-9]
	ldrsb	r3, [fp, #-10]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrsb	r2, [fp, #-9]
	ldr	r3, [fp, #-20]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-20]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [fp, #-9]
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L126:
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L131
	ldr	r0, [fp, #-20]
	bl	vec4state_clear_padding_bits
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_bitwise_unary_negation, .-vec4state_bitwise_unary_negation
	.align	2
	.global	vec4state_reduction_unary_and
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_reduction_unary_and, %function
vec4state_reduction_unary_and:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L133
.L136:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3]
	ldr	r3, [fp, #-16]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r1, r3
	ldrsb	r3, [r3, #1]
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	cmn	r3, #1
	beq	.L134
	mov	r1, #0
	ldr	r0, [fp, #-20]
	bl	vec4state_set
	b	.L132
.L134:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L133:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r2, r3, #1
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L136
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3]
	ldr	r3, [fp, #-16]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r1, r3
	ldrsb	r3, [r3, #1]
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	mov	r1, r3
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	rsb	r3, r3, #0
	and	r3, r3, #7
	mov	r2, #255
	asr	r3, r2, r3
	cmp	r1, r3
	beq	.L137
	mov	r1, #0
	ldr	r0, [fp, #-20]
	bl	vec4state_set
	b	.L132
.L137:
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L138
.L140:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	cmp	r3, #0
	beq	.L139
	mov	r1, #3
	ldr	r0, [fp, #-20]
	bl	vec4state_set
	b	.L132
.L139:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L138:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L140
	mov	r1, #1
	ldr	r0, [fp, #-20]
	bl	vec4state_set
.L132:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_reduction_unary_and, .-vec4state_reduction_unary_and
	.align	2
	.global	vec4state_reduction_unary_or
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_reduction_unary_or, %function
vec4state_reduction_unary_or:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L142
.L145:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	mov	r1, r3
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	mvn	r3, r3
	and	r3, r3, r1
	cmp	r3, #0
	beq	.L143
	mov	r1, #1
	ldr	r0, [fp, #-20]
	bl	vec4state_set
	b	.L141
.L143:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L142:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L145
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L146
.L148:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	cmp	r3, #0
	beq	.L147
	mov	r1, #3
	ldr	r0, [fp, #-20]
	bl	vec4state_set
	b	.L141
.L147:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L146:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L148
	mov	r1, #0
	ldr	r0, [fp, #-20]
	bl	vec4state_set
.L141:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_reduction_unary_or, .-vec4state_reduction_unary_or
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	count_bits, %function
count_bits:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	mov	r3, r0
	strb	r3, [fp, #-13]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L150
.L151:
	ldrb	r3, [fp, #-13]
	sub	r3, r3, #1
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-13]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	strb	r3, [fp, #-13]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L150:
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L151
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	count_bits, .-count_bits
	.align	2
	.global	vec4state_reduction_unary_xor
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_reduction_unary_xor, %function
vec4state_reduction_unary_xor:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-12]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L154
.L157:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	cmp	r3, #0
	beq	.L155
	mov	r1, #3
	ldr	r0, [fp, #-20]
	bl	vec4state_set
	b	.L153
.L155:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	mov	r0, r3
	bl	count_bits
	mov	r2, r0
	ldr	r3, [fp, #-12]
	add	r3, r3, r2
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L154:
	ldr	r3, [fp, #-16]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L157
	ldr	r3, [fp, #-12]
	and	r3, r3, #1
	mov	r1, r3
	ldr	r0, [fp, #-20]
	bl	vec4state_set
.L153:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_reduction_unary_xor, .-vec4state_reduction_unary_xor
	.align	2
	.global	vec4state_shift_right
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_shift_right, %function
vec4state_shift_right:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #40
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	str	r2, [fp, #-40]
	str	r3, [fp, #-44]
	mov	r3, #0
	strh	r3, [fp, #-28]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-26]	@ movhi
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	ble	.L159
	ldr	r3, [fp, #-36]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-36]
	rsbs	r2, r3, #0
	and	r3, r3, #7
	and	r2, r2, #7
	rsbpl	r3, r2, #0
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	str	r3, [fp, #-16]
	b	.L160
.L159:
	ldr	r3, [fp, #-36]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	rsb	r3, r3, #0
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-36]
	rsb	r3, r3, #0
	rsbs	r2, r3, #0
	and	r3, r3, #7
	and	r2, r2, #7
	rsbpl	r3, r2, #0
	rsb	r3, r3, #8
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-12]
	sub	r3, r3, #1
	str	r3, [fp, #-16]
.L160:
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	blt	.L161
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-16]
	cmp	r2, r3
	bls	.L161
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	strh	r3, [fp, #-28]	@ movhi
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	strh	r3, [fp, #-26]	@ movhi
.L161:
	mov	r3, #0
	str	r3, [fp, #-20]
	b	.L162
.L164:
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	blt	.L163
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-16]
	cmp	r2, r3
	bls	.L163
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrsh	r3, [fp, #-28]
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	strh	r3, [fp, #-28]	@ movhi
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrsh	r3, [fp, #-26]
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	strh	r3, [fp, #-26]	@ movhi
.L163:
	ldrh	r2, [fp, #-28]
	ldr	r3, [fp, #-24]
	asr	r2, r2, r3
	ldr	r3, [fp, #-40]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldrh	r2, [fp, #-26]
	ldr	r3, [fp, #-24]
	asr	r2, r2, r3
	ldr	r3, [fp, #-40]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	ldrh	r3, [fp, #-28]
	lsr	r3, r3, #8
	strh	r3, [fp, #-28]	@ movhi
	ldrh	r3, [fp, #-26]
	lsr	r3, r3, #8
	strh	r3, [fp, #-26]	@ movhi
	ldr	r3, [fp, #-20]
	add	r3, r3, #1
	str	r3, [fp, #-20]
.L162:
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	bhi	.L164
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	beq	.L165
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	sub	r3, r3, #1
	mov	r1, r3
	ldr	r0, [fp, #-32]
	bl	vec4state_bit_test
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-40]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-36]
	sub	r3, r2, r3
	sub	r1, r3, #1
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, #4]
	sub	r2, r3, #1
	ldr	r3, [fp, #-8]
	ldr	r0, [fp, #-40]
	bl	vec4state_bitfield_set
.L165:
	ldr	r0, [fp, #-40]
	bl	vec4state_clear_padding_bits
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_shift_right, .-vec4state_shift_right
	.align	2
	.global	vec4state_shift_left
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_shift_left, %function
vec4state_shift_left:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	str	r2, [fp, #-16]
	ldr	r3, [fp, #-12]
	rsb	r1, r3, #0
	mov	r3, #0
	ldr	r2, [fp, #-16]
	ldr	r0, [fp, #-8]
	bl	vec4state_shift_right
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_shift_left, .-vec4state_shift_left
	.align	2
	.global	vec4state_add_unsigned_word
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_add_unsigned_word, %function
vec4state_add_unsigned_word:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r0, [fp, #-16]
	mov	r3, r1
	str	r2, [fp, #-24]
	strb	r3, [fp, #-17]
	ldrb	r3, [fp, #-17]	@ zero_extendqisi2
	strh	r3, [fp, #-10]	@ movhi
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L168
.L171:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	cmp	r3, #0
	beq	.L169
	mov	r1, #3
	ldr	r0, [fp, #-24]
	bl	vec4state_set
	b	.L167
.L169:
	ldr	r3, [fp, #-16]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r3, [fp, #-10]	@ movhi
	add	r3, r2, r3
	strh	r3, [fp, #-10]	@ movhi
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrh	r2, [fp, #-10]	@ movhi
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3, #1]
	ldrh	r3, [fp, #-10]
	lsr	r3, r3, #8
	strh	r3, [fp, #-10]	@ movhi
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L168:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L171
	ldr	r0, [fp, #-24]
	bl	vec4state_clear_padding_bits
.L167:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_add_unsigned_word, .-vec4state_add_unsigned_word
	.align	2
	.global	vec4state_add
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_add, %function
vec4state_add:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #32
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-32]
	mov	r3, #0
	strh	r3, [fp, #-10]	@ movhi
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L173
.L185:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L174
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L175
.L174:
	mov	r3, #0
.L175:
	strb	r3, [fp, #-14]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L176
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L177
.L176:
	mov	r3, #0
.L177:
	strb	r3, [fp, #-13]
	ldr	r3, [fp, #-28]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L178
	ldr	r3, [fp, #-28]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L179
.L178:
	mov	r3, #0
.L179:
	strb	r3, [fp, #-12]
	ldr	r3, [fp, #-28]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L180
	ldr	r3, [fp, #-28]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L181
.L180:
	mov	r3, #0
.L181:
	strb	r3, [fp, #-11]
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldrb	r3, [fp, #-11]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
.L182:
	mov	r1, #3
	ldr	r0, [fp, #-32]
	bl	vec4state_set
	b	.L172
.L183:
	ldrh	r3, [fp, #-10]
	lsr	r3, r3, #8
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrb	r3, [fp, #-14]	@ zero_extendqisi2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrb	r3, [fp, #-12]	@ zero_extendqisi2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	strh	r3, [fp, #-10]	@ movhi
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrh	r2, [fp, #-10]	@ movhi
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L173:
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L185
.L172:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_add, .-vec4state_add
	.align	2
	.global	vec4state_sub
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_sub, %function
vec4state_sub:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #32
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-32]
	mov	r3, #0
	strh	r3, [fp, #-10]	@ movhi
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L187
.L199:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L188
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L189
.L188:
	mov	r3, #0
.L189:
	strb	r3, [fp, #-14]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L190
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L191
.L190:
	mov	r3, #0
.L191:
	strb	r3, [fp, #-13]
	ldr	r3, [fp, #-28]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L192
	ldr	r3, [fp, #-28]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L193
.L192:
	mov	r3, #0
.L193:
	strb	r3, [fp, #-12]
	ldr	r3, [fp, #-28]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L194
	ldr	r3, [fp, #-28]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	b	.L195
.L194:
	mov	r3, #0
.L195:
	strb	r3, [fp, #-11]
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldrb	r3, [fp, #-11]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
.L196:
	mov	r1, #3
	ldr	r0, [fp, #-32]
	bl	vec4state_set
	b	.L186
.L197:
	ldrh	r3, [fp, #-10]
	lsr	r3, r3, #8
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrb	r3, [fp, #-14]	@ zero_extendqisi2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrb	r3, [fp, #-12]	@ zero_extendqisi2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	strh	r3, [fp, #-10]	@ movhi
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrh	r2, [fp, #-10]	@ movhi
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L187:
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bhi	.L199
	ldr	r0, [fp, #-32]
	bl	vec4state_clear_padding_bits
.L186:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_sub, .-vec4state_sub
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	add3, %function
add3:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	mov	r3, r0
	str	r2, [fp, #-20]
	strh	r3, [fp, #-14]	@ movhi
	mov	r3, r1	@ movhi
	strh	r3, [fp, #-16]	@ movhi
	ldr	r3, [fp, #-20]
	ldrh	r3, [r3]	@ movhi
	strh	r3, [fp, #-10]	@ movhi
	ldrh	r2, [fp, #-14]	@ movhi
	ldrh	r3, [fp, #-16]	@ movhi
	add	r3, r2, r3
	strh	r3, [fp, #-8]	@ movhi
	ldrh	r2, [fp, #-8]	@ movhi
	ldrh	r3, [fp, #-10]	@ movhi
	add	r3, r2, r3
	strh	r3, [fp, #-6]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-10]	@ movhi
	ldrh	r2, [fp, #-8]
	ldrh	r3, [fp, #-16]
	cmp	r2, r3
	bcs	.L201
	ldrh	r3, [fp, #-10]
	add	r3, r3, #1
	strh	r3, [fp, #-10]	@ movhi
.L201:
	ldrh	r2, [fp, #-6]
	ldrh	r3, [fp, #-8]
	cmp	r2, r3
	bcs	.L202
	ldrh	r3, [fp, #-10]
	add	r3, r3, #1
	strh	r3, [fp, #-10]	@ movhi
.L202:
	ldrh	r2, [fp, #-6]
	ldrh	r3, [fp, #-14]
	cmp	r2, r3
	bcs	.L203
	ldrh	r3, [fp, #-10]
	add	r3, r3, #1
	strh	r3, [fp, #-10]	@ movhi
.L203:
	ldr	r3, [fp, #-20]
	ldrh	r2, [fp, #-10]	@ movhi
	strh	r2, [r3]	@ movhi
	ldrh	r3, [fp, #-6]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	add3, .-add3
	.section	.rodata
	.align	2
.LC3:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	vec4state_mul_unsigned_word
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_mul_unsigned_word, %function
vec4state_mul_unsigned_word:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #32
	str	r0, [fp, #-24]
	mov	r3, r1
	str	r2, [fp, #-32]
	strb	r3, [fp, #-25]
	ldr	r3, .L213
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r0, [fp, #-24]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	beq	.L206
	mov	r1, #3
	ldr	r0, [fp, #-32]
	bl	vec4state_set
	b	.L205
.L206:
	mov	r3, #0
	strh	r3, [fp, #-16]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-18]	@ movhi
	mov	r3, #0
	str	r3, [fp, #-12]
	b	.L208
.L211:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-12]
	cmp	r2, r3
	bls	.L209
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	b	.L210
.L209:
	mov	r3, #0
.L210:
	strb	r3, [fp, #-19]
	ldrb	r3, [fp, #-19]	@ zero_extendqisi2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldrb	r2, [fp, #-25]	@ zero_extendqisi2
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	mul	r3, r2, r3
	strh	r3, [fp, #-14]	@ movhi
	sub	r2, fp, #18
	ldrh	r1, [fp, #-14]
	ldrh	r3, [fp, #-16]
	mov	r0, r3
	bl	add3
	mov	r3, r0
	strh	r3, [fp, #-16]	@ movhi
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrh	r2, [fp, #-16]	@ movhi
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3, #1]
	ldrh	r3, [fp, #-16]
	lsr	r3, r3, #8
	strh	r3, [fp, #-16]	@ movhi
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
.L208:
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-12]
	cmp	r2, r3
	bhi	.L211
	ldr	r0, [fp, #-32]
	bl	vec4state_clear_padding_bits
.L205:
	ldr	r3, .L213
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L212
	bl	__stack_chk_fail
.L212:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L214:
	.align	2
.L213:
	.word	.LC3
	.size	vec4state_mul_unsigned_word, .-vec4state_mul_unsigned_word
	.section	.rodata
	.align	2
.LC4:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	vec4state_mul
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_mul, %function
vec4state_mul:
	@ args = 0, pretend = 0, frame = 48
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #48
	str	r0, [fp, #-40]
	str	r1, [fp, #-44]
	str	r2, [fp, #-48]
	ldr	r3, .L225
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r0, [fp, #-40]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	bne	.L216
	ldr	r0, [fp, #-44]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	beq	.L217
.L216:
	mov	r1, #3
	ldr	r0, [fp, #-48]
	bl	vec4state_set
	b	.L215
.L217:
	mov	r3, #0
	strh	r3, [fp, #-28]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-30]	@ movhi
	mov	r3, #0
	str	r3, [fp, #-24]
	b	.L219
.L223:
	mov	r3, #0
	str	r3, [fp, #-20]
	b	.L220
.L222:
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-20]
	sub	r3, r2, r3
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	ldr	r2, [fp, #-16]
	cmp	r2, r3
	bcs	.L221
	ldr	r3, [fp, #-44]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bcs	.L221
	ldr	r3, [fp, #-40]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-44]
	ldr	r1, [r2, #12]
	ldr	r2, [fp, #-12]
	lsl	r2, r2, #1
	add	r2, r1, r2
	ldrsb	r2, [r2]
	and	r2, r2, #255
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	mul	r3, r2, r3
	strh	r3, [fp, #-26]	@ movhi
	sub	r2, fp, #30
	ldrh	r1, [fp, #-26]
	ldrh	r3, [fp, #-28]
	mov	r0, r3
	bl	add3
	mov	r3, r0
	strh	r3, [fp, #-28]	@ movhi
.L221:
	ldr	r3, [fp, #-20]
	add	r3, r3, #1
	str	r3, [fp, #-20]
.L220:
	ldr	r3, [fp, #-44]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	bhi	.L222
	ldr	r3, [fp, #-48]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrh	r2, [fp, #-28]	@ movhi
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-48]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-24]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3, #1]
	ldrh	r3, [fp, #-28]
	lsr	r3, r3, #8
	strh	r3, [fp, #-28]	@ movhi
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	str	r3, [fp, #-24]
.L219:
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-24]
	cmp	r2, r3
	bhi	.L223
.L215:
	ldr	r3, .L225
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L224
	bl	__stack_chk_fail
.L224:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L226:
	.align	2
.L225:
	.word	.LC4
	.size	vec4state_mul, .-vec4state_mul
	.global	__aeabi_idivmod
	.global	__aeabi_idiv
	.align	2
	.global	vec4state_div_unsigned_word
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_div_unsigned_word, %function
vec4state_div_unsigned_word:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #32
	str	r0, [fp, #-24]
	mov	r3, r1
	str	r2, [fp, #-32]
	strb	r3, [fp, #-25]
	ldr	r0, [fp, #-24]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	beq	.L228
	mov	r1, #3
	ldr	r0, [fp, #-32]
	bl	vec4state_set
	mov	r3, #0
	b	.L229
.L228:
	mov	r3, #0
	strh	r3, [fp, #-14]	@ movhi
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #1
	str	r3, [fp, #-8]
	b	.L230
.L231:
	ldrh	r3, [fp, #-14]
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-24]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r1, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	strh	r3, [fp, #-12]	@ movhi
	ldrh	r3, [fp, #-12]
	ldrb	r2, [fp, #-25]	@ zero_extendqisi2
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_idivmod
	mov	r3, r1
	strh	r3, [fp, #-14]	@ movhi
	ldrh	r3, [fp, #-12]
	ldrb	r2, [fp, #-25]	@ zero_extendqisi2
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_idiv
	mov	r3, r0
	strh	r3, [fp, #-10]	@ movhi
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrh	r2, [fp, #-10]	@ movhi
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-8]
	sub	r3, r3, #1
	str	r3, [fp, #-8]
.L230:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bge	.L231
	ldr	r0, [fp, #-32]
	bl	vec4state_clear_padding_bits
	ldrh	r3, [fp, #-14]	@ movhi
	and	r3, r3, #255
.L229:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_div_unsigned_word, .-vec4state_div_unsigned_word
	.section	.rodata
	.align	2
.LC5:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	vec4state_div_unsigned
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_div_unsigned, %function
vec4state_div_unsigned:
	@ args = 0, pretend = 0, frame = 72
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, fp, lr}
	add	fp, sp, #8
	sub	sp, sp, #76
	str	r0, [fp, #-72]
	str	r1, [fp, #-76]
	str	r2, [fp, #-80]
	str	r3, [fp, #-84]
	ldr	r3, .L264
	ldr	r3, [r3]
	str	r3, [fp, #-16]
	mov	r3,#0
	ldr	r3, [fp, #-76]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	str	r3, [fp, #-48]
	b	.L233
.L235:
	ldr	r3, [fp, #-48]
	sub	r3, r3, #1
	str	r3, [fp, #-48]
.L233:
	ldr	r3, [fp, #-48]
	cmp	r3, #0
	ble	.L234
	ldr	r3, [fp, #-76]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-48]
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	cmp	r3, #0
	beq	.L235
.L234:
	ldr	r3, [fp, #-48]
	cmp	r3, #0
	beq	.L236
	ldr	r0, [fp, #-72]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	bne	.L236
	ldr	r0, [fp, #-76]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	beq	.L237
.L236:
	mov	r1, #3
	ldr	r0, [fp, #-80]
	bl	vec4state_set
	mov	r1, #3
	ldr	r0, [fp, #-84]
	bl	vec4state_set
	b	.L238
.L237:
	mov	r3, sp
	mov	r4, r3
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-44]
	add	r2, r3, #1
	ldr	r3, [fp, #-48]
	add	r3, r2, r3
	add	ip, r3, #1
	sub	r3, ip, #1
	str	r3, [fp, #-40]
	mov	r3, ip
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #3
	orr	r3, r3, r0, lsr #29
	lsl	r2, r0, #3
	mov	r3, ip
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #3
	orr	r3, r3, r0, lsr #29
	lsl	r2, r0, #3
	mov	r3, ip
	add	r3, r3, #7
	lsr	r3, r3, #3
	lsl	r3, r3, #3
	sub	sp, sp, r3
	mov	r3, sp
	add	r3, r3, #0
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-48]
	add	ip, r3, #2
	sub	r3, ip, #1
	str	r3, [fp, #-32]
	mov	r3, ip
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #3
	orr	r3, r3, r0, lsr #29
	lsl	r2, r0, #3
	mov	r3, ip
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #3
	orr	r3, r3, r0, lsr #29
	lsl	r2, r0, #3
	mov	r3, ip
	add	r3, r3, #7
	lsr	r3, r3, #3
	lsl	r3, r3, #3
	sub	sp, sp, r3
	mov	r3, sp
	add	r3, r3, #0
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-44]
	add	ip, r3, #1
	sub	r3, ip, #1
	str	r3, [fp, #-24]
	mov	r3, ip
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #3
	orr	r3, r3, r0, lsr #29
	lsl	r2, r0, #3
	mov	r3, ip
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #3
	orr	r3, r3, r0, lsr #29
	lsl	r2, r0, #3
	mov	r3, ip
	add	r3, r3, #7
	lsr	r3, r3, #3
	lsl	r3, r3, #3
	sub	sp, sp, r3
	mov	r3, sp
	add	r3, r3, #0
	str	r3, [fp, #-20]
	mov	r3, #1
	str	r3, [fp, #-52]
	b	.L239
.L240:
	ldr	r3, [fp, #-72]
	ldr	r2, [r3, #12]
	ldr	r1, [fp, #-44]
	ldr	r3, [fp, #-48]
	add	r1, r1, r3
	ldr	r3, [fp, #-52]
	sub	r3, r1, r3
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r1, r3, #255
	ldr	r2, [fp, #-36]
	ldr	r3, [fp, #-52]
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3]
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	str	r3, [fp, #-52]
.L239:
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-48]
	add	r3, r2, r3
	ldr	r2, [fp, #-52]
	cmp	r2, r3
	ble	.L240
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-48]
	add	r3, r2, r3
	add	r3, r3, #1
	ldr	r2, [fp, #-28]
	mov	r1, #0
	strb	r1, [r2, r3]
	mov	r3, #1
	str	r3, [fp, #-52]
	b	.L241
.L242:
	ldr	r3, [fp, #-76]
	ldr	r2, [r3, #12]
	ldr	r1, [fp, #-48]
	ldr	r3, [fp, #-52]
	sub	r3, r1, r3
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r1, r3, #255
	ldr	r2, [fp, #-28]
	ldr	r3, [fp, #-52]
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3]
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	str	r3, [fp, #-52]
.L241:
	ldr	r2, [fp, #-52]
	ldr	r3, [fp, #-48]
	cmp	r2, r3
	ble	.L242
	ldr	r3, [fp, #-48]
	add	r3, r3, #1
	ldr	r2, [fp, #-28]
	mov	r1, #0
	strb	r1, [r2, r3]
	mov	r3, #1
	str	r3, [fp, #-56]
	b	.L243
.L251:
	ldr	r2, [fp, #-36]
	ldr	r3, [fp, #-56]
	add	r3, r2, r3
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, [fp, #-28]
	ldrb	r3, [r3, #1]	@ zero_extendqisi2
	cmp	r2, r3
	bne	.L244
	mov	r3, #255
	strh	r3, [fp, #-64]	@ movhi
	b	.L248
.L244:
	ldr	r2, [fp, #-36]
	ldr	r3, [fp, #-56]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #8
	ldr	r2, [fp, #-56]
	add	r2, r2, #1
	ldr	r1, [fp, #-36]
	ldrb	r2, [r1, r2]	@ zero_extendqisi2
	orr	r2, r3, r2
	ldr	r3, [fp, #-28]
	ldrb	r3, [r3, #1]	@ zero_extendqisi2
	mov	r1, r3
	mov	r0, r2
	bl	__aeabi_idiv
	mov	r3, r0
	strh	r3, [fp, #-64]	@ movhi
.L248:
	ldr	r2, [fp, #-36]
	ldr	r3, [fp, #-56]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-56]
	add	r3, r3, #1
	ldr	r1, [fp, #-36]
	ldrb	r3, [r1, r3]	@ zero_extendqisi2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-28]
	ldrb	r3, [r3, #1]	@ zero_extendqisi2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldrh	r1, [fp, #-64]	@ movhi
	mul	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	strh	r3, [fp, #-60]	@ movhi
	ldr	r3, [fp, #-28]
	ldrb	r3, [r3, #2]	@ zero_extendqisi2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldrh	r2, [fp, #-64]	@ movhi
	mul	r3, r2, r3
	strh	r3, [fp, #-58]	@ movhi
	ldrh	r2, [fp, #-58]
	ldrh	r3, [fp, #-60]
	cmp	r2, r3
	bcc	.L246
	ldrh	r3, [fp, #-60]
	cmp	r3, #255
	bhi	.L246
	ldrh	r2, [fp, #-58]
	ldrh	r3, [fp, #-60]
	lsl	r3, r3, #8
	ldr	r1, [fp, #-56]
	add	r1, r1, #2
	ldr	r0, [fp, #-36]
	ldrb	r1, [r0, r1]	@ zero_extendqisi2
	orr	r3, r3, r1
	cmp	r2, r3
	ble	.L263
	ldrh	r3, [fp, #-64]	@ movhi
	sub	r3, r3, #1
	strh	r3, [fp, #-64]	@ movhi
	b	.L248
.L263:
	nop
.L246:
	mov	r3, #0
	strh	r3, [fp, #-62]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-66]	@ movhi
	ldr	r3, [fp, #-48]
	str	r3, [fp, #-52]
	b	.L249
.L250:
	ldr	r2, [fp, #-56]
	ldr	r3, [fp, #-52]
	add	r3, r2, r3
	ldr	r2, [fp, #-36]
	ldrb	r3, [r2, r3]	@ zero_extendqisi2
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r3, [fp, #-62]	@ movhi
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r0, r3, #16
	ldrh	r3, [fp, #-64]
	rsb	r3, r3, #0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r1, [fp, #-28]
	ldr	r2, [fp, #-52]
	add	r2, r1, r2
	ldrb	r2, [r2]	@ zero_extendqisi2
	lsl	r2, r2, #16
	lsr	r2, r2, #16
	mul	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r2, fp, #66
	mov	r1, r3
	bl	add3
	mov	r3, r0
	strh	r3, [fp, #-62]	@ movhi
	ldr	r2, [fp, #-56]
	ldr	r3, [fp, #-52]
	add	r3, r2, r3
	ldrh	r2, [fp, #-62]	@ movhi
	and	r1, r2, #255
	ldr	r2, [fp, #-36]
	strb	r1, [r2, r3]
	ldrh	r3, [fp, #-62]
	lsr	r3, r3, #8
	strh	r3, [fp, #-62]	@ movhi
	ldr	r3, [fp, #-52]
	sub	r3, r3, #1
	str	r3, [fp, #-52]
.L249:
	ldr	r3, [fp, #-52]
	cmp	r3, #0
	bgt	.L250
	ldrh	r3, [fp, #-64]	@ movhi
	and	r1, r3, #255
	ldr	r2, [fp, #-20]
	ldr	r3, [fp, #-56]
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3]
	ldr	r3, [fp, #-56]
	add	r3, r3, #1
	str	r3, [fp, #-56]
.L243:
	ldr	r2, [fp, #-56]
	ldr	r3, [fp, #-44]
	cmp	r2, r3
	ble	.L251
	ldr	r3, [fp, #-80]
	cmp	r3, #0
	beq	.L252
	mov	r3, #0
	str	r3, [fp, #-52]
	b	.L253
.L256:
	ldr	r2, [fp, #-52]
	ldr	r3, [fp, #-44]
	cmp	r2, r3
	bge	.L254
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-52]
	sub	r3, r2, r3
	ldr	r2, [fp, #-20]
	ldrb	r3, [r2, r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	b	.L255
.L254:
	mov	r1, #0
.L255:
	ldr	r3, [fp, #-80]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3]
	ldr	r3, [fp, #-80]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	str	r3, [fp, #-52]
.L253:
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-52]
	cmp	r2, r3
	bhi	.L256
.L252:
	ldr	r3, [fp, #-84]
	cmp	r3, #0
	beq	.L257
	mov	r3, #0
	str	r3, [fp, #-52]
	b	.L258
.L261:
	ldr	r2, [fp, #-52]
	ldr	r3, [fp, #-48]
	cmp	r2, r3
	bge	.L259
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-48]
	add	r2, r2, r3
	ldr	r3, [fp, #-52]
	sub	r3, r2, r3
	ldr	r2, [fp, #-36]
	ldrb	r3, [r2, r3]	@ zero_extendqisi2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	b	.L260
.L259:
	mov	r1, #0
.L260:
	ldr	r3, [fp, #-84]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, r1
	strb	r2, [r3]
	ldr	r3, [fp, #-84]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #1
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	str	r3, [fp, #-52]
.L258:
	ldr	r3, [fp, #-84]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-52]
	cmp	r2, r3
	bhi	.L261
.L257:
	mov	sp, r4
.L238:
	nop
	ldr	r3, .L264
	ldr	r2, [r3]
	ldr	r3, [fp, #-16]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L262
	bl	__stack_chk_fail
.L262:
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, fp, pc}
.L265:
	.align	2
.L264:
	.word	.LC5
	.size	vec4state_div_unsigned, .-vec4state_div_unsigned
	.section	.rodata
	.align	2
.LC6:
	.ascii	"FATAL: vec4state_pow(): exponent overflow! (runtime"
	.ascii	" may exceed your lifetime.)!\012\000"
	.text
	.align	2
	.global	vec4state_pow
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_pow, %function
vec4state_pow:
	@ args = 0, pretend = 0, frame = 48
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #48
	str	r0, [fp, #-40]
	str	r1, [fp, #-44]
	str	r2, [fp, #-48]
	ldr	r1, .L283
	ldr	r0, [fp, #-40]
	bl	vec4state_cmp
	str	r0, [fp, #-24]
	ldr	r1, .L283
	ldr	r0, [fp, #-44]
	bl	vec4state_cmp
	str	r0, [fp, #-20]
	ldr	r1, .L283+4
	ldr	r0, [fp, #-40]
	bl	vec4state_cmp
	str	r0, [fp, #-16]
	ldr	r1, .L283+8
	ldr	r0, [fp, #-40]
	bl	vec4state_cmp
	str	r0, [fp, #-12]
	ldr	r0, [fp, #-40]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	bne	.L267
	ldr	r0, [fp, #-44]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	beq	.L268
.L267:
	mov	r1, #3
	ldr	r0, [fp, #-48]
	bl	vec4state_set
	b	.L269
.L268:
	ldr	r3, [fp, #-20]
	cmp	r3, #0
	beq	.L270
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	bne	.L271
.L270:
	mov	r1, #1
	ldr	r0, [fp, #-48]
	bl	vec4state_set
	b	.L269
.L271:
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	bne	.L272
	ldr	r3, [fp, #-44]
	ldr	r3, [r3, #12]
	ldrsb	r3, [r3]
	and	r3, r3, #255
	and	r3, r3, #1
	cmp	r3, #0
	beq	.L273
	mvn	r3, #0
	b	.L274
.L273:
	mov	r3, #1
.L274:
	mov	r1, r3
	ldr	r0, [fp, #-48]
	bl	vec4state_set
	b	.L282
.L272:
	ldr	r3, [fp, #-20]
	cmp	r3, #0
	bge	.L275
	mov	r1, #0
	ldr	r0, [fp, #-48]
	bl	vec4state_set
	b	.L282
.L275:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L276
	ldr	r3, [fp, #-20]
	cmp	r3, #0
	bge	.L277
	mov	r3, #3
	b	.L278
.L277:
	mov	r3, #0
.L278:
	mov	r1, r3
	ldr	r0, [fp, #-48]
	bl	vec4state_set
	b	.L282
.L276:
	ldr	r3, [fp, #-44]
	ldr	r3, [r3, #4]
	cmp	r3, #32
	bls	.L279
	ldr	r3, .L283+12
	ldr	r3, [r3]
	mov	r2, #80
	mov	r1, #1
	ldr	r0, .L283+16
	bl	fwrite
	bl	abort
.L279:
	ldr	r3, [fp, #-48]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-44]
	ldr	r3, [r3, #12]
	ldrsb	r3, [r3]
	strb	r3, [fp, #-29]
	mov	r1, #1
	ldr	r0, [fp, #-48]
	bl	vec4state_set
	mov	r3, #0
	str	r3, [fp, #-28]
	b	.L280
.L281:
	ldr	r1, [fp, #-8]
	ldr	r0, [fp, #-48]
	bl	vec4state_copy
	ldr	r2, [fp, #-48]
	ldr	r1, [fp, #-40]
	ldr	r0, [fp, #-8]
	bl	vec4state_mul
	ldr	r3, [fp, #-28]
	add	r3, r3, #1
	str	r3, [fp, #-28]
.L280:
	ldrb	r3, [fp, #-29]	@ zero_extendqisi2
	ldr	r2, [fp, #-28]
	cmp	r2, r3
	blt	.L281
	ldr	r0, [fp, #-8]
	bl	vec4state_free
	b	.L282
.L269:
.L282:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L284:
	.align	2
.L283:
	.word	vec4state_const_zero
	.word	vec4state_const_one
	.word	vec4state_const_minus_one
	.word	stderr
	.word	.LC6
	.size	vec4state_pow, .-vec4state_pow
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	word_reverse_bits, %function
word_reverse_bits:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	mov	r3, r0
	strb	r3, [fp, #-13]
	mov	r3, #8
	str	r3, [fp, #-8]
	mvn	r3, #0
	strb	r3, [fp, #-9]
	b	.L286
.L287:
	ldrb	r2, [fp, #-9]	@ zero_extendqisi2
	ldr	r3, [fp, #-8]
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-9]
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	strb	r3, [fp, #-9]
	ldrb	r2, [fp, #-13]	@ zero_extendqisi2
	ldr	r3, [fp, #-8]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-9]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-13]	@ zero_extendqisi2
	ldr	r3, [fp, #-8]
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrsb	r3, [fp, #-9]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, r1
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	strb	r3, [fp, #-13]
.L286:
	ldr	r3, [fp, #-8]
	lsr	r3, r3, #1
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L287
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	word_reverse_bits, .-word_reverse_bits
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_get_word_at_bitpos, %function
vec4state_get_word_at_bitpos:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #36
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-32]
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-28]
	asr	r3, r3, #3
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	mov	r2, r3
	ldr	r3, [fp, #-16]
	cmp	r3, r2
	blt	.L290
	ldr	r3, [fp, #-32]
	mov	r2, #0
	strb	r2, [r3]
	ldr	r3, [fp, #-36]
	mov	r2, #0
	strb	r2, [r3]
	b	.L295
.L290:
	ldr	r3, [fp, #-28]
	and	r3, r3, #7
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	bge	.L292
	mov	r3, #0
	strh	r3, [fp, #-20]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-18]	@ movhi
	b	.L293
.L292:
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	strh	r3, [fp, #-20]	@ movhi
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	strh	r3, [fp, #-18]	@ movhi
.L293:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	blt	.L294
	ldr	r3, [fp, #-24]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	mov	r2, r3
	ldr	r3, [fp, #-8]
	cmp	r3, r2
	bge	.L294
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrsh	r3, [fp, #-20]
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	strh	r3, [fp, #-20]	@ movhi
	ldr	r3, [fp, #-24]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrsh	r3, [fp, #-18]
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	strh	r3, [fp, #-18]	@ movhi
.L294:
	ldrh	r2, [fp, #-20]
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	strh	r3, [fp, #-20]	@ movhi
	ldrh	r2, [fp, #-18]
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	strh	r3, [fp, #-18]	@ movhi
	ldrh	r3, [fp, #-20]	@ movhi
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-32]
	strb	r2, [r3]
	ldrh	r3, [fp, #-18]	@ movhi
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-36]
	strb	r2, [r3]
.L295:
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	vec4state_get_word_at_bitpos, .-vec4state_get_word_at_bitpos
	.section	.rodata
	.align	2
.LC7:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	vec4state_bitselect_get
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bitselect_get, %function
vec4state_bitselect_get:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #32
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-32]
	str	r3, [fp, #-36]
	ldr	r3, .L302
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	bne	.L297
	ldr	r1, [fp, #-28]
	mov	r3, #0
	ldr	r2, [fp, #-32]
	ldr	r0, [fp, #-24]
	bl	vec4state_shift_right
	b	.L298
.L297:
	mov	r3, #0
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-28]
	add	r3, r2, r3
	sub	r3, r3, #8
	str	r3, [fp, #-28]
	b	.L299
.L300:
	ldr	r1, [fp, #-28]
	sub	r3, fp, #13
	sub	r2, fp, #14
	ldr	r0, [fp, #-24]
	bl	vec4state_get_word_at_bitpos
	ldrsb	r3, [fp, #-14]
	and	r3, r3, #255
	mov	r0, r3
	bl	word_reverse_bits
	mov	r3, r0
	mov	r1, r3
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	lsl	r2, r1, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldrsb	r3, [fp, #-13]
	and	r3, r3, #255
	mov	r0, r3
	bl	word_reverse_bits
	mov	r3, r0
	mov	r1, r3
	ldr	r3, [fp, #-32]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	add	r3, r2, r3
	lsl	r2, r1, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-28]
	sub	r3, r3, #8
	str	r3, [fp, #-28]
.L299:
	ldr	r3, [fp, #-32]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r2, r3, #3
	ldr	r3, [fp, #-12]
	cmp	r2, r3
	bhi	.L300
.L298:
	ldr	r0, [fp, #-32]
	bl	vec4state_clear_padding_bits
	nop
	ldr	r3, .L302
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L301
	bl	__stack_chk_fail
.L301:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L303:
	.align	2
.L302:
	.word	.LC7
	.size	vec4state_bitselect_get, .-vec4state_bitselect_get
	.align	2
	.global	vec4state_bitselect_set
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_bitselect_set, %function
vec4state_bitselect_set:
	@ args = 0, pretend = 0, frame = 72
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #72
	str	r0, [fp, #-64]
	str	r1, [fp, #-68]
	str	r2, [fp, #-72]
	str	r3, [fp, #-76]
	ldr	r2, [fp, #-68]
	ldr	r3, [fp, #-72]
	cmp	r2, r3
	bcs	.L305
	ldr	r3, [fp, #-68]
	and	r3, r3, #7
	rsb	r3, r3, #8
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-68]
	lsr	r3, r3, #3
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-72]
	lsr	r3, r3, #3
	str	r3, [fp, #-8]
	mov	r3, #0
	strh	r3, [fp, #-52]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-50]	@ movhi
	mov	r3, #0
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-12]
	str	r3, [fp, #-40]
	b	.L306
.L312:
	ldr	r3, [fp, #-64]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	ldr	r2, [fp, #-44]
	cmp	r2, r3
	bcs	.L307
	ldr	r3, [fp, #-64]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-44]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrsh	r3, [fp, #-52]
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	strh	r3, [fp, #-52]	@ movhi
	ldr	r3, [fp, #-64]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-44]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrsh	r3, [fp, #-50]
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	strh	r3, [fp, #-50]	@ movhi
.L307:
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-12]
	cmp	r2, r3
	beq	.L308
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	beq	.L308
	ldrh	r2, [fp, #-52]
	ldr	r3, [fp, #-16]
	asr	r2, r2, r3
	ldr	r3, [fp, #-76]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-40]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldrh	r2, [fp, #-50]
	ldr	r3, [fp, #-16]
	asr	r2, r2, r3
	ldr	r3, [fp, #-76]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-40]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	b	.L309
.L308:
	mvn	r3, #0
	strb	r3, [fp, #-54]
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-12]
	cmp	r2, r3
	bne	.L310
	ldr	r3, [fp, #-68]
	and	r3, r3, #7
	mov	r2, #1
	lsl	r3, r2, r3
	and	r3, r3, #255
	rsb	r3, r3, #0
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-54]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	strb	r3, [fp, #-54]
.L310:
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bne	.L311
	ldr	r3, [fp, #-72]
	add	r3, r3, #1
	and	r3, r3, #7
	mov	r2, #1
	lsl	r3, r2, r3
	and	r3, r3, #255
	sub	r3, r3, #1
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-54]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	strb	r3, [fp, #-54]
.L311:
	ldr	r3, [fp, #-76]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-40]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3]
	ldrsb	r3, [fp, #-54]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrh	r2, [fp, #-52]
	ldr	r3, [fp, #-16]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-54]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-76]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-40]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-76]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-40]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3, #1]
	ldrsb	r3, [fp, #-54]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrh	r2, [fp, #-50]
	ldr	r3, [fp, #-16]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-54]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-76]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-40]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
.L309:
	ldrh	r3, [fp, #-52]
	lsr	r3, r3, #8
	strh	r3, [fp, #-52]	@ movhi
	ldrh	r3, [fp, #-50]
	lsr	r3, r3, #8
	strh	r3, [fp, #-50]	@ movhi
	ldr	r3, [fp, #-44]
	add	r3, r3, #1
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-40]
	add	r3, r3, #1
	str	r3, [fp, #-40]
.L306:
	ldr	r2, [fp, #-40]
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	bls	.L312
	b	.L313
.L305:
	ldr	r3, [fp, #-68]
	add	r3, r3, #1
	and	r3, r3, #7
	rsb	r3, r3, #8
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-68]
	lsr	r3, r3, #3
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-72]
	lsr	r3, r3, #3
	str	r3, [fp, #-20]
	mov	r3, #0
	strh	r3, [fp, #-48]	@ movhi
	mov	r3, #0
	strh	r3, [fp, #-46]	@ movhi
	mov	r3, #0
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-32]
	b	.L314
.L320:
	ldr	r3, [fp, #-64]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	ldr	r2, [fp, #-36]
	cmp	r2, r3
	bcs	.L315
	ldr	r3, [fp, #-64]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-36]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	mov	r0, r3
	bl	word_reverse_bits
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r3, [fp, #-48]	@ movhi
	orr	r3, r2, r3
	strh	r3, [fp, #-48]	@ movhi
	ldr	r3, [fp, #-64]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-36]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	mov	r0, r3
	bl	word_reverse_bits
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r3, [fp, #-46]	@ movhi
	orr	r3, r2, r3
	strh	r3, [fp, #-46]	@ movhi
.L315:
	ldr	r2, [fp, #-32]
	ldr	r3, [fp, #-24]
	cmp	r2, r3
	beq	.L316
	ldr	r2, [fp, #-32]
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	beq	.L316
	ldrh	r2, [fp, #-48]
	ldr	r3, [fp, #-28]
	asr	r2, r2, r3
	ldr	r3, [fp, #-76]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldrh	r2, [fp, #-46]
	ldr	r3, [fp, #-28]
	asr	r2, r2, r3
	ldr	r3, [fp, #-76]
	ldr	r1, [r3, #12]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #1
	add	r3, r1, r3
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
	b	.L317
.L316:
	mvn	r3, #0
	strb	r3, [fp, #-53]
	ldr	r2, [fp, #-32]
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	bne	.L318
	ldr	r3, [fp, #-72]
	and	r3, r3, #7
	mov	r2, #1
	lsl	r3, r2, r3
	and	r3, r3, #255
	rsb	r3, r3, #0
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-53]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	strb	r3, [fp, #-53]
.L318:
	ldr	r2, [fp, #-32]
	ldr	r3, [fp, #-24]
	cmp	r2, r3
	bne	.L319
	ldr	r3, [fp, #-68]
	add	r3, r3, #1
	and	r3, r3, #7
	mov	r2, #1
	lsl	r3, r2, r3
	and	r3, r3, #255
	sub	r3, r3, #1
	and	r3, r3, #255
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-53]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	strb	r3, [fp, #-53]
.L319:
	ldr	r3, [fp, #-76]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3]
	ldrsb	r3, [fp, #-53]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrh	r2, [fp, #-48]
	ldr	r3, [fp, #-28]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-53]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-76]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3]
	ldr	r3, [fp, #-76]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r2, [r3, #1]
	ldrsb	r3, [fp, #-53]
	mvn	r3, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r1, r3, #24
	ldrh	r2, [fp, #-46]
	ldr	r3, [fp, #-28]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrsb	r3, [fp, #-53]
	and	r3, r3, r2
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldr	r3, [fp, #-76]
	ldr	r0, [r3, #12]
	ldr	r3, [fp, #-32]
	lsl	r3, r3, #1
	add	r3, r0, r3
	orr	r2, r1, r2
	lsl	r2, r2, #24
	asr	r2, r2, #24
	strb	r2, [r3, #1]
.L317:
	ldrh	r3, [fp, #-48]	@ movhi
	lsl	r3, r3, #8
	strh	r3, [fp, #-48]	@ movhi
	ldrh	r3, [fp, #-46]	@ movhi
	lsl	r3, r3, #8
	strh	r3, [fp, #-46]	@ movhi
	ldr	r3, [fp, #-36]
	add	r3, r3, #1
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-32]
	sub	r3, r3, #1
	str	r3, [fp, #-32]
.L314:
	ldr	r2, [fp, #-32]
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	bge	.L320
.L313:
	ldr	r0, [fp, #-76]
	bl	vec4state_clear_padding_bits
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	vec4state_bitselect_set, .-vec4state_bitselect_set
	.section	.rodata
	.align	2
.LC8:
	.ascii	"FATAL: vec4state_to_real(): impossible double float"
	.ascii	" word order?!\012\000"
	.text
	.align	2
	.global	vec4state_to_real
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_to_real, %function
vec4state_to_real:
	@ args = 0, pretend = 0, frame = 96
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, fp, lr}
	add	fp, sp, #28
	sub	sp, sp, #96
	str	r0, [fp, #-72]
	ldr	r3, [fp, #-72]
	ldr	r3, [r3, #8]
	cmp	r3, #0
	beq	.L322
	ldr	r3, [fp, #-72]
	ldr	r3, [r3, #4]
	sub	r3, r3, #1
	mov	r1, r3
	ldr	r0, [fp, #-72]
	bl	vec4state_bit_test
	mov	r3, r0
	cmp	r3, #1
	bne	.L322
	mov	r3, #1
	b	.L323
.L322:
	mov	r3, #0
.L323:
	str	r3, [fp, #-56]
	ldr	r0, [fp, #-72]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	beq	.L324
	mov	r2, #0
	mov	r3, #0
	b	.L325
.L324:
	ldr	r3, [fp, #-72]
	ldr	r3, [r3, #4]
	sub	r3, r3, #1
	str	r3, [fp, #-68]
	b	.L326
.L334:
	ldr	r3, [fp, #-68]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	str	r3, [fp, #-52]
	ldr	r3, [fp, #-68]
	rsbs	r1, r3, #0
	and	r2, r3, #7
	and	r3, r1, #7
	rsbpl	r2, r3, #0
	str	r2, [fp, #-48]
	ldr	r3, [fp, #-72]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	mov	r2, r3
	ldr	r3, [fp, #-48]
	asr	r3, r2, r3
	and	r2, r3, #1
	ldr	r3, [fp, #-56]
	cmp	r3, r2
	beq	.L327
	mov	r2, #0
	ldr	r3, .L335
	str	r2, [fp, #-44]
	str	r3, [fp, #-40]
	mov	r2, #0
	mov	r3, #0
	str	r2, [fp, #-36]
	str	r3, [fp, #-32]
	ldr	r3, [fp, #-68]
	rsbs	r1, r3, #0
	and	r2, r3, #7
	and	r3, r1, #7
	rsbpl	r2, r3, #0
	rsb	r3, r2, #63
	str	r3, [fp, #-60]
	mov	r3, #0
	str	r3, [fp, #-64]
	b	.L328
.L330:
	ldr	r2, [fp, #-64]
	ldr	r3, [fp, #-52]
	cmp	r3, r2
	bcc	.L329
	ldr	r3, [fp, #-60]
	cmp	r3, #63
	bhi	.L329
	sub	r5, fp, #36
	ldmia	r5, {r4-r5}
	ldr	r3, [fp, #-72]
	ldr	r1, [r3, #12]
	ldr	r2, [fp, #-64]
	ldr	r3, [fp, #-52]
	sub	r3, r3, r2
	lsl	r3, r3, #1
	add	r3, r1, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	and	r2, r3, #255
	mov	r3, #0
	ldr	r1, [fp, #-60]
	sub	ip, r1, #32
	rsb	r0, r1, #32
	lsl	r7, r3, r1
	orr	r7, r7, r2, lsl ip
	orr	r7, r7, r2, lsr r0
	lsl	r6, r2, r1
	orr	r3, r4, r6
	str	r3, [fp, #-84]
	orr	r3, r5, r7
	str	r3, [fp, #-80]
	sub	r4, fp, #84
	ldmia	r4, {r3-r4}
	str	r3, [fp, #-36]
	str	r4, [fp, #-32]
	ldr	r3, [fp, #-60]
	sub	r3, r3, #8
	str	r3, [fp, #-60]
	ldr	r3, [fp, #-64]
	add	r3, r3, #1
	str	r3, [fp, #-64]
.L328:
	ldr	r3, [fp, #-64]
	cmp	r3, #7
	ble	.L330
.L329:
	ldr	r3, [fp, #-56]
	cmp	r3, #0
	beq	.L331
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	rsbs	r2, r2, #0
	rsc	r3, r3, #0
	str	r2, [fp, #-36]
	str	r3, [fp, #-32]
.L331:
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	adds	r1, r2, r2
	str	r1, [fp, #-124]
	adc	r3, r3, r3
	str	r3, [fp, #-120]
	sub	r3, fp, #124
	ldmia	r3, {r2-r3}
	str	r2, [fp, #-36]
	str	r3, [fp, #-32]
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	adds	r1, r2, #2048
	str	r1, [fp, #-92]
	adc	r3, r3, #0
	str	r3, [fp, #-88]
	sub	r4, fp, #92
	ldmia	r4, {r3-r4}
	str	r3, [fp, #-36]
	str	r4, [fp, #-32]
	sub	r1, fp, #36
	ldmia	r1, {r0-r1}
	mov	r2, #0
	mov	r3, #0
	lsr	r2, r0, #12
	orr	r2, r2, r1, lsl #20
	lsr	r3, r1, #12
	str	r2, [fp, #-36]
	str	r3, [fp, #-32]
	sub	r5, fp, #36
	ldmia	r5, {r4-r5}
	ldr	r3, [fp, #-68]
	add	r3, r3, #1020
	add	r3, r3, #3
	mov	r0, r3
	asr	r1, r0, #31
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r0, #20
	mov	r2, #0
	mov	r0, #0
	ldr	r1, .L335+4
	and	r8, r2, r0
	and	r9, r3, r1
	orr	r3, r4, r8
	str	r3, [fp, #-100]
	orr	r3, r5, r9
	str	r3, [fp, #-96]
	sub	r4, fp, #100
	ldmia	r4, {r3-r4}
	str	r3, [fp, #-36]
	str	r4, [fp, #-32]
	sub	r1, fp, #36
	ldmia	r1, {r0-r1}
	ldr	r3, [fp, #-56]
	mov	r4, r3
	asr	r5, r4, #31
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r4, #31
	mov	r2, #0
	orr	ip, r0, r2
	str	ip, [fp, #-108]
	orr	r3, r1, r3
	str	r3, [fp, #-104]
	sub	r4, fp, #108
	ldmia	r4, {r3-r4}
	str	r3, [fp, #-36]
	str	r4, [fp, #-32]
	sub	r3, fp, #44
	ldmia	r3, {r2-r3}
	mov	r0, #0
	ldr	r1, .L335
	cmp	r3, r1
	cmpeq	r2, r0
	beq	.L332
	sub	r3, fp, #44
	ldmia	r3, {r2-r3}
	ldr	r0, .L335
	mov	r1, #0
	cmp	r3, r1
	cmpeq	r2, r0
	bne	.L333
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	str	r3, [fp, #-116]
	str	r2, [fp, #-112]
	sub	r4, fp, #116
	ldmia	r4, {r3-r4}
	str	r3, [fp, #-36]
	str	r4, [fp, #-32]
	b	.L332
.L333:
	ldr	r3, .L335+8
	ldr	r3, [r3]
	mov	r2, #65
	mov	r1, #1
	ldr	r0, .L335+12
	bl	fwrite
	bl	abort
.L332:
	sub	r3, fp, #36
	ldmia	r3, {r2-r3}
	b	.L325
.L327:
	ldr	r3, [fp, #-68]
	sub	r3, r3, #1
	str	r3, [fp, #-68]
.L326:
	ldr	r3, [fp, #-68]
	cmp	r3, #0
	bge	.L334
	mov	r2, #0
	mov	r3, #0
.L325:
	mov	r0, r2
	mov	r1, r3
	sub	sp, fp, #28
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, fp, pc}
.L336:
	.align	2
.L335:
	.word	1072693248
	.word	2146435072
	.word	stderr
	.word	.LC8
	.size	vec4state_to_real, .-vec4state_to_real
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	count_vpiBinOctHexStr_digits, %function
count_vpiBinOctHexStr_digits:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L338
.L342:
	ldr	r3, [fp, #-16]
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r3, r3, #48
	cmp	r3, #74
	ldrls	pc, [pc, r3, asl #2]
	b	.L339
.L341:
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L340
	.word	.L339
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L340
	.word	.L339
	.word	.L340
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L340
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L339
	.word	.L340
	.word	.L339
	.word	.L340
.L340:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
	nop
.L339:
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
.L338:
	ldr	r3, [fp, #-16]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L342
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	count_vpiBinOctHexStr_digits, .-count_vpiBinOctHexStr_digits
	.section	.rodata
	.align	2
.LC9:
	.ascii	"ERROR: scan_size_and_base(): invalid size field (ov"
	.ascii	"erflow or zero?)\012\000"
	.align	2
.LC10:
	.ascii	"ERROR: scan_size_and_base(): no base-'tick found!\012"
	.ascii	"\000"
	.align	2
.LC11:
	.ascii	"ERROR: scan_size_and_base(): invalid base character"
	.ascii	" 0x%02x!\012\000"
	.align	2
.LC12:
	.ascii	"ERROR: scan_size_and_base(): base character not mat"
	.ascii	"ching format!\012\000"
	.align	2
.LC13:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	scan_size_and_base, %function
scan_size_and_base:
	@ args = 4, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #40
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-32]
	str	r3, [fp, #-36]
	ldr	r3, [fp, #4]
	str	r3, [fp, #-40]
	ldr	r3, .L375
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r3, [fp, #-24]
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-24]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #47
	bls	.L345
	ldr	r3, [fp, #-24]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #57
	bls	.L346
.L345:
	ldr	r3, [fp, #-32]
	mov	r2, #0
	str	r2, [r3]
	b	.L347
.L346:
	sub	r3, fp, #12
	mov	r2, #10
	mov	r1, r3
	ldr	r0, [fp, #-24]
	bl	strtoul
	mov	r2, r0
	ldr	r3, [fp, #-32]
	str	r2, [r3]
	ldr	r3, [fp, #-32]
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L348
	ldr	r3, [fp, #-32]
	ldr	r3, [r3]
	cmn	r3, #1
	bne	.L352
.L348:
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L350
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmn	r3, #1
	beq	.L350
	ldr	r3, .L375+4
	ldr	r3, [r3]
	mov	r2, #68
	mov	r1, #1
	ldr	r0, .L375+8
	bl	fwrite
	mov	r3, #0
	b	.L373
.L350:
	ldr	r3, [fp, #-28]
	mov	r2, #3
	str	r2, [r3]
	ldr	r3, [fp, #-32]
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-36]
	mov	r2, #4
	str	r2, [r3]
	ldr	r3, [fp, #-40]
	mov	r2, #1
	str	r2, [r3]
	ldr	r3, [fp, #-24]
	b	.L373
.L353:
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
.L352:
	ldr	r3, [fp, #-12]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #32
	beq	.L353
	ldr	r3, [fp, #-12]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #9
	beq	.L353
.L347:
	ldr	r3, [fp, #-12]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #39
	beq	.L354
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L355
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmn	r3, #1
	beq	.L355
	ldr	r3, .L375+4
	ldr	r3, [r3]
	mov	r2, #50
	mov	r1, #1
	ldr	r0, .L375+12
	bl	fwrite
	mov	r3, #0
	b	.L373
.L355:
	ldr	r3, [fp, #-28]
	mov	r2, #3
	str	r2, [r3]
	ldr	r3, [fp, #-32]
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-36]
	mov	r2, #4
	str	r2, [r3]
	ldr	r3, [fp, #-40]
	mov	r2, #1
	str	r2, [r3]
	ldr	r3, [fp, #-24]
	b	.L373
.L354:
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-12]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #115
	beq	.L356
	ldr	r3, [fp, #-12]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #83
	bne	.L357
.L356:
	ldr	r3, [fp, #-40]
	mov	r2, #1
	str	r2, [r3]
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
	b	.L358
.L357:
	ldr	r3, [fp, #-40]
	mov	r2, #0
	str	r2, [r3]
.L358:
	ldr	r3, [fp, #-12]
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r0, r3
	bl	tolower
	mov	r3, r0
	strb	r3, [fp, #-13]
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmn	r3, #1
	bne	.L359
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #98
	bne	.L360
	ldr	r3, [fp, #-28]
	mov	r2, #1
	str	r2, [r3]
	b	.L359
.L360:
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #111
	bne	.L361
	ldr	r3, [fp, #-28]
	mov	r2, #2
	str	r2, [r3]
	b	.L359
.L361:
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #104
	bne	.L362
	ldr	r3, [fp, #-28]
	mov	r2, #4
	str	r2, [r3]
	b	.L359
.L362:
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #100
	bne	.L363
	ldr	r3, [fp, #-28]
	mov	r2, #3
	str	r2, [r3]
	b	.L359
.L363:
	ldr	r3, .L375+4
	ldr	r3, [r3]
	ldrb	r2, [fp, #-13]	@ zero_extendqisi2
	ldr	r1, .L375+16
	mov	r0, r3
	bl	fprintf
	mov	r3, #0
	b	.L373
.L359:
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #98
	bne	.L364
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L365
.L364:
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #111
	bne	.L366
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L365
.L366:
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #104
	bne	.L367
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmp	r3, #4
	bne	.L365
.L367:
	ldrb	r3, [fp, #-13]	@ zero_extendqisi2
	cmp	r3, #100
	bne	.L368
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L368
.L365:
	ldr	r3, .L375+4
	ldr	r3, [r3]
	mov	r2, #65
	mov	r1, #1
	ldr	r0, .L375+20
	bl	fwrite
	mov	r3, #0
	b	.L373
.L368:
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L369
	ldr	r3, [fp, #-28]
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L370
	mov	r3, #3
	b	.L372
.L370:
	mov	r3, #4
	b	.L372
.L369:
	mov	r3, #1
.L372:
	ldr	r2, [fp, #-36]
	str	r3, [r2]
	ldr	r3, [fp, #-12]
.L373:
	ldr	r2, .L375
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L374
	bl	__stack_chk_fail
.L374:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L376:
	.align	2
.L375:
	.word	.LC13
	.word	stderr
	.word	.LC9
	.word	.LC10
	.word	.LC11
	.word	.LC12
	.size	scan_size_and_base, .-scan_size_and_base
	.section	.rodata
	.align	2
.LC14:
	.ascii	"ERROR: vec4state_from_vpiBinOctHexStr(): too many d"
	.ascii	"igits for defined size (%u > %ubits)!\012\000"
	.align	2
.LC15:
	.ascii	"ERROR: vec4state_from_vpiBinOctHexStr(): Invalid ch"
	.ascii	"aracter 0x%02x!\012\000"
	.align	2
.LC16:
	.ascii	"FATAL: vec4state_resize failed!\012\000"
	.text
	.align	2
	.global	vec4state_from_vpiBinOctHexStr
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_from_vpiBinOctHexStr, %function
vec4state_from_vpiBinOctHexStr:
	@ args = 0, pretend = 0, frame = 48
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #48
	str	r0, [fp, #-40]
	str	r1, [fp, #-44]
	str	r2, [fp, #-48]
	str	r3, [fp, #-52]
	ldr	r0, [fp, #-40]
	bl	count_vpiBinOctHexStr_digits
	str	r0, [fp, #-16]
	ldr	r2, [fp, #-48]
	ldr	r3, [fp, #-16]
	mul	r3, r2, r3
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	beq	.L378
	ldr	r2, [fp, #-12]
	ldr	r3, [fp, #-44]
	cmp	r2, r3
	bls	.L378
	ldr	r3, .L401
	ldr	r0, [r3]
	ldr	r3, [fp, #-44]
	ldr	r2, [fp, #-12]
	ldr	r1, .L401+4
	bl	fprintf
	mov	r3, #0
	b	.L379
.L378:
	ldr	r1, [fp, #-52]
	ldr	r0, [fp, #-12]
	bl	vec4state_new
	str	r0, [fp, #-8]
	mov	r3, #0
	str	r3, [fp, #-32]
	ldr	r0, [fp, #-40]
	bl	strlen
	mov	r3, r0
	sub	r3, r3, #1
	str	r3, [fp, #-28]
	b	.L380
.L397:
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #95
	beq	.L400
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #120
	beq	.L383
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #88
	bne	.L384
.L383:
	mov	r3, #0
	str	r3, [fp, #-24]
	b	.L385
.L386:
	ldr	r3, [fp, #-32]
	add	r2, r3, #1
	str	r2, [fp, #-32]
	mov	r2, #3
	mov	r1, r3
	ldr	r0, [fp, #-8]
	bl	vec4state_bit_set
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	str	r3, [fp, #-24]
.L385:
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-48]
	cmp	r2, r3
	blt	.L386
	b	.L382
.L384:
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #122
	beq	.L387
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #90
	beq	.L387
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #63
	bne	.L388
.L387:
	mov	r3, #0
	str	r3, [fp, #-24]
	b	.L389
.L390:
	ldr	r3, [fp, #-32]
	add	r2, r3, #1
	str	r2, [fp, #-32]
	mov	r2, #2
	mov	r1, r3
	ldr	r0, [fp, #-8]
	bl	vec4state_bit_set
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	str	r3, [fp, #-24]
.L389:
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-48]
	cmp	r2, r3
	blt	.L390
	b	.L382
.L388:
	mvn	r3, #-2147483648
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #47
	bls	.L391
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #57
	bhi	.L391
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r3, r3, #48
	str	r3, [fp, #-20]
	b	.L392
.L391:
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #96
	bls	.L393
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #102
	bhi	.L393
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r3, r3, #87
	str	r3, [fp, #-20]
	b	.L392
.L393:
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #64
	bls	.L392
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #70
	bhi	.L392
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r3, r3, #55
	str	r3, [fp, #-20]
.L392:
	mov	r2, #1
	ldr	r3, [fp, #-48]
	lsl	r3, r2, r3
	ldr	r2, [fp, #-20]
	cmp	r2, r3
	blt	.L394
	ldr	r3, .L401
	ldr	r0, [r3]
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-40]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r2, r3
	ldr	r1, .L401+8
	bl	fprintf
.L394:
	mov	r3, #0
	str	r3, [fp, #-24]
	b	.L395
.L396:
	ldr	r2, [fp, #-20]
	ldr	r3, [fp, #-24]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #1
	strb	r3, [fp, #-33]
	ldr	r3, [fp, #-32]
	add	r2, r3, #1
	str	r2, [fp, #-32]
	mov	r1, r3
	ldrsb	r3, [fp, #-33]
	mov	r2, r3
	ldr	r0, [fp, #-8]
	bl	vec4state_bit_set
	ldr	r3, [fp, #-24]
	add	r3, r3, #1
	str	r3, [fp, #-24]
.L395:
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-48]
	cmp	r2, r3
	blt	.L396
	b	.L382
.L400:
	nop
.L382:
	ldr	r3, [fp, #-28]
	sub	r3, r3, #1
	str	r3, [fp, #-28]
.L380:
	ldr	r3, [fp, #-28]
	cmp	r3, #0
	bge	.L397
	ldr	r3, [fp, #-44]
	cmp	r3, #0
	bne	.L398
	ldr	r3, [fp, #-12]
	str	r3, [fp, #-44]
.L398:
	ldr	r1, [fp, #-44]
	ldr	r0, [fp, #-8]
	bl	vec4state_resize
	mov	r3, r0
	cmp	r3, #0
	bne	.L399
	ldr	r3, .L401
	ldr	r3, [r3]
	mov	r2, #32
	mov	r1, #1
	ldr	r0, .L401+12
	bl	fwrite
	bl	abort
.L399:
	ldr	r3, [fp, #-8]
.L379:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L402:
	.align	2
.L401:
	.word	stderr
	.word	.LC14
	.word	.LC15
	.word	.LC16
	.size	vec4state_from_vpiBinOctHexStr, .-vec4state_from_vpiBinOctHexStr
	.section	.rodata
	.align	2
.LC17:
	.ascii	"ERROR: vec4state_from_vpiDecStr(): invalid characte"
	.ascii	"r in decimal digit string: 0x%02x\012\000"
	.align	2
.LC18:
	.ascii	"ERROR: vec4state_from_vpiDecStr(): number '%s' too "
	.ascii	"large to fit in %zd bits!\012\000"
	.align	2
.LC19:
	.ascii	"WARNING: vec4state_from_vpiDecStr(): integer > 32bi"
	.ascii	"t (actually %d, use %ubits).\012   IEEE1364-2005 is"
	.ascii	" ambiguous about the wrap-around of unsized integer"
	.ascii	"s:\012   In sec. 3.9 an implementation-dependend mi"
	.ascii	"nimum size of 32bit is specified,\012   but in sec."
	.ascii	" 4.1.3, the examples assume a fixed 32bit-wrap-arou"
	.ascii	"nd.\012   We follow sec. 3.9 and won't limit intege"
	.ascii	"rs to 32bits, to avoid unexpected wraparound effect"
	.ascii	"s.\012   Please keep in mind that other Verilog Too"
	.ascii	"ls may expose different behaviour.\012\000"
	.text
	.align	2
	.global	vec4state_from_vpiDecStr
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_from_vpiDecStr, %function
vec4state_from_vpiDecStr:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #32
	str	r0, [fp, #-24]
	str	r1, [fp, #-28]
	str	r2, [fp, #-32]
	ldr	r0, [fp, #-24]
	bl	strlen
	mov	r3, r0
	lsl	r3, r3, #2
	ldr	r1, [fp, #-32]
	mov	r0, r3
	bl	vec4state_new
	str	r0, [fp, #-8]
	mov	r1, #0
	ldr	r0, [fp, #-8]
	bl	vec4state_set
	mov	r3, #0
	str	r3, [fp, #-16]
	b	.L404
.L414:
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #95
	beq	.L424
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #47
	bls	.L407
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #57
	bhi	.L407
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r3, r3, #48
	and	r3, r3, #255
	strb	r3, [fp, #-17]
	ldr	r2, [fp, #-8]
	mov	r1, #10
	ldr	r0, [fp, #-8]
	bl	vec4state_mul_unsigned_word
	ldrb	r3, [fp, #-17]	@ zero_extendqisi2
	ldr	r2, [fp, #-8]
	mov	r1, r3
	ldr	r0, [fp, #-8]
	bl	vec4state_add_unsigned_word
	b	.L406
.L407:
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #120
	beq	.L408
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #88
	bne	.L409
.L408:
	mov	r1, #3
	ldr	r0, [fp, #-8]
	bl	vec4state_set
	b	.L410
.L409:
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #122
	beq	.L411
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #90
	beq	.L411
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #63
	bne	.L412
.L411:
	mov	r1, #2
	ldr	r0, [fp, #-8]
	bl	vec4state_set
	b	.L410
.L412:
	ldr	r3, .L425
	ldr	r0, [r3]
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-24]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r2, r3
	ldr	r1, .L425+4
	bl	fprintf
	ldr	r0, [fp, #-8]
	bl	vec4state_free
	mov	r3, #0
	b	.L413
.L424:
	nop
.L406:
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
.L404:
	ldr	r0, [fp, #-24]
	bl	strlen
	mov	r2, r0
	ldr	r3, [fp, #-16]
	cmp	r2, r3
	bhi	.L414
.L410:
	ldr	r3, [fp, #-28]
	cmp	r3, #0
	beq	.L415
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	sub	r3, r3, #1
	str	r3, [fp, #-16]
	b	.L416
.L418:
	ldr	r3, [fp, #-16]
	mov	r1, r3
	ldr	r0, [fp, #-8]
	bl	vec4state_bit_test
	mov	r3, r0
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L425
	ldr	r0, [r3]
	ldr	r3, [fp, #-28]
	ldr	r2, [fp, #-24]
	ldr	r1, .L425+8
	bl	fprintf
	ldr	r0, [fp, #-8]
	bl	vec4state_free
	mov	r3, #0
	b	.L413
.L417:
	ldr	r3, [fp, #-16]
	sub	r3, r3, #1
	str	r3, [fp, #-16]
.L416:
	ldr	r3, [fp, #-16]
	ldr	r2, [fp, #-28]
	cmp	r2, r3
	bls	.L418
	ldr	r1, [fp, #-28]
	ldr	r0, [fp, #-8]
	bl	vec4state_resize
	mov	r3, r0
	cmp	r3, #0
	bne	.L419
	ldr	r3, .L425
	ldr	r3, [r3]
	mov	r2, #32
	mov	r1, #1
	ldr	r0, .L425+12
	bl	fwrite
	bl	abort
.L415:
	mov	r3, #32
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	cmp	r3, #31
	bls	.L420
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	sub	r3, r3, #1
	str	r3, [fp, #-16]
	b	.L421
.L423:
	ldr	r3, [fp, #-16]
	mov	r1, r3
	ldr	r0, [fp, #-8]
	bl	vec4state_bit_test
	mov	r3, r0
	cmp	r3, #1
	bne	.L422
	ldr	r3, .L425
	ldr	r0, [r3]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-16]
	ldr	r1, .L425+16
	bl	fprintf
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	str	r3, [fp, #-12]
	b	.L420
.L422:
	ldr	r3, [fp, #-16]
	sub	r3, r3, #1
	str	r3, [fp, #-16]
.L421:
	ldr	r3, [fp, #-16]
	cmp	r3, #31
	bgt	.L423
.L420:
	ldr	r3, [fp, #-12]
	mov	r1, r3
	ldr	r0, [fp, #-8]
	bl	vec4state_resize
	mov	r3, r0
	cmp	r3, #0
	bne	.L419
	ldr	r3, .L425
	ldr	r3, [r3]
	mov	r2, #32
	mov	r1, #1
	ldr	r0, .L425+12
	bl	fwrite
	bl	abort
.L419:
	ldr	r3, [fp, #-8]
.L413:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L426:
	.align	2
.L425:
	.word	stderr
	.word	.LC17
	.word	.LC18
	.word	.LC16
	.word	.LC19
	.size	vec4state_from_vpiDecStr, .-vec4state_from_vpiDecStr
	.section	.rodata
	.align	2
.LC20:
	.ascii	"ERROR: vec4state_from_string(): Failed parsing size"
	.ascii	" and base!\012\000"
	.align	2
.LC21:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	vec4state_from_string
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_from_string, %function
vec4state_from_string:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #40
	str	r0, [fp, #-32]
	str	r1, [fp, #-36]
	ldr	r3, .L434
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	sub	r0, fp, #20
	sub	r2, fp, #24
	sub	r1, fp, #36
	sub	r3, fp, #16
	str	r3, [sp]
	mov	r3, r0
	ldr	r0, [fp, #-32]
	bl	scan_size_and_base
	str	r0, [fp, #-32]
	ldr	r3, [fp, #-32]
	cmp	r3, #0
	bne	.L428
	ldr	r3, .L434+4
	ldr	r3, [r3]
	mov	r2, #62
	mov	r1, #1
	ldr	r0, .L434+8
	bl	fwrite
	mov	r3, #0
	b	.L432
.L428:
	ldr	r3, [fp, #-36]
	cmp	r3, #3
	bne	.L430
	ldr	r3, [fp, #-24]
	ldr	r2, [fp, #-16]
	mov	r1, r3
	ldr	r0, [fp, #-32]
	bl	vec4state_from_vpiDecStr
	str	r0, [fp, #-12]
	b	.L431
.L430:
	ldr	r1, [fp, #-24]
	ldr	r2, [fp, #-20]
	ldr	r3, [fp, #-16]
	ldr	r0, [fp, #-32]
	bl	vec4state_from_vpiBinOctHexStr
	str	r0, [fp, #-12]
.L431:
	ldr	r3, [fp, #-12]
.L432:
	ldr	r2, .L434
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L433
	bl	__stack_chk_fail
.L433:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L435:
	.align	2
.L434:
	.word	.LC21
	.word	stderr
	.word	.LC20
	.size	vec4state_from_string, .-vec4state_from_string
	.section	.rodata
	.align	2
.LC22:
	.ascii	"s\000"
	.align	2
.LC23:
	.ascii	"\000"
	.align	2
.LC24:
	.ascii	"%d'%s%c\000"
	.global	__aeabi_uidiv
	.align	2
.LC25:
	.ascii	"ERROR: vec4state_to_vpiBinOctHexStr(): overflow of "
	.ascii	"size/base field!\012\000"
	.align	2
.LC26:
	.ascii	"FATAL: vec4state_to_vpiBinOctHexStr(): failed to al"
	.ascii	"locate %lu bytes for output string!\012\000"
	.align	2
.LC27:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	vec4state_to_vpiBinOctHexStr
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_to_vpiBinOctHexStr, %function
vec4state_to_vpiBinOctHexStr:
	@ args = 0, pretend = 0, frame = 80
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #88
	str	r0, [fp, #-80]
	str	r1, [fp, #-84]
	ldr	r3, .L468
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r3, [fp, #-84]
	cmp	r3, #4
	beq	.L437
	ldr	r3, [fp, #-84]
	cmp	r3, #2
	bne	.L438
	mov	r3, #111
	b	.L440
.L438:
	mov	r3, #98
	b	.L440
.L437:
	mov	r3, #104
.L440:
	strb	r3, [fp, #-69]
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #4]
	mov	r1, r3
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #8]
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L468+4
	b	.L442
.L441:
	ldr	r3, .L468+8
.L442:
	ldrb	r2, [fp, #-69]	@ zero_extendqisi2
	sub	r0, fp, #24
	str	r2, [sp, #4]
	str	r3, [sp]
	mov	r3, r1
	ldr	r2, .L468+12
	mov	r1, #14
	bl	snprintf
	mov	r3, r0
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-84]
	cmp	r3, #4
	beq	.L443
	ldr	r3, [fp, #-84]
	cmp	r3, #2
	bne	.L444
	mov	r3, #3
	b	.L446
.L444:
	mov	r3, #1
	b	.L446
.L443:
	mov	r3, #4
.L446:
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-80]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-40]
	add	r3, r2, r3
	sub	r3, r3, #1
	ldr	r2, [fp, #-40]
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_uidiv
	mov	r3, r0
	str	r3, [fp, #-36]
	mov	r3, #0
	str	r3, [fp, #-68]
	ldr	r3, [fp, #-44]
	cmp	r3, #12
	bls	.L447
	ldr	r3, .L468+16
	ldr	r3, [r3]
	mov	r2, #68
	mov	r1, #1
	ldr	r0, .L468+20
	bl	fwrite
	mov	r3, #0
	b	.L465
.L447:
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-36]
	add	r3, r2, r3
	add	r3, r3, #1
	mov	r0, r3
	bl	malloc
	mov	r3, r0
	str	r3, [fp, #-32]
	ldr	r3, [fp, #-32]
	cmp	r3, #0
	bne	.L449
	ldr	r3, .L468+16
	ldr	r0, [r3]
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-36]
	add	r3, r2, r3
	add	r3, r3, #1
	mov	r2, r3
	ldr	r1, .L468+24
	bl	fprintf
	bl	abort
.L449:
	sub	r3, fp, #24
	ldr	r2, [fp, #-44]
	mov	r1, r3
	ldr	r0, [fp, #-32]
	bl	strncpy
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-36]
	add	r3, r2, r3
	ldr	r2, [fp, #-32]
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3]
	ldr	r2, [fp, #-44]
	ldr	r3, [fp, #-36]
	add	r3, r2, r3
	sub	r3, r3, #1
	str	r3, [fp, #-64]
	b	.L450
.L464:
	mov	r3, #0
	str	r3, [fp, #-56]
	mov	r3, #0
	str	r3, [fp, #-52]
	mov	r3, #0
	str	r3, [fp, #-48]
	mov	r3, #0
	str	r3, [fp, #-60]
	b	.L451
.L457:
	ldr	r3, [fp, #-68]
	mov	r1, r3
	ldr	r0, [fp, #-80]
	bl	vec4state_bit_test
	str	r0, [fp, #-28]
	ldr	r3, [fp, #-28]
	cmp	r3, #1
	bne	.L452
	mov	r2, #1
	ldr	r3, [fp, #-60]
	lsl	r3, r2, r3
	ldr	r2, [fp, #-48]
	orr	r3, r2, r3
	str	r3, [fp, #-48]
	b	.L453
.L452:
	ldr	r3, [fp, #-28]
	cmp	r3, #3
	bne	.L454
	ldr	r3, [fp, #-56]
	add	r3, r3, #1
	str	r3, [fp, #-56]
	b	.L453
.L454:
	ldr	r3, [fp, #-28]
	cmp	r3, #2
	bne	.L453
	ldr	r3, [fp, #-52]
	add	r3, r3, #1
	str	r3, [fp, #-52]
.L453:
	ldr	r3, [fp, #-68]
	add	r3, r3, #1
	str	r3, [fp, #-68]
	ldr	r2, [fp, #-68]
	ldr	r3, [fp, #-80]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	bcs	.L467
	ldr	r3, [fp, #-60]
	add	r3, r3, #1
	str	r3, [fp, #-60]
.L451:
	ldr	r2, [fp, #-60]
	ldr	r3, [fp, #-40]
	cmp	r2, r3
	blt	.L457
	b	.L456
.L467:
	nop
.L456:
	ldr	r2, [fp, #-56]
	ldr	r3, [fp, #-40]
	cmp	r2, r3
	bne	.L458
	ldr	r3, [fp, #-64]
	ldr	r2, [fp, #-32]
	add	r3, r2, r3
	mov	r2, #120
	strb	r2, [r3]
	b	.L459
.L458:
	ldr	r3, [fp, #-56]
	cmp	r3, #0
	beq	.L460
	ldr	r3, [fp, #-64]
	ldr	r2, [fp, #-32]
	add	r3, r2, r3
	mov	r2, #88
	strb	r2, [r3]
	b	.L459
.L460:
	ldr	r2, [fp, #-52]
	ldr	r3, [fp, #-40]
	cmp	r2, r3
	bne	.L461
	ldr	r3, [fp, #-64]
	ldr	r2, [fp, #-32]
	add	r3, r2, r3
	mov	r2, #122
	strb	r2, [r3]
	b	.L459
.L461:
	ldr	r3, [fp, #-52]
	cmp	r3, #0
	beq	.L462
	ldr	r3, [fp, #-64]
	ldr	r2, [fp, #-32]
	add	r3, r2, r3
	mov	r2, #90
	strb	r2, [r3]
	b	.L459
.L462:
	ldr	r3, [fp, #-48]
	cmp	r3, #9
	bgt	.L463
	ldr	r3, [fp, #-48]
	and	r2, r3, #255
	ldr	r3, [fp, #-64]
	ldr	r1, [fp, #-32]
	add	r3, r1, r3
	add	r2, r2, #48
	and	r2, r2, #255
	strb	r2, [r3]
	b	.L459
.L463:
	ldr	r3, [fp, #-48]
	and	r2, r3, #255
	ldr	r3, [fp, #-64]
	ldr	r1, [fp, #-32]
	add	r3, r1, r3
	add	r2, r2, #87
	and	r2, r2, #255
	strb	r2, [r3]
.L459:
	ldr	r3, [fp, #-64]
	sub	r3, r3, #1
	str	r3, [fp, #-64]
.L450:
	ldr	r3, [fp, #-64]
	ldr	r2, [fp, #-44]
	cmp	r2, r3
	bls	.L464
	ldr	r3, [fp, #-32]
.L465:
	ldr	r2, .L468
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L466
	bl	__stack_chk_fail
.L466:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L469:
	.align	2
.L468:
	.word	.LC27
	.word	.LC22
	.word	.LC23
	.word	.LC24
	.word	stderr
	.word	.LC25
	.word	.LC26
	.size	vec4state_to_vpiBinOctHexStr, .-vec4state_to_vpiBinOctHexStr
	.section	.rodata
	.align	2
.LC28:
	.ascii	"%d'%sd\000"
	.text
	.align	2
	.global	vec4state_to_vpiDecStr
	.syntax unified
	.arm
	.fpu softvfp
	.type	vec4state_to_vpiDecStr, %function
vec4state_to_vpiDecStr:
	@ args = 0, pretend = 0, frame = 48
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #56
	str	r0, [fp, #-48]
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #4]
	mov	r1, #0
	mov	r0, r3
	bl	vec4state_new
	str	r0, [fp, #-28]
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #4]
	lsr	r3, r3, #1
	add	r3, r3, #15
	str	r3, [fp, #-24]
	ldr	r0, [fp, #-24]
	bl	malloc
	mov	r3, r0
	str	r3, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #8]
	cmp	r3, #0
	beq	.L471
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #4]
	sub	r3, r3, #1
	mov	r1, r3
	ldr	r0, [fp, #-48]
	bl	vec4state_bit_test
	mov	r3, r0
	cmp	r3, #1
	bne	.L471
	ldr	r2, [fp, #-28]
	ldr	r1, [fp, #-48]
	ldr	r0, .L484
	bl	vec4state_sub
	ldr	r3, [fp, #-36]
	add	r2, r3, #1
	str	r2, [fp, #-36]
	mov	r2, r3
	ldr	r3, [fp, #-20]
	add	r3, r3, r2
	mov	r2, #45
	strb	r2, [r3]
	b	.L472
.L471:
	ldr	r1, [fp, #-28]
	ldr	r0, [fp, #-48]
	bl	vec4state_copy
.L472:
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #4]
	cmp	r3, #32
	bne	.L473
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #8]
	cmp	r3, #0
	bne	.L474
.L473:
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-20]
	add	r0, r2, r3
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-24]
	sub	r1, r2, r3
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #4]
	mov	r2, r3
	ldr	r3, [fp, #-48]
	ldr	r3, [r3, #8]
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L484+4
	b	.L476
.L475:
	ldr	r3, .L484+8
.L476:
	str	r3, [sp]
	mov	r3, r2
	ldr	r2, .L484+12
	bl	snprintf
	mov	r2, r0
	ldr	r3, [fp, #-36]
	add	r3, r3, r2
	str	r3, [fp, #-36]
.L474:
	ldr	r0, [fp, #-48]
	bl	vec4state_any_bit_is_X_or_Z
	mov	r3, r0
	cmp	r3, #0
	beq	.L477
	ldr	r3, [fp, #-36]
	add	r2, r3, #1
	str	r2, [fp, #-36]
	mov	r2, r3
	ldr	r3, [fp, #-20]
	add	r3, r3, r2
	mov	r2, #120
	strb	r2, [r3]
	b	.L478
.L477:
	ldr	r3, [fp, #-36]
	str	r3, [fp, #-16]
.L480:
	ldr	r2, [fp, #-28]
	mov	r1, #10
	ldr	r0, [fp, #-28]
	bl	vec4state_div_unsigned_word
	mov	r3, r0
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-12]
	and	r2, r3, #255
	ldr	r3, [fp, #-36]
	add	r1, r3, #1
	str	r1, [fp, #-36]
	mov	r1, r3
	ldr	r3, [fp, #-20]
	add	r3, r3, r1
	add	r2, r2, #48
	and	r2, r2, #255
	strb	r2, [r3]
	ldr	r1, .L484
	ldr	r0, [fp, #-28]
	bl	vec4state_cmp
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	beq	.L479
	ldr	r3, [fp, #-8]
	cmp	r3, #3
	beq	.L479
	ldr	r3, [fp, #-8]
	cmp	r3, #2
	beq	.L479
	b	.L480
.L479:
	mov	r3, #0
	str	r3, [fp, #-32]
	b	.L481
.L482:
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-32]
	add	r3, r2, r3
	mov	r2, r3
	ldr	r3, [fp, #-20]
	add	r3, r3, r2
	ldrb	r3, [r3]
	strb	r3, [fp, #-37]
	ldr	r2, [fp, #-36]
	ldr	r3, [fp, #-32]
	sub	r3, r2, r3
	sub	r3, r3, #1
	ldr	r2, [fp, #-20]
	add	r2, r2, r3
	ldr	r1, [fp, #-16]
	ldr	r3, [fp, #-32]
	add	r3, r1, r3
	mov	r1, r3
	ldr	r3, [fp, #-20]
	add	r3, r3, r1
	ldrb	r2, [r2]	@ zero_extendqisi2
	strb	r2, [r3]
	ldr	r2, [fp, #-36]
	ldr	r3, [fp, #-32]
	sub	r3, r2, r3
	sub	r3, r3, #1
	ldr	r2, [fp, #-20]
	add	r3, r2, r3
	ldrb	r2, [fp, #-37]
	strb	r2, [r3]
	ldr	r3, [fp, #-32]
	add	r3, r3, #1
	str	r3, [fp, #-32]
.L481:
	ldr	r2, [fp, #-36]
	ldr	r3, [fp, #-16]
	sub	r3, r2, r3
	lsr	r2, r3, #31
	add	r3, r2, r3
	asr	r3, r3, #1
	mov	r2, r3
	ldr	r3, [fp, #-32]
	cmp	r3, r2
	blt	.L482
.L478:
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-20]
	add	r3, r2, r3
	mov	r2, #0
	strb	r2, [r3]
	ldr	r3, [fp, #-36]
	add	r3, r3, #1
	mov	r1, r3
	ldr	r0, [fp, #-20]
	bl	realloc
	str	r0, [fp, #-20]
	ldr	r0, [fp, #-28]
	bl	vec4state_free
	ldr	r3, [fp, #-20]
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L485:
	.align	2
.L484:
	.word	vec4state_const_zero
	.word	.LC22
	.word	.LC23
	.word	.LC28
	.size	vec4state_to_vpiDecStr, .-vec4state_to_vpiDecStr
	.section	.rodata
	.align	2
.LC29:
	.ascii	"FATAL: padding error (a) (vec4state %s, bits 0x%08x"
	.ascii	", mask 0x%08x)!\012\000"
	.align	2
.LC30:
	.ascii	"FATAL: padding error (b) (vec4state %s, bits 0x%08x"
	.ascii	", mask 0x%08x)!\012\000"
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	__check_padding, %function
__check_padding:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	and	r3, r3, #255
	mov	r1, r3
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	rsb	r3, r3, #0
	and	r3, r3, #7
	mov	r2, #255
	asr	r3, r2, r3
	mvn	r3, r3
	and	r3, r3, r1
	cmp	r3, #0
	beq	.L487
	ldr	r3, .L490
	ldr	r0, [r3]
	ldr	r3, [fp, #-12]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	mov	r1, r3
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	rsb	r3, r3, #0
	and	r3, r3, #7
	mov	r2, #255
	asr	r3, r2, r3
	str	r3, [sp]
	mov	r3, r1
	ldr	r2, [fp, #-8]
	ldr	r1, .L490+4
	bl	fprintf
	bl	abort
.L487:
	ldr	r3, [fp, #-12]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3, #1]
	and	r3, r3, #255
	mov	r1, r3
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	rsb	r3, r3, #0
	and	r3, r3, #7
	mov	r2, #255
	asr	r3, r2, r3
	mvn	r3, r3
	and	r3, r3, r1
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L490
	ldr	r0, [r3]
	ldr	r3, [fp, #-12]
	ldr	r2, [r3, #12]
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	add	r3, r3, #7
	lsr	r3, r3, #3
	sub	r3, r3, #-2147483647
	lsl	r3, r3, #1
	add	r3, r2, r3
	ldrsb	r3, [r3]
	mov	r1, r3
	ldr	r3, [fp, #-12]
	ldr	r3, [r3, #4]
	rsb	r3, r3, #0
	and	r3, r3, #7
	mov	r2, #255
	asr	r3, r2, r3
	str	r3, [sp]
	mov	r3, r1
	ldr	r2, [fp, #-8]
	ldr	r1, .L490+8
	bl	fprintf
	bl	abort
.L489:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L491:
	.align	2
.L490:
	.word	stderr
	.word	.LC29
	.word	.LC30
	.size	__check_padding, .-__check_padding
	.section	.rodata
	.align	2
.LC31:
	.ascii	"3\000"
	.align	2
.LC32:
	.ascii	"a\000"
	.align	2
.LC33:
	.ascii	"b\000"
	.align	2
.LC34:
	.ascii	"three\000"
	.align	2
.LC35:
	.ascii	"a = %s\012\000"
	.align	2
.LC36:
	.ascii	"b = %s\012\000"
	.align	2
.LC37:
	.ascii	"a = %g\012\000"
	.align	2
.LC38:
	.ascii	"b = %g\012\000"
	.align	2
.LC39:
	.ascii	"vec4state_shift_left(b, 5, c):\012\000"
	.align	2
.LC40:
	.ascii	"c = %s\012\000"
	.align	2
.LC41:
	.ascii	"c\000"
	.align	2
.LC42:
	.ascii	"vec4state_shift_right(b, 5, c, 0):\012\000"
	.align	2
.LC43:
	.ascii	"vec4state_shift_right(b, 5, c, 1):\012\000"
	.align	2
.LC44:
	.ascii	"vec4state_bitwise_binary_and(a, b, c):\012\000"
	.align	2
.LC45:
	.ascii	"vec4state_bitwise_binary_or(a, b, c):\012\000"
	.align	2
.LC46:
	.ascii	"vec4state_bitwise_binary_xor(a, b, c):\012\000"
	.align	2
.LC47:
	.ascii	"vec4state_bitwise_unary_negation(b, c):\012\000"
	.align	2
.LC48:
	.ascii	"vec4state_add(a, b, c):\012\000"
	.align	2
.LC49:
	.ascii	"vec4state_sub(a, b, c):\012\000"
	.align	2
.LC50:
	.ascii	"vec4state_mul_unsigned_word(a, 10, c):\012\000"
	.align	2
.LC51:
	.ascii	"vec4state_mul(a, b, c):\012\000"
	.align	2
.LC52:
	.ascii	"vec4state_div_unsigned_word(b, 2, c):\012\000"
	.align	2
.LC53:
	.ascii	"vec4state_reduction_unary_and(b, c):\012\000"
	.align	2
.LC54:
	.ascii	"vec4state_reduction_unary_or(b, c):\012\000"
	.align	2
.LC55:
	.ascii	"vec4state_reduction_unary_xor(b, c):\012\000"
	.align	2
.LC56:
	.ascii	"vec4state_bitselect_get(b, 0, c, 0):\012\000"
	.align	2
.LC57:
	.ascii	"vec4state_bitselect_get(b, 0, c, 1):\012\000"
	.align	2
.LC58:
	.ascii	"vec4state_bitselect_get(b, 1, c, 0):\012\000"
	.align	2
.LC59:
	.ascii	"vec4state_bitselect_get(b, 1, c, 1):\012\000"
	.align	2
.LC60:
	.ascii	"vec4state_bitselect_set(b, min(1, b->size), max(0, "
	.ascii	"(int) b->size - 7), c):\012\000"
	.align	2
.LC61:
	.ascii	"vec4state_bitselect_set(b, min(3, b->size), max(0, "
	.ascii	"(int) b->size - 7), c):\012\000"
	.align	2
.LC62:
	.ascii	"vec4state_bitselect_set(b, max(0, (int) b->size - 7"
	.ascii	"), min(1, b->size), c):\012\000"
	.align	2
.LC63:
	.ascii	"vec4state_bitselect_set(b, max(0, (int) b->size - 7"
	.ascii	"), min(3, b->size), c):\012\000"
	.align	2
.LC64:
	.ascii	"vec4state_pow(a, three, c):\012\000"
	.align	2
.LC65:
	.ascii	"vec4state_div_unsigned(a, b, c, d):\012\000"
	.align	2
.LC66:
	.ascii	"d = %s\012\000"
	.align	2
.LC67:
	.ascii	"d\000"
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 368
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, fp, lr}
	add	fp, sp, #8
	sub	sp, sp, #372
	str	r0, [fp, #-376]
	str	r1, [fp, #-380]
	ldr	r3, [fp, #-380]
	add	r3, r3, #4
	ldr	r3, [r3]
	mvn	r1, #0
	mov	r0, r3
	bl	vec4state_from_string
	str	r0, [fp, #-368]
	ldr	r3, [fp, #-380]
	add	r3, r3, #8
	ldr	r3, [r3]
	mvn	r1, #0
	mov	r0, r3
	bl	vec4state_from_string
	str	r0, [fp, #-364]
	mvn	r1, #0
	ldr	r0, .L495
	bl	vec4state_from_string
	str	r0, [fp, #-360]
	ldr	r3, [fp, #-368]
	cmp	r3, #0
	beq	.L493
	ldr	r3, [fp, #-364]
	cmp	r3, #0
	beq	.L493
	ldr	r3, [fp, #-360]
	cmp	r3, #0
	beq	.L493
	mov	r1, #1
	ldr	r0, [fp, #-368]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-356]
	mov	r1, #2
	ldr	r0, [fp, #-368]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-352]
	mov	r1, #4
	ldr	r0, [fp, #-368]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-348]
	ldr	r0, [fp, #-368]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-344]
	mov	r1, #1
	ldr	r0, [fp, #-364]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-340]
	mov	r1, #2
	ldr	r0, [fp, #-364]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-336]
	mov	r1, #4
	ldr	r0, [fp, #-364]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-332]
	ldr	r0, [fp, #-364]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-328]
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-360]
	ldr	r0, .L495+4
	bl	__check_padding
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-348]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-332]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-352]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-336]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-344]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-328]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r4, [r3]
	ldr	r0, [fp, #-368]
	bl	vec4state_to_real
	mov	r2, r0
	mov	r3, r1
	ldr	r1, .L495+8
	mov	r0, r4
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r4, [r3]
	ldr	r0, [fp, #-364]
	bl	vec4state_to_real
	mov	r2, r0
	mov	r3, r1
	ldr	r1, .L495+12
	mov	r0, r4
	bl	fprintf
	ldr	r0, [fp, #-352]
	bl	free
	ldr	r0, [fp, #-348]
	bl	free
	ldr	r0, [fp, #-344]
	bl	free
	ldr	r0, [fp, #-336]
	bl	free
	ldr	r0, [fp, #-332]
	bl	free
	ldr	r0, [fp, #-328]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-324]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #31
	mov	r1, #1
	ldr	r0, .L495+16
	bl	fwrite
	ldr	r2, [fp, #-324]
	mov	r1, #5
	ldr	r0, [fp, #-364]
	bl	vec4state_shift_left
	mov	r1, #1
	ldr	r0, [fp, #-324]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-320]
	ldr	r0, [fp, #-324]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-316]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-320]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-316]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-324]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-324]
	bl	vec4state_free
	ldr	r0, [fp, #-320]
	bl	free
	ldr	r0, [fp, #-316]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-312]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #35
	mov	r1, #1
	ldr	r0, .L495+20
	bl	fwrite
	mov	r3, #0
	ldr	r2, [fp, #-312]
	mov	r1, #5
	ldr	r0, [fp, #-364]
	bl	vec4state_shift_right
	mov	r1, #1
	ldr	r0, [fp, #-312]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-308]
	ldr	r0, [fp, #-312]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-304]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-308]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-304]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-312]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-312]
	bl	vec4state_free
	ldr	r0, [fp, #-308]
	bl	free
	ldr	r0, [fp, #-304]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-300]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #35
	mov	r1, #1
	ldr	r0, .L495+24
	bl	fwrite
	mov	r3, #1
	ldr	r2, [fp, #-300]
	mov	r1, #5
	ldr	r0, [fp, #-364]
	bl	vec4state_shift_right
	mov	r1, #1
	ldr	r0, [fp, #-300]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-296]
	ldr	r0, [fp, #-300]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-292]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-296]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-292]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-300]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-300]
	bl	vec4state_free
	ldr	r0, [fp, #-296]
	bl	free
	ldr	r0, [fp, #-292]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	movcs	r0, r2
	movcc	r0, r3
	ldr	r3, [fp, #-368]
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	orr	r3, r2, r3
	mov	r1, r3
	bl	vec4state_new
	str	r0, [fp, #-288]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #39
	mov	r1, #1
	ldr	r0, .L495+28
	bl	fwrite
	ldr	r2, [fp, #-288]
	ldr	r1, [fp, #-364]
	ldr	r0, [fp, #-368]
	bl	vec4state_bitwise_binary_and
	mov	r1, #1
	ldr	r0, [fp, #-288]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-284]
	ldr	r0, [fp, #-288]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-280]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-284]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-280]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-288]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-288]
	bl	vec4state_free
	ldr	r0, [fp, #-284]
	bl	free
	ldr	r0, [fp, #-280]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	movcs	r0, r2
	movcc	r0, r3
	ldr	r3, [fp, #-368]
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	orr	r3, r2, r3
	mov	r1, r3
	bl	vec4state_new
	str	r0, [fp, #-276]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #38
	mov	r1, #1
	ldr	r0, .L495+32
	bl	fwrite
	ldr	r2, [fp, #-276]
	ldr	r1, [fp, #-364]
	ldr	r0, [fp, #-368]
	bl	vec4state_bitwise_binary_or
	mov	r1, #1
	ldr	r0, [fp, #-276]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-272]
	ldr	r0, [fp, #-276]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-268]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-272]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-268]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-276]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-276]
	bl	vec4state_free
	ldr	r0, [fp, #-272]
	bl	free
	ldr	r0, [fp, #-268]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	movcs	r0, r2
	movcc	r0, r3
	ldr	r3, [fp, #-368]
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	orr	r3, r2, r3
	mov	r1, r3
	bl	vec4state_new
	str	r0, [fp, #-264]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #39
	mov	r1, #1
	ldr	r0, .L495+36
	bl	fwrite
	ldr	r2, [fp, #-264]
	ldr	r1, [fp, #-364]
	ldr	r0, [fp, #-368]
	bl	vec4state_bitwise_binary_xor
	mov	r1, #1
	ldr	r0, [fp, #-264]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-260]
	ldr	r0, [fp, #-264]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-256]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-260]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-256]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-264]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-264]
	bl	vec4state_free
	ldr	r0, [fp, #-260]
	bl	free
	ldr	r0, [fp, #-256]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-252]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #40
	mov	r1, #1
	ldr	r0, .L495+40
	bl	fwrite
	ldr	r1, [fp, #-252]
	ldr	r0, [fp, #-364]
	bl	vec4state_bitwise_unary_negation
	mov	r1, #1
	ldr	r0, [fp, #-252]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-248]
	ldr	r0, [fp, #-252]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-244]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-248]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-244]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-252]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-252]
	bl	vec4state_free
	ldr	r0, [fp, #-248]
	bl	free
	ldr	r0, [fp, #-244]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	movcs	r3, r2
	movcc	r3, r3
	add	r0, r3, #1
	ldr	r3, [fp, #-368]
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	orr	r3, r2, r3
	mov	r1, r3
	bl	vec4state_new
	str	r0, [fp, #-240]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #24
	mov	r1, #1
	ldr	r0, .L495+44
	bl	fwrite
	ldr	r2, [fp, #-240]
	ldr	r1, [fp, #-364]
	ldr	r0, [fp, #-368]
	bl	vec4state_add
	mov	r1, #1
	ldr	r0, [fp, #-240]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-236]
	ldr	r0, [fp, #-240]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-232]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-236]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-232]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-240]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-240]
	bl	vec4state_free
	ldr	r0, [fp, #-236]
	bl	free
	ldr	r0, [fp, #-232]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #4]
	cmp	r2, r3
	movcs	r3, r2
	movcc	r3, r3
	add	r0, r3, #1
	ldr	r3, [fp, #-368]
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	orr	r3, r2, r3
	mov	r1, r3
	bl	vec4state_new
	str	r0, [fp, #-228]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #24
	mov	r1, #1
	ldr	r0, .L495+48
	bl	fwrite
	ldr	r2, [fp, #-228]
	ldr	r1, [fp, #-364]
	ldr	r0, [fp, #-368]
	bl	vec4state_sub
	mov	r1, #1
	ldr	r0, [fp, #-228]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-224]
	ldr	r0, [fp, #-228]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-220]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-224]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-220]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-228]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-228]
	bl	vec4state_free
	ldr	r0, [fp, #-224]
	bl	free
	ldr	r0, [fp, #-220]
	bl	free
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #4]
	add	r2, r3, #8
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-216]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #39
	mov	r1, #1
	ldr	r0, .L495+52
	bl	fwrite
	ldr	r2, [fp, #-216]
	mov	r1, #10
	ldr	r0, [fp, #-368]
	bl	vec4state_mul_unsigned_word
	mov	r1, #1
	ldr	r0, [fp, #-216]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-212]
	ldr	r0, [fp, #-216]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-208]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-212]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-208]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-216]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-216]
	bl	vec4state_free
	ldr	r0, [fp, #-212]
	bl	free
	ldr	r0, [fp, #-208]
	bl	free
	ldr	r3, [fp, #-368]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	add	r0, r2, r3
	ldr	r3, [fp, #-368]
	ldr	r2, [r3, #8]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	orr	r3, r2, r3
	mov	r1, r3
	bl	vec4state_new
	str	r0, [fp, #-204]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #24
	mov	r1, #1
	ldr	r0, .L495+56
	bl	fwrite
	ldr	r2, [fp, #-204]
	ldr	r1, [fp, #-364]
	ldr	r0, [fp, #-368]
	bl	vec4state_mul
	mov	r1, #1
	ldr	r0, [fp, #-204]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-200]
	ldr	r0, [fp, #-204]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-196]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-200]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-196]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-204]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-204]
	bl	vec4state_free
	ldr	r0, [fp, #-200]
	bl	free
	ldr	r0, [fp, #-196]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	mov	r1, #0
	mov	r0, r3
	bl	vec4state_new
	str	r0, [fp, #-192]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #38
	mov	r1, #1
	ldr	r0, .L495+60
	bl	fwrite
	ldr	r2, [fp, #-192]
	mov	r1, #2
	ldr	r0, [fp, #-364]
	bl	vec4state_div_unsigned_word
	mov	r1, #1
	ldr	r0, [fp, #-192]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-188]
	ldr	r0, [fp, #-192]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-184]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-188]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-184]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-192]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-192]
	bl	vec4state_free
	ldr	r0, [fp, #-188]
	bl	free
	ldr	r0, [fp, #-184]
	bl	free
	mov	r1, #0
	mov	r0, #1
	bl	vec4state_new
	str	r0, [fp, #-180]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #37
	mov	r1, #1
	ldr	r0, .L495+64
	bl	fwrite
	ldr	r1, [fp, #-180]
	ldr	r0, [fp, #-364]
	bl	vec4state_reduction_unary_and
	mov	r1, #1
	ldr	r0, [fp, #-180]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-176]
	ldr	r0, [fp, #-180]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-172]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-176]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-172]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-180]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-180]
	bl	vec4state_free
	ldr	r0, [fp, #-176]
	bl	free
	ldr	r0, [fp, #-172]
	bl	free
	mov	r1, #0
	mov	r0, #1
	bl	vec4state_new
	str	r0, [fp, #-168]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #36
	mov	r1, #1
	ldr	r0, .L495+68
	bl	fwrite
	ldr	r1, [fp, #-168]
	ldr	r0, [fp, #-364]
	bl	vec4state_reduction_unary_or
	mov	r1, #1
	ldr	r0, [fp, #-168]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-164]
	ldr	r0, [fp, #-168]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-160]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	b	.L496
.L497:
	.align	2
.L495:
	.word	.LC31
	.word	.LC34
	.word	.LC37
	.word	.LC38
	.word	.LC39
	.word	.LC42
	.word	.LC43
	.word	.LC44
	.word	.LC45
	.word	.LC46
	.word	.LC47
	.word	.LC48
	.word	.LC49
	.word	.LC50
	.word	.LC51
	.word	.LC52
	.word	.LC53
	.word	.LC54
	.word	.LC55
	.word	.LC56
	.word	.LC57
	.word	.LC58
	.word	.LC59
	.word	.LC60
	.word	.LC61
	.word	.LC62
	.word	.LC63
	.word	.LC64
	.word	.LC65
	.word	.LC35
	.word	.LC36
	.word	.LC40
	.word	.LC32
	.word	.LC33
	.word	.LC41
	.word	stderr
	.word	.LC66
	.word	.LC67
.L496:
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-164]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-160]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-168]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-168]
	bl	vec4state_free
	ldr	r0, [fp, #-164]
	bl	free
	ldr	r0, [fp, #-160]
	bl	free
	mov	r1, #0
	mov	r0, #1
	bl	vec4state_new
	str	r0, [fp, #-156]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #37
	mov	r1, #1
	ldr	r0, .L495+72
	bl	fwrite
	ldr	r1, [fp, #-156]
	ldr	r0, [fp, #-364]
	bl	vec4state_reduction_unary_xor
	mov	r1, #1
	ldr	r0, [fp, #-156]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-152]
	ldr	r0, [fp, #-156]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-148]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-152]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-148]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-156]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-156]
	bl	vec4state_free
	ldr	r0, [fp, #-152]
	bl	free
	ldr	r0, [fp, #-148]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, #8
	bl	vec4state_new
	str	r0, [fp, #-144]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #37
	mov	r1, #1
	ldr	r0, .L495+76
	bl	fwrite
	mov	r3, #0
	ldr	r2, [fp, #-144]
	mov	r1, #0
	ldr	r0, [fp, #-364]
	bl	vec4state_bitselect_get
	mov	r1, #1
	ldr	r0, [fp, #-144]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-140]
	ldr	r0, [fp, #-144]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-136]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-140]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-136]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-144]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-144]
	bl	vec4state_free
	ldr	r0, [fp, #-140]
	bl	free
	ldr	r0, [fp, #-136]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, #8
	bl	vec4state_new
	str	r0, [fp, #-132]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #37
	mov	r1, #1
	ldr	r0, .L495+80
	bl	fwrite
	mov	r3, #1
	ldr	r2, [fp, #-132]
	mov	r1, #0
	ldr	r0, [fp, #-364]
	bl	vec4state_bitselect_get
	mov	r1, #1
	ldr	r0, [fp, #-132]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-128]
	ldr	r0, [fp, #-132]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-124]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-128]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-124]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-132]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-132]
	bl	vec4state_free
	ldr	r0, [fp, #-128]
	bl	free
	ldr	r0, [fp, #-124]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, #35
	bl	vec4state_new
	str	r0, [fp, #-120]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #37
	mov	r1, #1
	ldr	r0, .L495+84
	bl	fwrite
	mov	r3, #0
	ldr	r2, [fp, #-120]
	mov	r1, #1
	ldr	r0, [fp, #-364]
	bl	vec4state_bitselect_get
	mov	r1, #1
	ldr	r0, [fp, #-120]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-116]
	ldr	r0, [fp, #-120]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-112]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-116]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-112]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-120]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-120]
	bl	vec4state_free
	ldr	r0, [fp, #-116]
	bl	free
	ldr	r0, [fp, #-112]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, #35
	bl	vec4state_new
	str	r0, [fp, #-108]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #37
	mov	r1, #1
	ldr	r0, .L495+88
	bl	fwrite
	mov	r3, #1
	ldr	r2, [fp, #-108]
	mov	r1, #1
	ldr	r0, [fp, #-364]
	bl	vec4state_bitselect_get
	mov	r1, #1
	ldr	r0, [fp, #-108]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-104]
	ldr	r0, [fp, #-108]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-100]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-104]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-100]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-108]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-108]
	bl	vec4state_free
	ldr	r0, [fp, #-104]
	bl	free
	ldr	r0, [fp, #-100]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-96]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #75
	mov	r1, #1
	ldr	r0, .L495+92
	bl	fwrite
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	cmp	r3, #1
	movcc	r1, r3
	movcs	r1, #1
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	cmp	r3, #7
	movge	r3, r3
	movlt	r3, #7
	sub	r3, r3, #7
	mov	r2, r3
	ldr	r3, [fp, #-96]
	ldr	r0, [fp, #-364]
	bl	vec4state_bitselect_set
	mov	r1, #1
	ldr	r0, [fp, #-96]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-92]
	ldr	r0, [fp, #-96]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-88]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-92]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-88]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-96]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-96]
	bl	vec4state_free
	ldr	r0, [fp, #-92]
	bl	free
	ldr	r0, [fp, #-88]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-84]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #75
	mov	r1, #1
	ldr	r0, .L495+96
	bl	fwrite
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	cmp	r3, #3
	movcc	r1, r3
	movcs	r1, #3
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	cmp	r3, #7
	movge	r3, r3
	movlt	r3, #7
	sub	r3, r3, #7
	mov	r2, r3
	ldr	r3, [fp, #-84]
	ldr	r0, [fp, #-364]
	bl	vec4state_bitselect_set
	mov	r1, #1
	ldr	r0, [fp, #-84]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-80]
	ldr	r0, [fp, #-84]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-76]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-80]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-76]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-84]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-84]
	bl	vec4state_free
	ldr	r0, [fp, #-80]
	bl	free
	ldr	r0, [fp, #-76]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-72]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #75
	mov	r1, #1
	ldr	r0, .L495+100
	bl	fwrite
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	cmp	r3, #7
	movge	r3, r3
	movlt	r3, #7
	sub	r3, r3, #7
	mov	r1, r3
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	cmp	r3, #1
	movcc	r2, r3
	movcs	r2, #1
	ldr	r3, [fp, #-72]
	ldr	r0, [fp, #-364]
	bl	vec4state_bitselect_set
	mov	r1, #1
	ldr	r0, [fp, #-72]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-68]
	ldr	r0, [fp, #-72]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-64]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-68]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-64]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-72]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-72]
	bl	vec4state_free
	ldr	r0, [fp, #-68]
	bl	free
	ldr	r0, [fp, #-64]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r2, [r3, #4]
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-60]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #75
	mov	r1, #1
	ldr	r0, .L495+104
	bl	fwrite
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	cmp	r3, #7
	movge	r3, r3
	movlt	r3, #7
	sub	r3, r3, #7
	mov	r1, r3
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	cmp	r3, #3
	movcc	r2, r3
	movcs	r2, #3
	ldr	r3, [fp, #-60]
	ldr	r0, [fp, #-364]
	bl	vec4state_bitselect_set
	mov	r1, #1
	ldr	r0, [fp, #-60]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-56]
	ldr	r0, [fp, #-60]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-52]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-56]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-52]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-60]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-60]
	bl	vec4state_free
	ldr	r0, [fp, #-56]
	bl	free
	ldr	r0, [fp, #-52]
	bl	free
	ldr	r3, [fp, #-368]
	ldr	r2, [r3, #4]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r2, r3, r2
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #8]
	mov	r1, r3
	mov	r0, r2
	bl	vec4state_new
	str	r0, [fp, #-48]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #28
	mov	r1, #1
	ldr	r0, .L495+108
	bl	fwrite
	ldr	r2, [fp, #-48]
	ldr	r1, [fp, #-360]
	ldr	r0, [fp, #-368]
	bl	vec4state_pow
	mov	r1, #1
	ldr	r0, [fp, #-48]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-44]
	ldr	r0, [fp, #-48]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-40]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-44]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-40]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-48]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-48]
	bl	vec4state_free
	ldr	r0, [fp, #-44]
	bl	free
	ldr	r0, [fp, #-40]
	bl	free
	ldr	r3, [fp, #-364]
	ldr	r3, [r3, #4]
	mov	r1, #0
	mov	r0, r3
	bl	vec4state_new
	str	r0, [fp, #-36]
	ldr	r3, [fp, #-368]
	ldr	r3, [r3, #4]
	mov	r1, #0
	mov	r0, r3
	bl	vec4state_new
	str	r0, [fp, #-32]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	mov	r2, #36
	mov	r1, #1
	ldr	r0, .L495+112
	bl	fwrite
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-32]
	ldr	r1, [fp, #-364]
	ldr	r0, [fp, #-368]
	bl	vec4state_div_unsigned
	mov	r1, #1
	ldr	r0, [fp, #-32]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-28]
	ldr	r0, [fp, #-32]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-24]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-356]
	ldr	r1, .L495+116
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-340]
	ldr	r1, .L495+120
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-28]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-24]
	ldr	r1, .L495+124
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-368]
	ldr	r0, .L495+128
	bl	__check_padding
	ldr	r1, [fp, #-364]
	ldr	r0, .L495+132
	bl	__check_padding
	ldr	r1, [fp, #-32]
	ldr	r0, .L495+136
	bl	__check_padding
	ldr	r0, [fp, #-32]
	bl	vec4state_free
	ldr	r0, [fp, #-28]
	bl	free
	ldr	r0, [fp, #-24]
	bl	free
	mov	r1, #1
	ldr	r0, [fp, #-36]
	bl	vec4state_to_vpiBinOctHexStr
	str	r0, [fp, #-20]
	ldr	r0, [fp, #-36]
	bl	vec4state_to_vpiDecStr
	str	r0, [fp, #-16]
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-20]
	ldr	r1, .L495+144
	mov	r0, r3
	bl	fprintf
	ldr	r3, .L495+140
	ldr	r3, [r3]
	ldr	r2, [fp, #-16]
	ldr	r1, .L495+144
	mov	r0, r3
	bl	fprintf
	ldr	r1, [fp, #-36]
	ldr	r0, .L495+148
	bl	__check_padding
	ldr	r0, [fp, #-36]
	bl	vec4state_free
	ldr	r0, [fp, #-20]
	bl	free
	ldr	r0, [fp, #-16]
	bl	free
	ldr	r0, [fp, #-356]
	bl	free
	ldr	r0, [fp, #-340]
	bl	free
.L493:
	ldr	r0, [fp, #-368]
	bl	vec4state_free
	ldr	r0, [fp, #-364]
	bl	vec4state_free
	ldr	r0, [fp, #-360]
	bl	vec4state_free
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
