	.file	"168893948.c"
	.intel_syntax noprefix
	.text
	.globl	compound_while
	.type	compound_while, @function
compound_while:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -8[rbp], 0
	mov	edx, DWORD PTR -8[rbp]
	mov	eax, edx
	add	eax, eax
	add	eax, edx
	mov	DWORD PTR -4[rbp], eax
	jmp	.L2
.L4:
	add	DWORD PTR -8[rbp], 1
.L2:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L3
	mov	eax, DWORD PTR -8[rbp]
	cmp	eax, DWORD PTR -20[rbp]
	jl	.L4
.L3:
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	compound_while, .-compound_while
	.globl	simplified_simulated_while_with_and
	.type	simplified_simulated_while_with_and, @function
simplified_simulated_while_with_and:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 0
	mov	DWORD PTR -8[rbp], 0
.L7:
	add	DWORD PTR -8[rbp], 1
	cmp	DWORD PTR -4[rbp], 0
	jne	.L8
	cmp	DWORD PTR -8[rbp], 99
	jg	.L8
	jmp	.L7
.L8:
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	simplified_simulated_while_with_and, .-simplified_simulated_while_with_and
	.globl	simulated_while_with_and
	.type	simulated_while_with_and, @function
simulated_while_with_and:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -8[rbp], 0
	mov	DWORD PTR -4[rbp], 0
.L11:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L16
	mov	eax, DWORD PTR -8[rbp]
	cmp	eax, DWORD PTR -20[rbp]
	jge	.L16
	nop
.L13:
	add	DWORD PTR -8[rbp], 1
	jmp	.L11
.L16:
	nop
.L14:
	mov	eax, DWORD PTR -8[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	simulated_while_with_and, .-simulated_while_with_and
	.globl	simulated_while_shortcut
	.type	simulated_while_shortcut, @function
simulated_while_shortcut:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 0
	mov	DWORD PTR -8[rbp], 0
.L18:
	add	DWORD PTR -8[rbp], 1
	cmp	DWORD PTR -4[rbp], 1
	jne	.L19
	cmp	DWORD PTR -8[rbp], 99
	jg	.L19
	jmp	.L18
.L19:
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	simulated_while_shortcut, .-simulated_while_shortcut
	.globl	while_and_or
	.type	while_and_or, @function
while_and_or:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L22
.L23:
	add	DWORD PTR -4[rbp], 1
.L22:
	cmp	DWORD PTR -20[rbp], 1
	je	.L23
	cmp	DWORD PTR -4[rbp], 29
	jg	.L25
	cmp	DWORD PTR -4[rbp], 0
	jns	.L23
.L25:
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	while_and_or, .-while_and_or
	.globl	nested_while_and_or
	.type	nested_while_and_or, @function
nested_while_and_or:
.LFB5:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -8[rbp], 0
	mov	edx, DWORD PTR -8[rbp]
	mov	eax, edx
	add	eax, eax
	add	eax, edx
	mov	DWORD PTR -4[rbp], eax
	jmp	.L27
.L32:
	cmp	DWORD PTR -20[rbp], 1
	jne	.L28
.L31:
	mov	eax, DWORD PTR -4[rbp]
	jmp	.L29
.L28:
	cmp	DWORD PTR -4[rbp], 4
	jg	.L30
	cmp	DWORD PTR -4[rbp], 0
	jns	.L31
.L30:
	add	DWORD PTR -8[rbp], 1
.L27:
	cmp	DWORD PTR -20[rbp], 1
	je	.L32
	cmp	DWORD PTR -8[rbp], 29
	jg	.L33
	cmp	DWORD PTR -8[rbp], 0
	jns	.L32
.L33:
	mov	eax, DWORD PTR -4[rbp]
.L29:
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	nested_while_and_or, .-nested_while_and_or
	.globl	simulated_nested_loop_with_and
	.type	simulated_nested_loop_with_and, @function
simulated_nested_loop_with_and:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -8[rbp], 0
	mov	DWORD PTR -4[rbp], 5
	mov	DWORD PTR -16[rbp], 0
	mov	DWORD PTR -12[rbp], 0
	jmp	.L35
.L39:
	nop
.L36:
	mov	DWORD PTR -4[rbp], 3
	add	DWORD PTR -16[rbp], 1
	cmp	DWORD PTR -8[rbp], 0
	jne	.L37
	cmp	DWORD PTR -16[rbp], 99
	jg	.L37
	jmp	.L36
.L37:
	add	DWORD PTR -12[rbp], 1
.L35:
	cmp	DWORD PTR -12[rbp], 4
	jle	.L39
	mov	eax, DWORD PTR -8[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	simulated_nested_loop_with_and, .-simulated_nested_loop_with_and
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"168893948.c"
	.text
	.align	2
	.global	compound_while
	.syntax unified
	.arm
	.fpu softvfp
	.type	compound_while, %function
compound_while:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-12]
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	str	r3, [fp, #-8]
	b	.L2
.L4:
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
.L2:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L3
	ldr	r2, [fp, #-12]
	ldr	r3, [fp, #-16]
	cmp	r2, r3
	blt	.L4
.L3:
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	compound_while, .-compound_while
	.align	2
	.global	simplified_simulated_while_with_and
	.syntax unified
	.arm
	.fpu softvfp
	.type	simplified_simulated_while_with_and, %function
simplified_simulated_while_with_and:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-8]
	mov	r3, #0
	str	r3, [fp, #-12]
.L7:
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L8
	ldr	r3, [fp, #-12]
	cmp	r3, #99
	bgt	.L8
	b	.L7
.L8:
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	simplified_simulated_while_with_and, .-simplified_simulated_while_with_and
	.align	2
	.global	simulated_while_with_and
	.syntax unified
	.arm
	.fpu softvfp
	.type	simulated_while_with_and, %function
simulated_while_with_and:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-12]
	mov	r3, #0
	str	r3, [fp, #-8]
.L11:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L16
	ldr	r2, [fp, #-12]
	ldr	r3, [fp, #-16]
	cmp	r2, r3
	bge	.L16
	nop
.L13:
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
	b	.L11
.L16:
	nop
.L14:
	ldr	r3, [fp, #-12]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	simulated_while_with_and, .-simulated_while_with_and
	.align	2
	.global	simulated_while_shortcut
	.syntax unified
	.arm
	.fpu softvfp
	.type	simulated_while_shortcut, %function
simulated_while_shortcut:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-8]
	mov	r3, #0
	str	r3, [fp, #-12]
.L18:
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-8]
	cmp	r3, #1
	bne	.L19
	ldr	r3, [fp, #-12]
	cmp	r3, #99
	bgt	.L19
	b	.L18
.L19:
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	simulated_while_shortcut, .-simulated_while_shortcut
	.align	2
	.global	while_and_or
	.syntax unified
	.arm
	.fpu softvfp
	.type	while_and_or, %function
while_and_or:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L22
.L23:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L22:
	ldr	r3, [fp, #-16]
	cmp	r3, #1
	beq	.L23
	ldr	r3, [fp, #-8]
	cmp	r3, #29
	bgt	.L25
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bge	.L23
.L25:
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	while_and_or, .-while_and_or
	.align	2
	.global	nested_while_and_or
	.syntax unified
	.arm
	.fpu softvfp
	.type	nested_while_and_or, %function
nested_while_and_or:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-12]
	ldr	r2, [fp, #-12]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	str	r3, [fp, #-8]
	b	.L27
.L32:
	ldr	r3, [fp, #-16]
	cmp	r3, #1
	bne	.L28
.L31:
	ldr	r3, [fp, #-8]
	b	.L29
.L28:
	ldr	r3, [fp, #-8]
	cmp	r3, #4
	bgt	.L30
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bge	.L31
.L30:
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	str	r3, [fp, #-12]
.L27:
	ldr	r3, [fp, #-16]
	cmp	r3, #1
	beq	.L32
	ldr	r3, [fp, #-12]
	cmp	r3, #29
	bgt	.L33
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	bge	.L32
.L33:
	ldr	r3, [fp, #-8]
.L29:
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	nested_while_and_or, .-nested_while_and_or
	.align	2
	.global	simulated_nested_loop_with_and
	.syntax unified
	.arm
	.fpu softvfp
	.type	simulated_nested_loop_with_and, %function
simulated_nested_loop_with_and:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-24]
	mov	r3, #0
	str	r3, [fp, #-12]
	mov	r3, #5
	str	r3, [fp, #-8]
	mov	r3, #0
	str	r3, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-16]
	b	.L35
.L39:
	nop
.L36:
	mov	r3, #3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-20]
	add	r3, r3, #1
	str	r3, [fp, #-20]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	bne	.L37
	ldr	r3, [fp, #-20]
	cmp	r3, #99
	bgt	.L37
	b	.L36
.L37:
	ldr	r3, [fp, #-16]
	add	r3, r3, #1
	str	r3, [fp, #-16]
.L35:
	ldr	r3, [fp, #-16]
	cmp	r3, #4
	ble	.L39
	ldr	r3, [fp, #-12]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	simulated_nested_loop_with_and, .-simulated_nested_loop_with_and
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
