	.file	"55744.c"
	.intel_syntax noprefix
	.text
	.globl	unionInit
	.type	unionInit, @function
unionInit:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L2
.L3:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -24[rbp]
	add	rdx, rax
	mov	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR [rdx], eax
	add	DWORD PTR -4[rbp], 1
.L2:
	mov	eax, DWORD PTR -4[rbp]
	cmp	eax, DWORD PTR -28[rbp]
	jl	.L3
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	unionInit, .-unionInit
	.globl	unionGet
	.type	unionGet, @function
unionGet:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	eax, DWORD PTR -28[rbp]
	mov	DWORD PTR -8[rbp], eax
	jmp	.L5
.L6:
	mov	eax, DWORD PTR -8[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -8[rbp], eax
.L5:
	mov	eax, DWORD PTR -8[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -8[rbp], eax
	jne	.L6
	jmp	.L7
.L8:
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -24[rbp]
	add	rdx, rax
	mov	eax, DWORD PTR -8[rbp]
	mov	DWORD PTR [rdx], eax
	mov	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR -28[rbp], eax
.L7:
	mov	eax, DWORD PTR -28[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -28[rbp], eax
	jne	.L8
	mov	eax, DWORD PTR -28[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	unionGet, .-unionGet
	.globl	unionConnect
	.type	unionConnect, @function
unionConnect:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	DWORD PTR -12[rbp], esi
	mov	DWORD PTR -16[rbp], edx
	mov	edx, DWORD PTR -12[rbp]
	mov	rax, QWORD PTR -8[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	unionGet
	mov	DWORD PTR -12[rbp], eax
	mov	edx, DWORD PTR -16[rbp]
	mov	rax, QWORD PTR -8[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	unionGet
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -12[rbp]
	cmp	eax, DWORD PTR -16[rbp]
	jne	.L11
	mov	eax, 0
	jmp	.L12
.L11:
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -8[rbp]
	add	rdx, rax
	mov	eax, DWORD PTR -16[rbp]
	mov	DWORD PTR [rdx], eax
	mov	eax, 1
.L12:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	unionConnect, .-unionConnect
	.section	.rodata
.LC0:
	.string	"%d"
.LC1:
	.string	"%d%d"
.LC2:
	.string	"%d\n"
.LC3:
	.string	"%d %d %d %d\n"
	.text
	.globl	main
	.type	main, @function
main:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	lea	r11, -40960[rsp]
.LPSRL0:
	sub	rsp, 4096
	or	DWORD PTR [rsp], 0
	cmp	rsp, r11
	jne	.LPSRL0
	sub	rsp, 2304
	mov	DWORD PTR -43252[rbp], edi
	mov	QWORD PTR -43264[rbp], rsi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	lea	rax, -43248[rbp]
	mov	rsi, rax
	lea	rdi, .LC0[rip]
	mov	eax, 0
	call	__isoc99_scanf@PLT
	mov	eax, DWORD PTR -43248[rbp]
	sub	eax, 1
	mov	DWORD PTR -43220[rbp], eax
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L14
.L15:
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, -38416[rbp]
	add	rdx, rax
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	lea	rcx, 0[0+rax*4]
	lea	rax, -43216[rbp]
	add	rax, rcx
	mov	rsi, rax
	lea	rdi, .LC1[rip]
	mov	eax, 0
	call	__isoc99_scanf@PLT
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -43216[rbp+rax*4]
	lea	edx, -1[rax]
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	DWORD PTR -43216[rbp+rax*4], edx
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -38416[rbp+rax*4]
	lea	edx, -1[rax]
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	DWORD PTR -38416[rbp+rax*4], edx
	add	DWORD PTR -43244[rbp], 1
.L14:
	mov	eax, DWORD PTR -43244[rbp]
	cmp	eax, DWORD PTR -43220[rbp]
	jl	.L15
	mov	edx, DWORD PTR -43248[rbp]
	lea	rax, -28816[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	unionInit
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L16
.L17:
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	edx, DWORD PTR -38416[rbp+rax*4]
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	ecx, DWORD PTR -43216[rbp+rax*4]
	lea	rax, -28816[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	unionConnect
	add	DWORD PTR -43244[rbp], 1
.L16:
	mov	eax, DWORD PTR -43244[rbp]
	cmp	eax, DWORD PTR -43220[rbp]
	jl	.L17
	mov	DWORD PTR -43232[rbp], 0
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L18
.L19:
	mov	edx, DWORD PTR -43244[rbp]
	lea	rax, -28816[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	unionGet
	cdqe
	mov	DWORD PTR -24016[rbp+rax*4], 1
	add	DWORD PTR -43244[rbp], 1
.L18:
	mov	eax, DWORD PTR -43244[rbp]
	cmp	eax, DWORD PTR -43220[rbp]
	jl	.L19
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L20
.L21:
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -24016[rbp+rax*4]
	add	DWORD PTR -43232[rbp], eax
	add	DWORD PTR -43244[rbp], 1
.L20:
	mov	eax, DWORD PTR -43248[rbp]
	cmp	DWORD PTR -43244[rbp], eax
	jl	.L21
	mov	DWORD PTR -43228[rbp], 0
	mov	DWORD PTR -43224[rbp], -1
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L22
.L25:
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -24016[rbp+rax*4]
	test	eax, eax
	je	.L23
	cmp	DWORD PTR -43224[rbp], 0
	js	.L24
	mov	eax, DWORD PTR -43228[rbp]
	cdqe
	mov	edx, DWORD PTR -43224[rbp]
	mov	DWORD PTR -9616[rbp+rax*4], edx
	mov	eax, DWORD PTR -43228[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -43228[rbp], edx
	cdqe
	mov	edx, DWORD PTR -43244[rbp]
	mov	DWORD PTR -4816[rbp+rax*4], edx
.L24:
	mov	eax, DWORD PTR -43244[rbp]
	mov	DWORD PTR -43224[rbp], eax
.L23:
	add	DWORD PTR -43244[rbp], 1
.L22:
	mov	eax, DWORD PTR -43248[rbp]
	cmp	DWORD PTR -43244[rbp], eax
	jl	.L25
	mov	DWORD PTR -43228[rbp], 0
	mov	DWORD PTR -43236[rbp], 0
	jmp	.L26
.L27:
	mov	eax, DWORD PTR -43236[rbp]
	cdqe
	mov	DWORD PTR -33616[rbp+rax*4], 0
	add	DWORD PTR -43236[rbp], 1
.L26:
	mov	eax, DWORD PTR -43236[rbp]
	cmp	eax, DWORD PTR -43220[rbp]
	jl	.L27
	mov	DWORD PTR -43236[rbp], 0
	jmp	.L28
.L39:
	mov	edx, DWORD PTR -43248[rbp]
	lea	rax, -28816[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	unionInit
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L29
.L31:
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -33616[rbp+rax*4]
	test	eax, eax
	jne	.L30
	mov	eax, DWORD PTR -43244[rbp]
	cmp	eax, DWORD PTR -43236[rbp]
	je	.L30
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	edx, DWORD PTR -38416[rbp+rax*4]
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	ecx, DWORD PTR -43216[rbp+rax*4]
	lea	rax, -28816[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	unionConnect
.L30:
	add	DWORD PTR -43244[rbp], 1
.L29:
	mov	eax, DWORD PTR -43244[rbp]
	cmp	eax, DWORD PTR -43220[rbp]
	jl	.L31
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L32
.L33:
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	DWORD PTR -24016[rbp+rax*4], 0
	add	DWORD PTR -43244[rbp], 1
.L32:
	mov	eax, DWORD PTR -43248[rbp]
	cmp	DWORD PTR -43244[rbp], eax
	jl	.L33
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L34
.L35:
	mov	edx, DWORD PTR -43244[rbp]
	lea	rax, -28816[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	unionGet
	cdqe
	mov	DWORD PTR -24016[rbp+rax*4], 1
	add	DWORD PTR -43244[rbp], 1
.L34:
	mov	eax, DWORD PTR -43248[rbp]
	cmp	DWORD PTR -43244[rbp], eax
	jl	.L35
	mov	DWORD PTR -43240[rbp], 0
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L36
.L37:
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -24016[rbp+rax*4]
	add	DWORD PTR -43240[rbp], eax
	add	DWORD PTR -43244[rbp], 1
.L36:
	mov	eax, DWORD PTR -43248[rbp]
	cmp	DWORD PTR -43244[rbp], eax
	jl	.L37
	mov	eax, DWORD PTR -43240[rbp]
	cmp	eax, DWORD PTR -43232[rbp]
	jne	.L38
	mov	eax, DWORD PTR -43236[rbp]
	cdqe
	mov	DWORD PTR -33616[rbp+rax*4], 1
	mov	eax, DWORD PTR -43236[rbp]
	cdqe
	mov	edx, DWORD PTR -43216[rbp+rax*4]
	mov	eax, DWORD PTR -43228[rbp]
	cdqe
	mov	DWORD PTR -19216[rbp+rax*4], edx
	mov	eax, DWORD PTR -43228[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -43228[rbp], edx
	mov	edx, DWORD PTR -43236[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -38416[rbp+rdx*4]
	cdqe
	mov	DWORD PTR -14416[rbp+rax*4], edx
.L38:
	add	DWORD PTR -43236[rbp], 1
.L28:
	mov	eax, DWORD PTR -43236[rbp]
	cmp	eax, DWORD PTR -43220[rbp]
	jl	.L39
	mov	eax, DWORD PTR -43228[rbp]
	mov	esi, eax
	lea	rdi, .LC2[rip]
	mov	eax, 0
	call	printf@PLT
	mov	DWORD PTR -43244[rbp], 0
	jmp	.L40
.L41:
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -4816[rbp+rax*4]
	lea	esi, 1[rax]
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -9616[rbp+rax*4]
	lea	ecx, 1[rax]
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -14416[rbp+rax*4]
	lea	edx, 1[rax]
	mov	eax, DWORD PTR -43244[rbp]
	cdqe
	mov	eax, DWORD PTR -19216[rbp+rax*4]
	add	eax, 1
	mov	r8d, esi
	mov	esi, eax
	lea	rdi, .LC3[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -43244[rbp], 1
.L40:
	mov	eax, DWORD PTR -43244[rbp]
	cmp	eax, DWORD PTR -43228[rbp]
	jl	.L41
	mov	eax, 0
	mov	rcx, QWORD PTR -8[rbp]
	sub	rcx, QWORD PTR fs:40
	je	.L43
	call	__stack_chk_fail@PLT
.L43:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"55744.c"
	.text
	.align	2
	.global	unionInit
	.syntax unified
	.arm
	.fpu softvfp
	.type	unionInit, %function
unionInit:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L2
.L3:
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r2, [fp, #-8]
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L2:
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	blt	.L3
	nop
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	unionInit, .-unionInit
	.align	2
	.global	unionGet
	.syntax unified
	.arm
	.fpu softvfp
	.type	unionGet, %function
unionGet:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-20]
	str	r3, [fp, #-12]
	b	.L5
.L6:
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r3, [r3]
	str	r3, [fp, #-12]
.L5:
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r3, [r3]
	ldr	r2, [fp, #-12]
	cmp	r2, r3
	bne	.L6
	b	.L7
.L8:
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r2, [fp, #-12]
	str	r2, [r3]
	ldr	r3, [fp, #-8]
	str	r3, [fp, #-20]
.L7:
	ldr	r3, [fp, #-20]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r3, [r3]
	ldr	r2, [fp, #-20]
	cmp	r2, r3
	bne	.L8
	ldr	r3, [fp, #-20]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	unionGet, .-unionGet
	.align	2
	.global	unionConnect
	.syntax unified
	.arm
	.fpu softvfp
	.type	unionConnect, %function
unionConnect:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	str	r2, [fp, #-16]
	ldr	r1, [fp, #-12]
	ldr	r0, [fp, #-8]
	bl	unionGet
	str	r0, [fp, #-12]
	ldr	r1, [fp, #-16]
	ldr	r0, [fp, #-8]
	bl	unionGet
	str	r0, [fp, #-16]
	ldr	r2, [fp, #-12]
	ldr	r3, [fp, #-16]
	cmp	r2, r3
	bne	.L11
	mov	r3, #0
	b	.L12
.L11:
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-8]
	add	r3, r2, r3
	ldr	r2, [fp, #-16]
	str	r2, [r3]
	mov	r3, #1
.L12:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	unionConnect, .-unionConnect
	.section	.rodata
	.align	2
.LC0:
	.ascii	"%d\000"
	.align	2
.LC1:
	.ascii	"%d%d\000"
	.align	2
.LC2:
	.ascii	"%d\012\000"
	.align	2
.LC3:
	.ascii	"%d %d %d %d\012\000"
	.align	2
.LC4:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 43248
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #43008
	sub	sp, sp, #248
	sub	r3, fp, #40960
	sub	r3, r3, #4
	str	r0, [r3, #-2284]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	str	r1, [r3, #-2288]
	ldr	r3, .L44
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	sub	r3, fp, #43008
	sub	r3, r3, #4
	sub	r3, r3, #228
	mov	r1, r3
	ldr	r0, .L44+4
	bl	__isoc99_scanf
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2276]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	sub	r3, r3, #1
	str	r3, [r2, #-2248]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L14
.L15:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r2, r3, #2
	sub	r3, fp, #43008
	sub	r3, r3, #4
	sub	r3, r3, #196
	add	r1, r3, r2
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r2, r3, #2
	sub	r3, fp, #38400
	sub	r3, r3, #4
	sub	r3, r3, #4
	add	r3, r3, r2
	mov	r2, r3
	ldr	r0, .L44+8
	bl	__isoc99_scanf
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-2244]
	sub	r2, r3, #1
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r1, r3
	str	r2, [r3, #-2244]
	sub	r3, fp, #36864
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-1540]
	sub	r2, r3, #1
	sub	r3, fp, #36864
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r1, r3
	str	r2, [r3, #-1540]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L14:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2272]
	ldr	r3, [r3, #-2248]
	cmp	r2, r3
	blt	.L15
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r3, #-2276]
	sub	r3, fp, #28672
	sub	r3, r3, #4
	sub	r3, r3, #132
	mov	r1, r2
	mov	r0, r3
	bl	unionInit
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L16
.L17:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r1, [r3, #-2244]
	sub	r3, fp, #36864
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r2, [r3, #-1540]
	sub	r3, fp, #28672
	sub	r3, r3, #4
	sub	r3, r3, #132
	mov	r0, r3
	bl	unionConnect
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L16:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2272]
	ldr	r3, [r3, #-2248]
	cmp	r2, r3
	blt	.L17
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2260]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L18
.L19:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #28672
	sub	r3, r3, #4
	sub	r3, r3, #132
	ldr	r1, [r2, #-2272]
	mov	r0, r3
	bl	unionGet
	mov	r3, r0
	sub	r2, fp, #20480
	sub	r2, r2, #4
	lsl	r3, r3, #2
	add	r3, r2, r3
	mov	r2, #1
	str	r2, [r3, #-3524]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L18:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2272]
	ldr	r3, [r3, #-2248]
	cmp	r2, r3
	blt	.L19
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L20
.L21:
	sub	r3, fp, #20480
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-3524]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	mov	r1, r2
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2260]
	add	r3, r2, r3
	str	r3, [r1, #-2260]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L20:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2276]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2272]
	cmp	r2, r3
	blt	.L21
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2256]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mvn	r3, #0
	str	r3, [r2, #-2252]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L22
.L25:
	sub	r3, fp, #20480
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-3524]
	cmp	r3, #0
	beq	.L23
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2252]
	cmp	r3, #0
	blt	.L24
	sub	r3, fp, #8192
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2256]
	lsl	r3, r3, #2
	add	r3, r2, r3
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2252]
	str	r2, [r3, #-1412]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2256]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	mov	r1, r2
	add	r2, r3, #1
	str	r2, [r1, #-2256]
	sub	r2, fp, #4096
	sub	r2, r2, #4
	lsl	r3, r3, #2
	add	r3, r2, r3
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2272]
	str	r2, [r3, #-708]
.L24:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	str	r3, [r2, #-2252]
.L23:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L22:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2276]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2272]
	cmp	r2, r3
	blt	.L25
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2256]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2264]
	b	.L26
.L27:
	sub	r3, fp, #32768
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2264]
	lsl	r3, r3, #2
	add	r3, r2, r3
	mov	r2, #0
	str	r2, [r3, #-836]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2264]
	add	r3, r3, #1
	str	r3, [r2, #-2264]
.L26:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2264]
	ldr	r3, [r3, #-2248]
	cmp	r2, r3
	blt	.L27
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2264]
	b	.L28
.L39:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r3, #-2276]
	sub	r3, fp, #28672
	sub	r3, r3, #4
	sub	r3, r3, #132
	mov	r1, r2
	mov	r0, r3
	bl	unionInit
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L29
.L31:
	sub	r3, fp, #32768
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-836]
	cmp	r3, #0
	bne	.L30
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2272]
	ldr	r3, [r3, #-2264]
	cmp	r2, r3
	beq	.L30
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r1, [r3, #-2244]
	sub	r3, fp, #36864
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r2, [r3, #-1540]
	sub	r3, fp, #28672
	sub	r3, r3, #4
	sub	r3, r3, #132
	mov	r0, r3
	bl	unionConnect
.L30:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L29:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2272]
	ldr	r3, [r3, #-2248]
	cmp	r2, r3
	blt	.L31
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L32
.L33:
	sub	r3, fp, #20480
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	mov	r2, #0
	str	r2, [r3, #-3524]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L32:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2276]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2272]
	cmp	r2, r3
	blt	.L33
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L34
.L35:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #28672
	sub	r3, r3, #4
	sub	r3, r3, #132
	ldr	r1, [r2, #-2272]
	mov	r0, r3
	bl	unionGet
	mov	r3, r0
	sub	r2, fp, #20480
	sub	r2, r2, #4
	lsl	r3, r3, #2
	add	r3, r2, r3
	mov	r2, #1
	str	r2, [r3, #-3524]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L34:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2276]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2272]
	cmp	r2, r3
	blt	.L35
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2268]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L36
.L37:
	sub	r3, fp, #20480
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-3524]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	mov	r1, r2
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2268]
	add	r3, r2, r3
	str	r3, [r1, #-2268]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L36:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2276]
	sub	r2, fp, #40960
	sub	r2, r2, #4
	ldr	r2, [r2, #-2272]
	cmp	r2, r3
	blt	.L37
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2268]
	ldr	r3, [r3, #-2260]
	cmp	r2, r3
	bne	.L38
	sub	r3, fp, #32768
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2264]
	lsl	r3, r3, #2
	add	r3, r2, r3
	mov	r2, #1
	str	r2, [r3, #-836]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2264]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r2, [r3, #-2244]
	sub	r3, fp, #16384
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2256]
	lsl	r3, r3, #2
	add	r3, r1, r3
	str	r2, [r3, #-2820]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r3, #-2256]
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r1, r3
	add	r3, r2, #1
	str	r3, [r1, #-2256]
	sub	r3, fp, #36864
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2264]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-1540]
	sub	r3, fp, #12288
	sub	r3, r3, #4
	mov	r0, r3
	lsl	r3, r2, #2
	add	r3, r0, r3
	str	r1, [r3, #-2116]
.L38:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2264]
	add	r3, r3, #1
	str	r3, [r2, #-2264]
.L28:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2264]
	ldr	r3, [r3, #-2248]
	cmp	r2, r3
	blt	.L39
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r1, [r3, #-2256]
	ldr	r0, .L44+12
	bl	printf
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-2272]
	b	.L40
.L41:
	sub	r3, fp, #16384
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-2820]
	add	r1, r3, #1
	sub	r3, fp, #12288
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-2116]
	add	r2, r3, #1
	sub	r3, fp, #8192
	sub	r3, r3, #4
	mov	r0, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r3, [r3, #-1412]
	add	r0, r3, #1
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	ip, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	lsl	r3, r3, #2
	add	r3, ip, r3
	ldr	r3, [r3, #-708]
	add	r3, r3, #1
	str	r3, [sp]
	mov	r3, r0
	ldr	r0, .L44+16
	bl	printf
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r3, [r3, #-2272]
	add	r3, r3, #1
	str	r3, [r2, #-2272]
.L40:
	sub	r3, fp, #40960
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #40960
	sub	r3, r3, #4
	ldr	r2, [r2, #-2272]
	ldr	r3, [r3, #-2256]
	cmp	r2, r3
	blt	.L41
	mov	r3, #0
	ldr	r2, .L44
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L43
	bl	__stack_chk_fail
.L43:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L45:
	.align	2
.L44:
	.word	.LC4
	.word	.LC0
	.word	.LC1
	.word	.LC2
	.word	.LC3
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
