	.file	"231394265.c"
	.intel_syntax noprefix
	.text
	.globl	g_uvqi0
	.bss
	.align 16
	.type	g_uvqi0, @object
	.size	g_uvqi0, 16
g_uvqi0:
	.zero	16
	.globl	g_uvqi1
	.align 16
	.type	g_uvqi1, @object
	.size	g_uvqi1, 16
g_uvqi1:
	.zero	16
	.globl	g_uvqi2
	.align 16
	.type	g_uvqi2, @object
	.size	g_uvqi2, 16
g_uvqi2:
	.zero	16
	.globl	g_vqi0
	.align 16
	.type	g_vqi0, @object
	.size	g_vqi0, 16
g_vqi0:
	.zero	16
	.globl	g_vqi1
	.align 16
	.type	g_vqi1, @object
	.size	g_vqi1, 16
g_vqi1:
	.zero	16
	.globl	g_vqi2
	.align 16
	.type	g_vqi2, @object
	.size	g_vqi2, 16
g_vqi2:
	.zero	16
	.globl	g_uvhi0
	.align 16
	.type	g_uvhi0, @object
	.size	g_uvhi0, 16
g_uvhi0:
	.zero	16
	.globl	g_uvhi1
	.align 16
	.type	g_uvhi1, @object
	.size	g_uvhi1, 16
g_uvhi1:
	.zero	16
	.globl	g_uvhi2
	.align 16
	.type	g_uvhi2, @object
	.size	g_uvhi2, 16
g_uvhi2:
	.zero	16
	.globl	g_vhi0
	.align 16
	.type	g_vhi0, @object
	.size	g_vhi0, 16
g_vhi0:
	.zero	16
	.globl	g_vhi1
	.align 16
	.type	g_vhi1, @object
	.size	g_vhi1, 16
g_vhi1:
	.zero	16
	.globl	g_vhi2
	.align 16
	.type	g_vhi2, @object
	.size	g_vhi2, 16
g_vhi2:
	.zero	16
	.globl	g_uvsi0
	.align 16
	.type	g_uvsi0, @object
	.size	g_uvsi0, 16
g_uvsi0:
	.zero	16
	.globl	g_uvsi1
	.align 16
	.type	g_uvsi1, @object
	.size	g_uvsi1, 16
g_uvsi1:
	.zero	16
	.globl	g_uvsi2
	.align 16
	.type	g_uvsi2, @object
	.size	g_uvsi2, 16
g_uvsi2:
	.zero	16
	.globl	g_vsi0
	.align 16
	.type	g_vsi0, @object
	.size	g_vsi0, 16
g_vsi0:
	.zero	16
	.globl	g_vsi1
	.align 16
	.type	g_vsi1, @object
	.size	g_vsi1, 16
g_vsi1:
	.zero	16
	.globl	g_vsi2
	.align 16
	.type	g_vsi2, @object
	.size	g_vsi2, 16
g_vsi2:
	.zero	16
	.globl	g_uvdi0
	.align 16
	.type	g_uvdi0, @object
	.size	g_uvdi0, 16
g_uvdi0:
	.zero	16
	.globl	g_uvdi1
	.align 16
	.type	g_uvdi1, @object
	.size	g_uvdi1, 16
g_uvdi1:
	.zero	16
	.globl	g_uvdi2
	.align 16
	.type	g_uvdi2, @object
	.size	g_uvdi2, 16
g_uvdi2:
	.zero	16
	.globl	g_vdi0
	.align 16
	.type	g_vdi0, @object
	.size	g_vdi0, 16
g_vdi0:
	.zero	16
	.globl	g_vdi1
	.align 16
	.type	g_vdi1, @object
	.size	g_vdi1, 16
g_vdi1:
	.zero	16
	.globl	g_vdi2
	.align 16
	.type	g_vdi2, @object
	.size	g_vdi2, 16
g_vdi2:
	.zero	16
	.globl	g_vdf0
	.align 16
	.type	g_vdf0, @object
	.size	g_vdf0, 16
g_vdf0:
	.zero	16
	.globl	g_vdf1
	.align 16
	.type	g_vdf1, @object
	.size	g_vdf1, 16
g_vdf1:
	.zero	16
	.globl	g_vdf2
	.align 16
	.type	g_vdf2, @object
	.size	g_vdf2, 16
g_vdf2:
	.zero	16
	.text
	.globl	sub1
	.type	sub1, @function
sub1:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	movdqa	xmm0, XMMWORD PTR g_vqi1[rip]
	movdqa	xmm1, XMMWORD PTR g_vqi2[rip]
	psubb	xmm0, xmm1
	movaps	XMMWORD PTR g_vqi0[rip], xmm0
	movdqa	xmm0, XMMWORD PTR g_uvqi1[rip]
	movdqa	xmm1, XMMWORD PTR g_uvqi2[rip]
	psubb	xmm0, xmm1
	movaps	XMMWORD PTR g_uvqi0[rip], xmm0
	movdqa	xmm0, XMMWORD PTR g_vhi1[rip]
	movdqa	xmm1, XMMWORD PTR g_vhi2[rip]
	psubw	xmm0, xmm1
	movaps	XMMWORD PTR g_vhi0[rip], xmm0
	movdqa	xmm0, XMMWORD PTR g_uvhi1[rip]
	movdqa	xmm1, XMMWORD PTR g_uvhi2[rip]
	psubw	xmm0, xmm1
	movaps	XMMWORD PTR g_uvhi0[rip], xmm0
	movdqa	xmm0, XMMWORD PTR g_vsi1[rip]
	movdqa	xmm1, XMMWORD PTR g_vsi2[rip]
	psubd	xmm0, xmm1
	movaps	XMMWORD PTR g_vsi0[rip], xmm0
	movdqa	xmm0, XMMWORD PTR g_uvsi1[rip]
	movdqa	xmm1, XMMWORD PTR g_uvsi2[rip]
	psubd	xmm0, xmm1
	movaps	XMMWORD PTR g_uvsi0[rip], xmm0
	movdqa	xmm0, XMMWORD PTR g_vdi1[rip]
	movdqa	xmm1, XMMWORD PTR g_vdi2[rip]
	psubq	xmm0, xmm1
	movaps	XMMWORD PTR g_vdi0[rip], xmm0
	movdqa	xmm0, XMMWORD PTR g_uvdi1[rip]
	movdqa	xmm1, XMMWORD PTR g_uvdi2[rip]
	psubq	xmm0, xmm1
	movaps	XMMWORD PTR g_uvdi0[rip], xmm0
	movapd	xmm0, XMMWORD PTR g_vdf1[rip]
	movapd	xmm1, XMMWORD PTR g_vdf2[rip]
	subpd	xmm0, xmm1
	movaps	XMMWORD PTR g_vdf0[rip], xmm0
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	sub1, .-sub1
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"231394265.c"
	.text
	.comm	g_uvqi0,16,8
	.comm	g_uvqi1,16,8
	.comm	g_uvqi2,16,8
	.comm	g_vqi0,16,8
	.comm	g_vqi1,16,8
	.comm	g_vqi2,16,8
	.comm	g_uvhi0,16,8
	.comm	g_uvhi1,16,8
	.comm	g_uvhi2,16,8
	.comm	g_vhi0,16,8
	.comm	g_vhi1,16,8
	.comm	g_vhi2,16,8
	.comm	g_uvsi0,16,8
	.comm	g_uvsi1,16,8
	.comm	g_uvsi2,16,8
	.comm	g_vsi0,16,8
	.comm	g_vsi1,16,8
	.comm	g_vsi2,16,8
	.comm	g_uvdi0,16,8
	.comm	g_uvdi1,16,8
	.comm	g_uvdi2,16,8
	.comm	g_vdi0,16,8
	.comm	g_vdi1,16,8
	.comm	g_vdi2,16,8
	.comm	g_vdf0,16,8
	.comm	g_vdf1,16,8
	.comm	g_vdf2,16,8
	.global	__aeabi_dsub
	.align	2
	.global	sub1
	.syntax unified
	.arm
	.fpu softvfp
	.type	sub1, %function
sub1:
	@ args = 0, pretend = 0, frame = 120
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, r8, r9, r10, fp, lr}
	add	fp, sp, #32
	sub	sp, sp, #124
	ldr	r3, .L2
	ldr	r4, [r3]
	ldr	r5, [r3, #4]
	ldr	r6, [r3, #8]
	ldr	r7, [r3, #12]
	ldr	r3, .L2+4
	ldr	r2, [r3]
	str	r2, [fp, #-116]
	ldr	r2, [r3, #4]
	str	r2, [fp, #-112]
	ldr	r2, [r3, #8]
	str	r2, [fp, #-108]
	ldr	r3, [r3, #12]
	str	r3, [fp, #-104]
	mov	ip, r4
	ldr	r3, [fp, #-116]
	eor	r2, ip, r3
	ldr	r0, .L2+8
	and	r0, r0, r3
	ldr	r1, .L2+12
	orr	r1, ip, r1
	mvn	r3, r2
	ldr	r2, .L2+12
	and	r2, r2, r3
	sub	r3, r1, r0
	eor	r9, r2, r3
	mov	ip, r5
	ldr	r3, [fp, #-112]
	eor	r2, ip, r3
	ldr	r0, .L2+8
	and	r0, r0, r3
	ldr	r1, .L2+12
	orr	r1, ip, r1
	mvn	r3, r2
	ldr	r2, .L2+12
	and	r2, r2, r3
	sub	r3, r1, r0
	eor	r8, r2, r3
	mov	ip, r6
	ldr	r3, [fp, #-108]
	eor	r2, ip, r3
	ldr	r0, .L2+8
	and	r0, r0, r3
	ldr	r1, .L2+12
	orr	r1, ip, r1
	mvn	r3, r2
	ldr	r2, .L2+12
	and	r2, r2, r3
	sub	r3, r1, r0
	eor	lr, r2, r3
	mov	r2, r7
	ldr	r3, [fp, #-104]
	eor	r1, r2, r3
	ldr	r0, .L2+8
	and	r0, r0, r3
	ldr	r3, .L2+12
	orr	r3, r2, r3
	mvn	r1, r1
	ldr	r2, .L2+12
	and	r2, r2, r1
	sub	r3, r3, r0
	eor	ip, r2, r3
	mov	r0, #0
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	mov	r0, r9
	mov	r1, r8
	mov	r2, lr
	mov	r3, ip
	str	r0, [fp, #-116]
	str	r1, [fp, #-112]
	str	r2, [fp, #-108]
	str	r3, [fp, #-104]
	ldr	r4, [fp, #-116]
	ldr	r5, [fp, #-112]
	ldr	r6, [fp, #-108]
	ldr	r7, [fp, #-104]
	ldr	r3, .L2+16
	mov	r2, r4
	str	r2, [r3]
	mov	r2, r5
	str	r2, [r3, #4]
	mov	r2, r6
	str	r2, [r3, #8]
	mov	r2, r7
	str	r2, [r3, #12]
	ldr	r3, .L2+20
	ldr	r4, [r3]
	ldr	r5, [r3, #4]
	ldr	r6, [r3, #8]
	ldr	r7, [r3, #12]
	ldr	r3, .L2+24
	ldr	r2, [r3]
	str	r2, [fp, #-116]
	ldr	r2, [r3, #4]
	str	r2, [fp, #-112]
	ldr	r2, [r3, #8]
	str	r2, [fp, #-108]
	ldr	r3, [r3, #12]
	str	r3, [fp, #-104]
	mov	ip, r4
	ldr	r3, [fp, #-116]
	eor	r2, ip, r3
	ldr	r0, .L2+8
	and	r0, r0, r3
	ldr	r1, .L2+12
	orr	r1, ip, r1
	mvn	r3, r2
	ldr	r2, .L2+12
	and	r2, r2, r3
	sub	r3, r1, r0
	eor	r9, r2, r3
	mov	ip, r5
	ldr	r3, [fp, #-112]
	eor	r2, ip, r3
	ldr	r0, .L2+8
	and	r0, r0, r3
	ldr	r1, .L2+12
	orr	r1, ip, r1
	mvn	r3, r2
	ldr	r2, .L2+12
	and	r2, r2, r3
	sub	r3, r1, r0
	eor	r8, r2, r3
	mov	ip, r6
	ldr	r3, [fp, #-108]
	eor	r2, ip, r3
	ldr	r0, .L2+8
	and	r0, r0, r3
	ldr	r1, .L2+12
	orr	r1, ip, r1
	mvn	r3, r2
	ldr	r2, .L2+12
	and	r2, r2, r3
	sub	r3, r1, r0
	eor	lr, r2, r3
	mov	r2, r7
	ldr	r3, [fp, #-104]
	eor	r1, r2, r3
	ldr	r0, .L2+8
	and	r0, r0, r3
	ldr	r3, .L2+12
	orr	r3, r2, r3
	mvn	r1, r1
	ldr	r2, .L2+12
	and	r2, r2, r1
	sub	r3, r3, r0
	eor	ip, r2, r3
	mov	r0, #0
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	mov	r0, r9
	mov	r1, r8
	mov	r2, lr
	mov	r3, ip
	str	r0, [fp, #-116]
	str	r1, [fp, #-112]
	str	r2, [fp, #-108]
	str	r3, [fp, #-104]
	ldr	r4, [fp, #-116]
	ldr	r5, [fp, #-112]
	ldr	r6, [fp, #-108]
	ldr	r7, [fp, #-104]
	ldr	r3, .L2+28
	mov	r2, r4
	str	r2, [r3]
	mov	r2, r5
	str	r2, [r3, #4]
	mov	r2, r6
	str	r2, [r3, #8]
	mov	r2, r7
	str	r2, [r3, #12]
	ldr	r3, .L2+32
	ldr	r4, [r3]
	ldr	r5, [r3, #4]
	ldr	r6, [r3, #8]
	ldr	r7, [r3, #12]
	ldr	r3, .L2+36
	ldr	r2, [r3]
	str	r2, [fp, #-116]
	ldr	r2, [r3, #4]
	str	r2, [fp, #-112]
	ldr	r2, [r3, #8]
	str	r2, [fp, #-108]
	ldr	r3, [r3, #12]
	str	r3, [fp, #-104]
	lsl	r3, r4, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-116]
	lsl	r3, r3, #16
	asr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	str	r3, [fp, #-152]
	mov	r3, r4
	asr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-116]
	asr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	asr	r10, r3, #16
	lsl	r3, r5, #16
	asr	r2, r3, #16
	ldr	r1, [fp, #-112]
	lsl	r3, r1, #16
	asr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	asr	r9, r3, #16
	mov	r3, r5
	asr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-112]
	asr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	asr	r8, r3, #16
	lsl	r3, r6, #16
	asr	r2, r3, #16
	ldr	r1, [fp, #-108]
	lsl	r3, r1, #16
	asr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	asr	lr, r3, #16
	mov	r3, r6
	asr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-108]
	asr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	asr	ip, r3, #16
	lsl	r3, r7, #16
	asr	r2, r3, #16
	ldr	r1, [fp, #-104]
	lsl	r3, r1, #16
	asr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	asr	r0, r3, #16
	mov	r3, r7
	asr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldr	r3, [fp, #-104]
	asr	r3, r3, #16
	lsl	r3, r3, #16
	asr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	asr	r1, r3, #16
	mov	r4, #0
	mov	r5, #0
	mov	r6, #0
	mov	r7, #0
	ldr	r3, [fp, #-152]
	lsl	r2, r3, #16
	lsr	r3, r4, #16
	orr	r3, r3, r2
	ror	r3, r3, #16
	mov	r4, r3
	lsl	r2, r10, #16
	lsl	r3, r4, #16
	lsr	r3, r3, #16
	orr	r3, r3, r2
	mov	r4, r3
	lsl	r2, r9, #16
	lsr	r3, r5, #16
	orr	r3, r3, r2
	ror	r3, r3, #16
	mov	r5, r3
	lsl	r2, r8, #16
	lsl	r3, r5, #16
	lsr	r3, r3, #16
	orr	r3, r3, r2
	mov	r5, r3
	lsl	r2, lr, #16
	lsr	r3, r6, #16
	orr	r3, r3, r2
	ror	r3, r3, #16
	mov	r6, r3
	lsl	r2, ip, #16
	lsl	r3, r6, #16
	lsr	r3, r3, #16
	orr	r3, r3, r2
	mov	r6, r3
	lsl	r2, r0, #16
	lsr	r3, r7, #16
	orr	r3, r3, r2
	ror	r3, r3, #16
	mov	r7, r3
	lsl	r2, r1, #16
	lsl	r3, r7, #16
	lsr	r3, r3, #16
	orr	r3, r3, r2
	mov	r7, r3
	str	r4, [fp, #-116]
	str	r5, [fp, #-112]
	str	r6, [fp, #-108]
	str	r7, [fp, #-104]
	ldr	r3, .L2+40
	ldr	r2, [fp, #-116]
	str	r2, [r3]
	ldr	r2, [fp, #-112]
	str	r2, [r3, #4]
	ldr	r2, [fp, #-108]
	str	r2, [r3, #8]
	ldr	r2, [fp, #-104]
	str	r2, [r3, #12]
	ldr	r3, .L2+44
	ldr	r4, [r3]
	ldr	r5, [r3, #4]
	ldr	r6, [r3, #8]
	ldr	r7, [r3, #12]
	ldr	r3, .L2+48
	ldr	r2, [r3]
	str	r2, [fp, #-116]
	ldr	r2, [r3, #4]
	str	r2, [fp, #-112]
	ldr	r2, [r3, #8]
	str	r2, [fp, #-108]
	ldr	r3, [r3, #12]
	str	r3, [fp, #-104]
	lsl	r3, r4, #16
	lsr	r2, r3, #16
	ldr	r3, [fp, #-116]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-152]
	lsr	r3, r4, #16
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r1, [fp, #-116]
	lsr	r3, r1, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r10, r3, #16
	lsl	r3, r5, #16
	lsr	r2, r3, #16
	ldr	r1, [fp, #-112]
	lsl	r3, r1, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r9, r3, #16
	lsr	r3, r5, #16
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r1, [fp, #-112]
	lsr	r3, r1, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r8, r3, #16
	lsl	r3, r6, #16
	lsr	r2, r3, #16
	ldr	r1, [fp, #-108]
	lsl	r3, r1, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	lr, r3, #16
	lsr	r3, r6, #16
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r1, [fp, #-108]
	lsr	r3, r1, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	ip, r3, #16
	lsl	r3, r7, #16
	lsr	r2, r3, #16
	ldr	r1, [fp, #-104]
	lsl	r3, r1, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r0, r3, #16
	lsr	r3, r7, #16
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldr	r1, [fp, #-104]
	lsr	r3, r1, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r1, r3, #16
	mov	r4, #0
	mov	r5, #0
	mov	r6, #0
	mov	r7, #0
	ldr	r3, [fp, #-152]
	lsl	r2, r3, #16
	lsr	r3, r4, #16
	orr	r3, r3, r2
	ror	r3, r3, #16
	mov	r4, r3
	lsl	r2, r10, #16
	lsl	r3, r4, #16
	lsr	r3, r3, #16
	orr	r3, r3, r2
	mov	r4, r3
	lsl	r2, r9, #16
	lsr	r3, r5, #16
	orr	r3, r3, r2
	ror	r3, r3, #16
	mov	r5, r3
	lsl	r2, r8, #16
	lsl	r3, r5, #16
	lsr	r3, r3, #16
	orr	r3, r3, r2
	mov	r5, r3
	lsl	r2, lr, #16
	lsr	r3, r6, #16
	orr	r3, r3, r2
	ror	r3, r3, #16
	mov	r6, r3
	lsl	r2, ip, #16
	lsl	r3, r6, #16
	lsr	r3, r3, #16
	orr	r3, r3, r2
	mov	r6, r3
	lsl	r2, r0, #16
	lsr	r3, r7, #16
	orr	r3, r3, r2
	ror	r3, r3, #16
	mov	r7, r3
	lsl	r2, r1, #16
	lsl	r3, r7, #16
	lsr	r3, r3, #16
	orr	r3, r3, r2
	mov	r7, r3
	str	r4, [fp, #-116]
	str	r5, [fp, #-112]
	str	r6, [fp, #-108]
	str	r7, [fp, #-104]
	ldr	r3, .L2+52
	ldr	r2, [fp, #-116]
	str	r2, [r3]
	ldr	r2, [fp, #-112]
	str	r2, [r3, #4]
	ldr	r2, [fp, #-108]
	str	r2, [r3, #8]
	ldr	r2, [fp, #-104]
	str	r2, [r3, #12]
	ldr	r3, .L2+56
	ldr	r4, [r3]
	ldr	r5, [r3, #4]
	ldr	r6, [r3, #8]
	ldr	r7, [r3, #12]
	ldr	ip, .L2+60
	ldr	r0, [ip]
	ldr	r1, [ip, #4]
	ldr	r2, [ip, #8]
	ldr	r3, [ip, #12]
	mov	lr, r4
	mov	ip, r0
	sub	r9, lr, ip
	mov	lr, r5
	mov	ip, r1
	sub	r8, lr, ip
	mov	lr, r6
	mov	ip, r2
	sub	lr, lr, ip
	mov	ip, r7
	sub	ip, ip, r3
	mov	r0, #0
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	mov	r0, r9
	mov	r1, r8
	mov	r2, lr
	mov	r3, ip
	mov	r4, r0
	mov	r5, r1
	mov	r6, r2
	mov	r7, r3
	ldr	r3, .L2+64
	mov	r2, r4
	str	r2, [r3]
	mov	r2, r5
	str	r2, [r3, #4]
	mov	r2, r6
	str	r2, [r3, #8]
	mov	r2, r7
	str	r2, [r3, #12]
	ldr	r3, .L2+68
	ldr	r4, [r3]
	ldr	r5, [r3, #4]
	ldr	r6, [r3, #8]
	ldr	r7, [r3, #12]
	ldr	ip, .L2+72
	ldr	r0, [ip]
	ldr	r1, [ip, #4]
	ldr	r2, [ip, #8]
	ldr	r3, [ip, #12]
	mov	lr, r4
	mov	ip, r0
	sub	r9, lr, ip
	mov	lr, r5
	mov	ip, r1
	sub	r8, lr, ip
	mov	lr, r6
	mov	ip, r2
	sub	lr, lr, ip
	mov	ip, r7
	sub	ip, ip, r3
	mov	r0, #0
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	mov	r0, r9
	mov	r1, r8
	mov	r2, lr
	mov	r3, ip
	mov	r4, r0
	mov	r5, r1
	mov	r6, r2
	mov	r7, r3
	ldr	r3, .L2+76
	mov	r2, r4
	str	r2, [r3]
	mov	r2, r5
	str	r2, [r3, #4]
	mov	r2, r6
	str	r2, [r3, #8]
	mov	r2, r7
	str	r2, [r3, #12]
	ldr	r3, .L2+80
	ldr	r4, [r3]
	ldr	r5, [r3, #4]
	ldr	r6, [r3, #8]
	ldr	r7, [r3, #12]
	ldr	r3, .L2+84
	ldr	r2, [r3]
	str	r2, [fp, #-116]
	ldr	r2, [r3, #4]
	str	r2, [fp, #-112]
	ldr	r2, [r3, #8]
	str	r2, [fp, #-108]
	ldr	r3, [r3, #12]
	str	r3, [fp, #-104]
	mov	r0, r4
	mov	r1, r5
	sub	r3, fp, #116
	ldmia	r3, {r2-r3}
	subs	ip, r0, r2
	str	ip, [fp, #-124]
	sbc	r3, r1, r3
	str	r3, [fp, #-120]
	mov	r0, r6
	mov	r1, r7
	sub	r3, fp, #108
	ldmia	r3, {r2-r3}
	subs	ip, r0, r2
	str	ip, [fp, #-132]
	sbc	r3, r1, r3
	str	r3, [fp, #-128]
	mov	r0, #0
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	sub	r1, fp, #124
	ldmia	r1, {r0-r1}
	sub	r3, fp, #132
	ldmia	r3, {r2-r3}
	mov	r4, r0
	mov	r5, r1
	mov	r6, r2
	mov	r7, r3
	ldr	r3, .L2+88
	mov	r2, r4
	str	r2, [r3]
	mov	r2, r5
	str	r2, [r3, #4]
	mov	r2, r6
	str	r2, [r3, #8]
	mov	r2, r7
	str	r2, [r3, #12]
	ldr	r3, .L2+92
	ldr	r2, [r3]
	str	r2, [fp, #-116]
	ldr	r2, [r3, #4]
	str	r2, [fp, #-112]
	ldr	r2, [r3, #8]
	str	r2, [fp, #-108]
	ldr	r3, [r3, #12]
	str	r3, [fp, #-104]
	ldr	r3, .L2+96
	ldr	r4, [r3]
	ldr	r5, [r3, #4]
	ldr	r6, [r3, #8]
	ldr	r7, [r3, #12]
	sub	r1, fp, #116
	ldmia	r1, {r0-r1}
	mov	r2, r4
	mov	r3, r5
	subs	ip, r0, r2
	str	ip, [fp, #-140]
	sbc	r3, r1, r3
	str	r3, [fp, #-136]
	sub	r1, fp, #108
	ldmia	r1, {r0-r1}
	mov	r2, r6
	mov	r3, r7
	subs	ip, r0, r2
	str	ip, [fp, #-148]
	sbc	r3, r1, r3
	str	r3, [fp, #-144]
	mov	r0, #0
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	sub	r1, fp, #140
	ldmia	r1, {r0-r1}
	sub	r3, fp, #148
	ldmia	r3, {r2-r3}
	mov	r4, r0
	mov	r5, r1
	mov	r6, r2
	mov	r7, r3
	ldr	r3, .L2+100
	mov	r2, r4
	str	r2, [r3]
	mov	r2, r5
	str	r2, [r3, #4]
	mov	r2, r6
	str	r2, [r3, #8]
	mov	r2, r7
	str	r2, [r3, #12]
	ldr	r3, .L2+104
	sub	ip, fp, #84
	ldm	r3, {r0, r1, r2, r3}
	stm	ip, {r0, r1, r2, r3}
	ldr	r3, .L2+108
	sub	ip, fp, #68
	ldm	r3, {r0, r1, r2, r3}
	stm	ip, {r0, r1, r2, r3}
	sub	r1, fp, #84
	ldmia	r1, {r0-r1}
	sub	r3, fp, #68
	ldmia	r3, {r2-r3}
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r4, r2
	mov	r5, r3
	sub	r1, fp, #76
	ldmia	r1, {r0-r1}
	sub	r3, fp, #60
	ldmia	r3, {r2-r3}
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	str	r4, [fp, #-100]
	str	r5, [fp, #-96]
	str	r2, [fp, #-92]
	str	r3, [fp, #-88]
	sub	ip, fp, #52
	sub	r3, fp, #100
	ldm	r3, {r0, r1, r2, r3}
	stm	ip, {r0, r1, r2, r3}
	ldr	r3, .L2+112
	mov	ip, r3
	sub	r3, fp, #52
	ldm	r3, {r0, r1, r2, r3}
	stm	ip, {r0, r1, r2, r3}
	nop
	sub	sp, fp, #32
	@ sp needed
	pop	{r4, r5, r6, r7, r8, r9, r10, fp, pc}
.L3:
	.align	2
.L2:
	.word	g_vqi1
	.word	g_vqi2
	.word	2139062143
	.word	-2139062144
	.word	g_vqi0
	.word	g_uvqi1
	.word	g_uvqi2
	.word	g_uvqi0
	.word	g_vhi1
	.word	g_vhi2
	.word	g_vhi0
	.word	g_uvhi1
	.word	g_uvhi2
	.word	g_uvhi0
	.word	g_vsi1
	.word	g_vsi2
	.word	g_vsi0
	.word	g_uvsi1
	.word	g_uvsi2
	.word	g_uvsi0
	.word	g_vdi1
	.word	g_vdi2
	.word	g_vdi0
	.word	g_uvdi1
	.word	g_uvdi2
	.word	g_uvdi0
	.word	g_vdf1
	.word	g_vdf2
	.word	g_vdf0
	.size	sub1, .-sub1
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
