	.file	"147128.c"
	.intel_syntax noprefix
	.text
	.globl	registerPC_CPU
	.bss
	.align 4
	.type	registerPC_CPU, @object
	.size	registerPC_CPU, 4
registerPC_CPU:
	.zero	4
	.globl	registerAccumulator_CPU
	.align 4
	.type	registerAccumulator_CPU, @object
	.size	registerAccumulator_CPU, 4
registerAccumulator_CPU:
	.zero	4
	.globl	registerIR_CPU
	.align 8
	.type	registerIR_CPU, @object
	.size	registerIR_CPU, 12
registerIR_CPU:
	.zero	12
	.globl	registerPSW_CPU
	.data
	.align 4
	.type	registerPSW_CPU, @object
	.size	registerPSW_CPU, 4
registerPSW_CPU:
	.long	128
	.globl	registerMAR_CPU
	.bss
	.align 4
	.type	registerMAR_CPU, @object
	.size	registerMAR_CPU, 4
registerMAR_CPU:
	.zero	4
	.globl	registerMBR_CPU
	.align 8
	.type	registerMBR_CPU, @object
	.size	registerMBR_CPU, 12
registerMBR_CPU:
	.zero	12
	.globl	registerA_CPU
	.align 4
	.type	registerA_CPU, @object
	.size	registerA_CPU, 4
registerA_CPU:
	.zero	4
	.globl	registerB_CPU
	.align 4
	.type	registerB_CPU, @object
	.size	registerB_CPU, 4
registerB_CPU:
	.zero	4
	.globl	interruptLines_CPU
	.align 4
	.type	interruptLines_CPU, @object
	.size	interruptLines_CPU, 4
interruptLines_CPU:
	.zero	4
	.globl	interruptVectorTable
	.align 32
	.type	interruptVectorTable, @object
	.size	interruptVectorTable, 40
interruptVectorTable:
	.zero	40
	.globl	pswmask
	.data
	.align 16
	.type	pswmask, @object
	.size	pswmask, 17
pswmask:
	.string	"----------------"
	.text
	.globl	Processor_InitializeInterruptVectorTable
	.type	Processor_InitializeInterruptVectorTable, @function
Processor_InitializeInterruptVectorTable:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L2
.L3:
	mov	eax, DWORD PTR -20[rbp]
	lea	ecx, -1[rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, interruptVectorTable[rip]
	mov	DWORD PTR [rdx+rax], ecx
	add	DWORD PTR -4[rbp], 1
.L2:
	cmp	DWORD PTR -4[rbp], 9
	jle	.L3
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR interruptVectorTable[rip+8], eax
	mov	eax, DWORD PTR -20[rbp]
	add	eax, 2
	mov	DWORD PTR interruptVectorTable[rip+24], eax
	mov	eax, DWORD PTR -20[rbp]
	add	eax, 4
	mov	DWORD PTR interruptVectorTable[rip+36], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	Processor_InitializeInterruptVectorTable, .-Processor_InitializeInterruptVectorTable
	.globl	Processor_InstructionCycleLoop
	.type	Processor_InstructionCycleLoop, @function
Processor_InstructionCycleLoop:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	jmp	.L5
.L6:
	mov	eax, 0
	call	Processor_FetchInstruction
	mov	eax, 0
	call	Processor_DecodeAndExecuteInstruction
	mov	eax, DWORD PTR interruptLines_CPU[rip]
	test	eax, eax
	je	.L5
	mov	edi, 15
	call	Processor_PSW_BitState
	test	eax, eax
	jne	.L5
	mov	eax, 0
	call	Processor_ManageInterrupts
.L5:
	mov	edi, 0
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L6
	call	__utac_acc__Aspect__5@PLT
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	Processor_InstructionCycleLoop, .-Processor_InstructionCycleLoop
	.globl	Processor_FetchInstruction
	.type	Processor_FetchInstruction, @function
Processor_FetchInstruction:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__utac_acc__Aspect__1@PLT
	mov	eax, DWORD PTR registerPC_CPU[rip]
	mov	DWORD PTR registerMAR_CPU[rip], eax
	mov	esi, 1
	mov	edi, 2
	call	Buses_write_AddressBus_From_To@PLT
	mov	eax, 0
	call	MMU_readMemory@PLT
	cmp	eax, 1
	jne	.L8
	mov	rax, QWORD PTR registerMBR_CPU[rip]
	mov	QWORD PTR registerIR_CPU[rip], rax
	mov	eax, DWORD PTR registerMBR_CPU[rip+8]
	mov	DWORD PTR registerIR_CPU[rip+8], eax
	mov	edi, 104
	call	ComputerSystem_ShowTime@PLT
	mov	ecx, DWORD PTR registerIR_CPU[rip+8]
	mov	edx, DWORD PTR registerIR_CPU[rip+4]
	movzx	eax, BYTE PTR registerIR_CPU[rip]
	movsx	eax, al
	mov	r8d, ecx
	mov	ecx, edx
	mov	edx, eax
	mov	esi, 104
	mov	edi, 1
	mov	eax, 0
	call	ComputerSystem_DebugMessage@PLT
	jmp	.L10
.L8:
	mov	esi, 104
	mov	edi, 2
	mov	eax, 0
	call	ComputerSystem_DebugMessage@PLT
.L10:
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	Processor_FetchInstruction, .-Processor_FetchInstruction
	.globl	Processor_DecodeAndExecuteInstruction
	.type	Processor_DecodeAndExecuteInstruction, @function
Processor_DecodeAndExecuteInstruction:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	push	r14
	push	r13
	push	r12
	push	rbx
	sub	rsp, 16
	.cfi_offset 14, -24
	.cfi_offset 13, -32
	.cfi_offset 12, -40
	.cfi_offset 3, -48
	mov	edi, 3
	call	Processor_DeactivatePSW_Bit
	movzx	eax, BYTE PTR registerIR_CPU[rip]
	movsx	eax, al
	sub	eax, 97
	cmp	eax, 25
	ja	.L12
	mov	eax, eax
	lea	rdx, 0[0+rax*4]
	lea	rax, .L14[rip]
	mov	eax, DWORD PTR [rdx+rax]
	cdqe
	lea	rdx, .L14[rip]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L14:
	.long	.L27-.L14
	.long	.L12-.L14
	.long	.L12-.L14
	.long	.L26-.L14
	.long	.L12-.L14
	.long	.L12-.L14
	.long	.L12-.L14
	.long	.L25-.L14
	.long	.L24-.L14
	.long	.L23-.L14
	.long	.L12-.L14
	.long	.L12-.L14
	.long	.L22-.L14
	.long	.L21-.L14
	.long	.L20-.L14
	.long	.L12-.L14
	.long	.L12-.L14
	.long	.L19-.L14
	.long	.L18-.L14
	.long	.L17-.L14
	.long	.L12-.L14
	.long	.L12-.L14
	.long	.L16-.L14
	.long	.L12-.L14
	.long	.L15-.L14
	.long	.L13-.L14
	.text
.L27:
	mov	edx, DWORD PTR registerIR_CPU[rip+4]
	mov	eax, DWORD PTR registerIR_CPU[rip+8]
	add	eax, edx
	mov	DWORD PTR registerAccumulator_CPU[rip], eax
	mov	edx, DWORD PTR registerIR_CPU[rip+8]
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	esi, edx
	mov	edi, eax
	call	Processor_CheckOverflow
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L18:
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	edx, DWORD PTR registerIR_CPU[rip+8]
	sub	eax, edx
	mov	DWORD PTR registerAccumulator_CPU[rip], eax
	mov	eax, DWORD PTR registerIR_CPU[rip+8]
	neg	eax
	mov	edx, eax
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	esi, edx
	mov	edi, eax
	call	Processor_CheckOverflow
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L26:
	mov	eax, DWORD PTR registerIR_CPU[rip+8]
	test	eax, eax
	jne	.L29
	mov	edi, 0
	call	Processor_RaiseException
	jmp	.L28
.L29:
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	ecx, DWORD PTR registerIR_CPU[rip+8]
	cdq
	idiv	ecx
	mov	DWORD PTR registerAccumulator_CPU[rip], eax
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L17:
	mov	edi, 2
	call	Processor_RaiseInterrupt
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	DWORD PTR registerA_CPU[rip], eax
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L21:
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L23:
	mov	edx, DWORD PTR registerIR_CPU[rip+4]
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, edx
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L13:
	mov	edi, 1
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L31
	mov	edx, DWORD PTR registerIR_CPU[rip+4]
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, edx
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L31:
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L16:
	mov	eax, DWORD PTR registerAccumulator_CPU[rip]
	mov	DWORD PTR registerMBR_CPU[rip+8], eax
	mov	eax, DWORD PTR registerMBR_CPU[rip+8]
	mov	DWORD PTR registerMBR_CPU[rip+4], eax
	mov	eax, DWORD PTR registerMBR_CPU[rip+4]
	mov	BYTE PTR registerMBR_CPU[rip], al
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	DWORD PTR registerMAR_CPU[rip], eax
	mov	esi, 0
	mov	edi, 2
	call	Buses_write_DataBus_From_To@PLT
	mov	esi, 1
	mov	edi, 2
	call	Buses_write_AddressBus_From_To@PLT
	mov	eax, 0
	call	MMU_writeMemory@PLT
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L19:
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	DWORD PTR registerMAR_CPU[rip], eax
	mov	esi, 1
	mov	edi, 2
	call	Buses_write_AddressBus_From_To@PLT
	mov	eax, 0
	call	MMU_readMemory@PLT
	mov	eax, DWORD PTR registerMBR_CPU[rip+4]
	mov	DWORD PTR registerAccumulator_CPU[rip], eax
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L22:
	mov	eax, DWORD PTR registerIR_CPU[rip+8]
	mov	DWORD PTR registerMAR_CPU[rip], eax
	mov	esi, 1
	mov	edi, 2
	call	Buses_write_AddressBus_From_To@PLT
	mov	eax, 0
	call	MMU_readMemory@PLT
	mov	edx, DWORD PTR registerIR_CPU[rip+4]
	mov	eax, DWORD PTR registerMBR_CPU[rip+4]
	add	eax, edx
	mov	DWORD PTR registerAccumulator_CPU[rip], eax
	mov	edx, DWORD PTR registerMBR_CPU[rip+4]
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	esi, edx
	mov	edi, eax
	call	Processor_CheckOverflow
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L24:
	mov	eax, DWORD PTR registerAccumulator_CPU[rip]
	mov	DWORD PTR -36[rbp], eax
	mov	edx, DWORD PTR registerIR_CPU[rip+4]
	mov	eax, DWORD PTR registerAccumulator_CPU[rip]
	add	eax, edx
	mov	DWORD PTR registerAccumulator_CPU[rip], eax
	mov	edx, DWORD PTR registerIR_CPU[rip+4]
	mov	eax, DWORD PTR -36[rbp]
	mov	esi, edx
	mov	edi, eax
	call	Processor_CheckOverflow
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L28
.L25:
	mov	edi, 7
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L33
	mov	edi, 0
	call	Processor_ActivatePSW_Bit
	jmp	.L28
.L33:
	mov	edi, 1
	call	Processor_RaiseException
	jmp	.L28
.L20:
	mov	edi, 7
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L35
	mov	eax, 0
	call	Processor_ShowPSW
	mov	r12, rax
	mov	r14d, DWORD PTR registerPSW_CPU[rip]
	mov	r13d, DWORD PTR registerAccumulator_CPU[rip]
	mov	ebx, DWORD PTR registerPC_CPU[rip]
	mov	eax, 0
	call	OperatingSystem_GetExecutingProcessID@PLT
	sub	rsp, 8
	push	r12
	mov	r9d, r14d
	mov	r8d, r13d
	mov	ecx, ebx
	mov	edx, eax
	mov	esi, 104
	mov	edi, 130
	mov	eax, 0
	call	ComputerSystem_DebugMessage@PLT
	add	rsp, 16
	mov	eax, DWORD PTR registerIR_CPU[rip+4]
	mov	edi, eax
	call	OperatingSystem_InterruptLogic@PLT
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	mov	eax, 0
	call	Processor_UpdatePSW
	call	__utac_acc__Aspect__2@PLT
	jmp	.L11
.L35:
	mov	edi, 1
	call	Processor_RaiseException
	jmp	.L28
.L15:
	mov	edi, 7
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L37
	mov	edi, 299
	call	Processor_CopyFromSystemStack
	mov	DWORD PTR registerPC_CPU[rip], eax
	mov	edi, 298
	call	Processor_CopyFromSystemStack
	mov	DWORD PTR registerPSW_CPU[rip], eax
	jmp	.L28
.L37:
	mov	edi, 1
	call	Processor_RaiseException
	jmp	.L28
.L12:
	mov	eax, DWORD PTR registerPC_CPU[rip]
	add	eax, 1
	mov	DWORD PTR registerPC_CPU[rip], eax
	mov	edi, 3
	call	Processor_RaiseException
	nop
.L28:
	mov	eax, 0
	call	Processor_UpdatePSW
	mov	eax, 0
	call	Processor_ShowPSW
	mov	r12, rax
	mov	r14d, DWORD PTR registerPSW_CPU[rip]
	mov	r13d, DWORD PTR registerAccumulator_CPU[rip]
	mov	ebx, DWORD PTR registerPC_CPU[rip]
	mov	eax, 0
	call	OperatingSystem_GetExecutingProcessID@PLT
	sub	rsp, 8
	push	r12
	mov	r9d, r14d
	mov	r8d, r13d
	mov	ecx, ebx
	mov	edx, eax
	mov	esi, 104
	mov	edi, 130
	mov	eax, 0
	call	ComputerSystem_DebugMessage@PLT
	add	rsp, 16
	call	__utac_acc__Aspect__2@PLT
.L11:
	lea	rsp, -32[rbp]
	pop	rbx
	pop	r12
	pop	r13
	pop	r14
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	Processor_DecodeAndExecuteInstruction, .-Processor_DecodeAndExecuteInstruction
	.globl	Processor_ManageInterrupts
	.type	Processor_ManageInterrupts, @function
Processor_ManageInterrupts:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], 0
	jmp	.L40
.L43:
	mov	eax, DWORD PTR -4[rbp]
	mov	edi, eax
	call	Processor_GetInterruptLineStatus
	test	eax, eax
	je	.L41
	mov	eax, DWORD PTR -4[rbp]
	mov	edi, eax
	call	Processor_ACKInterrupt
	mov	eax, DWORD PTR registerPC_CPU[rip]
	mov	esi, eax
	mov	edi, 299
	call	Processor_CopyInSystemStack
	mov	eax, DWORD PTR registerPSW_CPU[rip]
	mov	esi, eax
	mov	edi, 298
	call	Processor_CopyInSystemStack
	mov	edi, 7
	call	Processor_ActivatePSW_Bit
	mov	edi, 15
	call	Processor_ActivatePSW_Bit
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, interruptVectorTable[rip]
	mov	eax, DWORD PTR [rdx+rax]
	mov	DWORD PTR registerPC_CPU[rip], eax
	jmp	.L42
.L41:
	add	DWORD PTR -4[rbp], 1
.L40:
	cmp	DWORD PTR -4[rbp], 9
	jle	.L43
	nop
.L42:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	Processor_ManageInterrupts, .-Processor_ManageInterrupts
	.globl	Processor_UpdatePSW
	.type	Processor_UpdatePSW, @function
Processor_UpdatePSW:
.LFB5:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR registerAccumulator_CPU[rip]
	test	eax, eax
	jne	.L45
	mov	edi, 1
	call	Processor_PSW_BitState
	test	eax, eax
	jne	.L46
	mov	edi, 1
	call	Processor_ActivatePSW_Bit
	jmp	.L46
.L45:
	mov	edi, 1
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L46
	mov	edi, 1
	call	Processor_DeactivatePSW_Bit
.L46:
	mov	eax, DWORD PTR registerAccumulator_CPU[rip]
	test	eax, eax
	jns	.L47
	mov	edi, 2
	call	Processor_PSW_BitState
	test	eax, eax
	jne	.L49
	mov	edi, 2
	call	Processor_ActivatePSW_Bit
	jmp	.L49
.L47:
	mov	edi, 2
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L49
	mov	edi, 2
	call	Processor_DeactivatePSW_Bit
.L49:
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	Processor_UpdatePSW, .-Processor_UpdatePSW
	.globl	Processor_CheckOverflow
	.type	Processor_CheckOverflow, @function
Processor_CheckOverflow:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	cmp	DWORD PTR -4[rbp], 0
	jle	.L51
	cmp	DWORD PTR -8[rbp], 0
	jle	.L51
	mov	eax, DWORD PTR registerAccumulator_CPU[rip]
	test	eax, eax
	js	.L52
.L51:
	cmp	DWORD PTR -4[rbp], 0
	jns	.L54
	cmp	DWORD PTR -8[rbp], 0
	jns	.L54
	mov	eax, DWORD PTR registerAccumulator_CPU[rip]
	test	eax, eax
	jle	.L54
.L52:
	mov	edi, 3
	call	Processor_ActivatePSW_Bit
.L54:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	Processor_CheckOverflow, .-Processor_CheckOverflow
	.globl	Processor_CopyInSystemStack
	.type	Processor_CopyInSystemStack, @function
Processor_CopyInSystemStack:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	mov	DWORD PTR registerMBR_CPU[rip+8], eax
	mov	eax, DWORD PTR registerMBR_CPU[rip+8]
	mov	DWORD PTR registerMBR_CPU[rip+4], eax
	mov	eax, DWORD PTR registerMBR_CPU[rip+4]
	mov	BYTE PTR registerMBR_CPU[rip], al
	mov	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR registerMAR_CPU[rip], eax
	mov	esi, 0
	mov	edi, 2
	call	Buses_write_AddressBus_From_To@PLT
	mov	esi, 0
	mov	edi, 2
	call	Buses_write_DataBus_From_To@PLT
	mov	eax, 0
	call	MainMemory_writeMemory@PLT
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	Processor_CopyInSystemStack, .-Processor_CopyInSystemStack
	.globl	Processor_CopyFromSystemStack
	.type	Processor_CopyFromSystemStack, @function
Processor_CopyFromSystemStack:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR -20[rbp]
	mov	DWORD PTR registerMAR_CPU[rip], eax
	mov	esi, 0
	mov	edi, 2
	call	Buses_write_AddressBus_From_To@PLT
	mov	eax, 0
	call	MainMemory_readMemory@PLT
	mov	eax, DWORD PTR registerMBR_CPU[rip+4]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	Processor_CopyFromSystemStack, .-Processor_CopyFromSystemStack
	.globl	Processor_RaiseInterrupt
	.type	Processor_RaiseInterrupt, @function
Processor_RaiseInterrupt:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 1
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	DWORD PTR -4[rbp], cl
	mov	eax, DWORD PTR interruptLines_CPU[rip]
	or	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR interruptLines_CPU[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	Processor_RaiseInterrupt, .-Processor_RaiseInterrupt
	.globl	Processor_ACKInterrupt
	.type	Processor_ACKInterrupt, @function
Processor_ACKInterrupt:
.LFB10:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 1
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	DWORD PTR -4[rbp], cl
	not	DWORD PTR -4[rbp]
	mov	eax, DWORD PTR interruptLines_CPU[rip]
	and	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR interruptLines_CPU[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE10:
	.size	Processor_ACKInterrupt, .-Processor_ACKInterrupt
	.globl	Processor_GetInterruptLineStatus
	.type	Processor_GetInterruptLineStatus, @function
Processor_GetInterruptLineStatus:
.LFB11:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -8[rbp], 1
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	DWORD PTR -8[rbp], cl
	mov	eax, DWORD PTR interruptLines_CPU[rip]
	and	eax, DWORD PTR -8[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE11:
	.size	Processor_GetInterruptLineStatus, .-Processor_GetInterruptLineStatus
	.globl	Processor_ActivatePSW_Bit
	.type	Processor_ActivatePSW_Bit, @function
Processor_ActivatePSW_Bit:
.LFB12:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 1
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	DWORD PTR -4[rbp], cl
	mov	eax, DWORD PTR registerPSW_CPU[rip]
	or	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR registerPSW_CPU[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE12:
	.size	Processor_ActivatePSW_Bit, .-Processor_ActivatePSW_Bit
	.globl	Processor_DeactivatePSW_Bit
	.type	Processor_DeactivatePSW_Bit, @function
Processor_DeactivatePSW_Bit:
.LFB13:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -4[rbp], 1
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	DWORD PTR -4[rbp], cl
	not	DWORD PTR -4[rbp]
	mov	eax, DWORD PTR registerPSW_CPU[rip]
	and	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR registerPSW_CPU[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE13:
	.size	Processor_DeactivatePSW_Bit, .-Processor_DeactivatePSW_Bit
	.globl	Processor_PSW_BitState
	.type	Processor_PSW_BitState, @function
Processor_PSW_BitState:
.LFB14:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -8[rbp], 1
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	DWORD PTR -8[rbp], cl
	mov	eax, DWORD PTR registerPSW_CPU[rip]
	and	eax, DWORD PTR -8[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -20[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE14:
	.size	Processor_PSW_BitState, .-Processor_PSW_BitState
	.globl	Processor_GetMAR
	.type	Processor_GetMAR, @function
Processor_GetMAR:
.LFB15:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR registerMAR_CPU[rip]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE15:
	.size	Processor_GetMAR, .-Processor_GetMAR
	.globl	Processor_SetMAR
	.type	Processor_SetMAR, @function
Processor_SetMAR:
.LFB16:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR registerMAR_CPU[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE16:
	.size	Processor_SetMAR, .-Processor_SetMAR
	.globl	Processor_GetMBR
	.type	Processor_GetMBR, @function
Processor_GetMBR:
.LFB17:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, 12
	lea	rsi, registerMBR_CPU[rip]
	mov	rdi, rax
	call	memcpy@PLT
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE17:
	.size	Processor_GetMBR, .-Processor_GetMBR
	.globl	Processor_SetMBR
	.type	Processor_SetMBR, @function
Processor_SetMBR:
.LFB18:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	edx, 12
	mov	rsi, rax
	lea	rdi, registerMBR_CPU[rip]
	call	memcpy@PLT
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE18:
	.size	Processor_SetMBR, .-Processor_SetMBR
	.globl	Processor_GetMBR_Value
	.type	Processor_GetMBR_Value, @function
Processor_GetMBR_Value:
.LFB19:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	movzx	eax, BYTE PTR registerMBR_CPU[rip]
	movsx	eax, al
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE19:
	.size	Processor_GetMBR_Value, .-Processor_GetMBR_Value
	.globl	Processor_SetAccumulator
	.type	Processor_SetAccumulator, @function
Processor_SetAccumulator:
.LFB20:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR registerAccumulator_CPU[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE20:
	.size	Processor_SetAccumulator, .-Processor_SetAccumulator
	.globl	Processor_SetPC
	.type	Processor_SetPC, @function
Processor_SetPC:
.LFB21:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR registerPC_CPU[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE21:
	.size	Processor_SetPC, .-Processor_SetPC
	.globl	Processor_GetAccumulator
	.type	Processor_GetAccumulator, @function
Processor_GetAccumulator:
.LFB22:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR registerAccumulator_CPU[rip]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE22:
	.size	Processor_GetAccumulator, .-Processor_GetAccumulator
	.globl	Processor_GetRegisterA
	.type	Processor_GetRegisterA, @function
Processor_GetRegisterA:
.LFB23:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR registerA_CPU[rip]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE23:
	.size	Processor_GetRegisterA, .-Processor_GetRegisterA
	.globl	Processor_GetRegisterB
	.type	Processor_GetRegisterB, @function
Processor_GetRegisterB:
.LFB24:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR registerB_CPU[rip]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE24:
	.size	Processor_GetRegisterB, .-Processor_GetRegisterB
	.globl	Processor_SetPSW
	.type	Processor_SetPSW, @function
Processor_SetPSW:
.LFB25:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR registerPSW_CPU[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE25:
	.size	Processor_SetPSW, .-Processor_SetPSW
	.globl	Processor_GetPSW
	.type	Processor_GetPSW, @function
Processor_GetPSW:
.LFB26:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR registerPSW_CPU[rip]
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE26:
	.size	Processor_GetPSW, .-Processor_GetPSW
	.globl	Processor_ShowPSW
	.type	Processor_ShowPSW, @function
Processor_ShowPSW:
.LFB27:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	movabs	rax, 3255307777713450285
	movabs	rdx, 3255307777713450285
	mov	QWORD PTR pswmask[rip], rax
	mov	QWORD PTR pswmask[rip+8], rdx
	mov	BYTE PTR pswmask[rip+16], 0
	lea	rdi, pswmask[rip]
	call	strlen@PLT
	sub	eax, 1
	mov	DWORD PTR -12[rbp], eax
	mov	edi, 7
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L85
	mov	eax, DWORD PTR -12[rbp]
	sub	eax, 7
	cdqe
	lea	rdx, pswmask[rip]
	mov	BYTE PTR [rax+rdx], 88
.L85:
	mov	edi, 3
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L86
	mov	eax, DWORD PTR -12[rbp]
	sub	eax, 3
	cdqe
	lea	rdx, pswmask[rip]
	mov	BYTE PTR [rax+rdx], 70
.L86:
	mov	edi, 2
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L87
	mov	eax, DWORD PTR -12[rbp]
	sub	eax, 2
	cdqe
	lea	rdx, pswmask[rip]
	mov	BYTE PTR [rax+rdx], 78
.L87:
	mov	edi, 1
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L88
	mov	eax, DWORD PTR -12[rbp]
	sub	eax, 1
	cdqe
	lea	rdx, pswmask[rip]
	mov	BYTE PTR [rax+rdx], 90
.L88:
	mov	edi, 0
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L89
	mov	eax, DWORD PTR -12[rbp]
	cdqe
	lea	rdx, pswmask[rip]
	mov	BYTE PTR [rax+rdx], 83
.L89:
	mov	edi, 15
	call	Processor_PSW_BitState
	test	eax, eax
	je	.L90
	mov	eax, DWORD PTR -12[rbp]
	sub	eax, 15
	cdqe
	lea	rdx, pswmask[rip]
	mov	BYTE PTR [rax+rdx], 77
.L90:
	lea	rax, pswmask[rip]
	mov	QWORD PTR -8[rbp], rax
	mov	rax, QWORD PTR -8[rbp]
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE27:
	.size	Processor_ShowPSW, .-Processor_ShowPSW
	.globl	Processor_RaiseException
	.type	Processor_RaiseException, @function
Processor_RaiseException:
.LFB28:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 8
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	DWORD PTR registerB_CPU[rip], eax
	mov	edi, 6
	call	Processor_RaiseInterrupt
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE28:
	.size	Processor_RaiseException, .-Processor_RaiseException
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"147128.c"
	.text
	.comm	registerPC_CPU,4,4
	.comm	registerAccumulator_CPU,4,4
	.comm	registerIR_CPU,12,4
	.global	registerPSW_CPU
	.data
	.align	2
	.type	registerPSW_CPU, %object
	.size	registerPSW_CPU, 4
registerPSW_CPU:
	.word	128
	.comm	registerMAR_CPU,4,4
	.comm	registerMBR_CPU,12,4
	.comm	registerA_CPU,4,4
	.comm	registerB_CPU,4,4
	.comm	interruptLines_CPU,4,4
	.comm	interruptVectorTable,40,4
	.global	pswmask
	.align	2
	.type	pswmask, %object
	.size	pswmask, 17
pswmask:
	.ascii	"----------------\000"
	.text
	.align	2
	.global	Processor_InitializeInterruptVectorTable
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_InitializeInterruptVectorTable, %function
Processor_InitializeInterruptVectorTable:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L2
.L3:
	ldr	r3, [fp, #-16]
	sub	r2, r3, #1
	ldr	r1, .L4
	ldr	r3, [fp, #-8]
	str	r2, [r1, r3, lsl #2]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L2:
	ldr	r3, [fp, #-8]
	cmp	r3, #9
	ble	.L3
	ldr	r2, .L4
	ldr	r3, [fp, #-16]
	str	r3, [r2, #8]
	ldr	r3, [fp, #-16]
	add	r3, r3, #2
	ldr	r2, .L4
	str	r3, [r2, #24]
	ldr	r3, [fp, #-16]
	add	r3, r3, #4
	ldr	r2, .L4
	str	r3, [r2, #36]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L5:
	.align	2
.L4:
	.word	interruptVectorTable
	.size	Processor_InitializeInterruptVectorTable, .-Processor_InitializeInterruptVectorTable
	.align	2
	.global	Processor_InstructionCycleLoop
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_InstructionCycleLoop, %function
Processor_InstructionCycleLoop:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	b	.L7
.L8:
	bl	Processor_FetchInstruction
	bl	Processor_DecodeAndExecuteInstruction
	ldr	r3, .L9
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L7
	mov	r0, #15
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	bne	.L7
	bl	Processor_ManageInterrupts
.L7:
	mov	r0, #0
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	bl	__utac_acc__Aspect__5
	nop
	pop	{fp, pc}
.L10:
	.align	2
.L9:
	.word	interruptLines_CPU
	.size	Processor_InstructionCycleLoop, .-Processor_InstructionCycleLoop
	.align	2
	.global	Processor_FetchInstruction
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_FetchInstruction, %function
Processor_FetchInstruction:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	bl	__utac_acc__Aspect__1
	ldr	r3, .L15
	ldr	r3, [r3]
	ldr	r2, .L15+4
	str	r3, [r2]
	mov	r1, #1
	mov	r0, #2
	bl	Buses_write_AddressBus_From_To
	bl	MMU_readMemory
	mov	r3, r0
	cmp	r3, #1
	bne	.L12
	ldr	r3, .L15+8
	ldr	r2, .L15+12
	ldm	r2, {r0, r1, r2}
	stm	r3, {r0, r1, r2}
	mov	r0, #104
	bl	ComputerSystem_ShowTime
	ldr	r3, .L15+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	mov	r1, r3
	ldr	r3, .L15+8
	ldr	r2, [r3, #4]
	ldr	r3, .L15+8
	ldr	r3, [r3, #8]
	str	r3, [sp]
	mov	r3, r2
	mov	r2, r1
	mov	r1, #104
	mov	r0, #1
	bl	ComputerSystem_DebugMessage
	b	.L14
.L12:
	mov	r1, #104
	mov	r0, #2
	bl	ComputerSystem_DebugMessage
.L14:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L16:
	.align	2
.L15:
	.word	registerPC_CPU
	.word	registerMAR_CPU
	.word	registerIR_CPU
	.word	registerMBR_CPU
	.size	Processor_FetchInstruction, .-Processor_FetchInstruction
	.global	__aeabi_idiv
	.align	2
	.global	Processor_DecodeAndExecuteInstruction
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_DecodeAndExecuteInstruction, %function
Processor_DecodeAndExecuteInstruction:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #24
	mov	r0, #3
	bl	Processor_DeactivatePSW_Bit
	ldr	r3, .L45
	ldrb	r3, [r3]	@ zero_extendqisi2
	sub	r3, r3, #97
	cmp	r3, #25
	ldrls	pc, [pc, r3, asl #2]
	b	.L18
.L20:
	.word	.L33
	.word	.L18
	.word	.L18
	.word	.L32
	.word	.L18
	.word	.L18
	.word	.L18
	.word	.L31
	.word	.L30
	.word	.L29
	.word	.L18
	.word	.L18
	.word	.L28
	.word	.L27
	.word	.L26
	.word	.L18
	.word	.L18
	.word	.L25
	.word	.L24
	.word	.L23
	.word	.L18
	.word	.L18
	.word	.L22
	.word	.L18
	.word	.L21
	.word	.L19
.L33:
	ldr	r3, .L45
	ldr	r2, [r3, #4]
	ldr	r3, .L45
	ldr	r3, [r3, #8]
	add	r3, r2, r3
	ldr	r2, .L45+4
	str	r3, [r2]
	ldr	r3, .L45
	ldr	r3, [r3, #4]
	ldr	r2, .L45
	ldr	r2, [r2, #8]
	mov	r1, r2
	mov	r0, r3
	bl	Processor_CheckOverflow
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L24:
	ldr	r3, .L45
	ldr	r2, [r3, #4]
	ldr	r3, .L45
	ldr	r3, [r3, #8]
	sub	r3, r2, r3
	ldr	r2, .L45+4
	str	r3, [r2]
	ldr	r3, .L45
	ldr	r2, [r3, #4]
	ldr	r3, .L45
	ldr	r3, [r3, #8]
	rsb	r3, r3, #0
	mov	r1, r3
	mov	r0, r2
	bl	Processor_CheckOverflow
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L32:
	ldr	r3, .L45
	ldr	r3, [r3, #8]
	cmp	r3, #0
	bne	.L35
	mov	r0, #0
	bl	Processor_RaiseException
	b	.L34
.L35:
	ldr	r3, .L45
	ldr	r3, [r3, #4]
	ldr	r2, .L45
	ldr	r2, [r2, #8]
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_idiv
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L45+4
	str	r2, [r3]
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L23:
	mov	r0, #2
	bl	Processor_RaiseInterrupt
	ldr	r3, .L45
	ldr	r3, [r3, #4]
	ldr	r2, .L45+12
	str	r3, [r2]
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L27:
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L29:
	ldr	r3, .L45
	ldr	r2, [r3, #4]
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r2, r3
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L19:
	mov	r0, #1
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L45
	ldr	r2, [r3, #4]
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r2, r3
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L37:
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L22:
	ldr	r3, .L45+4
	ldr	r3, [r3]
	ldr	r2, .L45+16
	str	r3, [r2, #8]
	ldr	r3, .L45+16
	ldr	r3, [r3, #8]
	ldr	r2, .L45+16
	str	r3, [r2, #4]
	ldr	r3, .L45+16
	ldr	r3, [r3, #4]
	and	r2, r3, #255
	ldr	r3, .L45+16
	strb	r2, [r3]
	ldr	r3, .L45
	ldr	r3, [r3, #4]
	ldr	r2, .L45+20
	str	r3, [r2]
	mov	r1, #0
	mov	r0, #2
	bl	Buses_write_DataBus_From_To
	mov	r1, #1
	mov	r0, #2
	bl	Buses_write_AddressBus_From_To
	bl	MMU_writeMemory
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L25:
	ldr	r3, .L45
	ldr	r3, [r3, #4]
	ldr	r2, .L45+20
	str	r3, [r2]
	mov	r1, #1
	mov	r0, #2
	bl	Buses_write_AddressBus_From_To
	bl	MMU_readMemory
	ldr	r3, .L45+16
	ldr	r3, [r3, #4]
	ldr	r2, .L45+4
	str	r3, [r2]
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L28:
	ldr	r3, .L45
	ldr	r3, [r3, #8]
	ldr	r2, .L45+20
	str	r3, [r2]
	mov	r1, #1
	mov	r0, #2
	bl	Buses_write_AddressBus_From_To
	bl	MMU_readMemory
	ldr	r3, .L45
	ldr	r2, [r3, #4]
	ldr	r3, .L45+16
	ldr	r3, [r3, #4]
	add	r3, r2, r3
	ldr	r2, .L45+4
	str	r3, [r2]
	ldr	r3, .L45
	ldr	r3, [r3, #4]
	ldr	r2, .L45+16
	ldr	r2, [r2, #4]
	mov	r1, r2
	mov	r0, r3
	bl	Processor_CheckOverflow
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L30:
	ldr	r3, .L45+4
	ldr	r3, [r3]
	str	r3, [fp, #-24]
	ldr	r3, .L45
	ldr	r2, [r3, #4]
	ldr	r3, .L45+4
	ldr	r3, [r3]
	add	r3, r2, r3
	ldr	r2, .L45+4
	str	r3, [r2]
	ldr	r3, .L45
	ldr	r3, [r3, #4]
	mov	r1, r3
	ldr	r0, [fp, #-24]
	bl	Processor_CheckOverflow
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	b	.L34
.L31:
	mov	r0, #7
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L39
	mov	r0, #0
	bl	Processor_ActivatePSW_Bit
	b	.L34
.L39:
	mov	r0, #1
	bl	Processor_RaiseException
	b	.L34
.L26:
	mov	r0, #7
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L41
	bl	OperatingSystem_GetExecutingProcessID
	mov	r7, r0
	ldr	r3, .L45+8
	ldr	r6, [r3]
	ldr	r3, .L45+4
	ldr	r4, [r3]
	ldr	r3, .L45+24
	ldr	r5, [r3]
	bl	Processor_ShowPSW
	mov	r3, r0
	str	r3, [sp, #8]
	str	r5, [sp, #4]
	str	r4, [sp]
	mov	r3, r6
	mov	r2, r7
	mov	r1, #104
	mov	r0, #130
	bl	ComputerSystem_DebugMessage
	ldr	r3, .L45
	ldr	r3, [r3, #4]
	mov	r0, r3
	bl	OperatingSystem_InterruptLogic
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	bl	Processor_UpdatePSW
	bl	__utac_acc__Aspect__2
	b	.L17
.L41:
	mov	r0, #1
	bl	Processor_RaiseException
	b	.L34
.L21:
	mov	r0, #7
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L43
	ldr	r0, .L45+28
	bl	Processor_CopyFromSystemStack
	mov	r3, r0
	ldr	r2, .L45+8
	str	r3, [r2]
	ldr	r0, .L45+32
	bl	Processor_CopyFromSystemStack
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L45+24
	str	r2, [r3]
	b	.L34
.L43:
	mov	r0, #1
	bl	Processor_RaiseException
	b	.L34
.L18:
	ldr	r3, .L45+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L45+8
	str	r3, [r2]
	mov	r0, #3
	bl	Processor_RaiseException
	nop
.L34:
	bl	Processor_UpdatePSW
	bl	OperatingSystem_GetExecutingProcessID
	mov	r7, r0
	ldr	r3, .L45+8
	ldr	r6, [r3]
	ldr	r3, .L45+4
	ldr	r4, [r3]
	ldr	r3, .L45+24
	ldr	r5, [r3]
	bl	Processor_ShowPSW
	mov	r3, r0
	str	r3, [sp, #8]
	str	r5, [sp, #4]
	str	r4, [sp]
	mov	r3, r6
	mov	r2, r7
	mov	r1, #104
	mov	r0, #130
	bl	ComputerSystem_DebugMessage
	bl	__utac_acc__Aspect__2
.L17:
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
.L46:
	.align	2
.L45:
	.word	registerIR_CPU
	.word	registerAccumulator_CPU
	.word	registerPC_CPU
	.word	registerA_CPU
	.word	registerMBR_CPU
	.word	registerMAR_CPU
	.word	registerPSW_CPU
	.word	299
	.word	298
	.size	Processor_DecodeAndExecuteInstruction, .-Processor_DecodeAndExecuteInstruction
	.align	2
	.global	Processor_ManageInterrupts
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_ManageInterrupts, %function
Processor_ManageInterrupts:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L48
.L51:
	ldr	r3, [fp, #-8]
	mov	r0, r3
	bl	Processor_GetInterruptLineStatus
	mov	r3, r0
	cmp	r3, #0
	beq	.L49
	ldr	r3, [fp, #-8]
	mov	r0, r3
	bl	Processor_ACKInterrupt
	ldr	r3, .L52
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L52+4
	bl	Processor_CopyInSystemStack
	ldr	r3, .L52+8
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L52+12
	bl	Processor_CopyInSystemStack
	mov	r0, #7
	bl	Processor_ActivatePSW_Bit
	mov	r0, #15
	bl	Processor_ActivatePSW_Bit
	ldr	r2, .L52+16
	ldr	r3, [fp, #-8]
	ldr	r3, [r2, r3, lsl #2]
	ldr	r2, .L52
	str	r3, [r2]
	b	.L50
.L49:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L48:
	ldr	r3, [fp, #-8]
	cmp	r3, #9
	ble	.L51
	nop
.L50:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L53:
	.align	2
.L52:
	.word	registerPC_CPU
	.word	299
	.word	registerPSW_CPU
	.word	298
	.word	interruptVectorTable
	.size	Processor_ManageInterrupts, .-Processor_ManageInterrupts
	.align	2
	.global	Processor_UpdatePSW
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_UpdatePSW, %function
Processor_UpdatePSW:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	ldr	r3, .L60
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L55
	mov	r0, #1
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	bne	.L56
	mov	r0, #1
	bl	Processor_ActivatePSW_Bit
	b	.L56
.L55:
	mov	r0, #1
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L56
	mov	r0, #1
	bl	Processor_DeactivatePSW_Bit
.L56:
	ldr	r3, .L60
	ldr	r3, [r3]
	cmp	r3, #0
	bge	.L57
	mov	r0, #2
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	mov	r0, #2
	bl	Processor_ActivatePSW_Bit
	b	.L59
.L57:
	mov	r0, #2
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L59
	mov	r0, #2
	bl	Processor_DeactivatePSW_Bit
.L59:
	nop
	pop	{fp, pc}
.L61:
	.align	2
.L60:
	.word	registerAccumulator_CPU
	.size	Processor_UpdatePSW, .-Processor_UpdatePSW
	.align	2
	.global	Processor_CheckOverflow
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_CheckOverflow, %function
Processor_CheckOverflow:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	ble	.L63
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	ble	.L63
	ldr	r3, .L67
	ldr	r3, [r3]
	cmp	r3, #0
	blt	.L64
.L63:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bge	.L66
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	bge	.L66
	ldr	r3, .L67
	ldr	r3, [r3]
	cmp	r3, #0
	ble	.L66
.L64:
	mov	r0, #3
	bl	Processor_ActivatePSW_Bit
.L66:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L68:
	.align	2
.L67:
	.word	registerAccumulator_CPU
	.size	Processor_CheckOverflow, .-Processor_CheckOverflow
	.align	2
	.global	Processor_CopyInSystemStack
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_CopyInSystemStack, %function
Processor_CopyInSystemStack:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, .L70
	ldr	r3, [fp, #-12]
	str	r3, [r2, #8]
	ldr	r3, .L70
	ldr	r3, [r3, #8]
	ldr	r2, .L70
	str	r3, [r2, #4]
	ldr	r3, .L70
	ldr	r3, [r3, #4]
	and	r2, r3, #255
	ldr	r3, .L70
	strb	r2, [r3]
	ldr	r2, .L70+4
	ldr	r3, [fp, #-8]
	str	r3, [r2]
	mov	r1, #0
	mov	r0, #2
	bl	Buses_write_AddressBus_From_To
	mov	r1, #0
	mov	r0, #2
	bl	Buses_write_DataBus_From_To
	bl	MainMemory_writeMemory
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L71:
	.align	2
.L70:
	.word	registerMBR_CPU
	.word	registerMAR_CPU
	.size	Processor_CopyInSystemStack, .-Processor_CopyInSystemStack
	.align	2
	.global	Processor_CopyFromSystemStack
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_CopyFromSystemStack, %function
Processor_CopyFromSystemStack:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	ldr	r2, .L74
	ldr	r3, [fp, #-16]
	str	r3, [r2]
	mov	r1, #0
	mov	r0, #2
	bl	Buses_write_AddressBus_From_To
	bl	MainMemory_readMemory
	ldr	r3, .L74+4
	ldr	r3, [r3, #4]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L75:
	.align	2
.L74:
	.word	registerMAR_CPU
	.word	registerMBR_CPU
	.size	Processor_CopyFromSystemStack, .-Processor_CopyFromSystemStack
	.align	2
	.global	Processor_RaiseInterrupt
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_RaiseInterrupt, %function
Processor_RaiseInterrupt:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #1
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-16]
	lsl	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, .L77
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r3, [fp, #-8]
	orr	r3, r2, r3
	mov	r2, r3
	ldr	r3, .L77
	str	r2, [r3]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L78:
	.align	2
.L77:
	.word	interruptLines_CPU
	.size	Processor_RaiseInterrupt, .-Processor_RaiseInterrupt
	.align	2
	.global	Processor_ACKInterrupt
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_ACKInterrupt, %function
Processor_ACKInterrupt:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #1
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-16]
	lsl	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mvn	r3, r3
	str	r3, [fp, #-8]
	ldr	r3, .L80
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r3, [fp, #-8]
	and	r3, r3, r2
	mov	r2, r3
	ldr	r3, .L80
	str	r2, [r3]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L81:
	.align	2
.L80:
	.word	interruptLines_CPU
	.size	Processor_ACKInterrupt, .-Processor_ACKInterrupt
	.align	2
	.global	Processor_GetInterruptLineStatus
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_GetInterruptLineStatus, %function
Processor_GetInterruptLineStatus:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #1
	str	r3, [fp, #-12]
	ldr	r2, [fp, #-12]
	ldr	r3, [fp, #-16]
	lsl	r3, r2, r3
	str	r3, [fp, #-12]
	ldr	r3, .L84
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r3, [fp, #-12]
	and	r2, r2, r3
	ldr	r3, [fp, #-16]
	lsr	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L85:
	.align	2
.L84:
	.word	interruptLines_CPU
	.size	Processor_GetInterruptLineStatus, .-Processor_GetInterruptLineStatus
	.align	2
	.global	Processor_ActivatePSW_Bit
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_ActivatePSW_Bit, %function
Processor_ActivatePSW_Bit:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #1
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-16]
	lsl	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, .L87
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	orr	r3, r2, r3
	ldr	r2, .L87
	str	r3, [r2]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L88:
	.align	2
.L87:
	.word	registerPSW_CPU
	.size	Processor_ActivatePSW_Bit, .-Processor_ActivatePSW_Bit
	.align	2
	.global	Processor_DeactivatePSW_Bit
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_DeactivatePSW_Bit, %function
Processor_DeactivatePSW_Bit:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #1
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-16]
	lsl	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mvn	r3, r3
	str	r3, [fp, #-8]
	ldr	r3, .L90
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	and	r3, r3, r2
	ldr	r2, .L90
	str	r3, [r2]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L91:
	.align	2
.L90:
	.word	registerPSW_CPU
	.size	Processor_DeactivatePSW_Bit, .-Processor_DeactivatePSW_Bit
	.align	2
	.global	Processor_PSW_BitState
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_PSW_BitState, %function
Processor_PSW_BitState:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	mov	r3, #1
	str	r3, [fp, #-12]
	ldr	r2, [fp, #-12]
	ldr	r3, [fp, #-16]
	lsl	r3, r2, r3
	str	r3, [fp, #-12]
	ldr	r3, .L94
	ldr	r2, [r3]
	ldr	r3, [fp, #-12]
	and	r2, r2, r3
	ldr	r3, [fp, #-16]
	lsr	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L95:
	.align	2
.L94:
	.word	registerPSW_CPU
	.size	Processor_PSW_BitState, .-Processor_PSW_BitState
	.align	2
	.global	Processor_GetMAR
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_GetMAR, %function
Processor_GetMAR:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	ldr	r3, .L98
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L99:
	.align	2
.L98:
	.word	registerMAR_CPU
	.size	Processor_GetMAR, .-Processor_GetMAR
	.align	2
	.global	Processor_SetMAR
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_SetMAR, %function
Processor_SetMAR:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r2, .L101
	ldr	r3, [fp, #-8]
	str	r3, [r2]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L102:
	.align	2
.L101:
	.word	registerMAR_CPU
	.size	Processor_SetMAR, .-Processor_SetMAR
	.align	2
	.global	Processor_GetMBR
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_GetMBR, %function
Processor_GetMBR:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	mov	r2, #12
	ldr	r1, .L104
	ldr	r0, [fp, #-8]
	bl	memcpy
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L105:
	.align	2
.L104:
	.word	registerMBR_CPU
	.size	Processor_GetMBR, .-Processor_GetMBR
	.align	2
	.global	Processor_SetMBR
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_SetMBR, %function
Processor_SetMBR:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	mov	r2, #12
	ldr	r1, [fp, #-8]
	ldr	r0, .L107
	bl	memcpy
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L108:
	.align	2
.L107:
	.word	registerMBR_CPU
	.size	Processor_SetMBR, .-Processor_SetMBR
	.align	2
	.global	Processor_GetMBR_Value
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_GetMBR_Value, %function
Processor_GetMBR_Value:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	ldr	r3, .L111
	ldrb	r3, [r3]	@ zero_extendqisi2
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L112:
	.align	2
.L111:
	.word	registerMBR_CPU
	.size	Processor_GetMBR_Value, .-Processor_GetMBR_Value
	.align	2
	.global	Processor_SetAccumulator
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_SetAccumulator, %function
Processor_SetAccumulator:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r2, .L114
	ldr	r3, [fp, #-8]
	str	r3, [r2]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L115:
	.align	2
.L114:
	.word	registerAccumulator_CPU
	.size	Processor_SetAccumulator, .-Processor_SetAccumulator
	.align	2
	.global	Processor_SetPC
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_SetPC, %function
Processor_SetPC:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r2, .L117
	ldr	r3, [fp, #-8]
	str	r3, [r2]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L118:
	.align	2
.L117:
	.word	registerPC_CPU
	.size	Processor_SetPC, .-Processor_SetPC
	.align	2
	.global	Processor_GetAccumulator
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_GetAccumulator, %function
Processor_GetAccumulator:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	ldr	r3, .L121
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L122:
	.align	2
.L121:
	.word	registerAccumulator_CPU
	.size	Processor_GetAccumulator, .-Processor_GetAccumulator
	.align	2
	.global	Processor_GetRegisterA
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_GetRegisterA, %function
Processor_GetRegisterA:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	ldr	r3, .L125
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L126:
	.align	2
.L125:
	.word	registerA_CPU
	.size	Processor_GetRegisterA, .-Processor_GetRegisterA
	.align	2
	.global	Processor_GetRegisterB
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_GetRegisterB, %function
Processor_GetRegisterB:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	ldr	r3, .L129
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L130:
	.align	2
.L129:
	.word	registerB_CPU
	.size	Processor_GetRegisterB, .-Processor_GetRegisterB
	.align	2
	.global	Processor_SetPSW
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_SetPSW, %function
Processor_SetPSW:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r2, .L132
	ldr	r3, [fp, #-8]
	str	r3, [r2]
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L133:
	.align	2
.L132:
	.word	registerPSW_CPU
	.size	Processor_SetPSW, .-Processor_SetPSW
	.align	2
	.global	Processor_GetPSW
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_GetPSW, %function
Processor_GetPSW:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	ldr	r3, .L136
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L137:
	.align	2
.L136:
	.word	registerPSW_CPU
	.size	Processor_GetPSW, .-Processor_GetPSW
	.section	.rodata
	.align	2
.LC0:
	.ascii	"----------------\000"
	.text
	.align	2
	.global	Processor_ShowPSW
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_ShowPSW, %function
Processor_ShowPSW:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	ldr	r2, .L146
	ldr	r3, .L146+4
	mov	ip, r2
	mov	lr, r3
	ldmia	lr!, {r0, r1, r2, r3}
	stmia	ip!, {r0, r1, r2, r3}
	ldr	r3, [lr]
	strb	r3, [ip]
	ldr	r0, .L146
	bl	strlen
	mov	r3, r0
	sub	r3, r3, #1
	str	r3, [fp, #-12]
	mov	r0, #7
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L139
	ldr	r3, [fp, #-12]
	sub	r3, r3, #7
	ldr	r2, .L146
	mov	r1, #88
	strb	r1, [r2, r3]
.L139:
	mov	r0, #3
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L140
	ldr	r3, [fp, #-12]
	sub	r3, r3, #3
	ldr	r2, .L146
	mov	r1, #70
	strb	r1, [r2, r3]
.L140:
	mov	r0, #2
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L141
	ldr	r3, [fp, #-12]
	sub	r3, r3, #2
	ldr	r2, .L146
	mov	r1, #78
	strb	r1, [r2, r3]
.L141:
	mov	r0, #1
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L142
	ldr	r3, [fp, #-12]
	sub	r3, r3, #1
	ldr	r2, .L146
	mov	r1, #90
	strb	r1, [r2, r3]
.L142:
	mov	r0, #0
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L143
	ldr	r2, .L146
	ldr	r3, [fp, #-12]
	add	r3, r2, r3
	mov	r2, #83
	strb	r2, [r3]
.L143:
	mov	r0, #15
	bl	Processor_PSW_BitState
	mov	r3, r0
	cmp	r3, #0
	beq	.L144
	ldr	r3, [fp, #-12]
	sub	r3, r3, #15
	ldr	r2, .L146
	mov	r1, #77
	strb	r1, [r2, r3]
.L144:
	ldr	r3, .L146
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L147:
	.align	2
.L146:
	.word	pswmask
	.word	.LC0
	.size	Processor_ShowPSW, .-Processor_ShowPSW
	.align	2
	.global	Processor_RaiseException
	.syntax unified
	.arm
	.fpu softvfp
	.type	Processor_RaiseException, %function
Processor_RaiseException:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r2, .L149
	ldr	r3, [fp, #-8]
	str	r3, [r2]
	mov	r0, #6
	bl	Processor_RaiseInterrupt
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L150:
	.align	2
.L149:
	.word	registerB_CPU
	.size	Processor_RaiseException, .-Processor_RaiseException
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
