	.file	"124678.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	s13_l0
	.bss
	.type	s13_l0, @object
	.size	s13_l0, 1
s13_l0:
	.zero	1
	.globl	_x_s13_l0
	.type	_x_s13_l0, @object
	.size	_x_s13_l0, 1
_x_s13_l0:
	.zero	1
	.globl	s13_evt2
	.type	s13_evt2, @object
	.size	s13_evt2, 1
s13_evt2:
	.zero	1
	.globl	_x_s13_evt2
	.type	_x_s13_evt2, @object
	.size	_x_s13_evt2, 1
_x_s13_evt2:
	.zero	1
	.globl	s13_evt1
	.type	s13_evt1, @object
	.size	s13_evt1, 1
s13_evt1:
	.zero	1
	.globl	_x_s13_evt1
	.type	_x_s13_evt1, @object
	.size	_x_s13_evt1, 1
_x_s13_evt1:
	.zero	1
	.globl	s13_evt0
	.type	s13_evt0, @object
	.size	s13_evt0, 1
s13_evt0:
	.zero	1
	.globl	_x_s13_evt0
	.type	_x_s13_evt0, @object
	.size	_x_s13_evt0, 1
_x_s13_evt0:
	.zero	1
	.globl	s13_backoff
	.align 4
	.type	s13_backoff, @object
	.size	s13_backoff, 4
s13_backoff:
	.zero	4
	.globl	_x_s13_backoff
	.align 4
	.type	_x_s13_backoff, @object
	.size	_x_s13_backoff, 4
_x_s13_backoff:
	.zero	4
	.globl	s12_l0
	.type	s12_l0, @object
	.size	s12_l0, 1
s12_l0:
	.zero	1
	.globl	_x_s12_l0
	.type	_x_s12_l0, @object
	.size	_x_s12_l0, 1
_x_s12_l0:
	.zero	1
	.globl	s12_evt2
	.type	s12_evt2, @object
	.size	s12_evt2, 1
s12_evt2:
	.zero	1
	.globl	_x_s12_evt2
	.type	_x_s12_evt2, @object
	.size	_x_s12_evt2, 1
_x_s12_evt2:
	.zero	1
	.globl	s12_evt1
	.type	s12_evt1, @object
	.size	s12_evt1, 1
s12_evt1:
	.zero	1
	.globl	_x_s12_evt1
	.type	_x_s12_evt1, @object
	.size	_x_s12_evt1, 1
_x_s12_evt1:
	.zero	1
	.globl	s12_evt0
	.type	s12_evt0, @object
	.size	s12_evt0, 1
s12_evt0:
	.zero	1
	.globl	_x_s12_evt0
	.type	_x_s12_evt0, @object
	.size	_x_s12_evt0, 1
_x_s12_evt0:
	.zero	1
	.globl	s12_backoff
	.align 4
	.type	s12_backoff, @object
	.size	s12_backoff, 4
s12_backoff:
	.zero	4
	.globl	_x_s12_backoff
	.align 4
	.type	_x_s12_backoff, @object
	.size	_x_s12_backoff, 4
_x_s12_backoff:
	.zero	4
	.globl	s11_l0
	.type	s11_l0, @object
	.size	s11_l0, 1
s11_l0:
	.zero	1
	.globl	_x_s11_l0
	.type	_x_s11_l0, @object
	.size	_x_s11_l0, 1
_x_s11_l0:
	.zero	1
	.globl	s11_evt2
	.type	s11_evt2, @object
	.size	s11_evt2, 1
s11_evt2:
	.zero	1
	.globl	_x_s11_evt2
	.type	_x_s11_evt2, @object
	.size	_x_s11_evt2, 1
_x_s11_evt2:
	.zero	1
	.globl	s11_evt1
	.type	s11_evt1, @object
	.size	s11_evt1, 1
s11_evt1:
	.zero	1
	.globl	_x_s11_evt1
	.type	_x_s11_evt1, @object
	.size	_x_s11_evt1, 1
_x_s11_evt1:
	.zero	1
	.globl	s11_evt0
	.type	s11_evt0, @object
	.size	s11_evt0, 1
s11_evt0:
	.zero	1
	.globl	_x_s11_evt0
	.type	_x_s11_evt0, @object
	.size	_x_s11_evt0, 1
_x_s11_evt0:
	.zero	1
	.globl	s11_lambda
	.align 4
	.type	s11_lambda, @object
	.size	s11_lambda, 4
s11_lambda:
	.zero	4
	.globl	_x_s11_lambda
	.align 4
	.type	_x_s11_lambda, @object
	.size	_x_s11_lambda, 4
_x_s11_lambda:
	.zero	4
	.globl	s11_backoff
	.align 4
	.type	s11_backoff, @object
	.size	s11_backoff, 4
s11_backoff:
	.zero	4
	.globl	_x_s11_backoff
	.align 4
	.type	_x_s11_backoff, @object
	.size	_x_s11_backoff, 4
_x_s11_backoff:
	.zero	4
	.globl	s11_x
	.align 4
	.type	s11_x, @object
	.size	s11_x, 4
s11_x:
	.zero	4
	.globl	_x_s11_x
	.align 4
	.type	_x_s11_x, @object
	.size	_x_s11_x, 4
_x_s11_x:
	.zero	4
	.globl	s10_l0
	.type	s10_l0, @object
	.size	s10_l0, 1
s10_l0:
	.zero	1
	.globl	_x_s10_l0
	.type	_x_s10_l0, @object
	.size	_x_s10_l0, 1
_x_s10_l0:
	.zero	1
	.globl	s10_evt2
	.type	s10_evt2, @object
	.size	s10_evt2, 1
s10_evt2:
	.zero	1
	.globl	_x_s10_evt2
	.type	_x_s10_evt2, @object
	.size	_x_s10_evt2, 1
_x_s10_evt2:
	.zero	1
	.globl	s10_evt1
	.type	s10_evt1, @object
	.size	s10_evt1, 1
s10_evt1:
	.zero	1
	.globl	_x_s10_evt1
	.type	_x_s10_evt1, @object
	.size	_x_s10_evt1, 1
_x_s10_evt1:
	.zero	1
	.globl	s10_evt0
	.type	s10_evt0, @object
	.size	s10_evt0, 1
s10_evt0:
	.zero	1
	.globl	_x_s10_evt0
	.type	_x_s10_evt0, @object
	.size	_x_s10_evt0, 1
_x_s10_evt0:
	.zero	1
	.globl	s10_lambda
	.align 4
	.type	s10_lambda, @object
	.size	s10_lambda, 4
s10_lambda:
	.zero	4
	.globl	_x_s10_lambda
	.align 4
	.type	_x_s10_lambda, @object
	.size	_x_s10_lambda, 4
_x_s10_lambda:
	.zero	4
	.globl	s10_backoff
	.align 4
	.type	s10_backoff, @object
	.size	s10_backoff, 4
s10_backoff:
	.zero	4
	.globl	_x_s10_backoff
	.align 4
	.type	_x_s10_backoff, @object
	.size	_x_s10_backoff, 4
_x_s10_backoff:
	.zero	4
	.globl	s10_x
	.align 4
	.type	s10_x, @object
	.size	s10_x, 4
s10_x:
	.zero	4
	.globl	_x_s10_x
	.align 4
	.type	_x_s10_x, @object
	.size	_x_s10_x, 4
_x_s10_x:
	.zero	4
	.globl	s9_l0
	.type	s9_l0, @object
	.size	s9_l0, 1
s9_l0:
	.zero	1
	.globl	_x_s9_l0
	.type	_x_s9_l0, @object
	.size	_x_s9_l0, 1
_x_s9_l0:
	.zero	1
	.globl	s9_evt2
	.type	s9_evt2, @object
	.size	s9_evt2, 1
s9_evt2:
	.zero	1
	.globl	_x_s9_evt2
	.type	_x_s9_evt2, @object
	.size	_x_s9_evt2, 1
_x_s9_evt2:
	.zero	1
	.globl	s9_evt1
	.type	s9_evt1, @object
	.size	s9_evt1, 1
s9_evt1:
	.zero	1
	.globl	_x_s9_evt1
	.type	_x_s9_evt1, @object
	.size	_x_s9_evt1, 1
_x_s9_evt1:
	.zero	1
	.globl	s9_evt0
	.type	s9_evt0, @object
	.size	s9_evt0, 1
s9_evt0:
	.zero	1
	.globl	_x_s9_evt0
	.type	_x_s9_evt0, @object
	.size	_x_s9_evt0, 1
_x_s9_evt0:
	.zero	1
	.globl	s9_lambda
	.align 4
	.type	s9_lambda, @object
	.size	s9_lambda, 4
s9_lambda:
	.zero	4
	.globl	_x_s9_lambda
	.align 4
	.type	_x_s9_lambda, @object
	.size	_x_s9_lambda, 4
_x_s9_lambda:
	.zero	4
	.globl	s9_backoff
	.align 4
	.type	s9_backoff, @object
	.size	s9_backoff, 4
s9_backoff:
	.zero	4
	.globl	_x_s9_backoff
	.align 4
	.type	_x_s9_backoff, @object
	.size	_x_s9_backoff, 4
_x_s9_backoff:
	.zero	4
	.globl	s9_x
	.align 4
	.type	s9_x, @object
	.size	s9_x, 4
s9_x:
	.zero	4
	.globl	_x_s9_x
	.align 4
	.type	_x_s9_x, @object
	.size	_x_s9_x, 4
_x_s9_x:
	.zero	4
	.globl	s8_l1
	.type	s8_l1, @object
	.size	s8_l1, 1
s8_l1:
	.zero	1
	.globl	_x_s8_l1
	.type	_x_s8_l1, @object
	.size	_x_s8_l1, 1
_x_s8_l1:
	.zero	1
	.globl	s8_l0
	.type	s8_l0, @object
	.size	s8_l0, 1
s8_l0:
	.zero	1
	.globl	_x_s8_l0
	.type	_x_s8_l0, @object
	.size	_x_s8_l0, 1
_x_s8_l0:
	.zero	1
	.globl	s8_evt2
	.type	s8_evt2, @object
	.size	s8_evt2, 1
s8_evt2:
	.zero	1
	.globl	_x_s8_evt2
	.type	_x_s8_evt2, @object
	.size	_x_s8_evt2, 1
_x_s8_evt2:
	.zero	1
	.globl	s8_evt1
	.type	s8_evt1, @object
	.size	s8_evt1, 1
s8_evt1:
	.zero	1
	.globl	_x_s8_evt1
	.type	_x_s8_evt1, @object
	.size	_x_s8_evt1, 1
_x_s8_evt1:
	.zero	1
	.globl	s8_evt0
	.type	s8_evt0, @object
	.size	s8_evt0, 1
s8_evt0:
	.zero	1
	.globl	_x_s8_evt0
	.type	_x_s8_evt0, @object
	.size	_x_s8_evt0, 1
_x_s8_evt0:
	.zero	1
	.globl	s8_lambda
	.align 4
	.type	s8_lambda, @object
	.size	s8_lambda, 4
s8_lambda:
	.zero	4
	.globl	_x_s8_lambda
	.align 4
	.type	_x_s8_lambda, @object
	.size	_x_s8_lambda, 4
_x_s8_lambda:
	.zero	4
	.globl	s8_backoff
	.align 4
	.type	s8_backoff, @object
	.size	s8_backoff, 4
s8_backoff:
	.zero	4
	.globl	_x_s8_backoff
	.align 4
	.type	_x_s8_backoff, @object
	.size	_x_s8_backoff, 4
_x_s8_backoff:
	.zero	4
	.globl	s8_x
	.align 4
	.type	s8_x, @object
	.size	s8_x, 4
s8_x:
	.zero	4
	.globl	_x_s8_x
	.align 4
	.type	_x_s8_x, @object
	.size	_x_s8_x, 4
_x_s8_x:
	.zero	4
	.globl	s7_l1
	.type	s7_l1, @object
	.size	s7_l1, 1
s7_l1:
	.zero	1
	.globl	_x_s7_l1
	.type	_x_s7_l1, @object
	.size	_x_s7_l1, 1
_x_s7_l1:
	.zero	1
	.globl	s7_l0
	.type	s7_l0, @object
	.size	s7_l0, 1
s7_l0:
	.zero	1
	.globl	_x_s7_l0
	.type	_x_s7_l0, @object
	.size	_x_s7_l0, 1
_x_s7_l0:
	.zero	1
	.globl	s7_evt2
	.type	s7_evt2, @object
	.size	s7_evt2, 1
s7_evt2:
	.zero	1
	.globl	_x_s7_evt2
	.type	_x_s7_evt2, @object
	.size	_x_s7_evt2, 1
_x_s7_evt2:
	.zero	1
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	s7_evt1
	.type	s7_evt1, @object
	.size	s7_evt1, 1
s7_evt1:
	.zero	1
	.globl	_x_s7_evt1
	.type	_x_s7_evt1, @object
	.size	_x_s7_evt1, 1
_x_s7_evt1:
	.zero	1
	.globl	s7_evt0
	.type	s7_evt0, @object
	.size	s7_evt0, 1
s7_evt0:
	.zero	1
	.globl	_x_s7_evt0
	.type	_x_s7_evt0, @object
	.size	_x_s7_evt0, 1
_x_s7_evt0:
	.zero	1
	.globl	s7_lambda
	.align 4
	.type	s7_lambda, @object
	.size	s7_lambda, 4
s7_lambda:
	.zero	4
	.globl	_x_s7_lambda
	.align 4
	.type	_x_s7_lambda, @object
	.size	_x_s7_lambda, 4
_x_s7_lambda:
	.zero	4
	.globl	s7_backoff
	.align 4
	.type	s7_backoff, @object
	.size	s7_backoff, 4
s7_backoff:
	.zero	4
	.globl	_x_s7_backoff
	.align 4
	.type	_x_s7_backoff, @object
	.size	_x_s7_backoff, 4
_x_s7_backoff:
	.zero	4
	.globl	s7_x
	.align 4
	.type	s7_x, @object
	.size	s7_x, 4
s7_x:
	.zero	4
	.globl	_x_s7_x
	.align 4
	.type	_x_s7_x, @object
	.size	_x_s7_x, 4
_x_s7_x:
	.zero	4
	.globl	s6_l1
	.type	s6_l1, @object
	.size	s6_l1, 1
s6_l1:
	.zero	1
	.globl	_x_s6_l1
	.type	_x_s6_l1, @object
	.size	_x_s6_l1, 1
_x_s6_l1:
	.zero	1
	.globl	s6_l0
	.type	s6_l0, @object
	.size	s6_l0, 1
s6_l0:
	.zero	1
	.globl	_x_s6_l0
	.type	_x_s6_l0, @object
	.size	_x_s6_l0, 1
_x_s6_l0:
	.zero	1
	.globl	s6_evt2
	.type	s6_evt2, @object
	.size	s6_evt2, 1
s6_evt2:
	.zero	1
	.globl	_x_s6_evt2
	.type	_x_s6_evt2, @object
	.size	_x_s6_evt2, 1
_x_s6_evt2:
	.zero	1
	.globl	s6_evt1
	.type	s6_evt1, @object
	.size	s6_evt1, 1
s6_evt1:
	.zero	1
	.globl	_x_s6_evt1
	.type	_x_s6_evt1, @object
	.size	_x_s6_evt1, 1
_x_s6_evt1:
	.zero	1
	.globl	s6_evt0
	.type	s6_evt0, @object
	.size	s6_evt0, 1
s6_evt0:
	.zero	1
	.globl	_x_s6_evt0
	.type	_x_s6_evt0, @object
	.size	_x_s6_evt0, 1
_x_s6_evt0:
	.zero	1
	.globl	s6_lambda
	.align 4
	.type	s6_lambda, @object
	.size	s6_lambda, 4
s6_lambda:
	.zero	4
	.globl	_x_s6_lambda
	.align 4
	.type	_x_s6_lambda, @object
	.size	_x_s6_lambda, 4
_x_s6_lambda:
	.zero	4
	.globl	s2_x
	.align 4
	.type	s2_x, @object
	.size	s2_x, 4
s2_x:
	.zero	4
	.globl	_x_s2_x
	.align 4
	.type	_x_s2_x, @object
	.size	_x_s2_x, 4
_x_s2_x:
	.zero	4
	.globl	s1_l1
	.type	s1_l1, @object
	.size	s1_l1, 1
s1_l1:
	.zero	1
	.globl	_x_s1_l1
	.type	_x_s1_l1, @object
	.size	_x_s1_l1, 1
_x_s1_l1:
	.zero	1
	.globl	s4_evt2
	.type	s4_evt2, @object
	.size	s4_evt2, 1
s4_evt2:
	.zero	1
	.globl	_x_s4_evt2
	.type	_x_s4_evt2, @object
	.size	_x_s4_evt2, 1
_x_s4_evt2:
	.zero	1
	.globl	s1_l0
	.type	s1_l0, @object
	.size	s1_l0, 1
s1_l0:
	.zero	1
	.globl	_x_s1_l0
	.type	_x_s1_l0, @object
	.size	_x_s1_l0, 1
_x_s1_l0:
	.zero	1
	.globl	s4_evt1
	.type	s4_evt1, @object
	.size	s4_evt1, 1
s4_evt1:
	.zero	1
	.globl	_x_s4_evt1
	.type	_x_s4_evt1, @object
	.size	_x_s4_evt1, 1
_x_s4_evt1:
	.zero	1
	.globl	s13_lambda
	.align 4
	.type	s13_lambda, @object
	.size	s13_lambda, 4
s13_lambda:
	.zero	4
	.globl	_x_s13_lambda
	.align 4
	.type	_x_s13_lambda, @object
	.size	_x_s13_lambda, 4
_x_s13_lambda:
	.zero	4
	.globl	s1_evt2
	.type	s1_evt2, @object
	.size	s1_evt2, 1
s1_evt2:
	.zero	1
	.globl	_x_s1_evt2
	.type	_x_s1_evt2, @object
	.size	_x_s1_evt2, 1
_x_s1_evt2:
	.zero	1
	.globl	s13_x
	.align 4
	.type	s13_x, @object
	.size	s13_x, 4
s13_x:
	.zero	4
	.globl	_x_s13_x
	.align 4
	.type	_x_s13_x, @object
	.size	_x_s13_x, 4
_x_s13_x:
	.zero	4
	.globl	s1_evt1
	.type	s1_evt1, @object
	.size	s1_evt1, 1
s1_evt1:
	.zero	1
	.globl	_x_s1_evt1
	.type	_x_s1_evt1, @object
	.size	_x_s1_evt1, 1
_x_s1_evt1:
	.zero	1
	.globl	s1_backoff
	.align 4
	.type	s1_backoff, @object
	.size	s1_backoff, 4
s1_backoff:
	.zero	4
	.globl	_x_s1_backoff
	.align 4
	.type	_x_s1_backoff, @object
	.size	_x_s1_backoff, 4
_x_s1_backoff:
	.zero	4
	.globl	s6_x
	.align 4
	.type	s6_x, @object
	.size	s6_x, 4
s6_x:
	.zero	4
	.globl	_x_s6_x
	.align 4
	.type	_x_s6_x, @object
	.size	_x_s6_x, 4
_x_s6_x:
	.zero	4
	.globl	s2_backoff
	.align 4
	.type	s2_backoff, @object
	.size	s2_backoff, 4
s2_backoff:
	.zero	4
	.globl	_x_s2_backoff
	.align 4
	.type	_x_s2_backoff, @object
	.size	_x_s2_backoff, 4
_x_s2_backoff:
	.zero	4
	.globl	s0_l1
	.type	s0_l1, @object
	.size	s0_l1, 1
s0_l1:
	.zero	1
	.globl	_x_s0_l1
	.type	_x_s0_l1, @object
	.size	_x_s0_l1, 1
_x_s0_l1:
	.zero	1
	.globl	s3_evt2
	.type	s3_evt2, @object
	.size	s3_evt2, 1
s3_evt2:
	.zero	1
	.globl	_x_s3_evt2
	.type	_x_s3_evt2, @object
	.size	_x_s3_evt2, 1
_x_s3_evt2:
	.zero	1
	.globl	s2_lambda
	.align 4
	.type	s2_lambda, @object
	.size	s2_lambda, 4
s2_lambda:
	.zero	4
	.globl	_x_s2_lambda
	.align 4
	.type	_x_s2_lambda, @object
	.size	_x_s2_lambda, 4
_x_s2_lambda:
	.zero	4
	.globl	s0_l0
	.type	s0_l0, @object
	.size	s0_l0, 1
s0_l0:
	.zero	1
	.globl	_x_s0_l0
	.type	_x_s0_l0, @object
	.size	_x_s0_l0, 1
_x_s0_l0:
	.zero	1
	.globl	s3_evt1
	.type	s3_evt1, @object
	.size	s3_evt1, 1
s3_evt1:
	.zero	1
	.globl	_x_s3_evt1
	.type	_x_s3_evt1, @object
	.size	_x_s3_evt1, 1
_x_s3_evt1:
	.zero	1
	.globl	s12_lambda
	.align 4
	.type	s12_lambda, @object
	.size	s12_lambda, 4
s12_lambda:
	.zero	4
	.globl	_x_s12_lambda
	.align 4
	.type	_x_s12_lambda, @object
	.size	_x_s12_lambda, 4
_x_s12_lambda:
	.zero	4
	.globl	s0_evt2
	.type	s0_evt2, @object
	.size	s0_evt2, 1
s0_evt2:
	.zero	1
	.globl	_x_s0_evt2
	.type	_x_s0_evt2, @object
	.size	_x_s0_evt2, 1
_x_s0_evt2:
	.zero	1
	.globl	bus_evt0
	.type	bus_evt0, @object
	.size	bus_evt0, 1
bus_evt0:
	.zero	1
	.globl	_x_bus_evt0
	.type	_x_bus_evt0, @object
	.size	_x_bus_evt0, 1
_x_bus_evt0:
	.zero	1
	.globl	s5_evt0
	.type	s5_evt0, @object
	.size	s5_evt0, 1
s5_evt0:
	.zero	1
	.globl	_x_s5_evt0
	.type	_x_s5_evt0, @object
	.size	_x_s5_evt0, 1
_x_s5_evt0:
	.zero	1
	.globl	s12_x
	.align 4
	.type	s12_x, @object
	.size	s12_x, 4
s12_x:
	.zero	4
	.globl	_x_s12_x
	.align 4
	.type	_x_s12_x, @object
	.size	_x_s12_x, 4
_x_s12_x:
	.zero	4
	.globl	s0_evt1
	.type	s0_evt1, @object
	.size	s0_evt1, 1
s0_evt1:
	.zero	1
	.globl	_x_s0_evt1
	.type	_x_s0_evt1, @object
	.size	_x_s0_evt1, 1
_x_s0_evt1:
	.zero	1
	.globl	s4_backoff
	.align 4
	.type	s4_backoff, @object
	.size	s4_backoff, 4
s4_backoff:
	.zero	4
	.globl	_x_s4_backoff
	.align 4
	.type	_x_s4_backoff, @object
	.size	_x_s4_backoff, 4
_x_s4_backoff:
	.zero	4
	.globl	s1_x
	.align 4
	.type	s1_x, @object
	.size	s1_x, 4
s1_x:
	.zero	4
	.globl	_x_s1_x
	.align 4
	.type	_x_s1_x, @object
	.size	_x_s1_x, 4
_x_s1_x:
	.zero	4
	.globl	s5_backoff
	.align 4
	.type	s5_backoff, @object
	.size	s5_backoff, 4
s5_backoff:
	.zero	4
	.globl	_x_s5_backoff
	.align 4
	.type	_x_s5_backoff, @object
	.size	_x_s5_backoff, 4
_x_s5_backoff:
	.zero	4
	.globl	bus_j
	.align 4
	.type	bus_j, @object
	.size	bus_j, 4
bus_j:
	.zero	4
	.globl	_x_bus_j
	.align 4
	.type	_x_bus_j, @object
	.size	_x_bus_j, 4
_x_bus_j:
	.zero	4
	.globl	s11_l1
	.type	s11_l1, @object
	.size	s11_l1, 1
s11_l1:
	.zero	1
	.globl	_x_s11_l1
	.type	_x_s11_l1, @object
	.size	_x_s11_l1, 1
_x_s11_l1:
	.zero	1
	.globl	s2_evt0
	.type	s2_evt0, @object
	.size	s2_evt0, 1
s2_evt0:
	.zero	1
	.globl	_x_s2_evt0
	.type	_x_s2_evt0, @object
	.size	_x_s2_evt0, 1
_x_s2_evt0:
	.zero	1
	.globl	s0_x
	.align 4
	.type	s0_x, @object
	.size	s0_x, 4
s0_x:
	.zero	4
	.globl	_x_s0_x
	.align 4
	.type	_x_s0_x, @object
	.size	_x_s0_x, 4
_x_s0_x:
	.zero	4
	.globl	s1_lambda
	.align 4
	.type	s1_lambda, @object
	.size	s1_lambda, 4
s1_lambda:
	.zero	4
	.globl	_x_s1_lambda
	.align 4
	.type	_x_s1_lambda, @object
	.size	_x_s1_lambda, 4
_x_s1_lambda:
	.zero	4
	.globl	bus_x
	.align 4
	.type	bus_x, @object
	.size	bus_x, 4
bus_x:
	.zero	4
	.globl	_x_bus_x
	.align 4
	.type	_x_bus_x, @object
	.size	_x_bus_x, 4
_x_bus_x:
	.zero	4
	.globl	s2_evt1
	.type	s2_evt1, @object
	.size	s2_evt1, 1
s2_evt1:
	.zero	1
	.globl	_x_s2_evt1
	.type	_x_s2_evt1, @object
	.size	_x_s2_evt1, 1
_x_s2_evt1:
	.zero	1
	.globl	s6_backoff
	.align 4
	.type	s6_backoff, @object
	.size	s6_backoff, 4
s6_backoff:
	.zero	4
	.globl	_x_s6_backoff
	.align 4
	.type	_x_s6_backoff, @object
	.size	_x_s6_backoff, 4
_x_s6_backoff:
	.zero	4
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	s10_l1
	.type	s10_l1, @object
	.size	s10_l1, 1
s10_l1:
	.zero	1
	.globl	_x_s10_l1
	.type	_x_s10_l1, @object
	.size	_x_s10_l1, 1
_x_s10_l1:
	.zero	1
	.globl	s1_evt0
	.type	s1_evt0, @object
	.size	s1_evt0, 1
s1_evt0:
	.zero	1
	.globl	_x_s1_evt0
	.type	_x_s1_evt0, @object
	.size	_x_s1_evt0, 1
_x_s1_evt0:
	.zero	1
	.globl	bus_cd_id
	.align 4
	.type	bus_cd_id, @object
	.size	bus_cd_id, 4
bus_cd_id:
	.zero	4
	.globl	_x_bus_cd_id
	.align 4
	.type	_x_bus_cd_id, @object
	.size	_x_bus_cd_id, 4
_x_bus_cd_id:
	.zero	4
	.globl	s5_lambda
	.align 4
	.type	s5_lambda, @object
	.size	s5_lambda, 4
s5_lambda:
	.zero	4
	.globl	_x_s5_lambda
	.align 4
	.type	_x_s5_lambda, @object
	.size	_x_s5_lambda, 4
_x_s5_lambda:
	.zero	4
	.globl	s0_lambda
	.align 4
	.type	s0_lambda, @object
	.size	s0_lambda, 4
s0_lambda:
	.zero	4
	.globl	_x_s0_lambda
	.align 4
	.type	_x_s0_lambda, @object
	.size	_x_s0_lambda, 4
_x_s0_lambda:
	.zero	4
	.globl	s0_backoff
	.align 4
	.type	s0_backoff, @object
	.size	s0_backoff, 4
s0_backoff:
	.zero	4
	.globl	_x_s0_backoff
	.align 4
	.type	_x_s0_backoff, @object
	.size	_x_s0_backoff, 4
_x_s0_backoff:
	.zero	4
	.globl	s5_x
	.align 4
	.type	s5_x, @object
	.size	s5_x, 4
s5_x:
	.zero	4
	.globl	_x_s5_x
	.align 4
	.type	_x_s5_x, @object
	.size	_x_s5_x, 4
_x_s5_x:
	.zero	4
	.globl	s3_l0
	.type	s3_l0, @object
	.size	s3_l0, 1
s3_l0:
	.zero	1
	.globl	_x_s3_l0
	.type	_x_s3_l0, @object
	.size	_x_s3_l0, 1
_x_s3_l0:
	.zero	1
	.globl	s9_l1
	.type	s9_l1, @object
	.size	s9_l1, 1
s9_l1:
	.zero	1
	.globl	_x_s9_l1
	.type	_x_s9_l1, @object
	.size	_x_s9_l1, 1
_x_s9_l1:
	.zero	1
	.globl	s0_evt0
	.type	s0_evt0, @object
	.size	s0_evt0, 1
s0_evt0:
	.zero	1
	.globl	_x_s0_evt0
	.type	_x_s0_evt0, @object
	.size	_x_s0_evt0, 1
_x_s0_evt0:
	.zero	1
	.globl	s4_lambda
	.align 4
	.type	s4_lambda, @object
	.size	s4_lambda, 4
s4_lambda:
	.zero	4
	.globl	_x_s4_lambda
	.align 4
	.type	_x_s4_lambda, @object
	.size	_x_s4_lambda, 4
_x_s4_lambda:
	.zero	4
	.globl	s2_evt2
	.type	s2_evt2, @object
	.size	s2_evt2, 1
s2_evt2:
	.zero	1
	.globl	_x_s2_evt2
	.type	_x_s2_evt2, @object
	.size	_x_s2_evt2, 1
_x_s2_evt2:
	.zero	1
	.globl	s2_l0
	.type	s2_l0, @object
	.size	s2_l0, 1
s2_l0:
	.zero	1
	.globl	_x_s2_l0
	.type	_x_s2_l0, @object
	.size	_x_s2_l0, 1
_x_s2_l0:
	.zero	1
	.globl	bus_evt1
	.type	bus_evt1, @object
	.size	bus_evt1, 1
bus_evt1:
	.zero	1
	.globl	_x_bus_evt1
	.type	_x_bus_evt1, @object
	.size	_x_bus_evt1, 1
_x_bus_evt1:
	.zero	1
	.globl	s5_evt1
	.type	s5_evt1, @object
	.size	s5_evt1, 1
s5_evt1:
	.zero	1
	.globl	_x_s5_evt1
	.type	_x_s5_evt1, @object
	.size	_x_s5_evt1, 1
_x_s5_evt1:
	.zero	1
	.globl	s2_l1
	.type	s2_l1, @object
	.size	s2_l1, 1
s2_l1:
	.zero	1
	.globl	_x_s2_l1
	.type	_x_s2_l1, @object
	.size	_x_s2_l1, 1
_x_s2_l1:
	.zero	1
	.globl	bus_evt2
	.type	bus_evt2, @object
	.size	bus_evt2, 1
bus_evt2:
	.zero	1
	.globl	_x_bus_evt2
	.type	_x_bus_evt2, @object
	.size	_x_bus_evt2, 1
_x_bus_evt2:
	.zero	1
	.globl	s5_evt2
	.type	s5_evt2, @object
	.size	s5_evt2, 1
s5_evt2:
	.zero	1
	.globl	_x_s5_evt2
	.type	_x_s5_evt2, @object
	.size	_x_s5_evt2, 1
_x_s5_evt2:
	.zero	1
	.globl	s3_x
	.align 4
	.type	s3_x, @object
	.size	s3_x, 4
s3_x:
	.zero	4
	.globl	_x_s3_x
	.align 4
	.type	_x_s3_x, @object
	.size	_x_s3_x, 4
_x_s3_x:
	.zero	4
	.globl	s3_backoff
	.align 4
	.type	s3_backoff, @object
	.size	s3_backoff, 4
s3_backoff:
	.zero	4
	.globl	_x_s3_backoff
	.align 4
	.type	_x_s3_backoff, @object
	.size	_x_s3_backoff, 4
_x_s3_backoff:
	.zero	4
	.globl	s3_lambda
	.align 4
	.type	s3_lambda, @object
	.size	s3_lambda, 4
s3_lambda:
	.zero	4
	.globl	_x_s3_lambda
	.align 4
	.type	_x_s3_lambda, @object
	.size	_x_s3_lambda, 4
_x_s3_lambda:
	.zero	4
	.globl	s12_l1
	.type	s12_l1, @object
	.size	s12_l1, 1
s12_l1:
	.zero	1
	.globl	_x_s12_l1
	.type	_x_s12_l1, @object
	.size	_x_s12_l1, 1
_x_s12_l1:
	.zero	1
	.globl	s3_evt0
	.type	s3_evt0, @object
	.size	s3_evt0, 1
s3_evt0:
	.zero	1
	.globl	_x_s3_evt0
	.type	_x_s3_evt0, @object
	.size	_x_s3_evt0, 1
_x_s3_evt0:
	.zero	1
	.globl	s3_l1
	.type	s3_l1, @object
	.size	s3_l1, 1
s3_l1:
	.zero	1
	.globl	_x_s3_l1
	.type	_x_s3_l1, @object
	.size	_x_s3_l1, 1
_x_s3_l1:
	.zero	1
	.globl	s4_x
	.align 4
	.type	s4_x, @object
	.size	s4_x, 4
s4_x:
	.zero	4
	.globl	_x_s4_x
	.align 4
	.type	_x_s4_x, @object
	.size	_x_s4_x, 4
_x_s4_x:
	.zero	4
	.globl	s13_l1
	.type	s13_l1, @object
	.size	s13_l1, 1
s13_l1:
	.zero	1
	.globl	_x_s13_l1
	.type	_x_s13_l1, @object
	.size	_x_s13_l1, 1
_x_s13_l1:
	.zero	1
	.globl	s4_evt0
	.type	s4_evt0, @object
	.size	s4_evt0, 1
s4_evt0:
	.zero	1
	.globl	_x_s4_evt0
	.type	_x_s4_evt0, @object
	.size	_x_s4_evt0, 1
_x_s4_evt0:
	.zero	1
	.globl	s4_l0
	.type	s4_l0, @object
	.size	s4_l0, 1
s4_l0:
	.zero	1
	.globl	_x_s4_l0
	.type	_x_s4_l0, @object
	.size	_x_s4_l0, 1
_x_s4_l0:
	.zero	1
	.globl	s4_l1
	.type	s4_l1, @object
	.size	s4_l1, 1
s4_l1:
	.zero	1
	.globl	_x_s4_l1
	.type	_x_s4_l1, @object
	.size	_x_s4_l1, 1
_x_s4_l1:
	.zero	1
	.globl	bus_l0
	.type	bus_l0, @object
	.size	bus_l0, 1
bus_l0:
	.zero	1
	.globl	_x_bus_l0
	.type	_x_bus_l0, @object
	.size	_x_bus_l0, 1
_x_bus_l0:
	.zero	1
	.globl	s5_l0
	.type	s5_l0, @object
	.size	s5_l0, 1
s5_l0:
	.zero	1
	.globl	_x_s5_l0
	.type	_x_s5_l0, @object
	.size	_x_s5_l0, 1
_x_s5_l0:
	.zero	1
	.globl	bus_l1
	.type	bus_l1, @object
	.size	bus_l1, 1
bus_l1:
	.zero	1
	.globl	_x_bus_l1
	.type	_x_bus_l1, @object
	.size	_x_bus_l1, 1
_x_bus_l1:
	.zero	1
	.globl	s5_l1
	.type	s5_l1, @object
	.size	s5_l1, 1
s5_l1:
	.zero	1
	.globl	_x_s5_l1
	.type	_x_s5_l1, @object
	.size	_x_s5_l1, 1
_x_s5_l1:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s13_backoff[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s12_backoff[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s11_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s11_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s11_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s10_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s10_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s9_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s9_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s9_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s8_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s8_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s8_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s7_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s7_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s7_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s6_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s6_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s13_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s13_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s6_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_backoff[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s12_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s4_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s5_backoff[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR bus_j[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR bus_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s6_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR bus_cd_id[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s5_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s4_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s3_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s3_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s3_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s3_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s4_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s5_l1[rip], al
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L6
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L9
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L10
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L7
.L10:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L4
.L7:
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L11
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L12
.L11:
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L12
.L13:
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L4
.L12:
	movss	xmm0, DWORD PTR s13_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s13_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s13_x[rip]
	movss	xmm0, DWORD PTR s13_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L15
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L4
.L15:
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L17
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L17
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L18
.L17:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L19
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L19
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L18
.L19:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L20
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L18
.L20:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L21
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L18
.L21:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L4
.L18:
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L23
.L22:
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L23
.L24:
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L4
.L23:
	movss	xmm0, DWORD PTR s12_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s12_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s12_x[rip]
	movss	xmm0, DWORD PTR s12_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L26
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L26
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L4
.L26:
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L28
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L29
.L28:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L29
.L30:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	je	.L31
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L31
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L29
.L31:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L32
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L29
.L32:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L4
.L29:
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L33
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L34
.L33:
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L35
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L34
.L35:
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L4
.L34:
	movss	xmm0, DWORD PTR s11_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s11_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s11_x[rip]
	movss	xmm0, DWORD PTR s11_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L37
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L4
.L37:
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L39
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L40
.L39:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L40
.L41:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	je	.L42
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L42
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L40
.L42:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L43
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L43
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L40
.L43:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L4
.L40:
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L44
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L45
.L44:
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L45
.L46:
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L4
.L45:
	movss	xmm0, DWORD PTR s10_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s10_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s10_x[rip]
	movss	xmm0, DWORD PTR s10_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L48
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L4
.L48:
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L50
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L50
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L51
.L50:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L52
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L52
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L51
.L52:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	je	.L53
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L53
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L51
.L53:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L54
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L51
.L54:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L4
.L51:
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L55
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L56
.L55:
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L56
.L57:
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L4
.L56:
	movss	xmm0, DWORD PTR s9_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s9_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s9_x[rip]
	movss	xmm0, DWORD PTR s9_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L59
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L4
.L59:
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L62
.L61:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L63
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L63
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L62
.L63:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	je	.L64
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L64
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L62
.L64:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L65
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L62
.L65:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L4
.L62:
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L66
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L67
.L66:
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L68
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L67
.L68:
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L4
.L67:
	movss	xmm0, DWORD PTR s8_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s8_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s8_x[rip]
	movss	xmm0, DWORD PTR s8_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L70
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L70
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L4
.L70:
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L72
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L73
.L72:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L73
.L74:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	je	.L75
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L75
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L73
.L75:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L76
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L76
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L73
.L76:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L4
.L73:
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L78
.L77:
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L78
.L79:
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L4
.L78:
	movss	xmm0, DWORD PTR s7_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s7_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s7_x[rip]
	movss	xmm0, DWORD PTR s7_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L81
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L4
.L81:
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L83
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L83
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L84
.L83:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L85
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L84
.L85:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	je	.L86
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L84
.L86:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L87
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L87
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L84
.L87:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L4
.L84:
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L88
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L89
.L88:
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L90
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L89
.L90:
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L4
.L89:
	movss	xmm0, DWORD PTR s6_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s6_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s6_x[rip]
	movss	xmm0, DWORD PTR s6_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L92
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L4
.L92:
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L94
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L95
.L94:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L95
.L96:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L97
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L95
.L97:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L95
.L98:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L4
.L95:
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L99
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L100
.L99:
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L101
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L100
.L101:
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L4
.L100:
	movss	xmm0, DWORD PTR s5_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s5_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s5_x[rip]
	movss	xmm0, DWORD PTR s5_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L103
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L4
.L103:
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L105
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L106
.L105:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L107
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L107
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L106
.L107:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L108
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L106
.L108:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L109
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L106
.L109:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L4
.L106:
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L111
.L110:
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L112
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L111
.L112:
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L4
.L111:
	movss	xmm0, DWORD PTR s4_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s4_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s4_x[rip]
	movss	xmm0, DWORD PTR s4_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L114
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L114
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L4
.L114:
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L116
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L117
.L116:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L117
.L118:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L119
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L117
.L119:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L120
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L117
.L120:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L4
.L117:
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L121
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L122
.L121:
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L123
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L122
.L123:
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L4
.L122:
	movss	xmm0, DWORD PTR s3_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s3_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s3_x[rip]
	movss	xmm0, DWORD PTR s3_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L125
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L125
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L4
.L125:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L127
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L127
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L128
.L127:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L129
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L129
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L128
.L129:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L128
.L130:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L131
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L128
.L131:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L4
.L128:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L132
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L133
.L132:
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L134
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L133
.L134:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L4
.L133:
	movss	xmm0, DWORD PTR s2_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s2_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s2_x[rip]
	movss	xmm0, DWORD PTR s2_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L136
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L136
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L4
.L136:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L138
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L139
.L138:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L139
.L140:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L141
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L139
.L141:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L142
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L139
.L142:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L4
.L139:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L143
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L144
.L143:
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L144
.L145:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L4
.L144:
	movss	xmm0, DWORD PTR s1_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s1_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s1_x[rip]
	movss	xmm0, DWORD PTR s1_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L147
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L147
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L4
.L147:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L150
.L149:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L151
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L151
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L150
.L151:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L150
.L152:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L153
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L150
.L153:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L4
.L150:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L155
.L154:
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L155
.L156:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L4
.L155:
	movss	xmm0, DWORD PTR s0_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s0_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s0_x[rip]
	movss	xmm0, DWORD PTR s0_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L158
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L4
.L158:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L160
.L159:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L161
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L160
.L161:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L160
.L162:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L163
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L163
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L160
.L163:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L4
.L160:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L164
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L165
.L164:
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L166
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L165
.L166:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L167
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L165
.L167:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L4
.L165:
	mov	eax, DWORD PTR bus_j[rip]
	test	eax, eax
	jne	.L4
	movss	xmm0, DWORD PTR bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L4
.L169:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1319
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L170
.L1319:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L170
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L4
.L170:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L174
.L4:
	mov	eax, 0
.L174:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L175
.L1288:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s13_backoff[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s12_backoff[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s11_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s11_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s11_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s10_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s10_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s9_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s9_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s9_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s8_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s8_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s8_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s7_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s7_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s7_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s6_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s6_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s13_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s13_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s6_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_backoff[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s12_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s4_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s5_backoff[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_bus_j[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_bus_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s6_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_bus_cd_id[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s5_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s4_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s3_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s3_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s3_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s3_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s4_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s5_l1[rip], al
	movzx	eax, BYTE PTR _x_s13_evt2[rip]
	test	al, al
	jne	.L176
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L177
.L176:
	movzx	eax, BYTE PTR _x_s13_evt2[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L177
.L178:
	movzx	eax, BYTE PTR _x_s13_evt2[rip]
	test	al, al
	je	.L179
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L177
.L179:
	movzx	eax, BYTE PTR _x_s13_evt2[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	je	.L177
.L180:
	movzx	eax, BYTE PTR _x_s13_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	test	al, al
	jne	.L181
.L177:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L183
.L182:
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L184
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L183
.L184:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L181
.L183:
	movss	xmm0, DWORD PTR _x_s13_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s13_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s13_x[rip]
	movss	xmm0, DWORD PTR _x_s13_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L186
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L181
.L186:
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L187
	movss	xmm0, DWORD PTR s13_lambda[rip]
	movss	xmm1, DWORD PTR _x_s13_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L187
	ucomiss	xmm0, xmm1
	jne	.L187
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s13_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s13_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L187
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L187
	movss	xmm0, DWORD PTR s13_backoff[rip]
	movss	xmm1, DWORD PTR _x_s13_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L187
	ucomiss	xmm0, xmm1
	je	.L190
.L187:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L181
.L190:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L194
.L193:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L195
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L194
.L195:
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L196
.L194:
	movss	xmm0, DWORD PTR s13_backoff[rip]
	movss	xmm1, DWORD PTR _x_s13_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L196
	ucomiss	xmm0, xmm1
	jne	.L196
	movss	xmm0, DWORD PTR _x_s13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L196
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L198
.L196:
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L198
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L198
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L198
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L198:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L200
	movss	xmm0, DWORD PTR s13_lambda[rip]
	movss	xmm1, DWORD PTR _x_s13_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L200
	ucomiss	xmm0, xmm1
	je	.L201
.L200:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L201
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L201
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L201
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L201:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L204
.L203:
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L204
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L204
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L204
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L204
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L204
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L204:
	movss	xmm0, DWORD PTR s13_lambda[rip]
	movss	xmm1, DWORD PTR _x_s13_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L205
	ucomiss	xmm0, xmm1
	jne	.L205
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L208
.L207:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L208
.L205:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L208
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L208
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L208
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L208
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L208
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L208:
	movss	xmm0, DWORD PTR s13_lambda[rip]
	movss	xmm1, DWORD PTR _x_s13_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L209
	ucomiss	xmm0, xmm1
	jne	.L209
	movss	xmm0, DWORD PTR _x_s13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L209
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L209
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L212
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L213
.L212:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L209
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L213
.L209:
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L213
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L213
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L213
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L213
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L213:
	movss	xmm1, DWORD PTR s13_lambda[rip]
	movss	xmm0, DWORD PTR s13_x[rip]
	comiss	xmm0, xmm1
	jb	.L214
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L214
	movss	xmm1, DWORD PTR _x_s13_backoff[rip]
	movss	xmm0, DWORD PTR s13_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L216
.L214:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L216
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L216
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L216
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L216
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L216
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L216:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L217
	movss	xmm0, DWORD PTR s13_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s13_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L218
.L217:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L218
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L218
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	je	.L218
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	jne	.L218
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L218
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L218
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L218:
	movss	xmm0, DWORD PTR s13_lambda[rip]
	movss	xmm1, DWORD PTR _x_s13_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L219
	ucomiss	xmm0, xmm1
	jne	.L219
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L222
.L221:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L219
.L222:
	movss	xmm0, DWORD PTR s13_backoff[rip]
	movss	xmm1, DWORD PTR _x_s13_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L219
	ucomiss	xmm0, xmm1
	jne	.L219
	movss	xmm0, DWORD PTR _x_s13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L219
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L224
.L219:
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L224
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L224
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L224
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L224:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L227
.L226:
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	jne	.L227
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L227
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L227
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L227
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L227:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L228
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L228
	movss	xmm1, DWORD PTR s13_backoff[rip]
	movss	xmm0, DWORD PTR s13_x[rip]
	comiss	xmm0, xmm1
	jnb	.L229
.L228:
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	test	al, al
	jne	.L229
	movzx	eax, BYTE PTR s13_l0[rip]
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR s13_l1[rip]
	test	al, al
	jne	.L229
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L229
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L229
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L181
.L229:
	movzx	eax, BYTE PTR _x_s12_evt2[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	je	.L230
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L231
.L230:
	movzx	eax, BYTE PTR _x_s12_evt2[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L231
.L232:
	movzx	eax, BYTE PTR _x_s12_evt2[rip]
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	jne	.L233
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L231
.L233:
	movzx	eax, BYTE PTR _x_s12_evt2[rip]
	test	al, al
	jne	.L234
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L234
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	je	.L231
.L234:
	movzx	eax, BYTE PTR _x_s12_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	test	al, al
	jne	.L181
.L231:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L236
.L235:
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L236
.L237:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L181
.L236:
	movss	xmm0, DWORD PTR _x_s12_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s12_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s12_x[rip]
	movss	xmm0, DWORD PTR _x_s12_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L239
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L239
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L181
.L239:
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L240
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L240
	movss	xmm0, DWORD PTR s12_lambda[rip]
	movss	xmm1, DWORD PTR _x_s12_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L240
	ucomiss	xmm0, xmm1
	jne	.L240
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L240
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L240
	movss	xmm0, DWORD PTR s12_backoff[rip]
	movss	xmm1, DWORD PTR _x_s12_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L240
	ucomiss	xmm0, xmm1
	je	.L243
.L240:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L243
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L243
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L181
.L243:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L247
.L246:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L247
.L248:
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L249
.L247:
	movss	xmm0, DWORD PTR s12_backoff[rip]
	movss	xmm1, DWORD PTR _x_s12_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L249
	ucomiss	xmm0, xmm1
	jne	.L249
	movss	xmm0, DWORD PTR _x_s12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L249
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L251
.L249:
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L251
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L251
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L251
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L251
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L251:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L253
	movss	xmm0, DWORD PTR s12_lambda[rip]
	movss	xmm1, DWORD PTR _x_s12_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L253
	ucomiss	xmm0, xmm1
	je	.L254
.L253:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L254
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L254
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L254
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L254
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L254
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L254
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L254:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L256
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L257
.L256:
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L257
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L257
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L257
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L257:
	movss	xmm0, DWORD PTR s12_lambda[rip]
	movss	xmm1, DWORD PTR _x_s12_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L258
	ucomiss	xmm0, xmm1
	jne	.L258
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	je	.L260
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L260
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L261
.L260:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L258
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L258
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L261
.L258:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L261
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L261
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L261
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L261
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L261
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L261
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L261:
	movss	xmm0, DWORD PTR s12_lambda[rip]
	movss	xmm1, DWORD PTR _x_s12_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L262
	ucomiss	xmm0, xmm1
	jne	.L262
	movss	xmm0, DWORD PTR _x_s12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L262
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L262
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L265
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L266
.L265:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L262
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L266
.L262:
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L266
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L266
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L266
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L266:
	movss	xmm1, DWORD PTR s12_lambda[rip]
	movss	xmm0, DWORD PTR s12_x[rip]
	comiss	xmm0, xmm1
	jb	.L267
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L267
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L267
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L267
	movss	xmm1, DWORD PTR _x_s12_backoff[rip]
	movss	xmm0, DWORD PTR s12_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L269
.L267:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L269
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L269
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L269
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L269
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L269
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L269
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L269:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L270
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L270
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L270
	movss	xmm0, DWORD PTR s12_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s12_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L271
.L270:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L271
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L271
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	je	.L271
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	jne	.L271
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L271
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L271
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L271:
	movss	xmm0, DWORD PTR s12_lambda[rip]
	movss	xmm1, DWORD PTR _x_s12_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L272
	ucomiss	xmm0, xmm1
	jne	.L272
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L274
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L275
.L274:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L272
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L272
.L275:
	movss	xmm0, DWORD PTR s12_backoff[rip]
	movss	xmm1, DWORD PTR _x_s12_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L272
	ucomiss	xmm0, xmm1
	jne	.L272
	movss	xmm0, DWORD PTR _x_s12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L272
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L277
.L272:
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L277
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L277
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L277
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L277:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L279
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L279
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L280
.L279:
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	je	.L280
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	jne	.L280
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L280
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L280
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L280
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L280
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L280:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	je	.L281
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L281
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L281
	movss	xmm1, DWORD PTR s12_backoff[rip]
	movss	xmm0, DWORD PTR s12_x[rip]
	comiss	xmm0, xmm1
	jnb	.L282
.L281:
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	test	al, al
	je	.L282
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	test	al, al
	jne	.L282
	movzx	eax, BYTE PTR s12_l0[rip]
	test	al, al
	je	.L282
	movzx	eax, BYTE PTR s12_l1[rip]
	test	al, al
	jne	.L282
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L282
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L282
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L181
.L282:
	movzx	eax, BYTE PTR _x_s11_evt2[rip]
	test	al, al
	jne	.L283
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	je	.L283
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L284
.L283:
	movzx	eax, BYTE PTR _x_s11_evt2[rip]
	test	al, al
	jne	.L285
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	jne	.L285
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L284
.L285:
	movzx	eax, BYTE PTR _x_s11_evt2[rip]
	test	al, al
	je	.L286
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	jne	.L286
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L284
.L286:
	movzx	eax, BYTE PTR _x_s11_evt2[rip]
	test	al, al
	jne	.L287
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L287
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	je	.L284
.L287:
	movzx	eax, BYTE PTR _x_s11_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	test	al, al
	jne	.L181
.L284:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L288
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L289
.L288:
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L289
.L290:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L181
.L289:
	movss	xmm0, DWORD PTR _x_s11_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s11_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s11_x[rip]
	movss	xmm0, DWORD PTR _x_s11_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L292
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L181
.L292:
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L293
	movss	xmm0, DWORD PTR s11_lambda[rip]
	movss	xmm1, DWORD PTR _x_s11_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L293
	ucomiss	xmm0, xmm1
	jne	.L293
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L293
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L293
	movss	xmm0, DWORD PTR s11_backoff[rip]
	movss	xmm1, DWORD PTR _x_s11_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L293
	ucomiss	xmm0, xmm1
	je	.L296
.L293:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L296
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L296
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L181
.L296:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L300
.L299:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L300
.L301:
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L302
.L300:
	movss	xmm0, DWORD PTR s11_backoff[rip]
	movss	xmm1, DWORD PTR _x_s11_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L302
	ucomiss	xmm0, xmm1
	jne	.L302
	movss	xmm0, DWORD PTR _x_s11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L302
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L304
.L302:
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L304
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L304
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L304
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L304
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L304:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L306
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L306
	movss	xmm0, DWORD PTR s11_lambda[rip]
	movss	xmm1, DWORD PTR _x_s11_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L306
	ucomiss	xmm0, xmm1
	je	.L307
.L306:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L307
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L307
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L307
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L307
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L307
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L307
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L307:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L309
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L310
.L309:
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L310
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L310
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L310
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L310
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L310:
	movss	xmm0, DWORD PTR s11_lambda[rip]
	movss	xmm1, DWORD PTR _x_s11_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L311
	ucomiss	xmm0, xmm1
	jne	.L311
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L314
.L313:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L311
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L311
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L314
.L311:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L314
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L314
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L314
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L314
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L314
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L314
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L314:
	movss	xmm0, DWORD PTR s11_lambda[rip]
	movss	xmm1, DWORD PTR _x_s11_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L315
	ucomiss	xmm0, xmm1
	jne	.L315
	movss	xmm0, DWORD PTR _x_s11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L315
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L315
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L318
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L319
.L318:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L319
.L315:
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L319
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L319
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L319
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L319
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L319:
	movss	xmm1, DWORD PTR s11_lambda[rip]
	movss	xmm0, DWORD PTR s11_x[rip]
	comiss	xmm0, xmm1
	jb	.L320
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L320
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L320
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L320
	movss	xmm1, DWORD PTR _x_s11_backoff[rip]
	movss	xmm0, DWORD PTR s11_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L322
.L320:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L322
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L322
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L322
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L322
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L322
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L322
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L322:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L323
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L323
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L323
	movss	xmm0, DWORD PTR s11_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s11_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L324
.L323:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L324
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L324
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	je	.L324
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	jne	.L324
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L324
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L324
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L324:
	movss	xmm0, DWORD PTR s11_lambda[rip]
	movss	xmm1, DWORD PTR _x_s11_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L325
	ucomiss	xmm0, xmm1
	jne	.L325
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L327
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L328
.L327:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L325
.L328:
	movss	xmm0, DWORD PTR s11_backoff[rip]
	movss	xmm1, DWORD PTR _x_s11_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L325
	ucomiss	xmm0, xmm1
	jne	.L325
	movss	xmm0, DWORD PTR _x_s11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L325
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L330
.L325:
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L330
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L330
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L330
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L330
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L330:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L332
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L333
.L332:
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	je	.L333
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	jne	.L333
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L333
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L333
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L333
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L333
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L333:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	je	.L334
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L334
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L334
	movss	xmm1, DWORD PTR s11_backoff[rip]
	movss	xmm0, DWORD PTR s11_x[rip]
	comiss	xmm0, xmm1
	jnb	.L335
.L334:
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	test	al, al
	jne	.L335
	movzx	eax, BYTE PTR s11_l0[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR s11_l1[rip]
	test	al, al
	jne	.L335
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L335
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L335
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L181
.L335:
	movzx	eax, BYTE PTR _x_s10_evt2[rip]
	test	al, al
	jne	.L336
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	je	.L336
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L337
.L336:
	movzx	eax, BYTE PTR _x_s10_evt2[rip]
	test	al, al
	jne	.L338
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	jne	.L338
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L337
.L338:
	movzx	eax, BYTE PTR _x_s10_evt2[rip]
	test	al, al
	je	.L339
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	jne	.L339
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L337
.L339:
	movzx	eax, BYTE PTR _x_s10_evt2[rip]
	test	al, al
	jne	.L340
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L340
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	je	.L337
.L340:
	movzx	eax, BYTE PTR _x_s10_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	test	al, al
	jne	.L181
.L337:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L341
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L342
.L341:
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L343
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L342
.L343:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L181
.L342:
	movss	xmm0, DWORD PTR _x_s10_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s10_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s10_x[rip]
	movss	xmm0, DWORD PTR _x_s10_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L345
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L181
.L345:
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L346
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L346
	movss	xmm0, DWORD PTR s10_lambda[rip]
	movss	xmm1, DWORD PTR _x_s10_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L346
	ucomiss	xmm0, xmm1
	jne	.L346
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L346
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L346
	movss	xmm0, DWORD PTR s10_backoff[rip]
	movss	xmm1, DWORD PTR _x_s10_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L346
	ucomiss	xmm0, xmm1
	je	.L349
.L346:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L349
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L349
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L181
.L349:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L352
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L353
.L352:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L354
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L353
.L354:
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L355
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L355
.L353:
	movss	xmm0, DWORD PTR s10_backoff[rip]
	movss	xmm1, DWORD PTR _x_s10_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L355
	ucomiss	xmm0, xmm1
	jne	.L355
	movss	xmm0, DWORD PTR _x_s10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L355
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L357
.L355:
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L357
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L357
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L357
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L357
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L357:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L359
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L359
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L359
	movss	xmm0, DWORD PTR s10_lambda[rip]
	movss	xmm1, DWORD PTR _x_s10_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L359
	ucomiss	xmm0, xmm1
	je	.L360
.L359:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L360
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L360
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L360
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L360
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L360
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L360
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L360:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	je	.L362
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L362
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L363
.L362:
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L363
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L363
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L363
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L363
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L363
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L363
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L363:
	movss	xmm0, DWORD PTR s10_lambda[rip]
	movss	xmm1, DWORD PTR _x_s10_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L364
	ucomiss	xmm0, xmm1
	jne	.L364
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	je	.L366
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L366
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L367
.L366:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L364
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L364
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L367
.L364:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L367
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L367
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L367
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L367
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L367
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L367
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L367:
	movss	xmm0, DWORD PTR s10_lambda[rip]
	movss	xmm1, DWORD PTR _x_s10_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L368
	ucomiss	xmm0, xmm1
	jne	.L368
	movss	xmm0, DWORD PTR _x_s10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L368
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L368
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L371
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L372
.L371:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L372
.L368:
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L372
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L372
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L372
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L372
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L372:
	movss	xmm1, DWORD PTR s10_lambda[rip]
	movss	xmm0, DWORD PTR s10_x[rip]
	comiss	xmm0, xmm1
	jb	.L373
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L373
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L373
	movss	xmm1, DWORD PTR _x_s10_backoff[rip]
	movss	xmm0, DWORD PTR s10_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L375
.L373:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L375
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L375
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L375
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L375
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L375
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L375
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L375:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L376
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L376
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L376
	movss	xmm0, DWORD PTR s10_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s10_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L377
.L376:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L377
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L377
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	je	.L377
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	jne	.L377
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L377
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L377
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L377:
	movss	xmm0, DWORD PTR s10_lambda[rip]
	movss	xmm1, DWORD PTR _x_s10_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L378
	ucomiss	xmm0, xmm1
	jne	.L378
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L380
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L381
.L380:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L378
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L378
.L381:
	movss	xmm0, DWORD PTR s10_backoff[rip]
	movss	xmm1, DWORD PTR _x_s10_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L378
	ucomiss	xmm0, xmm1
	jne	.L378
	movss	xmm0, DWORD PTR _x_s10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L378
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L383
.L378:
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L383
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L383
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L383
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L383
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L383:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L385
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L386
.L385:
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	je	.L386
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	jne	.L386
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L386
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L386
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L386
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L386
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L386:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	je	.L387
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L387
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L387
	movss	xmm1, DWORD PTR s10_backoff[rip]
	movss	xmm0, DWORD PTR s10_x[rip]
	comiss	xmm0, xmm1
	jnb	.L388
.L387:
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	test	al, al
	je	.L388
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	test	al, al
	jne	.L388
	movzx	eax, BYTE PTR s10_l0[rip]
	test	al, al
	je	.L388
	movzx	eax, BYTE PTR s10_l1[rip]
	test	al, al
	jne	.L388
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L388
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L388
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L181
.L388:
	movzx	eax, BYTE PTR _x_s9_evt2[rip]
	test	al, al
	jne	.L389
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	je	.L389
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L390
.L389:
	movzx	eax, BYTE PTR _x_s9_evt2[rip]
	test	al, al
	jne	.L391
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	jne	.L391
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L390
.L391:
	movzx	eax, BYTE PTR _x_s9_evt2[rip]
	test	al, al
	je	.L392
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	jne	.L392
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L390
.L392:
	movzx	eax, BYTE PTR _x_s9_evt2[rip]
	test	al, al
	jne	.L393
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	je	.L390
.L393:
	movzx	eax, BYTE PTR _x_s9_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	test	al, al
	jne	.L181
.L390:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L394
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L395
.L394:
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L396
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L395
.L396:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L181
.L395:
	movss	xmm0, DWORD PTR _x_s9_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s9_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s9_x[rip]
	movss	xmm0, DWORD PTR _x_s9_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L398
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L398
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L181
.L398:
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L399
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L399
	movss	xmm0, DWORD PTR s9_lambda[rip]
	movss	xmm1, DWORD PTR _x_s9_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L399
	ucomiss	xmm0, xmm1
	jne	.L399
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L399
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L399
	movss	xmm0, DWORD PTR s9_backoff[rip]
	movss	xmm1, DWORD PTR _x_s9_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L399
	ucomiss	xmm0, xmm1
	je	.L402
.L399:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L402
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L402
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L181
.L402:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L405
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L406
.L405:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L407
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L406
.L407:
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L408
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L408
.L406:
	movss	xmm0, DWORD PTR s9_backoff[rip]
	movss	xmm1, DWORD PTR _x_s9_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L408
	ucomiss	xmm0, xmm1
	jne	.L408
	movss	xmm0, DWORD PTR _x_s9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L408
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L410
.L408:
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L410
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L410
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L410
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L410
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L410:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L412
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L412
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L412
	movss	xmm0, DWORD PTR s9_lambda[rip]
	movss	xmm1, DWORD PTR _x_s9_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L412
	ucomiss	xmm0, xmm1
	je	.L413
.L412:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L413
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L413
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L413
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L413
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L413
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L413
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L413:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	je	.L415
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L415
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L416
.L415:
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L416
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L416
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L416
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L416
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L416
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L416
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L416:
	movss	xmm0, DWORD PTR s9_lambda[rip]
	movss	xmm1, DWORD PTR _x_s9_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L417
	ucomiss	xmm0, xmm1
	jne	.L417
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	je	.L419
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L419
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L420
.L419:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L417
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L420
.L417:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L420
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L420
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L420
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L420
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L420
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L420
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L420:
	movss	xmm0, DWORD PTR s9_lambda[rip]
	movss	xmm1, DWORD PTR _x_s9_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L421
	ucomiss	xmm0, xmm1
	jne	.L421
	movss	xmm0, DWORD PTR _x_s9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L421
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L421
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L424
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L425
.L424:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L425
.L421:
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L425
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L425
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L425
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L425
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L425:
	movss	xmm1, DWORD PTR s9_lambda[rip]
	movss	xmm0, DWORD PTR s9_x[rip]
	comiss	xmm0, xmm1
	jb	.L426
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L426
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L426
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L426
	movss	xmm1, DWORD PTR _x_s9_backoff[rip]
	movss	xmm0, DWORD PTR s9_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L428
.L426:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L428
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L428
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L428
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L428
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L428
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L428
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L428:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L429
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L429
	movss	xmm0, DWORD PTR s9_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s9_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L430
.L429:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L430
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L430
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	je	.L430
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	jne	.L430
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L430
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L430
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L430:
	movss	xmm0, DWORD PTR s9_lambda[rip]
	movss	xmm1, DWORD PTR _x_s9_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L431
	ucomiss	xmm0, xmm1
	jne	.L431
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L434
.L433:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L431
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L431
.L434:
	movss	xmm0, DWORD PTR s9_backoff[rip]
	movss	xmm1, DWORD PTR _x_s9_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L431
	ucomiss	xmm0, xmm1
	jne	.L431
	movss	xmm0, DWORD PTR _x_s9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L431
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L436
.L431:
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L436
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L436
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L436
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L436
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L436:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L438
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L438
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L439
.L438:
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	je	.L439
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	jne	.L439
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L439
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L439
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L439
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L439
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L439:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L440
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L440
	movss	xmm1, DWORD PTR s9_backoff[rip]
	movss	xmm0, DWORD PTR s9_x[rip]
	comiss	xmm0, xmm1
	jnb	.L441
.L440:
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	test	al, al
	je	.L441
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	test	al, al
	jne	.L441
	movzx	eax, BYTE PTR s9_l0[rip]
	test	al, al
	je	.L441
	movzx	eax, BYTE PTR s9_l1[rip]
	test	al, al
	jne	.L441
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L441
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L441
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L181
.L441:
	movzx	eax, BYTE PTR _x_s8_evt2[rip]
	test	al, al
	jne	.L442
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	je	.L442
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L443
.L442:
	movzx	eax, BYTE PTR _x_s8_evt2[rip]
	test	al, al
	jne	.L444
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	jne	.L444
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L443
.L444:
	movzx	eax, BYTE PTR _x_s8_evt2[rip]
	test	al, al
	je	.L445
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	jne	.L445
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L443
.L445:
	movzx	eax, BYTE PTR _x_s8_evt2[rip]
	test	al, al
	jne	.L446
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L446
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	je	.L443
.L446:
	movzx	eax, BYTE PTR _x_s8_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	test	al, al
	jne	.L181
.L443:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L447
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L448
.L447:
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L449
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L448
.L449:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L181
.L448:
	movss	xmm0, DWORD PTR _x_s8_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s8_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s8_x[rip]
	movss	xmm0, DWORD PTR _x_s8_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L451
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L451
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L181
.L451:
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L452
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L452
	movss	xmm0, DWORD PTR s8_lambda[rip]
	movss	xmm1, DWORD PTR _x_s8_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L452
	ucomiss	xmm0, xmm1
	jne	.L452
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L452
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L452
	movss	xmm0, DWORD PTR s8_backoff[rip]
	movss	xmm1, DWORD PTR _x_s8_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L452
	ucomiss	xmm0, xmm1
	je	.L455
.L452:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L455
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L455
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L181
.L455:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L458
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L459
.L458:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L460
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L459
.L460:
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L461
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L461
.L459:
	movss	xmm0, DWORD PTR s8_backoff[rip]
	movss	xmm1, DWORD PTR _x_s8_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L461
	ucomiss	xmm0, xmm1
	jne	.L461
	movss	xmm0, DWORD PTR _x_s8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L461
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L463
.L461:
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L463
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L463
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L463
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L463
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L463:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L465
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L465
	movss	xmm0, DWORD PTR s8_lambda[rip]
	movss	xmm1, DWORD PTR _x_s8_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L465
	ucomiss	xmm0, xmm1
	je	.L466
.L465:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L466
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L466
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L466
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L466
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L466
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L466
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L466:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	je	.L468
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L468
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L469
.L468:
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L469
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L469
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L469
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L469
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L469
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L469:
	movss	xmm0, DWORD PTR s8_lambda[rip]
	movss	xmm1, DWORD PTR _x_s8_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L470
	ucomiss	xmm0, xmm1
	jne	.L470
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L473
.L472:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L470
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L470
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L473
.L470:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L473
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L473
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L473
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L473
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L473
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L473:
	movss	xmm0, DWORD PTR s8_lambda[rip]
	movss	xmm1, DWORD PTR _x_s8_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L474
	ucomiss	xmm0, xmm1
	jne	.L474
	movss	xmm0, DWORD PTR _x_s8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L474
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L474
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L477
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L478
.L477:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L474
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L478
.L474:
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L478
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L478
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L478
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L478
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L478:
	movss	xmm1, DWORD PTR s8_lambda[rip]
	movss	xmm0, DWORD PTR s8_x[rip]
	comiss	xmm0, xmm1
	jb	.L479
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L479
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L479
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L479
	movss	xmm1, DWORD PTR _x_s8_backoff[rip]
	movss	xmm0, DWORD PTR s8_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L481
.L479:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L481
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L481
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L481
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L481
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L481
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L481
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L481:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L482
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L482
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L482
	movss	xmm0, DWORD PTR s8_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s8_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L483
.L482:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L483
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L483
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	je	.L483
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	jne	.L483
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L483
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L483
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L483:
	movss	xmm0, DWORD PTR s8_lambda[rip]
	movss	xmm1, DWORD PTR _x_s8_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L484
	ucomiss	xmm0, xmm1
	jne	.L484
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L486
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L487
.L486:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L484
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L484
.L487:
	movss	xmm0, DWORD PTR s8_backoff[rip]
	movss	xmm1, DWORD PTR _x_s8_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L484
	ucomiss	xmm0, xmm1
	jne	.L484
	movss	xmm0, DWORD PTR _x_s8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L484
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L489
.L484:
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L489
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L489
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L489
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L489:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L491
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L491
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L492
.L491:
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	je	.L492
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	jne	.L492
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L492
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L492
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L492
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L492
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L492:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L493
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L493
	movss	xmm1, DWORD PTR s8_backoff[rip]
	movss	xmm0, DWORD PTR s8_x[rip]
	comiss	xmm0, xmm1
	jnb	.L494
.L493:
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	test	al, al
	je	.L494
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	test	al, al
	jne	.L494
	movzx	eax, BYTE PTR s8_l0[rip]
	test	al, al
	je	.L494
	movzx	eax, BYTE PTR s8_l1[rip]
	test	al, al
	jne	.L494
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L494
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L494
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L181
.L494:
	movzx	eax, BYTE PTR _x_s7_evt2[rip]
	test	al, al
	jne	.L495
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L496
.L495:
	movzx	eax, BYTE PTR _x_s7_evt2[rip]
	test	al, al
	jne	.L497
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	jne	.L497
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L496
.L497:
	movzx	eax, BYTE PTR _x_s7_evt2[rip]
	test	al, al
	je	.L498
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	jne	.L498
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L496
.L498:
	movzx	eax, BYTE PTR _x_s7_evt2[rip]
	test	al, al
	jne	.L499
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L499
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	je	.L496
.L499:
	movzx	eax, BYTE PTR _x_s7_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	test	al, al
	jne	.L181
.L496:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L500
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L501
.L500:
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L502
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L501
.L502:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L181
.L501:
	movss	xmm0, DWORD PTR _x_s7_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s7_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s7_x[rip]
	movss	xmm0, DWORD PTR _x_s7_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L504
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L504
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L181
.L504:
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L505
	movss	xmm0, DWORD PTR s7_lambda[rip]
	movss	xmm1, DWORD PTR _x_s7_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L505
	ucomiss	xmm0, xmm1
	jne	.L505
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L505
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L505
	movss	xmm0, DWORD PTR s7_backoff[rip]
	movss	xmm1, DWORD PTR _x_s7_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L505
	ucomiss	xmm0, xmm1
	je	.L508
.L505:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L508
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L508
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L181
.L508:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L511
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L512
.L511:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L513
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L512
.L513:
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L514
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L514
.L512:
	movss	xmm0, DWORD PTR s7_backoff[rip]
	movss	xmm1, DWORD PTR _x_s7_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L514
	ucomiss	xmm0, xmm1
	jne	.L514
	movss	xmm0, DWORD PTR _x_s7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L514
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L516
.L514:
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L516
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L516
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L516
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L516
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L516:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L518
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L518
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L518
	movss	xmm0, DWORD PTR s7_lambda[rip]
	movss	xmm1, DWORD PTR _x_s7_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L518
	ucomiss	xmm0, xmm1
	je	.L519
.L518:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L519
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L519
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L519
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L519
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L519
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L519
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L519:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	je	.L521
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L521
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L522
.L521:
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L522
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L522
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L522
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L522
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L522
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L522
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L522:
	movss	xmm0, DWORD PTR s7_lambda[rip]
	movss	xmm1, DWORD PTR _x_s7_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L523
	ucomiss	xmm0, xmm1
	jne	.L523
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L526
.L525:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L523
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L523
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L526
.L523:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L526
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L526
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L526
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L526
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L526:
	movss	xmm0, DWORD PTR s7_lambda[rip]
	movss	xmm1, DWORD PTR _x_s7_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L527
	ucomiss	xmm0, xmm1
	jne	.L527
	movss	xmm0, DWORD PTR _x_s7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L527
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L527
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L530
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L531
.L530:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L527
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L531
.L527:
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L531
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L531
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L531
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L531
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L531:
	movss	xmm1, DWORD PTR s7_lambda[rip]
	movss	xmm0, DWORD PTR s7_x[rip]
	comiss	xmm0, xmm1
	jb	.L532
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L532
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L532
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L532
	movss	xmm1, DWORD PTR _x_s7_backoff[rip]
	movss	xmm0, DWORD PTR s7_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L534
.L532:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L534
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L534
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L534
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L534
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L534:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L535
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L535
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L535
	movss	xmm0, DWORD PTR s7_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s7_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L536
.L535:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L536
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	jne	.L536
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L536
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L536
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L536:
	movss	xmm0, DWORD PTR s7_lambda[rip]
	movss	xmm1, DWORD PTR _x_s7_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L537
	ucomiss	xmm0, xmm1
	jne	.L537
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L539
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L540
.L539:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L537
.L540:
	movss	xmm0, DWORD PTR s7_backoff[rip]
	movss	xmm1, DWORD PTR _x_s7_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L537
	ucomiss	xmm0, xmm1
	jne	.L537
	movss	xmm0, DWORD PTR _x_s7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L537
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L542
.L537:
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L542
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L542
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L542
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L542
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L542:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L544
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L544
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L545
.L544:
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	jne	.L545
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L545
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L545
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L545
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L545:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	je	.L546
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L546
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L546
	movss	xmm1, DWORD PTR s7_backoff[rip]
	movss	xmm0, DWORD PTR s7_x[rip]
	comiss	xmm0, xmm1
	jnb	.L547
.L546:
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	test	al, al
	je	.L547
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	test	al, al
	jne	.L547
	movzx	eax, BYTE PTR s7_l0[rip]
	test	al, al
	je	.L547
	movzx	eax, BYTE PTR s7_l1[rip]
	test	al, al
	jne	.L547
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L547
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L547
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L181
.L547:
	movzx	eax, BYTE PTR _x_s6_evt2[rip]
	test	al, al
	jne	.L548
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L549
.L548:
	movzx	eax, BYTE PTR _x_s6_evt2[rip]
	test	al, al
	jne	.L550
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	jne	.L550
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L549
.L550:
	movzx	eax, BYTE PTR _x_s6_evt2[rip]
	test	al, al
	je	.L551
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	jne	.L551
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L549
.L551:
	movzx	eax, BYTE PTR _x_s6_evt2[rip]
	test	al, al
	jne	.L552
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L552
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	je	.L549
.L552:
	movzx	eax, BYTE PTR _x_s6_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	test	al, al
	jne	.L181
.L549:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L553
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L554
.L553:
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L555
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L554
.L555:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L181
.L554:
	movss	xmm0, DWORD PTR _x_s6_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s6_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s6_x[rip]
	movss	xmm0, DWORD PTR _x_s6_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L557
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L557
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L181
.L557:
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L558
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L558
	movss	xmm0, DWORD PTR s6_lambda[rip]
	movss	xmm1, DWORD PTR _x_s6_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L558
	ucomiss	xmm0, xmm1
	jne	.L558
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L558
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L558
	movss	xmm0, DWORD PTR s6_backoff[rip]
	movss	xmm1, DWORD PTR _x_s6_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L558
	ucomiss	xmm0, xmm1
	je	.L561
.L558:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L561
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L561
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L181
.L561:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L565
.L564:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L566
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L565
.L566:
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L567
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L567
.L565:
	movss	xmm0, DWORD PTR s6_backoff[rip]
	movss	xmm1, DWORD PTR _x_s6_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L567
	ucomiss	xmm0, xmm1
	jne	.L567
	movss	xmm0, DWORD PTR _x_s6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L567
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L569
.L567:
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L569
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L569
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L569
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L569
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L569:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L571
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L571
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L571
	movss	xmm0, DWORD PTR s6_lambda[rip]
	movss	xmm1, DWORD PTR _x_s6_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L571
	ucomiss	xmm0, xmm1
	je	.L572
.L571:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L572
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L572
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L572
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L572
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L572
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L572
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L572:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	je	.L574
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L574
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L575
.L574:
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L575
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L575
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L575
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L575
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L575
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L575
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L575:
	movss	xmm0, DWORD PTR s6_lambda[rip]
	movss	xmm1, DWORD PTR _x_s6_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L576
	ucomiss	xmm0, xmm1
	jne	.L576
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L579
.L578:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L576
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L576
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L579
.L576:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L579
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L579
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L579
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L579
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L579
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L579
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L579:
	movss	xmm0, DWORD PTR s6_lambda[rip]
	movss	xmm1, DWORD PTR _x_s6_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L580
	ucomiss	xmm0, xmm1
	jne	.L580
	movss	xmm0, DWORD PTR _x_s6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L580
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L580
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L583
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L584
.L583:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L580
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L584
.L580:
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L584
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L584
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L584
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L584:
	movss	xmm1, DWORD PTR s6_lambda[rip]
	movss	xmm0, DWORD PTR s6_x[rip]
	comiss	xmm0, xmm1
	jb	.L585
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L585
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L585
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L585
	movss	xmm1, DWORD PTR _x_s6_backoff[rip]
	movss	xmm0, DWORD PTR s6_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L587
.L585:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L587
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L587
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L587
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L587
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L587
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L587
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L587:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L588
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L588
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L588
	movss	xmm0, DWORD PTR s6_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s6_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L589
.L588:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L589
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L589
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	je	.L589
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	jne	.L589
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L589
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L589
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L589:
	movss	xmm0, DWORD PTR s6_lambda[rip]
	movss	xmm1, DWORD PTR _x_s6_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L590
	ucomiss	xmm0, xmm1
	jne	.L590
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L592
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L593
.L592:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L590
.L593:
	movss	xmm0, DWORD PTR s6_backoff[rip]
	movss	xmm1, DWORD PTR _x_s6_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L590
	ucomiss	xmm0, xmm1
	jne	.L590
	movss	xmm0, DWORD PTR _x_s6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L590
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L595
.L590:
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L595
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L595
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L595
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L595
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L595:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L597
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L598
.L597:
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	je	.L598
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	jne	.L598
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L598
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L598
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L598
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L598
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L598:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	je	.L599
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L599
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L599
	movss	xmm1, DWORD PTR s6_backoff[rip]
	movss	xmm0, DWORD PTR s6_x[rip]
	comiss	xmm0, xmm1
	jnb	.L600
.L599:
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	test	al, al
	je	.L600
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	test	al, al
	jne	.L600
	movzx	eax, BYTE PTR s6_l0[rip]
	test	al, al
	je	.L600
	movzx	eax, BYTE PTR s6_l1[rip]
	test	al, al
	jne	.L600
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L600
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L600
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L181
.L600:
	movzx	eax, BYTE PTR _x_s5_evt2[rip]
	test	al, al
	jne	.L601
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L602
.L601:
	movzx	eax, BYTE PTR _x_s5_evt2[rip]
	test	al, al
	jne	.L603
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	jne	.L603
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L602
.L603:
	movzx	eax, BYTE PTR _x_s5_evt2[rip]
	test	al, al
	je	.L604
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	jne	.L604
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L602
.L604:
	movzx	eax, BYTE PTR _x_s5_evt2[rip]
	test	al, al
	jne	.L605
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L605
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	je	.L602
.L605:
	movzx	eax, BYTE PTR _x_s5_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	test	al, al
	jne	.L181
.L602:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L606
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L607
.L606:
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L608
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L607
.L608:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L181
.L607:
	movss	xmm0, DWORD PTR _x_s5_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s5_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s5_x[rip]
	movss	xmm0, DWORD PTR _x_s5_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L610
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L610
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L181
.L610:
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L611
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L611
	movss	xmm0, DWORD PTR s5_lambda[rip]
	movss	xmm1, DWORD PTR _x_s5_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L611
	ucomiss	xmm0, xmm1
	jne	.L611
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L611
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L611
	movss	xmm0, DWORD PTR s5_backoff[rip]
	movss	xmm1, DWORD PTR _x_s5_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L611
	ucomiss	xmm0, xmm1
	je	.L614
.L611:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L614
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L614
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L181
.L614:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L618
.L617:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L619
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L618
.L619:
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L620
.L618:
	movss	xmm0, DWORD PTR s5_backoff[rip]
	movss	xmm1, DWORD PTR _x_s5_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L620
	ucomiss	xmm0, xmm1
	jne	.L620
	movss	xmm0, DWORD PTR _x_s5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L620
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L622
.L620:
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L622
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L622
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L622
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L622
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L622:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L624
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L624
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L624
	movss	xmm0, DWORD PTR s5_lambda[rip]
	movss	xmm1, DWORD PTR _x_s5_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L624
	ucomiss	xmm0, xmm1
	je	.L625
.L624:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L625
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L625
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L625
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L625
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L625
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L625
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L625:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	je	.L627
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L627
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L628
.L627:
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L628
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L628
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L628
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L628
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L628
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L628
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L628:
	movss	xmm0, DWORD PTR s5_lambda[rip]
	movss	xmm1, DWORD PTR _x_s5_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L629
	ucomiss	xmm0, xmm1
	jne	.L629
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	je	.L631
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L631
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L632
.L631:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L629
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L629
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L632
.L629:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L632
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L632
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L632
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L632
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L632
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L632
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L632:
	movss	xmm0, DWORD PTR s5_lambda[rip]
	movss	xmm1, DWORD PTR _x_s5_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L633
	ucomiss	xmm0, xmm1
	jne	.L633
	movss	xmm0, DWORD PTR _x_s5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L633
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L633
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L637
.L636:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L637
.L633:
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L637
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L637
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L637
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L637:
	movss	xmm1, DWORD PTR s5_lambda[rip]
	movss	xmm0, DWORD PTR s5_x[rip]
	comiss	xmm0, xmm1
	jb	.L638
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L638
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L638
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L638
	movss	xmm1, DWORD PTR _x_s5_backoff[rip]
	movss	xmm0, DWORD PTR s5_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L640
.L638:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L640
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L640
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L640
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L640
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L640
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L640
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L640:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L641
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L641
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L641
	movss	xmm0, DWORD PTR s5_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s5_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L642
.L641:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L642
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	je	.L642
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	jne	.L642
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L642
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L642
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L642:
	movss	xmm0, DWORD PTR s5_lambda[rip]
	movss	xmm1, DWORD PTR _x_s5_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L643
	ucomiss	xmm0, xmm1
	jne	.L643
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L646
.L645:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L643
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L643
.L646:
	movss	xmm0, DWORD PTR s5_backoff[rip]
	movss	xmm1, DWORD PTR _x_s5_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L643
	ucomiss	xmm0, xmm1
	jne	.L643
	movss	xmm0, DWORD PTR _x_s5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L643
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L648
.L643:
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L648
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L648
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L648
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L648
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L648:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L650
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L650
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L651
.L650:
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	je	.L651
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	jne	.L651
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L651
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L651
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L651
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L651
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L651:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	je	.L652
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L652
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L652
	movss	xmm1, DWORD PTR s5_backoff[rip]
	movss	xmm0, DWORD PTR s5_x[rip]
	comiss	xmm0, xmm1
	jnb	.L653
.L652:
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR s5_l0[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR s5_l1[rip]
	test	al, al
	jne	.L653
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L653
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L653
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L181
.L653:
	movzx	eax, BYTE PTR _x_s4_evt2[rip]
	test	al, al
	jne	.L654
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	je	.L654
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L655
.L654:
	movzx	eax, BYTE PTR _x_s4_evt2[rip]
	test	al, al
	jne	.L656
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	jne	.L656
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L655
.L656:
	movzx	eax, BYTE PTR _x_s4_evt2[rip]
	test	al, al
	je	.L657
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	jne	.L657
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L655
.L657:
	movzx	eax, BYTE PTR _x_s4_evt2[rip]
	test	al, al
	jne	.L658
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L658
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	je	.L655
.L658:
	movzx	eax, BYTE PTR _x_s4_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	test	al, al
	jne	.L181
.L655:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L659
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L660
.L659:
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L661
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L660
.L661:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L181
.L660:
	movss	xmm0, DWORD PTR _x_s4_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s4_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s4_x[rip]
	movss	xmm0, DWORD PTR _x_s4_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L663
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L663
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L181
.L663:
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L664
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L664
	movss	xmm0, DWORD PTR s4_lambda[rip]
	movss	xmm1, DWORD PTR _x_s4_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L664
	ucomiss	xmm0, xmm1
	jne	.L664
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L664
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L664
	movss	xmm0, DWORD PTR s4_backoff[rip]
	movss	xmm1, DWORD PTR _x_s4_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L664
	ucomiss	xmm0, xmm1
	je	.L667
.L664:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L667
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L667
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L181
.L667:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L670
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L671
.L670:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L672
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L671
.L672:
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L673
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L673
.L671:
	movss	xmm0, DWORD PTR s4_backoff[rip]
	movss	xmm1, DWORD PTR _x_s4_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L673
	ucomiss	xmm0, xmm1
	jne	.L673
	movss	xmm0, DWORD PTR _x_s4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L673
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L675
.L673:
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L675
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L675
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L675
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L675
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L675:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L677
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L677
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L677
	movss	xmm0, DWORD PTR s4_lambda[rip]
	movss	xmm1, DWORD PTR _x_s4_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L677
	ucomiss	xmm0, xmm1
	je	.L678
.L677:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L678
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L678
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L678
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L678
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L678
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L678
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L678:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	je	.L680
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L680
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L681
.L680:
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L681
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L681
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L681
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L681
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L681
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L681:
	movss	xmm0, DWORD PTR s4_lambda[rip]
	movss	xmm1, DWORD PTR _x_s4_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L682
	ucomiss	xmm0, xmm1
	jne	.L682
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	je	.L684
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L684
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L685
.L684:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L682
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L682
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L685
.L682:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L685
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L685
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L685
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L685
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L685
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L685:
	movss	xmm0, DWORD PTR s4_lambda[rip]
	movss	xmm1, DWORD PTR _x_s4_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L686
	ucomiss	xmm0, xmm1
	jne	.L686
	movss	xmm0, DWORD PTR _x_s4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L686
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L686
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L689
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L690
.L689:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L686
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L690
.L686:
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L690
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L690
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L690
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L690
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L690:
	movss	xmm1, DWORD PTR s4_lambda[rip]
	movss	xmm0, DWORD PTR s4_x[rip]
	comiss	xmm0, xmm1
	jb	.L691
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L691
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L691
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L691
	movss	xmm1, DWORD PTR _x_s4_backoff[rip]
	movss	xmm0, DWORD PTR s4_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L693
.L691:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L693
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L693
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L693
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L693
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L693
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L693
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L693:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L694
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L694
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L694
	movss	xmm0, DWORD PTR s4_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s4_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L695
.L694:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L695
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L695
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	je	.L695
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	jne	.L695
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L695
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L695
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L695:
	movss	xmm0, DWORD PTR s4_lambda[rip]
	movss	xmm1, DWORD PTR _x_s4_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L696
	ucomiss	xmm0, xmm1
	jne	.L696
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L698
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L699
.L698:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L696
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L696
.L699:
	movss	xmm0, DWORD PTR s4_backoff[rip]
	movss	xmm1, DWORD PTR _x_s4_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L696
	ucomiss	xmm0, xmm1
	jne	.L696
	movss	xmm0, DWORD PTR _x_s4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L696
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L701
.L696:
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L701
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L701
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L701
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L701
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L701:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L703
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L703
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L704
.L703:
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	jne	.L704
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L704
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L704
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L704
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L704:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L705
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L705
	movss	xmm1, DWORD PTR s4_backoff[rip]
	movss	xmm0, DWORD PTR s4_x[rip]
	comiss	xmm0, xmm1
	jnb	.L706
.L705:
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	test	al, al
	je	.L706
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	test	al, al
	jne	.L706
	movzx	eax, BYTE PTR s4_l0[rip]
	test	al, al
	je	.L706
	movzx	eax, BYTE PTR s4_l1[rip]
	test	al, al
	jne	.L706
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L706
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L706
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L181
.L706:
	movzx	eax, BYTE PTR _x_s3_evt2[rip]
	test	al, al
	jne	.L707
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	je	.L707
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L708
.L707:
	movzx	eax, BYTE PTR _x_s3_evt2[rip]
	test	al, al
	jne	.L709
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	jne	.L709
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L708
.L709:
	movzx	eax, BYTE PTR _x_s3_evt2[rip]
	test	al, al
	je	.L710
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	jne	.L710
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L708
.L710:
	movzx	eax, BYTE PTR _x_s3_evt2[rip]
	test	al, al
	jne	.L711
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L711
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	je	.L708
.L711:
	movzx	eax, BYTE PTR _x_s3_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	test	al, al
	jne	.L181
.L708:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L712
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L713
.L712:
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L714
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L713
.L714:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L181
.L713:
	movss	xmm0, DWORD PTR _x_s3_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s3_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s3_x[rip]
	movss	xmm0, DWORD PTR _x_s3_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L716
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L716
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L181
.L716:
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L717
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L717
	movss	xmm0, DWORD PTR s3_lambda[rip]
	movss	xmm1, DWORD PTR _x_s3_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L717
	ucomiss	xmm0, xmm1
	jne	.L717
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L717
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L717
	movss	xmm0, DWORD PTR s3_backoff[rip]
	movss	xmm1, DWORD PTR _x_s3_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L717
	ucomiss	xmm0, xmm1
	je	.L720
.L717:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L720
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L720
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L181
.L720:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L723
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L724
.L723:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L725
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L724
.L725:
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L726
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L726
.L724:
	movss	xmm0, DWORD PTR s3_backoff[rip]
	movss	xmm1, DWORD PTR _x_s3_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L726
	ucomiss	xmm0, xmm1
	jne	.L726
	movss	xmm0, DWORD PTR _x_s3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L726
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L728
.L726:
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L728
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L728
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L728
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L728
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L728:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L730
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L730
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L730
	movss	xmm0, DWORD PTR s3_lambda[rip]
	movss	xmm1, DWORD PTR _x_s3_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L730
	ucomiss	xmm0, xmm1
	je	.L731
.L730:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L731
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L731
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L731
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L731
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L731
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L731
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L731:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	je	.L733
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L733
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L734
.L733:
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L734
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L734
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L734
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L734
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L734
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L734
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L734:
	movss	xmm0, DWORD PTR s3_lambda[rip]
	movss	xmm1, DWORD PTR _x_s3_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L735
	ucomiss	xmm0, xmm1
	jne	.L735
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	je	.L737
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L737
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L738
.L737:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L735
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L735
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L738
.L735:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L738
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L738
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L738
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L738
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L738
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L738:
	movss	xmm0, DWORD PTR s3_lambda[rip]
	movss	xmm1, DWORD PTR _x_s3_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L739
	ucomiss	xmm0, xmm1
	jne	.L739
	movss	xmm0, DWORD PTR _x_s3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L739
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L739
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L742
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L743
.L742:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L739
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L743
.L739:
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L743
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L743
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L743
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L743
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L743:
	movss	xmm1, DWORD PTR s3_lambda[rip]
	movss	xmm0, DWORD PTR s3_x[rip]
	comiss	xmm0, xmm1
	jb	.L744
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L744
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L744
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L744
	movss	xmm1, DWORD PTR _x_s3_backoff[rip]
	movss	xmm0, DWORD PTR s3_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L746
.L744:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L746
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L746
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L746
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L746
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L746
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L746
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L746:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L747
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L747
	movss	xmm0, DWORD PTR s3_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s3_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L748
.L747:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L748
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L748
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	je	.L748
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	jne	.L748
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L748
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L748
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L748:
	movss	xmm0, DWORD PTR s3_lambda[rip]
	movss	xmm1, DWORD PTR _x_s3_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L749
	ucomiss	xmm0, xmm1
	jne	.L749
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L751
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L752
.L751:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L749
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L749
.L752:
	movss	xmm0, DWORD PTR s3_backoff[rip]
	movss	xmm1, DWORD PTR _x_s3_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L749
	ucomiss	xmm0, xmm1
	jne	.L749
	movss	xmm0, DWORD PTR _x_s3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L749
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L754
.L749:
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L754
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L754
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L754
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L754
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L754:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L756
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L756
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L757
.L756:
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	je	.L757
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	jne	.L757
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L757
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L757
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L757
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L757
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L757:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	je	.L758
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L758
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L758
	movss	xmm1, DWORD PTR s3_backoff[rip]
	movss	xmm0, DWORD PTR s3_x[rip]
	comiss	xmm0, xmm1
	jnb	.L759
.L758:
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	test	al, al
	je	.L759
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	test	al, al
	jne	.L759
	movzx	eax, BYTE PTR s3_l0[rip]
	test	al, al
	je	.L759
	movzx	eax, BYTE PTR s3_l1[rip]
	test	al, al
	jne	.L759
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L759
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L759
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L181
.L759:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	jne	.L760
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	je	.L760
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L761
.L760:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	jne	.L762
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	jne	.L762
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L761
.L762:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	je	.L763
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	jne	.L763
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L761
.L763:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	jne	.L764
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	je	.L761
.L764:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	jne	.L181
.L761:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L765
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L766
.L765:
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L767
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L766
.L767:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L181
.L766:
	movss	xmm0, DWORD PTR _x_s2_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	movss	xmm0, DWORD PTR _x_s2_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L769
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L769
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L181
.L769:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L770
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L770
	ucomiss	xmm0, xmm1
	jne	.L770
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L770
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L770
	movss	xmm0, DWORD PTR s2_backoff[rip]
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L770
	ucomiss	xmm0, xmm1
	je	.L773
.L770:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L773
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L773
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L181
.L773:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L776
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L777
.L776:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L778
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L777
.L778:
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L779
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L779
.L777:
	movss	xmm0, DWORD PTR s2_backoff[rip]
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L779
	ucomiss	xmm0, xmm1
	jne	.L779
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L779
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L781
.L779:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L781
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L781
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L781
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L781
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L781:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L783
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L783
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L783
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L783
	ucomiss	xmm0, xmm1
	je	.L784
.L783:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L784
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L784
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L784
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L784
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L784
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L784
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L784:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L786
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L787
.L786:
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L787
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L787
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L787
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L787
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L787
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L787
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L787:
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L788
	ucomiss	xmm0, xmm1
	jne	.L788
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L790
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L790
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L791
.L790:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L788
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L788
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L791
.L788:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L791
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L791
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L791
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L791
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L791
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L791
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L791:
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L792
	ucomiss	xmm0, xmm1
	jne	.L792
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L792
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L792
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L795
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L796
.L795:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L792
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L796
.L792:
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L796
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L796
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L796
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L796
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L796:
	movss	xmm1, DWORD PTR s2_lambda[rip]
	movss	xmm0, DWORD PTR s2_x[rip]
	comiss	xmm0, xmm1
	jb	.L797
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L797
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L797
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L797
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	movss	xmm0, DWORD PTR s2_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L799
.L797:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L799
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L799
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L799
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L799
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L799
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L799
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L799:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L800
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L800
	movss	xmm0, DWORD PTR s2_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L801
.L800:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L801
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L801
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L801
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L801
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L801
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L801
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L801:
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L802
	ucomiss	xmm0, xmm1
	jne	.L802
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L804
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L805
.L804:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L802
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L802
.L805:
	movss	xmm0, DWORD PTR s2_backoff[rip]
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L802
	ucomiss	xmm0, xmm1
	jne	.L802
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L802
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L807
.L802:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L807
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L807
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L807
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L807
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L807:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L809
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L809
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L810
.L809:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L810
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L810
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L810
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L810
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L810
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L810
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L810:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L811
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L811
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L811
	movss	xmm1, DWORD PTR s2_backoff[rip]
	movss	xmm0, DWORD PTR s2_x[rip]
	comiss	xmm0, xmm1
	jnb	.L812
.L811:
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L812
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L812
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L812
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L812
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L812
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L812
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L181
.L812:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	jne	.L813
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	je	.L813
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L814
.L813:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	jne	.L815
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	jne	.L815
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L814
.L815:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	je	.L816
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	jne	.L816
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L814
.L816:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	jne	.L817
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L817
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	je	.L814
.L817:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	jne	.L181
.L814:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L818
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L819
.L818:
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L820
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L819
.L820:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L181
.L819:
	movss	xmm0, DWORD PTR _x_s1_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	movss	xmm0, DWORD PTR _x_s1_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L822
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L181
.L822:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L823
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L823
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L823
	ucomiss	xmm0, xmm1
	jne	.L823
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L823
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L823
	movss	xmm0, DWORD PTR s1_backoff[rip]
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L823
	ucomiss	xmm0, xmm1
	je	.L826
.L823:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L826
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L826
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L181
.L826:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L829
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L830
.L829:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L831
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L830
.L831:
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L832
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L832
.L830:
	movss	xmm0, DWORD PTR s1_backoff[rip]
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L832
	ucomiss	xmm0, xmm1
	jne	.L832
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L832
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L834
.L832:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L834
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L834
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L834
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L834
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L834:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L836
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L836
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L836
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L836
	ucomiss	xmm0, xmm1
	je	.L837
.L836:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L837
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L837
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L837
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L837
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L837
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L837
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L837:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L839
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L839
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L840
.L839:
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L840
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L840
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L840
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L840
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L840
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L840
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L840:
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L841
	ucomiss	xmm0, xmm1
	jne	.L841
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L843
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L843
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L844
.L843:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L841
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L841
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L844
.L841:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L844
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L844
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L844
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L844
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L844
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L844
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L844:
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L845
	ucomiss	xmm0, xmm1
	jne	.L845
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L845
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L845
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L848
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L849
.L848:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L845
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L849
.L845:
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L849
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L849
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L849
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L849
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L849:
	movss	xmm1, DWORD PTR s1_lambda[rip]
	movss	xmm0, DWORD PTR s1_x[rip]
	comiss	xmm0, xmm1
	jb	.L850
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L850
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L850
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L850
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	movss	xmm0, DWORD PTR s1_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L852
.L850:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L852
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L852
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L852
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L852
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L852:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L853
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L853
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L853
	movss	xmm0, DWORD PTR s1_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L854
.L853:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L854
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L854
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L854
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L854
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L854
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L854
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L854:
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L855
	ucomiss	xmm0, xmm1
	jne	.L855
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L857
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L858
.L857:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L855
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L855
.L858:
	movss	xmm0, DWORD PTR s1_backoff[rip]
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L855
	ucomiss	xmm0, xmm1
	jne	.L855
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L855
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L860
.L855:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L860
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L860
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L860
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L860
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L860:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L862
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L862
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L863
.L862:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L863
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L863
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L863
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L863
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L863
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L863
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L863:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L864
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L864
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L864
	movss	xmm1, DWORD PTR s1_backoff[rip]
	movss	xmm0, DWORD PTR s1_x[rip]
	comiss	xmm0, xmm1
	jnb	.L865
.L864:
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L865
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L865
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L865
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L865
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L865
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L865
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L181
.L865:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	jne	.L866
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	je	.L866
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L867
.L866:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	jne	.L868
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	jne	.L868
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L867
.L868:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	je	.L869
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	jne	.L869
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L867
.L869:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	jne	.L870
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L870
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	je	.L867
.L870:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	jne	.L181
.L867:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L871
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L872
.L871:
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L873
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L872
.L873:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L181
.L872:
	movss	xmm0, DWORD PTR _x_s0_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L181
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	movss	xmm0, DWORD PTR _x_s0_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L875
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L875
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L181
.L875:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L876
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L876
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L876
	ucomiss	xmm0, xmm1
	jne	.L876
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L876
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L876
	movss	xmm0, DWORD PTR s0_backoff[rip]
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L876
	ucomiss	xmm0, xmm1
	je	.L879
.L876:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L879
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L879
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L181
.L879:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L882
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L883
.L882:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L884
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L883
.L884:
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L885
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L885
.L883:
	movss	xmm0, DWORD PTR s0_backoff[rip]
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L885
	ucomiss	xmm0, xmm1
	jne	.L885
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L885
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L887
.L885:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L887
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L887
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L887
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L887
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L887:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L889
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L889
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L889
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L889
	ucomiss	xmm0, xmm1
	je	.L890
.L889:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L890
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L890
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L890
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L890
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L890
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L890
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L890:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L892
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L892
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L893
.L892:
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L893
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L893
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L893
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L893
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L893
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L893
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L893:
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L894
	ucomiss	xmm0, xmm1
	jne	.L894
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L896
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L896
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L897
.L896:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L894
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L894
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L897
.L894:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L897
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L897
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L897
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L897
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L897
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L897
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L897:
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L898
	ucomiss	xmm0, xmm1
	jne	.L898
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L898
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L898
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L901
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L902
.L901:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L898
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L902
.L898:
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L902
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L902
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L902
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L902
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L902:
	movss	xmm1, DWORD PTR s0_lambda[rip]
	movss	xmm0, DWORD PTR s0_x[rip]
	comiss	xmm0, xmm1
	jb	.L903
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L903
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L903
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L903
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	movss	xmm0, DWORD PTR s0_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L905
.L903:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L905
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L905
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L905
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L905
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L905:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L906
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L906
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L906
	movss	xmm0, DWORD PTR s0_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L907
.L906:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L907
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L907
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L907
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L907
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L907
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L907
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L907:
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L908
	ucomiss	xmm0, xmm1
	jne	.L908
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L910
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L911
.L910:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L908
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L908
.L911:
	movss	xmm0, DWORD PTR s0_backoff[rip]
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L908
	ucomiss	xmm0, xmm1
	jne	.L908
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L908
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L913
.L908:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L913
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L913
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L913
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L913
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L913:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L915
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L915
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L916
.L915:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L916
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L916
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L916
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L916
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L916
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L916
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L916:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L917
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L917
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L917
	movss	xmm1, DWORD PTR s0_backoff[rip]
	movss	xmm0, DWORD PTR s0_x[rip]
	comiss	xmm0, xmm1
	jnb	.L918
.L917:
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L918
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L918
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L918
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L918
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L918
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L918
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L181
.L918:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	jne	.L919
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	jne	.L919
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	je	.L920
.L919:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	jne	.L921
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	je	.L920
.L921:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	jne	.L922
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	je	.L922
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	je	.L920
.L922:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	je	.L923
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	je	.L923
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	je	.L920
.L923:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	jne	.L181
.L920:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L924
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L925
.L924:
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L926
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L925
.L926:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L927
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L925
.L927:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L181
.L925:
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L928
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L928
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L181
.L928:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1476
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L929
.L1476:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L929
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	jne	.L181
.L929:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L931
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR bus_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_bus_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L181
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L181
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L181
	mov	edx, DWORD PTR bus_j[rip]
	mov	eax, DWORD PTR _x_bus_j[rip]
	cmp	edx, eax
	jne	.L181
.L931:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR bus_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_bus_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L933
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L933
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L933
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L933
	mov	edx, DWORD PTR bus_j[rip]
	mov	eax, DWORD PTR _x_bus_j[rip]
	cmp	edx, eax
	je	.L935
.L933:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L935
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L935
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L181
.L935:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L936
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L936
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L936
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L936
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L936
	mov	edx, DWORD PTR bus_j[rip]
	mov	eax, DWORD PTR _x_bus_j[rip]
	cmp	edx, eax
	jne	.L936
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L936
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L937
.L936:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L937
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L937
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L937
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L937
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L181
.L937:
	mov	edx, DWORD PTR bus_j[rip]
	mov	eax, DWORD PTR _x_bus_j[rip]
	cmp	edx, eax
	jne	.L939
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L940
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L941
.L940:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L942
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L941
.L942:
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L939
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L941
.L939:
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L941
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L941
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L941
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L941
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L181
.L941:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L943
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L943
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L943
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L943
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L944
.L943:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L944
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L944
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L946
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L946
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L944
.L946:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L944
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	jne	.L944
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L944
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L181
.L944:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L947
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L947
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L947
	movss	xmm0, DWORD PTR bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L947
	movss	xmm0, DWORD PTR bus_x[rip]
	movss	xmm1, DWORD PTR _x_bus_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L947
	ucomiss	xmm0, xmm1
	je	.L949
.L947:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L949
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L949
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L951
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L951
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L949
.L951:
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L949
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L949
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L949
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L181
.L949:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L952
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L952
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L952
	movss	xmm0, DWORD PTR bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L952
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L952
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L953
.L952:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L953
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L953
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L955
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L955
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L953
.L955:
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L953
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L953
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L953
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L181
.L953:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L956
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L956
	movss	xmm0, DWORD PTR bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L956
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L956
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L956
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L956
	mov	edx, DWORD PTR bus_cd_id[rip]
	mov	eax, DWORD PTR bus_j[rip]
	cmp	edx, eax
	jne	.L956
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L956
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L956
	mov	eax, DWORD PTR bus_j[rip]
	mov	edx, DWORD PTR _x_bus_j[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L958
.L956:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L958
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L958
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L958
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L958
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L181
.L958:
	mov	eax, DWORD PTR bus_j[rip]
	mov	edx, DWORD PTR _x_bus_j[rip]
	sub	eax, edx
	cmp	eax, -1
	jne	.L959
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L959
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L959
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L959
	mov	edx, DWORD PTR bus_cd_id[rip]
	mov	eax, DWORD PTR bus_j[rip]
	cmp	edx, eax
	jne	.L959
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L959
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L959
	mov	eax, DWORD PTR bus_j[rip]
	cmp	eax, 12
	jle	.L961
.L959:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L961
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L961
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L962
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L962
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L961
.L962:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L961
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L961
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L961
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	jne	.L181
.L961:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L963
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L963
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L963
	mov	eax, DWORD PTR bus_j[rip]
	cmp	eax, 13
	jne	.L963
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L963
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L963
	mov	edx, DWORD PTR bus_cd_id[rip]
	mov	eax, DWORD PTR bus_j[rip]
	cmp	edx, eax
	jne	.L963
	mov	eax, DWORD PTR _x_bus_j[rip]
	test	eax, eax
	je	.L965
.L963:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L965
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L965
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L966
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L966
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L965
.L966:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L965
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	jne	.L965
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L965
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L181
.L965:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L181
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L968
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L968
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L969
.L968:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L970
.L969:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L971
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L971
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L972
.L971:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L970
.L972:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L973
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L973
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L974
.L973:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L970
.L974:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L975
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L975
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L976
.L975:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L970
.L976:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L978
.L977:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L970
.L978:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L979
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L979
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L980
.L979:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L970
.L980:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L981
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L981
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L982
.L981:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L970
.L982:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L983
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L983
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L984
.L983:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L970
.L984:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L985
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L985
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L986
.L985:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L986:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L987
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L987
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L988
.L987:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L988:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L989
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L989
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L990
.L989:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L990:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L991
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L991
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L992
.L991:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L992:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L993
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L993
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L994
.L993:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L994:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L995
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L995
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L996
.L995:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L970
.L996:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L997
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L997
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L998
.L997:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L970
.L998:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L999
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L999
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1000
.L999:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L970
.L1000:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1001
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1001
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1002
.L1001:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L970
.L1002:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1003
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1003
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1004
.L1003:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L970
.L1004:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1005
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1005
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1006
.L1005:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L970
.L1006:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1007
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1007
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1008
.L1007:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L970
.L1008:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1009
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1009
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1010
.L1009:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L1010:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1011
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1011
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1012
.L1011:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1012:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1013
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1013
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1014
.L1013:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1014:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1015
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1015
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1016
.L1015:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1016:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1017
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1017
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1018
.L1017:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1018:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1019
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1019
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1020
.L1019:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L970
.L1020:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1021
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1021
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1022
.L1021:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L970
.L1022:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1023
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1023
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1024
.L1023:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L970
.L1024:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1025
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1025
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1026
.L1025:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L970
.L1026:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1027
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1027
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1028
.L1027:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L970
.L1028:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1029
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1029
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1030
.L1029:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L970
.L1030:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1031
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1031
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1032
.L1031:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L1032:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1033
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1033
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1034
.L1033:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1034:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1035
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1035
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1036
.L1035:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1036:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1037
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1037
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1038
.L1037:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1038:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1039
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1039
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1040
.L1039:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1040:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1041
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1041
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1042
.L1041:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L970
.L1042:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1043
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1043
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1044
.L1043:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L970
.L1044:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1045
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1045
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1046
.L1045:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L970
.L1046:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1047
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1047
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1048
.L1047:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L970
.L1048:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1049
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1049
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1050
.L1049:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L970
.L1050:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1051
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1051
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1052
.L1051:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L1052:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1053
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1053
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1054
.L1053:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1054:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1055
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1055
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1056
.L1055:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1056:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1057
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1057
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1058
.L1057:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1058:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1059
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1059
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1060
.L1059:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1060:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1061
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1061
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1062
.L1061:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L970
.L1062:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1063
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1063
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1064
.L1063:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L970
.L1064:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1065
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1065
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1066
.L1065:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L970
.L1066:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1067
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1067
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1068
.L1067:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L970
.L1068:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1069
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1069
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1070
.L1069:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L1070:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1071
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1071
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1072
.L1071:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1072:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1073
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1073
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1074
.L1073:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1074:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1075
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1075
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1076
.L1075:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1076:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1077
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1077
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1078
.L1077:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1078:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1079
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1079
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1080
.L1079:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L970
.L1080:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1081
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1081
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1082
.L1081:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L970
.L1082:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1083
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1083
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1084
.L1083:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L970
.L1084:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1085
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1085
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1086
.L1085:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L1086:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1087
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1087
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1088
.L1087:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1088:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1089
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1089
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1090
.L1089:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1090:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1091
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1091
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1092
.L1091:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1092:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1093
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1093
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1094
.L1093:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1094:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1095
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1095
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1096
.L1095:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L970
.L1096:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1097
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1097
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1098
.L1097:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L970
.L1098:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1099
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1099
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1100
.L1099:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L1100:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1101
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1101
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1102
.L1101:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1102:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1103
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1103
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1104
.L1103:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1104:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1105
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1105
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1106
.L1105:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1106:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1107
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1107
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1108
.L1107:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1108:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1109
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1109
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1110
.L1109:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L970
.L1110:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1111
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1111
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1112
.L1111:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L1112:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1113
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1113
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1114
.L1113:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1114:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1115
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1115
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1116
.L1115:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1116:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1117
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1117
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1118
.L1117:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1118:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1119
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1119
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1120
.L1119:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1120:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1121
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1121
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1122
.L1121:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L970
.L1122:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1123
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1123
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1124
.L1123:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1124:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1125
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1125
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1126
.L1125:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1126:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1127
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1127
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1128
.L1127:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1128:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1129
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1129
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1130
.L1129:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1130:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L1131
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L1131
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1132
.L1131:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L970
.L1132:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L1133
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L1133
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1134
.L1133:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1134:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L1135
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L1135
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1136
.L1135:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1136:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L1137
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L1137
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1138
.L1137:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1138:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L1139
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L1139
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1140
.L1139:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L970
.L1140:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L1141
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L1141
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1142
.L1141:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1142:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L1143
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L1143
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1144
.L1143:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1144:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L1145
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L1145
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L1146
.L1145:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L970
.L1146:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L1147
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L1147
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L1148
.L1147:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L970
.L1148:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L1149
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L1149
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L1150
.L1149:
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L970
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L1150
.L970:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1150
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L181
.L1150:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1152
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1152
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L181
.L1152:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1153
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1153
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L1154
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L1154
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1154
	mov	eax, 1
	jmp	.L1155
.L1154:
	mov	eax, 0
.L1155:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	je	.L1156
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	jne	.L1156
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L1157
.L1156:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	je	.L1158
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	jne	.L1158
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L1157
.L1158:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	je	.L1159
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	jne	.L1159
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L1157
.L1159:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	je	.L1160
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	jne	.L1160
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1157
.L1160:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	je	.L1161
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	jne	.L1161
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1157
.L1161:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	je	.L1162
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	jne	.L1162
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1157
.L1162:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	je	.L1163
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	jne	.L1163
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1157
.L1163:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	je	.L1164
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	jne	.L1164
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1157
.L1164:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	je	.L1165
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	jne	.L1165
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1157
.L1165:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	je	.L1166
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	jne	.L1166
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1157
.L1166:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	je	.L1167
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	jne	.L1167
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1157
.L1167:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L1168
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L1168
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1157
.L1168:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L1169
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L1169
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1157
.L1169:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L1170
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1170
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L1170
.L1157:
	mov	eax, 1
	jmp	.L1171
.L1170:
	mov	eax, 0
.L1171:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1172
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L1172
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L1172
	mov	eax, 1
	jmp	.L1173
.L1172:
	mov	eax, 0
.L1173:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L1174
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L1174
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L1175
.L1174:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L1176
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L1176
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L1175
.L1176:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L1177
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L1177
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L1175
.L1177:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L1178
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1178
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L1175
.L1178:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L1179
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1179
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L1175
.L1179:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1180
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1180
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L1175
.L1180:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1181
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1181
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L1175
.L1181:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1182
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1182
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L1175
.L1182:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1183
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1183
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L1175
.L1183:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1184
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1184
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L1175
.L1184:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1185
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1185
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L1175
.L1185:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1186
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1186
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1175
.L1186:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L1187
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1187
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1175
.L1187:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1188
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1188
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1188
.L1175:
	mov	eax, 1
	jmp	.L1189
.L1188:
	mov	eax, 0
.L1189:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L1190
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L1190
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L1190
	mov	eax, 1
	jmp	.L1191
.L1190:
	mov	eax, 0
.L1191:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	je	.L1192
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L1192
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L1193
.L1192:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	je	.L1194
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L1194
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L1193
.L1194:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	je	.L1195
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L1195
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L1193
.L1195:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	je	.L1196
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1196
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L1193
.L1196:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	je	.L1197
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1197
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L1193
.L1197:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	je	.L1198
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1198
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L1193
.L1198:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	je	.L1199
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1199
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L1193
.L1199:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	je	.L1200
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1200
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L1193
.L1200:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	je	.L1201
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1201
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L1193
.L1201:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	je	.L1202
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1202
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L1193
.L1202:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	je	.L1203
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1203
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L1193
.L1203:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L1204
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1204
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1193
.L1204:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L1205
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1205
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1193
.L1205:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L1206
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L1206
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L1206
.L1193:
	mov	eax, 1
	jmp	.L1207
.L1206:
	mov	eax, 0
.L1207:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1208
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1208
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1208
	mov	eax, 1
	jmp	.L1209
.L1208:
	mov	eax, 0
.L1209:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L1210
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L1210
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	je	.L1211
.L1210:
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L1212
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L1212
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	je	.L1211
.L1212:
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L1213
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L1213
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	je	.L1211
.L1213:
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L1214
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L1214
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	je	.L1211
.L1214:
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L1215
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L1215
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	je	.L1211
.L1215:
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1216
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L1216
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	je	.L1211
.L1216:
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1217
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L1217
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	je	.L1211
.L1217:
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1218
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L1218
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	je	.L1211
.L1218:
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1219
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L1219
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	je	.L1211
.L1219:
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1220
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L1220
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	je	.L1211
.L1220:
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1221
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L1221
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	je	.L1211
.L1221:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1222
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1222
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L1211
.L1222:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L1223
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1223
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L1211
.L1223:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1224
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L1224
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L1224
.L1211:
	mov	eax, 1
	jmp	.L1225
.L1224:
	mov	eax, 0
.L1225:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
.L1153:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1226
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L1226
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L1227
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L1227
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L1227
	mov	eax, 1
	jmp	.L1228
.L1227:
	mov	eax, 0
.L1228:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1229
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1229
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1229
	mov	eax, DWORD PTR bus_cd_id[rip]
	test	eax, eax
	jne	.L1229
	mov	eax, 1
	jmp	.L1230
.L1229:
	mov	eax, 0
.L1230:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L1231
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L1231
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L1231
	mov	eax, 1
	jmp	.L1232
.L1231:
	mov	eax, 0
.L1232:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1233
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1233
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1233
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 1
	jne	.L1233
	mov	eax, 1
	jmp	.L1234
.L1233:
	mov	eax, 0
.L1234:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L1235
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L1235
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L1235
	mov	eax, 1
	jmp	.L1236
.L1235:
	mov	eax, 0
.L1236:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1237
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1237
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1237
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 2
	jne	.L1237
	mov	eax, 1
	jmp	.L1238
.L1237:
	mov	eax, 0
.L1238:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s3_evt2[rip]
	test	al, al
	jne	.L1239
	movzx	eax, BYTE PTR s3_evt0[rip]
	test	al, al
	je	.L1239
	movzx	eax, BYTE PTR s3_evt1[rip]
	test	al, al
	jne	.L1239
	mov	eax, 1
	jmp	.L1240
.L1239:
	mov	eax, 0
.L1240:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1241
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1241
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1241
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 3
	jne	.L1241
	mov	eax, 1
	jmp	.L1242
.L1241:
	mov	eax, 0
.L1242:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s4_evt2[rip]
	test	al, al
	jne	.L1243
	movzx	eax, BYTE PTR s4_evt0[rip]
	test	al, al
	je	.L1243
	movzx	eax, BYTE PTR s4_evt1[rip]
	test	al, al
	jne	.L1243
	mov	eax, 1
	jmp	.L1244
.L1243:
	mov	eax, 0
.L1244:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1245
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1245
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1245
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 4
	jne	.L1245
	mov	eax, 1
	jmp	.L1246
.L1245:
	mov	eax, 0
.L1246:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s5_evt2[rip]
	test	al, al
	jne	.L1247
	movzx	eax, BYTE PTR s5_evt0[rip]
	test	al, al
	je	.L1247
	movzx	eax, BYTE PTR s5_evt1[rip]
	test	al, al
	jne	.L1247
	mov	eax, 1
	jmp	.L1248
.L1247:
	mov	eax, 0
.L1248:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1249
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1249
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1249
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 5
	jne	.L1249
	mov	eax, 1
	jmp	.L1250
.L1249:
	mov	eax, 0
.L1250:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s6_evt2[rip]
	test	al, al
	jne	.L1251
	movzx	eax, BYTE PTR s6_evt0[rip]
	test	al, al
	je	.L1251
	movzx	eax, BYTE PTR s6_evt1[rip]
	test	al, al
	jne	.L1251
	mov	eax, 1
	jmp	.L1252
.L1251:
	mov	eax, 0
.L1252:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1253
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1253
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1253
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 6
	jne	.L1253
	mov	eax, 1
	jmp	.L1254
.L1253:
	mov	eax, 0
.L1254:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s7_evt2[rip]
	test	al, al
	jne	.L1255
	movzx	eax, BYTE PTR s7_evt0[rip]
	test	al, al
	je	.L1255
	movzx	eax, BYTE PTR s7_evt1[rip]
	test	al, al
	jne	.L1255
	mov	eax, 1
	jmp	.L1256
.L1255:
	mov	eax, 0
.L1256:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1257
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1257
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1257
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 7
	jne	.L1257
	mov	eax, 1
	jmp	.L1258
.L1257:
	mov	eax, 0
.L1258:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s8_evt2[rip]
	test	al, al
	jne	.L1259
	movzx	eax, BYTE PTR s8_evt0[rip]
	test	al, al
	je	.L1259
	movzx	eax, BYTE PTR s8_evt1[rip]
	test	al, al
	jne	.L1259
	mov	eax, 1
	jmp	.L1260
.L1259:
	mov	eax, 0
.L1260:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1261
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1261
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1261
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 8
	jne	.L1261
	mov	eax, 1
	jmp	.L1262
.L1261:
	mov	eax, 0
.L1262:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s9_evt2[rip]
	test	al, al
	jne	.L1263
	movzx	eax, BYTE PTR s9_evt0[rip]
	test	al, al
	je	.L1263
	movzx	eax, BYTE PTR s9_evt1[rip]
	test	al, al
	jne	.L1263
	mov	eax, 1
	jmp	.L1264
.L1263:
	mov	eax, 0
.L1264:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1265
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1265
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1265
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 9
	jne	.L1265
	mov	eax, 1
	jmp	.L1266
.L1265:
	mov	eax, 0
.L1266:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s10_evt2[rip]
	test	al, al
	jne	.L1267
	movzx	eax, BYTE PTR s10_evt0[rip]
	test	al, al
	je	.L1267
	movzx	eax, BYTE PTR s10_evt1[rip]
	test	al, al
	jne	.L1267
	mov	eax, 1
	jmp	.L1268
.L1267:
	mov	eax, 0
.L1268:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1269
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1269
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1269
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 10
	jne	.L1269
	mov	eax, 1
	jmp	.L1270
.L1269:
	mov	eax, 0
.L1270:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s11_evt2[rip]
	test	al, al
	jne	.L1271
	movzx	eax, BYTE PTR s11_evt0[rip]
	test	al, al
	je	.L1271
	movzx	eax, BYTE PTR s11_evt1[rip]
	test	al, al
	jne	.L1271
	mov	eax, 1
	jmp	.L1272
.L1271:
	mov	eax, 0
.L1272:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1273
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1273
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1273
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 11
	jne	.L1273
	mov	eax, 1
	jmp	.L1274
.L1273:
	mov	eax, 0
.L1274:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s12_evt2[rip]
	test	al, al
	jne	.L1275
	movzx	eax, BYTE PTR s12_evt0[rip]
	test	al, al
	je	.L1275
	movzx	eax, BYTE PTR s12_evt1[rip]
	test	al, al
	jne	.L1275
	mov	eax, 1
	jmp	.L1276
.L1275:
	mov	eax, 0
.L1276:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1277
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1277
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1277
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 12
	jne	.L1277
	mov	eax, 1
	jmp	.L1278
.L1277:
	mov	eax, 0
.L1278:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR s13_evt2[rip]
	test	al, al
	jne	.L1279
	movzx	eax, BYTE PTR s13_evt0[rip]
	test	al, al
	je	.L1279
	movzx	eax, BYTE PTR s13_evt1[rip]
	test	al, al
	jne	.L1279
	mov	eax, 1
	jmp	.L1280
.L1279:
	mov	eax, 0
.L1280:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L1281
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L1281
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L1281
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 13
	jne	.L1281
	mov	eax, 1
	jmp	.L1282
.L1281:
	mov	eax, 0
.L1282:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L181
.L1226:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L1484
	ucomiss	xmm0, xmm1
	je	.L1283
.L1484:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L181
.L1283:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jnb	.L1285
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L181
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L181
.L1285:
	mov	eax, 1
	jmp	.L1287
.L181:
	mov	eax, 0
.L1287:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_s13_l0[rip]
	mov	BYTE PTR s13_l0[rip], al
	movzx	eax, BYTE PTR _x_s13_evt2[rip]
	mov	BYTE PTR s13_evt2[rip], al
	movzx	eax, BYTE PTR _x_s13_evt1[rip]
	mov	BYTE PTR s13_evt1[rip], al
	movzx	eax, BYTE PTR _x_s13_evt0[rip]
	mov	BYTE PTR s13_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s13_backoff[rip]
	movss	DWORD PTR s13_backoff[rip], xmm0
	movzx	eax, BYTE PTR _x_s12_l0[rip]
	mov	BYTE PTR s12_l0[rip], al
	movzx	eax, BYTE PTR _x_s12_evt2[rip]
	mov	BYTE PTR s12_evt2[rip], al
	movzx	eax, BYTE PTR _x_s12_evt1[rip]
	mov	BYTE PTR s12_evt1[rip], al
	movzx	eax, BYTE PTR _x_s12_evt0[rip]
	mov	BYTE PTR s12_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s12_backoff[rip]
	movss	DWORD PTR s12_backoff[rip], xmm0
	movzx	eax, BYTE PTR _x_s11_l0[rip]
	mov	BYTE PTR s11_l0[rip], al
	movzx	eax, BYTE PTR _x_s11_evt2[rip]
	mov	BYTE PTR s11_evt2[rip], al
	movzx	eax, BYTE PTR _x_s11_evt1[rip]
	mov	BYTE PTR s11_evt1[rip], al
	movzx	eax, BYTE PTR _x_s11_evt0[rip]
	mov	BYTE PTR s11_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s11_lambda[rip]
	movss	DWORD PTR s11_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s11_backoff[rip]
	movss	DWORD PTR s11_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s11_x[rip]
	movss	DWORD PTR s11_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s10_l0[rip]
	mov	BYTE PTR s10_l0[rip], al
	movzx	eax, BYTE PTR _x_s10_evt2[rip]
	mov	BYTE PTR s10_evt2[rip], al
	movzx	eax, BYTE PTR _x_s10_evt1[rip]
	mov	BYTE PTR s10_evt1[rip], al
	movzx	eax, BYTE PTR _x_s10_evt0[rip]
	mov	BYTE PTR s10_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s10_lambda[rip]
	movss	DWORD PTR s10_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s10_backoff[rip]
	movss	DWORD PTR s10_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s10_x[rip]
	movss	DWORD PTR s10_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s9_l0[rip]
	mov	BYTE PTR s9_l0[rip], al
	movzx	eax, BYTE PTR _x_s9_evt2[rip]
	mov	BYTE PTR s9_evt2[rip], al
	movzx	eax, BYTE PTR _x_s9_evt1[rip]
	mov	BYTE PTR s9_evt1[rip], al
	movzx	eax, BYTE PTR _x_s9_evt0[rip]
	mov	BYTE PTR s9_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s9_lambda[rip]
	movss	DWORD PTR s9_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s9_backoff[rip]
	movss	DWORD PTR s9_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s9_x[rip]
	movss	DWORD PTR s9_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s8_l1[rip]
	mov	BYTE PTR s8_l1[rip], al
	movzx	eax, BYTE PTR _x_s8_l0[rip]
	mov	BYTE PTR s8_l0[rip], al
	movzx	eax, BYTE PTR _x_s8_evt2[rip]
	mov	BYTE PTR s8_evt2[rip], al
	movzx	eax, BYTE PTR _x_s8_evt1[rip]
	mov	BYTE PTR s8_evt1[rip], al
	movzx	eax, BYTE PTR _x_s8_evt0[rip]
	mov	BYTE PTR s8_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s8_lambda[rip]
	movss	DWORD PTR s8_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s8_backoff[rip]
	movss	DWORD PTR s8_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s8_x[rip]
	movss	DWORD PTR s8_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s7_l1[rip]
	mov	BYTE PTR s7_l1[rip], al
	movzx	eax, BYTE PTR _x_s7_l0[rip]
	mov	BYTE PTR s7_l0[rip], al
	movzx	eax, BYTE PTR _x_s7_evt2[rip]
	mov	BYTE PTR s7_evt2[rip], al
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_s7_evt1[rip]
	mov	BYTE PTR s7_evt1[rip], al
	movzx	eax, BYTE PTR _x_s7_evt0[rip]
	mov	BYTE PTR s7_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s7_lambda[rip]
	movss	DWORD PTR s7_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s7_backoff[rip]
	movss	DWORD PTR s7_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s7_x[rip]
	movss	DWORD PTR s7_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s6_l1[rip]
	mov	BYTE PTR s6_l1[rip], al
	movzx	eax, BYTE PTR _x_s6_l0[rip]
	mov	BYTE PTR s6_l0[rip], al
	movzx	eax, BYTE PTR _x_s6_evt2[rip]
	mov	BYTE PTR s6_evt2[rip], al
	movzx	eax, BYTE PTR _x_s6_evt1[rip]
	mov	BYTE PTR s6_evt1[rip], al
	movzx	eax, BYTE PTR _x_s6_evt0[rip]
	mov	BYTE PTR s6_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s6_lambda[rip]
	movss	DWORD PTR s6_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	movss	DWORD PTR s2_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	mov	BYTE PTR s1_l1[rip], al
	movzx	eax, BYTE PTR _x_s4_evt2[rip]
	mov	BYTE PTR s4_evt2[rip], al
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	mov	BYTE PTR s1_l0[rip], al
	movzx	eax, BYTE PTR _x_s4_evt1[rip]
	mov	BYTE PTR s4_evt1[rip], al
	movss	xmm0, DWORD PTR _x_s13_lambda[rip]
	movss	DWORD PTR s13_lambda[rip], xmm0
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	mov	BYTE PTR s1_evt2[rip], al
	movss	xmm0, DWORD PTR _x_s13_x[rip]
	movss	DWORD PTR s13_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	mov	BYTE PTR s1_evt1[rip], al
	movss	xmm0, DWORD PTR _x_s1_backoff[rip]
	movss	DWORD PTR s1_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s6_x[rip]
	movss	DWORD PTR s6_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s2_backoff[rip]
	movss	DWORD PTR s2_backoff[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	mov	BYTE PTR s0_l1[rip], al
	movzx	eax, BYTE PTR _x_s3_evt2[rip]
	mov	BYTE PTR s3_evt2[rip], al
	movss	xmm0, DWORD PTR _x_s2_lambda[rip]
	movss	DWORD PTR s2_lambda[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	mov	BYTE PTR s0_l0[rip], al
	movzx	eax, BYTE PTR _x_s3_evt1[rip]
	mov	BYTE PTR s3_evt1[rip], al
	movss	xmm0, DWORD PTR _x_s12_lambda[rip]
	movss	DWORD PTR s12_lambda[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	mov	BYTE PTR s0_evt2[rip], al
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	mov	BYTE PTR bus_evt0[rip], al
	movzx	eax, BYTE PTR _x_s5_evt0[rip]
	mov	BYTE PTR s5_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s12_x[rip]
	movss	DWORD PTR s12_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	mov	BYTE PTR s0_evt1[rip], al
	movss	xmm0, DWORD PTR _x_s4_backoff[rip]
	movss	DWORD PTR s4_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	movss	DWORD PTR s1_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s5_backoff[rip]
	movss	DWORD PTR s5_backoff[rip], xmm0
	mov	eax, DWORD PTR _x_bus_j[rip]
	mov	DWORD PTR bus_j[rip], eax
	movzx	eax, BYTE PTR _x_s11_l1[rip]
	mov	BYTE PTR s11_l1[rip], al
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	mov	BYTE PTR s2_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	movss	DWORD PTR s0_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s1_lambda[rip]
	movss	DWORD PTR s1_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	movss	DWORD PTR bus_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	mov	BYTE PTR s2_evt1[rip], al
	movss	xmm0, DWORD PTR _x_s6_backoff[rip]
	movss	DWORD PTR s6_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_s10_l1[rip]
	mov	BYTE PTR s10_l1[rip], al
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	mov	BYTE PTR s1_evt0[rip], al
	mov	eax, DWORD PTR _x_bus_cd_id[rip]
	mov	DWORD PTR bus_cd_id[rip], eax
	movss	xmm0, DWORD PTR _x_s5_lambda[rip]
	movss	DWORD PTR s5_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s0_lambda[rip]
	movss	DWORD PTR s0_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s0_backoff[rip]
	movss	DWORD PTR s0_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s5_x[rip]
	movss	DWORD PTR s5_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s3_l0[rip]
	mov	BYTE PTR s3_l0[rip], al
	movzx	eax, BYTE PTR _x_s9_l1[rip]
	mov	BYTE PTR s9_l1[rip], al
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	mov	BYTE PTR s0_evt0[rip], al
	movss	xmm0, DWORD PTR _x_s4_lambda[rip]
	movss	DWORD PTR s4_lambda[rip], xmm0
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	mov	BYTE PTR s2_evt2[rip], al
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	mov	BYTE PTR s2_l0[rip], al
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	mov	BYTE PTR bus_evt1[rip], al
	movzx	eax, BYTE PTR _x_s5_evt1[rip]
	mov	BYTE PTR s5_evt1[rip], al
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	mov	BYTE PTR s2_l1[rip], al
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	mov	BYTE PTR bus_evt2[rip], al
	movzx	eax, BYTE PTR _x_s5_evt2[rip]
	mov	BYTE PTR s5_evt2[rip], al
	movss	xmm0, DWORD PTR _x_s3_x[rip]
	movss	DWORD PTR s3_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s3_backoff[rip]
	movss	DWORD PTR s3_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s3_lambda[rip]
	movss	DWORD PTR s3_lambda[rip], xmm0
	movzx	eax, BYTE PTR _x_s12_l1[rip]
	mov	BYTE PTR s12_l1[rip], al
	movzx	eax, BYTE PTR _x_s3_evt0[rip]
	mov	BYTE PTR s3_evt0[rip], al
	movzx	eax, BYTE PTR _x_s3_l1[rip]
	mov	BYTE PTR s3_l1[rip], al
	movss	xmm0, DWORD PTR _x_s4_x[rip]
	movss	DWORD PTR s4_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s13_l1[rip]
	mov	BYTE PTR s13_l1[rip], al
	movzx	eax, BYTE PTR _x_s4_evt0[rip]
	mov	BYTE PTR s4_evt0[rip], al
	movzx	eax, BYTE PTR _x_s4_l0[rip]
	mov	BYTE PTR s4_l0[rip], al
	movzx	eax, BYTE PTR _x_s4_l1[rip]
	mov	BYTE PTR s4_l1[rip], al
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	mov	BYTE PTR bus_l0[rip], al
	movzx	eax, BYTE PTR _x_s5_l0[rip]
	mov	BYTE PTR s5_l0[rip], al
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	mov	BYTE PTR bus_l1[rip], al
	movzx	eax, BYTE PTR _x_s5_l1[rip]
	mov	BYTE PTR s5_l1[rip], al
.L175:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L1288
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1095761920
	.align 8
.LC3:
	.long	0
	.long	-1074790400
	.align 4
.LC4:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"124678.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	s13_l0,1,1
	.comm	_x_s13_l0,1,1
	.comm	s13_evt2,1,1
	.comm	_x_s13_evt2,1,1
	.comm	s13_evt1,1,1
	.comm	_x_s13_evt1,1,1
	.comm	s13_evt0,1,1
	.comm	_x_s13_evt0,1,1
	.comm	s13_backoff,4,4
	.comm	_x_s13_backoff,4,4
	.comm	s12_l0,1,1
	.comm	_x_s12_l0,1,1
	.comm	s12_evt2,1,1
	.comm	_x_s12_evt2,1,1
	.comm	s12_evt1,1,1
	.comm	_x_s12_evt1,1,1
	.comm	s12_evt0,1,1
	.comm	_x_s12_evt0,1,1
	.comm	s12_backoff,4,4
	.comm	_x_s12_backoff,4,4
	.comm	s11_l0,1,1
	.comm	_x_s11_l0,1,1
	.comm	s11_evt2,1,1
	.comm	_x_s11_evt2,1,1
	.comm	s11_evt1,1,1
	.comm	_x_s11_evt1,1,1
	.comm	s11_evt0,1,1
	.comm	_x_s11_evt0,1,1
	.comm	s11_lambda,4,4
	.comm	_x_s11_lambda,4,4
	.comm	s11_backoff,4,4
	.comm	_x_s11_backoff,4,4
	.comm	s11_x,4,4
	.comm	_x_s11_x,4,4
	.comm	s10_l0,1,1
	.comm	_x_s10_l0,1,1
	.comm	s10_evt2,1,1
	.comm	_x_s10_evt2,1,1
	.comm	s10_evt1,1,1
	.comm	_x_s10_evt1,1,1
	.comm	s10_evt0,1,1
	.comm	_x_s10_evt0,1,1
	.comm	s10_lambda,4,4
	.comm	_x_s10_lambda,4,4
	.comm	s10_backoff,4,4
	.comm	_x_s10_backoff,4,4
	.comm	s10_x,4,4
	.comm	_x_s10_x,4,4
	.comm	s9_l0,1,1
	.comm	_x_s9_l0,1,1
	.comm	s9_evt2,1,1
	.comm	_x_s9_evt2,1,1
	.comm	s9_evt1,1,1
	.comm	_x_s9_evt1,1,1
	.comm	s9_evt0,1,1
	.comm	_x_s9_evt0,1,1
	.comm	s9_lambda,4,4
	.comm	_x_s9_lambda,4,4
	.comm	s9_backoff,4,4
	.comm	_x_s9_backoff,4,4
	.comm	s9_x,4,4
	.comm	_x_s9_x,4,4
	.comm	s8_l1,1,1
	.comm	_x_s8_l1,1,1
	.comm	s8_l0,1,1
	.comm	_x_s8_l0,1,1
	.comm	s8_evt2,1,1
	.comm	_x_s8_evt2,1,1
	.comm	s8_evt1,1,1
	.comm	_x_s8_evt1,1,1
	.comm	s8_evt0,1,1
	.comm	_x_s8_evt0,1,1
	.comm	s8_lambda,4,4
	.comm	_x_s8_lambda,4,4
	.comm	s8_backoff,4,4
	.comm	_x_s8_backoff,4,4
	.comm	s8_x,4,4
	.comm	_x_s8_x,4,4
	.comm	s7_l1,1,1
	.comm	_x_s7_l1,1,1
	.comm	s7_l0,1,1
	.comm	_x_s7_l0,1,1
	.comm	s7_evt2,1,1
	.comm	_x_s7_evt2,1,1
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	s7_evt1,1,1
	.comm	_x_s7_evt1,1,1
	.comm	s7_evt0,1,1
	.comm	_x_s7_evt0,1,1
	.comm	s7_lambda,4,4
	.comm	_x_s7_lambda,4,4
	.comm	s7_backoff,4,4
	.comm	_x_s7_backoff,4,4
	.comm	s7_x,4,4
	.comm	_x_s7_x,4,4
	.comm	s6_l1,1,1
	.comm	_x_s6_l1,1,1
	.comm	s6_l0,1,1
	.comm	_x_s6_l0,1,1
	.comm	s6_evt2,1,1
	.comm	_x_s6_evt2,1,1
	.comm	s6_evt1,1,1
	.comm	_x_s6_evt1,1,1
	.comm	s6_evt0,1,1
	.comm	_x_s6_evt0,1,1
	.comm	s6_lambda,4,4
	.comm	_x_s6_lambda,4,4
	.comm	s2_x,4,4
	.comm	_x_s2_x,4,4
	.comm	s1_l1,1,1
	.comm	_x_s1_l1,1,1
	.comm	s4_evt2,1,1
	.comm	_x_s4_evt2,1,1
	.comm	s1_l0,1,1
	.comm	_x_s1_l0,1,1
	.comm	s4_evt1,1,1
	.comm	_x_s4_evt1,1,1
	.comm	s13_lambda,4,4
	.comm	_x_s13_lambda,4,4
	.comm	s1_evt2,1,1
	.comm	_x_s1_evt2,1,1
	.comm	s13_x,4,4
	.comm	_x_s13_x,4,4
	.comm	s1_evt1,1,1
	.comm	_x_s1_evt1,1,1
	.comm	s1_backoff,4,4
	.comm	_x_s1_backoff,4,4
	.comm	s6_x,4,4
	.comm	_x_s6_x,4,4
	.comm	s2_backoff,4,4
	.comm	_x_s2_backoff,4,4
	.comm	s0_l1,1,1
	.comm	_x_s0_l1,1,1
	.comm	s3_evt2,1,1
	.comm	_x_s3_evt2,1,1
	.comm	s2_lambda,4,4
	.comm	_x_s2_lambda,4,4
	.comm	s0_l0,1,1
	.comm	_x_s0_l0,1,1
	.comm	s3_evt1,1,1
	.comm	_x_s3_evt1,1,1
	.comm	s12_lambda,4,4
	.comm	_x_s12_lambda,4,4
	.comm	s0_evt2,1,1
	.comm	_x_s0_evt2,1,1
	.comm	bus_evt0,1,1
	.comm	_x_bus_evt0,1,1
	.comm	s5_evt0,1,1
	.comm	_x_s5_evt0,1,1
	.comm	s12_x,4,4
	.comm	_x_s12_x,4,4
	.comm	s0_evt1,1,1
	.comm	_x_s0_evt1,1,1
	.comm	s4_backoff,4,4
	.comm	_x_s4_backoff,4,4
	.comm	s1_x,4,4
	.comm	_x_s1_x,4,4
	.comm	s5_backoff,4,4
	.comm	_x_s5_backoff,4,4
	.comm	bus_j,4,4
	.comm	_x_bus_j,4,4
	.comm	s11_l1,1,1
	.comm	_x_s11_l1,1,1
	.comm	s2_evt0,1,1
	.comm	_x_s2_evt0,1,1
	.comm	s0_x,4,4
	.comm	_x_s0_x,4,4
	.comm	s1_lambda,4,4
	.comm	_x_s1_lambda,4,4
	.comm	bus_x,4,4
	.comm	_x_bus_x,4,4
	.comm	s2_evt1,1,1
	.comm	_x_s2_evt1,1,1
	.comm	s6_backoff,4,4
	.comm	_x_s6_backoff,4,4
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	s10_l1,1,1
	.comm	_x_s10_l1,1,1
	.comm	s1_evt0,1,1
	.comm	_x_s1_evt0,1,1
	.comm	bus_cd_id,4,4
	.comm	_x_bus_cd_id,4,4
	.comm	s5_lambda,4,4
	.comm	_x_s5_lambda,4,4
	.comm	s0_lambda,4,4
	.comm	_x_s0_lambda,4,4
	.comm	s0_backoff,4,4
	.comm	_x_s0_backoff,4,4
	.comm	s5_x,4,4
	.comm	_x_s5_x,4,4
	.comm	s3_l0,1,1
	.comm	_x_s3_l0,1,1
	.comm	s9_l1,1,1
	.comm	_x_s9_l1,1,1
	.comm	s0_evt0,1,1
	.comm	_x_s0_evt0,1,1
	.comm	s4_lambda,4,4
	.comm	_x_s4_lambda,4,4
	.comm	s2_evt2,1,1
	.comm	_x_s2_evt2,1,1
	.comm	s2_l0,1,1
	.comm	_x_s2_l0,1,1
	.comm	bus_evt1,1,1
	.comm	_x_bus_evt1,1,1
	.comm	s5_evt1,1,1
	.comm	_x_s5_evt1,1,1
	.comm	s2_l1,1,1
	.comm	_x_s2_l1,1,1
	.comm	bus_evt2,1,1
	.comm	_x_bus_evt2,1,1
	.comm	s5_evt2,1,1
	.comm	_x_s5_evt2,1,1
	.comm	s3_x,4,4
	.comm	_x_s3_x,4,4
	.comm	s3_backoff,4,4
	.comm	_x_s3_backoff,4,4
	.comm	s3_lambda,4,4
	.comm	_x_s3_lambda,4,4
	.comm	s12_l1,1,1
	.comm	_x_s12_l1,1,1
	.comm	s3_evt0,1,1
	.comm	_x_s3_evt0,1,1
	.comm	s3_l1,1,1
	.comm	_x_s3_l1,1,1
	.comm	s4_x,4,4
	.comm	_x_s4_x,4,4
	.comm	s13_l1,1,1
	.comm	_x_s13_l1,1,1
	.comm	s4_evt0,1,1
	.comm	_x_s4_evt0,1,1
	.comm	s4_l0,1,1
	.comm	_x_s4_l0,1,1
	.comm	s4_l1,1,1
	.comm	_x_s4_l1,1,1
	.comm	bus_l0,1,1
	.comm	_x_bus_l0,1,1
	.comm	s5_l0,1,1
	.comm	_x_s5_l0,1,1
	.comm	bus_l1,1,1
	.comm	_x_bus_l1,1,1
	.comm	s5_l1,1,1
	.comm	_x_s5_l1,1,1
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmpge
	.global	__aeabi_fcmple
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.global	__aeabi_dcmple
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+16
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+56
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+60
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+64
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+84
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+88
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+92
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+112
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+332
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+336
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+376
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+380
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+356
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+360
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+372
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+364
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+368
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+408
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+412
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+384
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+116
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+388
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+404
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+396
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+400
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+440
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+444
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+416
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+420
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+424
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+436
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+120
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+480
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+484
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+132
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+140
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+148
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+432
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+152
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+536
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+160
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+532
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+168
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+456
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+180
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+492
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+188
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+460
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L1452+192
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+204
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+208
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+212
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+428
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+220
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L1452+228
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+468
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+232
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+236
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+464
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+516
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+504
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+452
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+260
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+448
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+524
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+264
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+268
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+528
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+520
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1452+500
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+488
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+512
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+508
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+280
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+476
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1452+472
	strb	r2, [r3]
	ldr	r3, .L1452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L1452+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
	ldr	r3, .L1452+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L1452+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1452+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L1452+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L1452+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L1452+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L9
	ldr	r3, .L1452+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L1452+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L1452+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
	ldr	r3, .L1452+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L10:
	ldr	r3, .L1452+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L7:
	ldr	r3, .L1452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L11
	ldr	r3, .L1452+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
.L11:
	ldr	r3, .L1452+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L1452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
.L13:
	ldr	r3, .L1452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L12:
	ldr	r3, .L1452+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+132
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L15
	mov	r3, #0
	mov	r4, r3
.L15:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L1452+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L1452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L16:
	ldr	r3, .L1452+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L1452+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
	ldr	r3, .L1452+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L18:
	ldr	r3, .L1452+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L1452+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L1452+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L20:
	ldr	r3, .L1452+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L1452+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L21
	ldr	r3, .L1452+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L21:
	ldr	r3, .L1452+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L1452+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L1452+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L22:
	ldr	r3, .L1452+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L19:
	ldr	r3, .L1452+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L23
	ldr	r3, .L1452+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
.L23:
	ldr	r3, .L1452+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L1452+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
.L25:
	ldr	r3, .L1452+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L24:
	ldr	r3, .L1452+36
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+168
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
	mov	r3, #0
	mov	r4, r3
.L27:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L1452+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L1452+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L28:
	ldr	r3, .L1452+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L1452+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
	ldr	r3, .L1452+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L30:
	ldr	r3, .L1452+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L32
	ldr	r3, .L1452+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L32
	ldr	r3, .L1452+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L32:
	ldr	r3, .L1452+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L1452+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L33
	ldr	r3, .L1452+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L33:
	ldr	r3, .L1452+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L1452+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
	ldr	r3, .L1452+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L34:
	ldr	r3, .L1452+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L31:
	ldr	r3, .L1452+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L35
	ldr	r3, .L1452+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
.L35:
	ldr	r3, .L1452+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L1452+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
.L37:
	ldr	r3, .L1452+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L36:
	ldr	r3, .L1452+60
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+56
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L39
	mov	r3, #0
	mov	r4, r3
.L39:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L40
	ldr	r3, .L1452+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L1452+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L40:
	ldr	r3, .L1452+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L1452+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
	ldr	r3, .L1452+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L42:
	ldr	r3, .L1452+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L1452+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L1453
.L1454:
	.align	2
.L1452:
	.word	s13_l0
	.word	s13_evt2
	.word	s13_evt1
	.word	s13_evt0
	.word	s13_backoff
	.word	s12_l0
	.word	s12_evt2
	.word	s12_evt1
	.word	s12_evt0
	.word	s12_backoff
	.word	s11_l0
	.word	s11_evt2
	.word	s11_evt1
	.word	s11_evt0
	.word	s11_lambda
	.word	s11_backoff
	.word	s11_x
	.word	s10_l0
	.word	s10_evt2
	.word	s10_evt1
	.word	s10_evt0
	.word	s10_lambda
	.word	s10_backoff
	.word	s10_x
	.word	s9_l0
	.word	s9_evt2
	.word	s9_evt1
	.word	s9_evt0
	.word	s9_lambda
	.word	_diverge_delta
	.word	s2_x
	.word	s1_l1
	.word	s1_l0
	.word	s13_lambda
	.word	s1_evt2
	.word	s13_x
	.word	s1_evt1
	.word	s1_backoff
	.word	s2_backoff
	.word	s0_l1
	.word	s2_lambda
	.word	s0_l0
	.word	s12_lambda
	.word	s0_evt2
	.word	bus_evt0
	.word	s12_x
	.word	s0_evt1
	.word	s1_x
	.word	bus_j
	.word	s11_l1
	.word	s2_evt0
	.word	s0_x
	.word	s1_lambda
	.word	bus_x
	.word	s2_evt1
	.word	delta
	.word	s1_evt0
	.word	bus_cd_id
	.word	s0_lambda
	.word	s0_backoff
	.word	s0_evt0
	.word	s2_evt2
	.word	s2_l0
	.word	bus_evt1
	.word	s2_l1
	.word	bus_evt2
	.word	s3_backoff
	.word	s3_lambda
	.word	s12_l1
	.word	s13_l1
	.word	bus_l0
	.word	bus_l1
	.word	s10_evt2
	.word	s10_evt1
	.word	s10_evt0
	.word	s10_backoff
	.word	s10_x
	.word	s10_lambda
	.word	s10_l1
	.word	s10_l0
	.word	s9_evt2
	.word	s9_evt1
	.word	s9_evt0
	.word	s9_backoff
	.word	s9_x
	.word	s9_lambda
	.word	s9_l1
	.word	s9_l0
	.word	s8_evt2
	.word	s8_evt1
	.word	s8_evt0
	.word	s8_backoff
	.word	s8_x
	.word	s8_lambda
	.word	s8_l1
	.word	s8_l0
	.word	s7_evt2
	.word	s7_evt1
	.word	s7_evt0
	.word	s7_backoff
	.word	s7_x
	.word	s7_lambda
	.word	s7_l1
	.word	s7_l0
	.word	s6_evt2
	.word	s6_evt1
	.word	s6_evt0
	.word	s6_backoff
	.word	s6_x
	.word	s6_lambda
	.word	s6_l1
	.word	s6_l0
	.word	s5_evt2
	.word	s5_evt1
	.word	s5_evt0
	.word	s5_backoff
	.word	s5_x
	.word	s5_lambda
	.word	s5_l1
	.word	s5_l0
	.word	s4_evt2
	.word	s4_evt1
	.word	s4_evt0
	.word	s4_backoff
	.word	1095761920
	.word	s4_x
	.word	s4_lambda
	.word	s4_l1
	.word	s4_l0
	.word	s3_l0
	.word	s3_l1
	.word	s3_x
	.word	s3_evt0
	.word	s3_evt1
	.word	s3_evt2
.L1453:
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L1452+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L44:
	ldr	r3, .L1452+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L1452+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L45
	ldr	r3, .L1452+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L45:
	ldr	r3, .L1452+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L46
	ldr	r3, .L1452+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
	ldr	r3, .L1452+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L46:
	ldr	r3, .L1452+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L43:
	ldr	r3, .L1452+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L47
	ldr	r3, .L1452+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
.L47:
	ldr	r3, .L1452+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L1452+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
.L49:
	ldr	r3, .L1452+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L48:
	ldr	r3, .L1452+300
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+308
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	mov	r3, #0
	mov	r4, r3
.L51:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+304
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+308
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L1452+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L1452+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L52:
	ldr	r3, .L1452+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+336
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L54
	ldr	r3, .L1452+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
	ldr	r3, .L1452+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L54:
	ldr	r3, .L1452+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L56
	ldr	r3, .L1452+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L56
	ldr	r3, .L1452+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L56:
	ldr	r3, .L1452+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L1452+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L57
	ldr	r3, .L1452+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L57:
	ldr	r3, .L1452+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L1452+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
	ldr	r3, .L1452+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L58:
	ldr	r3, .L1452+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L55:
	ldr	r3, .L1452+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L59
	ldr	r3, .L1452+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
.L59:
	ldr	r3, .L1452+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L1452+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
.L61:
	ldr	r3, .L1452+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L60:
	ldr	r3, .L1452+332
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+340
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L63
	mov	r3, #0
	mov	r4, r3
.L63:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+336
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+340
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L64
	ldr	r3, .L1452+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L64
	ldr	r3, .L1452+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L64:
	ldr	r3, .L1452+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L1452+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L66
	ldr	r3, .L1452+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L66:
	ldr	r3, .L1452+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L68
	ldr	r3, .L1452+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L68
	ldr	r3, .L1452+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L68:
	ldr	r3, .L1452+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L1452+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L69
	ldr	r3, .L1452+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L69:
	ldr	r3, .L1452+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L1452+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L1452+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L70:
	ldr	r3, .L1452+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+360
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L67:
	ldr	r3, .L1452+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L71
	ldr	r3, .L1452+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
.L71:
	ldr	r3, .L1452+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L73
	ldr	r3, .L1452+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
.L73:
	ldr	r3, .L1452+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L72:
	ldr	r3, .L1452+364
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+372
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L75
	mov	r3, #0
	mov	r4, r3
.L75:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+368
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+372
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L1452+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L1452+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L76:
	ldr	r3, .L1452+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+400
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L1452+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
	ldr	r3, .L1452+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L78:
	ldr	r3, .L1452+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L1452+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L1452+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L80:
	ldr	r3, .L1452+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L1452+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
	ldr	r3, .L1452+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L81:
	ldr	r3, .L1452+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L1452+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L1452+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L82:
	ldr	r3, .L1452+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L79:
	ldr	r3, .L1452+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L1452+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
.L83:
	ldr	r3, .L1452+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L1452+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
.L85:
	ldr	r3, .L1452+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L84:
	ldr	r3, .L1452+396
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+404
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L87
	mov	r3, #0
	mov	r4, r3
.L87:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+400
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+404
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L1452+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L1452+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L88:
	ldr	r3, .L1452+444
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+432
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+416
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
	ldr	r3, .L1452+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L90
	ldr	r3, .L1452+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L90:
	ldr	r3, .L1452+416
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L92
	ldr	r3, .L1452+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L92
	ldr	r3, .L1452+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L92:
	ldr	r3, .L1452+416
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
	ldr	r3, .L1452+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L93
	ldr	r3, .L1452+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L93:
	ldr	r3, .L1452+416
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L1452+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L1452+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L94:
	ldr	r3, .L1452+416
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+420
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L91:
	ldr	r3, .L1452+444
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L95
	ldr	r3, .L1452+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
.L95:
	ldr	r3, .L1452+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L1452+444
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
.L97:
	ldr	r3, .L1452+444
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L96:
	ldr	r3, .L1452+428
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+436
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L99
	mov	r3, #0
	mov	r4, r3
.L99:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+432
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+436
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L1452+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L1452+444
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L100:
	ldr	r3, .L1452+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+464
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L102
	ldr	r3, .L1452+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
	ldr	r3, .L1452+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L102:
	ldr	r3, .L1452+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L1452+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L1452+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L104:
	ldr	r3, .L1452+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L1452+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L1452+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L105:
	ldr	r3, .L1452+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L1452+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
	ldr	r3, .L1452+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L106:
	ldr	r3, .L1452+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L103:
	ldr	r3, .L1452+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L107
	ldr	r3, .L1452+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
.L107:
	ldr	r3, .L1452+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L1452+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
.L109:
	ldr	r3, .L1452+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L108:
	ldr	r3, .L1452+460
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+468
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L111
	mov	r3, #0
	mov	r4, r3
.L111:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+464
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+468
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L112
	ldr	r3, .L1452+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L112
	ldr	r3, .L1452+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L112:
	ldr	r3, .L1452+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+500
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L1452+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L114
	ldr	r3, .L1452+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L114:
	ldr	r3, .L1452+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L1452+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L1452+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L116:
	ldr	r3, .L1452+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L1452+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L117
	ldr	r3, .L1452+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L117:
	ldr	r3, .L1452+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L1452+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
	ldr	r3, .L1452+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L118:
	ldr	r3, .L1452+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L115:
	ldr	r3, .L1452+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L119
	ldr	r3, .L1452+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
.L119:
	ldr	r3, .L1452+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
	ldr	r3, .L1452+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
.L121:
	ldr	r3, .L1452+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L120:
	ldr	r3, .L1452+492
	ldr	r3, [r3]	@ float
	ldr	r1, .L1452+496
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+504
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L123
	mov	r3, #0
	mov	r4, r3
.L123:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+500
	ldr	r3, [r3]	@ float
	ldr	r2, .L1452+504
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L1452+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L1452+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L124:
	ldr	r3, .L1452+516
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+520
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1452+524
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1452+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L1452+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
	ldr	r3, .L1452+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L126:
	ldr	r3, .L1452+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L1452+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
	ldr	r3, .L1452+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L128:
	ldr	r3, .L1452+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L1452+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L129
	ldr	r3, .L1452+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L129:
	ldr	r3, .L1452+536
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L1455
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L1455+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L130:
	ldr	r3, .L1455+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L127:
	ldr	r3, .L1455+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L1455+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
.L131:
	ldr	r3, .L1455+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L133
	ldr	r3, .L1455+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
.L133:
	ldr	r3, .L1455+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L132:
	ldr	r3, .L1455+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1455+628
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+24
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L135
	mov	r3, #0
	mov	r4, r3
.L135:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L136
	ldr	r3, .L1455+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L1455+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L136:
	ldr	r3, .L1455+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L1455+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L1455+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L138:
	ldr	r3, .L1455+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L1455+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L1455+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L140:
	ldr	r3, .L1455+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L1455+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L1455+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L141:
	ldr	r3, .L1455+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L1455+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
	ldr	r3, .L1455+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L142:
	ldr	r3, .L1455+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L139:
	ldr	r3, .L1455+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
	ldr	r3, .L1455+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
.L143:
	ldr	r3, .L1455+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L145
	ldr	r3, .L1455+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
.L145:
	ldr	r3, .L1455+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L144:
	ldr	r3, .L1455+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L1455+628
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+60
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L147
	mov	r3, #0
	mov	r4, r3
.L147:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L1455+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L1455+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L148:
	ldr	r3, .L1455+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L150
	ldr	r3, .L1455+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
	ldr	r3, .L1455+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L150:
	ldr	r3, .L1455+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L1455+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L152
	ldr	r3, .L1455+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L152:
	ldr	r3, .L1455+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L1455+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L153
	ldr	r3, .L1455+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L153:
	ldr	r3, .L1455+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L1455+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
	ldr	r3, .L1455+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L154:
	ldr	r3, .L1455+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L151:
	ldr	r3, .L1455+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L1455+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
.L155:
	ldr	r3, .L1455+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L1455+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
.L157:
	ldr	r3, .L1455+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L156:
	ldr	r3, .L1455+88
	ldr	r3, [r3]	@ float
	ldr	r1, .L1455+628
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+92
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L159
	mov	r3, #0
	mov	r4, r3
.L159:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L160
	ldr	r3, .L1455+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
	ldr	r3, .L1455+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L160:
	ldr	r3, .L1455+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+104
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L1455+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L162
	ldr	r3, .L1455+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L162:
	ldr	r3, .L1455+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L1455+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L1455+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L164:
	ldr	r3, .L1455+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L1455+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L165
	ldr	r3, .L1455+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L165:
	ldr	r3, .L1455+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L1455+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
	ldr	r3, .L1455+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L166:
	ldr	r3, .L1455+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L163:
	ldr	r3, .L1455+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L167
	ldr	r3, .L1455+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
.L167:
	ldr	r3, .L1455+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L1455+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
.L169:
	ldr	r3, .L1455+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L168:
	ldr	r3, .L1455+120
	ldr	r3, [r3]	@ float
	ldr	r1, .L1455+628
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+124
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L171
	mov	r3, #0
	mov	r4, r3
.L171:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L1455+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L1455+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L172:
	ldr	r3, .L1455+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L1455+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L1455+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L173:
	ldr	r3, .L1455+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
	ldr	r3, .L1455+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L175
	ldr	r3, .L1455+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L175:
	ldr	r3, .L1455+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L176
	ldr	r3, .L1455+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L1455+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L176:
	ldr	r3, .L1455+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L1455+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L1455+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L177:
	ldr	r3, .L1455+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L174:
	ldr	r3, .L1455+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L1455+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L178:
	ldr	r3, .L1455+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L1455+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L180:
	ldr	r3, .L1455+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L1455+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L181:
	ldr	r3, .L1455+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L179:
	ldr	r3, .L1455+148
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1455+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+152
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1455+628
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L183
	mov	r3, #0
	mov	r4, r3
.L183:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L1455+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L1455+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L184:
	ldr	r3, .L1455+648
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L185
	ldr	r3, .L1455+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L1455+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L185:
	ldr	r3, .L1455+648
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1455+648
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L188
.L4:
	mov	r3, #0
.L188:
	str	r3, [fp, #-24]
	b	.L189
.L1456:
	.align	2
.L1455:
	.word	s3_evt1
	.word	s3_evt0
	.word	s3_evt2
	.word	s3_l0
	.word	s3_l1
	.word	s3_backoff
	.word	s3_lambda
	.word	s3_x
	.word	s2_l0
	.word	s2_l1
	.word	s2_x
	.word	s2_evt2
	.word	s2_evt0
	.word	s2_evt1
	.word	s2_backoff
	.word	s2_lambda
	.word	s1_l0
	.word	s1_l1
	.word	s1_x
	.word	s1_evt2
	.word	s1_evt0
	.word	s1_evt1
	.word	s1_backoff
	.word	s1_lambda
	.word	s0_l0
	.word	s0_l1
	.word	s0_x
	.word	s0_evt2
	.word	s0_evt0
	.word	s0_evt1
	.word	s0_backoff
	.word	s0_lambda
	.word	bus_l0
	.word	bus_l1
	.word	bus_evt2
	.word	bus_evt0
	.word	bus_evt1
	.word	bus_j
	.word	bus_x
	.word	_diverge_delta
	.word	_x_s12_l0
	.word	_x_s12_evt2
	.word	_x_s12_evt1
	.word	_x_s12_evt0
	.word	_x_s12_backoff
	.word	_x_s11_l0
	.word	_x_s11_evt2
	.word	_x_s11_evt1
	.word	_x_s11_evt0
	.word	_x_s11_lambda
	.word	_x_s11_backoff
	.word	_x_s11_x
	.word	_x_s10_l0
	.word	_x_s10_evt2
	.word	_x_s10_evt1
	.word	_x_s10_evt0
	.word	_x_s10_lambda
	.word	_x_s10_backoff
	.word	_x_s10_x
	.word	_x_s9_l0
	.word	_x_s9_evt2
	.word	_x_s9_evt1
	.word	_x_s9_evt0
	.word	_x_s9_lambda
	.word	_x_s9_backoff
	.word	_x_s9_x
	.word	_x_s8_l1
	.word	_x_s8_l0
	.word	_x_s8_evt2
	.word	_x_s8_evt1
	.word	_x_s8_evt0
	.word	_x_s8_lambda
	.word	_x_s8_backoff
	.word	_x_s8_x
	.word	_x_s7_l1
	.word	_x_s7_l0
	.word	_x_s7_evt2
	.word	_x__diverge_delta
	.word	_x_s7_evt1
	.word	_x_s7_evt0
	.word	_x_s7_lambda
	.word	_x_s7_backoff
	.word	_x_s7_x
	.word	_x_s6_l1
	.word	_x_s6_l0
	.word	_x_s6_evt2
	.word	_x_s6_evt1
	.word	_x_s6_evt0
	.word	_x_s6_lambda
	.word	_x_s2_x
	.word	_x_s1_l1
	.word	_x_s4_evt2
	.word	_x_s1_l0
	.word	_x_s4_evt1
	.word	_x_s1_evt2
	.word	_x_s1_evt1
	.word	_x_s1_backoff
	.word	_x_s6_x
	.word	_x_s2_backoff
	.word	_x_s0_l1
	.word	_x_s3_evt2
	.word	_x_s2_lambda
	.word	_x_s0_l0
	.word	_x_s3_evt1
	.word	_x_s12_lambda
	.word	_x_s0_evt2
	.word	_x_bus_evt0
	.word	_x_s5_evt0
	.word	_x_s12_x
	.word	_x_s0_evt1
	.word	_x_s4_backoff
	.word	_x_s1_x
	.word	_x_s5_backoff
	.word	_x_bus_j
	.word	_x_s11_l1
	.word	_x_s2_evt0
	.word	_x_s0_x
	.word	_x_s1_lambda
	.word	_x_bus_x
	.word	_x_s2_evt1
	.word	_x_s6_backoff
	.word	_x_delta
	.word	_x_s10_l1
	.word	_x_s1_evt0
	.word	_x_bus_cd_id
	.word	_x_s5_lambda
	.word	_x_s0_lambda
	.word	_x_s0_backoff
	.word	_x_s5_x
	.word	_x_s3_l0
	.word	_x_s9_l1
	.word	_x_s0_evt0
	.word	_x_s4_lambda
	.word	_x_s2_evt2
	.word	_x_s2_l0
	.word	_x_bus_evt1
	.word	_x_s5_evt1
	.word	_x_s2_l1
	.word	_x_bus_evt2
	.word	_x_s5_evt2
	.word	_x_s3_x
	.word	_x_s3_backoff
	.word	_x_s3_lambda
	.word	_x_s12_l1
	.word	_x_s3_evt0
	.word	_x_s3_l1
	.word	_x_s4_x
	.word	_x_s4_evt0
	.word	_x_s4_l0
	.word	_x_s4_l1
	.word	_x_bus_l0
	.word	_x_s5_l0
	.word	_x_bus_l1
	.word	_x_s5_l1
	.word	_x_s13_evt2
	.word	_x_s13_evt1
	.word	_x_s13_evt0
	.word	1095761920
	.word	s13_x
	.word	s13_backoff
	.word	_x_s13_backoff
	.word	_x_s13_x
	.word	delta
	.word	s13_lambda
	.word	_x_s13_lambda
	.word	s13_evt2
	.word	s13_evt0
	.word	s13_evt1
	.word	_x_s13_l0
	.word	_x_s13_l1
	.word	s13_l0
	.word	s13_l1
.L1258:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+672
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+616
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+620
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+624
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+640
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+176
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+196
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+200
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+204
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+220
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+224
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+228
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+232
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+236
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+252
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+256
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+280
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+284
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+288
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+292
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+300
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+308
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+320
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+324
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+328
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+332
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+336
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+340
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+352
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+356
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+360
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+364
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+368
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+656
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+376
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+644
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+380
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+384
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+388
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+392
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+396
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+400
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+404
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+408
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+412
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+416
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+420
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+424
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+428
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+432
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+436
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+440
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+444
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+448
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L1455+452
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+456
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+460
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+464
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+468
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+472
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+476
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+480
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+484
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+488
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+492
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L1455+496
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+500
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+504
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+508
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+512
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+516
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+520
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+524
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+528
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+532
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+536
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+540
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+544
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+548
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+552
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+556
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+560
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+564
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+568
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+572
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+576
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+580
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1455+584
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+676
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+588
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+592
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+596
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+600
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+604
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+608
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1455+612
	strb	r2, [r3]
	ldr	r3, .L1455+616
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L1455+624
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L1455+620
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L190:
	ldr	r3, .L1455+616
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L1455+624
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L1455+620
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L192:
	ldr	r3, .L1455+616
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L1455+624
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L1455+620
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L193:
	ldr	r3, .L1455+616
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L1455+620
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L1455+624
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L194:
	ldr	r3, .L1455+616
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1455+620
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1455+624
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L191:
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
.L196:
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
.L198:
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L197:
	ldr	r3, .L1455+640
	ldr	r3, [r3]	@ float
	ldr	r1, .L1455+628
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1455+656
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L200
	mov	r3, #0
	mov	r4, r3
.L200:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1455+644
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+656
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L201:
	ldr	r3, .L1455+680
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L1455+684
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L1455+652
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+656
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L1455+648
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1455+632
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1455+644
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L1455+636
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+640
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L205
.L202:
	ldr	r3, .L1455+648
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1455+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L1455+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L1455+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L205:
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
.L207:
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
.L209:
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
.L208:
	ldr	r3, .L1455+636
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+640
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L1455+644
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L212
.L210:
	ldr	r3, .L1455+680
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L1455+684
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L1455+648
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L1455+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1455+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1455+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L212:
	ldr	r3, .L1455+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L1455+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L1455+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L1455+652
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+656
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L214
.L213:
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L1455+680
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L1455+684
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L1455+648
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L1455+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1455+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1455+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L214:
	ldr	r3, .L1455+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L1455+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L1455+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
.L215:
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	ldr	r3, .L1455+680
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	ldr	r3, .L1455+684
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	ldr	r3, .L1455+648
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L1455+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1455+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1455+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L216:
	ldr	r3, .L1455+652
	ldr	r3, [r3]	@ float
	ldr	r2, .L1455+656
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L1455+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L1455+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L1455+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
.L219:
	ldr	r3, .L1455+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L1455+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L1455+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
.L217:
	ldr	r3, .L1455+672
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L1455+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L1455+680
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L1455+684
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L220:
	ldr	r3, .L1457+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L1457+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L1457+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L1457+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L225
.L224:
	ldr	r3, .L1457+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L1457+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L225
.L221:
	ldr	r3, .L1457+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L225
	ldr	r3, .L1457+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L225
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L225
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L225:
	ldr	r3, .L1457+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L1457+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L228
.L226:
	ldr	r3, .L1457+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L228
	ldr	r3, .L1457+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L228
	ldr	r3, .L1457+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L1457+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L228
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L228:
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L1457+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1457+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1457+140
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L230
.L229:
	ldr	r3, .L1457+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L1457+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L1457+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L1457+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L230:
	ldr	r3, .L1457+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L1457+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L1457+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
.L233:
	ldr	r3, .L1457+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L1457+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L231
.L234:
	ldr	r3, .L1457+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L1457+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L236
.L231:
	ldr	r3, .L1457+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L1457+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L236:
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L238
.L237:
	ldr	r3, .L1457+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L238
	ldr	r3, .L1457+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1457+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L238
	ldr	r3, .L1457+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L238
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L238:
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L1457+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L240
.L239:
	ldr	r3, .L1457+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L1457+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L240
	ldr	r3, .L1457+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L1457+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L240
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L1457+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L240:
	ldr	r3, .L1457+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L1457+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L1457+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
.L241:
	ldr	r3, .L1457+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L1457+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L1457+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
.L243:
	ldr	r3, .L1457+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
	ldr	r3, .L1457+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L244
	ldr	r3, .L1457+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
.L244:
	ldr	r3, .L1457+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1457+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1457+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
.L245:
	ldr	r3, .L1457+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L242:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L246
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L246:
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L248
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L248:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L247:
	ldr	r3, .L1457+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1457+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+72
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L250
	mov	r3, #0
	mov	r4, r3
.L250:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L251
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L251:
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L1457+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1457+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1457+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L1457+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L255
.L252:
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L255
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L255
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L255:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L258
.L257:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L259
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L258
.L259:
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
.L258:
	ldr	r3, .L1457+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1457+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L262
.L260:
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L262:
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1457+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L264
.L263:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L264:
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
.L265:
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L266:
	ldr	r3, .L1457+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L267
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
.L269:
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L267
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L267
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
.L267:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L270
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L270
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L270
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L270
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L270:
	ldr	r3, .L1457+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L1457+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L274
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
.L274:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
.L271:
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L275
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L275:
	ldr	r3, .L1457+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L276
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L276
	ldr	r3, .L1457+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L278
.L276:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L1457
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L278:
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L279
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	b	.L1458
.L1459:
	.align	2
.L1457:
	.word	delta
	.word	s13_evt2
	.word	s13_evt0
	.word	s13_evt1
	.word	s13_lambda
	.word	_x_s13_lambda
	.word	_x_s13_x
	.word	_x_s13_l0
	.word	_x_s13_l1
	.word	s13_l1
	.word	s13_l0
	.word	s13_x
	.word	_x_s13_backoff
	.word	s13_backoff
	.word	_x_s12_evt2
	.word	_x_s12_evt0
	.word	_x_s12_evt1
	.word	s12_lambda
	.word	_x_s12_lambda
	.word	_x_s12_backoff
	.word	_x_s12_x
	.word	s12_backoff
	.word	s12_x
	.word	_x_s12_l1
	.word	_x_s12_l0
	.word	s12_l0
	.word	s12_l1
	.word	s12_evt2
	.word	s12_evt0
	.word	s12_evt1
	.word	_x_s11_evt2
	.word	_x_s11_evt1
	.word	_x_s11_evt0
	.word	1095761920
	.word	s11_x
	.word	-1074790400
	.word	s11_lambda
	.word	_x_s11_lambda
	.word	s11_backoff
	.word	_x_s11_backoff
	.word	_x_s11_x
	.word	delta
	.word	s11_evt2
	.word	s11_evt0
	.word	s11_evt1
	.word	_x_s11_l0
	.word	_x_s11_l1
	.word	s11_l0
	.word	s11_l1
.L1458:
	bne	.L279
	ldr	r3, .L1457+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1457+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1457+140
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L280
.L279:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L280:
	ldr	r3, .L1457+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
.L283:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L281
.L284:
	ldr	r3, .L1457+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L1457+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L286
.L281:
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L286
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L286:
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L288
.L287:
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L288
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L288
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L288:
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L289
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L289
	ldr	r3, .L1457+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L290
.L289:
	ldr	r3, .L1457+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L1457+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L290
	ldr	r3, .L1457+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L1457+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L290
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L1457+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L290:
	ldr	r3, .L1457+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L1457+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L1457+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L292
.L291:
	ldr	r3, .L1457+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1457+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1457+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L292
.L293:
	ldr	r3, .L1457+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L294
	ldr	r3, .L1457+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L294
	ldr	r3, .L1457+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L292
.L294:
	ldr	r3, .L1457+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L1457+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
	ldr	r3, .L1457+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L292
.L295:
	ldr	r3, .L1457+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L292:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L296
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L297
.L296:
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L297
.L298:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L297:
	ldr	r3, .L1457+156
	ldr	r3, [r3]	@ float
	ldr	r1, .L1457+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+148
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L300
	mov	r3, #0
	mov	r4, r3
.L300:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L301
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L301:
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1457+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1457+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1457+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1457+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L305
.L302:
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L305:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L307:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L309
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
.L309:
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
.L308:
	ldr	r3, .L1457+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1457+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L312
.L310:
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L312
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L312
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L312:
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L313
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L313
	ldr	r3, .L1457+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L314
.L313:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L314
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L314:
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
.L315:
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L316:
	ldr	r3, .L1457+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L317
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L319
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L319
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
.L319:
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L317
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
.L317:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L320
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L320
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L320
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L320:
	ldr	r3, .L1457+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1457+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L325
.L324:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L325
.L321:
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L325
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L325
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L325
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L325:
	ldr	r3, .L1457+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1457+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L328
.L326:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L328
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L328
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L328
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L328
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L328
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L328:
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L1457+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1457+156
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1457+140
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L330
.L329:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L330
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L330
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L330:
	ldr	r3, .L1457+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L333
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L334
.L333:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L331
.L334:
	ldr	r3, .L1457+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1457+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1457+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L336
.L331:
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L336
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L336
	ldr	r3, .L1457+164
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L336
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L336:
	ldr	r3, .L1457+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L1457+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1457+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L338
.L337:
	ldr	r3, .L1457+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L1457+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L338
	ldr	r3, .L1457+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L1457+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L338
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L1460+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L338:
	ldr	r3, .L1460+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L339
	ldr	r3, .L1460+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L339
	ldr	r3, .L1460+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L339
	ldr	r3, .L1460+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L340
.L339:
	ldr	r3, .L1460+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L340
	ldr	r3, .L1460+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L340
	ldr	r3, .L1460+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L340
	ldr	r3, .L1460+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L340
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L340
	ldr	r3, .L1460+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L340:
	ldr	r3, .L1460+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L341
	ldr	r3, .L1460+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L1460+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L342
.L341:
	ldr	r3, .L1460+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L343
	ldr	r3, .L1460+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L343
	ldr	r3, .L1460+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L342
.L343:
	ldr	r3, .L1460+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L1460+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L344
	ldr	r3, .L1460+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L342
.L344:
	ldr	r3, .L1460+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L345
	ldr	r3, .L1460+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L345
	ldr	r3, .L1460+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L342
.L345:
	ldr	r3, .L1460+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L342:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L347
.L346:
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L347
.L348:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L347:
	ldr	r3, .L1460+60
	ldr	r3, [r3]	@ float
	ldr	r1, .L1460+184
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L350
	mov	r3, #0
	mov	r4, r3
.L350:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L351
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L351:
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L352
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L352
	ldr	r3, .L1460+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L352
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1460+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1460+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L352
	ldr	r3, .L1460+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L355
.L352:
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L355
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L355
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L355:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L358
.L357:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L358
.L359:
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L360
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L360
.L358:
	ldr	r3, .L1460+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L360
	ldr	r3, .L1460+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L362
.L360:
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L362:
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L363
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L363
	ldr	r3, .L1460+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L364
.L363:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L364
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L364
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L364
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L364
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L364:
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L365
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L365
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
.L365:
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L366
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L366
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L366
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L366:
	ldr	r3, .L1460+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
.L369:
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L367
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
.L367:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L370:
	ldr	r3, .L1460+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1460+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L374
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L375
.L374:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L375
.L371:
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L375
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L375
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L375
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L375:
	ldr	r3, .L1460+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L376
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L376
	ldr	r3, .L1460+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L378
.L376:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L378
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L378
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L378
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L378
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L378
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L378:
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L1460+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1460+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1460+116
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L380
.L379:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L380
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L380
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L380
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L380
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L380
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L380:
	ldr	r3, .L1460+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L383
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
.L383:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L381
.L384:
	ldr	r3, .L1460+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1460+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L386
.L381:
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L386
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L386:
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L387
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L388
.L387:
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L388
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L388
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L388
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L388
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L388
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L388:
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L1460+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L390
.L389:
	ldr	r3, .L1460+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1460+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1460+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1460+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1460+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L390:
	ldr	r3, .L1460+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L391
	ldr	r3, .L1460+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
	ldr	r3, .L1460+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
.L391:
	ldr	r3, .L1460+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L393
	ldr	r3, .L1460+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L393
	ldr	r3, .L1460+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
.L393:
	ldr	r3, .L1460+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L394
	ldr	r3, .L1460+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L394
	ldr	r3, .L1460+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
.L394:
	ldr	r3, .L1460+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L395
	ldr	r3, .L1460+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L1460+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
.L395:
	ldr	r3, .L1460+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L392:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L396
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L397
.L396:
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L398
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L397
.L398:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	b	.L1461
.L1462:
	.align	2
.L1460:
	.word	delta
	.word	s11_evt2
	.word	s11_evt0
	.word	s11_evt1
	.word	s11_backoff
	.word	s11_x
	.word	_x_s11_l1
	.word	_x_s11_l0
	.word	s11_l0
	.word	s11_l1
	.word	_x_s10_evt2
	.word	_x_s10_evt0
	.word	_x_s10_evt1
	.word	_x_s10_l0
	.word	_x_s10_l1
	.word	_x_s10_backoff
	.word	_x_s10_lambda
	.word	_x_s10_x
	.word	s10_l0
	.word	s10_l1
	.word	s10_lambda
	.word	s10_x
	.word	s10_backoff
	.word	s10_evt2
	.word	s10_evt0
	.word	s10_evt1
	.word	_x_s9_evt2
	.word	_x_s9_evt0
	.word	_x_s9_evt1
	.word	-1074790400
	.word	s9_lambda
	.word	_x_s9_lambda
	.word	_x_s9_backoff
	.word	_x_s9_x
	.word	s9_backoff
	.word	s9_x
	.word	_x_s9_l1
	.word	_x_s9_l0
	.word	s9_l0
	.word	s9_l1
	.word	s9_evt2
	.word	s9_evt0
	.word	s9_evt1
	.word	_x_s8_evt2
	.word	_x_s8_evt1
	.word	_x_s8_evt0
	.word	1095761920
	.word	s8_l0
	.word	s8_l1
	.word	s8_lambda
	.word	_x_s8_lambda
	.word	s8_x
	.word	_x_s8_x
	.word	s8_backoff
	.word	_x_s8_backoff
	.word	delta
	.word	s8_evt2
	.word	s8_evt0
	.word	s8_evt1
	.word	_x_s8_l0
	.word	_x_s8_l1
.L1461:
	bne	.L195
.L397:
	ldr	r3, .L1460+128
	ldr	r3, [r3]	@ float
	ldr	r1, .L1460+184
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+124
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L400
	mov	r3, #0
	mov	r4, r3
.L400:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L401
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L401:
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L402
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L402
	ldr	r3, .L1460+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L402
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1460+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1460+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L402
	ldr	r3, .L1460+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L405
.L402:
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L405
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L405
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L405:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L408
.L407:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L409
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L408
.L409:
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L410
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L410
.L408:
	ldr	r3, .L1460+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L410
	ldr	r3, .L1460+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L412
.L410:
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L412:
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L413
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L413
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L413
	ldr	r3, .L1460+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L414
.L413:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L414:
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L415
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L415
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
.L415:
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L416:
	ldr	r3, .L1460+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
.L419:
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L417
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
.L417:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L420
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L420
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L420
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L420:
	ldr	r3, .L1460+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L1460+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L424
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
.L424:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
.L421:
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L425:
	ldr	r3, .L1460+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L426
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L426
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L426
	ldr	r3, .L1460+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L428
.L426:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L428
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L428
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L428
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L428:
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L429
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L429
	ldr	r3, .L1460+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1460+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1460+116
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L430
.L429:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L430
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L430
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L430:
	ldr	r3, .L1460+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L433
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
.L433:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L431
.L434:
	ldr	r3, .L1460+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L1460+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L436
.L431:
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L436
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L436:
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L437
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L438
.L437:
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L438
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L438
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L438
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L438
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L438
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L438:
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L1460+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L440
.L439:
	ldr	r3, .L1460+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1460+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L440
	ldr	r3, .L1460+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1460+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L440
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1460+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1460+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L440:
	ldr	r3, .L1460+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L441
	ldr	r3, .L1460+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L1460+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L442
.L441:
	ldr	r3, .L1460+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L443
	ldr	r3, .L1460+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L443
	ldr	r3, .L1460+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L442
.L443:
	ldr	r3, .L1460+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L444
	ldr	r3, .L1460+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L444
	ldr	r3, .L1460+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L442
.L444:
	ldr	r3, .L1460+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L445
	ldr	r3, .L1460+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L1460+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L442
.L445:
	ldr	r3, .L1460+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L442:
	ldr	r3, .L1460+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L446
	ldr	r3, .L1460+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
.L446:
	ldr	r3, .L1460+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L448
	ldr	r3, .L1460+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
.L448:
	ldr	r3, .L1460+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L447:
	ldr	r3, .L1460+216
	ldr	r3, [r3]	@ float
	ldr	r1, .L1460+184
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+200
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L450
	mov	r3, #0
	mov	r4, r3
.L450:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+200
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L451
	ldr	r3, .L1460+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
	ldr	r3, .L1460+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L451:
	ldr	r3, .L1460+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1460+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1460+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1460+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1460+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+200
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1460+204
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1460+208
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1460+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1460+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L455
.L452:
	ldr	r3, .L1460+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1460+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L455
	ldr	r3, .L1460+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L455
	ldr	r3, .L1460+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L455:
	ldr	r3, .L1460+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
	ldr	r3, .L1460+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
.L457:
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L459
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
.L459:
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L460
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L460
.L458:
	ldr	r3, .L1463+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L460
	ldr	r3, .L1463+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L462
.L460:
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L462
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L462
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L462:
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L463
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L463
	ldr	r3, .L1463+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L464
.L463:
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L464
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L464
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L464
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L464
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L464
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L464:
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L465
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L465
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
.L465:
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L466:
	ldr	r3, .L1463+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L470
.L469:
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L470
.L467:
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L470
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L470
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L470
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L470:
	ldr	r3, .L1463+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L1463+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L474
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L475
.L474:
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L475
.L471:
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L475
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L475:
	ldr	r3, .L1463+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L476
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L476
	ldr	r3, .L1463+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L478
.L476:
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L478
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L478
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L478:
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L479
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L479
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L479
	ldr	r3, .L1463+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1463+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1463+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L480
.L479:
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L480:
	ldr	r3, .L1463+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L483
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
.L483:
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L481
.L484:
	ldr	r3, .L1463+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L1463+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L486
.L481:
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L486
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L486:
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L487
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L487
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L488
.L487:
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L488
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L488
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L488
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L488
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L488
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L488:
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1463+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L490
.L489:
	ldr	r3, .L1463+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L1463
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L490
	ldr	r3, .L1463+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L1463+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L490
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L1463+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L490:
	ldr	r3, .L1463+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L1463+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1463+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L492
.L491:
	ldr	r3, .L1463+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L493
	ldr	r3, .L1463+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L493
	ldr	r3, .L1463+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L492
.L493:
	ldr	r3, .L1463+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1463+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L494
	ldr	r3, .L1463+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L492
.L494:
	ldr	r3, .L1463+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L495
	ldr	r3, .L1463+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
	ldr	r3, .L1463+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L492
.L495:
	ldr	r3, .L1463+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L492:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L496
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L497
.L496:
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L498
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L497
.L498:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L497:
	ldr	r3, .L1463+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1463+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+72
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L500
	mov	r3, #0
	mov	r4, r3
.L500:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L501
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L501
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L501:
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1463+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1463+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1463+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1463+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L505
.L502:
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L505
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L505
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L505:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L508
.L507:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L509
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L508
.L509:
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L510
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L510
.L508:
	ldr	r3, .L1463+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L510
	ldr	r3, .L1463+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L512
.L510:
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L512
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L512
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L512
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L512:
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L513
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L513
	ldr	r3, .L1463+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L514
.L513:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L514
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L514
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L514
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L514
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L514:
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L515
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L515
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
.L515:
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	b	.L1464
.L1465:
	.align	2
.L1463:
	.word	_x_s8_l0
	.word	_x_s8_l1
	.word	s8_backoff
	.word	_x_s8_backoff
	.word	_x_s8_x
	.word	s8_l0
	.word	s8_l1
	.word	s8_evt2
	.word	s8_evt0
	.word	s8_evt1
	.word	s8_lambda
	.word	_x_s8_lambda
	.word	s8_x
	.word	_x_s7_evt2
	.word	_x_s7_evt0
	.word	_x_s7_evt1
	.word	-1074790400
	.word	s7_lambda
	.word	_x_s7_lambda
	.word	_x_s7_backoff
	.word	_x_s7_x
	.word	s7_backoff
	.word	s7_x
	.word	_x_s7_l1
	.word	_x_s7_l0
	.word	s7_l0
	.word	s7_l1
	.word	s7_evt2
	.word	s7_evt0
	.word	s7_evt1
	.word	_x_s6_evt2
	.word	_x_s6_evt1
	.word	_x_s6_evt0
	.word	1095761920
	.word	delta
	.word	s6_backoff
	.word	_x_s6_backoff
	.word	_x_s6_lambda
	.word	_x_s6_x
	.word	_x_s6_l0
	.word	_x_s6_l1
	.word	s6_l1
	.word	s6_l0
	.word	delta
	.word	s6_lambda
	.word	s6_x
	.word	s6_evt2
	.word	s6_evt1
	.word	s6_evt0
.L1464:
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L516:
	ldr	r3, .L1463+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L517
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
.L519:
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L517
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L517
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
.L517:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L520
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L520
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L520
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L520
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L520:
	ldr	r3, .L1463+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L1463+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L525
.L524:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L525
.L521:
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L525
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L525
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L525
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L525:
	ldr	r3, .L1463+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L526
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L526
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L526
	ldr	r3, .L1463+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L528
.L526:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L528
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L528
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L528
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L528:
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L529
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L529
	ldr	r3, .L1463+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1463+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1463+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L530
.L529:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L530
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L530
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L530
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L530
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L530
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L530:
	ldr	r3, .L1463+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L533
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L534
.L533:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L531
.L534:
	ldr	r3, .L1463+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L1463+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L536
.L531:
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L536
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L536:
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L537
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L537
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L538
.L537:
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L538
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L538
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L538
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L538:
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L1463+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L540
.L539:
	ldr	r3, .L1463+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L540
	ldr	r3, .L1463+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L540
	ldr	r3, .L1463+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L540
	ldr	r3, .L1463+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L540
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L540
	ldr	r3, .L1463+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L540:
	ldr	r3, .L1463+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L541
	ldr	r3, .L1463+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1463+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
.L541:
	ldr	r3, .L1463+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L543
	ldr	r3, .L1463+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L543
	ldr	r3, .L1463+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
.L543:
	ldr	r3, .L1463+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L1463+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L544
	ldr	r3, .L1463+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
.L544:
	ldr	r3, .L1463+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L545
	ldr	r3, .L1463+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L545
	ldr	r3, .L1463+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
.L545:
	ldr	r3, .L1463+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L542:
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L546
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L547
.L546:
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L548
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L547
.L548:
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L547:
	ldr	r3, .L1463+144
	ldr	r3, [r3]	@ float
	ldr	r1, .L1463+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+148
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L550
	mov	r3, #0
	mov	r4, r3
.L550:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L551
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L551:
	ldr	r3, .L1463+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1463+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1463+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1463+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1463+180
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1463+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1463+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L555
.L552:
	ldr	r3, .L1463+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L555:
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
.L557:
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L559
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L558
.L559:
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
.L558:
	ldr	r3, .L1463+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L1463+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L562
.L560:
	ldr	r3, .L1463+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L562
	ldr	r3, .L1463+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L562
	ldr	r3, .L1463+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L562:
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L563
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L563
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L563
	ldr	r3, .L1463+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L564
.L563:
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L564
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L564
	ldr	r3, .L1463+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L564
	ldr	r3, .L1463+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L564
	ldr	r3, .L1463+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L564
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L564:
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L565
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L565
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
.L565:
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L1463+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L1463+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L1463+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L566:
	ldr	r3, .L1463+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L567
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L570
.L569:
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L567
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L567
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L570
.L567:
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L570
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L570
	ldr	r3, .L1463+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L570
	ldr	r3, .L1463+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L570
	ldr	r3, .L1463+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L570
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L570:
	ldr	r3, .L1463+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L1463+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L574
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
.L574:
	ldr	r3, .L1463+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L1463+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
.L571:
	ldr	r3, .L1463+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
	ldr	r3, .L1463+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L575
	ldr	r3, .L1463+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L575
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L575:
	ldr	r3, .L1463+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1463+180
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L576
	ldr	r3, .L1463+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L576
	ldr	r3, .L1463+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L576
	ldr	r3, .L1463+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L576
	ldr	r3, .L1466
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L578
.L576:
	ldr	r3, .L1466+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L578
	ldr	r3, .L1466+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L578
	ldr	r3, .L1466+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L1466+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L578
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L1466+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L578:
	ldr	r3, .L1466+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L1466+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L1466+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L1466+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1466
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1466+136
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L580
.L579:
	ldr	r3, .L1466+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L1466+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L580
	ldr	r3, .L1466+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L1466+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L580
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L1466+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L580:
	ldr	r3, .L1466+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L1466+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L583
	ldr	r3, .L1466+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
.L583:
	ldr	r3, .L1466+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L1466+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L581
.L584:
	ldr	r3, .L1466+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L1466+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L586
.L581:
	ldr	r3, .L1466+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L586
	ldr	r3, .L1466+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L586
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L586
	ldr	r3, .L1466+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L586:
	ldr	r3, .L1466+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L587
	ldr	r3, .L1466+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L1466+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
.L587:
	ldr	r3, .L1466+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1466+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1466+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1466+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1466+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L588:
	ldr	r3, .L1466+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L589
	ldr	r3, .L1466+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L1466+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L1466+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L590
.L589:
	ldr	r3, .L1466+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1466+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1466+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1466+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1466+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L590:
	ldr	r3, .L1466+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L591
	ldr	r3, .L1466+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L591
	ldr	r3, .L1466+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L592
.L591:
	ldr	r3, .L1466+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L1466+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L1466+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L592
.L593:
	ldr	r3, .L1466+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L1466+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L594
	ldr	r3, .L1466+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L592
.L594:
	ldr	r3, .L1466+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L595
	ldr	r3, .L1466+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1466+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L592
.L595:
	ldr	r3, .L1466+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L592:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L596
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
.L596:
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L598
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
.L598:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L597:
	ldr	r3, .L1466+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L1466+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+72
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L600
	mov	r3, #0
	mov	r4, r3
.L600:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L601
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L601:
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L1466+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1466+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1466+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L1466+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L605
.L602:
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L605
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L605
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L605:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L608
.L607:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L609
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L608
.L609:
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L610
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
.L608:
	ldr	r3, .L1466+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L610
	ldr	r3, .L1466+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L612
.L610:
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L612:
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L613
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L613
	ldr	r3, .L1466+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L614
.L613:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L614
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L614
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L614
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L614
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L614
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L614:
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
.L615:
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L616
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L616
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L616
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L616:
	ldr	r3, .L1466+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L619
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L619
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
.L619:
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L617
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
.L617:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L620
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L620:
	ldr	r3, .L1466+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L1466+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L624
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L625
.L624:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L625
.L621:
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L625
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L625
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L625
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L625:
	ldr	r3, .L1466+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L1466+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L628
.L626:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L628
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L628
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L628
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L628:
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L629
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L629
	ldr	r3, .L1466+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1466+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1466+136
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L630
.L629:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L630
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L630
	ldr	r3, .L1466+24
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L630
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L630:
	ldr	r3, .L1466+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L633
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L634
.L633:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L631
.L634:
	ldr	r3, .L1466+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L1466+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	b	.L1467
.L1468:
	.align	2
.L1466:
	.word	_x_s6_backoff
	.word	s6_backoff
	.word	_x_s6_l0
	.word	_x_s6_l1
	.word	s6_l1
	.word	s6_l0
	.word	delta
	.word	s6_evt2
	.word	s6_evt0
	.word	s6_evt1
	.word	s6_lambda
	.word	_x_s6_lambda
	.word	_x_s6_x
	.word	s6_x
	.word	_x_s5_evt2
	.word	_x_s5_evt0
	.word	_x_s5_evt1
	.word	_x_s5_backoff
	.word	_x_s5_lambda
	.word	_x_s5_x
	.word	s5_lambda
	.word	s5_backoff
	.word	s5_x
	.word	_x_s5_l1
	.word	_x_s5_l0
	.word	s5_l0
	.word	s5_l1
	.word	s5_evt2
	.word	s5_evt0
	.word	s5_evt1
	.word	_x_s4_evt2
	.word	_x_s4_evt1
	.word	_x_s4_evt0
	.word	1095761920
	.word	-1074790400
	.word	s4_lambda
	.word	_x_s4_lambda
	.word	_x_s4_backoff
	.word	_x_s4_x
	.word	s4_backoff
	.word	s4_x
	.word	_x_s4_l1
	.word	_x_s4_l0
	.word	s4_l0
	.word	s4_l1
	.word	delta
	.word	s4_evt2
	.word	s4_evt0
	.word	s4_evt1
	.word	_x_s3_evt2
	.word	_x_s3_evt0
	.word	_x_s3_evt1
.L1467:
	cmp	r3, #0
	bne	.L636
.L631:
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L636
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L636
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L636
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L636:
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L637
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L637
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L638
.L637:
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L638
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L638
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L638
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L638
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L638
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L638:
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L639
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L639
	ldr	r3, .L1466+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L640
.L639:
	ldr	r3, .L1466+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1466+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L640
	ldr	r3, .L1466+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1466+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L640
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1466+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L640:
	ldr	r3, .L1466+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L641
	ldr	r3, .L1466+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L1466+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L642
.L641:
	ldr	r3, .L1466+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1466+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1466+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L642
.L643:
	ldr	r3, .L1466+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L644
	ldr	r3, .L1466+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L644
	ldr	r3, .L1466+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L642
.L644:
	ldr	r3, .L1466+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L645
	ldr	r3, .L1466+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1466+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L642
.L645:
	ldr	r3, .L1466+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L642:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L646
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L647
.L646:
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L647
.L648:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L647:
	ldr	r3, .L1466+148
	ldr	r3, [r3]	@ float
	ldr	r1, .L1466+132
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+144
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L650
	mov	r3, #0
	mov	r4, r3
.L650:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L651
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L651:
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L1466+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1466+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1466+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L1466+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L655
.L652:
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L655
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L655
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L655:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L657
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L658
.L657:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L658
.L659:
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L660
.L658:
	ldr	r3, .L1466+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1466+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L662
.L660:
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L662
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L662
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L662
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L662:
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L663
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L663
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L663
	ldr	r3, .L1466+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L664
.L663:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L664
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L664:
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L665
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L665
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L666
.L665:
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L666
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L666
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L666
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L666
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L666
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L666:
	ldr	r3, .L1466+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L670
.L669:
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L667
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L670
.L667:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L670
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L670
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L670
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L670
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L670
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L670:
	ldr	r3, .L1466+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1466+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L674
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L675
.L674:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L675
.L671:
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L675
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L675
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L675
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L675:
	ldr	r3, .L1466+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L676
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L676
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L676
	ldr	r3, .L1466+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L678
.L676:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L678
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L678
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L678
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L678:
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L679
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L679
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L679
	ldr	r3, .L1466+156
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1466+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1466+136
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L680
.L679:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L680
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L680
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L680
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L680
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L680
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L680:
	ldr	r3, .L1466+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
.L683:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L681
.L684:
	ldr	r3, .L1466+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1466+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L686
.L681:
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L686
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L686:
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
.L687:
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L688
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L688
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L688
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L688
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L688:
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1466+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1466+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L690
.L689:
	ldr	r3, .L1466+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L1466+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L690
	ldr	r3, .L1466+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L1466+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L690
	ldr	r3, .L1466+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L1466+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1466+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L690:
	ldr	r3, .L1466+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L691
	ldr	r3, .L1466+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L691
	ldr	r3, .L1466+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
.L691:
	ldr	r3, .L1466+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
	ldr	r3, .L1466+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
	ldr	r3, .L1466+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
.L693:
	ldr	r3, .L1469
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1469+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L694
	ldr	r3, .L1469+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
.L694:
	ldr	r3, .L1469
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L695
	ldr	r3, .L1469+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L695
	ldr	r3, .L1469+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
.L695:
	ldr	r3, .L1469
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L692:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L696
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L697
.L696:
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L697
.L698:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L697:
	ldr	r3, .L1469+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L1469+144
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+24
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L700
	mov	r3, #0
	mov	r4, r3
.L700:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L701
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L701:
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L702
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L702
	ldr	r3, .L1469+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L702
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1469+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1469+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L702
	ldr	r3, .L1469+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L705
.L702:
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L705
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L705
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L705:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L708
.L707:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L709
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L708
.L709:
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L710
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L710
.L708:
	ldr	r3, .L1469+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L710
	ldr	r3, .L1469+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L712
.L710:
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L712
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L712
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L712:
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L713
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L713
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L713
	ldr	r3, .L1469+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L714
.L713:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L714
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L714:
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L715
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L715
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L716
.L715:
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L716
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L716
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L716
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L716:
	ldr	r3, .L1469+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L719
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L719
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
.L719:
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L717
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
.L717:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L720:
	ldr	r3, .L1469+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L721
	ldr	r3, .L1469+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L721
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L724
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L725
.L724:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L721
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L725
.L721:
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L725
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L725
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L725:
	ldr	r3, .L1469+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L726
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L726
	ldr	r3, .L1469+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L728
.L726:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L728
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L728
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L728:
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L729
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L729
	ldr	r3, .L1469+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1469+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1469+76
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L730
.L729:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L730
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L730
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L730
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L730
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L730
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L730:
	ldr	r3, .L1469+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L733
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L734
.L733:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L731
.L734:
	ldr	r3, .L1469+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L1469+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L736
.L731:
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L736
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L736
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L736
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L736:
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L737
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L737
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L738
.L737:
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L738
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L738
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L738
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L738
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L738
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L738:
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L1469+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L740
.L739:
	ldr	r3, .L1469+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L740
	ldr	r3, .L1469+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L740
	ldr	r3, .L1469+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L740
	ldr	r3, .L1469+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L740
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L740
	ldr	r3, .L1469+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L740:
	ldr	r3, .L1469+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L741
	ldr	r3, .L1469+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L741
	ldr	r3, .L1469+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L742
.L741:
	ldr	r3, .L1469+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L743
	ldr	r3, .L1469+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L743
	ldr	r3, .L1469+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L742
.L743:
	ldr	r3, .L1469+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L1469+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L744
	ldr	r3, .L1469+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L742
.L744:
	ldr	r3, .L1469+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L745
	ldr	r3, .L1469+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L1469+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L742
.L745:
	ldr	r3, .L1469+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L742:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L746
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L747
.L746:
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L748
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L747
.L748:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L747:
	ldr	r3, .L1469+88
	ldr	r3, [r3]	@ float
	ldr	r1, .L1469+144
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+84
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L750
	mov	r3, #0
	mov	r4, r3
.L750:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L751
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L751
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L751:
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L752
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L752
	ldr	r3, .L1469+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L752
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1469+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1469+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	b	.L1470
.L1471:
	.align	2
.L1469:
	.word	_x_s3_evt2
	.word	_x_s3_evt0
	.word	_x_s3_evt1
	.word	_x_s3_l0
	.word	_x_s3_l1
	.word	_x_s3_backoff
	.word	_x_s3_lambda
	.word	_x_s3_x
	.word	s3_l0
	.word	s3_l1
	.word	s3_lambda
	.word	s3_x
	.word	s3_backoff
	.word	s3_evt2
	.word	s3_evt0
	.word	s3_evt1
	.word	_x_s2_evt2
	.word	_x_s2_evt0
	.word	_x_s2_evt1
	.word	-1074790400
	.word	s2_lambda
	.word	_x_s2_lambda
	.word	_x_s2_backoff
	.word	_x_s2_x
	.word	s2_backoff
	.word	s2_x
	.word	_x_s2_l1
	.word	_x_s2_l0
	.word	s2_l0
	.word	s2_l1
	.word	s2_evt2
	.word	s2_evt0
	.word	s2_evt1
	.word	_x_s1_evt2
	.word	_x_s1_evt1
	.word	_x_s1_evt0
	.word	1095761920
	.word	s1_x
	.word	s1_backoff
	.word	_x_s1_backoff
	.word	_x_s1_x
	.word	s1_evt2
	.word	s1_evt0
	.word	s1_evt1
	.word	s1_lambda
	.word	_x_s1_lambda
	.word	_x_s1_l0
	.word	_x_s1_l1
	.word	s1_l0
	.word	s1_l1
	.word	delta
.L1470:
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L752
	ldr	r3, .L1469+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L755
.L752:
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L755:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L757
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
.L757:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L759
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
.L759:
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L760
.L758:
	ldr	r3, .L1469+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1469+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L762
.L760:
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L762
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L762
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L762
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L762:
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L763
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L763
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L763
	ldr	r3, .L1469+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L764
.L763:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L764
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L764
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L764
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L764
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L764
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L764:
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L765
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L765
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
.L765:
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L766
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L766
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L766
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L766:
	ldr	r3, .L1469+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L767
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L769
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L769
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L770
.L769:
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L767
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L767
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L770
.L767:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L770
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L770
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L770
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L770
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L770
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L770:
	ldr	r3, .L1469+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L771
	ldr	r3, .L1469+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L771
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L774
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
.L774:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L771
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
.L771:
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L775
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L775:
	ldr	r3, .L1469+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L776
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L776
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L776
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L776
	ldr	r3, .L1469+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L778
.L776:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L778
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L778
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L778
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L778
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L778
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L778:
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L779
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L779
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L779
	ldr	r3, .L1469+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1469+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1469+76
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L780
.L779:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L780
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L780
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L780
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L780:
	ldr	r3, .L1469+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L781
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L784
.L783:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L781
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L781
.L784:
	ldr	r3, .L1469+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L781
	ldr	r3, .L1469+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L786
.L781:
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L786
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L786:
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L787
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L787
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
.L787:
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L788:
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L789
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L789
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L789
	ldr	r3, .L1469+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L790
.L789:
	ldr	r3, .L1469+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L790
	ldr	r3, .L1469+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L790
	ldr	r3, .L1469+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L790
	ldr	r3, .L1469+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L790
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L790
	ldr	r3, .L1469+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L790:
	ldr	r3, .L1469+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L791
	ldr	r3, .L1469+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
	ldr	r3, .L1469+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
.L791:
	ldr	r3, .L1469+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L793
	ldr	r3, .L1469+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L793
	ldr	r3, .L1469+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
.L793:
	ldr	r3, .L1469+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L794
	ldr	r3, .L1469+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L794
	ldr	r3, .L1469+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
.L794:
	ldr	r3, .L1469+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L795
	ldr	r3, .L1469+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L795
	ldr	r3, .L1469+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
.L795:
	ldr	r3, .L1469+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L792:
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L796
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L797
.L796:
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L798
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L797
.L798:
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L797:
	ldr	r3, .L1469+156
	ldr	r3, [r3]	@ float
	ldr	r1, .L1469+144
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+180
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L800
	mov	r3, #0
	mov	r4, r3
.L800:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+180
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L801
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L801
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L801:
	ldr	r3, .L1469+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L802
	ldr	r3, .L1469+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L802
	ldr	r3, .L1469+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+180
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L802
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1469+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1469+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L802
	ldr	r3, .L1469+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L805
.L802:
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1469+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L805
	ldr	r3, .L1469+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L805
	ldr	r3, .L1469+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L805:
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L807:
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L809
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L809:
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
.L808:
	ldr	r3, .L1469+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1469+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L812
.L810:
	ldr	r3, .L1469+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L812
	ldr	r3, .L1469+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L812
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L812
	ldr	r3, .L1469+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1469+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L812:
	ldr	r3, .L1469+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L813
	ldr	r3, .L1469+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L813
	ldr	r3, .L1469+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L813
	ldr	r3, .L1469+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1469+180
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L814
.L813:
	ldr	r3, .L1469+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L814
	ldr	r3, .L1469+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L814
	ldr	r3, .L1469+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L814
	ldr	r3, .L1469+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L814
	ldr	r3, .L1469+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L814
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L814:
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L815
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L816
.L815:
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L816
	ldr	r3, .L1472+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L816
	ldr	r3, .L1472+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L816
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L816:
	ldr	r3, .L1472+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L817
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L820
.L819:
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L817
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L817
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L820
.L817:
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L820
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L820
	ldr	r3, .L1472+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L820
	ldr	r3, .L1472+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L820
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L820
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L820:
	ldr	r3, .L1472+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1472+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L824:
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L821:
	ldr	r3, .L1472+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
	ldr	r3, .L1472+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L825
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L825
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L825:
	ldr	r3, .L1472+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L826
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L826
	ldr	r3, .L1472+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L828
.L826:
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L828
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L828
	ldr	r3, .L1472+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L828
	ldr	r3, .L1472+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L828
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L828
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L828:
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L829
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L829
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L829
	ldr	r3, .L1472+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1472+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1472+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L830
.L829:
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L830
	ldr	r3, .L1472+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1472+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L830
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L830:
	ldr	r3, .L1472+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L831
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L834
.L833:
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L831
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L831
.L834:
	ldr	r3, .L1472+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L831
	ldr	r3, .L1472+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L836
.L831:
	ldr	r3, .L1472+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L836
	ldr	r3, .L1472+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L836
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L836
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L836:
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L837
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L837
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L838
.L837:
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L838
	ldr	r3, .L1472+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1472+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L838
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L838:
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L839
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L839
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L839
	ldr	r3, .L1472+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L840
.L839:
	ldr	r3, .L1472+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L840
	ldr	r3, .L1472+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L840
	ldr	r3, .L1472+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L840
	ldr	r3, .L1472+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L840
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L840
	ldr	r3, .L1472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L840:
	ldr	r3, .L1472+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L841
	ldr	r3, .L1472+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L841
	ldr	r3, .L1472+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L842
.L841:
	ldr	r3, .L1472+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1472+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1472+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L842
.L843:
	ldr	r3, .L1472+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L844
	ldr	r3, .L1472+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L844
	ldr	r3, .L1472+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L842
.L844:
	ldr	r3, .L1472+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L845
	ldr	r3, .L1472+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L845
	ldr	r3, .L1472+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L842
.L845:
	ldr	r3, .L1472+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L842:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L846
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L847
.L846:
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L847
.L848:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L847:
	ldr	r3, .L1472+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L1472+164
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+72
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L850
	mov	r3, #0
	mov	r4, r3
.L850:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L851
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L851
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L851:
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L1472+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1472+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1472+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L1472+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L855
.L852:
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L855
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L855
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L855:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L857
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L858
.L857:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L859
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L858
.L859:
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L860
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L860
.L858:
	ldr	r3, .L1472+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L860
	ldr	r3, .L1472+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L862
.L860:
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L862
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L862
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L862
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L862:
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L863
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L863
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L863
	ldr	r3, .L1472+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L864
.L863:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L864
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L864
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L864
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L864
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L864
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L864:
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L865
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L866
.L865:
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L866
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L866
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L866
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L866
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L866
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L866:
	ldr	r3, .L1472+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L867
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L869
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L869
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L870
.L869:
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L867
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L867
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L870
.L867:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L870
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L870
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L870
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L870
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L870
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L870:
	ldr	r3, .L1472+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1472+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L874
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L875
.L874:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L871
	b	.L1473
.L1474:
	.align	2
.L1472:
	.word	s1_evt2
	.word	s1_evt0
	.word	s1_evt1
	.word	_x_s1_l1
	.word	_x_s1_l0
	.word	s1_l0
	.word	s1_l1
	.word	s1_lambda
	.word	_x_s1_lambda
	.word	_x_s1_x
	.word	s1_x
	.word	_x_s1_backoff
	.word	s1_backoff
	.word	_x_s0_evt2
	.word	_x_s0_evt0
	.word	_x_s0_evt1
	.word	-1074790400
	.word	s0_lambda
	.word	_x_s0_lambda
	.word	_x_s0_backoff
	.word	_x_s0_x
	.word	s0_backoff
	.word	s0_x
	.word	_x_s0_l1
	.word	_x_s0_l0
	.word	s0_l0
	.word	s0_l1
	.word	s0_evt2
	.word	s0_evt0
	.word	s0_evt1
	.word	_x_bus_evt2
	.word	_x_bus_evt0
	.word	_x_bus_evt1
	.word	_x_delta
	.word	delta
	.word	delta
	.word	bus_l1
	.word	bus_l0
	.word	_x_bus_l0
	.word	_x_bus_l1
	.word	bus_x
	.word	1095761920
	.word	bus_evt2
	.word	bus_evt0
	.word	bus_evt1
	.word	bus_cd_id
	.word	_x_bus_x
	.word	bus_j
	.word	_x_bus_j
.L1473:
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L875
.L871:
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L875
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L875
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L875
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L875:
	ldr	r3, .L1472+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L876
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L876
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L876
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L876
	ldr	r3, .L1472+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L878
.L876:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L878
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L878
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L878
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L878
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L878
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L878:
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L879
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L879
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L879
	ldr	r3, .L1472+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1472+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L1472+64
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L880
.L879:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L880
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L880
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L880
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L880
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L880
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L880:
	ldr	r3, .L1472+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L883
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L884
.L883:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L881
.L884:
	ldr	r3, .L1472+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1472+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L886
.L881:
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L886
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L886
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L886
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L886:
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L888
.L887:
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L888
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L888
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L888
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L888
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L888
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L888:
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L889
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L889
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L889
	ldr	r3, .L1472+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L890
.L889:
	ldr	r3, .L1472+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L890
	ldr	r3, .L1472+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L890
	ldr	r3, .L1472+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L890
	ldr	r3, .L1472+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L890
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L890
	ldr	r3, .L1472+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L890:
	ldr	r3, .L1472+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L891
	ldr	r3, .L1472+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L891
	ldr	r3, .L1472+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
.L891:
	ldr	r3, .L1472+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L893
	ldr	r3, .L1472+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L893
	ldr	r3, .L1472+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
.L893:
	ldr	r3, .L1472+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L894
	ldr	r3, .L1472+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L894
	ldr	r3, .L1472+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
.L894:
	ldr	r3, .L1472+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L895
	ldr	r3, .L1472+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L895
	ldr	r3, .L1472+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
.L895:
	ldr	r3, .L1472+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L892:
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L896
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L897
.L896:
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L897
.L898:
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L899
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L897
.L899:
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L897:
	ldr	r3, .L1472+184
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1472+164
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L900
	mov	r3, #0
	mov	r4, r3
.L900:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L901
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L901
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L901:
	ldr	r3, .L1472+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L902
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L902:
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L903
	ldr	r3, .L1472+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1472+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1472+184
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1472+188
	ldr	r2, [r3]
	ldr	r3, .L1472+192
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L195
.L903:
	ldr	r3, .L1472+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1472+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1472+184
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L905
	ldr	r3, .L1472+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L905
	ldr	r3, .L1472+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L905
	ldr	r3, .L1472+188
	ldr	r2, [r3]
	ldr	r3, .L1472+192
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L907
.L905:
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L907
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L907
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L907:
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L908
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L908
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L908
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L908
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L908
	ldr	r3, .L1472+188
	ldr	r2, [r3]
	ldr	r3, .L1472+192
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L908
	ldr	r3, .L1472+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L909
.L908:
	ldr	r3, .L1472+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L909
	ldr	r3, .L1472+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L909
	ldr	r3, .L1472+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L909
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L909:
	ldr	r3, .L1472+188
	ldr	r2, [r3]
	ldr	r3, .L1472+192
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L910
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L911
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L912
.L911:
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L913
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L912
.L913:
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L910
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L912
.L910:
	ldr	r3, .L1472+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L912
	ldr	r3, .L1472+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L912
	ldr	r3, .L1472+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L912
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L912:
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L914
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L914
	ldr	r3, .L1472+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L915
.L914:
	ldr	r3, .L1472+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L916
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L916
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L915
.L916:
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L915
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L915
	ldr	r3, .L1472+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1472+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L915:
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L917
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L917
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L917
	ldr	r3, .L1472+160
	ldr	r3, [r3]	@ float
	ldr	r1, .L1472+164
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L917
	ldr	r3, .L1472+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1472+184
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L919
.L917:
	ldr	r3, .L1472+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L919
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L919
.L920:
	ldr	r3, .L1472+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L919
	ldr	r3, .L1472+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L919
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L919
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L919:
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L921
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L921
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L921
	ldr	r3, .L1472+160
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1472+164
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L922
	mov	r3, #0
	mov	r4, r3
.L922:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L921
	ldr	r3, .L1472+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L923
.L921:
	ldr	r3, .L1472+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L923
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L924
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L924
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L923
.L924:
	ldr	r3, .L1472+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L923
	ldr	r3, .L1472+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L923
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L923
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L923:
	ldr	r3, .L1472+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1472+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1472+160
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L1472+164
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L926
	mov	r3, #0
	mov	r4, r3
.L926:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1472+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L925
	ldr	r3, .L1472+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1472+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L925
	ldr	r3, .L1472+180
	ldr	r2, [r3]
	ldr	r3, .L1472+188
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L925
	ldr	r3, .L1472+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1472+188
	ldr	r2, [r3]
	ldr	r3, .L1472+192
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L928
.L925:
	ldr	r3, .L1475
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L928
	ldr	r3, .L1475+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L928
	ldr	r3, .L1475+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L928
	ldr	r3, .L1475+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1475+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1475+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L928:
	ldr	r3, .L1475+24
	ldr	r2, [r3]
	ldr	r3, .L1475+28
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	bne	.L929
	ldr	r3, .L1475+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1475+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L929
	ldr	r3, .L1475+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1475+32
	ldr	r2, [r3]
	ldr	r3, .L1475+24
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L929
	ldr	r3, .L1475+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L929
	ldr	r3, .L1475+24
	ldr	r3, [r3]
	cmp	r3, #12
	ble	.L931
.L929:
	ldr	r3, .L1475+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1475+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L932
	ldr	r3, .L1475+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L932
	ldr	r3, .L1475+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
.L932:
	ldr	r3, .L1475
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1475+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1475+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1475+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L931:
	ldr	r3, .L1475+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L933
	ldr	r3, .L1475+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L933
	ldr	r3, .L1475+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L933
	ldr	r3, .L1475+24
	ldr	r3, [r3]
	cmp	r3, #13
	bne	.L933
	ldr	r3, .L1475+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L933
	ldr	r3, .L1475+32
	ldr	r2, [r3]
	ldr	r3, .L1475+24
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L933
	ldr	r3, .L1475+28
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L935
.L933:
	ldr	r3, .L1475+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L935
	ldr	r3, .L1475+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L936
	ldr	r3, .L1475+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L936
	ldr	r3, .L1475+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L935
.L936:
	ldr	r3, .L1475+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L935
	ldr	r3, .L1475+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L935
	ldr	r3, .L1475
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L935
	ldr	r3, .L1475+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
.L935:
	ldr	r3, .L1475+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L938
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L938
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L939
.L938:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L939:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L941
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L941
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L942
.L941:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L942:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L943
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L943
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L944
.L943:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L944:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L945
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L945
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L946
.L945:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L946:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L947
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L947
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L948
.L947:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L948:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L949
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L949
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L950
.L949:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L950:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L952
.L951:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L952:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L954
.L953:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L954:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L955
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L955
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L956
.L955:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L956:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L958
.L957:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L958:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L959
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L959
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L959:
	ldr	r3, .L1475+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L960:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L961
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L961
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L962
.L961:
	ldr	r3, .L1475+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L962:
	ldr	r3, .L1475+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L963
	ldr	r3, .L1475+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L963
	ldr	r3, .L1475+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L964
.L963:
	ldr	r3, .L1475+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L964:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L965
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L965
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L966
.L965:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L966:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L967
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L967
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L968
.L967:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L968:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L969
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L969
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L970
.L969:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L970:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L971
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L971
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L972
.L971:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L972:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L974
.L973:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L974:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L976
.L975:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L976:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L977
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L977
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L978
.L977:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L978:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L979
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L979
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L980
.L979:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L980:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L981
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L981
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L982
.L981:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L982:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L983
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L983
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L984
.L983:
	ldr	r3, .L1475+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L984:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L985
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L985
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L986
.L985:
	ldr	r3, .L1475+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L986:
	ldr	r3, .L1475+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L987
	ldr	r3, .L1475+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L987
	ldr	r3, .L1475+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L988
.L987:
	ldr	r3, .L1475+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L988:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L989
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L989
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L990
.L989:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L990:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L991
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L991
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L992
.L991:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L992:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L993
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L993
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L994
.L993:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L994:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L995
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L995
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L996
.L995:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L996:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L997
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L997
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L998
.L997:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L998:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L999
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L999
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1000
.L999:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1000:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1001
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1001
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1002
.L1001:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1002:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1004
.L1003:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1004:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1005
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1005
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1006
.L1005:
	ldr	r3, .L1475+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1006:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1007
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1007
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1008
.L1007:
	ldr	r3, .L1475+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1008:
	ldr	r3, .L1475+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1009
	b	.L1476
.L1477:
	.align	2
.L1475:
	.word	bus_l0
	.word	bus_l1
	.word	delta
	.word	bus_evt2
	.word	bus_evt0
	.word	bus_evt1
	.word	bus_j
	.word	_x_bus_j
	.word	bus_cd_id
	.word	_x_bus_x
	.word	_x_bus_l0
	.word	_x_bus_l1
	.word	_x_delta
	.word	s0_evt2
	.word	s0_evt0
	.word	s0_evt1
	.word	s1_evt2
	.word	s1_evt0
	.word	s1_evt1
	.word	s2_evt2
	.word	s2_evt0
	.word	s2_evt1
	.word	s3_evt2
	.word	s3_evt0
	.word	s3_evt1
	.word	s4_evt2
	.word	s4_evt0
	.word	s4_evt1
	.word	s5_evt2
	.word	s5_evt0
	.word	s5_evt1
	.word	s6_evt2
	.word	s6_evt0
	.word	s6_evt1
	.word	s10_evt1
	.word	s11_evt2
	.word	s11_evt0
	.word	s11_evt1
	.word	s12_evt2
	.word	s12_evt0
	.word	s12_evt1
	.word	s7_evt2
	.word	s7_evt0
	.word	s7_evt1
	.word	s13_evt2
	.word	s13_evt0
	.word	s13_evt1
	.word	s9_evt2
	.word	s9_evt0
	.word	s9_evt1
	.word	s8_evt2
	.word	s8_evt0
	.word	s8_evt1
	.word	s10_evt2
	.word	s10_evt0
.L1476:
	ldr	r3, .L1475+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1009
	ldr	r3, .L1475+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1010
.L1009:
	ldr	r3, .L1475+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1010:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1012
.L1011:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1012:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1013
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1013
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1014
.L1013:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1014:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1015
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1015
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1016
.L1015:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1016:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1017
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1017
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1018
.L1017:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1018:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1019
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1019
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1020
.L1019:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1020:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1021
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1021
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1022
.L1021:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1022:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1023
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1023
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1024
.L1023:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1024:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1025
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1025
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1026
.L1025:
	ldr	r3, .L1475+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1026:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1027
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1027
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1028
.L1027:
	ldr	r3, .L1475+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1028:
	ldr	r3, .L1475+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1029
	ldr	r3, .L1475+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1029
	ldr	r3, .L1475+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1030
.L1029:
	ldr	r3, .L1475+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1030:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1031
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1031
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1032
.L1031:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1032:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1033
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1033
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1034
.L1033:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1034:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1035
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1035
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1036
.L1035:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1036:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1037
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1037
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1038
.L1037:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1038:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1039
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1039
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1040
.L1039:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1040:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1041
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1041
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1042
.L1041:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1042:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1043
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1043
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1044
.L1043:
	ldr	r3, .L1475+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1044:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1045
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1045
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1046
.L1045:
	ldr	r3, .L1475+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1046:
	ldr	r3, .L1475+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1047
	ldr	r3, .L1475+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1047
	ldr	r3, .L1475+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1048
.L1047:
	ldr	r3, .L1475+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1048:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1049
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1049
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1050
.L1049:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1050:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1051
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1051
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1052
.L1051:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1052:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1053
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1053
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1054
.L1053:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1054:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1055
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1055
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1056
.L1055:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1056:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1057
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1057
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1058
.L1057:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1058:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1059
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1059
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1060
.L1059:
	ldr	r3, .L1475+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1060:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1061
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1061
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1062
.L1061:
	ldr	r3, .L1475+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1062:
	ldr	r3, .L1475+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1063
	ldr	r3, .L1475+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1063
	ldr	r3, .L1475+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1064
.L1063:
	ldr	r3, .L1475+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1064:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1065
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1065
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1066
.L1065:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1066:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1067
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1067
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1068
.L1067:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1068:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1069
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1069
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1070
.L1069:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1070:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1071
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1071
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1072
.L1071:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1072:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1073
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1073
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1074
.L1073:
	ldr	r3, .L1475+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1074:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1075
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1075
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1076
.L1075:
	ldr	r3, .L1475+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1076:
	ldr	r3, .L1475+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1077
	ldr	r3, .L1475+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1077
	ldr	r3, .L1475+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1078
.L1077:
	ldr	r3, .L1475+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1078:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1079
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1079
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1080
.L1079:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1080:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1081
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1081
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1082
.L1081:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1082:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1083
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1083
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1084
.L1083:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1084:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1085
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1085
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1086
.L1085:
	ldr	r3, .L1475+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1086:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1087
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1087
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1088
.L1087:
	ldr	r3, .L1475+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1088:
	ldr	r3, .L1475+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1089
	ldr	r3, .L1475+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1089
	ldr	r3, .L1475+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1090
.L1089:
	ldr	r3, .L1475+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1090:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1091
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1091
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1092
.L1091:
	ldr	r3, .L1475+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1092:
	ldr	r3, .L1475+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1093
	ldr	r3, .L1475+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1093
	ldr	r3, .L1475+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1094
.L1093:
	ldr	r3, .L1475+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1475+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1094:
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1095
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1095
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1096
.L1095:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1096:
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1097
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1097
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1098
.L1097:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1098:
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1099
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1099
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1100
.L1099:
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1100:
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1101
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1101
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1102
.L1101:
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1102:
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1103
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1103
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1104
.L1103:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1104:
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1106
.L1105:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1106:
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1107
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1107
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1108
.L1107:
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1108:
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1109
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1109
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1110
.L1109:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1110:
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1111
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1111
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1112
.L1111:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1112:
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1113
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1113
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1114
.L1113:
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1114:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1115
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1115
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1116
.L1115:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1116:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1117
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1117
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1118
.L1117:
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
.L1118:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1119
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1119
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1120
.L1119:
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1120
.L940:
	ldr	r3, .L1478+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L195
.L1120:
	ldr	r3, .L1478+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1122
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1478+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L1122:
	ldr	r3, .L1478+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1123
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1124
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1124
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1124
	mov	r3, #1
	b	.L1125
.L1124:
	mov	r3, #0
.L1125:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1126
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1126
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1126:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1128
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1128
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1128:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1129
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1129
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1129:
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1130
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1130
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1130:
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1131
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1131
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1131:
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1132
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1132
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1132:
	ldr	r3, .L1478+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1133
	ldr	r3, .L1478+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1133
	ldr	r3, .L1478+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1133:
	ldr	r3, .L1478+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1134
	ldr	r3, .L1478+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1134
	ldr	r3, .L1478+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1134:
	ldr	r3, .L1478+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1478+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1135
	ldr	r3, .L1478+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1135:
	ldr	r3, .L1478+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1136
	ldr	r3, .L1478+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1136
	ldr	r3, .L1478+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1136:
	ldr	r3, .L1478+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1137
	ldr	r3, .L1478+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1137
	ldr	r3, .L1478+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1137:
	ldr	r3, .L1478+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1138
	ldr	r3, .L1478+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1478+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1138:
	ldr	r3, .L1478
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1139
	ldr	r3, .L1478+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1139
	ldr	r3, .L1478+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
.L1139:
	ldr	r3, .L1478+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1140
	ldr	r3, .L1478+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1140
	ldr	r3, .L1478+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1140
.L1127:
	mov	r3, #1
	b	.L1141
.L1140:
	mov	r3, #0
.L1141:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1142
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1142
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1142
	mov	r3, #1
	b	.L1143
.L1142:
	mov	r3, #0
.L1143:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1144
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1144
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1144:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1146
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1146
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1146:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1147
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1147
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1147:
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1148
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1148
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1148:
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1149
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1149
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1149:
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1150
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1150
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1150:
	ldr	r3, .L1478+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1151
	ldr	r3, .L1478+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1151
	ldr	r3, .L1478+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1151:
	ldr	r3, .L1478+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1152
	ldr	r3, .L1478+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1152
	ldr	r3, .L1478+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1152:
	ldr	r3, .L1478+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1153
	ldr	r3, .L1478+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1153
	ldr	r3, .L1478+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1153:
	ldr	r3, .L1478+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1154
	ldr	r3, .L1478+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1154
	ldr	r3, .L1478+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1154:
	ldr	r3, .L1478+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1155
	ldr	r3, .L1478+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1155
	ldr	r3, .L1478+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1155:
	ldr	r3, .L1478+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1156
	ldr	r3, .L1478+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1156
	ldr	r3, .L1478+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1156:
	ldr	r3, .L1478
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1157
	ldr	r3, .L1478+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1157
	ldr	r3, .L1478+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
.L1157:
	ldr	r3, .L1478+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1158
	ldr	r3, .L1478+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
	ldr	r3, .L1478+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1158
.L1145:
	mov	r3, #1
	b	.L1159
.L1158:
	mov	r3, #0
.L1159:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1160
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1160
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1160
	mov	r3, #1
	b	.L1161
.L1479:
	.align	2
.L1478:
	.word	s0_evt2
	.word	s0_evt0
	.word	s0_evt1
	.word	s1_evt2
	.word	s1_evt0
	.word	s1_evt1
	.word	s2_evt2
	.word	s2_evt0
	.word	s2_evt1
	.word	s3_evt2
	.word	s3_evt0
	.word	s3_evt1
	.word	s4_evt2
	.word	s4_evt0
	.word	s4_evt1
	.word	s5_evt2
	.word	s5_evt0
	.word	s5_evt1
	.word	s6_evt2
	.word	s6_evt0
	.word	s6_evt1
	.word	s7_evt2
	.word	s7_evt0
	.word	s7_evt1
	.word	s8_evt2
	.word	s8_evt0
	.word	s8_evt1
	.word	s9_evt2
	.word	s9_evt0
	.word	s9_evt1
	.word	s10_evt2
	.word	s10_evt0
	.word	s10_evt1
	.word	s11_evt2
	.word	s11_evt0
	.word	s11_evt1
	.word	s12_evt2
	.word	s12_evt0
	.word	s12_evt1
	.word	s13_evt2
	.word	s13_evt0
	.word	s13_evt1
	.word	bus_evt2
	.word	bus_evt0
	.word	bus_evt1
	.word	bus_cd_id
	.word	delta
	.word	_x__diverge_delta
	.word	_diverge_delta
.L1160:
	mov	r3, #0
.L1161:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1162
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1162
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1162:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1164
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1164
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1164:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1165
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1165
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1165:
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1166:
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1167
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1167
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1167:
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1168
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1168
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1168:
	ldr	r3, .L1478+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1169
	ldr	r3, .L1478+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1169
	ldr	r3, .L1478+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1169:
	ldr	r3, .L1478+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1478+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1478+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1170:
	ldr	r3, .L1478+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1171
	ldr	r3, .L1478+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1171
	ldr	r3, .L1478+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1171:
	ldr	r3, .L1478+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1172
	ldr	r3, .L1478+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1172
	ldr	r3, .L1478+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1172:
	ldr	r3, .L1478+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1173
	ldr	r3, .L1478+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1173
	ldr	r3, .L1478+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1173:
	ldr	r3, .L1478+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1478+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1478+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1174:
	ldr	r3, .L1478
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1175
	ldr	r3, .L1478+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1175
	ldr	r3, .L1478+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
.L1175:
	ldr	r3, .L1478+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1176
	ldr	r3, .L1478+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1176
	ldr	r3, .L1478+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1176
.L1163:
	mov	r3, #1
	b	.L1177
.L1176:
	mov	r3, #0
.L1177:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1178
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1178
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1178
	mov	r3, #1
	b	.L1179
.L1178:
	mov	r3, #0
.L1179:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1180
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1180
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1180:
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1182
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1182
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1182:
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1183
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1183
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1183:
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1184
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1184
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1184:
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1185
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1185:
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1186
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1186
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1186:
	ldr	r3, .L1478+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1187
	ldr	r3, .L1478+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1187
	ldr	r3, .L1478+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1187:
	ldr	r3, .L1478+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1188
	ldr	r3, .L1478+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1188
	ldr	r3, .L1478+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1188:
	ldr	r3, .L1478+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1189
	ldr	r3, .L1478+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1189
	ldr	r3, .L1478+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1189:
	ldr	r3, .L1478+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1190
	ldr	r3, .L1478+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1190
	ldr	r3, .L1478+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1190:
	ldr	r3, .L1478+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1191
	ldr	r3, .L1478+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1191
	ldr	r3, .L1478+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1191:
	ldr	r3, .L1478+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1192
	ldr	r3, .L1478+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1192
	ldr	r3, .L1478+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1192:
	ldr	r3, .L1478
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1193
	ldr	r3, .L1478+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1193
	ldr	r3, .L1478+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
.L1193:
	ldr	r3, .L1478+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1194
	ldr	r3, .L1478+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1194
	ldr	r3, .L1478+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1194
.L1181:
	mov	r3, #1
	b	.L1195
.L1194:
	mov	r3, #0
.L1195:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
.L1123:
	ldr	r3, .L1478+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1196
	ldr	r3, .L1478
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1197
	ldr	r3, .L1478+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1197
	ldr	r3, .L1478+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1197
	mov	r3, #1
	b	.L1198
.L1197:
	mov	r3, #0
.L1198:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1199
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1199
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1199
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L1199
	mov	r3, #1
	b	.L1200
.L1199:
	mov	r3, #0
.L1200:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1201
	ldr	r3, .L1478+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1201
	ldr	r3, .L1478+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1201
	mov	r3, #1
	b	.L1202
.L1201:
	mov	r3, #0
.L1202:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1203
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1203
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1203
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L1203
	mov	r3, #1
	b	.L1204
.L1203:
	mov	r3, #0
.L1204:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1205
	ldr	r3, .L1478+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1205
	ldr	r3, .L1478+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1205
	mov	r3, #1
	b	.L1206
.L1205:
	mov	r3, #0
.L1206:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1207
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1207
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1207
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L1207
	mov	r3, #1
	b	.L1208
.L1207:
	mov	r3, #0
.L1208:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1209
	ldr	r3, .L1478+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1209
	ldr	r3, .L1478+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1209
	mov	r3, #1
	b	.L1210
.L1209:
	mov	r3, #0
.L1210:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1211
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1211
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1211
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #3
	bne	.L1211
	mov	r3, #1
	b	.L1212
.L1211:
	mov	r3, #0
.L1212:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1213
	ldr	r3, .L1478+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1213
	ldr	r3, .L1478+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1213
	mov	r3, #1
	b	.L1214
.L1213:
	mov	r3, #0
.L1214:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1215
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1215
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1215
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #4
	bne	.L1215
	mov	r3, #1
	b	.L1216
.L1215:
	mov	r3, #0
.L1216:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1217
	ldr	r3, .L1478+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1217
	ldr	r3, .L1478+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1217
	mov	r3, #1
	b	.L1218
.L1217:
	mov	r3, #0
.L1218:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1219
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1219
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1219
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #5
	bne	.L1219
	mov	r3, #1
	b	.L1220
.L1219:
	mov	r3, #0
.L1220:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1221
	ldr	r3, .L1478+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1221
	ldr	r3, .L1478+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1221
	mov	r3, #1
	b	.L1222
.L1221:
	mov	r3, #0
.L1222:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1223
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1223
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1223
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #6
	bne	.L1223
	mov	r3, #1
	b	.L1224
.L1223:
	mov	r3, #0
.L1224:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1225
	ldr	r3, .L1478+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1225
	ldr	r3, .L1478+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1225
	mov	r3, #1
	b	.L1226
.L1225:
	mov	r3, #0
.L1226:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1227
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1227
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1227
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #7
	bne	.L1227
	mov	r3, #1
	b	.L1228
.L1227:
	mov	r3, #0
.L1228:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1229
	ldr	r3, .L1478+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1229
	ldr	r3, .L1478+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1229
	mov	r3, #1
	b	.L1230
.L1229:
	mov	r3, #0
.L1230:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1231
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1231
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1231
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #8
	bne	.L1231
	mov	r3, #1
	b	.L1232
.L1231:
	mov	r3, #0
.L1232:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1233
	ldr	r3, .L1478+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1233
	ldr	r3, .L1478+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1233
	mov	r3, #1
	b	.L1234
.L1233:
	mov	r3, #0
.L1234:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1235
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1235
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1235
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #9
	bne	.L1235
	mov	r3, #1
	b	.L1236
.L1235:
	mov	r3, #0
.L1236:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1237
	ldr	r3, .L1478+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1237
	ldr	r3, .L1478+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1237
	mov	r3, #1
	b	.L1238
.L1237:
	mov	r3, #0
.L1238:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1239
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1239
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1239
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #10
	bne	.L1239
	mov	r3, #1
	b	.L1240
.L1239:
	mov	r3, #0
.L1240:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1241
	ldr	r3, .L1478+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1241
	ldr	r3, .L1478+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1241
	mov	r3, #1
	b	.L1242
.L1241:
	mov	r3, #0
.L1242:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1243
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1243
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1243
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #11
	bne	.L1243
	mov	r3, #1
	b	.L1244
.L1243:
	mov	r3, #0
.L1244:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1245
	ldr	r3, .L1478+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1245
	ldr	r3, .L1478+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1245
	mov	r3, #1
	b	.L1246
.L1245:
	mov	r3, #0
.L1246:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1247
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1247
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1247
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #12
	bne	.L1247
	mov	r3, #1
	b	.L1248
.L1247:
	mov	r3, #0
.L1248:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1478+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1249
	ldr	r3, .L1478+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1249
	ldr	r3, .L1478+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1249
	mov	r3, #1
	b	.L1250
.L1249:
	mov	r3, #0
.L1250:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L1478+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1251
	ldr	r3, .L1478+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1251
	ldr	r3, .L1478+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1251
	ldr	r3, .L1478+180
	ldr	r3, [r3]
	cmp	r3, #13
	bne	.L1251
	mov	r3, #1
	b	.L1252
.L1251:
	mov	r3, #0
.L1252:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
.L1196:
	ldr	r3, .L1478+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L1478+188
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1253
	ldr	r3, .L1478+192
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1254
	mov	r3, #0
	mov	r4, r3
.L1254:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L195
.L1253:
	ldr	r3, .L1480
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1255
	ldr	r3, .L1480+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1480
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1480+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L195
.L1255:
	mov	r3, #1
	b	.L1257
.L195:
	mov	r3, #0
.L1257:
	str	r3, [fp, #-24]
	ldr	r3, .L1480+12
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+16
	strb	r2, [r3]
	ldr	r3, .L1480+20
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+24
	strb	r2, [r3]
	ldr	r3, .L1480+28
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+32
	strb	r2, [r3]
	ldr	r3, .L1480+36
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+40
	strb	r2, [r3]
	ldr	r3, .L1480+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+48
	str	r3, [r2]	@ float
	ldr	r3, .L1480+52
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+56
	strb	r2, [r3]
	ldr	r3, .L1480+60
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+64
	strb	r2, [r3]
	ldr	r3, .L1480+68
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+72
	strb	r2, [r3]
	ldr	r3, .L1480+76
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+80
	strb	r2, [r3]
	ldr	r3, .L1480+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+88
	str	r3, [r2]	@ float
	ldr	r3, .L1480+92
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+96
	strb	r2, [r3]
	ldr	r3, .L1480+100
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+104
	strb	r2, [r3]
	ldr	r3, .L1480+108
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+112
	strb	r2, [r3]
	ldr	r3, .L1480+116
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+120
	strb	r2, [r3]
	ldr	r3, .L1480+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+128
	str	r3, [r2]	@ float
	ldr	r3, .L1480+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+136
	str	r3, [r2]	@ float
	ldr	r3, .L1480+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+144
	str	r3, [r2]	@ float
	ldr	r3, .L1480+148
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+152
	strb	r2, [r3]
	ldr	r3, .L1480+156
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+160
	strb	r2, [r3]
	ldr	r3, .L1480+164
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+168
	strb	r2, [r3]
	ldr	r3, .L1480+172
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+176
	strb	r2, [r3]
	ldr	r3, .L1480+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+184
	str	r3, [r2]	@ float
	ldr	r3, .L1480+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+192
	str	r3, [r2]	@ float
	ldr	r3, .L1480+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+200
	str	r3, [r2]	@ float
	ldr	r3, .L1480+204
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+208
	strb	r2, [r3]
	ldr	r3, .L1480+212
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+216
	strb	r2, [r3]
	ldr	r3, .L1480+220
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+224
	strb	r2, [r3]
	ldr	r3, .L1480+228
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+232
	strb	r2, [r3]
	ldr	r3, .L1480+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+240
	str	r3, [r2]	@ float
	ldr	r3, .L1480+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+248
	str	r3, [r2]	@ float
	ldr	r3, .L1480+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+256
	str	r3, [r2]	@ float
	ldr	r3, .L1480+260
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+264
	strb	r2, [r3]
	ldr	r3, .L1480+268
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+272
	strb	r2, [r3]
	ldr	r3, .L1480+276
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+280
	strb	r2, [r3]
	ldr	r3, .L1480+284
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+288
	strb	r2, [r3]
	ldr	r3, .L1480+292
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+296
	strb	r2, [r3]
	ldr	r3, .L1480+300
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+304
	str	r3, [r2]	@ float
	ldr	r3, .L1480+308
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+312
	str	r3, [r2]	@ float
	ldr	r3, .L1480+316
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+320
	str	r3, [r2]	@ float
	ldr	r3, .L1480+324
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+328
	strb	r2, [r3]
	ldr	r3, .L1480+332
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+336
	strb	r2, [r3]
	ldr	r3, .L1480+340
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+344
	strb	r2, [r3]
	ldr	r3, .L1480+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480
	str	r3, [r2]	@ float
	ldr	r3, .L1480+348
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+352
	strb	r2, [r3]
	ldr	r3, .L1480+356
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+360
	strb	r2, [r3]
	ldr	r3, .L1480+364
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+368
	str	r3, [r2]	@ float
	ldr	r3, .L1480+372
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+376
	str	r3, [r2]	@ float
	ldr	r3, .L1480+380
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+384
	str	r3, [r2]	@ float
	ldr	r3, .L1480+388
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+392
	strb	r2, [r3]
	ldr	r3, .L1480+396
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+400
	strb	r2, [r3]
	ldr	r3, .L1480+404
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+408
	strb	r2, [r3]
	ldr	r3, .L1480+412
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+416
	strb	r2, [r3]
	ldr	r3, .L1480+420
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+424
	strb	r2, [r3]
	ldr	r3, .L1480+428
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+432
	str	r3, [r2]	@ float
	ldr	r3, .L1480+436
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+440
	str	r3, [r2]	@ float
	ldr	r3, .L1480+444
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+448
	strb	r2, [r3]
	ldr	r3, .L1480+452
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+456
	strb	r2, [r3]
	ldr	r3, .L1480+460
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+464
	strb	r2, [r3]
	ldr	r3, .L1480+468
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+472
	strb	r2, [r3]
	ldr	r3, .L1480+476
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+480
	str	r3, [r2]	@ float
	ldr	r3, .L1480+484
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+488
	strb	r2, [r3]
	ldr	r3, .L1480+492
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+496
	str	r3, [r2]	@ float
	ldr	r3, .L1480+500
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+504
	strb	r2, [r3]
	ldr	r3, .L1480+508
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+512
	str	r3, [r2]	@ float
	ldr	r3, .L1480+516
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+520
	str	r3, [r2]	@ float
	ldr	r3, .L1480+524
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+528
	str	r3, [r2]	@ float
	ldr	r3, .L1480+532
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+536
	strb	r2, [r3]
	ldr	r3, .L1480+540
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+544
	strb	r2, [r3]
	ldr	r3, .L1480+548
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+552
	str	r3, [r2]	@ float
	ldr	r3, .L1480+556
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+560
	strb	r2, [r3]
	ldr	r3, .L1480+564
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+568
	strb	r2, [r3]
	ldr	r3, .L1480+572
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+576
	str	r3, [r2]	@ float
	ldr	r3, .L1480+580
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+584
	strb	r2, [r3]
	ldr	r3, .L1480+588
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+592
	strb	r2, [r3]
	ldr	r3, .L1480+596
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+600
	strb	r2, [r3]
	ldr	r3, .L1480+604
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+608
	str	r3, [r2]	@ float
	ldr	r3, .L1480+612
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+616
	strb	r2, [r3]
	ldr	r3, .L1480+620
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+624
	str	r3, [r2]	@ float
	ldr	r3, .L1480+628
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+632
	str	r3, [r2]	@ float
	ldr	r3, .L1480+636
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+640
	str	r3, [r2]	@ float
	ldr	r3, .L1480+644
	ldr	r3, [r3]
	ldr	r2, .L1480+648
	str	r3, [r2]
	ldr	r3, .L1480+652
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+656
	strb	r2, [r3]
	ldr	r3, .L1480+660
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+664
	strb	r2, [r3]
	ldr	r3, .L1480+668
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+672
	str	r3, [r2]	@ float
	ldr	r3, .L1480+676
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+680
	str	r3, [r2]	@ float
	ldr	r3, .L1480+684
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+688
	str	r3, [r2]	@ float
	ldr	r3, .L1480+692
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+696
	strb	r2, [r3]
	ldr	r3, .L1480+700
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+704
	str	r3, [r2]	@ float
	ldr	r3, .L1480+708
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+4
	str	r3, [r2]	@ float
	ldr	r3, .L1480+712
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+716
	strb	r2, [r3]
	ldr	r3, .L1480+720
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+724
	strb	r2, [r3]
	ldr	r3, .L1480+728
	ldr	r3, [r3]
	ldr	r2, .L1480+732
	str	r3, [r2]
	ldr	r3, .L1480+736
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+740
	str	r3, [r2]	@ float
	ldr	r3, .L1480+744
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+748
	str	r3, [r2]	@ float
	ldr	r3, .L1480+752
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+756
	str	r3, [r2]	@ float
	ldr	r3, .L1480+760
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+764
	str	r3, [r2]	@ float
	ldr	r3, .L1480+768
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+772
	strb	r2, [r3]
	ldr	r3, .L1480+776
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+780
	strb	r2, [r3]
	ldr	r3, .L1480+784
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+788
	strb	r2, [r3]
	ldr	r3, .L1480+792
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+796
	str	r3, [r2]	@ float
	ldr	r3, .L1480+800
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+804
	strb	r2, [r3]
	ldr	r3, .L1480+808
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+812
	strb	r2, [r3]
	ldr	r3, .L1480+816
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+820
	strb	r2, [r3]
	ldr	r3, .L1480+824
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+828
	strb	r2, [r3]
	ldr	r3, .L1480+832
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+836
	strb	r2, [r3]
	ldr	r3, .L1480+840
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+844
	strb	r2, [r3]
	ldr	r3, .L1480+848
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+852
	strb	r2, [r3]
	ldr	r3, .L1480+856
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+860
	str	r3, [r2]	@ float
	ldr	r3, .L1480+864
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+868
	str	r3, [r2]	@ float
	ldr	r3, .L1480+872
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+876
	str	r3, [r2]	@ float
	ldr	r3, .L1480+880
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+884
	strb	r2, [r3]
	ldr	r3, .L1480+888
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+892
	strb	r2, [r3]
	ldr	r3, .L1480+896
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+900
	strb	r2, [r3]
	ldr	r3, .L1480+904
	ldr	r3, [r3]	@ float
	ldr	r2, .L1480+908
	str	r3, [r2]	@ float
	ldr	r3, .L1480+912
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+916
	strb	r2, [r3]
	ldr	r3, .L1480+920
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+924
	strb	r2, [r3]
	ldr	r3, .L1480+928
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+932
	strb	r2, [r3]
	ldr	r3, .L1480+936
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+940
	strb	r2, [r3]
	ldr	r3, .L1480+944
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+948
	strb	r2, [r3]
	ldr	r3, .L1480+952
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+956
	strb	r2, [r3]
	ldr	r3, .L1480+960
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+964
	strb	r2, [r3]
	ldr	r3, .L1480+968
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1480+972
	strb	r2, [r3]
.L189:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L1258
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
.L1481:
	.align	2
.L1480:
	.word	_diverge_delta
	.word	delta
	.word	_x__diverge_delta
	.word	_x_s13_l0
	.word	s13_l0
	.word	_x_s13_evt2
	.word	s13_evt2
	.word	_x_s13_evt1
	.word	s13_evt1
	.word	_x_s13_evt0
	.word	s13_evt0
	.word	_x_s13_backoff
	.word	s13_backoff
	.word	_x_s12_l0
	.word	s12_l0
	.word	_x_s12_evt2
	.word	s12_evt2
	.word	_x_s12_evt1
	.word	s12_evt1
	.word	_x_s12_evt0
	.word	s12_evt0
	.word	_x_s12_backoff
	.word	s12_backoff
	.word	_x_s11_l0
	.word	s11_l0
	.word	_x_s11_evt2
	.word	s11_evt2
	.word	_x_s11_evt1
	.word	s11_evt1
	.word	_x_s11_evt0
	.word	s11_evt0
	.word	_x_s11_lambda
	.word	s11_lambda
	.word	_x_s11_backoff
	.word	s11_backoff
	.word	_x_s11_x
	.word	s11_x
	.word	_x_s10_l0
	.word	s10_l0
	.word	_x_s10_evt2
	.word	s10_evt2
	.word	_x_s10_evt1
	.word	s10_evt1
	.word	_x_s10_evt0
	.word	s10_evt0
	.word	_x_s10_lambda
	.word	s10_lambda
	.word	_x_s10_backoff
	.word	s10_backoff
	.word	_x_s10_x
	.word	s10_x
	.word	_x_s9_l0
	.word	s9_l0
	.word	_x_s9_evt2
	.word	s9_evt2
	.word	_x_s9_evt1
	.word	s9_evt1
	.word	_x_s9_evt0
	.word	s9_evt0
	.word	_x_s9_lambda
	.word	s9_lambda
	.word	_x_s9_backoff
	.word	s9_backoff
	.word	_x_s9_x
	.word	s9_x
	.word	_x_s8_l1
	.word	s8_l1
	.word	_x_s8_l0
	.word	s8_l0
	.word	_x_s8_evt2
	.word	s8_evt2
	.word	_x_s8_evt1
	.word	s8_evt1
	.word	_x_s8_evt0
	.word	s8_evt0
	.word	_x_s8_lambda
	.word	s8_lambda
	.word	_x_s8_backoff
	.word	s8_backoff
	.word	_x_s8_x
	.word	s8_x
	.word	_x_s7_l1
	.word	s7_l1
	.word	_x_s7_l0
	.word	s7_l0
	.word	_x_s7_evt2
	.word	s7_evt2
	.word	_x_s7_evt1
	.word	s7_evt1
	.word	_x_s7_evt0
	.word	s7_evt0
	.word	_x_s7_lambda
	.word	s7_lambda
	.word	_x_s7_backoff
	.word	s7_backoff
	.word	_x_s7_x
	.word	s7_x
	.word	_x_s6_l1
	.word	s6_l1
	.word	_x_s6_l0
	.word	s6_l0
	.word	_x_s6_evt2
	.word	s6_evt2
	.word	_x_s6_evt1
	.word	s6_evt1
	.word	_x_s6_evt0
	.word	s6_evt0
	.word	_x_s6_lambda
	.word	s6_lambda
	.word	_x_s2_x
	.word	s2_x
	.word	_x_s1_l1
	.word	s1_l1
	.word	_x_s4_evt2
	.word	s4_evt2
	.word	_x_s1_l0
	.word	s1_l0
	.word	_x_s4_evt1
	.word	s4_evt1
	.word	_x_s13_lambda
	.word	s13_lambda
	.word	_x_s1_evt2
	.word	s1_evt2
	.word	_x_s13_x
	.word	s13_x
	.word	_x_s1_evt1
	.word	s1_evt1
	.word	_x_s1_backoff
	.word	s1_backoff
	.word	_x_s6_x
	.word	s6_x
	.word	_x_s2_backoff
	.word	s2_backoff
	.word	_x_s0_l1
	.word	s0_l1
	.word	_x_s3_evt2
	.word	s3_evt2
	.word	_x_s2_lambda
	.word	s2_lambda
	.word	_x_s0_l0
	.word	s0_l0
	.word	_x_s3_evt1
	.word	s3_evt1
	.word	_x_s12_lambda
	.word	s12_lambda
	.word	_x_s0_evt2
	.word	s0_evt2
	.word	_x_bus_evt0
	.word	bus_evt0
	.word	_x_s5_evt0
	.word	s5_evt0
	.word	_x_s12_x
	.word	s12_x
	.word	_x_s0_evt1
	.word	s0_evt1
	.word	_x_s4_backoff
	.word	s4_backoff
	.word	_x_s1_x
	.word	s1_x
	.word	_x_s5_backoff
	.word	s5_backoff
	.word	_x_bus_j
	.word	bus_j
	.word	_x_s11_l1
	.word	s11_l1
	.word	_x_s2_evt0
	.word	s2_evt0
	.word	_x_s0_x
	.word	s0_x
	.word	_x_s1_lambda
	.word	s1_lambda
	.word	_x_bus_x
	.word	bus_x
	.word	_x_s2_evt1
	.word	s2_evt1
	.word	_x_s6_backoff
	.word	s6_backoff
	.word	_x_delta
	.word	_x_s10_l1
	.word	s10_l1
	.word	_x_s1_evt0
	.word	s1_evt0
	.word	_x_bus_cd_id
	.word	bus_cd_id
	.word	_x_s5_lambda
	.word	s5_lambda
	.word	_x_s0_lambda
	.word	s0_lambda
	.word	_x_s0_backoff
	.word	s0_backoff
	.word	_x_s5_x
	.word	s5_x
	.word	_x_s3_l0
	.word	s3_l0
	.word	_x_s9_l1
	.word	s9_l1
	.word	_x_s0_evt0
	.word	s0_evt0
	.word	_x_s4_lambda
	.word	s4_lambda
	.word	_x_s2_evt2
	.word	s2_evt2
	.word	_x_s2_l0
	.word	s2_l0
	.word	_x_bus_evt1
	.word	bus_evt1
	.word	_x_s5_evt1
	.word	s5_evt1
	.word	_x_s2_l1
	.word	s2_l1
	.word	_x_bus_evt2
	.word	bus_evt2
	.word	_x_s5_evt2
	.word	s5_evt2
	.word	_x_s3_x
	.word	s3_x
	.word	_x_s3_backoff
	.word	s3_backoff
	.word	_x_s3_lambda
	.word	s3_lambda
	.word	_x_s12_l1
	.word	s12_l1
	.word	_x_s3_evt0
	.word	s3_evt0
	.word	_x_s3_l1
	.word	s3_l1
	.word	_x_s4_x
	.word	s4_x
	.word	_x_s13_l1
	.word	s13_l1
	.word	_x_s4_evt0
	.word	s4_evt0
	.word	_x_s4_l0
	.word	s4_l0
	.word	_x_s4_l1
	.word	s4_l1
	.word	_x_bus_l0
	.word	bus_l0
	.word	_x_s5_l0
	.word	s5_l0
	.word	_x_bus_l1
	.word	bus_l1
	.word	_x_s5_l1
	.word	s5_l1
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
