	.file	"663963.c"
	.intel_syntax noprefix
	.text
	.globl	CS_BITS
	.bss
	.align 4
	.type	CS_BITS, @object
	.size	CS_BITS, 4
CS_BITS:
	.zero	4
	.globl	AGEX_CS_BITS
	.align 4
	.type	AGEX_CS_BITS, @object
	.size	AGEX_CS_BITS, 4
AGEX_CS_BITS:
	.zero	4
	.globl	MEM_CS_BITS
	.align 4
	.type	MEM_CS_BITS, @object
	.size	MEM_CS_BITS, 4
MEM_CS_BITS:
	.zero	4
	.globl	SR_CS_BITS
	.align 4
	.type	SR_CS_BITS, @object
	.size	SR_CS_BITS, 4
SR_CS_BITS:
	.zero	4
	.text
	.globl	Get_SR1_NEEDED
	.type	Get_SR1_NEEDED, @function
Get_SR1_NEEDED:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	Get_SR1_NEEDED, .-Get_SR1_NEEDED
	.globl	Get_SR2_NEEDED
	.type	Get_SR2_NEEDED, @function
Get_SR2_NEEDED:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	Get_SR2_NEEDED, .-Get_SR2_NEEDED
	.globl	Get_DRMUX
	.type	Get_DRMUX, @function
Get_DRMUX:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 8[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	Get_DRMUX, .-Get_DRMUX
	.globl	Get_DE_BR_OP
	.type	Get_DE_BR_OP, @function
Get_DE_BR_OP:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 48[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	Get_DE_BR_OP, .-Get_DE_BR_OP
	.globl	Get_ADDR1MUX
	.type	Get_ADDR1MUX, @function
Get_ADDR1MUX:
.LFB10:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE10:
	.size	Get_ADDR1MUX, .-Get_ADDR1MUX
	.globl	Get_ADDR2MUX
	.type	Get_ADDR2MUX, @function
Get_ADDR2MUX:
.LFB11:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 4
	mov	eax, DWORD PTR [rax]
	lea	edx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 8
	mov	eax, DWORD PTR [rax]
	add	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE11:
	.size	Get_ADDR2MUX, .-Get_ADDR2MUX
	.globl	Get_LSHF1
	.type	Get_LSHF1, @function
Get_LSHF1:
.LFB12:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 12[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE12:
	.size	Get_LSHF1, .-Get_LSHF1
	.globl	Get_ADDRESSMUX
	.type	Get_ADDRESSMUX, @function
Get_ADDRESSMUX:
.LFB13:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 16[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE13:
	.size	Get_ADDRESSMUX, .-Get_ADDRESSMUX
	.globl	Get_SR2MUX
	.type	Get_SR2MUX, @function
Get_SR2MUX:
.LFB14:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 20[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE14:
	.size	Get_SR2MUX, .-Get_SR2MUX
	.globl	Get_ALUK
	.type	Get_ALUK, @function
Get_ALUK:
.LFB15:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 24
	mov	eax, DWORD PTR [rax]
	lea	edx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 28
	mov	eax, DWORD PTR [rax]
	add	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE15:
	.size	Get_ALUK, .-Get_ALUK
	.globl	Get_ALU_RESULTMUX
	.type	Get_ALU_RESULTMUX, @function
Get_ALU_RESULTMUX:
.LFB16:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 32[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE16:
	.size	Get_ALU_RESULTMUX, .-Get_ALU_RESULTMUX
	.globl	Get_BR_OP
	.type	Get_BR_OP, @function
Get_BR_OP:
.LFB17:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE17:
	.size	Get_BR_OP, .-Get_BR_OP
	.globl	Get_UNCOND_OP
	.type	Get_UNCOND_OP, @function
Get_UNCOND_OP:
.LFB18:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE18:
	.size	Get_UNCOND_OP, .-Get_UNCOND_OP
	.globl	Get_TRAP_OP
	.type	Get_TRAP_OP, @function
Get_TRAP_OP:
.LFB19:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 8[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE19:
	.size	Get_TRAP_OP, .-Get_TRAP_OP
	.globl	Get_DCACHE_EN
	.type	Get_DCACHE_EN, @function
Get_DCACHE_EN:
.LFB20:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 16[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE20:
	.size	Get_DCACHE_EN, .-Get_DCACHE_EN
	.globl	Get_DCACHE_RW
	.type	Get_DCACHE_RW, @function
Get_DCACHE_RW:
.LFB21:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 20[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE21:
	.size	Get_DCACHE_RW, .-Get_DCACHE_RW
	.globl	Get_DATA_SIZE
	.type	Get_DATA_SIZE, @function
Get_DATA_SIZE:
.LFB22:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 24[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE22:
	.size	Get_DATA_SIZE, .-Get_DATA_SIZE
	.globl	Get_DR_VALUEMUX1
	.type	Get_DR_VALUEMUX1, @function
Get_DR_VALUEMUX1:
.LFB23:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	lea	edx, [rax+rax]
	mov	rax, QWORD PTR -8[rbp]
	add	rax, 4
	mov	eax, DWORD PTR [rax]
	add	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE23:
	.size	Get_DR_VALUEMUX1, .-Get_DR_VALUEMUX1
	.globl	Get_AGEX_LD_REG
	.type	Get_AGEX_LD_REG, @function
Get_AGEX_LD_REG:
.LFB24:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 72[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE24:
	.size	Get_AGEX_LD_REG, .-Get_AGEX_LD_REG
	.globl	Get_AGEX_LD_CC
	.type	Get_AGEX_LD_CC, @function
Get_AGEX_LD_CC:
.LFB25:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 76[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE25:
	.size	Get_AGEX_LD_CC, .-Get_AGEX_LD_CC
	.globl	Get_MEM_LD_REG
	.type	Get_MEM_LD_REG, @function
Get_MEM_LD_REG:
.LFB26:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 36[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE26:
	.size	Get_MEM_LD_REG, .-Get_MEM_LD_REG
	.globl	Get_MEM_LD_CC
	.type	Get_MEM_LD_CC, @function
Get_MEM_LD_CC:
.LFB27:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 40[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE27:
	.size	Get_MEM_LD_CC, .-Get_MEM_LD_CC
	.globl	Get_SR_LD_REG
	.type	Get_SR_LD_REG, @function
Get_SR_LD_REG:
.LFB28:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 8[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE28:
	.size	Get_SR_LD_REG, .-Get_SR_LD_REG
	.globl	Get_SR_LD_CC
	.type	Get_SR_LD_CC, @function
Get_SR_LD_CC:
.LFB29:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 12[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE29:
	.size	Get_SR_LD_CC, .-Get_SR_LD_CC
	.globl	Get_DE_BR_STALL
	.type	Get_DE_BR_STALL, @function
Get_DE_BR_STALL:
.LFB30:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 60[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE30:
	.size	Get_DE_BR_STALL, .-Get_DE_BR_STALL
	.globl	Get_AGEX_BR_STALL
	.type	Get_AGEX_BR_STALL, @function
Get_AGEX_BR_STALL:
.LFB31:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 48[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE31:
	.size	Get_AGEX_BR_STALL, .-Get_AGEX_BR_STALL
	.globl	Get_MEM_BR_STALL
	.type	Get_MEM_BR_STALL, @function
Get_MEM_BR_STALL:
.LFB32:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 12[rax]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE32:
	.size	Get_MEM_BR_STALL, .-Get_MEM_BR_STALL
	.globl	CONTROL_STORE
	.bss
	.align 32
	.type	CONTROL_STORE, @object
	.size	CONTROL_STORE, 5888
CONTROL_STORE:
	.zero	5888
	.globl	MEMORY
	.align 32
	.type	MEMORY, @object
	.size	MEMORY, 262144
MEMORY:
	.zero	262144
	.globl	REGS
	.data
	.align 32
	.type	REGS, @object
	.size	REGS, 32
REGS:
	.long	0
	.long	1
	.long	2
	.long	3
	.long	4
	.long	5
	.long	4666
	.long	43981
	.globl	PC
	.bss
	.align 4
	.type	PC, @object
	.size	PC, 4
PC:
	.zero	4
	.globl	N
	.align 4
	.type	N, @object
	.size	N, 4
N:
	.zero	4
	.globl	Z
	.data
	.align 4
	.type	Z, @object
	.size	Z, 4
Z:
	.long	1
	.globl	P
	.bss
	.align 4
	.type	P, @object
	.size	P, 4
P:
	.zero	4
	.globl	PS
	.align 32
	.type	PS, @object
	.size	PS, 236
PS:
	.zero	236
	.globl	NEW_PS
	.align 32
	.type	NEW_PS, @object
	.size	NEW_PS, 236
NEW_PS:
	.zero	236
	.globl	RUN_BIT
	.align 4
	.type	RUN_BIT, @object
	.size	RUN_BIT, 4
RUN_BIT:
	.zero	4
	.globl	dep_stall
	.align 4
	.type	dep_stall, @object
	.size	dep_stall, 4
dep_stall:
	.zero	4
	.globl	v_de_br_stall
	.align 4
	.type	v_de_br_stall, @object
	.size	v_de_br_stall, 4
v_de_br_stall:
	.zero	4
	.globl	v_agex_br_stall
	.align 4
	.type	v_agex_br_stall, @object
	.size	v_agex_br_stall, 4
v_agex_br_stall:
	.zero	4
	.globl	v_mem_br_stall
	.align 4
	.type	v_mem_br_stall, @object
	.size	v_mem_br_stall, 4
v_mem_br_stall:
	.zero	4
	.globl	mem_stall
	.align 4
	.type	mem_stall, @object
	.size	mem_stall, 4
mem_stall:
	.zero	4
	.globl	icache_r
	.align 4
	.type	icache_r, @object
	.size	icache_r, 4
icache_r:
	.zero	4
	.globl	CYCLE_COUNT
	.align 4
	.type	CYCLE_COUNT, @object
	.size	CYCLE_COUNT, 4
CYCLE_COUNT:
	.zero	4
	.section	.rodata
	.align 8
.LC0:
	.string	"----------------LC-3bSIM Help-------------------------"
	.align 8
.LC1:
	.string	"go               -  run program to completion       "
	.align 8
.LC2:
	.string	"run n            -  execute program for n cycles    "
	.align 8
.LC3:
	.string	"mdump low high   -  dump memory from low to high    "
	.align 8
.LC4:
	.string	"rdump            -  dump the architectural state    "
	.align 8
.LC5:
	.string	"idump            -  dump the internal state         "
	.align 8
.LC6:
	.string	"?                -  display this help menu          "
	.align 8
.LC7:
	.string	"quit             -  exit the program                \n"
	.text
	.globl	help
	.type	help, @function
help:
.LFB33:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	lea	rdi, .LC0[rip]
	call	puts@PLT
	lea	rdi, .LC1[rip]
	call	puts@PLT
	lea	rdi, .LC2[rip]
	call	puts@PLT
	lea	rdi, .LC3[rip]
	call	puts@PLT
	lea	rdi, .LC4[rip]
	call	puts@PLT
	lea	rdi, .LC5[rip]
	call	puts@PLT
	lea	rdi, .LC6[rip]
	call	puts@PLT
	lea	rdi, .LC7[rip]
	call	puts@PLT
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE33:
	.size	help, .-help
	.section	.rodata
.LC8:
	.string	"%d"
	.text
	.globl	print_CS
	.type	print_CS, @function
print_CS:
.LFB34:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	DWORD PTR -4[rbp], 0
	jmp	.L57
.L58:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -24[rbp]
	add	rax, rdx
	mov	eax, DWORD PTR [rax]
	mov	esi, eax
	lea	rdi, .LC8[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -4[rbp], 1
.L57:
	mov	eax, DWORD PTR -4[rbp]
	cmp	eax, DWORD PTR -28[rbp]
	jl	.L58
	mov	edi, 10
	call	putchar@PLT
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE34:
	.size	print_CS, .-print_CS
	.globl	cycle
	.type	cycle, @function
cycle:
.LFB35:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	rax, QWORD PTR PS[rip]
	mov	rdx, QWORD PTR PS[rip+8]
	mov	QWORD PTR NEW_PS[rip], rax
	mov	QWORD PTR NEW_PS[rip+8], rdx
	mov	rax, QWORD PTR PS[rip+16]
	mov	rdx, QWORD PTR PS[rip+24]
	mov	QWORD PTR NEW_PS[rip+16], rax
	mov	QWORD PTR NEW_PS[rip+24], rdx
	mov	rax, QWORD PTR PS[rip+32]
	mov	rdx, QWORD PTR PS[rip+40]
	mov	QWORD PTR NEW_PS[rip+32], rax
	mov	QWORD PTR NEW_PS[rip+40], rdx
	mov	rax, QWORD PTR PS[rip+48]
	mov	rdx, QWORD PTR PS[rip+56]
	mov	QWORD PTR NEW_PS[rip+48], rax
	mov	QWORD PTR NEW_PS[rip+56], rdx
	mov	rax, QWORD PTR PS[rip+64]
	mov	rdx, QWORD PTR PS[rip+72]
	mov	QWORD PTR NEW_PS[rip+64], rax
	mov	QWORD PTR NEW_PS[rip+72], rdx
	mov	rax, QWORD PTR PS[rip+80]
	mov	rdx, QWORD PTR PS[rip+88]
	mov	QWORD PTR NEW_PS[rip+80], rax
	mov	QWORD PTR NEW_PS[rip+88], rdx
	mov	rax, QWORD PTR PS[rip+96]
	mov	rdx, QWORD PTR PS[rip+104]
	mov	QWORD PTR NEW_PS[rip+96], rax
	mov	QWORD PTR NEW_PS[rip+104], rdx
	mov	rax, QWORD PTR PS[rip+112]
	mov	rdx, QWORD PTR PS[rip+120]
	mov	QWORD PTR NEW_PS[rip+112], rax
	mov	QWORD PTR NEW_PS[rip+120], rdx
	mov	rax, QWORD PTR PS[rip+128]
	mov	rdx, QWORD PTR PS[rip+136]
	mov	QWORD PTR NEW_PS[rip+128], rax
	mov	QWORD PTR NEW_PS[rip+136], rdx
	mov	rax, QWORD PTR PS[rip+144]
	mov	rdx, QWORD PTR PS[rip+152]
	mov	QWORD PTR NEW_PS[rip+144], rax
	mov	QWORD PTR NEW_PS[rip+152], rdx
	mov	rax, QWORD PTR PS[rip+160]
	mov	rdx, QWORD PTR PS[rip+168]
	mov	QWORD PTR NEW_PS[rip+160], rax
	mov	QWORD PTR NEW_PS[rip+168], rdx
	mov	rax, QWORD PTR PS[rip+176]
	mov	rdx, QWORD PTR PS[rip+184]
	mov	QWORD PTR NEW_PS[rip+176], rax
	mov	QWORD PTR NEW_PS[rip+184], rdx
	mov	rax, QWORD PTR PS[rip+192]
	mov	rdx, QWORD PTR PS[rip+200]
	mov	QWORD PTR NEW_PS[rip+192], rax
	mov	QWORD PTR NEW_PS[rip+200], rdx
	mov	rax, QWORD PTR PS[rip+208]
	mov	rdx, QWORD PTR PS[rip+216]
	mov	QWORD PTR NEW_PS[rip+208], rax
	mov	QWORD PTR NEW_PS[rip+216], rdx
	mov	rax, QWORD PTR PS[rip+224]
	mov	QWORD PTR NEW_PS[rip+224], rax
	mov	eax, DWORD PTR PS[rip+232]
	mov	DWORD PTR NEW_PS[rip+232], eax
	mov	eax, 0
	call	SR_stage
	mov	eax, 0
	call	MEM_stage
	mov	eax, 0
	call	AGEX_stage
	mov	eax, 0
	call	DE_stage
	mov	eax, 0
	call	FETCH_stage
	mov	rax, QWORD PTR NEW_PS[rip]
	mov	rdx, QWORD PTR NEW_PS[rip+8]
	mov	QWORD PTR PS[rip], rax
	mov	QWORD PTR PS[rip+8], rdx
	mov	rax, QWORD PTR NEW_PS[rip+16]
	mov	rdx, QWORD PTR NEW_PS[rip+24]
	mov	QWORD PTR PS[rip+16], rax
	mov	QWORD PTR PS[rip+24], rdx
	mov	rax, QWORD PTR NEW_PS[rip+32]
	mov	rdx, QWORD PTR NEW_PS[rip+40]
	mov	QWORD PTR PS[rip+32], rax
	mov	QWORD PTR PS[rip+40], rdx
	mov	rax, QWORD PTR NEW_PS[rip+48]
	mov	rdx, QWORD PTR NEW_PS[rip+56]
	mov	QWORD PTR PS[rip+48], rax
	mov	QWORD PTR PS[rip+56], rdx
	mov	rax, QWORD PTR NEW_PS[rip+64]
	mov	rdx, QWORD PTR NEW_PS[rip+72]
	mov	QWORD PTR PS[rip+64], rax
	mov	QWORD PTR PS[rip+72], rdx
	mov	rax, QWORD PTR NEW_PS[rip+80]
	mov	rdx, QWORD PTR NEW_PS[rip+88]
	mov	QWORD PTR PS[rip+80], rax
	mov	QWORD PTR PS[rip+88], rdx
	mov	rax, QWORD PTR NEW_PS[rip+96]
	mov	rdx, QWORD PTR NEW_PS[rip+104]
	mov	QWORD PTR PS[rip+96], rax
	mov	QWORD PTR PS[rip+104], rdx
	mov	rax, QWORD PTR NEW_PS[rip+112]
	mov	rdx, QWORD PTR NEW_PS[rip+120]
	mov	QWORD PTR PS[rip+112], rax
	mov	QWORD PTR PS[rip+120], rdx
	mov	rax, QWORD PTR NEW_PS[rip+128]
	mov	rdx, QWORD PTR NEW_PS[rip+136]
	mov	QWORD PTR PS[rip+128], rax
	mov	QWORD PTR PS[rip+136], rdx
	mov	rax, QWORD PTR NEW_PS[rip+144]
	mov	rdx, QWORD PTR NEW_PS[rip+152]
	mov	QWORD PTR PS[rip+144], rax
	mov	QWORD PTR PS[rip+152], rdx
	mov	rax, QWORD PTR NEW_PS[rip+160]
	mov	rdx, QWORD PTR NEW_PS[rip+168]
	mov	QWORD PTR PS[rip+160], rax
	mov	QWORD PTR PS[rip+168], rdx
	mov	rax, QWORD PTR NEW_PS[rip+176]
	mov	rdx, QWORD PTR NEW_PS[rip+184]
	mov	QWORD PTR PS[rip+176], rax
	mov	QWORD PTR PS[rip+184], rdx
	mov	rax, QWORD PTR NEW_PS[rip+192]
	mov	rdx, QWORD PTR NEW_PS[rip+200]
	mov	QWORD PTR PS[rip+192], rax
	mov	QWORD PTR PS[rip+200], rdx
	mov	rax, QWORD PTR NEW_PS[rip+208]
	mov	rdx, QWORD PTR NEW_PS[rip+216]
	mov	QWORD PTR PS[rip+208], rax
	mov	QWORD PTR PS[rip+216], rdx
	mov	rax, QWORD PTR NEW_PS[rip+224]
	mov	QWORD PTR PS[rip+224], rax
	mov	eax, DWORD PTR NEW_PS[rip+232]
	mov	DWORD PTR PS[rip+232], eax
	mov	eax, DWORD PTR CYCLE_COUNT[rip]
	add	eax, 1
	mov	DWORD PTR CYCLE_COUNT[rip], eax
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE35:
	.size	cycle, .-cycle
	.section	.rodata
	.align 8
.LC9:
	.string	"Can't simulate, Simulator is halted\n"
.LC10:
	.string	"Simulating for %d cycles...\n\n"
.LC11:
	.string	"Simulator halted\n"
	.text
	.globl	run
	.type	run, @function
run:
.LFB36:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	DWORD PTR -20[rbp], edi
	mov	eax, DWORD PTR RUN_BIT[rip]
	test	eax, eax
	jne	.L61
	lea	rdi, .LC9[rip]
	call	puts@PLT
	jmp	.L60
.L61:
	mov	eax, DWORD PTR -20[rbp]
	mov	esi, eax
	lea	rdi, .LC10[rip]
	mov	eax, 0
	call	printf@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L63
.L65:
	mov	eax, DWORD PTR PC[rip]
	test	eax, eax
	jne	.L64
	mov	eax, 0
	call	cycle
	mov	DWORD PTR RUN_BIT[rip], 0
	lea	rdi, .LC11[rip]
	call	puts@PLT
	jmp	.L60
.L64:
	mov	eax, 0
	call	cycle
	add	DWORD PTR -4[rbp], 1
.L63:
	mov	eax, DWORD PTR -4[rbp]
	cmp	eax, DWORD PTR -20[rbp]
	jl	.L65
.L60:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE36:
	.size	run, .-run
	.section	.rodata
.LC12:
	.string	"Simulating...\n"
	.text
	.globl	go
	.type	go, @function
go:
.LFB37:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, DWORD PTR RUN_BIT[rip]
	test	eax, eax
	je	.L67
	mov	eax, DWORD PTR PC[rip]
	test	eax, eax
	jne	.L68
.L67:
	lea	rdi, .LC9[rip]
	call	puts@PLT
	jmp	.L66
.L68:
	lea	rdi, .LC12[rip]
	call	puts@PLT
	jmp	.L70
.L71:
	mov	eax, 0
	call	cycle
.L70:
	mov	eax, DWORD PTR PC[rip]
	test	eax, eax
	jne	.L71
	mov	eax, 0
	call	cycle
	mov	DWORD PTR RUN_BIT[rip], 0
	lea	rdi, .LC11[rip]
	call	puts@PLT
.L66:
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE37:
	.size	go, .-go
	.section	.rodata
	.align 8
.LC13:
	.string	"\nMemory content [0x%04x..0x%04x] :\n"
	.align 8
.LC14:
	.string	"-------------------------------------"
.LC15:
	.string	"  0x%04x (%d) : 0x%02x%02x\n"
	.align 8
.LC16:
	.string	"-------------------------------------\n"
.LC17:
	.string	" 0x%04x (%d) : 0x%02x%02x\n"
	.text
	.globl	mdump
	.type	mdump, @function
mdump:
.LFB38:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	mov	DWORD PTR -28[rbp], esi
	mov	DWORD PTR -32[rbp], edx
	mov	edx, DWORD PTR -32[rbp]
	mov	eax, DWORD PTR -28[rbp]
	mov	esi, eax
	lea	rdi, .LC13[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rdi, .LC14[rip]
	call	puts@PLT
	mov	eax, DWORD PTR -28[rbp]
	sar	eax
	mov	DWORD PTR -4[rbp], eax
	jmp	.L73
.L74:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip]
	mov	edi, DWORD PTR [rdx+rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip+4]
	mov	eax, DWORD PTR [rdx+rax]
	mov	edx, DWORD PTR -4[rbp]
	add	edx, edx
	mov	ecx, DWORD PTR -4[rbp]
	lea	esi, [rcx+rcx]
	mov	r8d, edi
	mov	ecx, eax
	lea	rdi, .LC15[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -4[rbp], 1
.L73:
	mov	eax, DWORD PTR -32[rbp]
	sar	eax
	cmp	DWORD PTR -4[rbp], eax
	jle	.L74
	mov	edi, 10
	call	putchar@PLT
	mov	ecx, DWORD PTR -32[rbp]
	mov	edx, DWORD PTR -28[rbp]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC13[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 38
	mov	esi, 1
	lea	rdi, .LC16[rip]
	call	fwrite@PLT
	mov	eax, DWORD PTR -28[rbp]
	sar	eax
	mov	DWORD PTR -4[rbp], eax
	jmp	.L75
.L76:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip]
	mov	edi, DWORD PTR [rdx+rax]
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip+4]
	mov	esi, DWORD PTR [rdx+rax]
	mov	eax, DWORD PTR -4[rbp]
	lea	ecx, [rax+rax]
	mov	eax, DWORD PTR -4[rbp]
	lea	edx, [rax+rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	r9d, edi
	mov	r8d, esi
	lea	rsi, .LC17[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	add	DWORD PTR -4[rbp], 1
.L75:
	mov	eax, DWORD PTR -32[rbp]
	sar	eax
	cmp	DWORD PTR -4[rbp], eax
	jle	.L76
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE38:
	.size	mdump, .-mdump
	.section	.rodata
	.align 8
.LC18:
	.string	"\nCurrent architectural state :"
.LC19:
	.string	"Cycle Count : %d\n"
.LC20:
	.string	"PC          : 0x%04x\n"
.LC21:
	.string	"CCs: N = %d  Z = %d  P = %d\n"
.LC22:
	.string	"Registers:"
.LC23:
	.string	"%d: 0x%04x\n"
	.align 8
.LC24:
	.string	"\nCurrent architectural state :\n"
.LC25:
	.string	"Registers:\n"
	.text
	.globl	rdump
	.type	rdump, @function
rdump:
.LFB39:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	lea	rdi, .LC18[rip]
	call	puts@PLT
	lea	rdi, .LC14[rip]
	call	puts@PLT
	mov	eax, DWORD PTR CYCLE_COUNT[rip]
	mov	esi, eax
	lea	rdi, .LC19[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PC[rip]
	mov	esi, eax
	lea	rdi, .LC20[rip]
	mov	eax, 0
	call	printf@PLT
	mov	ecx, DWORD PTR P[rip]
	mov	edx, DWORD PTR Z[rip]
	mov	eax, DWORD PTR N[rip]
	mov	esi, eax
	lea	rdi, .LC21[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rdi, .LC22[rip]
	call	puts@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L78
.L79:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, REGS[rip]
	mov	eax, DWORD PTR [rdx+rax]
	movzx	edx, ax
	mov	eax, DWORD PTR -4[rbp]
	mov	esi, eax
	lea	rdi, .LC23[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -4[rbp], 1
.L78:
	cmp	DWORD PTR -4[rbp], 7
	jle	.L79
	mov	edi, 10
	call	putchar@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 31
	mov	esi, 1
	lea	rdi, .LC24[rip]
	call	fwrite@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 38
	mov	esi, 1
	lea	rdi, .LC16[rip]
	call	fwrite@PLT
	mov	edx, DWORD PTR CYCLE_COUNT[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC19[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PC[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC20[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	esi, DWORD PTR P[rip]
	mov	ecx, DWORD PTR Z[rip]
	mov	edx, DWORD PTR N[rip]
	mov	rax, QWORD PTR -24[rbp]
	mov	r8d, esi
	lea	rsi, .LC21[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 11
	mov	esi, 1
	lea	rdi, .LC25[rip]
	call	fwrite@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L80
.L81:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, REGS[rip]
	mov	eax, DWORD PTR [rdx+rax]
	movzx	ecx, ax
	mov	edx, DWORD PTR -4[rbp]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC23[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	add	DWORD PTR -4[rbp], 1
.L80:
	cmp	DWORD PTR -4[rbp], 7
	jle	.L81
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE39:
	.size	rdump, .-rdump
	.section	.rodata
.LC26:
	.string	"Cycle Count     : %d\n"
.LC27:
	.string	"PC              : 0x%04x\n"
	.align 8
.LC28:
	.string	"------------- Stall Signals -------------"
.LC29:
	.string	"ICACHE_R        :  %d\n"
.LC30:
	.string	"DEP_STALL       :  %d\n"
.LC31:
	.string	"V_DE_BR_STALL   :  %d\n"
.LC32:
	.string	"V_AGEX_BR_STALL :  %d\n"
.LC33:
	.string	"MEM_STALL       :  %d\n"
.LC34:
	.string	"V_MEM_BR_STALL  :  %d\n"
	.align 8
.LC35:
	.string	"------------- DE   Latches --------------"
.LC36:
	.string	"DE_NPC          :  0x%04x\n"
.LC37:
	.string	"DE_IR           :  0x%04x\n"
.LC38:
	.string	"DE_V            :  %d\n"
	.align 8
.LC39:
	.string	"------------- AGEX Latches --------------"
.LC40:
	.string	"AGEX_NPC        :  0x%04x\n"
.LC41:
	.string	"AGEX_SR1        :  0x%04x\n"
.LC42:
	.string	"AGEX_SR2        :  0x%04x\n"
.LC43:
	.string	"AGEX_CC         :  %d\n"
.LC44:
	.string	"AGEX_IR         :  0x%04x\n"
.LC45:
	.string	"AGEX_DRID       :  %d\n"
.LC46:
	.string	"AGEX_CS         :  "
.LC47:
	.string	"AGEX_V          :  %d\n"
	.align 8
.LC48:
	.string	"------------- MEM  Latches --------------"
.LC49:
	.string	"MEM_NPC         :  0x%04x\n"
.LC50:
	.string	"MEM_ALU_RESULT  :  0x%04x\n"
.LC51:
	.string	"MEM_ADDRESS     :  0x%04x\n"
.LC52:
	.string	"MEM_CC          :  %d\n"
.LC53:
	.string	"MEM_IR          :  0x%04x\n"
.LC54:
	.string	"MEM_DRID        :  %d\n"
.LC55:
	.string	"MEM_CS          :  "
.LC56:
	.string	"MEM_V           :  %d\n"
	.align 8
.LC57:
	.string	"------------- SR   Latches --------------"
.LC58:
	.string	"SR_NPC          :  0x%04x\n"
.LC59:
	.string	"SR_DATA         :  0x%04x\n"
.LC60:
	.string	"SR_ALU_RESULT   :  0x%04x\n"
.LC61:
	.string	"SR_ADDRESS      :  0x%04x\n"
.LC62:
	.string	"SR_IR           :  0x%04x\n"
.LC63:
	.string	"SR_DRID         :  %d\n"
.LC64:
	.string	"SR_CS           :  "
.LC65:
	.string	"SR_V            :  %d\n"
	.align 8
.LC66:
	.string	"\nCurrent register/bus values :\n"
	.align 8
.LC67:
	.string	"------------- Stall Signals -------------\n"
	.align 8
.LC68:
	.string	"------------- DE   Latches --------------\n"
	.align 8
.LC69:
	.string	"------------- AGEX Latches --------------\n"
	.align 8
.LC70:
	.string	"------------- MEM  Latches --------------\n"
	.align 8
.LC71:
	.string	"------------- SR   Latches --------------\n"
	.text
	.globl	idump
	.type	idump, @function
idump:
.LFB40:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	QWORD PTR -24[rbp], rdi
	lea	rdi, .LC18[rip]
	call	puts@PLT
	lea	rdi, .LC14[rip]
	call	puts@PLT
	mov	eax, DWORD PTR CYCLE_COUNT[rip]
	mov	esi, eax
	lea	rdi, .LC26[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PC[rip]
	mov	esi, eax
	lea	rdi, .LC27[rip]
	mov	eax, 0
	call	printf@PLT
	mov	ecx, DWORD PTR P[rip]
	mov	edx, DWORD PTR Z[rip]
	mov	eax, DWORD PTR N[rip]
	mov	esi, eax
	lea	rdi, .LC21[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rdi, .LC22[rip]
	call	puts@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L83
.L84:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, REGS[rip]
	mov	eax, DWORD PTR [rdx+rax]
	movzx	edx, ax
	mov	eax, DWORD PTR -4[rbp]
	mov	esi, eax
	lea	rdi, .LC23[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -4[rbp], 1
.L83:
	cmp	DWORD PTR -4[rbp], 7
	jle	.L84
	mov	edi, 10
	call	putchar@PLT
	lea	rdi, .LC28[rip]
	call	puts@PLT
	mov	eax, DWORD PTR icache_r[rip]
	mov	esi, eax
	lea	rdi, .LC29[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR dep_stall[rip]
	mov	esi, eax
	lea	rdi, .LC30[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR v_de_br_stall[rip]
	mov	esi, eax
	lea	rdi, .LC31[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR v_agex_br_stall[rip]
	mov	esi, eax
	lea	rdi, .LC32[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR mem_stall[rip]
	mov	esi, eax
	lea	rdi, .LC33[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR v_mem_br_stall[rip]
	mov	esi, eax
	lea	rdi, .LC34[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, 10
	call	putchar@PLT
	lea	rdi, .LC35[rip]
	call	puts@PLT
	mov	eax, DWORD PTR PS[rip]
	mov	esi, eax
	lea	rdi, .LC36[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+4]
	mov	esi, eax
	lea	rdi, .LC37[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+8]
	mov	esi, eax
	lea	rdi, .LC38[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, 10
	call	putchar@PLT
	lea	rdi, .LC39[rip]
	call	puts@PLT
	mov	eax, DWORD PTR PS[rip+12]
	mov	esi, eax
	lea	rdi, .LC40[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+16]
	mov	esi, eax
	lea	rdi, .LC41[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+20]
	mov	esi, eax
	lea	rdi, .LC42[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+24]
	mov	esi, eax
	lea	rdi, .LC43[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+28]
	mov	esi, eax
	lea	rdi, .LC44[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+32]
	mov	esi, eax
	lea	rdi, .LC45[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rdi, .LC46[rip]
	mov	eax, 0
	call	printf@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L85
.L86:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 8
	lea	rdx, 0[0+rax*4]
	lea	rax, PS[rip+8]
	mov	eax, DWORD PTR [rdx+rax]
	mov	esi, eax
	lea	rdi, .LC8[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -4[rbp], 1
.L85:
	cmp	DWORD PTR -4[rbp], 19
	jle	.L86
	mov	edi, 10
	call	putchar@PLT
	mov	eax, DWORD PTR PS[rip+36]
	mov	esi, eax
	lea	rdi, .LC47[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, 10
	call	putchar@PLT
	lea	rdi, .LC48[rip]
	call	puts@PLT
	mov	eax, DWORD PTR PS[rip+120]
	mov	esi, eax
	lea	rdi, .LC49[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+124]
	mov	esi, eax
	lea	rdi, .LC50[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+128]
	mov	esi, eax
	lea	rdi, .LC51[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+132]
	mov	esi, eax
	lea	rdi, .LC52[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+136]
	mov	esi, eax
	lea	rdi, .LC53[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+140]
	mov	esi, eax
	lea	rdi, .LC54[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rdi, .LC55[rip]
	mov	eax, 0
	call	printf@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L87
.L88:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 36
	lea	rdx, 0[0+rax*4]
	lea	rax, PS[rip+4]
	mov	eax, DWORD PTR [rdx+rax]
	mov	esi, eax
	lea	rdi, .LC8[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -4[rbp], 1
.L87:
	cmp	DWORD PTR -4[rbp], 10
	jle	.L88
	mov	edi, 10
	call	putchar@PLT
	mov	eax, DWORD PTR PS[rip+144]
	mov	esi, eax
	lea	rdi, .LC56[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, 10
	call	putchar@PLT
	lea	rdi, .LC57[rip]
	call	puts@PLT
	mov	eax, DWORD PTR PS[rip+192]
	mov	esi, eax
	lea	rdi, .LC58[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+196]
	mov	esi, eax
	lea	rdi, .LC59[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+200]
	mov	esi, eax
	lea	rdi, .LC60[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+204]
	mov	esi, eax
	lea	rdi, .LC61[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+208]
	mov	esi, eax
	lea	rdi, .LC62[rip]
	mov	eax, 0
	call	printf@PLT
	mov	eax, DWORD PTR PS[rip+212]
	mov	esi, eax
	lea	rdi, .LC63[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rdi, .LC64[rip]
	mov	eax, 0
	call	printf@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L89
.L90:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 52
	lea	rdx, 0[0+rax*4]
	lea	rax, PS[rip+12]
	mov	eax, DWORD PTR [rdx+rax]
	mov	esi, eax
	lea	rdi, .LC8[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -4[rbp], 1
.L89:
	cmp	DWORD PTR -4[rbp], 3
	jle	.L90
	mov	edi, 10
	call	putchar@PLT
	mov	eax, DWORD PTR PS[rip+216]
	mov	esi, eax
	lea	rdi, .LC65[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, 10
	call	putchar@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 31
	mov	esi, 1
	lea	rdi, .LC66[rip]
	call	fwrite@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 31
	mov	esi, 1
	lea	rdi, .LC24[rip]
	call	fwrite@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 38
	mov	esi, 1
	lea	rdi, .LC16[rip]
	call	fwrite@PLT
	mov	edx, DWORD PTR CYCLE_COUNT[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC26[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PC[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC27[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	esi, DWORD PTR P[rip]
	mov	ecx, DWORD PTR Z[rip]
	mov	edx, DWORD PTR N[rip]
	mov	rax, QWORD PTR -24[rbp]
	mov	r8d, esi
	lea	rsi, .LC21[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 11
	mov	esi, 1
	lea	rdi, .LC25[rip]
	call	fwrite@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L91
.L92:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, REGS[rip]
	mov	eax, DWORD PTR [rdx+rax]
	movzx	ecx, ax
	mov	edx, DWORD PTR -4[rbp]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC23[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	add	DWORD PTR -4[rbp], 1
.L91:
	cmp	DWORD PTR -4[rbp], 7
	jle	.L92
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 42
	mov	esi, 1
	lea	rdi, .LC67[rip]
	call	fwrite@PLT
	mov	edx, DWORD PTR icache_r[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC29[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR dep_stall[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC30[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR v_de_br_stall[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC31[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR v_agex_br_stall[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC32[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR mem_stall[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC33[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR v_mem_br_stall[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC34[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 42
	mov	esi, 1
	lea	rdi, .LC68[rip]
	call	fwrite@PLT
	mov	edx, DWORD PTR PS[rip]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC36[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+4]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC37[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+8]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC38[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 42
	mov	esi, 1
	lea	rdi, .LC69[rip]
	call	fwrite@PLT
	mov	edx, DWORD PTR PS[rip+12]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC40[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+16]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC41[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+20]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC42[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+24]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC43[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+28]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC44[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+32]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC45[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 19
	mov	esi, 1
	lea	rdi, .LC46[rip]
	call	fwrite@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L93
.L94:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 8
	lea	rdx, 0[0+rax*4]
	lea	rax, PS[rip+8]
	mov	edx, DWORD PTR [rdx+rax]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC8[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	add	DWORD PTR -4[rbp], 1
.L93:
	cmp	DWORD PTR -4[rbp], 19
	jle	.L94
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	mov	edx, DWORD PTR PS[rip+36]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC47[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 42
	mov	esi, 1
	lea	rdi, .LC70[rip]
	call	fwrite@PLT
	mov	edx, DWORD PTR PS[rip+120]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC49[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+124]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC50[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+128]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC51[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+132]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC52[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+136]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC53[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+140]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC54[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 19
	mov	esi, 1
	lea	rdi, .LC55[rip]
	call	fwrite@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L95
.L96:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 36
	lea	rdx, 0[0+rax*4]
	lea	rax, PS[rip+4]
	mov	edx, DWORD PTR [rdx+rax]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC8[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	add	DWORD PTR -4[rbp], 1
.L95:
	cmp	DWORD PTR -4[rbp], 10
	jle	.L96
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	mov	edx, DWORD PTR PS[rip+144]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC56[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 42
	mov	esi, 1
	lea	rdi, .LC71[rip]
	call	fwrite@PLT
	mov	edx, DWORD PTR PS[rip+192]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC58[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+196]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC59[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+200]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC60[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+204]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC61[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+208]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC62[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	edx, DWORD PTR PS[rip+212]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC63[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rcx, rax
	mov	edx, 19
	mov	esi, 1
	lea	rdi, .LC64[rip]
	call	fwrite@PLT
	mov	DWORD PTR -4[rbp], 0
	jmp	.L97
.L98:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	add	rax, 52
	lea	rdx, 0[0+rax*4]
	lea	rax, PS[rip+12]
	mov	edx, DWORD PTR [rdx+rax]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC8[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	add	DWORD PTR -4[rbp], 1
.L97:
	cmp	DWORD PTR -4[rbp], 3
	jle	.L98
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	mov	edx, DWORD PTR PS[rip+216]
	mov	rax, QWORD PTR -24[rbp]
	lea	rsi, .LC65[rip]
	mov	rdi, rax
	mov	eax, 0
	call	fprintf@PLT
	mov	rax, QWORD PTR -24[rbp]
	mov	rsi, rax
	mov	edi, 10
	call	fputc@PLT
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE40:
	.size	idump, .-idump
	.section	.rodata
.LC72:
	.string	"LC-3b-SIM> "
.LC73:
	.string	"%s"
.LC74:
	.string	"%i %i"
.LC75:
	.string	"Bye."
.LC76:
	.string	"Invalid Command"
	.text
	.globl	get_command
	.type	get_command, @function
get_command:
.LFB41:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	mov	QWORD PTR -56[rbp], rdi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	lea	rdi, .LC72[rip]
	mov	eax, 0
	call	printf@PLT
	lea	rax, -32[rbp]
	mov	rsi, rax
	lea	rdi, .LC73[rip]
	mov	eax, 0
	call	__isoc99_scanf@PLT
	mov	edi, 10
	call	putchar@PLT
	movzx	eax, BYTE PTR -32[rbp]
	movsx	eax, al
	sub	eax, 63
	cmp	eax, 51
	ja	.L100
	mov	eax, eax
	lea	rdx, 0[0+rax*4]
	lea	rax, .L102[rip]
	mov	eax, DWORD PTR [rdx+rax]
	cdqe
	lea	rdx, .L102[rip]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L102:
	.long	.L107-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L106-.L102
	.long	.L100-.L102
	.long	.L105-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L104-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L103-.L102
	.long	.L101-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L106-.L102
	.long	.L100-.L102
	.long	.L105-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L104-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L100-.L102
	.long	.L103-.L102
	.long	.L101-.L102
	.text
.L106:
	mov	eax, 0
	call	go
	jmp	.L108
.L104:
	lea	rdx, -36[rbp]
	lea	rax, -40[rbp]
	mov	rsi, rax
	lea	rdi, .LC74[rip]
	mov	eax, 0
	call	__isoc99_scanf@PLT
	mov	edx, DWORD PTR -36[rbp]
	mov	ecx, DWORD PTR -40[rbp]
	mov	rax, QWORD PTR -56[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	mdump
	jmp	.L108
.L107:
	mov	eax, 0
	call	help
	jmp	.L108
.L103:
	lea	rdi, .LC75[rip]
	call	puts@PLT
	mov	edi, 0
	call	exit@PLT
.L101:
	movzx	eax, BYTE PTR -31[rbp]
	cmp	al, 100
	je	.L109
	movzx	eax, BYTE PTR -31[rbp]
	cmp	al, 68
	jne	.L110
.L109:
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	rdump
	jmp	.L108
.L110:
	lea	rax, -36[rbp]
	mov	rsi, rax
	lea	rdi, .LC8[rip]
	mov	eax, 0
	call	__isoc99_scanf@PLT
	mov	eax, DWORD PTR -36[rbp]
	mov	edi, eax
	call	run
	jmp	.L108
.L105:
	mov	rax, QWORD PTR -56[rbp]
	mov	rdi, rax
	call	idump
	jmp	.L108
.L100:
	lea	rdi, .LC76[rip]
	call	puts@PLT
	nop
.L108:
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L112
	call	__stack_chk_fail@PLT
.L112:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE41:
	.size	get_command, .-get_command
	.section	.rodata
	.align 8
.LC77:
	.string	"Loading Control Store from file: %s\n"
.LC78:
	.string	"r"
	.align 8
.LC79:
	.string	"Error: Can't open micro-code file %s\n"
.LC80:
	.string	"%[^\n]\n"
	.align 8
.LC81:
	.string	"Error: Too few lines (%d) in micro-code file: %s\n"
	.align 8
.LC82:
	.string	"Error: Too few control bits in micro-code file: %s\nLine: %d\n"
	.align 8
.LC83:
	.string	"Error: Unknown value in micro-code file: %s\nLine: %d, Bit: %d\n"
	.align 8
.LC84:
	.string	"Warning: Extra bit(s) in control store file %s. Line: %d\n"
	.text
	.globl	init_control_store
	.type	init_control_store, @function
init_control_store:
.LFB42:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 256
	mov	QWORD PTR -248[rbp], rdi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rax, QWORD PTR -248[rbp]
	mov	rsi, rax
	lea	rdi, .LC77[rip]
	mov	eax, 0
	call	printf@PLT
	mov	rax, QWORD PTR -248[rbp]
	lea	rsi, .LC78[rip]
	mov	rdi, rax
	call	fopen@PLT
	mov	QWORD PTR -216[rbp], rax
	cmp	QWORD PTR -216[rbp], 0
	jne	.L114
	mov	rax, QWORD PTR -248[rbp]
	mov	rsi, rax
	lea	rdi, .LC79[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, -1
	call	exit@PLT
.L114:
	mov	DWORD PTR -228[rbp], 0
	jmp	.L115
.L122:
	lea	rdx, -208[rbp]
	mov	rax, QWORD PTR -216[rbp]
	lea	rsi, .LC80[rip]
	mov	rdi, rax
	mov	eax, 0
	call	__isoc99_fscanf@PLT
	cmp	eax, -1
	jne	.L116
	mov	rdx, QWORD PTR -248[rbp]
	mov	eax, DWORD PTR -228[rbp]
	mov	esi, eax
	lea	rdi, .LC81[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, -1
	call	exit@PLT
.L116:
	mov	DWORD PTR -220[rbp], 0
	mov	DWORD PTR -224[rbp], 0
	jmp	.L117
.L120:
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	movzx	eax, BYTE PTR -208[rbp+rax]
	test	al, al
	jne	.L118
	mov	edx, DWORD PTR -228[rbp]
	mov	rax, QWORD PTR -248[rbp]
	mov	rsi, rax
	lea	rdi, .LC82[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, -1
	call	exit@PLT
.L118:
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	movzx	eax, BYTE PTR -208[rbp+rax]
	cmp	al, 48
	je	.L119
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	movzx	eax, BYTE PTR -208[rbp+rax]
	cmp	al, 49
	je	.L119
	mov	ecx, DWORD PTR -224[rbp]
	mov	edx, DWORD PTR -228[rbp]
	mov	rax, QWORD PTR -248[rbp]
	mov	rsi, rax
	lea	rdi, .LC83[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, -1
	call	exit@PLT
.L119:
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	movzx	eax, BYTE PTR -208[rbp+rax]
	cmp	al, 48
	setne	al
	movzx	ecx, al
	mov	eax, DWORD PTR -224[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -228[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	sal	rax, 3
	sub	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, CONTROL_STORE[rip]
	mov	DWORD PTR [rdx+rax], ecx
	add	DWORD PTR -220[rbp], 1
	add	DWORD PTR -224[rbp], 1
.L117:
	cmp	DWORD PTR -224[rbp], 22
	jle	.L120
	mov	eax, DWORD PTR -220[rbp]
	cdqe
	movzx	eax, BYTE PTR -208[rbp+rax]
	test	al, al
	je	.L121
	mov	edx, DWORD PTR -228[rbp]
	mov	rax, QWORD PTR -248[rbp]
	mov	rsi, rax
	lea	rdi, .LC84[rip]
	mov	eax, 0
	call	printf@PLT
.L121:
	add	DWORD PTR -228[rbp], 1
.L115:
	cmp	DWORD PTR -228[rbp], 63
	jle	.L122
	mov	edi, 10
	call	putchar@PLT
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L123
	call	__stack_chk_fail@PLT
.L123:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE42:
	.size	init_control_store, .-init_control_store
	.globl	init_memory
	.type	init_memory, @function
init_memory:
.LFB43:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], 0
	jmp	.L125
.L126:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip]
	mov	DWORD PTR [rdx+rax], 0
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip+4]
	mov	DWORD PTR [rdx+rax], 0
	add	DWORD PTR -4[rbp], 1
.L125:
	cmp	DWORD PTR -4[rbp], 32767
	jle	.L126
	nop
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE43:
	.size	init_memory, .-init_memory
	.globl	init_state
	.type	init_state, @function
init_state:
.LFB44:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	edx, 236
	mov	esi, 0
	lea	rdi, PS[rip]
	call	memset@PLT
	mov	edx, 236
	mov	esi, 0
	lea	rdi, NEW_PS[rip]
	call	memset@PLT
	mov	DWORD PTR dep_stall[rip], 0
	mov	DWORD PTR v_de_br_stall[rip], 0
	mov	DWORD PTR v_agex_br_stall[rip], 0
	mov	DWORD PTR v_mem_br_stall[rip], 0
	mov	DWORD PTR mem_stall[rip], 0
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE44:
	.size	init_state, .-init_state
	.section	.rodata
	.align 8
.LC85:
	.string	"Error: Can't open program file %s\n"
.LC86:
	.string	"%x\n"
.LC87:
	.string	"Error: Program file is empty"
	.align 8
.LC88:
	.string	"Error: Program file %s is too long to fit in memory. %x\n"
	.align 8
.LC89:
	.string	"Read %d words from program into memory.\n\n"
	.text
	.globl	load_program
	.type	load_program, @function
load_program:
.LFB45:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 48
	mov	QWORD PTR -40[rbp], rdi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	rax, QWORD PTR -40[rbp]
	lea	rsi, .LC78[rip]
	mov	rdi, rax
	call	fopen@PLT
	mov	QWORD PTR -16[rbp], rax
	cmp	QWORD PTR -16[rbp], 0
	jne	.L129
	mov	rax, QWORD PTR -40[rbp]
	mov	rsi, rax
	lea	rdi, .LC85[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, -1
	call	exit@PLT
.L129:
	lea	rdx, -28[rbp]
	mov	rax, QWORD PTR -16[rbp]
	lea	rsi, .LC86[rip]
	mov	rdi, rax
	mov	eax, 0
	call	__isoc99_fscanf@PLT
	cmp	eax, -1
	je	.L130
	mov	eax, DWORD PTR -28[rbp]
	sar	eax
	mov	DWORD PTR -20[rbp], eax
	mov	DWORD PTR -24[rbp], 0
	jmp	.L132
.L130:
	lea	rdi, .LC87[rip]
	call	puts@PLT
	mov	edi, -1
	call	exit@PLT
.L134:
	mov	edx, DWORD PTR -20[rbp]
	mov	eax, DWORD PTR -24[rbp]
	add	eax, edx
	cmp	eax, 32767
	jle	.L133
	mov	edx, DWORD PTR -24[rbp]
	mov	rax, QWORD PTR -40[rbp]
	mov	rsi, rax
	lea	rdi, .LC88[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, -1
	call	exit@PLT
.L133:
	mov	eax, DWORD PTR -28[rbp]
	mov	ecx, DWORD PTR -20[rbp]
	mov	edx, DWORD PTR -24[rbp]
	add	edx, ecx
	movzx	eax, al
	movsx	rdx, edx
	lea	rcx, 0[0+rdx*8]
	lea	rdx, MEMORY[rip]
	mov	DWORD PTR [rcx+rdx], eax
	mov	eax, DWORD PTR -28[rbp]
	sar	eax, 8
	mov	ecx, DWORD PTR -20[rbp]
	mov	edx, DWORD PTR -24[rbp]
	add	edx, ecx
	movzx	eax, al
	movsx	rdx, edx
	lea	rcx, 0[0+rdx*8]
	lea	rdx, MEMORY[rip+4]
	mov	DWORD PTR [rcx+rdx], eax
	add	DWORD PTR -24[rbp], 1
.L132:
	lea	rdx, -28[rbp]
	mov	rax, QWORD PTR -16[rbp]
	lea	rsi, .LC86[rip]
	mov	rdi, rax
	mov	eax, 0
	call	__isoc99_fscanf@PLT
	cmp	eax, -1
	jne	.L134
	mov	eax, DWORD PTR PC[rip]
	test	eax, eax
	jne	.L135
	mov	eax, DWORD PTR -20[rbp]
	add	eax, eax
	mov	DWORD PTR PC[rip], eax
.L135:
	mov	eax, DWORD PTR -24[rbp]
	mov	esi, eax
	lea	rdi, .LC89[rip]
	mov	eax, 0
	call	printf@PLT
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L136
	call	__stack_chk_fail@PLT
.L136:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE45:
	.size	load_program, .-load_program
	.globl	initialize
	.type	initialize, @function
initialize:
.LFB46:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 48
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -36[rbp], edx
	mov	rax, QWORD PTR -24[rbp]
	mov	rdi, rax
	call	init_control_store
	mov	eax, 0
	call	init_memory
	mov	DWORD PTR -4[rbp], 0
	jmp	.L138
.L140:
	mov	rax, QWORD PTR -32[rbp]
	mov	rdi, rax
	call	load_program
	nop
.L139:
	mov	rax, QWORD PTR -32[rbp]
	lea	rdx, 1[rax]
	mov	QWORD PTR -32[rbp], rdx
	movzx	eax, BYTE PTR [rax]
	test	al, al
	jne	.L139
	add	DWORD PTR -4[rbp], 1
.L138:
	mov	eax, DWORD PTR -4[rbp]
	cmp	eax, DWORD PTR -36[rbp]
	jl	.L140
	mov	eax, 0
	call	init_state
	mov	DWORD PTR RUN_BIT[rip], 1
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE46:
	.size	initialize, .-initialize
	.globl	dcache_access
	.type	dcache_access, @function
dcache_access:
.LFB47:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -24[rbp], edx
	mov	QWORD PTR -40[rbp], rcx
	mov	DWORD PTR -44[rbp], r8d
	mov	DWORD PTR -48[rbp], r9d
	mov	eax, DWORD PTR -20[rbp]
	sar	eax
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR CYCLE_COUNT[rip]
	movsx	rdx, eax
	imul	rdx, rdx, 954437177
	shr	rdx, 32
	sar	edx
	mov	ecx, eax
	sar	ecx, 31
	sub	edx, ecx
	mov	DWORD PTR -4[rbp], edx
	mov	ecx, DWORD PTR -4[rbp]
	mov	edx, ecx
	sal	edx, 3
	add	edx, ecx
	sub	eax, edx
	mov	DWORD PTR -4[rbp], eax
	cmp	DWORD PTR -4[rbp], 0
	jne	.L142
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR [rax], 0
	mov	rax, QWORD PTR -32[rbp]
	mov	DWORD PTR [rax], 65261
	jmp	.L145
.L142:
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR [rax], 1
	mov	eax, DWORD PTR -8[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip+4]
	mov	eax, DWORD PTR [rdx+rax]
	sal	eax, 8
	mov	ecx, eax
	mov	eax, DWORD PTR -8[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip]
	mov	eax, DWORD PTR [rdx+rax]
	movzx	eax, al
	or	ecx, eax
	mov	edx, ecx
	mov	rax, QWORD PTR -32[rbp]
	mov	DWORD PTR [rax], edx
	cmp	DWORD PTR -44[rbp], 0
	je	.L144
	mov	eax, DWORD PTR -24[rbp]
	movzx	eax, al
	mov	edx, DWORD PTR -8[rbp]
	movsx	rdx, edx
	lea	rcx, 0[0+rdx*8]
	lea	rdx, MEMORY[rip]
	mov	DWORD PTR [rcx+rdx], eax
.L144:
	cmp	DWORD PTR -48[rbp], 0
	je	.L145
	mov	eax, DWORD PTR -24[rbp]
	sar	eax, 8
	movzx	eax, al
	mov	edx, DWORD PTR -8[rbp]
	movsx	rdx, edx
	lea	rcx, 0[0+rdx*8]
	lea	rdx, MEMORY[rip+4]
	mov	DWORD PTR [rcx+rdx], eax
.L145:
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE47:
	.size	dcache_access, .-dcache_access
	.globl	icache_access
	.type	icache_access, @function
icache_access:
.LFB48:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	QWORD PTR -32[rbp], rsi
	mov	QWORD PTR -40[rbp], rdx
	mov	eax, DWORD PTR -20[rbp]
	sar	eax
	mov	DWORD PTR -8[rbp], eax
	mov	edx, DWORD PTR CYCLE_COUNT[rip]
	movsx	rax, edx
	imul	rax, rax, 1321528399
	shr	rax, 32
	sar	eax, 2
	mov	ecx, edx
	sar	ecx, 31
	sub	eax, ecx
	mov	DWORD PTR -4[rbp], eax
	mov	ecx, DWORD PTR -4[rbp]
	mov	eax, ecx
	add	eax, eax
	add	eax, ecx
	sal	eax, 2
	add	eax, ecx
	sub	edx, eax
	mov	DWORD PTR -4[rbp], edx
	cmp	DWORD PTR -4[rbp], 0
	jne	.L147
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR [rax], 0
	mov	rax, QWORD PTR -32[rbp]
	mov	DWORD PTR [rax], 65261
	jmp	.L149
.L147:
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR [rax], 1
	mov	eax, DWORD PTR -8[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip+4]
	mov	eax, DWORD PTR [rdx+rax]
	sal	eax, 8
	mov	ecx, eax
	mov	eax, DWORD PTR -8[rbp]
	cdqe
	lea	rdx, 0[0+rax*8]
	lea	rax, MEMORY[rip]
	mov	eax, DWORD PTR [rdx+rax]
	or	ecx, eax
	mov	edx, ecx
	mov	rax, QWORD PTR -32[rbp]
	mov	DWORD PTR [rax], edx
.L149:
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE48:
	.size	icache_access, .-icache_access
	.section	.rodata
	.align 8
.LC90:
	.string	"Error: usage: %s <micro_code_file> <program_file_1> <program_file_2> ...\n"
.LC91:
	.string	"LC-3b Simulator\n"
.LC92:
	.string	"w"
.LC93:
	.string	"dumpsim"
	.align 8
.LC94:
	.string	"Error: Can't open dumpsim file"
	.text
	.globl	main
	.type	main, @function
main:
.LFB49:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 32
	mov	DWORD PTR -20[rbp], edi
	mov	QWORD PTR -32[rbp], rsi
	cmp	DWORD PTR -20[rbp], 2
	jg	.L151
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR [rax]
	mov	rsi, rax
	lea	rdi, .LC90[rip]
	mov	eax, 0
	call	printf@PLT
	mov	edi, 1
	call	exit@PLT
.L151:
	lea	rdi, .LC91[rip]
	call	puts@PLT
	mov	eax, DWORD PTR -20[rbp]
	lea	edx, -2[rax]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, 16
	mov	rcx, QWORD PTR [rax]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, 8
	mov	rax, QWORD PTR [rax]
	mov	rsi, rcx
	mov	rdi, rax
	call	initialize
	lea	rsi, .LC92[rip]
	lea	rdi, .LC93[rip]
	call	fopen@PLT
	mov	QWORD PTR -8[rbp], rax
	cmp	QWORD PTR -8[rbp], 0
	jne	.L152
	lea	rdi, .LC94[rip]
	call	puts@PLT
	mov	edi, -1
	call	exit@PLT
.L152:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	get_command
	jmp	.L152
	.cfi_endproc
.LFE49:
	.size	main, .-main
	.globl	SEXT
	.type	SEXT, @function
SEXT:
.LFB50:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	edx, DWORD PTR -24[rbp]
	mov	eax, 32
	sub	eax, edx
	mov	DWORD PTR -4[rbp], eax
	mov	eax, DWORD PTR -4[rbp]
	mov	edx, DWORD PTR -20[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE50:
	.size	SEXT, .-SEXT
	.globl	ZEXT
	.type	ZEXT, @function
ZEXT:
.LFB51:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	add	eax, 1
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	sub	eax, 1
	and	eax, DWORD PTR -4[rbp]
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE51:
	.size	ZEXT, .-ZEXT
	.globl	RSHF
	.type	RSHF, @function
RSHF:
.LFB52:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	DWORD PTR -24[rbp], esi
	mov	DWORD PTR -28[rbp], edx
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, 1
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	DWORD PTR -4[rbp], eax
	sub	DWORD PTR -4[rbp], 1
	mov	eax, 16
	sub	eax, DWORD PTR -24[rbp]
	mov	ecx, eax
	sal	DWORD PTR -4[rbp], cl
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, DWORD PTR -20[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, DWORD PTR -4[rbp]
	not	eax
	and	edx, eax
	cmp	DWORD PTR -28[rbp], 0
	je	.L158
	mov	eax, DWORD PTR -4[rbp]
	jmp	.L159
.L158:
	mov	eax, 0
.L159:
	or	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE52:
	.size	RSHF, .-RSHF
	.globl	sr_reg_data
	.bss
	.align 4
	.type	sr_reg_data, @object
	.size	sr_reg_data, 4
sr_reg_data:
	.zero	4
	.globl	sr_n
	.align 4
	.type	sr_n, @object
	.size	sr_n, 4
sr_n:
	.zero	4
	.globl	sr_z
	.align 4
	.type	sr_z, @object
	.size	sr_z, 4
sr_z:
	.zero	4
	.globl	sr_p
	.align 4
	.type	sr_p, @object
	.size	sr_p, 4
sr_p:
	.zero	4
	.globl	v_sr_ld_cc
	.align 4
	.type	v_sr_ld_cc, @object
	.size	v_sr_ld_cc, 4
v_sr_ld_cc:
	.zero	4
	.globl	v_sr_ld_reg
	.align 4
	.type	v_sr_ld_reg, @object
	.size	v_sr_ld_reg, 4
v_sr_ld_reg:
	.zero	4
	.globl	sr_reg_id
	.align 4
	.type	sr_reg_id, @object
	.size	sr_reg_id, 4
sr_reg_id:
	.zero	4
	.globl	mem_pcmux
	.align 4
	.type	mem_pcmux, @object
	.size	mem_pcmux, 4
mem_pcmux:
	.zero	4
	.globl	target_pc
	.align 4
	.type	target_pc, @object
	.size	target_pc, 4
target_pc:
	.zero	4
	.globl	trap_pc
	.align 4
	.type	trap_pc, @object
	.size	trap_pc, 4
trap_pc:
	.zero	4
	.globl	v_mem_ld_cc
	.align 4
	.type	v_mem_ld_cc, @object
	.size	v_mem_ld_cc, 4
v_mem_ld_cc:
	.zero	4
	.globl	v_mem_ld_reg
	.align 4
	.type	v_mem_ld_reg, @object
	.size	v_mem_ld_reg, 4
v_mem_ld_reg:
	.zero	4
	.globl	cc_match
	.align 4
	.type	cc_match, @object
	.size	cc_match, 4
cc_match:
	.zero	4
	.globl	v_agex_ld_cc
	.align 4
	.type	v_agex_ld_cc, @object
	.size	v_agex_ld_cc, 4
v_agex_ld_cc:
	.zero	4
	.globl	v_agex_ld_reg
	.align 4
	.type	v_agex_ld_reg, @object
	.size	v_agex_ld_reg, 4
v_agex_ld_reg:
	.zero	4
	.text
	.globl	SR_stage
	.type	SR_stage, @function
SR_stage:
.LFB53:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	lea	rdi, PS[rip+220]
	call	Get_DR_VALUEMUX1
	cmp	eax, 3
	je	.L162
	cmp	eax, 3
	jg	.L163
	cmp	eax, 2
	je	.L164
	cmp	eax, 2
	jg	.L163
	test	eax, eax
	je	.L165
	cmp	eax, 1
	je	.L166
	jmp	.L163
.L165:
	mov	eax, DWORD PTR PS[rip+204]
	mov	DWORD PTR sr_reg_data[rip], eax
	jmp	.L163
.L166:
	mov	eax, DWORD PTR PS[rip+196]
	mov	DWORD PTR sr_reg_data[rip], eax
	jmp	.L163
.L164:
	mov	eax, DWORD PTR PS[rip+192]
	mov	DWORD PTR sr_reg_data[rip], eax
	jmp	.L163
.L162:
	mov	eax, DWORD PTR PS[rip+200]
	mov	DWORD PTR sr_reg_data[rip], eax
	nop
.L163:
	mov	eax, DWORD PTR PS[rip+212]
	mov	DWORD PTR sr_reg_id[rip], eax
	lea	rdi, PS[rip+220]
	call	Get_SR_LD_REG
	mov	edx, DWORD PTR PS[rip+216]
	and	eax, edx
	mov	DWORD PTR v_sr_ld_reg[rip], eax
	lea	rdi, PS[rip+220]
	call	Get_SR_LD_CC
	mov	edx, DWORD PTR PS[rip+216]
	and	eax, edx
	mov	DWORD PTR v_sr_ld_cc[rip], eax
	mov	eax, DWORD PTR sr_reg_data[rip]
	sar	eax, 15
	and	eax, 1
	mov	DWORD PTR sr_n[rip], eax
	mov	eax, DWORD PTR sr_reg_data[rip]
	movzx	eax, ax
	test	eax, eax
	sete	al
	movzx	eax, al
	mov	DWORD PTR sr_z[rip], eax
	mov	DWORD PTR sr_p[rip], 0
	mov	eax, DWORD PTR sr_n[rip]
	test	eax, eax
	jne	.L168
	mov	eax, DWORD PTR sr_z[rip]
	test	eax, eax
	jne	.L168
	mov	DWORD PTR sr_p[rip], 1
.L168:
	nop
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE53:
	.size	SR_stage, .-SR_stage
	.globl	MEM_stage
	.type	MEM_stage, @function
MEM_stage:
.LFB54:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 48
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	lea	rax, PS[rip+148]
	mov	QWORD PTR -16[rbp], rax
	mov	DWORD PTR mem_pcmux[rip], 0
	mov	eax, DWORD PTR PS[rip+136]
	sar	eax, 9
	and	eax, 7
	mov	DWORD PTR -32[rbp], eax
	mov	eax, DWORD PTR -32[rbp]
	and	eax, 1
	test	eax, eax
	je	.L170
	mov	eax, DWORD PTR P[rip]
	test	eax, eax
	jne	.L171
.L170:
	mov	eax, DWORD PTR -32[rbp]
	and	eax, 2
	test	eax, eax
	je	.L172
	mov	eax, DWORD PTR Z[rip]
	test	eax, eax
	jne	.L171
.L172:
	mov	eax, DWORD PTR -32[rbp]
	and	eax, 4
	test	eax, eax
	je	.L173
	mov	eax, DWORD PTR N[rip]
	test	eax, eax
	je	.L173
.L171:
	mov	eax, 1
	jmp	.L174
.L173:
	mov	eax, 0
.L174:
	mov	DWORD PTR cc_match[rip], eax
	mov	eax, DWORD PTR PS[rip+144]
	test	eax, eax
	je	.L175
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_BR_OP
	test	eax, eax
	je	.L176
	mov	eax, DWORD PTR cc_match[rip]
	test	eax, eax
	je	.L177
	mov	DWORD PTR mem_pcmux[rip], 1
	jmp	.L175
.L177:
	mov	DWORD PTR mem_pcmux[rip], 0
	jmp	.L175
.L176:
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_UNCOND_OP
	test	eax, eax
	je	.L178
	mov	eax, DWORD PTR PS[rip+136]
	sar	eax, 11
	and	eax, 1
	mov	DWORD PTR -28[rbp], eax
	mov	DWORD PTR mem_pcmux[rip], 1
	jmp	.L175
.L178:
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_TRAP_OP
	test	eax, eax
	je	.L179
	mov	DWORD PTR mem_pcmux[rip], 2
	jmp	.L175
.L179:
	mov	DWORD PTR mem_pcmux[rip], 0
.L175:
	mov	DWORD PTR v_mem_ld_reg[rip], 0
	mov	DWORD PTR v_mem_br_stall[rip], 0
	mov	DWORD PTR v_mem_ld_cc[rip], 0
	mov	eax, DWORD PTR PS[rip+144]
	test	eax, eax
	je	.L180
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_MEM_LD_CC
	test	eax, eax
	je	.L181
	mov	DWORD PTR v_mem_ld_cc[rip], 1
.L181:
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_MEM_LD_REG
	test	eax, eax
	je	.L182
	mov	DWORD PTR v_mem_ld_reg[rip], 1
.L182:
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_MEM_BR_STALL
	test	eax, eax
	je	.L180
	mov	DWORD PTR v_mem_br_stall[rip], 1
.L180:
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_DCACHE_EN
	test	eax, eax
	je	.L183
	mov	eax, DWORD PTR PS[rip+144]
	test	eax, eax
	je	.L183
	mov	eax, 1
	jmp	.L184
.L183:
	mov	eax, 0
.L184:
	mov	DWORD PTR -24[rbp], eax
	mov	DWORD PTR -48[rbp], 0
	mov	DWORD PTR -20[rbp], 0
	mov	DWORD PTR -44[rbp], 0
	cmp	DWORD PTR -24[rbp], 0
	je	.L185
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_DCACHE_RW
	test	eax, eax
	je	.L186
	mov	eax, DWORD PTR PS[rip+124]
	mov	DWORD PTR -20[rbp], eax
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_DATA_SIZE
	test	eax, eax
	je	.L187
	mov	eax, DWORD PTR PS[rip+128]
	lea	rcx, -44[rbp]
	mov	edx, DWORD PTR -20[rbp]
	lea	rsi, -48[rbp]
	mov	r9d, 1
	mov	r8d, 1
	mov	edi, eax
	call	dcache_access
	jmp	.L185
.L187:
	mov	eax, DWORD PTR PS[rip+128]
	and	eax, 1
	test	eax, eax
	je	.L188
	mov	eax, DWORD PTR -20[rbp]
	sal	eax, 8
	and	eax, 65535
	mov	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR PS[rip+128]
	lea	rcx, -44[rbp]
	mov	edx, DWORD PTR -20[rbp]
	lea	rsi, -48[rbp]
	mov	r9d, 1
	mov	r8d, 0
	mov	edi, eax
	call	dcache_access
	mov	eax, DWORD PTR -48[rbp]
	sar	eax, 8
	movzx	eax, al
	mov	esi, 8
	mov	edi, eax
	call	SEXT
	movzx	eax, ax
	mov	DWORD PTR -48[rbp], eax
	jmp	.L185
.L188:
	mov	eax, DWORD PTR PS[rip+128]
	lea	rcx, -44[rbp]
	mov	edx, DWORD PTR -20[rbp]
	lea	rsi, -48[rbp]
	mov	r9d, 0
	mov	r8d, 1
	mov	edi, eax
	call	dcache_access
	mov	eax, DWORD PTR -48[rbp]
	movzx	eax, al
	mov	esi, 8
	mov	edi, eax
	call	SEXT
	movzx	eax, ax
	mov	DWORD PTR -48[rbp], eax
	jmp	.L185
.L186:
	mov	eax, DWORD PTR PS[rip+128]
	lea	rdx, -44[rbp]
	lea	rsi, -48[rbp]
	mov	r9d, 0
	mov	r8d, 0
	mov	rcx, rdx
	mov	edx, 0
	mov	edi, eax
	call	dcache_access
	mov	rax, QWORD PTR -16[rbp]
	mov	rdi, rax
	call	Get_DATA_SIZE
	test	eax, eax
	jne	.L185
	mov	eax, DWORD PTR PS[rip+128]
	and	eax, 1
	test	eax, eax
	je	.L189
	mov	eax, DWORD PTR -48[rbp]
	sar	eax, 8
	movzx	eax, al
	mov	esi, 8
	mov	edi, eax
	call	SEXT
	movzx	eax, ax
	mov	DWORD PTR -48[rbp], eax
	jmp	.L185
.L189:
	mov	eax, DWORD PTR -48[rbp]
	movzx	eax, al
	mov	esi, 8
	mov	edi, eax
	call	SEXT
	movzx	eax, ax
	mov	DWORD PTR -48[rbp], eax
.L185:
	cmp	DWORD PTR -24[rbp], 0
	je	.L190
	mov	eax, DWORD PTR -44[rbp]
	test	eax, eax
	jne	.L190
	mov	eax, 1
	jmp	.L191
.L190:
	mov	eax, 0
.L191:
	mov	DWORD PTR mem_stall[rip], eax
	mov	eax, DWORD PTR PS[rip+128]
	mov	DWORD PTR target_pc[rip], eax
	mov	eax, DWORD PTR -48[rbp]
	mov	DWORD PTR trap_pc[rip], eax
	mov	eax, DWORD PTR -48[rbp]
	mov	DWORD PTR NEW_PS[rip+196], eax
	mov	DWORD PTR -36[rbp], 0
	mov	DWORD PTR -40[rbp], 7
	jmp	.L192
.L193:
	mov	eax, DWORD PTR -36[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -36[rbp], edx
	mov	edx, DWORD PTR -40[rbp]
	movsx	rdx, edx
	add	rdx, 36
	lea	rcx, 0[0+rdx*4]
	lea	rdx, PS[rip+4]
	mov	edx, DWORD PTR [rcx+rdx]
	cdqe
	add	rax, 52
	lea	rcx, 0[0+rax*4]
	lea	rax, NEW_PS[rip+12]
	mov	DWORD PTR [rcx+rax], edx
	add	DWORD PTR -40[rbp], 1
.L192:
	cmp	DWORD PTR -40[rbp], 10
	jle	.L193
	mov	eax, DWORD PTR PS[rip+128]
	mov	DWORD PTR NEW_PS[rip+204], eax
	mov	eax, DWORD PTR PS[rip+120]
	mov	DWORD PTR NEW_PS[rip+192], eax
	mov	eax, DWORD PTR PS[rip+124]
	mov	DWORD PTR NEW_PS[rip+200], eax
	mov	eax, DWORD PTR PS[rip+136]
	mov	DWORD PTR NEW_PS[rip+208], eax
	mov	eax, DWORD PTR PS[rip+140]
	mov	DWORD PTR NEW_PS[rip+212], eax
	mov	eax, DWORD PTR PS[rip+144]
	test	eax, eax
	je	.L194
	mov	eax, DWORD PTR mem_stall[rip]
	test	eax, eax
	je	.L195
.L194:
	mov	DWORD PTR NEW_PS[rip+216], 0
	jmp	.L196
.L195:
	mov	DWORD PTR NEW_PS[rip+216], 1
.L196:
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L197
	call	__stack_chk_fail@PLT
.L197:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE54:
	.size	MEM_stage, .-MEM_stage
	.globl	AGEX_stage
	.type	AGEX_stage, @function
AGEX_stage:
.LFB55:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 64
	lea	rax, PS[rip+40]
	mov	QWORD PTR -8[rbp], rax
	mov	DWORD PTR v_agex_br_stall[rip], 0
	mov	DWORD PTR v_agex_ld_reg[rip], 0
	mov	DWORD PTR v_agex_ld_cc[rip], 0
	mov	eax, DWORD PTR PS[rip+36]
	test	eax, eax
	je	.L199
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_AGEX_LD_CC
	test	eax, eax
	je	.L200
	mov	DWORD PTR v_agex_ld_cc[rip], 1
.L200:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_AGEX_LD_REG
	test	eax, eax
	je	.L201
	mov	DWORD PTR v_agex_ld_reg[rip], 1
.L201:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_AGEX_BR_STALL
	test	eax, eax
	je	.L199
	mov	DWORD PTR v_agex_br_stall[rip], 1
.L199:
	mov	DWORD PTR -64[rbp], 1
	mov	eax, DWORD PTR mem_stall[rip]
	test	eax, eax
	je	.L202
	mov	DWORD PTR -64[rbp], 0
.L202:
	cmp	DWORD PTR -64[rbp], 0
	je	.L225
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_ADDRESSMUX
	test	eax, eax
	je	.L204
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_ADDR1MUX
	test	eax, eax
	je	.L205
	mov	eax, DWORD PTR PS[rip+16]
	mov	DWORD PTR -56[rbp], eax
	jmp	.L206
.L205:
	mov	eax, DWORD PTR PS[rip+12]
	mov	DWORD PTR -56[rbp], eax
.L206:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_ADDR2MUX
	mov	DWORD PTR -32[rbp], eax
	cmp	DWORD PTR -32[rbp], 0
	jne	.L207
	mov	DWORD PTR -52[rbp], 0
	jmp	.L208
.L207:
	cmp	DWORD PTR -32[rbp], 1
	jne	.L209
	mov	eax, DWORD PTR PS[rip+28]
	and	eax, 63
	mov	esi, 6
	mov	edi, eax
	call	SEXT
	mov	DWORD PTR -52[rbp], eax
	jmp	.L208
.L209:
	cmp	DWORD PTR -32[rbp], 2
	jne	.L210
	mov	eax, DWORD PTR PS[rip+28]
	and	eax, 511
	mov	esi, 9
	mov	edi, eax
	call	SEXT
	mov	DWORD PTR -52[rbp], eax
	jmp	.L208
.L210:
	cmp	DWORD PTR -32[rbp], 3
	jne	.L208
	mov	eax, DWORD PTR PS[rip+28]
	and	eax, 2047
	mov	esi, 11
	mov	edi, eax
	call	SEXT
	mov	DWORD PTR -52[rbp], eax
.L208:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_LSHF1
	test	eax, eax
	je	.L211
	sal	DWORD PTR -52[rbp]
.L211:
	mov	edx, DWORD PTR -56[rbp]
	mov	eax, DWORD PTR -52[rbp]
	add	eax, edx
	and	eax, 65535
	mov	DWORD PTR -60[rbp], eax
	jmp	.L212
.L204:
	mov	eax, DWORD PTR PS[rip+28]
	movzx	eax, al
	mov	esi, 8
	mov	edi, eax
	call	ZEXT
	add	eax, eax
	mov	DWORD PTR -60[rbp], eax
.L212:
	mov	eax, DWORD PTR -60[rbp]
	mov	DWORD PTR NEW_PS[rip+128], eax
	mov	eax, DWORD PTR PS[rip+16]
	mov	DWORD PTR -28[rbp], eax
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_SR2MUX
	cmp	eax, 1
	jne	.L213
	mov	eax, DWORD PTR PS[rip+28]
	and	eax, 31
	mov	esi, 5
	mov	edi, eax
	call	SEXT
	mov	DWORD PTR -48[rbp], eax
	jmp	.L214
.L213:
	mov	eax, DWORD PTR PS[rip+20]
	mov	DWORD PTR -48[rbp], eax
.L214:
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_ALU_RESULTMUX
	test	eax, eax
	je	.L215
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	Get_ALUK
	mov	DWORD PTR -12[rbp], eax
	cmp	DWORD PTR -12[rbp], 0
	jne	.L216
	mov	edx, DWORD PTR -28[rbp]
	mov	eax, DWORD PTR -48[rbp]
	add	eax, edx
	and	eax, 65535
	mov	DWORD PTR -44[rbp], eax
	jmp	.L217
.L216:
	cmp	DWORD PTR -12[rbp], 1
	jne	.L218
	mov	eax, DWORD PTR -28[rbp]
	and	eax, DWORD PTR -48[rbp]
	and	eax, 65535
	mov	DWORD PTR -44[rbp], eax
	jmp	.L217
.L218:
	cmp	DWORD PTR -12[rbp], 2
	jne	.L219
	mov	eax, DWORD PTR -28[rbp]
	xor	eax, DWORD PTR -48[rbp]
	and	eax, 65535
	mov	DWORD PTR -44[rbp], eax
	jmp	.L217
.L219:
	cmp	DWORD PTR -12[rbp], 3
	jne	.L217
	mov	eax, DWORD PTR -48[rbp]
	movzx	eax, ax
	mov	DWORD PTR -44[rbp], eax
	jmp	.L217
.L215:
	mov	eax, DWORD PTR PS[rip+28]
	and	eax, 15
	mov	DWORD PTR -24[rbp], eax
	mov	eax, DWORD PTR PS[rip+28]
	and	eax, 16
	mov	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR PS[rip+28]
	and	eax, 32
	mov	DWORD PTR -16[rbp], eax
	cmp	DWORD PTR -20[rbp], 0
	je	.L220
	cmp	DWORD PTR -16[rbp], 0
	je	.L221
	mov	eax, DWORD PTR -28[rbp]
	sar	eax, 15
	and	eax, 1
	mov	edx, eax
	mov	ecx, DWORD PTR -24[rbp]
	mov	eax, DWORD PTR -28[rbp]
	mov	esi, ecx
	mov	edi, eax
	call	RSHF
	and	eax, 65535
	mov	DWORD PTR -44[rbp], eax
	jmp	.L217
.L221:
	mov	ecx, DWORD PTR -24[rbp]
	mov	eax, DWORD PTR -28[rbp]
	mov	edx, 0
	mov	esi, ecx
	mov	edi, eax
	call	RSHF
	and	eax, 65535
	mov	DWORD PTR -44[rbp], eax
	jmp	.L217
.L220:
	mov	eax, DWORD PTR -24[rbp]
	mov	edx, DWORD PTR -28[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	and	eax, 65535
	mov	DWORD PTR -44[rbp], eax
.L217:
	mov	eax, DWORD PTR -44[rbp]
	mov	DWORD PTR NEW_PS[rip+124], eax
	mov	eax, DWORD PTR PS[rip+28]
	mov	DWORD PTR NEW_PS[rip+136], eax
	mov	eax, DWORD PTR PS[rip+32]
	mov	DWORD PTR NEW_PS[rip+140], eax
	mov	eax, DWORD PTR PS[rip+12]
	mov	DWORD PTR NEW_PS[rip+120], eax
	mov	eax, DWORD PTR PS[rip+24]
	mov	DWORD PTR NEW_PS[rip+132], eax
	mov	DWORD PTR -36[rbp], 0
	mov	DWORD PTR -40[rbp], 9
	jmp	.L222
.L223:
	mov	eax, DWORD PTR -36[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -36[rbp], edx
	mov	edx, DWORD PTR -40[rbp]
	movsx	rdx, edx
	add	rdx, 8
	lea	rcx, 0[0+rdx*4]
	lea	rdx, PS[rip+8]
	mov	edx, DWORD PTR [rcx+rdx]
	cdqe
	add	rax, 36
	lea	rcx, 0[0+rax*4]
	lea	rax, NEW_PS[rip+4]
	mov	DWORD PTR [rcx+rax], edx
	add	DWORD PTR -40[rbp], 1
.L222:
	cmp	DWORD PTR -40[rbp], 19
	jle	.L223
	mov	eax, DWORD PTR PS[rip+36]
	test	eax, eax
	jne	.L224
	mov	DWORD PTR NEW_PS[rip+144], 0
	jmp	.L225
.L224:
	mov	DWORD PTR NEW_PS[rip+144], 1
.L225:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE55:
	.size	AGEX_stage, .-AGEX_stage
	.globl	DE_stage
	.type	DE_stage, @function
DE_stage:
.LFB56:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 48
	mov	eax, DWORD PTR NEW_PS[rip+4]
	sar	eax, 10
	and	eax, 62
	mov	edx, eax
	mov	eax, DWORD PTR NEW_PS[rip+4]
	sar	eax, 5
	and	eax, 1
	or	eax, edx
	mov	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR PS[rip+4]
	sar	eax, 6
	and	eax, 7
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR -16[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, REGS[rip]
	mov	eax, DWORD PTR [rdx+rax]
	mov	DWORD PTR -12[rbp], eax
	mov	eax, DWORD PTR PS[rip+4]
	and	eax, 8192
	test	eax, eax
	je	.L227
	mov	eax, DWORD PTR PS[rip+4]
	sar	eax, 9
	and	eax, 7
	mov	DWORD PTR -40[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, REGS[rip]
	mov	eax, DWORD PTR [rdx+rax]
	mov	DWORD PTR -36[rbp], eax
	jmp	.L228
.L227:
	mov	eax, DWORD PTR PS[rip+4]
	and	eax, 7
	mov	DWORD PTR -40[rbp], eax
	mov	eax, DWORD PTR -40[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	lea	rax, REGS[rip]
	mov	eax, DWORD PTR [rdx+rax]
	mov	DWORD PTR -36[rbp], eax
.L228:
	mov	eax, DWORD PTR v_sr_ld_reg[rip]
	test	eax, eax
	je	.L229
	mov	edx, DWORD PTR sr_reg_id[rip]
	mov	eax, DWORD PTR sr_reg_data[rip]
	movsx	rdx, edx
	lea	rcx, 0[0+rdx*4]
	lea	rdx, REGS[rip]
	mov	DWORD PTR [rcx+rdx], eax
.L229:
	mov	DWORD PTR dep_stall[rip], 0
	mov	eax, DWORD PTR -20[rbp]
	cdqe
	imul	rax, rax, 92
	lea	rdx, CONTROL_STORE[rip]
	mov	eax, DWORD PTR [rax+rdx]
	mov	DWORD PTR -8[rbp], eax
	mov	eax, DWORD PTR -20[rbp]
	cdqe
	imul	rax, rax, 92
	lea	rdx, CONTROL_STORE[rip+4]
	mov	eax, DWORD PTR [rax+rdx]
	mov	DWORD PTR -4[rbp], eax
	cmp	DWORD PTR -8[rbp], 0
	je	.L230
	mov	eax, DWORD PTR PS[rip+32]
	cmp	DWORD PTR -16[rbp], eax
	jne	.L231
	mov	eax, DWORD PTR v_agex_ld_reg[rip]
	test	eax, eax
	jne	.L232
.L231:
	mov	eax, DWORD PTR PS[rip+140]
	cmp	DWORD PTR -16[rbp], eax
	jne	.L233
	mov	eax, DWORD PTR v_mem_ld_reg[rip]
	test	eax, eax
	jne	.L232
.L233:
	mov	eax, DWORD PTR PS[rip+212]
	cmp	DWORD PTR -16[rbp], eax
	jne	.L230
	mov	eax, DWORD PTR v_sr_ld_reg[rip]
	test	eax, eax
	je	.L230
.L232:
	mov	DWORD PTR dep_stall[rip], 1
.L230:
	cmp	DWORD PTR -4[rbp], 0
	je	.L234
	mov	eax, DWORD PTR PS[rip+32]
	cmp	DWORD PTR -40[rbp], eax
	jne	.L235
	mov	eax, DWORD PTR v_agex_ld_reg[rip]
	test	eax, eax
	jne	.L236
.L235:
	mov	eax, DWORD PTR PS[rip+140]
	cmp	DWORD PTR -40[rbp], eax
	jne	.L237
	mov	eax, DWORD PTR v_mem_ld_reg[rip]
	test	eax, eax
	jne	.L236
.L237:
	mov	eax, DWORD PTR PS[rip+212]
	cmp	DWORD PTR -40[rbp], eax
	jne	.L234
	mov	eax, DWORD PTR v_sr_ld_reg[rip]
	test	eax, eax
	je	.L234
.L236:
	mov	DWORD PTR dep_stall[rip], 1
.L234:
	mov	eax, DWORD PTR -20[rbp]
	cdqe
	imul	rax, rax, 92
	lea	rdx, CONTROL_STORE[rip+48]
	mov	eax, DWORD PTR [rax+rdx]
	test	eax, eax
	je	.L238
	mov	eax, DWORD PTR v_agex_ld_cc[rip]
	test	eax, eax
	jne	.L239
	mov	eax, DWORD PTR v_mem_ld_cc[rip]
	test	eax, eax
	jne	.L239
	mov	eax, DWORD PTR v_sr_ld_cc[rip]
	test	eax, eax
	je	.L238
.L239:
	mov	DWORD PTR dep_stall[rip], 1
.L238:
	mov	DWORD PTR v_de_br_stall[rip], 0
	mov	eax, DWORD PTR PS[rip+8]
	test	eax, eax
	je	.L240
	mov	eax, DWORD PTR -20[rbp]
	cdqe
	imul	rax, rax, 92
	lea	rdx, CONTROL_STORE[rip+60]
	mov	eax, DWORD PTR [rax+rdx]
	test	eax, eax
	jne	.L241
	mov	eax, DWORD PTR PS[rip+4]
	cmp	eax, 61477
	jne	.L240
.L241:
	mov	DWORD PTR v_de_br_stall[rip], 1
.L240:
	mov	DWORD PTR -32[rbp], 1
	mov	eax, DWORD PTR mem_stall[rip]
	test	eax, eax
	je	.L242
	mov	DWORD PTR -32[rbp], 0
.L242:
	cmp	DWORD PTR -32[rbp], 0
	je	.L254
	mov	eax, DWORD PTR -12[rbp]
	mov	DWORD PTR NEW_PS[rip+16], eax
	mov	eax, DWORD PTR -36[rbp]
	mov	DWORD PTR NEW_PS[rip+20], eax
	mov	eax, DWORD PTR PS[rip+4]
	mov	DWORD PTR NEW_PS[rip+28], eax
	mov	eax, DWORD PTR PS[rip]
	mov	DWORD PTR NEW_PS[rip+12], eax
	mov	DWORD PTR -28[rbp], 0
	mov	DWORD PTR -24[rbp], 0
	mov	DWORD PTR -28[rbp], 3
	jmp	.L244
.L245:
	mov	ecx, DWORD PTR -24[rbp]
	lea	eax, 1[rcx]
	mov	DWORD PTR -24[rbp], eax
	mov	eax, DWORD PTR -28[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -20[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	add	rax, rax
	add	rax, rdx
	sal	rax, 3
	sub	rax, rdx
	add	rax, rsi
	lea	rdx, 0[0+rax*4]
	lea	rax, CONTROL_STORE[rip]
	mov	eax, DWORD PTR [rdx+rax]
	movsx	rdx, ecx
	add	rdx, 8
	lea	rcx, 0[0+rdx*4]
	lea	rdx, NEW_PS[rip+8]
	mov	DWORD PTR [rcx+rdx], eax
	add	DWORD PTR -28[rbp], 1
.L244:
	cmp	DWORD PTR -28[rbp], 22
	jle	.L245
	mov	eax, DWORD PTR N[rip]
	cmp	eax, 1
	jne	.L246
	mov	DWORD PTR NEW_PS[rip+24], 4
	jmp	.L247
.L246:
	mov	eax, DWORD PTR P[rip]
	cmp	eax, 1
	jne	.L248
	mov	DWORD PTR NEW_PS[rip+24], 1
	jmp	.L247
.L248:
	mov	DWORD PTR NEW_PS[rip+24], 2
.L247:
	lea	rdi, PS[rip+220]
	call	Get_SR_LD_CC
	test	eax, eax
	je	.L249
	mov	eax, DWORD PTR PS[rip+216]
	test	eax, eax
	je	.L249
	mov	eax, DWORD PTR sr_n[rip]
	mov	DWORD PTR N[rip], eax
	mov	eax, DWORD PTR sr_z[rip]
	mov	DWORD PTR Z[rip], eax
	mov	eax, DWORD PTR sr_p[rip]
	mov	DWORD PTR P[rip], eax
.L249:
	mov	eax, DWORD PTR -20[rbp]
	cdqe
	imul	rax, rax, 92
	lea	rdx, CONTROL_STORE[rip+8]
	mov	eax, DWORD PTR [rax+rdx]
	test	eax, eax
	je	.L250
	mov	DWORD PTR NEW_PS[rip+32], 7
	jmp	.L251
.L250:
	mov	eax, DWORD PTR PS[rip+4]
	sar	eax, 9
	and	eax, 7
	mov	DWORD PTR NEW_PS[rip+32], eax
.L251:
	mov	eax, DWORD PTR PS[rip+8]
	test	eax, eax
	je	.L252
	mov	eax, DWORD PTR dep_stall[rip]
	test	eax, eax
	je	.L253
.L252:
	mov	DWORD PTR NEW_PS[rip+36], 0
	jmp	.L254
.L253:
	mov	DWORD PTR NEW_PS[rip+36], 1
.L254:
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE56:
	.size	DE_stage, .-DE_stage
	.globl	FETCH_stage
	.type	FETCH_stage, @function
FETCH_stage:
.LFB57:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 48
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	mov	DWORD PTR -40[rbp], 0
	mov	eax, DWORD PTR PC[rip]
	lea	rcx, -40[rbp]
	lea	rdx, icache_r[rip]
	mov	rsi, rcx
	mov	edi, eax
	call	icache_access
	mov	DWORD PTR -36[rbp], 1
	mov	eax, DWORD PTR dep_stall[rip]
	test	eax, eax
	jne	.L256
	mov	eax, DWORD PTR mem_stall[rip]
	test	eax, eax
	je	.L257
.L256:
	mov	DWORD PTR -36[rbp], 0
.L257:
	cmp	DWORD PTR -36[rbp], 0
	je	.L258
	mov	eax, DWORD PTR -40[rbp]
	mov	DWORD PTR NEW_PS[rip+4], eax
	mov	eax, DWORD PTR PC[rip]
	add	eax, 2
	mov	DWORD PTR NEW_PS[rip], eax
	mov	eax, DWORD PTR v_de_br_stall[rip]
	test	eax, eax
	jne	.L259
	mov	eax, DWORD PTR v_agex_br_stall[rip]
	test	eax, eax
	jne	.L259
	mov	eax, DWORD PTR v_mem_br_stall[rip]
	test	eax, eax
	jne	.L259
	mov	eax, DWORD PTR icache_r[rip]
	test	eax, eax
	jne	.L260
.L259:
	mov	DWORD PTR -32[rbp], 0
	jmp	.L261
.L260:
	mov	DWORD PTR -32[rbp], 1
.L261:
	mov	eax, DWORD PTR -32[rbp]
	mov	DWORD PTR NEW_PS[rip+8], eax
.L258:
	mov	eax, DWORD PTR v_de_br_stall[rip]
	test	eax, eax
	jne	.L262
	mov	eax, DWORD PTR v_agex_br_stall[rip]
	test	eax, eax
	jne	.L262
	mov	eax, DWORD PTR v_mem_br_stall[rip]
	test	eax, eax
	jne	.L262
	mov	eax, DWORD PTR dep_stall[rip]
	test	eax, eax
	jne	.L262
	mov	eax, DWORD PTR mem_stall[rip]
	test	eax, eax
	jne	.L262
	mov	eax, DWORD PTR icache_r[rip]
	test	eax, eax
	je	.L262
	mov	eax, 1
	jmp	.L263
.L262:
	mov	eax, 0
.L263:
	mov	DWORD PTR -24[rbp], eax
	mov	eax, DWORD PTR PS[rip+144]
	test	eax, eax
	je	.L264
	lea	rdi, PS[rip+148]
	call	Get_UNCOND_OP
	test	eax, eax
	je	.L264
	mov	eax, 1
	jmp	.L265
.L264:
	mov	eax, 0
.L265:
	mov	DWORD PTR -20[rbp], eax
	mov	eax, DWORD PTR PS[rip+144]
	test	eax, eax
	je	.L266
	lea	rdi, PS[rip+148]
	call	Get_BR_OP
	test	eax, eax
	je	.L266
	mov	eax, 1
	jmp	.L267
.L266:
	mov	eax, 0
.L267:
	mov	DWORD PTR -16[rbp], eax
	mov	eax, DWORD PTR PS[rip+144]
	test	eax, eax
	je	.L268
	lea	rdi, PS[rip+148]
	call	Get_TRAP_OP
	test	eax, eax
	je	.L268
	mov	eax, 1
	jmp	.L269
.L268:
	mov	eax, 0
.L269:
	mov	DWORD PTR -12[rbp], eax
	mov	DWORD PTR -28[rbp], 0
	cmp	DWORD PTR -24[rbp], 0
	jne	.L270
	cmp	DWORD PTR -12[rbp], 0
	jne	.L270
	cmp	DWORD PTR -20[rbp], 0
	je	.L271
.L270:
	mov	DWORD PTR -28[rbp], 1
	jmp	.L272
.L271:
	cmp	DWORD PTR -16[rbp], 0
	je	.L272
	mov	eax, DWORD PTR cc_match[rip]
	test	eax, eax
	je	.L272
	mov	DWORD PTR -28[rbp], 1
.L272:
	cmp	DWORD PTR -28[rbp], 0
	je	.L277
	mov	eax, DWORD PTR mem_pcmux[rip]
	test	eax, eax
	jne	.L274
	mov	eax, DWORD PTR PC[rip]
	add	eax, 2
	mov	DWORD PTR PC[rip], eax
	jmp	.L277
.L274:
	mov	eax, DWORD PTR mem_pcmux[rip]
	cmp	eax, 1
	jne	.L275
	mov	eax, DWORD PTR target_pc[rip]
	mov	DWORD PTR PC[rip], eax
	jmp	.L277
.L275:
	mov	eax, DWORD PTR mem_pcmux[rip]
	cmp	eax, 2
	jne	.L277
	mov	eax, DWORD PTR trap_pc[rip]
	mov	DWORD PTR PC[rip], eax
.L277:
	nop
	mov	rax, QWORD PTR -8[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L276
	call	__stack_chk_fail@PLT
.L276:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE57:
	.size	FETCH_stage, .-FETCH_stage
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"663963.c"
	.text
	.comm	CS_BITS,4,4
	.comm	AGEX_CS_BITS,4,4
	.comm	MEM_CS_BITS,4,4
	.comm	SR_CS_BITS,4,4
	.align	2
	.global	Get_SR1_NEEDED
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_SR1_NEEDED, %function
Get_SR1_NEEDED:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_SR1_NEEDED, .-Get_SR1_NEEDED
	.align	2
	.global	Get_SR2_NEEDED
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_SR2_NEEDED, %function
Get_SR2_NEEDED:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_SR2_NEEDED, .-Get_SR2_NEEDED
	.align	2
	.global	Get_DRMUX
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_DRMUX, %function
Get_DRMUX:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_DRMUX, .-Get_DRMUX
	.align	2
	.global	Get_DE_BR_OP
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_DE_BR_OP, %function
Get_DE_BR_OP:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #48]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_DE_BR_OP, .-Get_DE_BR_OP
	.align	2
	.global	Get_ADDR1MUX
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_ADDR1MUX, %function
Get_ADDR1MUX:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_ADDR1MUX, .-Get_ADDR1MUX
	.align	2
	.global	Get_ADDR2MUX
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_ADDR2MUX, %function
Get_ADDR2MUX:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	ldr	r3, [r3]
	lsl	r2, r3, #1
	ldr	r3, [fp, #-8]
	add	r3, r3, #8
	ldr	r3, [r3]
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_ADDR2MUX, .-Get_ADDR2MUX
	.align	2
	.global	Get_LSHF1
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_LSHF1, %function
Get_LSHF1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #12]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_LSHF1, .-Get_LSHF1
	.align	2
	.global	Get_ADDRESSMUX
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_ADDRESSMUX, %function
Get_ADDRESSMUX:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #16]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_ADDRESSMUX, .-Get_ADDRESSMUX
	.align	2
	.global	Get_SR2MUX
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_SR2MUX, %function
Get_SR2MUX:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #20]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_SR2MUX, .-Get_SR2MUX
	.align	2
	.global	Get_ALUK
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_ALUK, %function
Get_ALUK:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	add	r3, r3, #24
	ldr	r3, [r3]
	lsl	r2, r3, #1
	ldr	r3, [fp, #-8]
	add	r3, r3, #28
	ldr	r3, [r3]
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_ALUK, .-Get_ALUK
	.align	2
	.global	Get_ALU_RESULTMUX
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_ALU_RESULTMUX, %function
Get_ALU_RESULTMUX:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #32]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_ALU_RESULTMUX, .-Get_ALU_RESULTMUX
	.align	2
	.global	Get_BR_OP
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_BR_OP, %function
Get_BR_OP:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_BR_OP, .-Get_BR_OP
	.align	2
	.global	Get_UNCOND_OP
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_UNCOND_OP, %function
Get_UNCOND_OP:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #4]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_UNCOND_OP, .-Get_UNCOND_OP
	.align	2
	.global	Get_TRAP_OP
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_TRAP_OP, %function
Get_TRAP_OP:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_TRAP_OP, .-Get_TRAP_OP
	.align	2
	.global	Get_DCACHE_EN
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_DCACHE_EN, %function
Get_DCACHE_EN:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #16]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_DCACHE_EN, .-Get_DCACHE_EN
	.align	2
	.global	Get_DCACHE_RW
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_DCACHE_RW, %function
Get_DCACHE_RW:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #20]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_DCACHE_RW, .-Get_DCACHE_RW
	.align	2
	.global	Get_DATA_SIZE
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_DATA_SIZE, %function
Get_DATA_SIZE:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #24]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_DATA_SIZE, .-Get_DATA_SIZE
	.align	2
	.global	Get_DR_VALUEMUX1
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_DR_VALUEMUX1, %function
Get_DR_VALUEMUX1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3]
	lsl	r2, r3, #1
	ldr	r3, [fp, #-8]
	add	r3, r3, #4
	ldr	r3, [r3]
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_DR_VALUEMUX1, .-Get_DR_VALUEMUX1
	.align	2
	.global	Get_AGEX_LD_REG
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_AGEX_LD_REG, %function
Get_AGEX_LD_REG:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #72]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_AGEX_LD_REG, .-Get_AGEX_LD_REG
	.align	2
	.global	Get_AGEX_LD_CC
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_AGEX_LD_CC, %function
Get_AGEX_LD_CC:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #76]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_AGEX_LD_CC, .-Get_AGEX_LD_CC
	.align	2
	.global	Get_MEM_LD_REG
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_MEM_LD_REG, %function
Get_MEM_LD_REG:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #36]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_MEM_LD_REG, .-Get_MEM_LD_REG
	.align	2
	.global	Get_MEM_LD_CC
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_MEM_LD_CC, %function
Get_MEM_LD_CC:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #40]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_MEM_LD_CC, .-Get_MEM_LD_CC
	.align	2
	.global	Get_SR_LD_REG
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_SR_LD_REG, %function
Get_SR_LD_REG:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #8]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_SR_LD_REG, .-Get_SR_LD_REG
	.align	2
	.global	Get_SR_LD_CC
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_SR_LD_CC, %function
Get_SR_LD_CC:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #12]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_SR_LD_CC, .-Get_SR_LD_CC
	.align	2
	.global	Get_DE_BR_STALL
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_DE_BR_STALL, %function
Get_DE_BR_STALL:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #60]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_DE_BR_STALL, .-Get_DE_BR_STALL
	.align	2
	.global	Get_AGEX_BR_STALL
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_AGEX_BR_STALL, %function
Get_AGEX_BR_STALL:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #48]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_AGEX_BR_STALL, .-Get_AGEX_BR_STALL
	.align	2
	.global	Get_MEM_BR_STALL
	.syntax unified
	.arm
	.fpu softvfp
	.type	Get_MEM_BR_STALL, %function
Get_MEM_BR_STALL:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	ldr	r3, [r3, #12]
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	Get_MEM_BR_STALL, .-Get_MEM_BR_STALL
	.comm	CONTROL_STORE,5888,4
	.comm	MEMORY,262144,4
	.global	REGS
	.data
	.align	2
	.type	REGS, %object
	.size	REGS, 32
REGS:
	.word	0
	.word	1
	.word	2
	.word	3
	.word	4
	.word	5
	.word	4666
	.word	43981
	.comm	PC,4,4
	.comm	N,4,4
	.global	Z
	.align	2
	.type	Z, %object
	.size	Z, 4
Z:
	.word	1
	.comm	P,4,4
	.comm	PS,236,4
	.comm	NEW_PS,236,4
	.comm	RUN_BIT,4,4
	.comm	dep_stall,4,4
	.comm	v_de_br_stall,4,4
	.comm	v_agex_br_stall,4,4
	.comm	v_mem_br_stall,4,4
	.comm	mem_stall,4,4
	.comm	icache_r,4,4
	.comm	CYCLE_COUNT,4,4
	.section	.rodata
	.align	2
.LC0:
	.ascii	"----------------LC-3bSIM Help----------------------"
	.ascii	"---\000"
	.align	2
.LC1:
	.ascii	"go               -  run program to completion      "
	.ascii	" \000"
	.align	2
.LC2:
	.ascii	"run n            -  execute program for n cycles   "
	.ascii	" \000"
	.align	2
.LC3:
	.ascii	"mdump low high   -  dump memory from low to high   "
	.ascii	" \000"
	.align	2
.LC4:
	.ascii	"rdump            -  dump the architectural state   "
	.ascii	" \000"
	.align	2
.LC5:
	.ascii	"idump            -  dump the internal state        "
	.ascii	" \000"
	.align	2
.LC6:
	.ascii	"?                -  display this help menu         "
	.ascii	" \000"
	.align	2
.LC7:
	.ascii	"quit             -  exit the program               "
	.ascii	" \012\000"
	.text
	.align	2
	.global	help
	.syntax unified
	.arm
	.fpu softvfp
	.type	help, %function
help:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	ldr	r0, .L56
	bl	puts
	ldr	r0, .L56+4
	bl	puts
	ldr	r0, .L56+8
	bl	puts
	ldr	r0, .L56+12
	bl	puts
	ldr	r0, .L56+16
	bl	puts
	ldr	r0, .L56+20
	bl	puts
	ldr	r0, .L56+24
	bl	puts
	ldr	r0, .L56+28
	bl	puts
	nop
	pop	{fp, pc}
.L57:
	.align	2
.L56:
	.word	.LC0
	.word	.LC1
	.word	.LC2
	.word	.LC3
	.word	.LC4
	.word	.LC5
	.word	.LC6
	.word	.LC7
	.size	help, .-help
	.section	.rodata
	.align	2
.LC8:
	.ascii	"%d\000"
	.text
	.align	2
	.global	print_CS
	.syntax unified
	.arm
	.fpu softvfp
	.type	print_CS, %function
print_CS:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L59
.L60:
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-16]
	add	r3, r2, r3
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L61
	bl	printf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L59:
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-20]
	cmp	r2, r3
	blt	.L60
	mov	r0, #10
	bl	putchar
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L62:
	.align	2
.L61:
	.word	.LC8
	.size	print_CS, .-print_CS
	.align	2
	.global	cycle
	.syntax unified
	.arm
	.fpu softvfp
	.type	cycle, %function
cycle:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	ldr	r2, .L64
	ldr	r3, .L64+4
	mov	r0, r2
	mov	r1, r3
	mov	r3, #236
	mov	r2, r3
	bl	memcpy
	bl	SR_stage
	bl	MEM_stage
	bl	AGEX_stage
	bl	DE_stage
	bl	FETCH_stage
	ldr	r2, .L64+4
	ldr	r3, .L64
	mov	r0, r2
	mov	r1, r3
	mov	r3, #236
	mov	r2, r3
	bl	memcpy
	ldr	r3, .L64+8
	ldr	r3, [r3]
	add	r3, r3, #1
	ldr	r2, .L64+8
	str	r3, [r2]
	nop
	pop	{fp, pc}
.L65:
	.align	2
.L64:
	.word	NEW_PS
	.word	PS
	.word	CYCLE_COUNT
	.size	cycle, .-cycle
	.section	.rodata
	.align	2
.LC9:
	.ascii	"Can't simulate, Simulator is halted\012\000"
	.align	2
.LC10:
	.ascii	"Simulating for %d cycles...\012\012\000"
	.align	2
.LC11:
	.ascii	"Simulator halted\012\000"
	.text
	.align	2
	.global	run
	.syntax unified
	.arm
	.fpu softvfp
	.type	run, %function
run:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	ldr	r3, .L72
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L67
	ldr	r0, .L72+4
	bl	puts
	b	.L66
.L67:
	ldr	r1, [fp, #-16]
	ldr	r0, .L72+8
	bl	printf
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L69
.L71:
	ldr	r3, .L72+12
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L70
	bl	cycle
	ldr	r3, .L72
	mov	r2, #0
	str	r2, [r3]
	ldr	r0, .L72+16
	bl	puts
	b	.L66
.L70:
	bl	cycle
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L69:
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-16]
	cmp	r2, r3
	blt	.L71
.L66:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L73:
	.align	2
.L72:
	.word	RUN_BIT
	.word	.LC9
	.word	.LC10
	.word	PC
	.word	.LC11
	.size	run, .-run
	.section	.rodata
	.align	2
.LC12:
	.ascii	"Simulating...\012\000"
	.text
	.align	2
	.global	go
	.syntax unified
	.arm
	.fpu softvfp
	.type	go, %function
go:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	ldr	r3, .L80
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L75
	ldr	r3, .L80+4
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L76
.L75:
	ldr	r0, .L80+8
	bl	puts
	pop	{fp, pc}
.L76:
	ldr	r0, .L80+12
	bl	puts
	b	.L78
.L79:
	bl	cycle
.L78:
	ldr	r3, .L80+4
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L79
	bl	cycle
	ldr	r3, .L80
	mov	r2, #0
	str	r2, [r3]
	ldr	r0, .L80+16
	bl	puts
	pop	{fp, pc}
.L81:
	.align	2
.L80:
	.word	RUN_BIT
	.word	PC
	.word	.LC9
	.word	.LC12
	.word	.LC11
	.size	go, .-go
	.section	.rodata
	.align	2
.LC13:
	.ascii	"\012Memory content [0x%04x..0x%04x] :\012\000"
	.align	2
.LC14:
	.ascii	"-------------------------------------\000"
	.align	2
.LC15:
	.ascii	"  0x%04x (%d) : 0x%02x%02x\012\000"
	.align	2
.LC16:
	.ascii	"-------------------------------------\012\000"
	.align	2
.LC17:
	.ascii	" 0x%04x (%d) : 0x%02x%02x\012\000"
	.text
	.align	2
	.global	mdump
	.syntax unified
	.arm
	.fpu softvfp
	.type	mdump, %function
mdump:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #32
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	ldr	r2, [fp, #-24]
	ldr	r1, [fp, #-20]
	ldr	r0, .L87
	bl	printf
	ldr	r0, .L87+4
	bl	puts
	ldr	r3, [fp, #-20]
	asr	r3, r3, #1
	str	r3, [fp, #-8]
	b	.L83
.L84:
	ldr	r3, [fp, #-8]
	lsl	r1, r3, #1
	ldr	r3, [fp, #-8]
	lsl	r2, r3, #1
	ldr	r0, .L87+8
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #3
	add	r3, r0, r3
	ldr	r0, [r3, #4]
	ldr	ip, .L87+8
	ldr	r3, [fp, #-8]
	ldr	r3, [ip, r3, lsl #3]
	str	r3, [sp]
	mov	r3, r0
	ldr	r0, .L87+12
	bl	printf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L83:
	ldr	r3, [fp, #-24]
	asr	r3, r3, #1
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	ble	.L84
	mov	r0, #10
	bl	putchar
	ldr	r3, [fp, #-24]
	ldr	r2, [fp, #-20]
	ldr	r1, .L87
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-16]
	mov	r2, #38
	mov	r1, #1
	ldr	r0, .L87+16
	bl	fwrite
	ldr	r3, [fp, #-20]
	asr	r3, r3, #1
	str	r3, [fp, #-8]
	b	.L85
.L86:
	ldr	r3, [fp, #-8]
	lsl	r1, r3, #1
	ldr	r3, [fp, #-8]
	lsl	r0, r3, #1
	ldr	r2, .L87+8
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #3
	add	r3, r2, r3
	ldr	r3, [r3, #4]
	ldr	ip, .L87+8
	ldr	r2, [fp, #-8]
	ldr	r2, [ip, r2, lsl #3]
	str	r2, [sp, #4]
	str	r3, [sp]
	mov	r3, r0
	mov	r2, r1
	ldr	r1, .L87+20
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L85:
	ldr	r3, [fp, #-24]
	asr	r3, r3, #1
	ldr	r2, [fp, #-8]
	cmp	r2, r3
	ble	.L86
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L88:
	.align	2
.L87:
	.word	.LC13
	.word	.LC14
	.word	MEMORY
	.word	.LC15
	.word	.LC16
	.word	.LC17
	.size	mdump, .-mdump
	.section	.rodata
	.align	2
.LC18:
	.ascii	"\012Current architectural state :\000"
	.align	2
.LC19:
	.ascii	"Cycle Count : %d\012\000"
	.align	2
.LC20:
	.ascii	"PC          : 0x%04x\012\000"
	.align	2
.LC21:
	.ascii	"CCs: N = %d  Z = %d  P = %d\012\000"
	.align	2
.LC22:
	.ascii	"Registers:\000"
	.align	2
.LC23:
	.ascii	"%d: 0x%04x\012\000"
	.align	2
.LC24:
	.ascii	"\012Current architectural state :\012\000"
	.align	2
.LC25:
	.ascii	"Registers:\012\000"
	.text
	.align	2
	.global	rdump
	.syntax unified
	.arm
	.fpu softvfp
	.type	rdump, %function
rdump:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r0, [fp, #-16]
	ldr	r0, .L94
	bl	puts
	ldr	r0, .L94+4
	bl	puts
	ldr	r3, .L94+8
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L94+12
	bl	printf
	ldr	r3, .L94+16
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L94+20
	bl	printf
	ldr	r3, .L94+24
	ldr	r1, [r3]
	ldr	r3, .L94+28
	ldr	r2, [r3]
	ldr	r3, .L94+32
	ldr	r3, [r3]
	ldr	r0, .L94+36
	bl	printf
	ldr	r0, .L94+40
	bl	puts
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L90
.L91:
	ldr	r2, .L94+44
	ldr	r3, [fp, #-8]
	ldr	r3, [r2, r3, lsl #2]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r2, r3
	ldr	r1, [fp, #-8]
	ldr	r0, .L94+48
	bl	printf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L90:
	ldr	r3, [fp, #-8]
	cmp	r3, #7
	ble	.L91
	mov	r0, #10
	bl	putchar
	ldr	r3, [fp, #-16]
	mov	r2, #31
	mov	r1, #1
	ldr	r0, .L94+52
	bl	fwrite
	ldr	r3, [fp, #-16]
	mov	r2, #38
	mov	r1, #1
	ldr	r0, .L94+56
	bl	fwrite
	ldr	r3, .L94+8
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L94+12
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L94+16
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L94+20
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L94+24
	ldr	r2, [r3]
	ldr	r3, .L94+28
	ldr	r1, [r3]
	ldr	r3, .L94+32
	ldr	r3, [r3]
	str	r3, [sp]
	mov	r3, r1
	ldr	r1, .L94+36
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-16]
	mov	r2, #11
	mov	r1, #1
	ldr	r0, .L94+60
	bl	fwrite
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L92
.L93:
	ldr	r2, .L94+44
	ldr	r3, [fp, #-8]
	ldr	r3, [r2, r3, lsl #2]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-8]
	ldr	r1, .L94+48
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L92:
	ldr	r3, [fp, #-8]
	cmp	r3, #7
	ble	.L93
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L95:
	.align	2
.L94:
	.word	.LC18
	.word	.LC14
	.word	CYCLE_COUNT
	.word	.LC19
	.word	PC
	.word	.LC20
	.word	N
	.word	Z
	.word	P
	.word	.LC21
	.word	.LC22
	.word	REGS
	.word	.LC23
	.word	.LC24
	.word	.LC16
	.word	.LC25
	.size	rdump, .-rdump
	.section	.rodata
	.align	2
.LC26:
	.ascii	"Cycle Count     : %d\012\000"
	.align	2
.LC27:
	.ascii	"PC              : 0x%04x\012\000"
	.align	2
.LC28:
	.ascii	"------------- Stall Signals -------------\000"
	.align	2
.LC29:
	.ascii	"ICACHE_R        :  %d\012\000"
	.align	2
.LC30:
	.ascii	"DEP_STALL       :  %d\012\000"
	.align	2
.LC31:
	.ascii	"V_DE_BR_STALL   :  %d\012\000"
	.align	2
.LC32:
	.ascii	"V_AGEX_BR_STALL :  %d\012\000"
	.align	2
.LC33:
	.ascii	"MEM_STALL       :  %d\012\000"
	.align	2
.LC34:
	.ascii	"V_MEM_BR_STALL  :  %d\012\000"
	.align	2
.LC35:
	.ascii	"------------- DE   Latches --------------\000"
	.align	2
.LC36:
	.ascii	"DE_NPC          :  0x%04x\012\000"
	.align	2
.LC37:
	.ascii	"DE_IR           :  0x%04x\012\000"
	.align	2
.LC38:
	.ascii	"DE_V            :  %d\012\000"
	.align	2
.LC39:
	.ascii	"------------- AGEX Latches --------------\000"
	.align	2
.LC40:
	.ascii	"AGEX_NPC        :  0x%04x\012\000"
	.align	2
.LC41:
	.ascii	"AGEX_SR1        :  0x%04x\012\000"
	.align	2
.LC42:
	.ascii	"AGEX_SR2        :  0x%04x\012\000"
	.align	2
.LC43:
	.ascii	"AGEX_CC         :  %d\012\000"
	.align	2
.LC44:
	.ascii	"AGEX_IR         :  0x%04x\012\000"
	.align	2
.LC45:
	.ascii	"AGEX_DRID       :  %d\012\000"
	.align	2
.LC46:
	.ascii	"AGEX_CS         :  \000"
	.align	2
.LC47:
	.ascii	"AGEX_V          :  %d\012\000"
	.align	2
.LC48:
	.ascii	"------------- MEM  Latches --------------\000"
	.align	2
.LC49:
	.ascii	"MEM_NPC         :  0x%04x\012\000"
	.align	2
.LC50:
	.ascii	"MEM_ALU_RESULT  :  0x%04x\012\000"
	.align	2
.LC51:
	.ascii	"MEM_ADDRESS     :  0x%04x\012\000"
	.align	2
.LC52:
	.ascii	"MEM_CC          :  %d\012\000"
	.align	2
.LC53:
	.ascii	"MEM_IR          :  0x%04x\012\000"
	.align	2
.LC54:
	.ascii	"MEM_DRID        :  %d\012\000"
	.align	2
.LC55:
	.ascii	"MEM_CS          :  \000"
	.align	2
.LC56:
	.ascii	"MEM_V           :  %d\012\000"
	.align	2
.LC57:
	.ascii	"------------- SR   Latches --------------\000"
	.align	2
.LC58:
	.ascii	"SR_NPC          :  0x%04x\012\000"
	.align	2
.LC59:
	.ascii	"SR_DATA         :  0x%04x\012\000"
	.align	2
.LC60:
	.ascii	"SR_ALU_RESULT   :  0x%04x\012\000"
	.align	2
.LC61:
	.ascii	"SR_ADDRESS      :  0x%04x\012\000"
	.align	2
.LC62:
	.ascii	"SR_IR           :  0x%04x\012\000"
	.align	2
.LC63:
	.ascii	"SR_DRID         :  %d\012\000"
	.align	2
.LC64:
	.ascii	"SR_CS           :  \000"
	.align	2
.LC65:
	.ascii	"SR_V            :  %d\012\000"
	.align	2
.LC66:
	.ascii	"\012Current register/bus values :\012\000"
	.align	2
.LC67:
	.ascii	"------------- Stall Signals -------------\012\000"
	.align	2
.LC68:
	.ascii	"------------- DE   Latches --------------\012\000"
	.align	2
.LC69:
	.ascii	"------------- AGEX Latches --------------\012\000"
	.align	2
.LC70:
	.ascii	"------------- MEM  Latches --------------\012\000"
	.align	2
.LC71:
	.ascii	"------------- SR   Latches --------------\012\000"
	.text
	.align	2
	.global	idump
	.syntax unified
	.arm
	.fpu softvfp
	.type	idump, %function
idump:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r0, [fp, #-16]
	ldr	r0, .L113
	bl	puts
	ldr	r0, .L113+4
	bl	puts
	ldr	r3, .L113+8
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+12
	bl	printf
	ldr	r3, .L113+16
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+20
	bl	printf
	ldr	r3, .L113+24
	ldr	r1, [r3]
	ldr	r3, .L113+28
	ldr	r2, [r3]
	ldr	r3, .L113+32
	ldr	r3, [r3]
	ldr	r0, .L113+36
	bl	printf
	ldr	r0, .L113+40
	bl	puts
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L97
.L98:
	ldr	r2, .L113+44
	ldr	r3, [fp, #-8]
	ldr	r3, [r2, r3, lsl #2]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r2, r3
	ldr	r1, [fp, #-8]
	ldr	r0, .L113+48
	bl	printf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L97:
	ldr	r3, [fp, #-8]
	cmp	r3, #7
	ble	.L98
	mov	r0, #10
	bl	putchar
	ldr	r0, .L113+52
	bl	puts
	ldr	r3, .L113+56
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+60
	bl	printf
	ldr	r3, .L113+64
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+68
	bl	printf
	ldr	r3, .L113+72
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+76
	bl	printf
	ldr	r3, .L113+80
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+84
	bl	printf
	ldr	r3, .L113+88
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+92
	bl	printf
	ldr	r3, .L113+96
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+100
	bl	printf
	mov	r0, #10
	bl	putchar
	ldr	r0, .L113+104
	bl	puts
	ldr	r3, .L113+108
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L113+112
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #4]
	mov	r1, r3
	ldr	r0, .L113+116
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #8]
	mov	r1, r3
	ldr	r0, .L113+120
	bl	printf
	mov	r0, #10
	bl	putchar
	ldr	r0, .L113+124
	bl	puts
	ldr	r3, .L113+108
	ldr	r3, [r3, #12]
	mov	r1, r3
	ldr	r0, .L113+128
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #16]
	mov	r1, r3
	ldr	r0, .L113+132
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #20]
	mov	r1, r3
	ldr	r0, .L113+136
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #24]
	mov	r1, r3
	ldr	r0, .L113+140
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #28]
	mov	r1, r3
	ldr	r0, .L113+144
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #32]
	mov	r1, r3
	ldr	r0, .L113+148
	bl	printf
	ldr	r0, .L113+152
	bl	printf
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L99
.L100:
	ldr	r2, .L113+108
	ldr	r3, [fp, #-8]
	add	r3, r3, #10
	ldr	r3, [r2, r3, lsl #2]
	mov	r1, r3
	ldr	r0, .L113+156
	bl	printf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L99:
	ldr	r3, [fp, #-8]
	cmp	r3, #19
	ble	.L100
	mov	r0, #10
	bl	putchar
	ldr	r3, .L113+108
	ldr	r3, [r3, #36]
	mov	r1, r3
	ldr	r0, .L113+160
	bl	printf
	mov	r0, #10
	bl	putchar
	ldr	r0, .L113+164
	bl	puts
	ldr	r3, .L113+108
	ldr	r3, [r3, #120]
	mov	r1, r3
	ldr	r0, .L113+168
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #124]
	mov	r1, r3
	ldr	r0, .L113+172
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #128]
	mov	r1, r3
	ldr	r0, .L113+176
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #132]
	mov	r1, r3
	ldr	r0, .L113+180
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #136]
	mov	r1, r3
	ldr	r0, .L113+184
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #140]
	mov	r1, r3
	ldr	r0, .L113+188
	bl	printf
	ldr	r0, .L113+192
	bl	printf
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L101
.L102:
	ldr	r2, .L113+108
	ldr	r3, [fp, #-8]
	add	r3, r3, #36
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #4]
	mov	r1, r3
	ldr	r0, .L113+156
	bl	printf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L101:
	ldr	r3, [fp, #-8]
	cmp	r3, #10
	ble	.L102
	mov	r0, #10
	bl	putchar
	ldr	r3, .L113+108
	ldr	r3, [r3, #144]
	mov	r1, r3
	ldr	r0, .L113+196
	bl	printf
	mov	r0, #10
	bl	putchar
	ldr	r0, .L113+200
	bl	puts
	ldr	r3, .L113+108
	ldr	r3, [r3, #192]
	mov	r1, r3
	ldr	r0, .L113+204
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #196]
	mov	r1, r3
	ldr	r0, .L113+208
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #200]
	mov	r1, r3
	ldr	r0, .L113+212
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #204]
	mov	r1, r3
	ldr	r0, .L113+216
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #208]
	mov	r1, r3
	ldr	r0, .L113+220
	bl	printf
	ldr	r3, .L113+108
	ldr	r3, [r3, #212]
	mov	r1, r3
	ldr	r0, .L113+224
	bl	printf
	ldr	r0, .L113+228
	bl	printf
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L103
.L104:
	ldr	r2, .L113+108
	ldr	r3, [fp, #-8]
	add	r3, r3, #54
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #4]
	mov	r1, r3
	ldr	r0, .L113+156
	bl	printf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L103:
	ldr	r3, [fp, #-8]
	cmp	r3, #3
	ble	.L104
	mov	r0, #10
	bl	putchar
	ldr	r3, .L113+108
	ldr	r3, [r3, #216]
	mov	r1, r3
	ldr	r0, .L113+232
	bl	printf
	mov	r0, #10
	bl	putchar
	ldr	r3, [fp, #-16]
	mov	r2, #31
	mov	r1, #1
	ldr	r0, .L113+236
	bl	fwrite
	ldr	r3, [fp, #-16]
	mov	r2, #31
	mov	r1, #1
	ldr	r0, .L113+240
	bl	fwrite
	ldr	r3, [fp, #-16]
	mov	r2, #38
	mov	r1, #1
	ldr	r0, .L113+244
	bl	fwrite
	ldr	r3, .L113+8
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+12
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+16
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+20
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+24
	ldr	r2, [r3]
	ldr	r3, .L113+28
	ldr	r1, [r3]
	ldr	r3, .L113+32
	ldr	r3, [r3]
	str	r3, [sp]
	mov	r3, r1
	ldr	r1, .L113+36
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-16]
	mov	r2, #11
	mov	r1, #1
	ldr	r0, .L113+248
	bl	fwrite
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L105
.L106:
	ldr	r2, .L113+44
	ldr	r3, [fp, #-8]
	ldr	r3, [r2, r3, lsl #2]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-8]
	ldr	r1, .L113+48
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L105:
	ldr	r3, [fp, #-8]
	cmp	r3, #7
	ble	.L106
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	ldr	r3, [fp, #-16]
	mov	r2, #42
	mov	r1, #1
	ldr	r0, .L113+252
	bl	fwrite
	ldr	r3, .L113+56
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+60
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+64
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+68
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+72
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+76
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+80
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+84
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+88
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+92
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+96
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+100
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	ldr	r3, [fp, #-16]
	mov	r2, #42
	mov	r1, #1
	ldr	r0, .L113+256
	bl	fwrite
	ldr	r3, .L113+108
	ldr	r3, [r3]
	mov	r2, r3
	ldr	r1, .L113+112
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #4]
	mov	r2, r3
	ldr	r1, .L113+116
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #8]
	mov	r2, r3
	ldr	r1, .L113+120
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	ldr	r3, [fp, #-16]
	mov	r2, #42
	mov	r1, #1
	ldr	r0, .L113+260
	bl	fwrite
	ldr	r3, .L113+108
	ldr	r3, [r3, #12]
	mov	r2, r3
	ldr	r1, .L113+128
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #16]
	mov	r2, r3
	ldr	r1, .L113+132
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #20]
	mov	r2, r3
	ldr	r1, .L113+136
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #24]
	mov	r2, r3
	ldr	r1, .L113+140
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #28]
	mov	r2, r3
	ldr	r1, .L113+144
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #32]
	mov	r2, r3
	ldr	r1, .L113+148
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-16]
	mov	r2, #19
	mov	r1, #1
	ldr	r0, .L113+152
	bl	fwrite
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L107
.L108:
	ldr	r2, .L113+108
	ldr	r3, [fp, #-8]
	add	r3, r3, #10
	ldr	r3, [r2, r3, lsl #2]
	mov	r2, r3
	ldr	r1, .L113+156
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L107:
	ldr	r3, [fp, #-8]
	cmp	r3, #19
	ble	.L108
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	ldr	r3, .L113+108
	ldr	r3, [r3, #36]
	mov	r2, r3
	ldr	r1, .L113+160
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	ldr	r3, [fp, #-16]
	mov	r2, #42
	mov	r1, #1
	ldr	r0, .L113+264
	bl	fwrite
	ldr	r3, .L113+108
	ldr	r3, [r3, #120]
	mov	r2, r3
	ldr	r1, .L113+168
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #124]
	mov	r2, r3
	ldr	r1, .L113+172
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #128]
	mov	r2, r3
	ldr	r1, .L113+176
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #132]
	mov	r2, r3
	ldr	r1, .L113+180
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #136]
	mov	r2, r3
	ldr	r1, .L113+184
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #140]
	mov	r2, r3
	ldr	r1, .L113+188
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-16]
	mov	r2, #19
	mov	r1, #1
	ldr	r0, .L113+192
	bl	fwrite
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L109
.L110:
	ldr	r2, .L113+108
	ldr	r3, [fp, #-8]
	add	r3, r3, #36
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #4]
	mov	r2, r3
	ldr	r1, .L113+156
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L109:
	ldr	r3, [fp, #-8]
	cmp	r3, #10
	ble	.L110
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	ldr	r3, .L113+108
	ldr	r3, [r3, #144]
	mov	r2, r3
	ldr	r1, .L113+196
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	ldr	r3, [fp, #-16]
	mov	r2, #42
	mov	r1, #1
	ldr	r0, .L113+268
	bl	fwrite
	ldr	r3, .L113+108
	ldr	r3, [r3, #192]
	mov	r2, r3
	ldr	r1, .L113+204
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #196]
	mov	r2, r3
	ldr	r1, .L113+208
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #200]
	mov	r2, r3
	ldr	r1, .L113+212
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #204]
	mov	r2, r3
	ldr	r1, .L113+216
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #208]
	mov	r2, r3
	ldr	r1, .L113+220
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, .L113+108
	ldr	r3, [r3, #212]
	mov	r2, r3
	ldr	r1, .L113+224
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-16]
	mov	r2, #19
	mov	r1, #1
	ldr	r0, .L113+228
	bl	fwrite
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L111
.L112:
	ldr	r2, .L113+108
	ldr	r3, [fp, #-8]
	add	r3, r3, #54
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #4]
	mov	r2, r3
	ldr	r1, .L113+156
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L111:
	ldr	r3, [fp, #-8]
	cmp	r3, #3
	ble	.L112
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	ldr	r3, .L113+108
	ldr	r3, [r3, #216]
	mov	r2, r3
	ldr	r1, .L113+232
	ldr	r0, [fp, #-16]
	bl	fprintf
	ldr	r1, [fp, #-16]
	mov	r0, #10
	bl	fputc
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L114:
	.align	2
.L113:
	.word	.LC18
	.word	.LC14
	.word	CYCLE_COUNT
	.word	.LC26
	.word	PC
	.word	.LC27
	.word	N
	.word	Z
	.word	P
	.word	.LC21
	.word	.LC22
	.word	REGS
	.word	.LC23
	.word	.LC28
	.word	icache_r
	.word	.LC29
	.word	dep_stall
	.word	.LC30
	.word	v_de_br_stall
	.word	.LC31
	.word	v_agex_br_stall
	.word	.LC32
	.word	mem_stall
	.word	.LC33
	.word	v_mem_br_stall
	.word	.LC34
	.word	.LC35
	.word	PS
	.word	.LC36
	.word	.LC37
	.word	.LC38
	.word	.LC39
	.word	.LC40
	.word	.LC41
	.word	.LC42
	.word	.LC43
	.word	.LC44
	.word	.LC45
	.word	.LC46
	.word	.LC8
	.word	.LC47
	.word	.LC48
	.word	.LC49
	.word	.LC50
	.word	.LC51
	.word	.LC52
	.word	.LC53
	.word	.LC54
	.word	.LC55
	.word	.LC56
	.word	.LC57
	.word	.LC58
	.word	.LC59
	.word	.LC60
	.word	.LC61
	.word	.LC62
	.word	.LC63
	.word	.LC64
	.word	.LC65
	.word	.LC66
	.word	.LC24
	.word	.LC16
	.word	.LC25
	.word	.LC67
	.word	.LC68
	.word	.LC69
	.word	.LC70
	.word	.LC71
	.size	idump, .-idump
	.section	.rodata
	.align	2
.LC72:
	.ascii	"LC-3b-SIM> \000"
	.align	2
.LC73:
	.ascii	"%s\000"
	.align	2
.LC74:
	.ascii	"%i %i\000"
	.align	2
.LC75:
	.ascii	"Bye.\000"
	.align	2
.LC76:
	.ascii	"Invalid Command\000"
	.align	2
.LC77:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	get_command
	.syntax unified
	.arm
	.fpu softvfp
	.type	get_command, %function
get_command:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #40
	str	r0, [fp, #-40]
	ldr	r3, .L129
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r0, .L129+4
	bl	printf
	sub	r3, fp, #28
	mov	r1, r3
	ldr	r0, .L129+8
	bl	__isoc99_scanf
	mov	r0, #10
	bl	putchar
	ldrb	r3, [fp, #-28]	@ zero_extendqisi2
	sub	r3, r3, #63
	cmp	r3, #51
	ldrls	pc, [pc, r3, asl #2]
	b	.L116
.L118:
	.word	.L123
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L122
	.word	.L116
	.word	.L121
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L120
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L119
	.word	.L117
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L122
	.word	.L116
	.word	.L121
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L120
	.word	.L116
	.word	.L116
	.word	.L116
	.word	.L119
	.word	.L117
.L122:
	bl	go
	b	.L124
.L120:
	sub	r2, fp, #32
	sub	r3, fp, #36
	mov	r1, r3
	ldr	r0, .L129+12
	bl	__isoc99_scanf
	ldr	r3, [fp, #-36]
	ldr	r2, [fp, #-32]
	mov	r1, r3
	ldr	r0, [fp, #-40]
	bl	mdump
	b	.L124
.L123:
	bl	help
	b	.L124
.L119:
	ldr	r0, .L129+16
	bl	puts
	mov	r0, #0
	bl	exit
.L117:
	ldrb	r3, [fp, #-27]	@ zero_extendqisi2
	cmp	r3, #100
	beq	.L125
	ldrb	r3, [fp, #-27]	@ zero_extendqisi2
	cmp	r3, #68
	bne	.L126
.L125:
	ldr	r0, [fp, #-40]
	bl	rdump
	b	.L124
.L126:
	sub	r3, fp, #32
	mov	r1, r3
	ldr	r0, .L129+20
	bl	__isoc99_scanf
	ldr	r3, [fp, #-32]
	mov	r0, r3
	bl	run
	b	.L124
.L121:
	ldr	r0, [fp, #-40]
	bl	idump
	b	.L124
.L116:
	ldr	r0, .L129+24
	bl	puts
	nop
.L124:
	nop
	ldr	r3, .L129
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L128
	bl	__stack_chk_fail
.L128:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L130:
	.align	2
.L129:
	.word	.LC77
	.word	.LC72
	.word	.LC73
	.word	.LC74
	.word	.LC75
	.word	.LC8
	.word	.LC76
	.size	get_command, .-get_command
	.section	.rodata
	.align	2
.LC78:
	.ascii	"Loading Control Store from file: %s\012\000"
	.align	2
.LC79:
	.ascii	"r\000"
	.align	2
.LC80:
	.ascii	"Error: Can't open micro-code file %s\012\000"
	.align	2
.LC81:
	.ascii	"%[^\012]\012\000"
	.align	2
.LC82:
	.ascii	"Error: Too few lines (%d) in micro-code file: %s\012"
	.ascii	"\000"
	.align	2
.LC83:
	.ascii	"Error: Too few control bits in micro-code file: %s\012"
	.ascii	"Line: %d\012\000"
	.align	2
.LC84:
	.ascii	"Error: Unknown value in micro-code file: %s\012Line"
	.ascii	": %d, Bit: %d\012\000"
	.align	2
.LC85:
	.ascii	"Warning: Extra bit(s) in control store file %s. Lin"
	.ascii	"e: %d\012\000"
	.align	2
.LC86:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	init_control_store
	.syntax unified
	.arm
	.fpu softvfp
	.type	init_control_store, %function
init_control_store:
	@ args = 0, pretend = 0, frame = 232
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #232
	str	r0, [fp, #-232]
	ldr	r3, .L142
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r1, [fp, #-232]
	ldr	r0, .L142+4
	bl	printf
	ldr	r1, .L142+8
	ldr	r0, [fp, #-232]
	bl	fopen
	str	r0, [fp, #-212]
	ldr	r3, [fp, #-212]
	cmp	r3, #0
	bne	.L132
	ldr	r1, [fp, #-232]
	ldr	r0, .L142+12
	bl	printf
	mvn	r0, #0
	bl	exit
.L132:
	mov	r3, #0
	str	r3, [fp, #-224]
	b	.L133
.L140:
	sub	r3, fp, #208
	mov	r2, r3
	ldr	r1, .L142+16
	ldr	r0, [fp, #-212]
	bl	__isoc99_fscanf
	mov	r3, r0
	cmn	r3, #1
	bne	.L134
	ldr	r2, [fp, #-232]
	ldr	r1, [fp, #-224]
	ldr	r0, .L142+20
	bl	printf
	mvn	r0, #0
	bl	exit
.L134:
	mov	r3, #0
	str	r3, [fp, #-216]
	mov	r3, #0
	str	r3, [fp, #-220]
	b	.L135
.L138:
	sub	r2, fp, #208
	ldr	r3, [fp, #-216]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L136
	ldr	r2, [fp, #-224]
	ldr	r1, [fp, #-232]
	ldr	r0, .L142+24
	bl	printf
	mvn	r0, #0
	bl	exit
.L136:
	sub	r2, fp, #208
	ldr	r3, [fp, #-216]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #48
	beq	.L137
	sub	r2, fp, #208
	ldr	r3, [fp, #-216]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #49
	beq	.L137
	ldr	r3, [fp, #-220]
	ldr	r2, [fp, #-224]
	ldr	r1, [fp, #-232]
	ldr	r0, .L142+28
	bl	printf
	mvn	r0, #0
	bl	exit
.L137:
	sub	r2, fp, #208
	ldr	r3, [fp, #-216]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #48
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	ldr	r1, .L142+32
	ldr	r2, [fp, #-224]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	ldr	r2, [fp, #-220]
	add	r3, r3, r2
	str	r0, [r1, r3, lsl #2]
	ldr	r3, [fp, #-216]
	add	r3, r3, #1
	str	r3, [fp, #-216]
	ldr	r3, [fp, #-220]
	add	r3, r3, #1
	str	r3, [fp, #-220]
.L135:
	ldr	r3, [fp, #-220]
	cmp	r3, #22
	ble	.L138
	sub	r2, fp, #208
	ldr	r3, [fp, #-216]
	add	r3, r2, r3
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
	ldr	r2, [fp, #-224]
	ldr	r1, [fp, #-232]
	ldr	r0, .L142+36
	bl	printf
.L139:
	ldr	r3, [fp, #-224]
	add	r3, r3, #1
	str	r3, [fp, #-224]
.L133:
	ldr	r3, [fp, #-224]
	cmp	r3, #63
	ble	.L140
	mov	r0, #10
	bl	putchar
	nop
	ldr	r3, .L142
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L141
	bl	__stack_chk_fail
.L141:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L143:
	.align	2
.L142:
	.word	.LC86
	.word	.LC78
	.word	.LC79
	.word	.LC80
	.word	.LC81
	.word	.LC82
	.word	.LC83
	.word	.LC84
	.word	CONTROL_STORE
	.word	.LC85
	.size	init_control_store, .-init_control_store
	.align	2
	.global	init_memory
	.syntax unified
	.arm
	.fpu softvfp
	.type	init_memory, %function
init_memory:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L145
.L146:
	ldr	r2, .L147
	ldr	r3, [fp, #-8]
	mov	r1, #0
	str	r1, [r2, r3, lsl #3]
	ldr	r2, .L147
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #3
	add	r3, r2, r3
	mov	r2, #0
	str	r2, [r3, #4]
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L145:
	ldr	r3, [fp, #-8]
	cmp	r3, #32768
	blt	.L146
	nop
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L148:
	.align	2
.L147:
	.word	MEMORY
	.size	init_memory, .-init_memory
	.align	2
	.global	init_state
	.syntax unified
	.arm
	.fpu softvfp
	.type	init_state, %function
init_state:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	mov	r2, #236
	mov	r1, #0
	ldr	r0, .L150
	bl	memset
	mov	r2, #236
	mov	r1, #0
	ldr	r0, .L150+4
	bl	memset
	ldr	r3, .L150+8
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L150+12
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L150+16
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L150+20
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L150+24
	mov	r2, #0
	str	r2, [r3]
	nop
	pop	{fp, pc}
.L151:
	.align	2
.L150:
	.word	PS
	.word	NEW_PS
	.word	dep_stall
	.word	v_de_br_stall
	.word	v_agex_br_stall
	.word	v_mem_br_stall
	.word	mem_stall
	.size	init_state, .-init_state
	.section	.rodata
	.align	2
.LC87:
	.ascii	"Error: Can't open program file %s\012\000"
	.align	2
.LC88:
	.ascii	"%x\012\000"
	.align	2
.LC89:
	.ascii	"Error: Program file is empty\000"
	.align	2
.LC90:
	.ascii	"Error: Program file %s is too long to fit in memory"
	.ascii	". %x\012\000"
	.align	2
.LC91:
	.ascii	"Read %d words from program into memory.\012\012\000"
	.align	2
.LC92:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	load_program
	.syntax unified
	.arm
	.fpu softvfp
	.type	load_program, %function
load_program:
	@ args = 0, pretend = 0, frame = 32
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #32
	str	r0, [fp, #-32]
	ldr	r3, .L161
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r1, .L161+4
	ldr	r0, [fp, #-32]
	bl	fopen
	str	r0, [fp, #-16]
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	bne	.L153
	ldr	r1, [fp, #-32]
	ldr	r0, .L161+8
	bl	printf
	mvn	r0, #0
	bl	exit
.L153:
	sub	r3, fp, #24
	mov	r2, r3
	ldr	r1, .L161+12
	ldr	r0, [fp, #-16]
	bl	__isoc99_fscanf
	mov	r3, r0
	cmn	r3, #1
	beq	.L154
	ldr	r3, [fp, #-24]
	asr	r3, r3, #1
	str	r3, [fp, #-12]
	mov	r3, #0
	str	r3, [fp, #-20]
	b	.L156
.L154:
	ldr	r0, .L161+16
	bl	puts
	mvn	r0, #0
	bl	exit
.L158:
	ldr	r2, [fp, #-12]
	ldr	r3, [fp, #-20]
	add	r3, r2, r3
	cmp	r3, #32768
	blt	.L157
	ldr	r2, [fp, #-20]
	ldr	r1, [fp, #-32]
	ldr	r0, .L161+20
	bl	printf
	mvn	r0, #0
	bl	exit
.L157:
	ldr	r2, [fp, #-24]
	ldr	r1, [fp, #-12]
	ldr	r3, [fp, #-20]
	add	r3, r1, r3
	and	r2, r2, #255
	ldr	r1, .L161+24
	str	r2, [r1, r3, lsl #3]
	ldr	r3, [fp, #-24]
	asr	r2, r3, #8
	ldr	r1, [fp, #-12]
	ldr	r3, [fp, #-20]
	add	r3, r1, r3
	and	r2, r2, #255
	ldr	r1, .L161+24
	lsl	r3, r3, #3
	add	r3, r1, r3
	str	r2, [r3, #4]
	ldr	r3, [fp, #-20]
	add	r3, r3, #1
	str	r3, [fp, #-20]
.L156:
	sub	r3, fp, #24
	mov	r2, r3
	ldr	r1, .L161+12
	ldr	r0, [fp, #-16]
	bl	__isoc99_fscanf
	mov	r3, r0
	cmn	r3, #1
	bne	.L158
	ldr	r3, .L161+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L159
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #1
	ldr	r2, .L161+28
	str	r3, [r2]
.L159:
	ldr	r1, [fp, #-20]
	ldr	r0, .L161+32
	bl	printf
	nop
	ldr	r3, .L161
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L160
	bl	__stack_chk_fail
.L160:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L162:
	.align	2
.L161:
	.word	.LC92
	.word	.LC79
	.word	.LC87
	.word	.LC88
	.word	.LC89
	.word	.LC90
	.word	MEMORY
	.word	PC
	.word	.LC91
	.size	load_program, .-load_program
	.align	2
	.global	initialize
	.syntax unified
	.arm
	.fpu softvfp
	.type	initialize, %function
initialize:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #24
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	ldr	r0, [fp, #-16]
	bl	init_control_store
	bl	init_memory
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L164
.L166:
	ldr	r0, [fp, #-20]
	bl	load_program
	nop
.L165:
	ldr	r3, [fp, #-20]
	add	r2, r3, #1
	str	r2, [fp, #-20]
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L165
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L164:
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-24]
	cmp	r2, r3
	blt	.L166
	bl	init_state
	ldr	r3, .L167
	mov	r2, #1
	str	r2, [r3]
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L168:
	.align	2
.L167:
	.word	RUN_BIT
	.size	initialize, .-initialize
	.align	2
	.global	dcache_access
	.syntax unified
	.arm
	.fpu softvfp
	.type	dcache_access, %function
dcache_access:
	@ args = 8, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-16]
	asr	r3, r3, #1
	str	r3, [fp, #-12]
	ldr	r3, .L174
	ldr	r2, [r3]
	ldr	r3, .L174+4
	smull	r1, r3, r2, r3
	asr	r1, r3, #1
	asr	r3, r2, #31
	sub	r1, r1, r3
	mov	r3, r1
	lsl	r3, r3, #3
	add	r3, r3, r1
	sub	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L170
	ldr	r3, [fp, #-28]
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-20]
	ldr	r2, .L174+8
	str	r2, [r3]
	b	.L173
.L170:
	ldr	r3, [fp, #-28]
	mov	r2, #1
	str	r2, [r3]
	ldr	r2, .L174+12
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #3
	add	r3, r2, r3
	ldr	r3, [r3, #4]
	lsl	r2, r3, #8
	ldr	r1, .L174+12
	ldr	r3, [fp, #-12]
	ldr	r3, [r1, r3, lsl #3]
	and	r3, r3, #255
	orr	r2, r2, r3
	ldr	r3, [fp, #-20]
	str	r2, [r3]
	ldr	r3, [fp, #4]
	cmp	r3, #0
	beq	.L172
	ldr	r3, [fp, #-24]
	and	r2, r3, #255
	ldr	r1, .L174+12
	ldr	r3, [fp, #-12]
	str	r2, [r1, r3, lsl #3]
.L172:
	ldr	r3, [fp, #8]
	cmp	r3, #0
	beq	.L173
	ldr	r3, [fp, #-24]
	asr	r3, r3, #8
	and	r2, r3, #255
	ldr	r1, .L174+12
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #3
	add	r3, r1, r3
	str	r2, [r3, #4]
.L173:
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L175:
	.align	2
.L174:
	.word	CYCLE_COUNT
	.word	954437177
	.word	65261
	.word	MEMORY
	.size	dcache_access, .-dcache_access
	.align	2
	.global	icache_access
	.syntax unified
	.arm
	.fpu softvfp
	.type	icache_access, %function
icache_access:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	ldr	r3, [fp, #-16]
	asr	r3, r3, #1
	str	r3, [fp, #-12]
	ldr	r3, .L180
	ldr	r2, [r3]
	ldr	r3, .L180+4
	smull	r1, r3, r2, r3
	asr	r1, r3, #2
	asr	r3, r2, #31
	sub	r1, r1, r3
	mov	r3, r1
	lsl	r3, r3, #1
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r3, r1
	sub	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L177
	ldr	r3, [fp, #-24]
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, [fp, #-20]
	ldr	r2, .L180+8
	str	r2, [r3]
	b	.L179
.L177:
	ldr	r3, [fp, #-24]
	mov	r2, #1
	str	r2, [r3]
	ldr	r2, .L180+12
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #3
	add	r3, r2, r3
	ldr	r3, [r3, #4]
	lsl	r2, r3, #8
	ldr	r1, .L180+12
	ldr	r3, [fp, #-12]
	ldr	r3, [r1, r3, lsl #3]
	orr	r2, r2, r3
	ldr	r3, [fp, #-20]
	str	r2, [r3]
.L179:
	nop
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
.L181:
	.align	2
.L180:
	.word	CYCLE_COUNT
	.word	1321528399
	.word	65261
	.word	MEMORY
	.size	icache_access, .-icache_access
	.section	.rodata
	.align	2
.LC93:
	.ascii	"Error: usage: %s <micro_code_file> <program_file_1>"
	.ascii	" <program_file_2> ...\012\000"
	.align	2
.LC94:
	.ascii	"LC-3b Simulator\012\000"
	.align	2
.LC95:
	.ascii	"w\000"
	.align	2
.LC96:
	.ascii	"dumpsim\000"
	.align	2
.LC97:
	.ascii	"Error: Can't open dumpsim file\000"
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #16
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-16]
	cmp	r3, #2
	bgt	.L183
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, .L185
	bl	printf
	mov	r0, #1
	bl	exit
.L183:
	ldr	r0, .L185+4
	bl	puts
	ldr	r3, [fp, #-20]
	add	r3, r3, #4
	ldr	r0, [r3]
	ldr	r3, [fp, #-20]
	add	r3, r3, #8
	ldr	r1, [r3]
	ldr	r3, [fp, #-16]
	sub	r3, r3, #2
	mov	r2, r3
	bl	initialize
	ldr	r1, .L185+8
	ldr	r0, .L185+12
	bl	fopen
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L184
	ldr	r0, .L185+16
	bl	puts
	mvn	r0, #0
	bl	exit
.L184:
	ldr	r0, [fp, #-8]
	bl	get_command
	b	.L184
.L186:
	.align	2
.L185:
	.word	.LC93
	.word	.LC94
	.word	.LC95
	.word	.LC96
	.word	.LC97
	.size	main, .-main
	.align	2
	.global	SEXT
	.syntax unified
	.arm
	.fpu softvfp
	.type	SEXT, %function
SEXT:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-20]
	rsb	r3, r3, #32
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r3, [fp, #-8]
	asr	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	SEXT, .-SEXT
	.align	2
	.global	ZEXT
	.syntax unified
	.arm
	.fpu softvfp
	.type	ZEXT, %function
ZEXT:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	add	r3, r3, #1
	mov	r2, #1
	lsl	r3, r2, r3
	sub	r2, r3, #1
	ldr	r3, [fp, #-8]
	and	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	ZEXT, .-ZEXT
	.align	2
	.global	RSHF
	.syntax unified
	.arm
	.fpu softvfp
	.type	RSHF, %function
RSHF:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	mov	r2, #1
	ldr	r3, [fp, #-20]
	lsl	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-8]
	sub	r3, r3, #1
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-20]
	rsb	r3, r3, #16
	ldr	r2, [fp, #-8]
	lsl	r3, r2, r3
	str	r3, [fp, #-8]
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-20]
	asr	r2, r2, r3
	ldr	r3, [fp, #-8]
	mvn	r3, r3
	and	r2, r2, r3
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	beq	.L192
	ldr	r3, [fp, #-8]
	b	.L193
.L192:
	mov	r3, #0
.L193:
	orr	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	RSHF, .-RSHF
	.comm	sr_reg_data,4,4
	.comm	sr_n,4,4
	.comm	sr_z,4,4
	.comm	sr_p,4,4
	.comm	v_sr_ld_cc,4,4
	.comm	v_sr_ld_reg,4,4
	.comm	sr_reg_id,4,4
	.global	mem_pcmux
	.bss
	.align	2
	.type	mem_pcmux, %object
	.size	mem_pcmux, 4
mem_pcmux:
	.space	4
	.global	target_pc
	.align	2
	.type	target_pc, %object
	.size	target_pc, 4
target_pc:
	.space	4
	.global	trap_pc
	.align	2
	.type	trap_pc, %object
	.size	trap_pc, 4
trap_pc:
	.space	4
	.global	v_mem_ld_cc
	.align	2
	.type	v_mem_ld_cc, %object
	.size	v_mem_ld_cc, 4
v_mem_ld_cc:
	.space	4
	.global	v_mem_ld_reg
	.align	2
	.type	v_mem_ld_reg, %object
	.size	v_mem_ld_reg, 4
v_mem_ld_reg:
	.space	4
	.global	cc_match
	.align	2
	.type	cc_match, %object
	.size	cc_match, 4
cc_match:
	.space	4
	.global	v_agex_ld_cc
	.align	2
	.type	v_agex_ld_cc, %object
	.size	v_agex_ld_cc, 4
v_agex_ld_cc:
	.space	4
	.global	v_agex_ld_reg
	.align	2
	.type	v_agex_ld_reg, %object
	.size	v_agex_ld_reg, 4
v_agex_ld_reg:
	.space	4
	.text
	.align	2
	.global	SR_stage
	.syntax unified
	.arm
	.fpu softvfp
	.type	SR_stage, %function
SR_stage:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	ldr	r0, .L204
	bl	Get_DR_VALUEMUX1
	mov	r3, r0
	cmp	r3, #3
	ldrls	pc, [pc, r3, asl #2]
	b	.L196
.L198:
	.word	.L201
	.word	.L200
	.word	.L199
	.word	.L197
.L201:
	ldr	r3, .L204+4
	ldr	r3, [r3, #204]
	ldr	r2, .L204+8
	str	r3, [r2]
	b	.L196
.L200:
	ldr	r3, .L204+4
	ldr	r3, [r3, #196]
	ldr	r2, .L204+8
	str	r3, [r2]
	b	.L196
.L199:
	ldr	r3, .L204+4
	ldr	r3, [r3, #192]
	ldr	r2, .L204+8
	str	r3, [r2]
	b	.L196
.L197:
	ldr	r3, .L204+4
	ldr	r3, [r3, #200]
	ldr	r2, .L204+8
	str	r3, [r2]
	nop
.L196:
	ldr	r3, .L204+4
	ldr	r3, [r3, #212]
	ldr	r2, .L204+12
	str	r3, [r2]
	ldr	r0, .L204
	bl	Get_SR_LD_REG
	mov	r2, r0
	ldr	r3, .L204+4
	ldr	r3, [r3, #216]
	and	r3, r3, r2
	ldr	r2, .L204+16
	str	r3, [r2]
	ldr	r0, .L204
	bl	Get_SR_LD_CC
	mov	r2, r0
	ldr	r3, .L204+4
	ldr	r3, [r3, #216]
	and	r3, r3, r2
	ldr	r2, .L204+20
	str	r3, [r2]
	ldr	r3, .L204+8
	ldr	r3, [r3]
	asr	r3, r3, #15
	and	r3, r3, #1
	ldr	r2, .L204+24
	str	r3, [r2]
	ldr	r3, .L204+8
	ldr	r3, [r3]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r2, r3
	ldr	r3, .L204+28
	str	r2, [r3]
	ldr	r3, .L204+32
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L204+24
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L204+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L204+32
	mov	r2, #1
	str	r2, [r3]
.L203:
	nop
	pop	{fp, pc}
.L205:
	.align	2
.L204:
	.word	PS+220
	.word	PS
	.word	sr_reg_data
	.word	sr_reg_id
	.word	v_sr_ld_reg
	.word	v_sr_ld_cc
	.word	sr_n
	.word	sr_z
	.word	sr_p
	.size	SR_stage, .-SR_stage
	.section	.rodata
	.align	2
.LC98:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	MEM_stage
	.syntax unified
	.arm
	.fpu softvfp
	.type	MEM_stage, %function
MEM_stage:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #48
	ldr	r3, .L235
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	ldr	r3, .L235+4
	str	r3, [fp, #-28]
	ldr	r3, .L235+8
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L235+12
	ldr	r3, [r3, #136]
	asr	r3, r3, #9
	and	r3, r3, #7
	str	r3, [fp, #-24]
	ldr	r3, [fp, #-24]
	and	r3, r3, #1
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L235+16
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L208
.L207:
	ldr	r3, [fp, #-24]
	and	r3, r3, #2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L235+20
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L208
.L209:
	ldr	r3, [fp, #-24]
	and	r3, r3, #4
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L235+24
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L210
.L208:
	mov	r3, #1
	b	.L211
.L210:
	mov	r3, #0
.L211:
	ldr	r2, .L235+28
	str	r3, [r2]
	ldr	r3, .L235+12
	ldr	r3, [r3, #144]
	cmp	r3, #0
	beq	.L212
	ldr	r0, [fp, #-28]
	bl	Get_BR_OP
	mov	r3, r0
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L235+28
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L235+8
	mov	r2, #1
	str	r2, [r3]
	b	.L212
.L214:
	ldr	r3, .L235+8
	mov	r2, #0
	str	r2, [r3]
	b	.L212
.L213:
	ldr	r0, [fp, #-28]
	bl	Get_UNCOND_OP
	mov	r3, r0
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L235+12
	ldr	r3, [r3, #136]
	asr	r3, r3, #11
	and	r3, r3, #1
	str	r3, [fp, #-20]
	ldr	r3, .L235+8
	mov	r2, #1
	str	r2, [r3]
	b	.L212
.L215:
	ldr	r0, [fp, #-28]
	bl	Get_TRAP_OP
	mov	r3, r0
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L235+8
	mov	r2, #2
	str	r2, [r3]
	b	.L212
.L216:
	ldr	r3, .L235+8
	mov	r2, #0
	str	r2, [r3]
.L212:
	ldr	r3, .L235+32
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L235+36
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L235+40
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L235+12
	ldr	r3, [r3, #144]
	cmp	r3, #0
	beq	.L217
	ldr	r0, [fp, #-28]
	bl	Get_MEM_LD_CC
	mov	r3, r0
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L235+40
	mov	r2, #1
	str	r2, [r3]
.L218:
	ldr	r0, [fp, #-28]
	bl	Get_MEM_LD_REG
	mov	r3, r0
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L235+32
	mov	r2, #1
	str	r2, [r3]
.L219:
	ldr	r0, [fp, #-28]
	bl	Get_MEM_BR_STALL
	mov	r3, r0
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L235+36
	mov	r2, #1
	str	r2, [r3]
.L217:
	ldr	r0, [fp, #-28]
	bl	Get_DCACHE_EN
	mov	r3, r0
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L235+12
	ldr	r3, [r3, #144]
	cmp	r3, #0
	beq	.L220
	mov	r3, #1
	b	.L221
.L220:
	mov	r3, #0
.L221:
	str	r3, [fp, #-16]
	mov	r3, #0
	str	r3, [fp, #-44]
	mov	r3, #0
	str	r3, [fp, #-12]
	mov	r3, #0
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	beq	.L222
	ldr	r0, [fp, #-28]
	bl	Get_DCACHE_RW
	mov	r3, r0
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L235+12
	ldr	r3, [r3, #124]
	str	r3, [fp, #-12]
	ldr	r0, [fp, #-28]
	bl	Get_DATA_SIZE
	mov	r3, r0
	cmp	r3, #0
	beq	.L224
	ldr	r3, .L235+12
	ldr	r0, [r3, #128]
	sub	r3, fp, #40
	sub	r1, fp, #44
	mov	r2, #1
	str	r2, [sp, #4]
	mov	r2, #1
	str	r2, [sp]
	ldr	r2, [fp, #-12]
	bl	dcache_access
	b	.L222
.L224:
	ldr	r3, .L235+12
	ldr	r3, [r3, #128]
	and	r3, r3, #1
	cmp	r3, #0
	beq	.L225
	ldr	r3, [fp, #-12]
	lsl	r3, r3, #8
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-12]
	ldr	r3, .L235+12
	ldr	r0, [r3, #128]
	sub	r3, fp, #40
	sub	r1, fp, #44
	mov	r2, #1
	str	r2, [sp, #4]
	mov	r2, #0
	str	r2, [sp]
	ldr	r2, [fp, #-12]
	bl	dcache_access
	ldr	r3, [fp, #-44]
	asr	r3, r3, #8
	and	r3, r3, #255
	mov	r1, #8
	mov	r0, r3
	bl	SEXT
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L222
.L225:
	ldr	r3, .L235+12
	ldr	r0, [r3, #128]
	sub	r3, fp, #40
	sub	r1, fp, #44
	mov	r2, #0
	str	r2, [sp, #4]
	mov	r2, #1
	str	r2, [sp]
	ldr	r2, [fp, #-12]
	bl	dcache_access
	ldr	r3, [fp, #-44]
	and	r3, r3, #255
	mov	r1, #8
	mov	r0, r3
	bl	SEXT
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L222
.L223:
	ldr	r3, .L235+12
	ldr	r0, [r3, #128]
	sub	r3, fp, #40
	sub	r1, fp, #44
	mov	r2, #0
	str	r2, [sp, #4]
	mov	r2, #0
	str	r2, [sp]
	mov	r2, #0
	bl	dcache_access
	ldr	r0, [fp, #-28]
	bl	Get_DATA_SIZE
	mov	r3, r0
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L235+12
	ldr	r3, [r3, #128]
	and	r3, r3, #1
	cmp	r3, #0
	beq	.L226
	ldr	r3, [fp, #-44]
	asr	r3, r3, #8
	and	r3, r3, #255
	mov	r1, #8
	mov	r0, r3
	bl	SEXT
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L222
.L226:
	ldr	r3, [fp, #-44]
	and	r3, r3, #255
	mov	r1, #8
	mov	r0, r3
	bl	SEXT
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
.L222:
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	beq	.L227
	ldr	r3, [fp, #-40]
	cmp	r3, #0
	bne	.L227
	mov	r3, #1
	b	.L228
.L227:
	mov	r3, #0
.L228:
	ldr	r2, .L235+44
	str	r3, [r2]
	ldr	r3, .L235+12
	ldr	r3, [r3, #128]
	ldr	r2, .L235+48
	str	r3, [r2]
	ldr	r3, [fp, #-44]
	ldr	r2, .L235+52
	str	r3, [r2]
	ldr	r3, [fp, #-44]
	ldr	r2, .L235+56
	str	r3, [r2, #196]
	mov	r3, #0
	str	r3, [fp, #-32]
	mov	r3, #7
	str	r3, [fp, #-36]
	b	.L229
.L230:
	ldr	r2, [fp, #-32]
	add	r3, r2, #1
	str	r3, [fp, #-32]
	ldr	r1, .L235+12
	ldr	r3, [fp, #-36]
	add	r3, r3, #36
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #4]
	ldr	r0, .L235+56
	add	r3, r2, #54
	lsl	r3, r3, #2
	add	r3, r0, r3
	str	r1, [r3, #4]
	ldr	r3, [fp, #-36]
	add	r3, r3, #1
	str	r3, [fp, #-36]
.L229:
	ldr	r3, [fp, #-36]
	cmp	r3, #10
	ble	.L230
	ldr	r3, .L235+12
	ldr	r3, [r3, #128]
	ldr	r2, .L235+56
	str	r3, [r2, #204]
	ldr	r3, .L235+12
	ldr	r3, [r3, #120]
	ldr	r2, .L235+56
	str	r3, [r2, #192]
	ldr	r3, .L235+12
	ldr	r3, [r3, #124]
	ldr	r2, .L235+56
	str	r3, [r2, #200]
	ldr	r3, .L235+12
	ldr	r3, [r3, #136]
	ldr	r2, .L235+56
	str	r3, [r2, #208]
	ldr	r3, .L235+12
	ldr	r3, [r3, #140]
	ldr	r2, .L235+56
	str	r3, [r2, #212]
	ldr	r3, .L235+12
	ldr	r3, [r3, #144]
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L235+44
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L232
.L231:
	ldr	r3, .L235+56
	mov	r2, #0
	str	r2, [r3, #216]
	b	.L233
.L232:
	ldr	r3, .L235+56
	mov	r2, #1
	str	r2, [r3, #216]
.L233:
	nop
	ldr	r3, .L235
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L234
	bl	__stack_chk_fail
.L234:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L236:
	.align	2
.L235:
	.word	.LC98
	.word	PS+148
	.word	mem_pcmux
	.word	PS
	.word	P
	.word	Z
	.word	N
	.word	cc_match
	.word	v_mem_ld_reg
	.word	v_mem_br_stall
	.word	v_mem_ld_cc
	.word	mem_stall
	.word	target_pc
	.word	trap_pc
	.word	NEW_PS
	.size	MEM_stage, .-MEM_stage
	.align	2
	.global	AGEX_stage
	.syntax unified
	.arm
	.fpu softvfp
	.type	AGEX_stage, %function
AGEX_stage:
	@ args = 0, pretend = 0, frame = 64
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #64
	ldr	r3, .L265
	str	r3, [fp, #-32]
	ldr	r3, .L265+4
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L265+8
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L265+12
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L265+16
	ldr	r3, [r3, #36]
	cmp	r3, #0
	beq	.L238
	ldr	r0, [fp, #-32]
	bl	Get_AGEX_LD_CC
	mov	r3, r0
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L265+12
	mov	r2, #1
	str	r2, [r3]
.L239:
	ldr	r0, [fp, #-32]
	bl	Get_AGEX_LD_REG
	mov	r3, r0
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L265+8
	mov	r2, #1
	str	r2, [r3]
.L240:
	ldr	r0, [fp, #-32]
	bl	Get_AGEX_BR_STALL
	mov	r3, r0
	cmp	r3, #0
	beq	.L238
	ldr	r3, .L265+4
	mov	r2, #1
	str	r2, [r3]
.L238:
	mov	r3, #1
	str	r3, [fp, #-64]
	ldr	r3, .L265+20
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L241
	mov	r3, #0
	str	r3, [fp, #-64]
.L241:
	ldr	r3, [fp, #-64]
	cmp	r3, #0
	beq	.L264
	ldr	r0, [fp, #-32]
	bl	Get_ADDRESSMUX
	mov	r3, r0
	cmp	r3, #0
	beq	.L243
	ldr	r0, [fp, #-32]
	bl	Get_ADDR1MUX
	mov	r3, r0
	cmp	r3, #0
	beq	.L244
	ldr	r3, .L265+16
	ldr	r3, [r3, #16]
	str	r3, [fp, #-56]
	b	.L245
.L244:
	ldr	r3, .L265+16
	ldr	r3, [r3, #12]
	str	r3, [fp, #-56]
.L245:
	ldr	r0, [fp, #-32]
	bl	Get_ADDR2MUX
	str	r0, [fp, #-28]
	ldr	r3, [fp, #-28]
	cmp	r3, #0
	bne	.L246
	mov	r3, #0
	str	r3, [fp, #-52]
	b	.L247
.L246:
	ldr	r3, [fp, #-28]
	cmp	r3, #1
	bne	.L248
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	and	r3, r3, #63
	mov	r1, #6
	mov	r0, r3
	bl	SEXT
	str	r0, [fp, #-52]
	b	.L247
.L248:
	ldr	r3, [fp, #-28]
	cmp	r3, #2
	bne	.L249
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	lsl	r3, r3, #23
	lsr	r3, r3, #23
	mov	r1, #9
	mov	r0, r3
	bl	SEXT
	str	r0, [fp, #-52]
	b	.L247
.L249:
	ldr	r3, [fp, #-28]
	cmp	r3, #3
	bne	.L247
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	lsl	r3, r3, #21
	lsr	r3, r3, #21
	mov	r1, #11
	mov	r0, r3
	bl	SEXT
	str	r0, [fp, #-52]
.L247:
	ldr	r0, [fp, #-32]
	bl	Get_LSHF1
	mov	r3, r0
	cmp	r3, #0
	beq	.L250
	ldr	r3, [fp, #-52]
	lsl	r3, r3, #1
	str	r3, [fp, #-52]
.L250:
	ldr	r2, [fp, #-56]
	ldr	r3, [fp, #-52]
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-60]
	b	.L251
.L243:
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	and	r3, r3, #255
	mov	r1, #8
	mov	r0, r3
	bl	ZEXT
	mov	r3, r0
	lsl	r3, r3, #1
	str	r3, [fp, #-60]
.L251:
	ldr	r2, .L265+24
	ldr	r3, [fp, #-60]
	str	r3, [r2, #128]
	ldr	r3, .L265+16
	ldr	r3, [r3, #16]
	str	r3, [fp, #-24]
	ldr	r0, [fp, #-32]
	bl	Get_SR2MUX
	mov	r3, r0
	cmp	r3, #1
	bne	.L252
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	and	r3, r3, #31
	mov	r1, #5
	mov	r0, r3
	bl	SEXT
	str	r0, [fp, #-48]
	b	.L253
.L252:
	ldr	r3, .L265+16
	ldr	r3, [r3, #20]
	str	r3, [fp, #-48]
.L253:
	ldr	r0, [fp, #-32]
	bl	Get_ALU_RESULTMUX
	mov	r3, r0
	cmp	r3, #0
	beq	.L254
	ldr	r0, [fp, #-32]
	bl	Get_ALUK
	str	r0, [fp, #-8]
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	bne	.L255
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-48]
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L256
.L255:
	ldr	r3, [fp, #-8]
	cmp	r3, #1
	bne	.L257
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-48]
	and	r3, r3, r2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L256
.L257:
	ldr	r3, [fp, #-8]
	cmp	r3, #2
	bne	.L258
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-48]
	eor	r3, r3, r2
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L256
.L258:
	ldr	r3, [fp, #-8]
	cmp	r3, #3
	bne	.L256
	ldr	r3, [fp, #-48]
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L256
.L254:
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	and	r3, r3, #15
	str	r3, [fp, #-20]
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	and	r3, r3, #16
	str	r3, [fp, #-16]
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	and	r3, r3, #32
	str	r3, [fp, #-12]
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	beq	.L259
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	beq	.L260
	ldr	r3, [fp, #-24]
	asr	r3, r3, #15
	and	r3, r3, #1
	mov	r2, r3
	ldr	r1, [fp, #-20]
	ldr	r0, [fp, #-24]
	bl	RSHF
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L256
.L260:
	mov	r2, #0
	ldr	r1, [fp, #-20]
	ldr	r0, [fp, #-24]
	bl	RSHF
	mov	r3, r0
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
	b	.L256
.L259:
	ldr	r2, [fp, #-24]
	ldr	r3, [fp, #-20]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	str	r3, [fp, #-44]
.L256:
	ldr	r2, .L265+24
	ldr	r3, [fp, #-44]
	str	r3, [r2, #124]
	ldr	r3, .L265+16
	ldr	r3, [r3, #28]
	ldr	r2, .L265+24
	str	r3, [r2, #136]
	ldr	r3, .L265+16
	ldr	r3, [r3, #32]
	ldr	r2, .L265+24
	str	r3, [r2, #140]
	ldr	r3, .L265+16
	ldr	r3, [r3, #12]
	ldr	r2, .L265+24
	str	r3, [r2, #120]
	ldr	r3, .L265+16
	ldr	r3, [r3, #24]
	ldr	r2, .L265+24
	str	r3, [r2, #132]
	mov	r3, #0
	str	r3, [fp, #-36]
	mov	r3, #9
	str	r3, [fp, #-40]
	b	.L261
.L262:
	ldr	r3, [fp, #-36]
	add	r2, r3, #1
	str	r2, [fp, #-36]
	ldr	r1, .L265+16
	ldr	r2, [fp, #-40]
	add	r2, r2, #10
	ldr	r2, [r1, r2, lsl #2]
	ldr	r1, .L265+24
	add	r3, r3, #36
	lsl	r3, r3, #2
	add	r3, r1, r3
	str	r2, [r3, #4]
	ldr	r3, [fp, #-40]
	add	r3, r3, #1
	str	r3, [fp, #-40]
.L261:
	ldr	r3, [fp, #-40]
	cmp	r3, #19
	ble	.L262
	ldr	r3, .L265+16
	ldr	r3, [r3, #36]
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L265+24
	mov	r2, #0
	str	r2, [r3, #144]
	b	.L264
.L263:
	ldr	r3, .L265+24
	mov	r2, #1
	str	r2, [r3, #144]
.L264:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L266:
	.align	2
.L265:
	.word	PS+40
	.word	v_agex_br_stall
	.word	v_agex_ld_reg
	.word	v_agex_ld_cc
	.word	PS
	.word	mem_stall
	.word	NEW_PS
	.size	AGEX_stage, .-AGEX_stage
	.align	2
	.global	DE_stage
	.syntax unified
	.arm
	.fpu softvfp
	.type	DE_stage, %function
DE_stage:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #40
	ldr	r3, .L296
	ldr	r3, [r3, #4]
	asr	r3, r3, #10
	and	r2, r3, #62
	ldr	r3, .L296
	ldr	r3, [r3, #4]
	asr	r3, r3, #5
	and	r3, r3, #1
	orr	r3, r2, r3
	str	r3, [fp, #-24]
	ldr	r3, .L296+4
	ldr	r3, [r3, #4]
	asr	r3, r3, #6
	and	r3, r3, #7
	str	r3, [fp, #-20]
	ldr	r2, .L296+8
	ldr	r3, [fp, #-20]
	ldr	r3, [r2, r3, lsl #2]
	str	r3, [fp, #-16]
	ldr	r3, .L296+4
	ldr	r3, [r3, #4]
	and	r3, r3, #8192
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L296+4
	ldr	r3, [r3, #4]
	asr	r3, r3, #9
	and	r3, r3, #7
	str	r3, [fp, #-44]
	ldr	r2, .L296+8
	ldr	r3, [fp, #-44]
	ldr	r3, [r2, r3, lsl #2]
	str	r3, [fp, #-40]
	b	.L269
.L268:
	ldr	r3, .L296+4
	ldr	r3, [r3, #4]
	and	r3, r3, #7
	str	r3, [fp, #-44]
	ldr	r2, .L296+8
	ldr	r3, [fp, #-44]
	ldr	r3, [r2, r3, lsl #2]
	str	r3, [fp, #-40]
.L269:
	ldr	r3, .L296+12
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L270
	ldr	r3, .L296+16
	ldr	r3, [r3]
	ldr	r2, .L296+20
	ldr	r2, [r2]
	ldr	r1, .L296+8
	str	r2, [r1, r3, lsl #2]
.L270:
	ldr	r3, .L296+24
	mov	r2, #0
	str	r2, [r3]
	ldr	r1, .L296+28
	ldr	r2, [fp, #-24]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3]
	str	r3, [fp, #-12]
	ldr	r1, .L296+28
	ldr	r2, [fp, #-24]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	add	r3, r3, #4
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L296+4
	ldr	r3, [r3, #32]
	ldr	r2, [fp, #-20]
	cmp	r2, r3
	bne	.L272
	ldr	r3, .L296+32
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L273
.L272:
	ldr	r3, .L296+4
	ldr	r3, [r3, #140]
	ldr	r2, [fp, #-20]
	cmp	r2, r3
	bne	.L274
	ldr	r3, .L296+36
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L273
.L274:
	ldr	r3, .L296+4
	ldr	r3, [r3, #212]
	ldr	r2, [fp, #-20]
	cmp	r2, r3
	bne	.L271
	ldr	r3, .L296+12
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L271
.L273:
	ldr	r3, .L296+24
	mov	r2, #1
	str	r2, [r3]
.L271:
	ldr	r3, [fp, #-8]
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L296+4
	ldr	r3, [r3, #32]
	ldr	r2, [fp, #-44]
	cmp	r2, r3
	bne	.L276
	ldr	r3, .L296+32
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L277
.L276:
	ldr	r3, .L296+4
	ldr	r3, [r3, #140]
	ldr	r2, [fp, #-44]
	cmp	r2, r3
	bne	.L278
	ldr	r3, .L296+36
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L277
.L278:
	ldr	r3, .L296+4
	ldr	r3, [r3, #212]
	ldr	r2, [fp, #-44]
	cmp	r2, r3
	bne	.L275
	ldr	r3, .L296+12
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L275
.L277:
	ldr	r3, .L296+24
	mov	r2, #1
	str	r2, [r3]
.L275:
	ldr	r1, .L296+28
	ldr	r2, [fp, #-24]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	add	r3, r3, #48
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L296+40
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L296+44
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L280
	ldr	r3, .L296+48
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L279
.L280:
	ldr	r3, .L296+24
	mov	r2, #1
	str	r2, [r3]
.L279:
	ldr	r3, .L296+52
	mov	r2, #0
	str	r2, [r3]
	ldr	r3, .L296+4
	ldr	r3, [r3, #8]
	cmp	r3, #0
	beq	.L281
	ldr	r1, .L296+28
	ldr	r2, [fp, #-24]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	add	r3, r3, #60
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L282
	ldr	r3, .L296+4
	ldr	r3, [r3, #4]
	ldr	r2, .L296+56
	cmp	r3, r2
	bne	.L281
.L282:
	ldr	r3, .L296+52
	mov	r2, #1
	str	r2, [r3]
.L281:
	mov	r3, #1
	str	r3, [fp, #-36]
	ldr	r3, .L296+60
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L283
	mov	r3, #0
	str	r3, [fp, #-36]
.L283:
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	beq	.L295
	ldr	r2, .L296
	ldr	r3, [fp, #-16]
	str	r3, [r2, #16]
	ldr	r2, .L296
	ldr	r3, [fp, #-40]
	str	r3, [r2, #20]
	ldr	r3, .L296+4
	ldr	r3, [r3, #4]
	ldr	r2, .L296
	str	r3, [r2, #28]
	ldr	r3, .L296+4
	ldr	r3, [r3]
	ldr	r2, .L296
	str	r3, [r2, #12]
	mov	r3, #0
	str	r3, [fp, #-32]
	mov	r3, #0
	str	r3, [fp, #-28]
	mov	r3, #3
	str	r3, [fp, #-32]
	b	.L285
.L286:
	ldr	r1, [fp, #-28]
	add	r3, r1, #1
	str	r3, [fp, #-28]
	ldr	r0, .L296+28
	ldr	r2, [fp, #-24]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	ldr	r2, [fp, #-32]
	add	r3, r3, r2
	ldr	r2, [r0, r3, lsl #2]
	ldr	r0, .L296
	add	r3, r1, #10
	str	r2, [r0, r3, lsl #2]
	ldr	r3, [fp, #-32]
	add	r3, r3, #1
	str	r3, [fp, #-32]
.L285:
	ldr	r3, [fp, #-32]
	cmp	r3, #22
	ble	.L286
	ldr	r3, .L296+64
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L287
	ldr	r3, .L296
	mov	r2, #4
	str	r2, [r3, #24]
	b	.L288
.L287:
	ldr	r3, .L296+68
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L289
	ldr	r3, .L296
	mov	r2, #1
	str	r2, [r3, #24]
	b	.L288
.L289:
	ldr	r3, .L296
	mov	r2, #2
	str	r2, [r3, #24]
.L288:
	ldr	r0, .L296+72
	bl	Get_SR_LD_CC
	mov	r3, r0
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L296+4
	ldr	r3, [r3, #216]
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L296+76
	ldr	r3, [r3]
	ldr	r2, .L296+64
	str	r3, [r2]
	ldr	r3, .L296+80
	ldr	r3, [r3]
	ldr	r2, .L296+84
	str	r3, [r2]
	ldr	r3, .L296+88
	ldr	r3, [r3]
	ldr	r2, .L296+68
	str	r3, [r2]
.L290:
	ldr	r1, .L296+28
	ldr	r2, [fp, #-24]
	mov	r3, r2
	lsl	r3, r3, #1
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	add	r3, r3, #8
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L296
	mov	r2, #7
	str	r2, [r3, #32]
	b	.L292
.L291:
	ldr	r3, .L296+4
	ldr	r3, [r3, #4]
	asr	r3, r3, #9
	and	r3, r3, #7
	ldr	r2, .L296
	str	r3, [r2, #32]
.L292:
	ldr	r3, .L296+4
	ldr	r3, [r3, #8]
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L296+24
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L294
.L293:
	ldr	r3, .L296
	mov	r2, #0
	str	r2, [r3, #36]
	b	.L295
.L294:
	ldr	r3, .L296
	mov	r2, #1
	str	r2, [r3, #36]
.L295:
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L297:
	.align	2
.L296:
	.word	NEW_PS
	.word	PS
	.word	REGS
	.word	v_sr_ld_reg
	.word	sr_reg_id
	.word	sr_reg_data
	.word	dep_stall
	.word	CONTROL_STORE
	.word	v_agex_ld_reg
	.word	v_mem_ld_reg
	.word	v_agex_ld_cc
	.word	v_mem_ld_cc
	.word	v_sr_ld_cc
	.word	v_de_br_stall
	.word	61477
	.word	mem_stall
	.word	N
	.word	P
	.word	PS+220
	.word	sr_n
	.word	sr_z
	.word	Z
	.word	sr_p
	.size	DE_stage, .-DE_stage
	.section	.rodata
	.align	2
.LC99:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	FETCH_stage
	.syntax unified
	.arm
	.fpu softvfp
	.type	FETCH_stage, %function
FETCH_stage:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #40
	ldr	r3, .L321
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	mov	r3, #0
	str	r3, [fp, #-40]
	ldr	r3, .L321+4
	ldr	r3, [r3]
	sub	r1, fp, #40
	ldr	r2, .L321+8
	mov	r0, r3
	bl	icache_access
	mov	r3, #1
	str	r3, [fp, #-36]
	ldr	r3, .L321+12
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L321+16
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L300
.L299:
	mov	r3, #0
	str	r3, [fp, #-36]
.L300:
	ldr	r3, [fp, #-36]
	cmp	r3, #0
	beq	.L301
	ldr	r3, [fp, #-40]
	ldr	r2, .L321+20
	str	r3, [r2, #4]
	ldr	r3, .L321+4
	ldr	r3, [r3]
	add	r3, r3, #2
	ldr	r2, .L321+20
	str	r3, [r2]
	ldr	r3, .L321+24
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L321+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L321+32
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L321+8
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L303
.L302:
	mov	r3, #0
	str	r3, [fp, #-32]
	b	.L304
.L303:
	mov	r3, #1
	str	r3, [fp, #-32]
.L304:
	ldr	r2, .L321+20
	ldr	r3, [fp, #-32]
	str	r3, [r2, #8]
.L301:
	ldr	r3, .L321+24
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L321+28
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L321+32
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L321+12
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L321+16
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L321+8
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L305
	mov	r3, #1
	b	.L306
.L305:
	mov	r3, #0
.L306:
	str	r3, [fp, #-24]
	ldr	r3, .L321+36
	ldr	r3, [r3, #144]
	cmp	r3, #0
	beq	.L307
	ldr	r0, .L321+40
	bl	Get_UNCOND_OP
	mov	r3, r0
	cmp	r3, #0
	beq	.L307
	mov	r3, #1
	b	.L308
.L307:
	mov	r3, #0
.L308:
	str	r3, [fp, #-20]
	ldr	r3, .L321+36
	ldr	r3, [r3, #144]
	cmp	r3, #0
	beq	.L309
	ldr	r0, .L321+40
	bl	Get_BR_OP
	mov	r3, r0
	cmp	r3, #0
	beq	.L309
	mov	r3, #1
	b	.L310
.L309:
	mov	r3, #0
.L310:
	str	r3, [fp, #-16]
	ldr	r3, .L321+36
	ldr	r3, [r3, #144]
	cmp	r3, #0
	beq	.L311
	ldr	r0, .L321+40
	bl	Get_TRAP_OP
	mov	r3, r0
	cmp	r3, #0
	beq	.L311
	mov	r3, #1
	b	.L312
.L311:
	mov	r3, #0
.L312:
	str	r3, [fp, #-12]
	mov	r3, #0
	str	r3, [fp, #-28]
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L313
	ldr	r3, [fp, #-12]
	cmp	r3, #0
	bne	.L313
	ldr	r3, [fp, #-20]
	cmp	r3, #0
	beq	.L314
.L313:
	mov	r3, #1
	str	r3, [fp, #-28]
	b	.L315
.L314:
	ldr	r3, [fp, #-16]
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L321+44
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L315
	mov	r3, #1
	str	r3, [fp, #-28]
.L315:
	ldr	r3, [fp, #-28]
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L321+48
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L321+4
	ldr	r3, [r3]
	add	r3, r3, #2
	ldr	r2, .L321+4
	str	r3, [r2]
	b	.L320
.L317:
	ldr	r3, .L321+48
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L318
	ldr	r3, .L321+52
	ldr	r3, [r3]
	ldr	r2, .L321+4
	str	r3, [r2]
	b	.L320
.L318:
	ldr	r3, .L321+48
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L320
	ldr	r3, .L321+56
	ldr	r3, [r3]
	ldr	r2, .L321+4
	str	r3, [r2]
.L320:
	nop
	ldr	r3, .L321
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L319
	bl	__stack_chk_fail
.L319:
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L322:
	.align	2
.L321:
	.word	.LC99
	.word	PC
	.word	icache_r
	.word	dep_stall
	.word	mem_stall
	.word	NEW_PS
	.word	v_de_br_stall
	.word	v_agex_br_stall
	.word	v_mem_br_stall
	.word	PS
	.word	PS+148
	.word	cc_match
	.word	mem_pcmux
	.word	target_pc
	.word	trap_pc
	.size	FETCH_stage, .-FETCH_stage
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
