	.file	"778532.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	t17_l1
	.bss
	.type	t17_l1, @object
	.size	t17_l1, 1
t17_l1:
	.zero	1
	.globl	_x_t17_l1
	.type	_x_t17_l1, @object
	.size	_x_t17_l1, 1
_x_t17_l1:
	.zero	1
	.globl	t17_l0
	.type	t17_l0, @object
	.size	t17_l0, 1
t17_l0:
	.zero	1
	.globl	_x_t17_l0
	.type	_x_t17_l0, @object
	.size	_x_t17_l0, 1
_x_t17_l0:
	.zero	1
	.globl	t17_evt1
	.type	t17_evt1, @object
	.size	t17_evt1, 1
t17_evt1:
	.zero	1
	.globl	_x_t17_evt1
	.type	_x_t17_evt1, @object
	.size	_x_t17_evt1, 1
_x_t17_evt1:
	.zero	1
	.globl	t17_x
	.align 4
	.type	t17_x, @object
	.size	t17_x, 4
t17_x:
	.zero	4
	.globl	_x_t17_x
	.align 4
	.type	_x_t17_x, @object
	.size	_x_t17_x, 4
_x_t17_x:
	.zero	4
	.globl	t16_l1
	.type	t16_l1, @object
	.size	t16_l1, 1
t16_l1:
	.zero	1
	.globl	_x_t16_l1
	.type	_x_t16_l1, @object
	.size	_x_t16_l1, 1
_x_t16_l1:
	.zero	1
	.globl	t16_l0
	.type	t16_l0, @object
	.size	t16_l0, 1
t16_l0:
	.zero	1
	.globl	_x_t16_l0
	.type	_x_t16_l0, @object
	.size	_x_t16_l0, 1
_x_t16_l0:
	.zero	1
	.globl	t16_evt1
	.type	t16_evt1, @object
	.size	t16_evt1, 1
t16_evt1:
	.zero	1
	.globl	_x_t16_evt1
	.type	_x_t16_evt1, @object
	.size	_x_t16_evt1, 1
_x_t16_evt1:
	.zero	1
	.globl	t16_evt0
	.type	t16_evt0, @object
	.size	t16_evt0, 1
t16_evt0:
	.zero	1
	.globl	_x_t16_evt0
	.type	_x_t16_evt0, @object
	.size	_x_t16_evt0, 1
_x_t16_evt0:
	.zero	1
	.globl	t16_x
	.align 4
	.type	t16_x, @object
	.size	t16_x, 4
t16_x:
	.zero	4
	.globl	_x_t16_x
	.align 4
	.type	_x_t16_x, @object
	.size	_x_t16_x, 4
_x_t16_x:
	.zero	4
	.globl	t15_l1
	.type	t15_l1, @object
	.size	t15_l1, 1
t15_l1:
	.zero	1
	.globl	_x_t15_l1
	.type	_x_t15_l1, @object
	.size	_x_t15_l1, 1
_x_t15_l1:
	.zero	1
	.globl	t15_l0
	.type	t15_l0, @object
	.size	t15_l0, 1
t15_l0:
	.zero	1
	.globl	_x_t15_l0
	.type	_x_t15_l0, @object
	.size	_x_t15_l0, 1
_x_t15_l0:
	.zero	1
	.globl	t15_evt1
	.type	t15_evt1, @object
	.size	t15_evt1, 1
t15_evt1:
	.zero	1
	.globl	_x_t15_evt1
	.type	_x_t15_evt1, @object
	.size	_x_t15_evt1, 1
_x_t15_evt1:
	.zero	1
	.globl	t15_evt0
	.type	t15_evt0, @object
	.size	t15_evt0, 1
t15_evt0:
	.zero	1
	.globl	_x_t15_evt0
	.type	_x_t15_evt0, @object
	.size	_x_t15_evt0, 1
_x_t15_evt0:
	.zero	1
	.globl	t15_x
	.align 4
	.type	t15_x, @object
	.size	t15_x, 4
t15_x:
	.zero	4
	.globl	_x_t15_x
	.align 4
	.type	_x_t15_x, @object
	.size	_x_t15_x, 4
_x_t15_x:
	.zero	4
	.globl	t14_l1
	.type	t14_l1, @object
	.size	t14_l1, 1
t14_l1:
	.zero	1
	.globl	_x_t14_l1
	.type	_x_t14_l1, @object
	.size	_x_t14_l1, 1
_x_t14_l1:
	.zero	1
	.globl	t14_l0
	.type	t14_l0, @object
	.size	t14_l0, 1
t14_l0:
	.zero	1
	.globl	_x_t14_l0
	.type	_x_t14_l0, @object
	.size	_x_t14_l0, 1
_x_t14_l0:
	.zero	1
	.globl	t14_evt1
	.type	t14_evt1, @object
	.size	t14_evt1, 1
t14_evt1:
	.zero	1
	.globl	_x_t14_evt1
	.type	_x_t14_evt1, @object
	.size	_x_t14_evt1, 1
_x_t14_evt1:
	.zero	1
	.globl	t14_evt0
	.type	t14_evt0, @object
	.size	t14_evt0, 1
t14_evt0:
	.zero	1
	.globl	_x_t14_evt0
	.type	_x_t14_evt0, @object
	.size	_x_t14_evt0, 1
_x_t14_evt0:
	.zero	1
	.globl	t14_x
	.align 4
	.type	t14_x, @object
	.size	t14_x, 4
t14_x:
	.zero	4
	.globl	_x_t14_x
	.align 4
	.type	_x_t14_x, @object
	.size	_x_t14_x, 4
_x_t14_x:
	.zero	4
	.globl	t13_l1
	.type	t13_l1, @object
	.size	t13_l1, 1
t13_l1:
	.zero	1
	.globl	_x_t13_l1
	.type	_x_t13_l1, @object
	.size	_x_t13_l1, 1
_x_t13_l1:
	.zero	1
	.globl	t13_l0
	.type	t13_l0, @object
	.size	t13_l0, 1
t13_l0:
	.zero	1
	.globl	_x_t13_l0
	.type	_x_t13_l0, @object
	.size	_x_t13_l0, 1
_x_t13_l0:
	.zero	1
	.globl	t13_evt1
	.type	t13_evt1, @object
	.size	t13_evt1, 1
t13_evt1:
	.zero	1
	.globl	_x_t13_evt1
	.type	_x_t13_evt1, @object
	.size	_x_t13_evt1, 1
_x_t13_evt1:
	.zero	1
	.globl	t13_evt0
	.type	t13_evt0, @object
	.size	t13_evt0, 1
t13_evt0:
	.zero	1
	.globl	_x_t13_evt0
	.type	_x_t13_evt0, @object
	.size	_x_t13_evt0, 1
_x_t13_evt0:
	.zero	1
	.globl	t13_x
	.align 4
	.type	t13_x, @object
	.size	t13_x, 4
t13_x:
	.zero	4
	.globl	_x_t13_x
	.align 4
	.type	_x_t13_x, @object
	.size	_x_t13_x, 4
_x_t13_x:
	.zero	4
	.globl	t12_l1
	.type	t12_l1, @object
	.size	t12_l1, 1
t12_l1:
	.zero	1
	.globl	_x_t12_l1
	.type	_x_t12_l1, @object
	.size	_x_t12_l1, 1
_x_t12_l1:
	.zero	1
	.globl	t12_l0
	.type	t12_l0, @object
	.size	t12_l0, 1
t12_l0:
	.zero	1
	.globl	_x_t12_l0
	.type	_x_t12_l0, @object
	.size	_x_t12_l0, 1
_x_t12_l0:
	.zero	1
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	t12_evt0
	.type	t12_evt0, @object
	.size	t12_evt0, 1
t12_evt0:
	.zero	1
	.globl	_x_t12_evt0
	.type	_x_t12_evt0, @object
	.size	_x_t12_evt0, 1
_x_t12_evt0:
	.zero	1
	.globl	t12_x
	.align 4
	.type	t12_x, @object
	.size	t12_x, 4
t12_x:
	.zero	4
	.globl	_x_t12_x
	.align 4
	.type	_x_t12_x, @object
	.size	_x_t12_x, 4
_x_t12_x:
	.zero	4
	.globl	t11_l1
	.type	t11_l1, @object
	.size	t11_l1, 1
t11_l1:
	.zero	1
	.globl	_x_t11_l1
	.type	_x_t11_l1, @object
	.size	_x_t11_l1, 1
_x_t11_l1:
	.zero	1
	.globl	t11_l0
	.type	t11_l0, @object
	.size	t11_l0, 1
t11_l0:
	.zero	1
	.globl	_x_t11_l0
	.type	_x_t11_l0, @object
	.size	_x_t11_l0, 1
_x_t11_l0:
	.zero	1
	.globl	t11_evt1
	.type	t11_evt1, @object
	.size	t11_evt1, 1
t11_evt1:
	.zero	1
	.globl	_x_t11_evt1
	.type	_x_t11_evt1, @object
	.size	_x_t11_evt1, 1
_x_t11_evt1:
	.zero	1
	.globl	t11_evt0
	.type	t11_evt0, @object
	.size	t11_evt0, 1
t11_evt0:
	.zero	1
	.globl	_x_t11_evt0
	.type	_x_t11_evt0, @object
	.size	_x_t11_evt0, 1
_x_t11_evt0:
	.zero	1
	.globl	t11_x
	.align 4
	.type	t11_x, @object
	.size	t11_x, 4
t11_x:
	.zero	4
	.globl	_x_t11_x
	.align 4
	.type	_x_t11_x, @object
	.size	_x_t11_x, 4
_x_t11_x:
	.zero	4
	.globl	t10_l1
	.type	t10_l1, @object
	.size	t10_l1, 1
t10_l1:
	.zero	1
	.globl	_x_t10_l1
	.type	_x_t10_l1, @object
	.size	_x_t10_l1, 1
_x_t10_l1:
	.zero	1
	.globl	t10_l0
	.type	t10_l0, @object
	.size	t10_l0, 1
t10_l0:
	.zero	1
	.globl	_x_t10_l0
	.type	_x_t10_l0, @object
	.size	_x_t10_l0, 1
_x_t10_l0:
	.zero	1
	.globl	t10_evt1
	.type	t10_evt1, @object
	.size	t10_evt1, 1
t10_evt1:
	.zero	1
	.globl	_x_t10_evt1
	.type	_x_t10_evt1, @object
	.size	_x_t10_evt1, 1
_x_t10_evt1:
	.zero	1
	.globl	t10_evt0
	.type	t10_evt0, @object
	.size	t10_evt0, 1
t10_evt0:
	.zero	1
	.globl	_x_t10_evt0
	.type	_x_t10_evt0, @object
	.size	_x_t10_evt0, 1
_x_t10_evt0:
	.zero	1
	.globl	t10_x
	.align 4
	.type	t10_x, @object
	.size	t10_x, 4
t10_x:
	.zero	4
	.globl	_x_t10_x
	.align 4
	.type	_x_t10_x, @object
	.size	_x_t10_x, 4
_x_t10_x:
	.zero	4
	.globl	t9_l1
	.type	t9_l1, @object
	.size	t9_l1, 1
t9_l1:
	.zero	1
	.globl	_x_t9_l1
	.type	_x_t9_l1, @object
	.size	_x_t9_l1, 1
_x_t9_l1:
	.zero	1
	.globl	t9_l0
	.type	t9_l0, @object
	.size	t9_l0, 1
t9_l0:
	.zero	1
	.globl	_x_t9_l0
	.type	_x_t9_l0, @object
	.size	_x_t9_l0, 1
_x_t9_l0:
	.zero	1
	.globl	t9_evt1
	.type	t9_evt1, @object
	.size	t9_evt1, 1
t9_evt1:
	.zero	1
	.globl	_x_t9_evt1
	.type	_x_t9_evt1, @object
	.size	_x_t9_evt1, 1
_x_t9_evt1:
	.zero	1
	.globl	t9_evt0
	.type	t9_evt0, @object
	.size	t9_evt0, 1
t9_evt0:
	.zero	1
	.globl	_x_t9_evt0
	.type	_x_t9_evt0, @object
	.size	_x_t9_evt0, 1
_x_t9_evt0:
	.zero	1
	.globl	t3_x
	.align 4
	.type	t3_x, @object
	.size	t3_x, 4
t3_x:
	.zero	4
	.globl	_x_t3_x
	.align 4
	.type	_x_t3_x, @object
	.size	_x_t3_x, 4
_x_t3_x:
	.zero	4
	.globl	t2_evt1
	.type	t2_evt1, @object
	.size	t2_evt1, 1
t2_evt1:
	.zero	1
	.globl	_x_t2_evt1
	.type	_x_t2_evt1, @object
	.size	_x_t2_evt1, 1
_x_t2_evt1:
	.zero	1
	.globl	t2_l1
	.type	t2_l1, @object
	.size	t2_l1, 1
t2_l1:
	.zero	1
	.globl	_x_t2_l1
	.type	_x_t2_l1, @object
	.size	_x_t2_l1, 1
_x_t2_l1:
	.zero	1
	.globl	t3_evt0
	.type	t3_evt0, @object
	.size	t3_evt0, 1
t3_evt0:
	.zero	1
	.globl	_x_t3_evt0
	.type	_x_t3_evt0, @object
	.size	_x_t3_evt0, 1
_x_t3_evt0:
	.zero	1
	.globl	t2_l0
	.type	t2_l0, @object
	.size	t2_l0, 1
t2_l0:
	.zero	1
	.globl	_x_t2_l0
	.type	_x_t2_l0, @object
	.size	_x_t2_l0, 1
_x_t2_l0:
	.zero	1
	.globl	t1_l1
	.type	t1_l1, @object
	.size	t1_l1, 1
t1_l1:
	.zero	1
	.globl	_x_t1_l1
	.type	_x_t1_l1, @object
	.size	_x_t1_l1, 1
_x_t1_l1:
	.zero	1
	.globl	t2_evt0
	.type	t2_evt0, @object
	.size	t2_evt0, 1
t2_evt0:
	.zero	1
	.globl	_x_t2_evt0
	.type	_x_t2_evt0, @object
	.size	_x_t2_evt0, 1
_x_t2_evt0:
	.zero	1
	.globl	t17_evt0
	.type	t17_evt0, @object
	.size	t17_evt0, 1
t17_evt0:
	.zero	1
	.globl	_x_t17_evt0
	.type	_x_t17_evt0, @object
	.size	_x_t17_evt0, 1
_x_t17_evt0:
	.zero	1
	.globl	controller_evt2
	.type	controller_evt2, @object
	.size	controller_evt2, 1
controller_evt2:
	.zero	1
	.globl	_x_controller_evt2
	.type	_x_controller_evt2, @object
	.size	_x_controller_evt2, 1
_x_controller_evt2:
	.zero	1
	.globl	t1_l0
	.type	t1_l0, @object
	.size	t1_l0, 1
t1_l0:
	.zero	1
	.globl	_x_t1_l0
	.type	_x_t1_l0, @object
	.size	_x_t1_l0, 1
_x_t1_l0:
	.zero	1
	.globl	controller_evt1
	.type	controller_evt1, @object
	.size	controller_evt1, 1
controller_evt1:
	.zero	1
	.globl	_x_controller_evt1
	.type	_x_controller_evt1, @object
	.size	_x_controller_evt1, 1
_x_controller_evt1:
	.zero	1
	.globl	t1_evt1
	.type	t1_evt1, @object
	.size	t1_evt1, 1
t1_evt1:
	.zero	1
	.globl	_x_t1_evt1
	.type	_x_t1_evt1, @object
	.size	_x_t1_evt1, 1
_x_t1_evt1:
	.zero	1
	.globl	t1_evt0
	.type	t1_evt0, @object
	.size	t1_evt0, 1
t1_evt0:
	.zero	1
	.globl	_x_t1_evt0
	.type	_x_t1_evt0, @object
	.size	_x_t1_evt0, 1
_x_t1_evt0:
	.zero	1
	.globl	t1_x
	.align 4
	.type	t1_x, @object
	.size	t1_x, 4
t1_x:
	.zero	4
	.globl	_x_t1_x
	.align 4
	.type	_x_t1_x, @object
	.size	_x_t1_x, 4
_x_t1_x:
	.zero	4
	.globl	t0_evt1
	.type	t0_evt1, @object
	.size	t0_evt1, 1
t0_evt1:
	.zero	1
	.globl	_x_t0_evt1
	.type	_x_t0_evt1, @object
	.size	_x_t0_evt1, 1
_x_t0_evt1:
	.zero	1
	.globl	t0_l0
	.type	t0_l0, @object
	.size	t0_l0, 1
t0_l0:
	.zero	1
	.globl	_x_t0_l0
	.type	_x_t0_l0, @object
	.size	_x_t0_l0, 1
_x_t0_l0:
	.zero	1
	.globl	t0_evt0
	.type	t0_evt0, @object
	.size	t0_evt0, 1
t0_evt0:
	.zero	1
	.globl	_x_t0_evt0
	.type	_x_t0_evt0, @object
	.size	_x_t0_evt0, 1
_x_t0_evt0:
	.zero	1
	.globl	controller_cnt
	.align 4
	.type	controller_cnt, @object
	.size	controller_cnt, 4
controller_cnt:
	.zero	4
	.globl	_x_controller_cnt
	.align 4
	.type	_x_controller_cnt, @object
	.size	_x_controller_cnt, 4
_x_controller_cnt:
	.zero	4
	.globl	t12_evt1
	.type	t12_evt1, @object
	.size	t12_evt1, 1
t12_evt1:
	.zero	1
	.globl	_x_t12_evt1
	.type	_x_t12_evt1, @object
	.size	_x_t12_evt1, 1
_x_t12_evt1:
	.zero	1
	.globl	gate_l0
	.type	gate_l0, @object
	.size	gate_l0, 1
gate_l0:
	.zero	1
	.globl	_x_gate_l0
	.type	_x_gate_l0, @object
	.size	_x_gate_l0, 1
_x_gate_l0:
	.zero	1
	.globl	t2_x
	.align 4
	.type	t2_x, @object
	.size	t2_x, 4
t2_x:
	.zero	4
	.globl	_x_t2_x
	.align 4
	.type	_x_t2_x, @object
	.size	_x_t2_x, 4
_x_t2_x:
	.zero	4
	.globl	controller_l0
	.type	controller_l0, @object
	.size	controller_l0, 1
controller_l0:
	.zero	1
	.globl	_x_controller_l0
	.type	_x_controller_l0, @object
	.size	_x_controller_l0, 1
_x_controller_l0:
	.zero	1
	.globl	controller_l1
	.type	controller_l1, @object
	.size	controller_l1, 1
controller_l1:
	.zero	1
	.globl	_x_controller_l1
	.type	_x_controller_l1, @object
	.size	_x_controller_l1, 1
_x_controller_l1:
	.zero	1
	.globl	t0_l1
	.type	t0_l1, @object
	.size	t0_l1, 1
t0_l1:
	.zero	1
	.globl	_x_t0_l1
	.type	_x_t0_l1, @object
	.size	_x_t0_l1, 1
_x_t0_l1:
	.zero	1
	.globl	controller_evt0
	.type	controller_evt0, @object
	.size	controller_evt0, 1
controller_evt0:
	.zero	1
	.globl	_x_controller_evt0
	.type	_x_controller_evt0, @object
	.size	_x_controller_evt0, 1
_x_controller_evt0:
	.zero	1
	.globl	t0_x
	.align 4
	.type	t0_x, @object
	.size	t0_x, 4
t0_x:
	.zero	4
	.globl	_x_t0_x
	.align 4
	.type	_x_t0_x, @object
	.size	_x_t0_x, 4
_x_t0_x:
	.zero	4
	.globl	controller_z
	.align 4
	.type	controller_z, @object
	.size	controller_z, 4
controller_z:
	.zero	4
	.globl	_x_controller_z
	.align 4
	.type	_x_controller_z, @object
	.size	_x_controller_z, 4
_x_controller_z:
	.zero	4
	.globl	t3_evt1
	.type	t3_evt1, @object
	.size	t3_evt1, 1
t3_evt1:
	.zero	1
	.globl	_x_t3_evt1
	.type	_x_t3_evt1, @object
	.size	_x_t3_evt1, 1
_x_t3_evt1:
	.zero	1
	.globl	t4_x
	.align 4
	.type	t4_x, @object
	.size	t4_x, 4
t4_x:
	.zero	4
	.globl	_x_t4_x
	.align 4
	.type	_x_t4_x, @object
	.size	_x_t4_x, 4
_x_t4_x:
	.zero	4
	.globl	t3_l0
	.type	t3_l0, @object
	.size	t3_l0, 1
t3_l0:
	.zero	1
	.globl	_x_t3_l0
	.type	_x_t3_l0, @object
	.size	_x_t3_l0, 1
_x_t3_l0:
	.zero	1
	.globl	t3_l1
	.type	t3_l1, @object
	.size	t3_l1, 1
t3_l1:
	.zero	1
	.globl	_x_t3_l1
	.type	_x_t3_l1, @object
	.size	_x_t3_l1, 1
_x_t3_l1:
	.zero	1
	.globl	t4_evt0
	.type	t4_evt0, @object
	.size	t4_evt0, 1
t4_evt0:
	.zero	1
	.globl	_x_t4_evt0
	.type	_x_t4_evt0, @object
	.size	_x_t4_evt0, 1
_x_t4_evt0:
	.zero	1
	.globl	t4_evt1
	.type	t4_evt1, @object
	.size	t4_evt1, 1
t4_evt1:
	.zero	1
	.globl	_x_t4_evt1
	.type	_x_t4_evt1, @object
	.size	_x_t4_evt1, 1
_x_t4_evt1:
	.zero	1
	.globl	t5_x
	.align 4
	.type	t5_x, @object
	.size	t5_x, 4
t5_x:
	.zero	4
	.globl	_x_t5_x
	.align 4
	.type	_x_t5_x, @object
	.size	_x_t5_x, 4
_x_t5_x:
	.zero	4
	.globl	t4_l0
	.type	t4_l0, @object
	.size	t4_l0, 1
t4_l0:
	.zero	1
	.globl	_x_t4_l0
	.type	_x_t4_l0, @object
	.size	_x_t4_l0, 1
_x_t4_l0:
	.zero	1
	.globl	t4_l1
	.type	t4_l1, @object
	.size	t4_l1, 1
t4_l1:
	.zero	1
	.globl	_x_t4_l1
	.type	_x_t4_l1, @object
	.size	_x_t4_l1, 1
_x_t4_l1:
	.zero	1
	.globl	gate_y
	.align 4
	.type	gate_y, @object
	.size	gate_y, 4
gate_y:
	.zero	4
	.globl	_x_gate_y
	.align 4
	.type	_x_gate_y, @object
	.size	_x_gate_y, 4
_x_gate_y:
	.zero	4
	.globl	t5_evt0
	.type	t5_evt0, @object
	.size	t5_evt0, 1
t5_evt0:
	.zero	1
	.globl	_x_t5_evt0
	.type	_x_t5_evt0, @object
	.size	_x_t5_evt0, 1
_x_t5_evt0:
	.zero	1
	.globl	t5_evt1
	.type	t5_evt1, @object
	.size	t5_evt1, 1
t5_evt1:
	.zero	1
	.globl	_x_t5_evt1
	.type	_x_t5_evt1, @object
	.size	_x_t5_evt1, 1
_x_t5_evt1:
	.zero	1
	.globl	t6_x
	.align 4
	.type	t6_x, @object
	.size	t6_x, 4
t6_x:
	.zero	4
	.globl	_x_t6_x
	.align 4
	.type	_x_t6_x, @object
	.size	_x_t6_x, 4
_x_t6_x:
	.zero	4
	.globl	gate_evt0
	.type	gate_evt0, @object
	.size	gate_evt0, 1
gate_evt0:
	.zero	1
	.globl	_x_gate_evt0
	.type	_x_gate_evt0, @object
	.size	_x_gate_evt0, 1
_x_gate_evt0:
	.zero	1
	.globl	t5_l0
	.type	t5_l0, @object
	.size	t5_l0, 1
t5_l0:
	.zero	1
	.globl	_x_t5_l0
	.type	_x_t5_l0, @object
	.size	_x_t5_l0, 1
_x_t5_l0:
	.zero	1
	.globl	gate_evt1
	.type	gate_evt1, @object
	.size	gate_evt1, 1
gate_evt1:
	.zero	1
	.globl	_x_gate_evt1
	.type	_x_gate_evt1, @object
	.size	_x_gate_evt1, 1
_x_gate_evt1:
	.zero	1
	.globl	t5_l1
	.type	t5_l1, @object
	.size	t5_l1, 1
t5_l1:
	.zero	1
	.globl	_x_t5_l1
	.type	_x_t5_l1, @object
	.size	_x_t5_l1, 1
_x_t5_l1:
	.zero	1
	.globl	t6_evt0
	.type	t6_evt0, @object
	.size	t6_evt0, 1
t6_evt0:
	.zero	1
	.globl	_x_t6_evt0
	.type	_x_t6_evt0, @object
	.size	_x_t6_evt0, 1
_x_t6_evt0:
	.zero	1
	.globl	t6_evt1
	.type	t6_evt1, @object
	.size	t6_evt1, 1
t6_evt1:
	.zero	1
	.globl	_x_t6_evt1
	.type	_x_t6_evt1, @object
	.size	_x_t6_evt1, 1
_x_t6_evt1:
	.zero	1
	.globl	gate_l1
	.type	gate_l1, @object
	.size	gate_l1, 1
gate_l1:
	.zero	1
	.globl	_x_gate_l1
	.type	_x_gate_l1, @object
	.size	_x_gate_l1, 1
_x_gate_l1:
	.zero	1
	.globl	t7_x
	.align 4
	.type	t7_x, @object
	.size	t7_x, 4
t7_x:
	.zero	4
	.globl	_x_t7_x
	.align 4
	.type	_x_t7_x, @object
	.size	_x_t7_x, 4
_x_t7_x:
	.zero	4
	.globl	t6_l0
	.type	t6_l0, @object
	.size	t6_l0, 1
t6_l0:
	.zero	1
	.globl	_x_t6_l0
	.type	_x_t6_l0, @object
	.size	_x_t6_l0, 1
_x_t6_l0:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	t6_l1
	.type	t6_l1, @object
	.size	t6_l1, 1
t6_l1:
	.zero	1
	.globl	_x_t6_l1
	.type	_x_t6_l1, @object
	.size	_x_t6_l1, 1
_x_t6_l1:
	.zero	1
	.globl	t7_evt0
	.type	t7_evt0, @object
	.size	t7_evt0, 1
t7_evt0:
	.zero	1
	.globl	_x_t7_evt0
	.type	_x_t7_evt0, @object
	.size	_x_t7_evt0, 1
_x_t7_evt0:
	.zero	1
	.globl	t7_evt1
	.type	t7_evt1, @object
	.size	t7_evt1, 1
t7_evt1:
	.zero	1
	.globl	_x_t7_evt1
	.type	_x_t7_evt1, @object
	.size	_x_t7_evt1, 1
_x_t7_evt1:
	.zero	1
	.globl	t8_x
	.align 4
	.type	t8_x, @object
	.size	t8_x, 4
t8_x:
	.zero	4
	.globl	_x_t8_x
	.align 4
	.type	_x_t8_x, @object
	.size	_x_t8_x, 4
_x_t8_x:
	.zero	4
	.globl	t7_l0
	.type	t7_l0, @object
	.size	t7_l0, 1
t7_l0:
	.zero	1
	.globl	_x_t7_l0
	.type	_x_t7_l0, @object
	.size	_x_t7_l0, 1
_x_t7_l0:
	.zero	1
	.globl	t7_l1
	.type	t7_l1, @object
	.size	t7_l1, 1
t7_l1:
	.zero	1
	.globl	_x_t7_l1
	.type	_x_t7_l1, @object
	.size	_x_t7_l1, 1
_x_t7_l1:
	.zero	1
	.globl	t8_evt0
	.type	t8_evt0, @object
	.size	t8_evt0, 1
t8_evt0:
	.zero	1
	.globl	_x_t8_evt0
	.type	_x_t8_evt0, @object
	.size	_x_t8_evt0, 1
_x_t8_evt0:
	.zero	1
	.globl	t8_evt1
	.type	t8_evt1, @object
	.size	t8_evt1, 1
t8_evt1:
	.zero	1
	.globl	_x_t8_evt1
	.type	_x_t8_evt1, @object
	.size	_x_t8_evt1, 1
_x_t8_evt1:
	.zero	1
	.globl	t9_x
	.align 4
	.type	t9_x, @object
	.size	t9_x, 4
t9_x:
	.zero	4
	.globl	_x_t9_x
	.align 4
	.type	_x_t9_x, @object
	.size	_x_t9_x, 4
_x_t9_x:
	.zero	4
	.globl	t8_l0
	.type	t8_l0, @object
	.size	t8_l0, 1
t8_l0:
	.zero	1
	.globl	_x_t8_l0
	.type	_x_t8_l0, @object
	.size	_x_t8_l0, 1
_x_t8_l0:
	.zero	1
	.globl	t8_l1
	.type	t8_l1, @object
	.size	t8_l1, 1
t8_l1:
	.zero	1
	.globl	_x_t8_l1
	.type	_x_t8_l1, @object
	.size	_x_t8_l1, 1
_x_t8_l1:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t17_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t17_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t17_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t17_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t16_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t16_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t16_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t16_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t16_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t15_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t15_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t15_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t15_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t15_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t14_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t14_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t14_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t14_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t14_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t13_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t11_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t17_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR controller_cnt[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t0_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t4_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t9_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_l1[rip], al
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	je	.L4
.L7:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L11
.L10:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	je	.L12
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L11
.L12:
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	je	.L11
.L13:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L4
.L11:
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	je	.L15
.L14:
	movss	xmm1, DWORD PTR t17_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L15:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L18
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L19
.L18:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L19
.L20:
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L19
.L21:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L4
.L19:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L23
.L22:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L23
.L24:
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L23
.L25:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L4
.L23:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L27
.L26:
	movss	xmm1, DWORD PTR t16_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L27:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L31
.L30:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L31
.L32:
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L33
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L31
.L33:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L4
.L31:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L35
.L34:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L35
.L36:
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L35
.L37:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L4
.L35:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L39
.L38:
	movss	xmm1, DWORD PTR t15_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L39:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L42
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L43
.L42:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L44
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L43
.L44:
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L43
.L45:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L4
.L43:
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L46
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L47
.L46:
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L47
.L48:
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L47
.L49:
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L4
.L47:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L50
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L51
.L50:
	movss	xmm1, DWORD PTR t14_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L51:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L55
.L54:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L55
.L56:
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L55
.L57:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L4
.L55:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L59
.L58:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L59
.L60:
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L59
.L61:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L4
.L59:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L63
.L62:
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L63:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L66
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L67
.L66:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L68
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L67
.L68:
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L69
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L67
.L69:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L4
.L67:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L71
.L70:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L71
.L72:
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L73
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L71
.L73:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L4
.L71:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L75
.L74:
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L75:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L78
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L79
.L78:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L80
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L79
.L80:
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L79
.L81:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L4
.L79:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L83
.L82:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L83
.L84:
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L85
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L83
.L85:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L4
.L83:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L87
.L86:
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L87:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L90
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L91
.L90:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L91
.L92:
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L91
.L93:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L4
.L91:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L95
.L94:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L95
.L96:
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L95
.L97:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L4
.L95:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L99
.L98:
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L99:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L103
.L102:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L103
.L104:
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L103
.L105:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L4
.L103:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L107
.L106:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L107
.L108:
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L107
.L109:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L4
.L107:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L111
.L110:
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L111:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L115
.L114:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L115
.L116:
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L115
.L117:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L4
.L115:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L119
.L118:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L119
.L120:
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L121
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L119
.L121:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L4
.L119:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L123
.L122:
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L123:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L127
.L126:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L127
.L128:
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L129
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L127
.L129:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L4
.L127:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L131
.L130:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L132
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L131
.L132:
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L131
.L133:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L4
.L131:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L134
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L135
.L134:
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L135:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L139
.L138:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L139
.L140:
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L139
.L141:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L4
.L139:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L143
.L142:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L143
.L144:
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L143
.L145:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L4
.L143:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L147
.L146:
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L147:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L150
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L151
.L150:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L151
.L152:
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L151
.L153:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L4
.L151:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L155
.L154:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L155
.L156:
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L155
.L157:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L4
.L155:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L159
.L158:
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L159:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L163
.L162:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L163
.L164:
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L163
.L165:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L4
.L163:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L167
.L166:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L167
.L168:
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L167
.L169:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L4
.L167:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L170
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L171
.L170:
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L171:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L175
.L174:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L175
.L176:
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L177
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L175
.L177:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L4
.L175:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L179
.L178:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L179
.L180:
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L179
.L181:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L4
.L179:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L183
.L182:
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L183:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L187
.L186:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L187
.L188:
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L187
.L189:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L4
.L187:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L191
.L190:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L191
.L192:
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L191
.L193:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L4
.L191:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L195
.L194:
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L195:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L199
.L198:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L199
.L200:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L199
.L201:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L4
.L199:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L202
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L203
.L202:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L203
.L204:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L203
.L205:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L4
.L203:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L207
.L206:
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L207:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L211
.L210:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L211
.L212:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L213
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L211
.L213:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L4
.L211:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L215
.L214:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L215
.L216:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L215
.L217:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L4
.L215:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L218
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L219
.L218:
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L219:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L223
.L222:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L223
.L224:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L223
.L225:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L223:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L227
.L226:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L228
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L227
.L228:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L229
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L227
.L229:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L230
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L227
.L230:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L4
.L227:
	mov	eax, DWORD PTR controller_cnt[rip]
	test	eax, eax
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 2
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 3
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 4
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 5
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 6
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 7
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 8
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 9
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 10
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 11
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 12
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 13
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 14
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 15
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 16
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 17
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 18
	je	.L231
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 19
	jne	.L4
.L231:
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L232
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L233:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
.L232:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L236
.L235:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L236
.L237:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L238
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L236
.L238:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L236:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L239
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L240
.L239:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L240
.L241:
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L242
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L240
.L242:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L4
.L240:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L243
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L243
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L243:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L244
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L244
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
.L244:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L247
.L4:
	mov	eax, 0
.L247:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L248
.L932:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t17_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t17_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t17_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t17_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t16_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t16_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t16_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t16_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t16_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t15_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t15_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t15_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t15_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t15_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t14_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t14_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t14_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t14_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t14_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t13_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t11_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t17_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_controller_cnt[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t0_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t4_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t9_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_l1[rip], al
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	jne	.L249
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	je	.L250
.L249:
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	je	.L251
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	je	.L250
.L251:
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	je	.L252
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	je	.L250
.L252:
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	je	.L253
.L250:
	movzx	eax, BYTE PTR _x_t17_evt0[rip]
	test	al, al
	jne	.L254
	movzx	eax, BYTE PTR _x_t17_evt1[rip]
	test	al, al
	je	.L255
.L254:
	movzx	eax, BYTE PTR _x_t17_evt0[rip]
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR _x_t17_evt1[rip]
	test	al, al
	je	.L255
.L256:
	movzx	eax, BYTE PTR _x_t17_evt1[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR _x_t17_evt0[rip]
	test	al, al
	je	.L255
.L257:
	movzx	eax, BYTE PTR _x_t17_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t17_evt1[rip]
	test	al, al
	je	.L253
.L255:
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	jne	.L258
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	je	.L259
.L258:
	movss	xmm1, DWORD PTR _x_t17_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L259:
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L261
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L261
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t17_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t17_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L261
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L262
.L261:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L262
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L253
.L262:
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	je	.L265
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	jne	.L265
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	je	.L265
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	jne	.L265
	movss	xmm0, DWORD PTR _x_t17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L265
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L266
.L265:
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	jne	.L266
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L266
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L266
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	jne	.L253
.L266:
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	je	.L268
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	jne	.L268
	movss	xmm1, DWORD PTR t17_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L268
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	je	.L268
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L268
	movss	xmm0, DWORD PTR t17_x[rip]
	movss	xmm1, DWORD PTR _x_t17_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L268
	ucomiss	xmm0, xmm1
	je	.L269
.L268:
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	je	.L269
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	jne	.L269
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L269
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L269
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	jne	.L253
.L269:
	movss	xmm0, DWORD PTR t17_x[rip]
	movss	xmm1, DWORD PTR _x_t17_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L271
	ucomiss	xmm0, xmm1
	jne	.L271
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	je	.L271
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	je	.L271
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	je	.L271
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	jne	.L273
.L271:
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	je	.L273
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	jne	.L273
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L273
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L273
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	jne	.L253
.L273:
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	test	al, al
	jne	.L274
	movss	xmm1, DWORD PTR t17_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L274
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L274
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L274
	movss	xmm0, DWORD PTR t17_x[rip]
	movss	xmm1, DWORD PTR _x_t17_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L274
	ucomiss	xmm0, xmm1
	je	.L276
.L274:
	movzx	eax, BYTE PTR t17_l0[rip]
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR t17_l1[rip]
	test	al, al
	je	.L276
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L276
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L276
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	jne	.L253
.L276:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L279
.L278:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L280
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L279
.L280:
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L281
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L279
.L281:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L253
.L279:
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	test	al, al
	jne	.L282
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	test	al, al
	je	.L283
.L282:
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	test	al, al
	je	.L283
.L284:
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	test	al, al
	je	.L285
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	test	al, al
	je	.L283
.L285:
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	test	al, al
	je	.L253
.L283:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	jne	.L286
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L287
.L286:
	movss	xmm1, DWORD PTR _x_t16_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L287:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L289
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L289
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t16_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t16_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L289
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L290
.L289:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L290
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L253
.L290:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	jne	.L293
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L293
	movss	xmm0, DWORD PTR _x_t16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L293
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L294
.L293:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L294
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	jne	.L294
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L294
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L294
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L253
.L294:
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L296
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	jne	.L296
	movss	xmm1, DWORD PTR t16_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L296
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L296
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L296
	movss	xmm0, DWORD PTR t16_x[rip]
	movss	xmm1, DWORD PTR _x_t16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L296
	ucomiss	xmm0, xmm1
	je	.L297
.L296:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L297
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	jne	.L297
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L297
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L297
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L253
.L297:
	movss	xmm0, DWORD PTR t16_x[rip]
	movss	xmm1, DWORD PTR _x_t16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L299
	ucomiss	xmm0, xmm1
	jne	.L299
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L301
.L299:
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L301
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L301
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L301
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L253
.L301:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	jne	.L302
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	jne	.L302
	movss	xmm1, DWORD PTR t16_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L302
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L302
	movss	xmm0, DWORD PTR t16_x[rip]
	movss	xmm1, DWORD PTR _x_t16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L302
	ucomiss	xmm0, xmm1
	je	.L304
.L302:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L304
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L304
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L304
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L304
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L253
.L304:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L307
.L306:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L308
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L307
.L308:
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L307
.L309:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L253
.L307:
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	test	al, al
	je	.L311
.L310:
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	test	al, al
	je	.L311
.L312:
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	test	al, al
	je	.L311
.L313:
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	test	al, al
	je	.L253
.L311:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	jne	.L314
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L315
.L314:
	movss	xmm1, DWORD PTR _x_t15_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L315:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L317
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L317
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t15_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t15_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L317
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L318
.L317:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L318
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L253
.L318:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	jne	.L321
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L321
	movss	xmm0, DWORD PTR _x_t15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L321
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L322
.L321:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L322
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	jne	.L322
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L322
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L322
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L253
.L322:
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L324
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	jne	.L324
	movss	xmm1, DWORD PTR t15_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L324
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L324
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L324
	movss	xmm0, DWORD PTR t15_x[rip]
	movss	xmm1, DWORD PTR _x_t15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L324
	ucomiss	xmm0, xmm1
	je	.L325
.L324:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	jne	.L325
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L325
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L325
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L253
.L325:
	movss	xmm0, DWORD PTR t15_x[rip]
	movss	xmm1, DWORD PTR _x_t15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L327
	ucomiss	xmm0, xmm1
	jne	.L327
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L327
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L327
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L327
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L329
.L327:
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L329
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L329
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L329
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L253
.L329:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	jne	.L330
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	jne	.L330
	movss	xmm1, DWORD PTR t15_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L330
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L330
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L330
	movss	xmm0, DWORD PTR t15_x[rip]
	movss	xmm1, DWORD PTR _x_t15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L330
	ucomiss	xmm0, xmm1
	je	.L332
.L330:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L332
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L332
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L332
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L253
.L332:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	jne	.L334
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L335
.L334:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L336
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L335
.L336:
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L337
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L335
.L337:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L253
.L335:
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	test	al, al
	jne	.L338
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	test	al, al
	je	.L339
.L338:
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	test	al, al
	je	.L340
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	test	al, al
	je	.L339
.L340:
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	test	al, al
	je	.L341
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	test	al, al
	je	.L339
.L341:
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	test	al, al
	je	.L253
.L339:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	jne	.L342
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L343
.L342:
	movss	xmm1, DWORD PTR _x_t14_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L343:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L345
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t14_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t14_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L345
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L346
.L345:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L346
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L253
.L346:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	jne	.L349
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L349
	movss	xmm0, DWORD PTR _x_t14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L349
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L350
.L349:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L350
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	jne	.L350
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L350
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L350
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L253
.L350:
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L352
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	jne	.L352
	movss	xmm1, DWORD PTR t14_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L352
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L352
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L352
	movss	xmm0, DWORD PTR t14_x[rip]
	movss	xmm1, DWORD PTR _x_t14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L352
	ucomiss	xmm0, xmm1
	je	.L353
.L352:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L353
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	jne	.L353
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L353
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L353
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L253
.L353:
	movss	xmm0, DWORD PTR t14_x[rip]
	movss	xmm1, DWORD PTR _x_t14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L355
	ucomiss	xmm0, xmm1
	jne	.L355
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L355
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L355
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L355
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L357
.L355:
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L357
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L357
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L357
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L253
.L357:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	jne	.L358
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	jne	.L358
	movss	xmm1, DWORD PTR t14_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L358
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L358
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L358
	movss	xmm0, DWORD PTR t14_x[rip]
	movss	xmm1, DWORD PTR _x_t14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L358
	ucomiss	xmm0, xmm1
	je	.L360
.L358:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L360
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L360
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L360
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L360
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L253
.L360:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L362
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L363
.L362:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L364
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L363
.L364:
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L363
.L365:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L253
.L363:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	jne	.L366
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L367
.L366:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L367
.L368:
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L369
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L367
.L369:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L253
.L367:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L370
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L371
.L370:
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L371:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L373
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t13_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t13_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L373
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L374
.L373:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L374
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L253
.L374:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L377
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	jne	.L377
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L377
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L377
	movss	xmm0, DWORD PTR _x_t13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L377
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L378
.L377:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L378
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L378
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L378
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L378
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L253
.L378:
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L380
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L380
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L380
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L380
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L380
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L380
	ucomiss	xmm0, xmm1
	je	.L381
.L380:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L381
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L381
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L381
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L253
.L381:
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L383
	ucomiss	xmm0, xmm1
	jne	.L383
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L383
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L383
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L383
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L385
.L383:
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L385
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L385
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L385
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L253
.L385:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L386
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	jne	.L386
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L386
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L386
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L386
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L386
	ucomiss	xmm0, xmm1
	je	.L388
.L386:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L388
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L388
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L388
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L388
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L253
.L388:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L390
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L391
.L390:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L392
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L391
.L392:
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L391
.L393:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L253
.L391:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	jne	.L394
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L395
.L394:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L396
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L395
.L396:
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L397
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L395
.L397:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L253
.L395:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L398
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L399
.L398:
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L399:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L401
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L401
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L402
.L401:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L402
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L253
.L402:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L405
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	jne	.L405
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L405
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L405
	movss	xmm0, DWORD PTR _x_t12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L405
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L406
.L405:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L406
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L406
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L406
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L406
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L253
.L406:
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L408
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L408
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L408
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L408
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L408
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L408
	ucomiss	xmm0, xmm1
	je	.L409
.L408:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L409
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L409
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L409
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L409
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L253
.L409:
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L411
	ucomiss	xmm0, xmm1
	jne	.L411
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L411
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L411
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L411
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L413
.L411:
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L413
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L413
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L413
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L413
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L253
.L413:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L414
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	jne	.L414
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L414
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L414
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L414
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L414
	ucomiss	xmm0, xmm1
	je	.L416
.L414:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L416
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L416
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L416
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L416
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L253
.L416:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L418
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L419
.L418:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L420
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L419
.L420:
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L419
.L421:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L253
.L419:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	jne	.L422
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L423
.L422:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L424
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L423
.L424:
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L425
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L423
.L425:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L253
.L423:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L426
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L427
.L426:
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L427:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L429
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L429
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L430
.L429:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L430
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L253
.L430:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	jne	.L433
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L433
	movss	xmm0, DWORD PTR _x_t11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L433
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L434
.L433:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L434
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L434
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L434
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L434
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L253
.L434:
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L436
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L436
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L436
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L436
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L436
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L436
	ucomiss	xmm0, xmm1
	je	.L437
.L436:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L437
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L437
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L437
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L253
.L437:
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L439
	ucomiss	xmm0, xmm1
	jne	.L439
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L439
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L439
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L439
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L441
.L439:
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L441
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L441
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L441
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L441
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L253
.L441:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L442
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	jne	.L442
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L442
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L442
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L442
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L442
	ucomiss	xmm0, xmm1
	je	.L444
.L442:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L444
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L444
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L444
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L253
.L444:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L446
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L447
.L446:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L448
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L447
.L448:
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L449
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L447
.L449:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L253
.L447:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L451
.L450:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L452
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L451
.L452:
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L453
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L451
.L453:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L253
.L451:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L454
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L455
.L454:
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L455:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L457
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L457
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L458
.L457:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L458
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L253
.L458:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L461
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	jne	.L461
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L461
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L461
	movss	xmm0, DWORD PTR _x_t10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L461
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L462
.L461:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L462
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L462
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L462
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L462
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L253
.L462:
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L464
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L464
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L464
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L464
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L464
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L464
	ucomiss	xmm0, xmm1
	je	.L465
.L464:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L465
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L465
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L465
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L253
.L465:
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L467
	ucomiss	xmm0, xmm1
	jne	.L467
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L467
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L467
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L467
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L469
.L467:
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L469
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L469
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L469
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L253
.L469:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L470
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	jne	.L470
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L470
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L470
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L470
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L470
	ucomiss	xmm0, xmm1
	je	.L472
.L470:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L472
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L472
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L472
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L472
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L253
.L472:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L474
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L475
.L474:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L475
.L476:
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L477
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L475
.L477:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L253
.L475:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	jne	.L478
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L479
.L478:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L480
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L479
.L480:
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L481
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L479
.L481:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L253
.L479:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L482
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L483
.L482:
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L483:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L485
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L485
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L485
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L486
.L485:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L486
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L253
.L486:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	jne	.L489
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L489
	movss	xmm0, DWORD PTR _x_t9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L489
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L490
.L489:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L490
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L490
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L490
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L490
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L253
.L490:
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L492
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L492
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L492
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L492
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L492
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L492
	ucomiss	xmm0, xmm1
	je	.L493
.L492:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L493
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L493
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L493
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L253
.L493:
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L495
	ucomiss	xmm0, xmm1
	jne	.L495
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L497
.L495:
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L497
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L497
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L497
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L497
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L253
.L497:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L498
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	jne	.L498
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L498
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L498
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L498
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L498
	ucomiss	xmm0, xmm1
	je	.L500
.L498:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L500
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L500
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L500
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L500
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L253
.L500:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L502
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L503
.L502:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L504
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L503
.L504:
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L503
.L505:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L253
.L503:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	jne	.L506
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L507
.L506:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L508
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L507
.L508:
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L507
.L509:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L253
.L507:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L510
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L511
.L510:
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L511:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L513
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L513
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L513
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L514
.L513:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L514
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L253
.L514:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L517
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	jne	.L517
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L517
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L517
	movss	xmm0, DWORD PTR _x_t8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L517
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L518
.L517:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L518
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L518
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L518
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L518
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L253
.L518:
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L520
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L520
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L520
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L520
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L520
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L520
	ucomiss	xmm0, xmm1
	je	.L521
.L520:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L521
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L521
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L521
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L521
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L253
.L521:
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L523
	ucomiss	xmm0, xmm1
	jne	.L523
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L523
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L523
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L523
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L525
.L523:
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L525
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L525
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L525
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L253
.L525:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	jne	.L526
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L526
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L526
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L526
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L526
	ucomiss	xmm0, xmm1
	je	.L528
.L526:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L528
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L528
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L528
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L528
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L253
.L528:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L530
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L531
.L530:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L532
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L531
.L532:
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L533
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L531
.L533:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L253
.L531:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L535
.L534:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L535
.L536:
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L535
.L537:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L253
.L535:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L538
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L539
.L538:
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L539:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L541
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L541
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L541
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L542
.L541:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L542
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L253
.L542:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	jne	.L545
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L545
	movss	xmm0, DWORD PTR _x_t7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L545
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L546
.L545:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L546
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L546
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L546
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L546
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L253
.L546:
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L548
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L548
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L548
	ucomiss	xmm0, xmm1
	je	.L549
.L548:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L549
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L549
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L549
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L549
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L253
.L549:
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L551
	ucomiss	xmm0, xmm1
	jne	.L551
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L551
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L551
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L551
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L553
.L551:
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L553
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L553
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L553
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L553
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L253
.L553:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L554
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	jne	.L554
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L554
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L554
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L554
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L554
	ucomiss	xmm0, xmm1
	je	.L556
.L554:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L556
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L556
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L556
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L556
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L253
.L556:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L558
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L559
.L558:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L560
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L559
.L560:
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L559
.L561:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L253
.L559:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L563
.L562:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L563
.L564:
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L565
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L563
.L565:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L253
.L563:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L566
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L567
.L566:
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L567:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L569
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L569
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L569
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L570
.L569:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L570
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L253
.L570:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	jne	.L573
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L573
	movss	xmm0, DWORD PTR _x_t6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L573
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L574
.L573:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L574
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L574
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L574
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L574
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L253
.L574:
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L576
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L576
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L576
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L576
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L576
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L576
	ucomiss	xmm0, xmm1
	je	.L577
.L576:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L577
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L577
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L577
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L577
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L253
.L577:
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L579
	ucomiss	xmm0, xmm1
	jne	.L579
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L579
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L579
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L579
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L581
.L579:
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L581
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L581
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L581
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L253
.L581:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L582
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	jne	.L582
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L582
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L582
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L582
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L582
	ucomiss	xmm0, xmm1
	je	.L584
.L582:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L584
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L584
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L584
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L253
.L584:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L586
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L587
.L586:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L588
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L587
.L588:
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L589
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L587
.L589:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L253
.L587:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	jne	.L590
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L591
.L590:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L592
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L591
.L592:
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L593
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L591
.L593:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L253
.L591:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L594
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L595
.L594:
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L595:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L597
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L597
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L598
.L597:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L598
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L253
.L598:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	jne	.L601
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L601
	movss	xmm0, DWORD PTR _x_t5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L601
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L602
.L601:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L602
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L602
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L602
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L602
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L253
.L602:
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L604
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L604
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L604
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L604
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L604
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L604
	ucomiss	xmm0, xmm1
	je	.L605
.L604:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L605
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L605
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L605
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L605
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L253
.L605:
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L607
	ucomiss	xmm0, xmm1
	jne	.L607
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L607
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L607
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L607
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L609
.L607:
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L609
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L609
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L609
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L253
.L609:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L610
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	jne	.L610
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L610
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L610
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L610
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L610
	ucomiss	xmm0, xmm1
	je	.L612
.L610:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L612
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L612
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L612
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L612
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L253
.L612:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L614
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L615
.L614:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L616
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L615
.L616:
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L615
.L617:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L253
.L615:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	jne	.L618
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L619
.L618:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L619
.L620:
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L621
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L619
.L621:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L253
.L619:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L622
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L623
.L622:
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L623:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L625
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L625
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L625
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L626
.L625:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L626
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L253
.L626:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L629
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	jne	.L629
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L629
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L629
	movss	xmm0, DWORD PTR _x_t4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L629
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L630
.L629:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L630
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L630
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L630
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L630
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L253
.L630:
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L632
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L632
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L632
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L632
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L632
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L632
	ucomiss	xmm0, xmm1
	je	.L633
.L632:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L633
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L633
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L633
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L253
.L633:
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L635
	ucomiss	xmm0, xmm1
	jne	.L635
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L635
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L635
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L635
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L637
.L635:
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L637
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L637
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L637
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L253
.L637:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L638
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	jne	.L638
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L638
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L638
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L638
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L638
	ucomiss	xmm0, xmm1
	je	.L640
.L638:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L640
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L640
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L640
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L640
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L253
.L640:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L643
.L642:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L644
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L643
.L644:
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L643
.L645:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L253
.L643:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	jne	.L646
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L647
.L646:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L648
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L647
.L648:
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L649
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L647
.L649:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L253
.L647:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L650
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L651
.L650:
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L651:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L653
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L653
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L654
.L653:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L654
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L253
.L654:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L657
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	jne	.L657
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L657
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L657
	movss	xmm0, DWORD PTR _x_t3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L657
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L658
.L657:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L658
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L658
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L658
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L658
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L253
.L658:
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L660
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L660
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L660
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L660
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L660
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L660
	ucomiss	xmm0, xmm1
	je	.L661
.L660:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L661
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L661
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L661
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L661
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L253
.L661:
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L663
	ucomiss	xmm0, xmm1
	jne	.L663
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L663
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L663
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L663
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L665
.L663:
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L665
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L665
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L665
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L665
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L253
.L665:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L666
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	jne	.L666
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L666
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L666
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L666
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L666
	ucomiss	xmm0, xmm1
	je	.L668
.L666:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L668
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L668
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L668
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L668
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L253
.L668:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L670
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L671
.L670:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L672
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L671
.L672:
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L673
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L671
.L673:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L253
.L671:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	jne	.L674
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L675
.L674:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L676
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L675
.L676:
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L677
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L675
.L677:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L253
.L675:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L678
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L679
.L678:
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L679:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L681
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L681
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L682
.L681:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L682
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L253
.L682:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	jne	.L685
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L685
	movss	xmm0, DWORD PTR _x_t2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L685
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L686
.L685:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L686
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L686
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L686
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L686
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L253
.L686:
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L688
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L688
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L688
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L688
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L688
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L688
	ucomiss	xmm0, xmm1
	je	.L689
.L688:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L689
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L689
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L689
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L689
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L253
.L689:
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L691
	ucomiss	xmm0, xmm1
	jne	.L691
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L691
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L691
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L691
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L693
.L691:
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L693
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L693
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L693
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L693
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L253
.L693:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L694
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	jne	.L694
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L694
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L694
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L694
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L694
	ucomiss	xmm0, xmm1
	je	.L696
.L694:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L696
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L696
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L696
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L696
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L253
.L696:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L698
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L699
.L698:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L700
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L699
.L700:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L701
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L699
.L701:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L253
.L699:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	jne	.L702
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L703
.L702:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L703
.L704:
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L703
.L705:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L253
.L703:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L706
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L707
.L706:
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L707:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L709
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L709
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L709
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L710
.L709:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L710
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L253
.L710:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L713
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L713
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L713
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L713
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L713
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L714
.L713:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L714
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L714
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L714
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L714
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L253
.L714:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L716
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L716
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L716
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L716
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L716
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L716
	ucomiss	xmm0, xmm1
	je	.L717
.L716:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L717
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L717
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L717
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L717
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L253
.L717:
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L719
	ucomiss	xmm0, xmm1
	jne	.L719
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L719
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L719
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L719
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L721
.L719:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L721
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L721
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L721
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L721
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L253
.L721:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L722
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L722
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L722
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L722
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L722
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L722
	ucomiss	xmm0, xmm1
	je	.L724
.L722:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L724
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L724
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L724
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L724
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L253
.L724:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L726
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L727
.L726:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L727
.L728:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L729
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L727
.L729:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L253
.L727:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	jne	.L730
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L731
.L730:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L732
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L731
.L732:
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L733
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L731
.L733:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L253
.L731:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L734
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L735
.L734:
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L253
.L735:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L737
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L737
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L737
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L738
.L737:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L738
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L253
.L738:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L741
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L741
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L741
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L742
.L741:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L742
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L742
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L742
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L742
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L253
.L742:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L744
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L744
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L744
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L744
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L744
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L744
	ucomiss	xmm0, xmm1
	je	.L745
.L744:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L745
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L745
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L745
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L745
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L253
.L745:
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L747
	ucomiss	xmm0, xmm1
	jne	.L747
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L749
.L747:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L749
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L749
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L749
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L749
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L253
.L749:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L750
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L750
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L750
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L750
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L750
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L750
	ucomiss	xmm0, xmm1
	je	.L752
.L750:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L752
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L752
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L752
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L752
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L253
.L752:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L754
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L755
.L754:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L756
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L755
.L756:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L757
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L755
.L757:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L253
.L755:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L758
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L758
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L759
.L758:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L760
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L760
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L759
.L760:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L759
.L761:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L762
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L762
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L759
.L762:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L253
.L759:
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 2
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 3
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 4
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 5
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 6
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 7
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 8
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 9
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 10
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 11
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 12
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 13
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 14
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 15
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 16
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 17
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 18
	je	.L763
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 19
	jne	.L253
.L763:
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L764
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L765
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L253
.L765:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L253
.L764:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L766
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L766
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR controller_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_controller_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L766
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L766
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	je	.L768
.L766:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L768
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L768
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L253
.L768:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L770
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L770
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L770
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	jne	.L770
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L770
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L771
.L770:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L771
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L771
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L771
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L771
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L253
.L771:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L773
	ucomiss	xmm0, xmm1
	jne	.L773
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L775
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L776
.L775:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L773
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L776
.L773:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L776
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L776
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L776
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L776
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L253
.L776:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L777
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L777
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L777
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L778
.L777:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L779
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L779
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L779
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L778
.L779:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L778
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L778
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L780
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L780
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L778
.L780:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L778
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L778
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L778
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L253
.L778:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L781
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L781
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L781
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	jne	.L781
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jp	.L781
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	je	.L782
.L781:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L782
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L782
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L784
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L784
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L782
.L784:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L782
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L782
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L782
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L253
.L782:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L785
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L786
.L785:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L787
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L786
.L787:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L786
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L786
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L786
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L253
.L786:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L788
	ucomiss	xmm0, xmm1
	jne	.L788
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L790
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L790
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L790
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L791
.L790:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L788
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L788
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L788
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L788
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jg	.L791
.L788:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L791
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L791
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L792
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L792
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L791
.L792:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L791
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L791
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L791
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L253
.L791:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L793
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L793
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L793
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jne	.L793
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	jne	.L793
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L793
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L794
.L793:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L794
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L794
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L796
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L796
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L794
.L796:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L794
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L794
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L794
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L253
.L794:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L797
	ucomiss	xmm0, xmm1
	jne	.L797
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L799
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L800
.L799:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L797
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L800
.L797:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L800
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L800
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L800
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L253
.L800:
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	jne	.L801
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L801
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L801
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L801
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L802
.L801:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L802
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L802
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L802
.L803:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L802
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L802
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L802
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L253
.L802:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L804
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L805
.L804:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L806
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L805
.L806:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L807
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L805
.L807:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L253
.L805:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	jne	.L808
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L809
.L808:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L810
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L809
.L810:
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L811
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L809
.L811:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L253
.L809:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L812
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L812
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L253
.L812:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L813
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L813
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L253
.L813:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L814
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L814
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR gate_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_gate_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L814
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L815
.L814:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L817
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L253
.L817:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L253
.L815:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L819
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L819
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L819
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L819
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L819
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L820
.L819:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L820
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L820
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L820
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L820
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L253
.L820:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L822
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L822
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L822
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L822
	ucomiss	xmm0, xmm1
	je	.L824
.L822:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L824
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L824
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L824
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L824
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L253
.L824:
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L826
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L826
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L826
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L826
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L826
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L828
.L826:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L828
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L828
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L828
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L828
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L253
.L828:
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L829
	ucomiss	xmm0, xmm1
	jne	.L829
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L829
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L829
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L829
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L829
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L829
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L832
.L829:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L832
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L832
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L832
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L832
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L253
.L832:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L253
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L834
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L835
.L834:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L835
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L835
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L253
.L835:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L836
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L837
.L836:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L837
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L837
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L253
.L837:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L838
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L839
.L838:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L839
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L839
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L253
.L839:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L840
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L841
.L840:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L841
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L841
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L253
.L841:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L842
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L843
.L842:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L843
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L843
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L253
.L843:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L844
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L845
.L844:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L845
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L845
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L253
.L845:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L846
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L847
.L846:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L847
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L847
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L253
.L847:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L848
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L849
.L848:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L849
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L849
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L253
.L849:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L850
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L851
.L850:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L851
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L851
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L253
.L851:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L853
.L852:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L853
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L853
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L253
.L853:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L854
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L855
.L854:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L855
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L855
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L253
.L855:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L856
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L857
.L856:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L857
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L857
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L253
.L857:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L858
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L859
.L858:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L859
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L859
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L253
.L859:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L860
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L861
.L860:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L861
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L861
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L253
.L861:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L862
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L863
.L862:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L863
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L863
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L253
.L863:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L864
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L865
.L864:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L865
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L865
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L253
.L865:
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L866
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L867
.L866:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L867
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L867
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L253
.L867:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L868
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L869
.L868:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L869
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L869
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	jne	.L253
.L869:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L870
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L870
	mov	eax, 1
	jmp	.L871
.L870:
	mov	eax, 0
.L871:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L872
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L872
	mov	eax, 1
	jmp	.L873
.L872:
	mov	eax, 0
.L873:
	and	eax, 1
	xor	eax, edx
	test	al, al
	jne	.L874
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L874
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L253
.L874:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L876
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L876
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L877
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L877
	mov	eax, 1
	jmp	.L878
.L877:
	mov	eax, 0
.L878:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L879
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L879
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L879
	mov	eax, 1
	jmp	.L880
.L879:
	mov	eax, 0
.L880:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L253
.L876:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L881
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L881
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L882
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L882
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L882
	mov	eax, 1
	jmp	.L883
.L882:
	mov	eax, 0
.L883:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	je	.L884
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L885
.L884:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L886
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L885
.L886:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L887
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L885
.L887:
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L888
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L885
.L888:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L889
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L885
.L889:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L890
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L885
.L890:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L891
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L885
.L891:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L892
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L885
.L892:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L893
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L885
.L893:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L894
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L885
.L894:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L895
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L885
.L895:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L896
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L885
.L896:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L897
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L885
.L897:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L898
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L885
.L898:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L899
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L885
.L899:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L900
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L885
.L900:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L901
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L885
.L901:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L902
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L902
.L885:
	mov	eax, 1
	jmp	.L903
.L902:
	mov	eax, 0
.L903:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L253
.L881:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L904
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L904
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L905
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L905
	mov	eax, 1
	jmp	.L906
.L905:
	mov	eax, 0
.L906:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t17_evt1[rip]
	test	al, al
	je	.L907
	movzx	eax, BYTE PTR t17_evt0[rip]
	test	al, al
	je	.L908
.L907:
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L909
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L908
.L909:
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L910
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L908
.L910:
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L911
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L908
.L911:
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L912
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L908
.L912:
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L913
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L908
.L913:
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L914
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L908
.L914:
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L915
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L908
.L915:
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L916
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L908
.L916:
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L917
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L908
.L917:
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L918
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L908
.L918:
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L919
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L908
.L919:
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L920
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L908
.L920:
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L908
.L921:
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L922
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L908
.L922:
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L923
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L908
.L923:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L924
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L908
.L924:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L925
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L925
.L908:
	mov	eax, 1
	jmp	.L926
.L925:
	mov	eax, 0
.L926:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L253
.L904:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L1020
	ucomiss	xmm0, xmm1
	je	.L927
.L1020:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L253
.L927:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L929
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L253
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L253
.L929:
	mov	eax, 1
	jmp	.L931
.L253:
	mov	eax, 0
.L931:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_t17_l1[rip]
	mov	BYTE PTR t17_l1[rip], al
	movzx	eax, BYTE PTR _x_t17_l0[rip]
	mov	BYTE PTR t17_l0[rip], al
	movzx	eax, BYTE PTR _x_t17_evt1[rip]
	mov	BYTE PTR t17_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t17_x[rip]
	movss	DWORD PTR t17_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	mov	BYTE PTR t16_l1[rip], al
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	mov	BYTE PTR t16_l0[rip], al
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	mov	BYTE PTR t16_evt1[rip], al
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	mov	BYTE PTR t16_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t16_x[rip]
	movss	DWORD PTR t16_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	mov	BYTE PTR t15_l1[rip], al
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	mov	BYTE PTR t15_l0[rip], al
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	mov	BYTE PTR t15_evt1[rip], al
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	mov	BYTE PTR t15_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t15_x[rip]
	movss	DWORD PTR t15_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	mov	BYTE PTR t14_l1[rip], al
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	mov	BYTE PTR t14_l0[rip], al
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	mov	BYTE PTR t14_evt1[rip], al
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	mov	BYTE PTR t14_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t14_x[rip]
	movss	DWORD PTR t14_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	mov	BYTE PTR t13_l1[rip], al
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	mov	BYTE PTR t13_l0[rip], al
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	mov	BYTE PTR t13_evt1[rip], al
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	mov	BYTE PTR t13_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t13_x[rip]
	movss	DWORD PTR t13_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	mov	BYTE PTR t12_l1[rip], al
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	mov	BYTE PTR t12_l0[rip], al
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	mov	BYTE PTR t12_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t12_x[rip]
	movss	DWORD PTR t12_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	mov	BYTE PTR t11_l1[rip], al
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	mov	BYTE PTR t11_l0[rip], al
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	mov	BYTE PTR t11_evt1[rip], al
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	mov	BYTE PTR t11_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t11_x[rip]
	movss	DWORD PTR t11_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	mov	BYTE PTR t10_l1[rip], al
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	mov	BYTE PTR t10_l0[rip], al
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	mov	BYTE PTR t10_evt1[rip], al
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	mov	BYTE PTR t10_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t10_x[rip]
	movss	DWORD PTR t10_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	mov	BYTE PTR t9_l1[rip], al
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	mov	BYTE PTR t9_l0[rip], al
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	mov	BYTE PTR t9_evt1[rip], al
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	mov	BYTE PTR t9_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t3_x[rip]
	movss	DWORD PTR t3_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	mov	BYTE PTR t2_evt1[rip], al
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	mov	BYTE PTR t2_l1[rip], al
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	mov	BYTE PTR t3_evt0[rip], al
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	mov	BYTE PTR t2_l0[rip], al
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	mov	BYTE PTR t1_l1[rip], al
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	mov	BYTE PTR t2_evt0[rip], al
	movzx	eax, BYTE PTR _x_t17_evt0[rip]
	mov	BYTE PTR t17_evt0[rip], al
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	mov	BYTE PTR controller_evt2[rip], al
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	mov	BYTE PTR t1_l0[rip], al
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	mov	BYTE PTR controller_evt1[rip], al
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	mov	BYTE PTR t1_evt1[rip], al
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	mov	BYTE PTR t1_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	movss	DWORD PTR t1_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	mov	BYTE PTR t0_evt1[rip], al
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	mov	BYTE PTR t0_l0[rip], al
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	mov	BYTE PTR t0_evt0[rip], al
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	mov	DWORD PTR controller_cnt[rip], eax
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	mov	BYTE PTR t12_evt1[rip], al
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	mov	BYTE PTR gate_l0[rip], al
	movss	xmm0, DWORD PTR _x_t2_x[rip]
	movss	DWORD PTR t2_x[rip], xmm0
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	mov	BYTE PTR controller_l0[rip], al
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	mov	BYTE PTR controller_l1[rip], al
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	mov	BYTE PTR t0_l1[rip], al
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	mov	BYTE PTR controller_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	movss	DWORD PTR t0_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	movss	DWORD PTR controller_z[rip], xmm0
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	mov	BYTE PTR t3_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t4_x[rip]
	movss	DWORD PTR t4_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	mov	BYTE PTR t3_l0[rip], al
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	mov	BYTE PTR t3_l1[rip], al
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	mov	BYTE PTR t4_evt0[rip], al
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	mov	BYTE PTR t4_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t5_x[rip]
	movss	DWORD PTR t5_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	mov	BYTE PTR t4_l0[rip], al
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	mov	BYTE PTR t4_l1[rip], al
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	movss	DWORD PTR gate_y[rip], xmm0
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	mov	BYTE PTR t5_evt0[rip], al
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	mov	BYTE PTR t5_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t6_x[rip]
	movss	DWORD PTR t6_x[rip], xmm0
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	mov	BYTE PTR gate_evt0[rip], al
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	mov	BYTE PTR t5_l0[rip], al
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	mov	BYTE PTR gate_evt1[rip], al
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	mov	BYTE PTR t5_l1[rip], al
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	mov	BYTE PTR t6_evt0[rip], al
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	mov	BYTE PTR t6_evt1[rip], al
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	mov	BYTE PTR gate_l1[rip], al
	movss	xmm0, DWORD PTR _x_t7_x[rip]
	movss	DWORD PTR t7_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	mov	BYTE PTR t6_l0[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	mov	BYTE PTR t6_l1[rip], al
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	mov	BYTE PTR t7_evt0[rip], al
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	mov	BYTE PTR t7_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t8_x[rip]
	movss	DWORD PTR t8_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	mov	BYTE PTR t7_l0[rip], al
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	mov	BYTE PTR t7_l1[rip], al
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	mov	BYTE PTR t8_evt0[rip], al
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	mov	BYTE PTR t8_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t9_x[rip]
	movss	DWORD PTR t9_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	mov	BYTE PTR t8_l0[rip], al
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	mov	BYTE PTR t8_l1[rip], al
.L248:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L932
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1084227584
	.align 4
.LC2:
	.long	1065353216
	.align 4
.LC3:
	.long	1073741824
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"778532.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	t17_l1,1,1
	.comm	_x_t17_l1,1,1
	.comm	t17_l0,1,1
	.comm	_x_t17_l0,1,1
	.comm	t17_evt1,1,1
	.comm	_x_t17_evt1,1,1
	.comm	t17_x,4,4
	.comm	_x_t17_x,4,4
	.comm	t16_l1,1,1
	.comm	_x_t16_l1,1,1
	.comm	t16_l0,1,1
	.comm	_x_t16_l0,1,1
	.comm	t16_evt1,1,1
	.comm	_x_t16_evt1,1,1
	.comm	t16_evt0,1,1
	.comm	_x_t16_evt0,1,1
	.comm	t16_x,4,4
	.comm	_x_t16_x,4,4
	.comm	t15_l1,1,1
	.comm	_x_t15_l1,1,1
	.comm	t15_l0,1,1
	.comm	_x_t15_l0,1,1
	.comm	t15_evt1,1,1
	.comm	_x_t15_evt1,1,1
	.comm	t15_evt0,1,1
	.comm	_x_t15_evt0,1,1
	.comm	t15_x,4,4
	.comm	_x_t15_x,4,4
	.comm	t14_l1,1,1
	.comm	_x_t14_l1,1,1
	.comm	t14_l0,1,1
	.comm	_x_t14_l0,1,1
	.comm	t14_evt1,1,1
	.comm	_x_t14_evt1,1,1
	.comm	t14_evt0,1,1
	.comm	_x_t14_evt0,1,1
	.comm	t14_x,4,4
	.comm	_x_t14_x,4,4
	.comm	t13_l1,1,1
	.comm	_x_t13_l1,1,1
	.comm	t13_l0,1,1
	.comm	_x_t13_l0,1,1
	.comm	t13_evt1,1,1
	.comm	_x_t13_evt1,1,1
	.comm	t13_evt0,1,1
	.comm	_x_t13_evt0,1,1
	.comm	t13_x,4,4
	.comm	_x_t13_x,4,4
	.comm	t12_l1,1,1
	.comm	_x_t12_l1,1,1
	.comm	t12_l0,1,1
	.comm	_x_t12_l0,1,1
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	t12_evt0,1,1
	.comm	_x_t12_evt0,1,1
	.comm	t12_x,4,4
	.comm	_x_t12_x,4,4
	.comm	t11_l1,1,1
	.comm	_x_t11_l1,1,1
	.comm	t11_l0,1,1
	.comm	_x_t11_l0,1,1
	.comm	t11_evt1,1,1
	.comm	_x_t11_evt1,1,1
	.comm	t11_evt0,1,1
	.comm	_x_t11_evt0,1,1
	.comm	t11_x,4,4
	.comm	_x_t11_x,4,4
	.comm	t10_l1,1,1
	.comm	_x_t10_l1,1,1
	.comm	t10_l0,1,1
	.comm	_x_t10_l0,1,1
	.comm	t10_evt1,1,1
	.comm	_x_t10_evt1,1,1
	.comm	t10_evt0,1,1
	.comm	_x_t10_evt0,1,1
	.comm	t10_x,4,4
	.comm	_x_t10_x,4,4
	.comm	t9_l1,1,1
	.comm	_x_t9_l1,1,1
	.comm	t9_l0,1,1
	.comm	_x_t9_l0,1,1
	.comm	t9_evt1,1,1
	.comm	_x_t9_evt1,1,1
	.comm	t9_evt0,1,1
	.comm	_x_t9_evt0,1,1
	.comm	t3_x,4,4
	.comm	_x_t3_x,4,4
	.comm	t2_evt1,1,1
	.comm	_x_t2_evt1,1,1
	.comm	t2_l1,1,1
	.comm	_x_t2_l1,1,1
	.comm	t3_evt0,1,1
	.comm	_x_t3_evt0,1,1
	.comm	t2_l0,1,1
	.comm	_x_t2_l0,1,1
	.comm	t1_l1,1,1
	.comm	_x_t1_l1,1,1
	.comm	t2_evt0,1,1
	.comm	_x_t2_evt0,1,1
	.comm	t17_evt0,1,1
	.comm	_x_t17_evt0,1,1
	.comm	controller_evt2,1,1
	.comm	_x_controller_evt2,1,1
	.comm	t1_l0,1,1
	.comm	_x_t1_l0,1,1
	.comm	controller_evt1,1,1
	.comm	_x_controller_evt1,1,1
	.comm	t1_evt1,1,1
	.comm	_x_t1_evt1,1,1
	.comm	t1_evt0,1,1
	.comm	_x_t1_evt0,1,1
	.comm	t1_x,4,4
	.comm	_x_t1_x,4,4
	.comm	t0_evt1,1,1
	.comm	_x_t0_evt1,1,1
	.comm	t0_l0,1,1
	.comm	_x_t0_l0,1,1
	.comm	t0_evt0,1,1
	.comm	_x_t0_evt0,1,1
	.comm	controller_cnt,4,4
	.comm	_x_controller_cnt,4,4
	.comm	t12_evt1,1,1
	.comm	_x_t12_evt1,1,1
	.comm	gate_l0,1,1
	.comm	_x_gate_l0,1,1
	.comm	t2_x,4,4
	.comm	_x_t2_x,4,4
	.comm	controller_l0,1,1
	.comm	_x_controller_l0,1,1
	.comm	controller_l1,1,1
	.comm	_x_controller_l1,1,1
	.comm	t0_l1,1,1
	.comm	_x_t0_l1,1,1
	.comm	controller_evt0,1,1
	.comm	_x_controller_evt0,1,1
	.comm	t0_x,4,4
	.comm	_x_t0_x,4,4
	.comm	controller_z,4,4
	.comm	_x_controller_z,4,4
	.comm	t3_evt1,1,1
	.comm	_x_t3_evt1,1,1
	.comm	t4_x,4,4
	.comm	_x_t4_x,4,4
	.comm	t3_l0,1,1
	.comm	_x_t3_l0,1,1
	.comm	t3_l1,1,1
	.comm	_x_t3_l1,1,1
	.comm	t4_evt0,1,1
	.comm	_x_t4_evt0,1,1
	.comm	t4_evt1,1,1
	.comm	_x_t4_evt1,1,1
	.comm	t5_x,4,4
	.comm	_x_t5_x,4,4
	.comm	t4_l0,1,1
	.comm	_x_t4_l0,1,1
	.comm	t4_l1,1,1
	.comm	_x_t4_l1,1,1
	.comm	gate_y,4,4
	.comm	_x_gate_y,4,4
	.comm	t5_evt0,1,1
	.comm	_x_t5_evt0,1,1
	.comm	t5_evt1,1,1
	.comm	_x_t5_evt1,1,1
	.comm	t6_x,4,4
	.comm	_x_t6_x,4,4
	.comm	gate_evt0,1,1
	.comm	_x_gate_evt0,1,1
	.comm	t5_l0,1,1
	.comm	_x_t5_l0,1,1
	.comm	gate_evt1,1,1
	.comm	_x_gate_evt1,1,1
	.comm	t5_l1,1,1
	.comm	_x_t5_l1,1,1
	.comm	t6_evt0,1,1
	.comm	_x_t6_evt0,1,1
	.comm	t6_evt1,1,1
	.comm	_x_t6_evt1,1,1
	.comm	gate_l1,1,1
	.comm	_x_gate_l1,1,1
	.comm	t7_x,4,4
	.comm	_x_t7_x,4,4
	.comm	t6_l0,1,1
	.comm	_x_t6_l0,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	t6_l1,1,1
	.comm	_x_t6_l1,1,1
	.comm	t7_evt0,1,1
	.comm	_x_t7_evt0,1,1
	.comm	t7_evt1,1,1
	.comm	_x_t7_evt1,1,1
	.comm	t8_x,4,4
	.comm	_x_t8_x,4,4
	.comm	t7_l0,1,1
	.comm	_x_t7_l0,1,1
	.comm	t7_l1,1,1
	.comm	_x_t7_l1,1,1
	.comm	t8_evt0,1,1
	.comm	_x_t8_evt0,1,1
	.comm	t8_evt1,1,1
	.comm	_x_t8_evt1,1,1
	.comm	t9_x,4,4
	.comm	_x_t9_x,4,4
	.comm	t8_l0,1,1
	.comm	_x_t8_l0,1,1
	.comm	t8_l1,1,1
	.comm	_x_t8_l1,1,1
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+12
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+32
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+36
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+52
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+64
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+72
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+88
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+92
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+96
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+200
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+204
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+220
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+236
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+228
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+240
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+380
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+388
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+396
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+364
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+412
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+384
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+408
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+416
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L960+132
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+400
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+156
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+160
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+368
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+360
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+376
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+340
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+356
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+164
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+324
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+328
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+320
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+332
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+336
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+308
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+300
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+180
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+288
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+280
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+292
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L960+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L960+276
	strb	r2, [r3]
	ldr	r3, .L960+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L960
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L960+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L960
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L960
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L960+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L960+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L7:
	ldr	r3, .L960+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L960+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L10:
	ldr	r3, .L960+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L960+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L12:
	ldr	r3, .L960+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L960+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L13:
	ldr	r3, .L960+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L11:
	ldr	r3, .L960+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L960
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
.L14:
	ldr	r3, .L960+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L15:
	ldr	r3, .L960+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L960+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L18:
	ldr	r3, .L960+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L960+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L20:
	ldr	r3, .L960+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L960+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L21:
	ldr	r3, .L960+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L19:
	ldr	r3, .L960+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L960+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L22:
	ldr	r3, .L960+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L960+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L24:
	ldr	r3, .L960+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L960+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L25:
	ldr	r3, .L960+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L23:
	ldr	r3, .L960+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L960+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L26:
	ldr	r3, .L960+32
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L27:
	ldr	r3, .L960+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L960+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L30:
	ldr	r3, .L960+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L960+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L32:
	ldr	r3, .L960+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L960+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L33:
	ldr	r3, .L960+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L31:
	ldr	r3, .L960+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L960+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L34:
	ldr	r3, .L960+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L960+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L36:
	ldr	r3, .L960+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L960+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L37:
	ldr	r3, .L960+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L35:
	ldr	r3, .L960+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L960+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
.L38:
	ldr	r3, .L960+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L39:
	ldr	r3, .L960+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L960+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L42:
	ldr	r3, .L960+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L960+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L44:
	ldr	r3, .L960+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L960+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L45:
	ldr	r3, .L960+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L43:
	ldr	r3, .L960+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L46
	ldr	r3, .L960+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L46:
	ldr	r3, .L960+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L960+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L48:
	ldr	r3, .L960+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L960+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L49:
	ldr	r3, .L960+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L47:
	ldr	r3, .L960+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L50
	ldr	r3, .L960+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
.L50:
	ldr	r3, .L960+72
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L51:
	ldr	r3, .L960+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L54
	ldr	r3, .L960+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L54:
	ldr	r3, .L960+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L960+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L56:
	ldr	r3, .L960+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L960+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L57:
	ldr	r3, .L960+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L55:
	ldr	r3, .L960+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L960+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L58:
	ldr	r3, .L960+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L960+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L60:
	ldr	r3, .L960+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L960+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L61:
	ldr	r3, .L960+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L59:
	ldr	r3, .L960+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L960+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L62:
	ldr	r3, .L960+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L63:
	ldr	r3, .L960+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L960+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L66:
	ldr	r3, .L960+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L960+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L68:
	ldr	r3, .L960+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L960+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L69:
	ldr	r3, .L960+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	b	.L961
.L962:
	.align	2
.L960:
	.word	t17_l1
	.word	t17_l0
	.word	t17_evt1
	.word	t17_x
	.word	t16_l1
	.word	t16_l0
	.word	t16_evt1
	.word	t16_evt0
	.word	t16_x
	.word	t15_l1
	.word	t15_l0
	.word	t15_evt1
	.word	t15_evt0
	.word	t15_x
	.word	t14_l1
	.word	t14_l0
	.word	t14_evt1
	.word	t14_evt0
	.word	t14_x
	.word	t13_l1
	.word	t13_l0
	.word	t13_evt1
	.word	t13_evt0
	.word	t13_x
	.word	_diverge_delta
	.word	t17_evt0
	.word	controller_evt2
	.word	controller_evt1
	.word	t1_evt1
	.word	t1_evt0
	.word	t0_evt1
	.word	t0_l0
	.word	t0_evt0
	.word	controller_cnt
	.word	gate_l0
	.word	controller_l0
	.word	controller_l1
	.word	t0_l1
	.word	controller_evt0
	.word	t0_x
	.word	controller_z
	.word	gate_y
	.word	gate_evt0
	.word	gate_evt1
	.word	gate_l1
	.word	delta
	.word	t12_evt0
	.word	t12_evt1
	.word	t12_l0
	.word	t12_l1
	.word	t12_x
	.word	t11_evt0
	.word	t11_evt1
	.word	t11_l0
	.word	t11_l1
	.word	t11_x
	.word	t10_evt0
	.word	t10_evt1
	.word	t10_l0
	.word	t10_l1
	.word	t10_x
	.word	t9_evt0
	.word	t9_evt1
	.word	t9_l0
	.word	t9_l1
	.word	t9_x
	.word	t8_evt0
	.word	t8_evt1
	.word	t8_l0
	.word	t8_l1
	.word	t8_x
	.word	t7_evt0
	.word	t7_evt1
	.word	t7_l0
	.word	t7_l1
	.word	t7_x
	.word	t6_evt0
	.word	t6_evt1
	.word	t6_l0
	.word	t6_l1
	.word	t6_x
	.word	t5_evt0
	.word	t5_evt1
	.word	t5_l0
	.word	t5_l1
	.word	t5_x
	.word	t4_evt0
	.word	t4_evt1
	.word	t4_l0
	.word	t4_l1
	.word	t4_x
	.word	t3_evt0
	.word	t3_evt1
	.word	t3_l0
	.word	t3_l1
	.word	t3_x
	.word	t2_evt0
	.word	t2_evt1
	.word	t2_l0
	.word	t2_l1
	.word	t2_x
	.word	1084227584
	.word	t1_l0
	.word	t1_l1
	.word	t1_x
.L961:
.L67:
	ldr	r3, .L960+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L960+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L70:
	ldr	r3, .L960+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L960+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L72:
	ldr	r3, .L960+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L73
	ldr	r3, .L960+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L73:
	ldr	r3, .L960+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L71:
	ldr	r3, .L960+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L960+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
.L74:
	ldr	r3, .L960+200
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L75:
	ldr	r3, .L960+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L960+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L78:
	ldr	r3, .L960+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L960+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L80:
	ldr	r3, .L960+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L960+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L81:
	ldr	r3, .L960+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L79:
	ldr	r3, .L960+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L960+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L82:
	ldr	r3, .L960+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L960+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L84:
	ldr	r3, .L960+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L960+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L85:
	ldr	r3, .L960+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L83:
	ldr	r3, .L960+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L86
	ldr	r3, .L960+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
.L86:
	ldr	r3, .L960+220
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L87:
	ldr	r3, .L960+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+240
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
	ldr	r3, .L960+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L90:
	ldr	r3, .L960+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L960+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L92:
	ldr	r3, .L960+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
	ldr	r3, .L960+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L93:
	ldr	r3, .L960+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L91:
	ldr	r3, .L960+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L960+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L94:
	ldr	r3, .L960+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L960+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L96:
	ldr	r3, .L960+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L960+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L97:
	ldr	r3, .L960+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L95:
	ldr	r3, .L960+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L960+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
.L98:
	ldr	r3, .L960+240
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L99:
	ldr	r3, .L960+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L102
	ldr	r3, .L960+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L102:
	ldr	r3, .L960+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L960+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L104:
	ldr	r3, .L960+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L960+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L105:
	ldr	r3, .L960+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L103:
	ldr	r3, .L960+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L960+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L106:
	ldr	r3, .L960+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L960+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L108:
	ldr	r3, .L960+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L960+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L109:
	ldr	r3, .L960+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L107:
	ldr	r3, .L960+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L960+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
.L110:
	ldr	r3, .L960+260
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L111:
	ldr	r3, .L960+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+280
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L960+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L114:
	ldr	r3, .L960+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L960+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L116:
	ldr	r3, .L960+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L960+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L117:
	ldr	r3, .L960+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L115:
	ldr	r3, .L960+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L960+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L118:
	ldr	r3, .L960+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L960+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L120:
	ldr	r3, .L960+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
	ldr	r3, .L960+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L121:
	ldr	r3, .L960+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L119:
	ldr	r3, .L960+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L960+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
.L122:
	ldr	r3, .L960+280
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L123:
	ldr	r3, .L960+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+300
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L960+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L126:
	ldr	r3, .L960+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L960+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L128:
	ldr	r3, .L960+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L960+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L129:
	ldr	r3, .L960+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L127:
	ldr	r3, .L960+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L960+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L130:
	ldr	r3, .L960+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L960+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L132:
	ldr	r3, .L960+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L133
	ldr	r3, .L960+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L133:
	ldr	r3, .L960+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L131:
	ldr	r3, .L960+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L960+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
.L134:
	ldr	r3, .L960+300
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L135:
	ldr	r3, .L960+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+320
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L960+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L138:
	ldr	r3, .L960+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L960+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L140:
	ldr	r3, .L960+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L960+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L141:
	ldr	r3, .L960+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L139:
	ldr	r3, .L960+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L960+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L142:
	ldr	r3, .L960+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L960+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L144:
	ldr	r3, .L960+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L145
	ldr	r3, .L960+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L145:
	ldr	r3, .L960+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L143:
	ldr	r3, .L960+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L960+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
.L146:
	ldr	r3, .L960+320
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L147:
	ldr	r3, .L960+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L150
	ldr	r3, .L960+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L150:
	ldr	r3, .L960+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L960+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L152:
	ldr	r3, .L960+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L960+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L153:
	ldr	r3, .L960+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L151:
	ldr	r3, .L960+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L960+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L154:
	ldr	r3, .L960+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L960+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L156:
	ldr	r3, .L960+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L960+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L157:
	ldr	r3, .L960+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L155:
	ldr	r3, .L960+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
	ldr	r3, .L960+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L158:
	ldr	r3, .L960+340
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L159:
	ldr	r3, .L960+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+360
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L960+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L162:
	ldr	r3, .L960+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L960+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L164:
	ldr	r3, .L960+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L960+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L165:
	ldr	r3, .L960+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L163:
	ldr	r3, .L960+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L960+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L166:
	ldr	r3, .L960+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L960+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L168:
	ldr	r3, .L960+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L960+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L169:
	ldr	r3, .L960+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L167:
	ldr	r3, .L960+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L170
	ldr	r3, .L960+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L171
.L170:
	ldr	r3, .L960+360
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L171:
	ldr	r3, .L960+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+380
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L960+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L174:
	ldr	r3, .L960+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L960+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L176:
	ldr	r3, .L960+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L960+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L177:
	ldr	r3, .L960+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L175:
	ldr	r3, .L960+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L960+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L178:
	ldr	r3, .L960+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L960+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L180:
	ldr	r3, .L960+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L960+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L181:
	ldr	r3, .L960+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L179:
	ldr	r3, .L960+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L960+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
.L182:
	ldr	r3, .L960+380
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L183:
	ldr	r3, .L960+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+400
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	ldr	r3, .L960+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
.L186:
	ldr	r3, .L960+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L960+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
.L188:
	ldr	r3, .L960+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L960+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
.L189:
	ldr	r3, .L960+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L187:
	ldr	r3, .L960+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L960+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L190:
	ldr	r3, .L960+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L960+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L192:
	ldr	r3, .L960+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L960+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L193:
	ldr	r3, .L960+384
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L960+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L191:
	ldr	r3, .L960+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L960+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L194:
	ldr	r3, .L960+400
	ldr	r3, [r3]	@ float
	ldr	r1, .L960+404
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L195:
	ldr	r3, .L960+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L960+416
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L963+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
.L198:
	ldr	r3, .L963
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L963+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
.L200:
	ldr	r3, .L963+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L963
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
.L201:
	ldr	r3, .L963
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L199:
	ldr	r3, .L963+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L963+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
.L202:
	ldr	r3, .L963+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L963+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
.L204:
	ldr	r3, .L963+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L963+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
.L205:
	ldr	r3, .L963+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L203:
	ldr	r3, .L963
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L963+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
.L206:
	ldr	r3, .L963+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L963+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L207:
	ldr	r3, .L963+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L963+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L963+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L963+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
.L210:
	ldr	r3, .L963+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L963+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
.L212:
	ldr	r3, .L963+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L963+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
.L213:
	ldr	r3, .L963+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L211:
	ldr	r3, .L963+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L963+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L214:
	ldr	r3, .L963+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L963+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L216:
	ldr	r3, .L963+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L963+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L217:
	ldr	r3, .L963+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L215:
	ldr	r3, .L963+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L218
	ldr	r3, .L963+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
.L218:
	ldr	r3, .L963+28
	ldr	r3, [r3]	@ float
	ldr	r1, .L963+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L219:
	ldr	r3, .L963+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L963+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L963+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L963+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L223
.L222:
	ldr	r3, .L963+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
	ldr	r3, .L963+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L223
.L224:
	ldr	r3, .L963+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L225
	ldr	r3, .L963+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L223
.L225:
	ldr	r3, .L963+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L223:
	ldr	r3, .L963+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L963+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L963+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L227
.L226:
	ldr	r3, .L963+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L228
	ldr	r3, .L963+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L963+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L227
.L228:
	ldr	r3, .L963+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L963+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L963+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L227
.L229:
	ldr	r3, .L963+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L963+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L963+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
.L230:
	ldr	r3, .L963+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L963+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L227:
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #14
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #15
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #16
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #17
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #18
	beq	.L231
	ldr	r3, .L963+64
	ldr	r3, [r3]
	cmp	r3, #19
	bne	.L4
.L231:
	ldr	r3, .L963+48
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L963+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L963+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L233:
	ldr	r3, .L963+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
	ldr	r3, .L963+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L232:
	ldr	r3, .L963+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L963+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L963+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
	ldr	r3, .L963+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
.L235:
	ldr	r3, .L963+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L963+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
.L237:
	ldr	r3, .L963+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L238
	ldr	r3, .L963+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
.L238:
	ldr	r3, .L963+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L236:
	ldr	r3, .L963+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L963+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
.L239:
	ldr	r3, .L963+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L963+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
.L241:
	ldr	r3, .L963+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
	ldr	r3, .L963+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
.L242:
	ldr	r3, .L963+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L240:
	ldr	r3, .L963+76
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L963+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L963+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L243:
	ldr	r3, .L963+76
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L244
	ldr	r3, .L963+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
	ldr	r3, .L963+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L244:
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	ldr	r2, .L963+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L247
.L4:
	mov	r3, #0
.L247:
	str	r3, [fp, #-24]
	b	.L248
.L964:
	.align	2
.L963:
	.word	t1_l0
	.word	t1_l1
	.word	t1_evt0
	.word	t1_evt1
	.word	t1_x
	.word	t0_l0
	.word	t0_l1
	.word	t0_x
	.word	t0_evt0
	.word	t0_evt1
	.word	controller_l0
	.word	controller_l1
	.word	controller_z
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_evt1
	.word	controller_cnt
	.word	gate_l0
	.word	gate_l1
	.word	gate_y
	.word	gate_evt0
	.word	gate_evt1
	.word	_diverge_delta
	.word	_x_t15_l1
	.word	_x_t15_l0
	.word	_x_t15_evt1
	.word	_x_t15_evt0
	.word	_x_t15_x
	.word	_x_t14_l1
	.word	_x_t14_l0
	.word	_x_t14_evt1
	.word	_x_t14_evt0
	.word	_x_t14_x
	.word	_x_t13_l1
	.word	_x_t13_l0
	.word	_x_t13_evt1
	.word	_x_t13_evt0
	.word	_x_t13_x
	.word	_x_t12_l1
	.word	_x_t12_l0
	.word	_x__diverge_delta
	.word	_x_t12_evt0
	.word	_x_t12_x
	.word	_x_t11_l1
	.word	_x_t11_l0
	.word	_x_t11_evt1
	.word	_x_t11_evt0
	.word	_x_t11_x
	.word	_x_t10_l1
	.word	_x_t10_l0
	.word	_x_t10_evt1
	.word	_x_t10_evt0
	.word	_x_t10_x
	.word	_x_t9_l1
	.word	_x_t9_l0
	.word	_x_t9_evt1
	.word	_x_t9_evt0
	.word	_x_t3_x
	.word	_x_t2_evt1
	.word	_x_t2_l1
	.word	_x_t3_evt0
	.word	_x_t2_l0
	.word	_x_t1_l1
	.word	_x_t2_evt0
	.word	_x_controller_evt2
	.word	_x_t1_l0
	.word	_x_controller_evt1
	.word	_x_t1_evt1
	.word	_x_t1_evt0
	.word	_x_t1_x
	.word	_x_t0_evt1
	.word	_x_t0_l0
	.word	_x_t0_evt0
	.word	_x_controller_cnt
	.word	_x_t12_evt1
	.word	_x_gate_l0
	.word	_x_t2_x
	.word	_x_controller_l0
	.word	_x_controller_l1
	.word	_x_t0_l1
	.word	_x_controller_evt0
	.word	_x_t0_x
	.word	_x_controller_z
	.word	_x_t3_evt1
	.word	_x_t4_x
	.word	_x_t3_l0
	.word	_x_t3_l1
	.word	_x_t4_evt0
	.word	_x_t4_evt1
	.word	_x_t5_x
	.word	_x_t4_l0
	.word	_x_t4_l1
	.word	_x_gate_y
	.word	_x_t5_evt0
	.word	_x_t5_evt1
	.word	_x_t6_x
	.word	_x_gate_evt0
	.word	_x_t5_l0
	.word	_x_gate_evt1
	.word	_x_t5_l1
	.word	_x_t6_evt0
	.word	_x_t6_evt1
	.word	_x_gate_l1
	.word	_x_t7_x
	.word	_x_t6_l0
	.word	_x_delta
	.word	_x_t6_l1
	.word	_x_t7_evt0
	.word	_x_t7_evt1
	.word	_x_t8_x
	.word	_x_t7_l0
	.word	_x_t7_l1
	.word	_x_t8_evt0
	.word	_x_t8_evt1
	.word	_x_t9_x
	.word	_x_t8_l0
	.word	_x_t8_l1
	.word	_x_t17_evt0
	.word	_x_t17_evt1
	.word	_x_t17_l0
	.word	_x_t17_l1
	.word	t17_x
	.word	_x_t17_x
	.word	t17_l0
	.word	t17_l1
	.word	t17_evt0
	.word	t17_evt1
	.word	_x_t16_evt0
	.word	_x_t16_evt1
	.word	1084227584
	.word	t16_l0
	.word	_x_t16_l0
	.word	t16_l1
	.word	_x_t16_l1
	.word	delta
	.word	t16_x
	.word	_x_t16_x
.L872:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+480
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+476
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+472
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+488
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+532
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+524
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+512
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+508
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+544
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+108
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+128
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+148
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+160
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+168
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+188
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+204
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+208
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+220
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+228
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+236
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+468
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+260
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+276
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+280
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+288
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L963+292
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+300
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+304
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+308
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+320
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+324
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+328
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+332
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+336
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+340
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+356
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+360
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+364
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+368
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+376
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+380
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+384
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+388
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+396
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+400
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+404
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+408
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+412
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+416
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+420
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+424
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+428
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+432
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+436
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+440
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+444
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+448
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+452
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L963+456
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+460
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L963+464
	strb	r2, [r3]
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L249
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L250
.L249:
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L250
.L251:
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L250
.L252:
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L250:
	ldr	r3, .L963+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L963+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L255
.L254:
	ldr	r3, .L963+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L963+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L255
.L256:
	ldr	r3, .L963+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L963+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L255
.L257:
	ldr	r3, .L963+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L963+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L255:
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
.L258:
	ldr	r3, .L963+488
	ldr	r3, [r3]	@ float
	ldr	r1, .L963+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L259:
	ldr	r3, .L963+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L261
	ldr	r3, .L963+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L261
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L963+484
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L963+488
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L262
.L261:
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L262:
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L963+488
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L265
.L264:
	ldr	r3, .L963+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L963+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L265:
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L963+484
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L267
	mov	r3, #0
	mov	r4, r3
.L267:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L963+484
	ldr	r3, [r3]	@ float
	ldr	r2, .L963+488
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L268
.L266:
	ldr	r3, .L963+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L963+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L268
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L268:
	ldr	r3, .L963+484
	ldr	r3, [r3]	@ float
	ldr	r2, .L963+488
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
.L269:
	ldr	r3, .L963+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L963+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L271:
	ldr	r3, .L963+476
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L272
	ldr	r3, .L963+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L272
	ldr	r3, .L963+484
	ldr	r3, [r3]	@ float
	ldr	r1, .L963+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L272
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L272
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L272
	ldr	r3, .L963+484
	ldr	r3, [r3]	@ float
	ldr	r2, .L963+488
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L274
.L272:
	ldr	r3, .L963+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L274
	ldr	r3, .L963+496
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L274
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L274
	ldr	r3, .L963+500
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L963+504
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L274:
	ldr	r3, .L963+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L275
	ldr	r3, .L963+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
.L275:
	ldr	r3, .L963+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L277
	ldr	r3, .L963+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
.L277:
	ldr	r3, .L963+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L963+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
.L278:
	ldr	r3, .L963+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L963+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L276:
	ldr	r3, .L963+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L279
	ldr	r3, .L963+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
.L279:
	ldr	r3, .L963+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L963+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
.L281:
	ldr	r3, .L963+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L963+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
.L282:
	ldr	r3, .L963+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L963+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L280:
	ldr	r3, .L963+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L283
	ldr	r3, .L963+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
.L283:
	ldr	r3, .L963+544
	ldr	r3, [r3]	@ float
	ldr	r1, .L963+516
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L284:
	ldr	r3, .L963+520
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L963+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L963+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L963+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L286
	ldr	r3, .L963+536
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L963+540
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L963+544
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L287
.L286:
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L287:
	ldr	r3, .L965+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L965+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L289
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L289
	ldr	r3, .L965+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L290
.L289:
	ldr	r3, .L965+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L290
	ldr	r3, .L965+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L290
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L290:
	ldr	r3, .L965+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L965+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L965+32
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L292
	mov	r3, #0
	mov	r4, r3
.L292:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L965+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
.L291:
	ldr	r3, .L965+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L965+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L293:
	ldr	r3, .L965+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L294
	ldr	r3, .L965+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L294
	ldr	r3, .L965+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L294
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L294
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L296
.L294:
	ldr	r3, .L965+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L965+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L296
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L296:
	ldr	r3, .L965+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L297
	ldr	r3, .L965+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L297
	ldr	r3, .L965+32
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L297
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L297
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L297
	ldr	r3, .L965+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L299
.L297:
	ldr	r3, .L965+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L965+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L965+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L299:
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L300
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
.L300:
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
.L302:
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L303
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
.L303:
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L301:
	ldr	r3, .L965+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L965+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L305
.L304:
	ldr	r3, .L965+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L306
	ldr	r3, .L965+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L305
.L306:
	ldr	r3, .L965+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
	ldr	r3, .L965+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L305
.L307:
	ldr	r3, .L965+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L305:
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L308
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
.L308:
	ldr	r3, .L965+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L309:
	ldr	r3, .L965+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L311
	ldr	r3, .L965+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L311
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L965+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L965+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L312
.L311:
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L312
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L312:
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L314
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L314
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L314
	ldr	r3, .L965+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L315
.L314:
	ldr	r3, .L965+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L965+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L315:
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L316
	ldr	r3, .L965+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L317
	mov	r3, #0
	mov	r4, r3
.L317:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L965+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L318
.L316:
	ldr	r3, .L965+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L965+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L318
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L318:
	ldr	r3, .L965+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L319
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L319
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L319
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L319
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L321
.L319:
	ldr	r3, .L965+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L965+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L321
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L321:
	ldr	r3, .L965+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L322
	ldr	r3, .L965+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L322
	ldr	r3, .L965+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L322
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L322
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L322
	ldr	r3, .L965+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L324
.L322:
	ldr	r3, .L965+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L965+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L965+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L324:
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L325
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
.L325:
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L327
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
.L327:
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L328
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
.L328:
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L326:
	ldr	r3, .L965+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L965+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
.L329:
	ldr	r3, .L965+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L965+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
.L331:
	ldr	r3, .L965+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L332
	ldr	r3, .L965+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
.L332:
	ldr	r3, .L965+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L330:
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L333
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L334
.L333:
	ldr	r3, .L965+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L334:
	ldr	r3, .L965+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L336
	ldr	r3, .L965+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L336
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L965+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L965+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L337
.L336:
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L337:
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L339
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L339
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L339
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L339
	ldr	r3, .L965+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L340
.L339:
	ldr	r3, .L965+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L340
	ldr	r3, .L965+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L340
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L340
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L340:
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L341
	ldr	r3, .L965+104
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L342
	mov	r3, #0
	mov	r4, r3
.L342:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L965+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L343
.L341:
	ldr	r3, .L965+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L965+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L343
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L343:
	ldr	r3, .L965+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
.L344:
	ldr	r3, .L965+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L965+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L346:
	ldr	r3, .L965+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L347
	ldr	r3, .L965+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L347
	ldr	r3, .L965+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L347
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L347
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L347
	ldr	r3, .L965+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L349
.L347:
	ldr	r3, .L965+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L965+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L965
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L965+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L349:
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L350
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
.L350:
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L966
.L967:
	.align	2
.L965:
	.word	delta
	.word	t16_evt0
	.word	t16_evt1
	.word	_x_t16_l0
	.word	_x_t16_l1
	.word	_x_t16_x
	.word	t16_l0
	.word	t16_l1
	.word	t16_x
	.word	_x_t15_l0
	.word	_x_t15_l1
	.word	_x_t15_evt0
	.word	_x_t15_evt1
	.word	_x_t15_x
	.word	t15_l0
	.word	t15_l1
	.word	t15_x
	.word	t15_evt0
	.word	t15_evt1
	.word	_x_t14_l0
	.word	_x_t14_l1
	.word	_x_t14_evt0
	.word	_x_t14_evt1
	.word	_x_t14_x
	.word	t14_l0
	.word	t14_l1
	.word	t14_x
	.word	t14_evt0
	.word	t14_evt1
	.word	_x_t13_evt0
	.word	_x_t13_evt1
	.word	_x_t13_l0
	.word	_x_t13_l1
	.word	t13_x
	.word	_x_t13_x
	.word	t13_l0
	.word	t13_l1
	.word	t13_evt0
	.word	t13_evt1
	.word	_x_t12_evt0
	.word	_x_t12_evt1
	.word	_x_t12_l0
	.word	_x_t12_l1
	.word	t12_x
	.word	_x_t12_x
	.word	t12_l0
	.word	t12_l1
	.word	t12_evt0
	.word	t12_evt1
	.word	_x_t11_evt0
	.word	_x_t11_evt1
	.word	1084227584
	.word	t11_l1
	.word	delta
	.word	_x_t11_l1
	.word	_x_t11_l0
	.word	t11_evt0
	.word	t11_evt1
	.word	t11_x
	.word	_x_t11_x
	.word	t11_l0
.L966:
	cmp	r3, #0
	beq	.L352
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
.L352:
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
.L353:
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L351:
	ldr	r3, .L965+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L354
	ldr	r3, .L965+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L355
.L354:
	ldr	r3, .L965+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L356
	ldr	r3, .L965+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L355
.L356:
	ldr	r3, .L965+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L965+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L355
.L357:
	ldr	r3, .L965+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L355:
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L358
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
.L358:
	ldr	r3, .L965+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L359:
	ldr	r3, .L965+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L361
	ldr	r3, .L965+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L361
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L965+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L965+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L362
.L361:
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L362:
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L364
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L364
	ldr	r3, .L965+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L365
.L364:
	ldr	r3, .L965+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L365
	ldr	r3, .L965+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L365
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L365
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L365:
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L366
	ldr	r3, .L965+132
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L367
	mov	r3, #0
	mov	r4, r3
.L367:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L965+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L368
.L366:
	ldr	r3, .L965+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L965+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L368
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L368:
	ldr	r3, .L965+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L371
.L369:
	ldr	r3, .L965+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L965+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L371
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L371:
	ldr	r3, .L965+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L372
	ldr	r3, .L965+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L372
	ldr	r3, .L965+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L372
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L372
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L372
	ldr	r3, .L965+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L374
.L372:
	ldr	r3, .L965+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L965+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L965+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L374:
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L375
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L376
.L375:
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L376
.L377:
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L378
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L376
.L378:
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L376:
	ldr	r3, .L965+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L965+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L380
.L379:
	ldr	r3, .L965+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L965+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L380
.L381:
	ldr	r3, .L965+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L965+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L380
.L382:
	ldr	r3, .L965+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L380:
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L383
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
.L383:
	ldr	r3, .L965+176
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L384:
	ldr	r3, .L965+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L965+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L965+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L965+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L387
.L386:
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L387
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L387:
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L965+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L390
.L389:
	ldr	r3, .L965+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L965+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L390:
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L391
	ldr	r3, .L965+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L392
	mov	r3, #0
	mov	r4, r3
.L392:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L391
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
	ldr	r3, .L965+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L393
.L391:
	ldr	r3, .L965+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L393
	ldr	r3, .L965+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L393
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L393
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L393:
	ldr	r3, .L965+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L394
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L394
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L394
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L394
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L396
.L394:
	ldr	r3, .L965+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L965+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L396
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L396:
	ldr	r3, .L965+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L397
	ldr	r3, .L965+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L397
	ldr	r3, .L965+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L397
	ldr	r3, .L965+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L399
.L397:
	ldr	r3, .L965+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L965+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L965+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L399:
	ldr	r3, .L965+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L400
	ldr	r3, .L965+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
.L400:
	ldr	r3, .L965+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L402
	ldr	r3, .L965+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
.L402:
	ldr	r3, .L965+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L965+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
.L403:
	ldr	r3, .L965+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L401:
	ldr	r3, .L965+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L404
	ldr	r3, .L965+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L405
.L404:
	ldr	r3, .L965+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L406
	ldr	r3, .L965+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L405
.L406:
	ldr	r3, .L965+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L965+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L405
.L407:
	ldr	r3, .L965+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L405:
	ldr	r3, .L965+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L408
	ldr	r3, .L965+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L409
.L408:
	ldr	r3, .L965+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L965+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L409:
	ldr	r3, .L965+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L411
	ldr	r3, .L965+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L965+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L411
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L965+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L965+236
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L412
.L411:
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L965+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L965+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L412:
	ldr	r3, .L965+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L965+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L965+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L965+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L965+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L415
.L414:
	ldr	r3, .L965+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L415
	ldr	r3, .L965+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L415
	ldr	r3, .L965+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L415
	ldr	r3, .L965+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L965+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L415:
	ldr	r3, .L965+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L965+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L416
	ldr	r3, .L965+232
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L417
	mov	r3, #0
	mov	r4, r3
.L417:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L965+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L965+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L965+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L965+236
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L418
.L416:
	ldr	r3, .L965+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L968
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L418
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L418
	ldr	r3, .L968+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L418:
	ldr	r3, .L968+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L968+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L968+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L968+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L968+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L421
.L419:
	ldr	r3, .L968
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L968+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L421
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L421
	ldr	r3, .L968+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L421:
	ldr	r3, .L968+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L422
	ldr	r3, .L968+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L422
	ldr	r3, .L968+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L422
	ldr	r3, .L968+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L422
	ldr	r3, .L968+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L422
	ldr	r3, .L968+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L424
.L422:
	ldr	r3, .L968+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L424
	ldr	r3, .L968
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L424
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L424
	ldr	r3, .L968+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L424:
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L426
.L425:
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L427
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L426
.L427:
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L426
.L428:
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L426:
	ldr	r3, .L968+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L429
	ldr	r3, .L968+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L430
.L429:
	ldr	r3, .L968+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L968+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L430
.L431:
	ldr	r3, .L968+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
	ldr	r3, .L968+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L430
.L432:
	ldr	r3, .L968+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L430:
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L433
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
.L433:
	ldr	r3, .L968+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L434:
	ldr	r3, .L968+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L968+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L968+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L968+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L437
.L436:
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L437
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L437:
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L439
	ldr	r3, .L968+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L440
.L439:
	ldr	r3, .L968+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L440
	ldr	r3, .L968+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L440
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L440:
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L441
	ldr	r3, .L968+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L442
	mov	r3, #0
	mov	r4, r3
.L442:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L968+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L443
.L441:
	ldr	r3, .L968+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
	ldr	r3, .L968+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L443
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L443
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L443:
	ldr	r3, .L968+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L444
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L444
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L444
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L444
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L446
.L444:
	ldr	r3, .L968+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L446
	ldr	r3, .L968+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L446
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L446
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L446:
	ldr	r3, .L968+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L447
	ldr	r3, .L968+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L447
	ldr	r3, .L968+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L447
	ldr	r3, .L968+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L449
.L447:
	ldr	r3, .L968+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L449
	ldr	r3, .L968+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L449
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L449
	ldr	r3, .L968+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L449:
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L450
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
.L450:
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
.L452:
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L451
.L453:
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L451:
	ldr	r3, .L968+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L454
	ldr	r3, .L968+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L455
.L454:
	ldr	r3, .L968+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L968+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L455
.L456:
	ldr	r3, .L968+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
	ldr	r3, .L968+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L455
.L457:
	ldr	r3, .L968+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L455:
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L459
.L458:
	ldr	r3, .L968+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L459:
	ldr	r3, .L968+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L461
	ldr	r3, .L968+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L461
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L968+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L968+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L462
.L461:
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L462
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L462:
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L464
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L464
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L464
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L464
	ldr	r3, .L968+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L465
.L464:
	ldr	r3, .L968+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L465
	ldr	r3, .L968+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L465
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L465
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L465:
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L968+104
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L467
	mov	r3, #0
	mov	r4, r3
.L467:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L968+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L468
.L466:
	ldr	r3, .L968+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L468
	ldr	r3, .L968+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L468
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L468
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L468:
	ldr	r3, .L968+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L471
.L469:
	ldr	r3, .L968+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L968+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L471
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L471
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L471:
	ldr	r3, .L968+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L472
	ldr	r3, .L968+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L472
	ldr	r3, .L968+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L472
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L472
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L472
	ldr	r3, .L968+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L474
.L472:
	ldr	r3, .L968+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L474
	ldr	r3, .L968+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L474
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L474
	ldr	r3, .L968+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L474:
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L475
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
.L475:
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L477
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
.L477:
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L478
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
.L478:
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L476:
	ldr	r3, .L968+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L479
	ldr	r3, .L968+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
.L479:
	ldr	r3, .L968+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L968+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
.L481:
	ldr	r3, .L968+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L482
	ldr	r3, .L968+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
.L482:
	ldr	r3, .L968+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L480:
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L483
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
.L483:
	ldr	r3, .L968+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L484:
	ldr	r3, .L968+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L968+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L968+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L968+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	b	.L969
.L970:
	.align	2
.L968:
	.word	t11_l1
	.word	delta
	.word	t11_evt0
	.word	t11_evt1
	.word	t11_x
	.word	_x_t11_x
	.word	_x_t11_l0
	.word	_x_t11_l1
	.word	t11_l0
	.word	_x_t10_l0
	.word	_x_t10_l1
	.word	_x_t10_evt0
	.word	_x_t10_evt1
	.word	_x_t10_x
	.word	t10_l0
	.word	t10_l1
	.word	t10_x
	.word	t10_evt0
	.word	t10_evt1
	.word	_x_t9_l0
	.word	_x_t9_l1
	.word	_x_t9_evt0
	.word	_x_t9_evt1
	.word	_x_t9_x
	.word	t9_l0
	.word	t9_l1
	.word	t9_x
	.word	t9_evt0
	.word	t9_evt1
	.word	_x_t8_evt0
	.word	_x_t8_evt1
	.word	_x_t8_l0
	.word	_x_t8_l1
	.word	t8_x
	.word	_x_t8_x
	.word	t8_l0
	.word	t8_l1
	.word	t8_evt0
	.word	t8_evt1
	.word	_x_t7_evt0
	.word	_x_t7_evt1
	.word	_x_t7_l0
	.word	_x_t7_l1
	.word	t7_x
	.word	_x_t7_x
	.word	t7_l0
	.word	t7_l1
	.word	t7_evt0
	.word	t7_evt1
	.word	_x_t6_evt0
	.word	_x_t6_evt1
	.word	delta
	.word	_x_t6_l0
	.word	_x_t6_l1
	.word	1084227584
	.word	t6_evt1
	.word	t6_evt0
	.word	t6_x
	.word	_x_t6_x
	.word	t6_l0
	.word	t6_l1
.L969:
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L968+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L487
.L486:
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L487
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L487:
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L968+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L490
.L489:
	ldr	r3, .L968+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L490
	ldr	r3, .L968+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L490
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L490:
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L968+132
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L492
	mov	r3, #0
	mov	r4, r3
.L492:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L968+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L493
.L491:
	ldr	r3, .L968+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L968+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L493
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L493
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L493:
	ldr	r3, .L968+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L496
.L494:
	ldr	r3, .L968+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L968+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L496
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L496:
	ldr	r3, .L968+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L497
	ldr	r3, .L968+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L497
	ldr	r3, .L968+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L497
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L497
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L497
	ldr	r3, .L968+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L499
.L497:
	ldr	r3, .L968+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L968+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L968+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L499:
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L500
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L501
.L500:
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L501
.L502:
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L501
.L503:
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L501:
	ldr	r3, .L968+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L504
	ldr	r3, .L968+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L505
.L504:
	ldr	r3, .L968+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L968+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L505
.L506:
	ldr	r3, .L968+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
	ldr	r3, .L968+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L505
.L507:
	ldr	r3, .L968+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L505:
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L508
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
.L508:
	ldr	r3, .L968+176
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L509:
	ldr	r3, .L968+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L511
	ldr	r3, .L968+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L511
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L968+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L968+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L512
.L511:
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L512
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L512:
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L514
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L514
	ldr	r3, .L968+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L515
.L514:
	ldr	r3, .L968+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L515
	ldr	r3, .L968+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L515
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L515
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L515:
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L968+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L517
	mov	r3, #0
	mov	r4, r3
.L517:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L968+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L518
.L516:
	ldr	r3, .L968+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L968+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L518
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L518:
	ldr	r3, .L968+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L521
.L519:
	ldr	r3, .L968+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L968+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L521
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L521
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L521:
	ldr	r3, .L968+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L968+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L968+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L968+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L524
.L522:
	ldr	r3, .L968+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L968+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L968+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L524:
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L525
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
.L525:
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
.L527:
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L526
.L528:
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L526:
	ldr	r3, .L968+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L529
	ldr	r3, .L968+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L530
.L529:
	ldr	r3, .L968+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L968+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L530
.L531:
	ldr	r3, .L968+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L532
	ldr	r3, .L968+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L530
.L532:
	ldr	r3, .L968+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L530:
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L533
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L534
.L533:
	ldr	r3, .L968+232
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L534:
	ldr	r3, .L968+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L968+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L968+228
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L968+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L537
.L536:
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L968+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L537
	ldr	r3, .L968+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L537:
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L968+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L968+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L968+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L540
.L539:
	ldr	r3, .L968+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L540
	ldr	r3, .L968+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L540
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L540
	ldr	r3, .L968+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L540:
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L541
	ldr	r3, .L968+228
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L542
	mov	r3, #0
	mov	r4, r3
.L542:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L968+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L968+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L968+228
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+232
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L543
.L541:
	ldr	r3, .L968+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L543
	ldr	r3, .L968+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L543
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L543
	ldr	r3, .L968+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L543:
	ldr	r3, .L968+228
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+232
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L968+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L968+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L546
.L544:
	ldr	r3, .L968+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L968+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L546
	ldr	r3, .L968+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L968+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L968+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L546:
	ldr	r3, .L968+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L547
	ldr	r3, .L968+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L547
	ldr	r3, .L968+228
	ldr	r3, [r3]	@ float
	ldr	r1, .L968+216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L547
	ldr	r3, .L968+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L547
	ldr	r3, .L968+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L547
	ldr	r3, .L968+228
	ldr	r3, [r3]	@ float
	ldr	r2, .L968+232
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L549
.L547:
	ldr	r3, .L968+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L968+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L971+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L549:
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L550
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L551
.L550:
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L551
.L552:
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L553
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L551
.L553:
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L551:
	ldr	r3, .L971+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L554
	ldr	r3, .L971+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
.L554:
	ldr	r3, .L971+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L556
	ldr	r3, .L971+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
.L556:
	ldr	r3, .L971+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L971+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
.L557:
	ldr	r3, .L971+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L555:
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L558
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L559
.L558:
	ldr	r3, .L971+28
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L559:
	ldr	r3, .L971+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L971+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L971+40
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L971+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L562
.L561:
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L562
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L562:
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L564
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L564
	ldr	r3, .L971+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L565
.L564:
	ldr	r3, .L971+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L565
	ldr	r3, .L971+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L565
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L565
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L565:
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L971+40
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L567
	mov	r3, #0
	mov	r4, r3
.L567:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L971+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L568
.L566:
	ldr	r3, .L971+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L971+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L568:
	ldr	r3, .L971+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L571
.L569:
	ldr	r3, .L971+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L971+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L571
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L571
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L571:
	ldr	r3, .L971+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L572
	ldr	r3, .L971+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L572
	ldr	r3, .L971+40
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L572
	ldr	r3, .L971+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L574
.L572:
	ldr	r3, .L971+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L971+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L971+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L574:
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L575
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L576
.L575:
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L576
.L577:
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L576
.L578:
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L576:
	ldr	r3, .L971+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L971+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L580
.L579:
	ldr	r3, .L971+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L971+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L580
.L581:
	ldr	r3, .L971+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L971+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L580
.L582:
	ldr	r3, .L971+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L580:
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L583
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
.L583:
	ldr	r3, .L971+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L584:
	ldr	r3, .L971+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L586
	ldr	r3, .L971+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L586
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L971+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L971+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L587
.L586:
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L587
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L587:
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L589
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L589
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L589
	ldr	r3, .L971+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L590
.L589:
	ldr	r3, .L971+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L971+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L590:
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L591
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L591
	ldr	r3, .L971+80
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L592
	mov	r3, #0
	mov	r4, r3
.L592:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L591
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L591
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L591
	ldr	r3, .L971+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L593
.L591:
	ldr	r3, .L971+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L593
	ldr	r3, .L971+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L593
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L593:
	ldr	r3, .L971+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L596
.L594:
	ldr	r3, .L971+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L596
	ldr	r3, .L971+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L596
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L596
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L596:
	ldr	r3, .L971+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L597
	ldr	r3, .L971+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L597
	ldr	r3, .L971+80
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L597
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L597
	ldr	r3, .L971+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L599
.L597:
	ldr	r3, .L971+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L971+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L971+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L599:
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L600
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
.L600:
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
.L602:
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L603
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
.L603:
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L601:
	ldr	r3, .L971+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L604
	ldr	r3, .L971+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L605
.L604:
	ldr	r3, .L971+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L606
	ldr	r3, .L971+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L605
.L606:
	ldr	r3, .L971+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L971+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L605
.L607:
	ldr	r3, .L971+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L605:
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L608
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L609
.L608:
	ldr	r3, .L971+112
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L609:
	ldr	r3, .L971+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L611
	ldr	r3, .L971+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L611
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L971+108
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L971+112
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L612
.L611:
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L612:
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L614
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L614
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L614
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L614
	ldr	r3, .L971+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L615
.L614:
	ldr	r3, .L971+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L971+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L971
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L615:
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L616
	ldr	r3, .L971+108
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L617
	mov	r3, #0
	mov	r4, r3
	b	.L972
.L973:
	.align	2
.L971:
	.word	delta
	.word	t6_evt0
	.word	t6_evt1
	.word	_x_t5_l0
	.word	_x_t5_l1
	.word	_x_t5_evt0
	.word	_x_t5_evt1
	.word	_x_t5_x
	.word	t5_l0
	.word	t5_l1
	.word	t5_x
	.word	t5_evt0
	.word	t5_evt1
	.word	_x_t4_l0
	.word	_x_t4_l1
	.word	_x_t4_evt0
	.word	_x_t4_evt1
	.word	_x_t4_x
	.word	t4_l0
	.word	t4_l1
	.word	t4_x
	.word	t4_evt0
	.word	t4_evt1
	.word	_x_t3_evt0
	.word	_x_t3_evt1
	.word	_x_t3_l0
	.word	_x_t3_l1
	.word	t3_x
	.word	_x_t3_x
	.word	t3_l0
	.word	t3_l1
	.word	t3_evt0
	.word	t3_evt1
	.word	_x_t2_evt0
	.word	_x_t2_evt1
	.word	_x_t2_l0
	.word	_x_t2_l1
	.word	t2_x
	.word	_x_t2_x
	.word	t2_l0
	.word	t2_l1
	.word	t2_evt0
	.word	t2_evt1
	.word	_x_t1_evt0
	.word	_x_t1_evt1
	.word	_x_t1_l0
	.word	_x_t1_l1
	.word	t1_x
	.word	_x_t1_x
	.word	t1_l0
	.word	t1_l1
	.word	delta
	.word	t1_evt0
	.word	t1_evt1
	.word	_x_t0_evt0
	.word	_x_t0_evt1
	.word	_x_t0_l1
	.word	_x_t0_x
	.word	1084227584
	.word	t0_l0
	.word	_x_t0_l0
.L972:
.L617:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L971+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L618
.L616:
	ldr	r3, .L971+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L971+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L618
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L618:
	ldr	r3, .L971+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L619
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L619
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L619
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L619
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
.L619:
	ldr	r3, .L971+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L971+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L621:
	ldr	r3, .L971+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L622
	ldr	r3, .L971+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L622
	ldr	r3, .L971+108
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L622
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L622
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L622
	ldr	r3, .L971+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L624
.L622:
	ldr	r3, .L971+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L971+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L971+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L624:
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L625
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
.L625:
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L627
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
.L627:
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
.L628:
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L626:
	ldr	r3, .L971+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L629
	ldr	r3, .L971+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L629:
	ldr	r3, .L971+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L971+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L631:
	ldr	r3, .L971+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L971+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L632:
	ldr	r3, .L971+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L630:
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L633
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L634
.L633:
	ldr	r3, .L971+152
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L634:
	ldr	r3, .L971+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L636
	ldr	r3, .L971+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L636
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L971+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L971+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L637
.L636:
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L637
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L637:
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L639
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L639
	ldr	r3, .L971+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L640
.L639:
	ldr	r3, .L971+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L640
	ldr	r3, .L971+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L640
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L640:
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L641
	ldr	r3, .L971+148
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L642
	mov	r3, #0
	mov	r4, r3
.L642:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L971+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L643
.L641:
	ldr	r3, .L971+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L971+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L643:
	ldr	r3, .L971+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L644
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L644
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L644
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L644
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L646
.L644:
	ldr	r3, .L971+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L646
	ldr	r3, .L971+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L646
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L646
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L646:
	ldr	r3, .L971+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L647
	ldr	r3, .L971+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L647
	ldr	r3, .L971+148
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L647
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L647
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L647
	ldr	r3, .L971+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L649
.L647:
	ldr	r3, .L971+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L971+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L971+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L649:
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L650
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
.L650:
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
.L652:
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L653
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
.L653:
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L651:
	ldr	r3, .L971+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L971+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L655
.L654:
	ldr	r3, .L971+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L971+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L655
.L656:
	ldr	r3, .L971+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L657
	ldr	r3, .L971+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L655
.L657:
	ldr	r3, .L971+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L655:
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L658
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L659
.L658:
	ldr	r3, .L971+192
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L659:
	ldr	r3, .L971+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L971+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L971+188
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L971+192
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L662
.L661:
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L662
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L662:
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L664
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L664
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L971+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L665
.L664:
	ldr	r3, .L971+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L665
	ldr	r3, .L971+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L665
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L665
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L665:
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L666
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L666
	ldr	r3, .L971+188
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L667
	mov	r3, #0
	mov	r4, r3
.L667:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L666
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L666
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L666
	ldr	r3, .L971+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+192
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L668
.L666:
	ldr	r3, .L971+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L668
	ldr	r3, .L971+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L668
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L668
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L668:
	ldr	r3, .L971+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+192
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L669
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
.L669:
	ldr	r3, .L971+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L971+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L671:
	ldr	r3, .L971+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L672
	ldr	r3, .L971+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L672
	ldr	r3, .L971+188
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L672
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L672
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L672
	ldr	r3, .L971+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L971+192
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L674
.L672:
	ldr	r3, .L971+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L674
	ldr	r3, .L971+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L674
	ldr	r3, .L971+204
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L674
	ldr	r3, .L971+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L971+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L674:
	ldr	r3, .L971+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L675
	ldr	r3, .L971+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
.L675:
	ldr	r3, .L971+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L677
	ldr	r3, .L971+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
.L677:
	ldr	r3, .L971+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L971+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
.L678:
	ldr	r3, .L971+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L676:
	ldr	r3, .L971+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L679
	ldr	r3, .L971+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L680
.L679:
	ldr	r3, .L971+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L971+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L680
.L681:
	ldr	r3, .L971+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L682
	ldr	r3, .L971+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L680
.L682:
	ldr	r3, .L971+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L971+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L680:
	ldr	r3, .L971+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L683
	ldr	r3, .L971+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
.L683:
	ldr	r3, .L971+228
	ldr	r3, [r3]	@ float
	ldr	r1, .L971+232
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L684:
	ldr	r3, .L971+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L971+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L974
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L974+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L974+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L974+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L687
.L686:
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L687:
	ldr	r3, .L974+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L974+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L974+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L690
.L689:
	ldr	r3, .L974+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L690
	ldr	r3, .L974
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L690
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L690:
	ldr	r3, .L974+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L691
	ldr	r3, .L974+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L691
	ldr	r3, .L974+12
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L692
	mov	r3, #0
	mov	r4, r3
.L692:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L691
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L691
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L691
	ldr	r3, .L974+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L974+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L693
.L691:
	ldr	r3, .L974+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L974
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L693:
	ldr	r3, .L974+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L974+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L974+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L974+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L696
.L694:
	ldr	r3, .L974
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L696
	ldr	r3, .L974+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L696
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L696
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L696:
	ldr	r3, .L974+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L697
	ldr	r3, .L974+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L697
	ldr	r3, .L974+12
	ldr	r3, [r3]	@ float
	ldr	r1, .L974+28
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L697
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L697
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L697
	ldr	r3, .L974+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L974+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L699
.L697:
	ldr	r3, .L974+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L699
	ldr	r3, .L974
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L699
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L699
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L699:
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L701
.L700:
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L702
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L701
.L702:
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L703
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L701
.L703:
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L701:
	ldr	r3, .L974+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L704
	ldr	r3, .L974+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L704
	ldr	r3, .L974+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L705
.L704:
	ldr	r3, .L974+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L706
	ldr	r3, .L974+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L974+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L705
.L706:
	ldr	r3, .L974+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L707
	ldr	r3, .L974+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
	ldr	r3, .L974+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L705
.L707:
	ldr	r3, .L974+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L708
	ldr	r3, .L974+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L708
	ldr	r3, .L974+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L705
.L708:
	ldr	r3, .L974+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L974+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L705:
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #14
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #15
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #16
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #17
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #18
	beq	.L709
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #19
	bne	.L253
.L709:
	ldr	r3, .L974+44
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L710
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L711:
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L710
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L710:
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L974+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L974+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L974+48
	ldr	r2, [r3]
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L714
.L712:
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L714:
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L716
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L716
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L716
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L716
	ldr	r3, .L974+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L717
.L716:
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L717
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L717
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L717:
	ldr	r3, .L974+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L974+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L718
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L721
.L720:
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L718
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L721
.L718:
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L721
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L721
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L721
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L721:
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L974+48
	ldr	r2, [r3]
	ldr	r3, .L974+52
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L723
.L722:
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L724
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L724
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L724
	ldr	r3, .L974+48
	ldr	r2, [r3]
	ldr	r3, .L974+52
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L723
.L724:
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L723
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L723
.L725:
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L723
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L723
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L723
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L723:
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L726
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L974+48
	ldr	r2, [r3]
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L726
	ldr	r3, .L974+56
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L727
.L726:
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L727
.L728:
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L727
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L727:
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L730
.L729:
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L730
.L731:
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L730
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L730
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L730
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L730:
	ldr	r3, .L974+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L974+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L732
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L734
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L734
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L734
	ldr	r3, .L974+48
	ldr	r2, [r3]
	ldr	r3, .L974+52
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L735
.L734:
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L732
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L732
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L732
	ldr	r3, .L974+48
	ldr	r2, [r3]
	ldr	r3, .L974+52
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L732
	ldr	r3, .L974+48
	ldr	r3, [r3]
	cmp	r3, #1
	bgt	.L735
.L732:
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L736
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L736
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L735
.L736:
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L735
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L735:
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L737
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L737
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L737
	ldr	r3, .L974+48
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L737
	ldr	r3, .L974+52
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L737
	ldr	r3, .L974+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L738
.L737:
	ldr	r3, .L974+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L738
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L738
.L739:
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L738
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L738
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L738
	b	.L975
.L976:
	.align	2
.L974:
	.word	t0_l1
	.word	_x_t0_l1
	.word	delta
	.word	t0_x
	.word	_x_t0_x
	.word	_x_t0_l0
	.word	t0_l0
	.word	1084227584
	.word	_x_controller_evt2
	.word	_x_controller_evt0
	.word	_x_controller_evt1
	.word	_x_controller_z
	.word	controller_cnt
	.word	_x_controller_cnt
	.word	controller_z
	.word	_x_controller_l1
	.word	_x_controller_l0
	.word	controller_l0
	.word	controller_l1
	.word	_x_gate_evt0
	.word	_x_gate_evt1
	.word	_x_gate_y
	.word	_x_gate_l0
	.word	_x_gate_l1
	.word	gate_y
	.word	gate_l0
	.word	gate_l1
	.word	_x_delta
	.word	t0_evt0
	.word	t0_evt1
	.word	t1_evt0
	.word	t1_evt1
	.word	t2_evt0
	.word	t2_evt1
	.word	t3_evt0
	.word	t3_evt1
	.word	t4_evt0
	.word	t4_evt1
	.word	t5_evt0
	.word	t5_evt1
	.word	t6_evt0
	.word	t6_evt1
	.word	t7_evt0
	.word	t7_evt1
	.word	t8_evt0
	.word	t8_evt1
	.word	t9_evt0
	.word	t9_evt1
	.word	t10_evt0
	.word	t10_evt1
	.word	t11_evt0
	.word	t11_evt1
	.word	t12_evt0
	.word	t12_evt1
	.word	t13_evt0
	.word	t13_evt1
	.word	t14_evt0
	.word	t14_evt1
	.word	t15_evt0
	.word	t15_evt1
	.word	t16_evt0
	.word	t16_evt1
	.word	t17_evt0
	.word	t17_evt1
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_evt1
	.word	delta
	.word	gate_evt1
	.word	gate_evt0
.L975:
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L738:
	ldr	r3, .L974+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L974+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L740
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L743
.L742:
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L740
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L743
.L740:
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L743
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L743
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L743
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L743:
	ldr	r3, .L974+48
	ldr	r2, [r3]
	ldr	r3, .L974+52
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	bne	.L744
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L744
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L744
	ldr	r3, .L974+56
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L745
.L744:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L746
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L746
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L745
.L746:
	ldr	r3, .L974+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L974+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L745
	ldr	r3, .L974+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L974+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L745:
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L747
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L748
.L747:
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L748
.L749:
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L748
.L750:
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L748:
	ldr	r3, .L974+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L751
	ldr	r3, .L974+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L752
.L751:
	ldr	r3, .L974+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L753
	ldr	r3, .L974+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L752
.L753:
	ldr	r3, .L974+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L754
	ldr	r3, .L974+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L752
.L754:
	ldr	r3, .L974+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L974+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L752:
	ldr	r3, .L974+84
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L755:
	ldr	r3, .L974+84
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L756
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L756
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L756:
	ldr	r3, .L974+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L757
	ldr	r3, .L974+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L757
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L974+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L974+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L758
.L757:
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L759
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L759:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L758:
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L761
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L761
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L761
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L761
	ldr	r3, .L974+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L762
.L761:
	ldr	r3, .L974+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L762
	ldr	r3, .L974+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L762
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L762
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L762:
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L763
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L763
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L763
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L763
	ldr	r3, .L974+96
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L763
	ldr	r3, .L974+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L974+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L765
.L763:
	ldr	r3, .L974+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L765
	ldr	r3, .L974+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L765
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L765
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L765:
	ldr	r3, .L974+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L768
.L766:
	ldr	r3, .L974+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L768
	ldr	r3, .L974+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L768
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L768
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L768:
	ldr	r3, .L974+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L974+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L769
	ldr	r3, .L974+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L769
	ldr	r3, .L974+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L769
	ldr	r3, .L974+96
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L769
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L769
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L769
	ldr	r3, .L974+96
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L772
.L769:
	ldr	r3, .L974+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L974+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L772:
	ldr	r3, .L974+108
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L774
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
.L774:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L974+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L775:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L776
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L777
.L776:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L974+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L777:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L778
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L779
.L778:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L779
	ldr	r3, .L974+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L779:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L781
.L780:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L781
	ldr	r3, .L974+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L781:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L782
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L783
.L782:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L974+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L783:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L784
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L785
.L784:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L785
	ldr	r3, .L974+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L785:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L787
.L786:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L787
	ldr	r3, .L974+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L787:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L789
.L788:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L789
	ldr	r3, .L974+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L789:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L790
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
.L790:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L791
	ldr	r3, .L974+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L791:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L792
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L793
.L792:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L974+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L793:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L794
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L795
.L794:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L795
	ldr	r3, .L974+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L795:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L796
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L797
.L796:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L797
	ldr	r3, .L974+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L797:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L798
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L799
.L798:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L799
	ldr	r3, .L974+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L799:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L800
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L801
.L800:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L801
	ldr	r3, .L974+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L801:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L802
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L803
.L802:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L974+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L803:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L804
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L805
.L804:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L974+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L805:
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L806
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L807
.L806:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L974+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L807:
	ldr	r3, .L974+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L808
	ldr	r3, .L974+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L809
.L808:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L809
	ldr	r3, .L974+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L974+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
.L809:
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
	mov	r3, #1
	b	.L811
.L810:
	mov	r3, #0
.L811:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L974+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L812
	ldr	r3, .L974+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L812
	ldr	r3, .L974+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L812
	mov	r3, #1
	b	.L813
.L812:
	mov	r3, #0
.L813:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L814
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L253
.L814:
	ldr	r3, .L974+268
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L974+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L817
	ldr	r3, .L974+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L817
	mov	r3, #1
	b	.L818
.L817:
	mov	r3, #0
.L818:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L977
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L977+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L977+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	mov	r3, #1
	b	.L820
.L819:
	mov	r3, #0
.L820:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L253
.L816:
	ldr	r3, .L977+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L977
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L822
	ldr	r3, .L977+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L822
	ldr	r3, .L977+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L822
	mov	r3, #1
	b	.L823
.L822:
	mov	r3, #0
.L823:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L977+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L824
	ldr	r3, .L977+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L824:
	ldr	r3, .L977+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L977+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L826:
	ldr	r3, .L977+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L827
	ldr	r3, .L977+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L827:
	ldr	r3, .L977+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L828
	ldr	r3, .L977+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L828:
	ldr	r3, .L977+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L829
	ldr	r3, .L977+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L829:
	ldr	r3, .L977+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L977+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L830:
	ldr	r3, .L977+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L831
	ldr	r3, .L977+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L831:
	ldr	r3, .L977+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L832
	ldr	r3, .L977+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L832:
	ldr	r3, .L977+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L977+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L833:
	ldr	r3, .L977+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L834
	ldr	r3, .L977+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L834:
	ldr	r3, .L977+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L835
	ldr	r3, .L977+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L835:
	ldr	r3, .L977+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L836
	ldr	r3, .L977+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L836:
	ldr	r3, .L977+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L837
	ldr	r3, .L977+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L837:
	ldr	r3, .L977+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L977+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L838:
	ldr	r3, .L977+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L839
	ldr	r3, .L977+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L839:
	ldr	r3, .L977+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L840
	ldr	r3, .L977+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L840:
	ldr	r3, .L977+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L841
	ldr	r3, .L977+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
.L841:
	ldr	r3, .L977+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L842
	ldr	r3, .L977+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L842
.L825:
	mov	r3, #1
	b	.L843
.L842:
	mov	r3, #0
.L843:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L253
.L821:
	ldr	r3, .L977+12
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L844
	ldr	r3, .L977
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L845
	ldr	r3, .L977+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L845
	ldr	r3, .L977+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L845
	mov	r3, #1
	b	.L846
.L845:
	mov	r3, #0
.L846:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L977+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L847
	ldr	r3, .L977+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L847:
	ldr	r3, .L977+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L977+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L849:
	ldr	r3, .L977+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L850
	ldr	r3, .L977+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L850:
	ldr	r3, .L977+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L851
	ldr	r3, .L977+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L851:
	ldr	r3, .L977+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L977+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L852:
	ldr	r3, .L977+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L853
	ldr	r3, .L977+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L853:
	ldr	r3, .L977+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L977+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L854:
	ldr	r3, .L977+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L855
	ldr	r3, .L977+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L855:
	ldr	r3, .L977+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L856
	ldr	r3, .L977+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L856:
	ldr	r3, .L977+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L857
	ldr	r3, .L977+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L857:
	ldr	r3, .L977+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L858
	ldr	r3, .L977+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L858:
	ldr	r3, .L977+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L977+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L859:
	ldr	r3, .L977+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L860
	ldr	r3, .L977+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L860:
	ldr	r3, .L977+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L861
	ldr	r3, .L977+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L861:
	ldr	r3, .L977+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L862
	ldr	r3, .L977+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L862:
	ldr	r3, .L977+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L863
	ldr	r3, .L977+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L863:
	ldr	r3, .L977+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L864
	ldr	r3, .L977+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
.L864:
	ldr	r3, .L977+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L977+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L865
.L848:
	mov	r3, #1
	b	.L866
.L865:
	mov	r3, #0
.L866:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L253
.L844:
	ldr	r3, .L977+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L867
	ldr	r3, .L977+164
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L868
	mov	r3, #0
	mov	r4, r3
.L868:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L253
.L867:
	ldr	r3, .L977+164
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L869
	ldr	r3, .L977+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L977+164
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L977+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
.L869:
	mov	r3, #1
	b	.L871
.L253:
	mov	r3, #0
.L871:
	str	r3, [fp, #-24]
	ldr	r3, .L977+168
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+172
	strb	r2, [r3]
	ldr	r3, .L977+176
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+180
	strb	r2, [r3]
	ldr	r3, .L977+184
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+20
	strb	r2, [r3]
	ldr	r3, .L977+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+192
	str	r3, [r2]	@ float
	ldr	r3, .L977+196
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+200
	strb	r2, [r3]
	ldr	r3, .L977+204
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+208
	strb	r2, [r3]
	ldr	r3, .L977+212
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+28
	strb	r2, [r3]
	ldr	r3, .L977+216
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+24
	strb	r2, [r3]
	ldr	r3, .L977+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+224
	str	r3, [r2]	@ float
	ldr	r3, .L977+228
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+232
	strb	r2, [r3]
	ldr	r3, .L977+236
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+240
	strb	r2, [r3]
	ldr	r3, .L977+244
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+36
	strb	r2, [r3]
	ldr	r3, .L977+248
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+32
	strb	r2, [r3]
	ldr	r3, .L977+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+256
	str	r3, [r2]	@ float
	ldr	r3, .L977+260
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+264
	strb	r2, [r3]
	ldr	r3, .L977+268
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+272
	strb	r2, [r3]
	ldr	r3, .L977+276
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+44
	strb	r2, [r3]
	ldr	r3, .L977+280
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+40
	strb	r2, [r3]
	ldr	r3, .L977+284
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+288
	str	r3, [r2]	@ float
	ldr	r3, .L977+292
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+296
	strb	r2, [r3]
	ldr	r3, .L977+300
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+304
	strb	r2, [r3]
	ldr	r3, .L977+308
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+52
	strb	r2, [r3]
	ldr	r3, .L977+312
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+48
	strb	r2, [r3]
	ldr	r3, .L977+316
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+320
	str	r3, [r2]	@ float
	ldr	r3, .L977+324
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+328
	strb	r2, [r3]
	ldr	r3, .L977+332
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+336
	strb	r2, [r3]
	ldr	r3, .L977+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+164
	str	r3, [r2]	@ float
	ldr	r3, .L977+340
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+56
	strb	r2, [r3]
	ldr	r3, .L977+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+348
	str	r3, [r2]	@ float
	ldr	r3, .L977+352
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+356
	strb	r2, [r3]
	ldr	r3, .L977+360
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+364
	strb	r2, [r3]
	ldr	r3, .L977+368
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+68
	strb	r2, [r3]
	ldr	r3, .L977+372
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+64
	strb	r2, [r3]
	ldr	r3, .L977+376
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+380
	str	r3, [r2]	@ float
	ldr	r3, .L977+384
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+388
	strb	r2, [r3]
	ldr	r3, .L977+392
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+396
	strb	r2, [r3]
	ldr	r3, .L977+400
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+76
	strb	r2, [r3]
	ldr	r3, .L977+404
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+72
	strb	r2, [r3]
	ldr	r3, .L977+408
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+412
	str	r3, [r2]	@ float
	ldr	r3, .L977+416
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+420
	strb	r2, [r3]
	ldr	r3, .L977+424
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+428
	strb	r2, [r3]
	ldr	r3, .L977+432
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+84
	strb	r2, [r3]
	ldr	r3, .L977+436
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+80
	strb	r2, [r3]
	ldr	r3, .L977+440
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+444
	str	r3, [r2]	@ float
	ldr	r3, .L977+448
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+140
	strb	r2, [r3]
	ldr	r3, .L977+452
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+456
	strb	r2, [r3]
	ldr	r3, .L977+460
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+128
	strb	r2, [r3]
	ldr	r3, .L977+464
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+468
	strb	r2, [r3]
	ldr	r3, .L977+472
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+476
	strb	r2, [r3]
	ldr	r3, .L977+480
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+136
	strb	r2, [r3]
	ldr	r3, .L977+484
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+16
	strb	r2, [r3]
	ldr	r3, .L977+488
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977
	strb	r2, [r3]
	ldr	r3, .L977+492
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+496
	strb	r2, [r3]
	ldr	r3, .L977+500
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+8
	strb	r2, [r3]
	ldr	r3, .L977+504
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+156
	strb	r2, [r3]
	ldr	r3, .L977+508
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+152
	strb	r2, [r3]
	ldr	r3, .L977+512
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+516
	str	r3, [r2]	@ float
	ldr	r3, .L977+520
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+148
	strb	r2, [r3]
	ldr	r3, .L977+524
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+528
	strb	r2, [r3]
	ldr	r3, .L977+532
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+144
	strb	r2, [r3]
	ldr	r3, .L977+536
	ldr	r3, [r3]
	ldr	r2, .L977+540
	str	r3, [r2]
	ldr	r3, .L977+544
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+60
	strb	r2, [r3]
	ldr	r3, .L977+548
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+552
	strb	r2, [r3]
	ldr	r3, .L977+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+560
	str	r3, [r2]	@ float
	ldr	r3, .L977+564
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+568
	strb	r2, [r3]
	ldr	r3, .L977+572
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+576
	strb	r2, [r3]
	ldr	r3, .L977+580
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+584
	strb	r2, [r3]
	ldr	r3, .L977+588
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+4
	strb	r2, [r3]
	ldr	r3, .L977+592
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+596
	str	r3, [r2]	@ float
	ldr	r3, .L977+600
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+604
	str	r3, [r2]	@ float
	ldr	r3, .L977+608
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+132
	strb	r2, [r3]
	ldr	r3, .L977+612
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+616
	str	r3, [r2]	@ float
	ldr	r3, .L977+620
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+624
	strb	r2, [r3]
	ldr	r3, .L977+628
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+632
	strb	r2, [r3]
	ldr	r3, .L977+636
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+120
	strb	r2, [r3]
	ldr	r3, .L977+640
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+124
	strb	r2, [r3]
	ldr	r3, .L977+644
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+648
	str	r3, [r2]	@ float
	ldr	r3, .L977+652
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+656
	strb	r2, [r3]
	ldr	r3, .L977+660
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+664
	strb	r2, [r3]
	ldr	r3, .L977+668
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+672
	str	r3, [r2]	@ float
	ldr	r3, .L977+676
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+112
	strb	r2, [r3]
	ldr	r3, .L977+680
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+116
	strb	r2, [r3]
	ldr	r3, .L977+684
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+688
	str	r3, [r2]	@ float
	ldr	r3, .L977+692
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+696
	strb	r2, [r3]
	ldr	r3, .L977+700
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+704
	strb	r2, [r3]
	ldr	r3, .L977+708
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+712
	strb	r2, [r3]
	ldr	r3, .L977+716
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+720
	strb	r2, [r3]
	ldr	r3, .L977+724
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+104
	strb	r2, [r3]
	ldr	r3, .L977+728
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+108
	strb	r2, [r3]
	ldr	r3, .L977+732
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+736
	strb	r2, [r3]
	ldr	r3, .L977+740
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+744
	str	r3, [r2]	@ float
	ldr	r3, .L977+748
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+752
	strb	r2, [r3]
	ldr	r3, .L977+756
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+12
	str	r3, [r2]	@ float
	ldr	r3, .L977+760
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+764
	strb	r2, [r3]
	ldr	r3, .L977+768
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+96
	strb	r2, [r3]
	ldr	r3, .L977+772
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+100
	strb	r2, [r3]
	ldr	r3, .L977+776
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+780
	str	r3, [r2]	@ float
	ldr	r3, .L977+784
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+788
	strb	r2, [r3]
	ldr	r3, .L977+792
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+796
	strb	r2, [r3]
	ldr	r3, .L977+800
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+88
	strb	r2, [r3]
	ldr	r3, .L977+804
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+92
	strb	r2, [r3]
	ldr	r3, .L977+808
	ldr	r3, [r3]	@ float
	ldr	r2, .L977+812
	str	r3, [r2]	@ float
	ldr	r3, .L977+816
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+820
	strb	r2, [r3]
	ldr	r3, .L977+824
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L977+828
	strb	r2, [r3]
.L248:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L872
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
.L978:
	.align	2
.L977:
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_evt1
	.word	delta
	.word	t17_evt0
	.word	t17_evt1
	.word	t16_evt0
	.word	t16_evt1
	.word	t15_evt0
	.word	t15_evt1
	.word	t14_evt0
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	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
