	.file	"137429.c"
	.intel_syntax noprefix
	.text
	.globl	f1
	.type	f1, @function
f1:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	rol	edx, cl
	mov	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	f1, .-f1
	.globl	f2
	.type	f2, @function
f2:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	rol	eax, cl
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	f2, .-f2
	.globl	f3
	.type	f3, @function
f3:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	f3, .-f3
	.globl	f4
	.type	f4, @function
f4:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	f4, .-f4
	.globl	f5
	.type	f5, @function
f5:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	f5, .-f5
	.globl	f6
	.type	f6, @function
f6:
.LFB5:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	f6, .-f6
	.globl	f7
	.type	f7, @function
f7:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	f7, .-f7
	.globl	f8
	.type	f8, @function
f8:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	f8, .-f8
	.globl	f9
	.type	f9, @function
f9:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	f9, .-f9
	.globl	f10
	.type	f10, @function
f10:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	rol	eax, cl
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	f10, .-f10
	.globl	f11
	.type	f11, @function
f11:
.LFB10:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE10:
	.size	f11, .-f11
	.globl	f12
	.type	f12, @function
f12:
.LFB11:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE11:
	.size	f12, .-f12
	.globl	f13
	.type	f13, @function
f13:
.LFB12:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE12:
	.size	f13, .-f13
	.globl	f14
	.type	f14, @function
f14:
.LFB13:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE13:
	.size	f14, .-f14
	.globl	f15
	.type	f15, @function
f15:
.LFB14:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE14:
	.size	f15, .-f15
	.globl	f16
	.type	f16, @function
f16:
.LFB15:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE15:
	.size	f16, .-f16
	.globl	f17
	.type	f17, @function
f17:
.LFB16:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	shr	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE16:
	.size	f17, .-f17
	.globl	f18
	.type	f18, @function
f18:
.LFB17:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	shr	esi, cl
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	sal	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE17:
	.size	f18, .-f18
	.globl	f19
	.type	f19, @function
f19:
.LFB18:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE18:
	.size	f19, .-f19
	.globl	f20
	.type	f20, @function
f20:
.LFB19:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE19:
	.size	f20, .-f20
	.globl	f21
	.type	f21, @function
f21:
.LFB20:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE20:
	.size	f21, .-f21
	.globl	f22
	.type	f22, @function
f22:
.LFB21:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE21:
	.size	f22, .-f22
	.globl	f23
	.type	f23, @function
f23:
.LFB22:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE22:
	.size	f23, .-f23
	.globl	f24
	.type	f24, @function
f24:
.LFB23:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE23:
	.size	f24, .-f24
	.globl	f25
	.type	f25, @function
f25:
.LFB24:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	shr	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE24:
	.size	f25, .-f25
	.globl	f26
	.type	f26, @function
f26:
.LFB25:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	shr	esi, cl
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	sal	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE25:
	.size	f26, .-f26
	.globl	f27
	.type	f27, @function
f27:
.LFB26:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE26:
	.size	f27, .-f27
	.globl	f28
	.type	f28, @function
f28:
.LFB27:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE27:
	.size	f28, .-f28
	.globl	f29
	.type	f29, @function
f29:
.LFB28:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE28:
	.size	f29, .-f29
	.globl	f30
	.type	f30, @function
f30:
.LFB29:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE29:
	.size	f30, .-f30
	.globl	f31
	.type	f31, @function
f31:
.LFB30:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE30:
	.size	f31, .-f31
	.globl	f32
	.type	f32, @function
f32:
.LFB31:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE31:
	.size	f32, .-f32
	.globl	f33
	.type	f33, @function
f33:
.LFB32:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	ror	edx, cl
	mov	eax, edx
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE32:
	.size	f33, .-f33
	.globl	f34
	.type	f34, @function
f34:
.LFB33:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	ror	eax, cl
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE33:
	.size	f34, .-f34
	.globl	f35
	.type	f35, @function
f35:
.LFB34:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE34:
	.size	f35, .-f35
	.globl	f36
	.type	f36, @function
f36:
.LFB35:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE35:
	.size	f36, .-f36
	.globl	f37
	.type	f37, @function
f37:
.LFB36:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE36:
	.size	f37, .-f37
	.globl	f38
	.type	f38, @function
f38:
.LFB37:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE37:
	.size	f38, .-f38
	.globl	f39
	.type	f39, @function
f39:
.LFB38:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE38:
	.size	f39, .-f39
	.globl	f40
	.type	f40, @function
f40:
.LFB39:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE39:
	.size	f40, .-f40
	.globl	f41
	.type	f41, @function
f41:
.LFB40:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	shr	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE40:
	.size	f41, .-f41
	.globl	f42
	.type	f42, @function
f42:
.LFB41:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	ror	eax, cl
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE41:
	.size	f42, .-f42
	.globl	f43
	.type	f43, @function
f43:
.LFB42:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE42:
	.size	f43, .-f43
	.globl	f44
	.type	f44, @function
f44:
.LFB43:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE43:
	.size	f44, .-f44
	.globl	f45
	.type	f45, @function
f45:
.LFB44:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE44:
	.size	f45, .-f45
	.globl	f46
	.type	f46, @function
f46:
.LFB45:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE45:
	.size	f46, .-f46
	.globl	f47
	.type	f47, @function
f47:
.LFB46:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE46:
	.size	f47, .-f47
	.globl	f48
	.type	f48, @function
f48:
.LFB47:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	or	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE47:
	.size	f48, .-f48
	.globl	f49
	.type	f49, @function
f49:
.LFB48:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE48:
	.size	f49, .-f49
	.globl	f50
	.type	f50, @function
f50:
.LFB49:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	shr	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE49:
	.size	f50, .-f50
	.globl	f51
	.type	f51, @function
f51:
.LFB50:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE50:
	.size	f51, .-f51
	.globl	f52
	.type	f52, @function
f52:
.LFB51:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE51:
	.size	f52, .-f52
	.globl	f53
	.type	f53, @function
f53:
.LFB52:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE52:
	.size	f53, .-f53
	.globl	f54
	.type	f54, @function
f54:
.LFB53:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE53:
	.size	f54, .-f54
	.globl	f55
	.type	f55, @function
f55:
.LFB54:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE54:
	.size	f55, .-f55
	.globl	f56
	.type	f56, @function
f56:
.LFB55:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE55:
	.size	f56, .-f56
	.globl	f57
	.type	f57, @function
f57:
.LFB56:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE56:
	.size	f57, .-f57
	.globl	f58
	.type	f58, @function
f58:
.LFB57:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	shr	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE57:
	.size	f58, .-f58
	.globl	f59
	.type	f59, @function
f59:
.LFB58:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE58:
	.size	f59, .-f59
	.globl	f60
	.type	f60, @function
f60:
.LFB59:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE59:
	.size	f60, .-f60
	.globl	f61
	.type	f61, @function
f61:
.LFB60:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE60:
	.size	f61, .-f61
	.globl	f62
	.type	f62, @function
f62:
.LFB61:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE61:
	.size	f62, .-f62
	.globl	f63
	.type	f63, @function
f63:
.LFB62:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE62:
	.size	f63, .-f63
	.globl	f64
	.type	f64, @function
f64:
.LFB63:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	xor	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE63:
	.size	f64, .-f64
	.globl	f65
	.type	f65, @function
f65:
.LFB64:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE64:
	.size	f65, .-f65
	.globl	f66
	.type	f66, @function
f66:
.LFB65:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE65:
	.size	f66, .-f66
	.globl	f67
	.type	f67, @function
f67:
.LFB66:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE66:
	.size	f67, .-f67
	.globl	f68
	.type	f68, @function
f68:
.LFB67:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE67:
	.size	f68, .-f68
	.globl	f69
	.type	f69, @function
f69:
.LFB68:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE68:
	.size	f69, .-f69
	.globl	f70
	.type	f70, @function
f70:
.LFB69:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE69:
	.size	f70, .-f70
	.globl	f71
	.type	f71, @function
f71:
.LFB70:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE70:
	.size	f71, .-f71
	.globl	f72
	.type	f72, @function
f72:
.LFB71:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE71:
	.size	f72, .-f72
	.globl	f73
	.type	f73, @function
f73:
.LFB72:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE72:
	.size	f73, .-f73
	.globl	f74
	.type	f74, @function
f74:
.LFB73:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE73:
	.size	f74, .-f74
	.globl	f75
	.type	f75, @function
f75:
.LFB74:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE74:
	.size	f75, .-f75
	.globl	f76
	.type	f76, @function
f76:
.LFB75:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE75:
	.size	f76, .-f76
	.globl	f77
	.type	f77, @function
f77:
.LFB76:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE76:
	.size	f77, .-f77
	.globl	f78
	.type	f78, @function
f78:
.LFB77:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE77:
	.size	f78, .-f78
	.globl	f79
	.type	f79, @function
f79:
.LFB78:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE78:
	.size	f79, .-f79
	.globl	f80
	.type	f80, @function
f80:
.LFB79:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sal	eax, cl
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE79:
	.size	f80, .-f80
	.globl	f81
	.type	f81, @function
f81:
.LFB80:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE80:
	.size	f81, .-f81
	.globl	f82
	.type	f82, @function
f82:
.LFB81:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	shr	eax, cl
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE81:
	.size	f82, .-f82
	.globl	f83
	.type	f83, @function
f83:
.LFB82:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE82:
	.size	f83, .-f83
	.globl	f84
	.type	f84, @function
f84:
.LFB83:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE83:
	.size	f84, .-f84
	.globl	f85
	.type	f85, @function
f85:
.LFB84:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE84:
	.size	f85, .-f85
	.globl	f86
	.type	f86, @function
f86:
.LFB85:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE85:
	.size	f86, .-f86
	.globl	f87
	.type	f87, @function
f87:
.LFB86:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE86:
	.size	f87, .-f87
	.globl	f88
	.type	f88, @function
f88:
.LFB87:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE87:
	.size	f88, .-f88
	.globl	f89
	.type	f89, @function
f89:
.LFB88:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	eax, DWORD PTR -8[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	ecx, eax
	shr	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE88:
	.size	f89, .-f89
	.globl	f90
	.type	f90, @function
f90:
.LFB89:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	QWORD PTR -16[rbp], rsi
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 31
	mov	edx, DWORD PTR -4[rbp]
	mov	esi, edx
	mov	ecx, eax
	sal	esi, cl
	mov	rax, QWORD PTR -16[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR -4[rbp]
	mov	ecx, edx
	shr	eax, cl
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE89:
	.size	f90, .-f90
	.globl	f91
	.type	f91, @function
f91:
.LFB90:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	ror	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE90:
	.size	f91, .-f91
	.globl	f92
	.type	f92, @function
f92:
.LFB91:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	DWORD PTR -8[rbp], esi
	mov	eax, DWORD PTR -4[rbp]
	rol	eax
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE91:
	.size	f92, .-f92
	.globl	f93
	.type	f93, @function
f93:
.LFB92:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, WORD PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE92:
	.size	f93, .-f93
	.globl	f94
	.type	f94, @function
f94:
.LFB93:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	WORD PTR -4[rbp], ax
	movzx	edx, WORD PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 15
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, WORD PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE93:
	.size	f94, .-f94
	.globl	f95
	.type	f95, @function
f95:
.LFB94:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	DWORD PTR -8[rbp], esi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	edx, BYTE PTR -4[rbp]
	mov	eax, DWORD PTR -8[rbp]
	mov	ecx, eax
	sar	edx, cl
	mov	eax, edx
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE94:
	.size	f95, .-f95
	.globl	f96
	.type	f96, @function
f96:
.LFB95:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, edi
	mov	QWORD PTR -16[rbp], rsi
	mov	BYTE PTR -4[rbp], al
	movzx	edx, BYTE PTR -4[rbp]
	mov	rax, QWORD PTR -16[rbp]
	neg	eax
	and	eax, 7
	mov	ecx, eax
	sal	edx, cl
	mov	eax, edx
	mov	esi, eax
	movzx	eax, BYTE PTR -4[rbp]
	mov	rdx, QWORD PTR -16[rbp]
	mov	ecx, edx
	sar	eax, cl
	add	eax, esi
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE95:
	.size	f96, .-f96
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"137429.c"
	.text
	.align	2
	.global	f1
	.syntax unified
	.arm
	.fpu softvfp
	.type	f1, %function
f1:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #32
	ror	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f1, .-f1
	.align	2
	.global	f2
	.syntax unified
	.arm
	.fpu softvfp
	.type	f2, %function
f2:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #32
	ror	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f2, .-f2
	.align	2
	.global	f3
	.syntax unified
	.arm
	.fpu softvfp
	.type	f3, %function
f3:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f3, .-f3
	.align	2
	.global	f4
	.syntax unified
	.arm
	.fpu softvfp
	.type	f4, %function
f4:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f4, .-f4
	.align	2
	.global	f5
	.syntax unified
	.arm
	.fpu softvfp
	.type	f5, %function
f5:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f5, .-f5
	.align	2
	.global	f6
	.syntax unified
	.arm
	.fpu softvfp
	.type	f6, %function
f6:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f6, .-f6
	.align	2
	.global	f7
	.syntax unified
	.arm
	.fpu softvfp
	.type	f7, %function
f7:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f7, .-f7
	.align	2
	.global	f8
	.syntax unified
	.arm
	.fpu softvfp
	.type	f8, %function
f8:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f8, .-f8
	.align	2
	.global	f9
	.syntax unified
	.arm
	.fpu softvfp
	.type	f9, %function
f9:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #32
	ror	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f9, .-f9
	.align	2
	.global	f10
	.syntax unified
	.arm
	.fpu softvfp
	.type	f10, %function
f10:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #32
	ror	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f10, .-f10
	.align	2
	.global	f11
	.syntax unified
	.arm
	.fpu softvfp
	.type	f11, %function
f11:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f11, .-f11
	.align	2
	.global	f12
	.syntax unified
	.arm
	.fpu softvfp
	.type	f12, %function
f12:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f12, .-f12
	.align	2
	.global	f13
	.syntax unified
	.arm
	.fpu softvfp
	.type	f13, %function
f13:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f13, .-f13
	.align	2
	.global	f14
	.syntax unified
	.arm
	.fpu softvfp
	.type	f14, %function
f14:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f14, .-f14
	.align	2
	.global	f15
	.syntax unified
	.arm
	.fpu softvfp
	.type	f15, %function
f15:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f15, .-f15
	.align	2
	.global	f16
	.syntax unified
	.arm
	.fpu softvfp
	.type	f16, %function
f16:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f16, .-f16
	.align	2
	.global	f17
	.syntax unified
	.arm
	.fpu softvfp
	.type	f17, %function
f17:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsr	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	eor	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f17, .-f17
	.align	2
	.global	f18
	.syntax unified
	.arm
	.fpu softvfp
	.type	f18, %function
f18:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsr	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	eor	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f18, .-f18
	.align	2
	.global	f19
	.syntax unified
	.arm
	.fpu softvfp
	.type	f19, %function
f19:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f19, .-f19
	.align	2
	.global	f20
	.syntax unified
	.arm
	.fpu softvfp
	.type	f20, %function
f20:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f20, .-f20
	.align	2
	.global	f21
	.syntax unified
	.arm
	.fpu softvfp
	.type	f21, %function
f21:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	eor	r3, r3, r2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f21, .-f21
	.align	2
	.global	f22
	.syntax unified
	.arm
	.fpu softvfp
	.type	f22, %function
f22:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	eor	r3, r3, r2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f22, .-f22
	.align	2
	.global	f23
	.syntax unified
	.arm
	.fpu softvfp
	.type	f23, %function
f23:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f23, .-f23
	.align	2
	.global	f24
	.syntax unified
	.arm
	.fpu softvfp
	.type	f24, %function
f24:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f24, .-f24
	.align	2
	.global	f25
	.syntax unified
	.arm
	.fpu softvfp
	.type	f25, %function
f25:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsr	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	eor	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f25, .-f25
	.align	2
	.global	f26
	.syntax unified
	.arm
	.fpu softvfp
	.type	f26, %function
f26:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsr	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	eor	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f26, .-f26
	.align	2
	.global	f27
	.syntax unified
	.arm
	.fpu softvfp
	.type	f27, %function
f27:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f27, .-f27
	.align	2
	.global	f28
	.syntax unified
	.arm
	.fpu softvfp
	.type	f28, %function
f28:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f28, .-f28
	.align	2
	.global	f29
	.syntax unified
	.arm
	.fpu softvfp
	.type	f29, %function
f29:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	eor	r3, r3, r2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f29, .-f29
	.align	2
	.global	f30
	.syntax unified
	.arm
	.fpu softvfp
	.type	f30, %function
f30:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	eor	r3, r3, r2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f30, .-f30
	.align	2
	.global	f31
	.syntax unified
	.arm
	.fpu softvfp
	.type	f31, %function
f31:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f31, .-f31
	.align	2
	.global	f32
	.syntax unified
	.arm
	.fpu softvfp
	.type	f32, %function
f32:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f32, .-f32
	.align	2
	.global	f33
	.syntax unified
	.arm
	.fpu softvfp
	.type	f33, %function
f33:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	ror	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f33, .-f33
	.align	2
	.global	f34
	.syntax unified
	.arm
	.fpu softvfp
	.type	f34, %function
f34:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	ror	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f34, .-f34
	.align	2
	.global	f35
	.syntax unified
	.arm
	.fpu softvfp
	.type	f35, %function
f35:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f35, .-f35
	.align	2
	.global	f36
	.syntax unified
	.arm
	.fpu softvfp
	.type	f36, %function
f36:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f36, .-f36
	.align	2
	.global	f37
	.syntax unified
	.arm
	.fpu softvfp
	.type	f37, %function
f37:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f37, .-f37
	.align	2
	.global	f38
	.syntax unified
	.arm
	.fpu softvfp
	.type	f38, %function
f38:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f38, .-f38
	.align	2
	.global	f39
	.syntax unified
	.arm
	.fpu softvfp
	.type	f39, %function
f39:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f39, .-f39
	.align	2
	.global	f40
	.syntax unified
	.arm
	.fpu softvfp
	.type	f40, %function
f40:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f40, .-f40
	.align	2
	.global	f41
	.syntax unified
	.arm
	.fpu softvfp
	.type	f41, %function
f41:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	ror	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f41, .-f41
	.align	2
	.global	f42
	.syntax unified
	.arm
	.fpu softvfp
	.type	f42, %function
f42:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	ror	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f42, .-f42
	.align	2
	.global	f43
	.syntax unified
	.arm
	.fpu softvfp
	.type	f43, %function
f43:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f43, .-f43
	.align	2
	.global	f44
	.syntax unified
	.arm
	.fpu softvfp
	.type	f44, %function
f44:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f44, .-f44
	.align	2
	.global	f45
	.syntax unified
	.arm
	.fpu softvfp
	.type	f45, %function
f45:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f45, .-f45
	.align	2
	.global	f46
	.syntax unified
	.arm
	.fpu softvfp
	.type	f46, %function
f46:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	orr	r3, r2, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f46, .-f46
	.align	2
	.global	f47
	.syntax unified
	.arm
	.fpu softvfp
	.type	f47, %function
f47:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f47, .-f47
	.align	2
	.global	f48
	.syntax unified
	.arm
	.fpu softvfp
	.type	f48, %function
f48:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	orr	r3, r2, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f48, .-f48
	.align	2
	.global	f49
	.syntax unified
	.arm
	.fpu softvfp
	.type	f49, %function
f49:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsr	r3, r1, r3
	eor	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f49, .-f49
	.align	2
	.global	f50
	.syntax unified
	.arm
	.fpu softvfp
	.type	f50, %function
f50:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsr	r3, r1, r3
	eor	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f50, .-f50
	.align	2
	.global	f51
	.syntax unified
	.arm
	.fpu softvfp
	.type	f51, %function
f51:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f51, .-f51
	.align	2
	.global	f52
	.syntax unified
	.arm
	.fpu softvfp
	.type	f52, %function
f52:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f52, .-f52
	.align	2
	.global	f53
	.syntax unified
	.arm
	.fpu softvfp
	.type	f53, %function
f53:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	eor	r3, r3, r2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f53, .-f53
	.align	2
	.global	f54
	.syntax unified
	.arm
	.fpu softvfp
	.type	f54, %function
f54:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	eor	r3, r3, r2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f54, .-f54
	.align	2
	.global	f55
	.syntax unified
	.arm
	.fpu softvfp
	.type	f55, %function
f55:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f55, .-f55
	.align	2
	.global	f56
	.syntax unified
	.arm
	.fpu softvfp
	.type	f56, %function
f56:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f56, .-f56
	.align	2
	.global	f57
	.syntax unified
	.arm
	.fpu softvfp
	.type	f57, %function
f57:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsr	r3, r1, r3
	eor	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f57, .-f57
	.align	2
	.global	f58
	.syntax unified
	.arm
	.fpu softvfp
	.type	f58, %function
f58:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsr	r3, r1, r3
	eor	r3, r3, r2
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f58, .-f58
	.align	2
	.global	f59
	.syntax unified
	.arm
	.fpu softvfp
	.type	f59, %function
f59:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f59, .-f59
	.align	2
	.global	f60
	.syntax unified
	.arm
	.fpu softvfp
	.type	f60, %function
f60:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f60, .-f60
	.align	2
	.global	f61
	.syntax unified
	.arm
	.fpu softvfp
	.type	f61, %function
f61:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	eor	r3, r3, r2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f61, .-f61
	.align	2
	.global	f62
	.syntax unified
	.arm
	.fpu softvfp
	.type	f62, %function
f62:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	asr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #16
	asr	r3, r3, #16
	eor	r3, r3, r2
	lsl	r3, r3, #16
	asr	r3, r3, #16
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f62, .-f62
	.align	2
	.global	f63
	.syntax unified
	.arm
	.fpu softvfp
	.type	f63, %function
f63:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f63, .-f63
	.align	2
	.global	f64
	.syntax unified
	.arm
	.fpu softvfp
	.type	f64, %function
f64:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r2, r3
	lsl	r3, r3, #24
	asr	r2, r3, #24
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #24
	asr	r3, r3, #24
	eor	r3, r3, r2
	lsl	r3, r3, #24
	asr	r3, r3, #24
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f64, .-f64
	.align	2
	.global	f65
	.syntax unified
	.arm
	.fpu softvfp
	.type	f65, %function
f65:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsl	r2, r2, r3
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r1, [fp, #-8]
	lsr	r3, r1, r3
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f65, .-f65
	.align	2
	.global	f66
	.syntax unified
	.arm
	.fpu softvfp
	.type	f66, %function
f66:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsl	r2, r2, r3
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r1, [fp, #-8]
	lsr	r3, r1, r3
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f66, .-f66
	.align	2
	.global	f67
	.syntax unified
	.arm
	.fpu softvfp
	.type	f67, %function
f67:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f67, .-f67
	.align	2
	.global	f68
	.syntax unified
	.arm
	.fpu softvfp
	.type	f68, %function
f68:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f68, .-f68
	.align	2
	.global	f69
	.syntax unified
	.arm
	.fpu softvfp
	.type	f69, %function
f69:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f69, .-f69
	.align	2
	.global	f70
	.syntax unified
	.arm
	.fpu softvfp
	.type	f70, %function
f70:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f70, .-f70
	.align	2
	.global	f71
	.syntax unified
	.arm
	.fpu softvfp
	.type	f71, %function
f71:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r1, r3
	and	r3, r3, #255
	add	r3, r2, r3
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f71, .-f71
	.align	2
	.global	f72
	.syntax unified
	.arm
	.fpu softvfp
	.type	f72, %function
f72:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r1, r3
	and	r3, r3, #255
	add	r3, r2, r3
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f72, .-f72
	.align	2
	.global	f73
	.syntax unified
	.arm
	.fpu softvfp
	.type	f73, %function
f73:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsl	r2, r2, r3
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r1, [fp, #-8]
	lsr	r3, r1, r3
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f73, .-f73
	.align	2
	.global	f74
	.syntax unified
	.arm
	.fpu softvfp
	.type	f74, %function
f74:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsl	r2, r2, r3
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r1, [fp, #-8]
	lsr	r3, r1, r3
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f74, .-f74
	.align	2
	.global	f75
	.syntax unified
	.arm
	.fpu softvfp
	.type	f75, %function
f75:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f75, .-f75
	.align	2
	.global	f76
	.syntax unified
	.arm
	.fpu softvfp
	.type	f76, %function
f76:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f76, .-f76
	.align	2
	.global	f77
	.syntax unified
	.arm
	.fpu softvfp
	.type	f77, %function
f77:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f77, .-f77
	.align	2
	.global	f78
	.syntax unified
	.arm
	.fpu softvfp
	.type	f78, %function
f78:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	asr	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f78, .-f78
	.align	2
	.global	f79
	.syntax unified
	.arm
	.fpu softvfp
	.type	f79, %function
f79:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r1, r3
	and	r3, r3, #255
	add	r3, r2, r3
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f79, .-f79
	.align	2
	.global	f80
	.syntax unified
	.arm
	.fpu softvfp
	.type	f80, %function
f80:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	lsl	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	asr	r3, r1, r3
	and	r3, r3, #255
	add	r3, r2, r3
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f80, .-f80
	.align	2
	.global	f81
	.syntax unified
	.arm
	.fpu softvfp
	.type	f81, %function
f81:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsr	r3, r1, r3
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f81, .-f81
	.align	2
	.global	f82
	.syntax unified
	.arm
	.fpu softvfp
	.type	f82, %function
f82:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsr	r3, r1, r3
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f82, .-f82
	.align	2
	.global	f83
	.syntax unified
	.arm
	.fpu softvfp
	.type	f83, %function
f83:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f83, .-f83
	.align	2
	.global	f84
	.syntax unified
	.arm
	.fpu softvfp
	.type	f84, %function
f84:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f84, .-f84
	.align	2
	.global	f85
	.syntax unified
	.arm
	.fpu softvfp
	.type	f85, %function
f85:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f85, .-f85
	.align	2
	.global	f86
	.syntax unified
	.arm
	.fpu softvfp
	.type	f86, %function
f86:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f86, .-f86
	.align	2
	.global	f87
	.syntax unified
	.arm
	.fpu softvfp
	.type	f87, %function
f87:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	and	r3, r3, #255
	add	r3, r2, r3
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f87, .-f87
	.align	2
	.global	f88
	.syntax unified
	.arm
	.fpu softvfp
	.type	f88, %function
f88:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	and	r3, r3, #255
	add	r3, r2, r3
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f88, .-f88
	.align	2
	.global	f89
	.syntax unified
	.arm
	.fpu softvfp
	.type	f89, %function
f89:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsr	r3, r1, r3
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f89, .-f89
	.align	2
	.global	f90
	.syntax unified
	.arm
	.fpu softvfp
	.type	f90, %function
f90:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #31
	ldr	r2, [fp, #-8]
	lsl	r2, r2, r3
	ldr	r1, [fp, #-8]
	ldr	r3, [fp, #-12]
	lsr	r3, r1, r3
	add	r3, r2, r3
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f90, .-f90
	.align	2
	.global	f91
	.syntax unified
	.arm
	.fpu softvfp
	.type	f91, %function
f91:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #1
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f91, .-f91
	.align	2
	.global	f92
	.syntax unified
	.arm
	.fpu softvfp
	.type	f92, %function
f92:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r3, [fp, #-8]
	ror	r3, r3, #31
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f92, .-f92
	.align	2
	.global	f93
	.syntax unified
	.arm
	.fpu softvfp
	.type	f93, %function
f93:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f93, .-f93
	.align	2
	.global	f94
	.syntax unified
	.arm
	.fpu softvfp
	.type	f94, %function
f94:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strh	r3, [fp, #-6]	@ movhi
	ldrh	r2, [fp, #-6]
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #15
	lsl	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r2, r3, #16
	ldrh	r1, [fp, #-6]
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	add	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f94, .-f94
	.align	2
	.global	f95
	.syntax unified
	.arm
	.fpu softvfp
	.type	f95, %function
f95:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	and	r3, r3, #255
	add	r3, r2, r3
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f95, .-f95
	.align	2
	.global	f96
	.syntax unified
	.arm
	.fpu softvfp
	.type	f96, %function
f96:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	mov	r3, r0
	str	r1, [fp, #-12]
	strb	r3, [fp, #-5]
	ldrb	r2, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	rsb	r3, r3, #0
	and	r3, r3, #7
	lsl	r3, r2, r3
	and	r2, r3, #255
	ldrb	r1, [fp, #-5]	@ zero_extendqisi2
	ldr	r3, [fp, #-12]
	asr	r3, r1, r3
	and	r3, r3, #255
	add	r3, r2, r3
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	f96, .-f96
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
