	.file	"99777.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	_diverge_delta
	.bss
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	p20_l1
	.type	p20_l1, @object
	.size	p20_l1, 1
p20_l1:
	.zero	1
	.globl	_x_p20_l1
	.type	_x_p20_l1, @object
	.size	_x_p20_l1, 1
_x_p20_l1:
	.zero	1
	.globl	p20_saved_max
	.align 4
	.type	p20_saved_max, @object
	.size	p20_saved_max, 4
p20_saved_max:
	.zero	4
	.globl	_x_p20_saved_max
	.align 4
	.type	_x_p20_saved_max, @object
	.size	_x_p20_saved_max, 4
_x_p20_saved_max:
	.zero	4
	.globl	p19_l1
	.type	p19_l1, @object
	.size	p19_l1, 1
p19_l1:
	.zero	1
	.globl	_x_p19_l1
	.type	_x_p19_l1, @object
	.size	_x_p19_l1, 1
_x_p19_l1:
	.zero	1
	.globl	p19_saved_max
	.align 4
	.type	p19_saved_max, @object
	.size	p19_saved_max, 4
p19_saved_max:
	.zero	4
	.globl	_x_p19_saved_max
	.align 4
	.type	_x_p19_saved_max, @object
	.size	_x_p19_saved_max, 4
_x_p19_saved_max:
	.zero	4
	.globl	p17_l1
	.type	p17_l1, @object
	.size	p17_l1, 1
p17_l1:
	.zero	1
	.globl	_x_p17_l1
	.type	_x_p17_l1, @object
	.size	_x_p17_l1, 1
_x_p17_l1:
	.zero	1
	.globl	p17_saved_max
	.align 4
	.type	p17_saved_max, @object
	.size	p17_saved_max, 4
p17_saved_max:
	.zero	4
	.globl	_x_p17_saved_max
	.align 4
	.type	_x_p17_saved_max, @object
	.size	_x_p17_saved_max, 4
_x_p17_saved_max:
	.zero	4
	.globl	p16_l1
	.type	p16_l1, @object
	.size	p16_l1, 1
p16_l1:
	.zero	1
	.globl	_x_p16_l1
	.type	_x_p16_l1, @object
	.size	_x_p16_l1, 1
_x_p16_l1:
	.zero	1
	.globl	p16_saved_max
	.align 4
	.type	p16_saved_max, @object
	.size	p16_saved_max, 4
p16_saved_max:
	.zero	4
	.globl	_x_p16_saved_max
	.align 4
	.type	_x_p16_saved_max, @object
	.size	_x_p16_saved_max, 4
_x_p16_saved_max:
	.zero	4
	.globl	p20_l0
	.type	p20_l0, @object
	.size	p20_l0, 1
p20_l0:
	.zero	1
	.globl	_x_p20_l0
	.type	_x_p20_l0, @object
	.size	_x_p20_l0, 1
_x_p20_l0:
	.zero	1
	.globl	p15_l1
	.type	p15_l1, @object
	.size	p15_l1, 1
p15_l1:
	.zero	1
	.globl	_x_p15_l1
	.type	_x_p15_l1, @object
	.size	_x_p15_l1, 1
_x_p15_l1:
	.zero	1
	.globl	p20_x
	.align 4
	.type	p20_x, @object
	.size	p20_x, 4
p20_x:
	.zero	4
	.globl	_x_p20_x
	.align 4
	.type	_x_p20_x, @object
	.size	_x_p20_x, 4
_x_p20_x:
	.zero	4
	.globl	p15_saved_max
	.align 4
	.type	p15_saved_max, @object
	.size	p15_saved_max, 4
p15_saved_max:
	.zero	4
	.globl	_x_p15_saved_max
	.align 4
	.type	_x_p15_saved_max, @object
	.size	_x_p15_saved_max, 4
_x_p15_saved_max:
	.zero	4
	.globl	p19_l0
	.type	p19_l0, @object
	.size	p19_l0, 1
p19_l0:
	.zero	1
	.globl	_x_p19_l0
	.type	_x_p19_l0, @object
	.size	_x_p19_l0, 1
_x_p19_l0:
	.zero	1
	.globl	p14_l1
	.type	p14_l1, @object
	.size	p14_l1, 1
p14_l1:
	.zero	1
	.globl	_x_p14_l1
	.type	_x_p14_l1, @object
	.size	_x_p14_l1, 1
_x_p14_l1:
	.zero	1
	.globl	p19_x
	.align 4
	.type	p19_x, @object
	.size	p19_x, 4
p19_x:
	.zero	4
	.globl	_x_p19_x
	.align 4
	.type	_x_p19_x, @object
	.size	_x_p19_x, 4
_x_p19_x:
	.zero	4
	.globl	p14_saved_max
	.align 4
	.type	p14_saved_max, @object
	.size	p14_saved_max, 4
p14_saved_max:
	.zero	4
	.globl	_x_p14_saved_max
	.align 4
	.type	_x_p14_saved_max, @object
	.size	_x_p14_saved_max, 4
_x_p14_saved_max:
	.zero	4
	.globl	p17_l0
	.type	p17_l0, @object
	.size	p17_l0, 1
p17_l0:
	.zero	1
	.globl	_x_p17_l0
	.type	_x_p17_l0, @object
	.size	_x_p17_l0, 1
_x_p17_l0:
	.zero	1
	.globl	p12_l1
	.type	p12_l1, @object
	.size	p12_l1, 1
p12_l1:
	.zero	1
	.globl	_x_p12_l1
	.type	_x_p12_l1, @object
	.size	_x_p12_l1, 1
_x_p12_l1:
	.zero	1
	.globl	p17_x
	.align 4
	.type	p17_x, @object
	.size	p17_x, 4
p17_x:
	.zero	4
	.globl	_x_p17_x
	.align 4
	.type	_x_p17_x, @object
	.size	_x_p17_x, 4
_x_p17_x:
	.zero	4
	.globl	p12_saved_max
	.align 4
	.type	p12_saved_max, @object
	.size	p12_saved_max, 4
p12_saved_max:
	.zero	4
	.globl	_x_p12_saved_max
	.align 4
	.type	_x_p12_saved_max, @object
	.size	_x_p12_saved_max, 4
_x_p12_saved_max:
	.zero	4
	.globl	p16_l0
	.type	p16_l0, @object
	.size	p16_l0, 1
p16_l0:
	.zero	1
	.globl	_x_p16_l0
	.type	_x_p16_l0, @object
	.size	_x_p16_l0, 1
_x_p16_l0:
	.zero	1
	.globl	p11_l1
	.type	p11_l1, @object
	.size	p11_l1, 1
p11_l1:
	.zero	1
	.globl	_x_p11_l1
	.type	_x_p11_l1, @object
	.size	_x_p11_l1, 1
_x_p11_l1:
	.zero	1
	.globl	p15_l0
	.type	p15_l0, @object
	.size	p15_l0, 1
p15_l0:
	.zero	1
	.globl	_x_p15_l0
	.type	_x_p15_l0, @object
	.size	_x_p15_l0, 1
_x_p15_l0:
	.zero	1
	.globl	p10_l1
	.type	p10_l1, @object
	.size	p10_l1, 1
p10_l1:
	.zero	1
	.globl	_x_p10_l1
	.type	_x_p10_l1, @object
	.size	_x_p10_l1, 1
_x_p10_l1:
	.zero	1
	.globl	p15_x
	.align 4
	.type	p15_x, @object
	.size	p15_x, 4
p15_x:
	.zero	4
	.globl	_x_p15_x
	.align 4
	.type	_x_p15_x, @object
	.size	_x_p15_x, 4
_x_p15_x:
	.zero	4
	.globl	p10_saved_max
	.align 4
	.type	p10_saved_max, @object
	.size	p10_saved_max, 4
p10_saved_max:
	.zero	4
	.globl	_x_p10_saved_max
	.align 4
	.type	_x_p10_saved_max, @object
	.size	_x_p10_saved_max, 4
_x_p10_saved_max:
	.zero	4
	.globl	p14_l0
	.type	p14_l0, @object
	.size	p14_l0, 1
p14_l0:
	.zero	1
	.globl	_x_p14_l0
	.type	_x_p14_l0, @object
	.size	_x_p14_l0, 1
_x_p14_l0:
	.zero	1
	.globl	p9_l1
	.type	p9_l1, @object
	.size	p9_l1, 1
p9_l1:
	.zero	1
	.globl	_x_p9_l1
	.type	_x_p9_l1, @object
	.size	_x_p9_l1, 1
_x_p9_l1:
	.zero	1
	.globl	p14_x
	.align 4
	.type	p14_x, @object
	.size	p14_x, 4
p14_x:
	.zero	4
	.globl	_x_p14_x
	.align 4
	.type	_x_p14_x, @object
	.size	_x_p14_x, 4
_x_p14_x:
	.zero	4
	.globl	p9_saved_max
	.align 4
	.type	p9_saved_max, @object
	.size	p9_saved_max, 4
p9_saved_max:
	.zero	4
	.globl	_x_p9_saved_max
	.align 4
	.type	_x_p9_saved_max, @object
	.size	_x_p9_saved_max, 4
_x_p9_saved_max:
	.zero	4
	.globl	p12_l0
	.type	p12_l0, @object
	.size	p12_l0, 1
p12_l0:
	.zero	1
	.globl	_x_p12_l0
	.type	_x_p12_l0, @object
	.size	_x_p12_l0, 1
_x_p12_l0:
	.zero	1
	.globl	p7_l1
	.type	p7_l1, @object
	.size	p7_l1, 1
p7_l1:
	.zero	1
	.globl	_x_p7_l1
	.type	_x_p7_l1, @object
	.size	_x_p7_l1, 1
_x_p7_l1:
	.zero	1
	.globl	p12_x
	.align 4
	.type	p12_x, @object
	.size	p12_x, 4
p12_x:
	.zero	4
	.globl	_x_p12_x
	.align 4
	.type	_x_p12_x, @object
	.size	_x_p12_x, 4
_x_p12_x:
	.zero	4
	.globl	p7_saved_max
	.align 4
	.type	p7_saved_max, @object
	.size	p7_saved_max, 4
p7_saved_max:
	.zero	4
	.globl	_x_p7_saved_max
	.align 4
	.type	_x_p7_saved_max, @object
	.size	_x_p7_saved_max, 4
_x_p7_saved_max:
	.zero	4
	.globl	p11_l0
	.type	p11_l0, @object
	.size	p11_l0, 1
p11_l0:
	.zero	1
	.globl	_x_p11_l0
	.type	_x_p11_l0, @object
	.size	_x_p11_l0, 1
_x_p11_l0:
	.zero	1
	.globl	p6_l1
	.type	p6_l1, @object
	.size	p6_l1, 1
p6_l1:
	.zero	1
	.globl	_x_p6_l1
	.type	_x_p6_l1, @object
	.size	_x_p6_l1, 1
_x_p6_l1:
	.zero	1
	.globl	proposed15
	.align 4
	.type	proposed15, @object
	.size	proposed15, 4
proposed15:
	.zero	4
	.globl	_x_proposed15
	.align 4
	.type	_x_proposed15, @object
	.size	_x_proposed15, 4
_x_proposed15:
	.zero	4
	.globl	proposed14
	.align 4
	.type	proposed14, @object
	.size	proposed14, 4
proposed14:
	.zero	4
	.globl	_x_proposed14
	.align 4
	.type	_x_proposed14, @object
	.size	_x_proposed14, 4
_x_proposed14:
	.zero	4
	.globl	proposed13
	.align 4
	.type	proposed13, @object
	.size	proposed13, 4
proposed13:
	.zero	4
	.globl	_x_proposed13
	.align 4
	.type	_x_proposed13, @object
	.size	_x_proposed13, 4
_x_proposed13:
	.zero	4
	.globl	p1_x
	.align 4
	.type	p1_x, @object
	.size	p1_x, 4
p1_x:
	.zero	4
	.globl	_x_p1_x
	.align 4
	.type	_x_p1_x, @object
	.size	_x_p1_x, 4
_x_p1_x:
	.zero	4
	.globl	proposed5
	.align 4
	.type	proposed5, @object
	.size	proposed5, 4
proposed5:
	.zero	4
	.globl	_x_proposed5
	.align 4
	.type	_x_proposed5, @object
	.size	_x_proposed5, 4
_x_proposed5:
	.zero	4
	.globl	proposed4
	.align 4
	.type	proposed4, @object
	.size	proposed4, 4
proposed4:
	.zero	4
	.globl	_x_proposed4
	.align 4
	.type	_x_proposed4, @object
	.size	_x_proposed4, 4
_x_proposed4:
	.zero	4
	.globl	turn4
	.type	turn4, @object
	.size	turn4, 1
turn4:
	.zero	1
	.globl	_x_turn4
	.type	_x_turn4, @object
	.size	_x_turn4, 1
_x_turn4:
	.zero	1
	.globl	max_prop
	.align 4
	.type	max_prop, @object
	.size	max_prop, 4
max_prop:
	.zero	4
	.globl	_x_max_prop
	.align 4
	.type	_x_max_prop, @object
	.size	_x_max_prop, 4
_x_max_prop:
	.zero	4
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	p18_l1
	.type	p18_l1, @object
	.size	p18_l1, 1
p18_l1:
	.zero	1
	.globl	_x_p18_l1
	.type	_x_p18_l1, @object
	.size	_x_p18_l1, 1
_x_p18_l1:
	.zero	1
	.globl	proposed2
	.align 4
	.type	proposed2, @object
	.size	proposed2, 4
proposed2:
	.zero	4
	.globl	_x_proposed2
	.align 4
	.type	_x_proposed2, @object
	.size	_x_proposed2, 4
_x_proposed2:
	.zero	4
	.globl	turn2
	.type	turn2, @object
	.size	turn2, 1
turn2:
	.zero	1
	.globl	_x_turn2
	.type	_x_turn2, @object
	.size	_x_turn2, 1
_x_turn2:
	.zero	1
	.globl	proposed11
	.align 4
	.type	proposed11, @object
	.size	proposed11, 4
proposed11:
	.zero	4
	.globl	_x_proposed11
	.align 4
	.type	_x_proposed11, @object
	.size	_x_proposed11, 4
_x_proposed11:
	.zero	4
	.globl	id3
	.type	id3, @object
	.size	id3, 1
id3:
	.zero	1
	.globl	_x_id3
	.type	_x_id3, @object
	.size	_x_id3, 1
_x_id3:
	.zero	1
	.globl	turn3
	.type	turn3, @object
	.size	turn3, 1
turn3:
	.zero	1
	.globl	_x_turn3
	.type	_x_turn3, @object
	.size	_x_turn3, 1
_x_turn3:
	.zero	1
	.globl	proposed3
	.align 4
	.type	proposed3, @object
	.size	proposed3, 4
proposed3:
	.zero	4
	.globl	_x_proposed3
	.align 4
	.type	_x_proposed3, @object
	.size	_x_proposed3, 4
_x_proposed3:
	.zero	4
	.globl	proposed12
	.align 4
	.type	proposed12, @object
	.size	proposed12, 4
proposed12:
	.zero	4
	.globl	_x_proposed12
	.align 4
	.type	_x_proposed12, @object
	.size	_x_proposed12, 4
_x_proposed12:
	.zero	4
	.globl	id4
	.type	id4, @object
	.size	id4, 1
id4:
	.zero	1
	.globl	_x_id4
	.type	_x_id4, @object
	.size	_x_id4, 1
_x_id4:
	.zero	1
	.globl	p13_x
	.align 4
	.type	p13_x, @object
	.size	p13_x, 4
p13_x:
	.zero	4
	.globl	_x_p13_x
	.align 4
	.type	_x_p13_x, @object
	.size	_x_p13_x, 4
_x_p13_x:
	.zero	4
	.globl	p8_saved_max
	.align 4
	.type	p8_saved_max, @object
	.size	p8_saved_max, 4
p8_saved_max:
	.zero	4
	.globl	_x_p8_saved_max
	.align 4
	.type	_x_p8_saved_max, @object
	.size	_x_p8_saved_max, 4
_x_p8_saved_max:
	.zero	4
	.globl	proposed8
	.align 4
	.type	proposed8, @object
	.size	proposed8, 4
proposed8:
	.zero	4
	.globl	_x_proposed8
	.align 4
	.type	_x_proposed8, @object
	.size	_x_proposed8, 4
_x_proposed8:
	.zero	4
	.globl	id0
	.type	id0, @object
	.size	id0, 1
id0:
	.zero	1
	.globl	_x_id0
	.type	_x_id0, @object
	.size	_x_id0, 1
_x_id0:
	.zero	1
	.globl	p6_l0
	.type	p6_l0, @object
	.size	p6_l0, 1
p6_l0:
	.zero	1
	.globl	_x_p6_l0
	.type	_x_p6_l0, @object
	.size	_x_p6_l0, 1
_x_p6_l0:
	.zero	1
	.globl	p1_l1
	.type	p1_l1, @object
	.size	p1_l1, 1
p1_l1:
	.zero	1
	.globl	_x_p1_l1
	.type	_x_p1_l1, @object
	.size	_x_p1_l1, 1
_x_p1_l1:
	.zero	1
	.globl	p7_x
	.align 4
	.type	p7_x, @object
	.size	p7_x, 4
p7_x:
	.zero	4
	.globl	_x_p7_x
	.align 4
	.type	_x_p7_x, @object
	.size	_x_p7_x, 4
_x_p7_x:
	.zero	4
	.globl	p2_saved_max
	.align 4
	.type	p2_saved_max, @object
	.size	p2_saved_max, 4
p2_saved_max:
	.zero	4
	.globl	_x_p2_saved_max
	.align 4
	.type	_x_p2_saved_max, @object
	.size	_x_p2_saved_max, 4
_x_p2_saved_max:
	.zero	4
	.globl	p18_x
	.align 4
	.type	p18_x, @object
	.size	p18_x, 4
p18_x:
	.zero	4
	.globl	_x_p18_x
	.align 4
	.type	_x_p18_x, @object
	.size	_x_p18_x, 4
_x_p18_x:
	.zero	4
	.globl	p13_saved_max
	.align 4
	.type	p13_saved_max, @object
	.size	p13_saved_max, 4
p13_saved_max:
	.zero	4
	.globl	_x_p13_saved_max
	.align 4
	.type	_x_p13_saved_max, @object
	.size	_x_p13_saved_max, 4
_x_p13_saved_max:
	.zero	4
	.globl	proposed9
	.align 4
	.type	proposed9, @object
	.size	proposed9, 4
proposed9:
	.zero	4
	.globl	_x_proposed9
	.align 4
	.type	_x_proposed9, @object
	.size	_x_proposed9, 4
_x_proposed9:
	.zero	4
	.globl	id1
	.type	id1, @object
	.size	id1, 1
id1:
	.zero	1
	.globl	_x_id1
	.type	_x_id1, @object
	.size	_x_id1, 1
_x_id1:
	.zero	1
	.globl	turn0
	.type	turn0, @object
	.size	turn0, 1
turn0:
	.zero	1
	.globl	_x_turn0
	.type	_x_turn0, @object
	.size	_x_turn0, 1
_x_turn0:
	.zero	1
	.globl	p13_l0
	.type	p13_l0, @object
	.size	p13_l0, 1
p13_l0:
	.zero	1
	.globl	_x_p13_l0
	.type	_x_p13_l0, @object
	.size	_x_p13_l0, 1
_x_p13_l0:
	.zero	1
	.globl	p8_l1
	.type	p8_l1, @object
	.size	p8_l1, 1
p8_l1:
	.zero	1
	.globl	_x_p8_l1
	.type	_x_p8_l1, @object
	.size	_x_p8_l1, 1
_x_p8_l1:
	.zero	1
	.globl	proposed0
	.align 4
	.type	proposed0, @object
	.size	proposed0, 4
proposed0:
	.zero	4
	.globl	_x_proposed0
	.align 4
	.type	_x_proposed0, @object
	.size	_x_proposed0, 4
_x_proposed0:
	.zero	4
	.globl	p18_l0
	.type	p18_l0, @object
	.size	p18_l0, 1
p18_l0:
	.zero	1
	.globl	_x_p18_l0
	.type	_x_p18_l0, @object
	.size	_x_p18_l0, 1
_x_p18_l0:
	.zero	1
	.globl	p13_l1
	.type	p13_l1, @object
	.size	p13_l1, 1
p13_l1:
	.zero	1
	.globl	_x_p13_l1
	.type	_x_p13_l1, @object
	.size	_x_p13_l1, 1
_x_p13_l1:
	.zero	1
	.globl	proposed1
	.align 4
	.type	proposed1, @object
	.size	proposed1, 4
proposed1:
	.zero	4
	.globl	_x_proposed1
	.align 4
	.type	_x_proposed1, @object
	.size	_x_proposed1, 4
_x_proposed1:
	.zero	4
	.globl	p18_saved_max
	.align 4
	.type	p18_saved_max, @object
	.size	p18_saved_max, 4
p18_saved_max:
	.zero	4
	.globl	_x_p18_saved_max
	.align 4
	.type	_x_p18_saved_max, @object
	.size	_x_p18_saved_max, 4
_x_p18_saved_max:
	.zero	4
	.globl	proposed10
	.align 4
	.type	proposed10, @object
	.size	proposed10, 4
proposed10:
	.zero	4
	.globl	_x_proposed10
	.align 4
	.type	_x_proposed10, @object
	.size	_x_proposed10, 4
_x_proposed10:
	.zero	4
	.globl	id2
	.type	id2, @object
	.size	id2, 1
id2:
	.zero	1
	.globl	_x_id2
	.type	_x_id2, @object
	.size	_x_id2, 1
_x_id2:
	.zero	1
	.globl	turn1
	.type	turn1, @object
	.size	turn1, 1
turn1:
	.zero	1
	.globl	_x_turn1
	.type	_x_turn1, @object
	.size	_x_turn1, 1
_x_turn1:
	.zero	1
	.globl	proposed16
	.align 4
	.type	proposed16, @object
	.size	proposed16, 4
proposed16:
	.zero	4
	.globl	_x_proposed16
	.align 4
	.type	_x_proposed16, @object
	.size	_x_proposed16, 4
_x_proposed16:
	.zero	4
	.globl	proposed17
	.align 4
	.type	proposed17, @object
	.size	proposed17, 4
proposed17:
	.zero	4
	.globl	_x_proposed17
	.align 4
	.type	_x_proposed17, @object
	.size	_x_proposed17, 4
_x_proposed17:
	.zero	4
	.globl	proposed18
	.align 4
	.type	proposed18, @object
	.size	proposed18, 4
proposed18:
	.zero	4
	.globl	_x_proposed18
	.align 4
	.type	_x_proposed18, @object
	.size	_x_proposed18, 4
_x_proposed18:
	.zero	4
	.globl	proposed19
	.align 4
	.type	proposed19, @object
	.size	proposed19, 4
proposed19:
	.zero	4
	.globl	_x_proposed19
	.align 4
	.type	_x_proposed19, @object
	.size	_x_proposed19, 4
_x_proposed19:
	.zero	4
	.globl	proposed20
	.align 4
	.type	proposed20, @object
	.size	proposed20, 4
proposed20:
	.zero	4
	.globl	_x_proposed20
	.align 4
	.type	_x_proposed20, @object
	.size	_x_proposed20, 4
_x_proposed20:
	.zero	4
	.globl	p0_x
	.align 4
	.type	p0_x, @object
	.size	p0_x, 4
p0_x:
	.zero	4
	.globl	_x_p0_x
	.align 4
	.type	_x_p0_x, @object
	.size	_x_p0_x, 4
_x_p0_x:
	.zero	4
	.globl	p3_l0
	.type	p3_l0, @object
	.size	p3_l0, 1
p3_l0:
	.zero	1
	.globl	_x_p3_l0
	.type	_x_p3_l0, @object
	.size	_x_p3_l0, 1
_x_p3_l0:
	.zero	1
	.globl	p4_x
	.align 4
	.type	p4_x, @object
	.size	p4_x, 4
p4_x:
	.zero	4
	.globl	_x_p4_x
	.align 4
	.type	_x_p4_x, @object
	.size	_x_p4_x, 4
_x_p4_x:
	.zero	4
	.globl	p0_saved_max
	.align 4
	.type	p0_saved_max, @object
	.size	p0_saved_max, 4
p0_saved_max:
	.zero	4
	.globl	_x_p0_saved_max
	.align 4
	.type	_x_p0_saved_max, @object
	.size	_x_p0_saved_max, 4
_x_p0_saved_max:
	.zero	4
	.globl	p8_l0
	.type	p8_l0, @object
	.size	p8_l0, 1
p8_l0:
	.zero	1
	.globl	_x_p8_l0
	.type	_x_p8_l0, @object
	.size	_x_p8_l0, 1
_x_p8_l0:
	.zero	1
	.globl	p3_l1
	.type	p3_l1, @object
	.size	p3_l1, 1
p3_l1:
	.zero	1
	.globl	_x_p3_l1
	.type	_x_p3_l1, @object
	.size	_x_p3_l1, 1
_x_p3_l1:
	.zero	1
	.globl	p9_x
	.align 4
	.type	p9_x, @object
	.size	p9_x, 4
p9_x:
	.zero	4
	.globl	_x_p9_x
	.align 4
	.type	_x_p9_x, @object
	.size	_x_p9_x, 4
_x_p9_x:
	.zero	4
	.globl	p4_saved_max
	.align 4
	.type	p4_saved_max, @object
	.size	p4_saved_max, 4
p4_saved_max:
	.zero	4
	.globl	_x_p4_saved_max
	.align 4
	.type	_x_p4_saved_max, @object
	.size	_x_p4_saved_max, 4
_x_p4_saved_max:
	.zero	4
	.globl	p11_x
	.align 4
	.type	p11_x, @object
	.size	p11_x, 4
p11_x:
	.zero	4
	.globl	_x_p11_x
	.align 4
	.type	_x_p11_x, @object
	.size	_x_p11_x, 4
_x_p11_x:
	.zero	4
	.globl	p6_saved_max
	.align 4
	.type	p6_saved_max, @object
	.size	p6_saved_max, 4
p6_saved_max:
	.zero	4
	.globl	_x_p6_saved_max
	.align 4
	.type	_x_p6_saved_max, @object
	.size	_x_p6_saved_max, 4
_x_p6_saved_max:
	.zero	4
	.globl	p0_l0
	.type	p0_l0, @object
	.size	p0_l0, 1
p0_l0:
	.zero	1
	.globl	_x_p0_l0
	.type	_x_p0_l0, @object
	.size	_x_p0_l0, 1
_x_p0_l0:
	.zero	1
	.globl	p4_l0
	.type	p4_l0, @object
	.size	p4_l0, 1
p4_l0:
	.zero	1
	.globl	_x_p4_l0
	.type	_x_p4_l0, @object
	.size	_x_p4_l0, 1
_x_p4_l0:
	.zero	1
	.globl	p5_x
	.align 4
	.type	p5_x, @object
	.size	p5_x, 4
p5_x:
	.zero	4
	.globl	_x_p5_x
	.align 4
	.type	_x_p5_x, @object
	.size	_x_p5_x, 4
_x_p5_x:
	.zero	4
	.globl	p16_x
	.align 4
	.type	p16_x, @object
	.size	p16_x, 4
p16_x:
	.zero	4
	.globl	_x_p16_x
	.align 4
	.type	_x_p16_x, @object
	.size	_x_p16_x, 4
_x_p16_x:
	.zero	4
	.globl	p11_saved_max
	.align 4
	.type	p11_saved_max, @object
	.size	p11_saved_max, 4
p11_saved_max:
	.zero	4
	.globl	_x_p11_saved_max
	.align 4
	.type	_x_p11_saved_max, @object
	.size	_x_p11_saved_max, 4
_x_p11_saved_max:
	.zero	4
	.globl	p0_l1
	.type	p0_l1, @object
	.size	p0_l1, 1
p0_l1:
	.zero	1
	.globl	_x_p0_l1
	.type	_x_p0_l1, @object
	.size	_x_p0_l1, 1
_x_p0_l1:
	.zero	1
	.globl	p9_l0
	.type	p9_l0, @object
	.size	p9_l0, 1
p9_l0:
	.zero	1
	.globl	_x_p9_l0
	.type	_x_p9_l0, @object
	.size	_x_p9_l0, 1
_x_p9_l0:
	.zero	1
	.globl	p4_l1
	.type	p4_l1, @object
	.size	p4_l1, 1
p4_l1:
	.zero	1
	.globl	_x_p4_l1
	.type	_x_p4_l1, @object
	.size	_x_p4_l1, 1
_x_p4_l1:
	.zero	1
	.globl	p10_x
	.align 4
	.type	p10_x, @object
	.size	p10_x, 4
p10_x:
	.zero	4
	.globl	_x_p10_x
	.align 4
	.type	_x_p10_x, @object
	.size	_x_p10_x, 4
_x_p10_x:
	.zero	4
	.globl	p5_saved_max
	.align 4
	.type	p5_saved_max, @object
	.size	p5_saved_max, 4
p5_saved_max:
	.zero	4
	.globl	_x_p5_saved_max
	.align 4
	.type	_x_p5_saved_max, @object
	.size	_x_p5_saved_max, 4
_x_p5_saved_max:
	.zero	4
	.globl	inc_max_prop
	.type	inc_max_prop, @object
	.size	inc_max_prop, 1
inc_max_prop:
	.zero	1
	.globl	_x_inc_max_prop
	.type	_x_inc_max_prop, @object
	.size	_x_inc_max_prop, 1
_x_inc_max_prop:
	.zero	1
	.globl	p1_l0
	.type	p1_l0, @object
	.size	p1_l0, 1
p1_l0:
	.zero	1
	.globl	_x_p1_l0
	.type	_x_p1_l0, @object
	.size	_x_p1_l0, 1
_x_p1_l0:
	.zero	1
	.globl	p2_x
	.align 4
	.type	p2_x, @object
	.size	p2_x, 4
p2_x:
	.zero	4
	.globl	_x_p2_x
	.align 4
	.type	_x_p2_x, @object
	.size	_x_p2_x, 4
_x_p2_x:
	.zero	4
	.globl	p2_l0
	.type	p2_l0, @object
	.size	p2_l0, 1
p2_l0:
	.zero	1
	.globl	_x_p2_l0
	.type	_x_p2_l0, @object
	.size	_x_p2_l0, 1
_x_p2_l0:
	.zero	1
	.globl	proposed6
	.align 4
	.type	proposed6, @object
	.size	proposed6, 4
proposed6:
	.zero	4
	.globl	_x_proposed6
	.align 4
	.type	_x_proposed6, @object
	.size	_x_proposed6, 4
_x_proposed6:
	.zero	4
	.globl	p3_x
	.align 4
	.type	p3_x, @object
	.size	p3_x, 4
p3_x:
	.zero	4
	.globl	_x_p3_x
	.align 4
	.type	_x_p3_x, @object
	.size	_x_p3_x, 4
_x_p3_x:
	.zero	4
	.globl	p7_l0
	.type	p7_l0, @object
	.size	p7_l0, 1
p7_l0:
	.zero	1
	.globl	_x_p7_l0
	.type	_x_p7_l0, @object
	.size	_x_p7_l0, 1
_x_p7_l0:
	.zero	1
	.globl	p2_l1
	.type	p2_l1, @object
	.size	p2_l1, 1
p2_l1:
	.zero	1
	.globl	_x_p2_l1
	.type	_x_p2_l1, @object
	.size	_x_p2_l1, 1
_x_p2_l1:
	.zero	1
	.globl	p8_x
	.align 4
	.type	p8_x, @object
	.size	p8_x, 4
p8_x:
	.zero	4
	.globl	_x_p8_x
	.align 4
	.type	_x_p8_x, @object
	.size	_x_p8_x, 4
_x_p8_x:
	.zero	4
	.globl	proposed7
	.align 4
	.type	proposed7, @object
	.size	proposed7, 4
proposed7:
	.zero	4
	.globl	_x_proposed7
	.align 4
	.type	_x_proposed7, @object
	.size	_x_proposed7, 4
_x_proposed7:
	.zero	4
	.globl	p3_saved_max
	.align 4
	.type	p3_saved_max, @object
	.size	p3_saved_max, 4
p3_saved_max:
	.zero	4
	.globl	_x_p3_saved_max
	.align 4
	.type	_x_p3_saved_max, @object
	.size	_x_p3_saved_max, 4
_x_p3_saved_max:
	.zero	4
	.globl	p5_l0
	.type	p5_l0, @object
	.size	p5_l0, 1
p5_l0:
	.zero	1
	.globl	_x_p5_l0
	.type	_x_p5_l0, @object
	.size	_x_p5_l0, 1
_x_p5_l0:
	.zero	1
	.globl	p1_saved_max
	.align 4
	.type	p1_saved_max, @object
	.size	p1_saved_max, 4
p1_saved_max:
	.zero	4
	.globl	_x_p1_saved_max
	.align 4
	.type	_x_p1_saved_max, @object
	.size	_x_p1_saved_max, 4
_x_p1_saved_max:
	.zero	4
	.globl	p6_x
	.align 4
	.type	p6_x, @object
	.size	p6_x, 4
p6_x:
	.zero	4
	.globl	_x_p6_x
	.align 4
	.type	_x_p6_x, @object
	.size	_x_p6_x, 4
_x_p6_x:
	.zero	4
	.globl	p10_l0
	.type	p10_l0, @object
	.size	p10_l0, 1
p10_l0:
	.zero	1
	.globl	_x_p10_l0
	.type	_x_p10_l0, @object
	.size	_x_p10_l0, 1
_x_p10_l0:
	.zero	1
	.globl	p5_l1
	.type	p5_l1, @object
	.size	p5_l1, 1
p5_l1:
	.zero	1
	.globl	_x_p5_l1
	.type	_x_p5_l1, @object
	.size	_x_p5_l1, 1
_x_p5_l1:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p20_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p20_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p19_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p19_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p17_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p17_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p16_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p16_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p20_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p15_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p20_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p15_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p19_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p14_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p19_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p14_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p17_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p12_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p17_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p12_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p16_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p15_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p10_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p15_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p10_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p14_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p9_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p14_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p9_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p7_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p12_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p7_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p6_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed15[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed14[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed13[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed5[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed4[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn4[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR max_prop[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p18_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed2[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed11[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn3[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed3[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed12[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id4[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p13_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p8_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed8[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p7_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p2_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p18_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p13_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed9[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p8_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed0[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p18_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p13_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed1[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p18_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed10[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed16[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed17[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed18[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed19[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed20[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p3_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p4_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p0_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p3_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p9_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p4_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p11_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p6_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p4_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p5_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p16_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p11_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p4_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p10_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p5_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR inc_max_prop[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed6[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p8_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed7[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p3_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p5_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p1_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p5_l1[rip], al
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	jne	.L5
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L6
.L5:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L7
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L6
.L7:
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L6
.L8:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L4
.L6:
	movss	xmm0, DWORD PTR p20_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed20[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p20_x[rip]
	movss	xmm0, DWORD PTR proposed20[rip]
	comiss	xmm0, xmm1
	jnb	.L11
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L11
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L4
.L11:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L13
.L12:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L14
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L13
.L14:
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L13
.L15:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L4
.L13:
	movss	xmm0, DWORD PTR p19_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed19[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p19_x[rip]
	movss	xmm0, DWORD PTR proposed19[rip]
	comiss	xmm0, xmm1
	jnb	.L18
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L18
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L4
.L18:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	jne	.L19
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L20
.L19:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L20
.L21:
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L22
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L20
.L22:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L4
.L20:
	movss	xmm0, DWORD PTR p18_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed18[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p18_x[rip]
	movss	xmm0, DWORD PTR proposed18[rip]
	comiss	xmm0, xmm1
	jnb	.L25
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L4
.L25:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L27
.L26:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L27
.L28:
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L29
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L27
.L29:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L4
.L27:
	movss	xmm0, DWORD PTR p17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed17[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p17_x[rip]
	movss	xmm0, DWORD PTR proposed17[rip]
	comiss	xmm0, xmm1
	jnb	.L32
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L4
.L32:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	jne	.L33
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L34
.L33:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L35
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L34
.L35:
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L34
.L36:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L4
.L34:
	movss	xmm0, DWORD PTR p16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed16[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p16_x[rip]
	movss	xmm0, DWORD PTR proposed16[rip]
	comiss	xmm0, xmm1
	jnb	.L39
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L4
.L39:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	jne	.L40
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L41
.L40:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L42
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L41
.L42:
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L43
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L41
.L43:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L4
.L41:
	movss	xmm0, DWORD PTR p15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed15[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p15_x[rip]
	movss	xmm0, DWORD PTR proposed15[rip]
	comiss	xmm0, xmm1
	jnb	.L46
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L4
.L46:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	jne	.L47
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L48
.L47:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L48
.L49:
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L50
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L48
.L50:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L4
.L48:
	movss	xmm0, DWORD PTR p14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed14[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p14_x[rip]
	movss	xmm0, DWORD PTR proposed14[rip]
	comiss	xmm0, xmm1
	jnb	.L53
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L53
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L4
.L53:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L55
.L54:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L55
.L56:
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L55
.L57:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L4
.L55:
	movss	xmm0, DWORD PTR p13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed13[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p13_x[rip]
	movss	xmm0, DWORD PTR proposed13[rip]
	comiss	xmm0, xmm1
	jnb	.L60
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L4
.L60:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L62
.L61:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L63
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L62
.L63:
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L64
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L62
.L64:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L4
.L62:
	movss	xmm0, DWORD PTR p12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed12[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p12_x[rip]
	movss	xmm0, DWORD PTR proposed12[rip]
	comiss	xmm0, xmm1
	jnb	.L67
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L67
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L4
.L67:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	jne	.L68
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L69
.L68:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L70
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L69
.L70:
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L71
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L69
.L71:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L4
.L69:
	movss	xmm0, DWORD PTR p11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed11[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p11_x[rip]
	movss	xmm0, DWORD PTR proposed11[rip]
	comiss	xmm0, xmm1
	jnb	.L74
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L74
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L4
.L74:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L75
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L76
.L75:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L77
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L76
.L77:
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L78
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L76
.L78:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L4
.L76:
	movss	xmm0, DWORD PTR p10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed10[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p10_x[rip]
	movss	xmm0, DWORD PTR proposed10[rip]
	comiss	xmm0, xmm1
	jnb	.L81
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L4
.L81:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L83
.L82:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L83
.L84:
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L85
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L83
.L85:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L4
.L83:
	movss	xmm0, DWORD PTR p9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed9[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p9_x[rip]
	movss	xmm0, DWORD PTR proposed9[rip]
	comiss	xmm0, xmm1
	jnb	.L88
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L4
.L88:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L90
.L89:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L90
.L91:
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L90
.L92:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L4
.L90:
	movss	xmm0, DWORD PTR p8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed8[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p8_x[rip]
	movss	xmm0, DWORD PTR proposed8[rip]
	comiss	xmm0, xmm1
	jnb	.L95
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L95
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L4
.L95:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L97
.L96:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L97
.L98:
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L99
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L97
.L99:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L4
.L97:
	movss	xmm0, DWORD PTR p7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed7[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p7_x[rip]
	movss	xmm0, DWORD PTR proposed7[rip]
	comiss	xmm0, xmm1
	jnb	.L102
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L102
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L4
.L102:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L103
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L104
.L103:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L104
.L105:
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L106
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L104
.L106:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L4
.L104:
	movss	xmm0, DWORD PTR p6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed6[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p6_x[rip]
	movss	xmm0, DWORD PTR proposed6[rip]
	comiss	xmm0, xmm1
	jnb	.L109
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L4
.L109:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L111
.L110:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L112
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L111
.L112:
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L113
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L111
.L113:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L4
.L111:
	movss	xmm0, DWORD PTR p5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed5[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p5_x[rip]
	movss	xmm0, DWORD PTR proposed5[rip]
	comiss	xmm0, xmm1
	jnb	.L116
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L4
.L116:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L117
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L118
.L117:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L118
.L119:
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L118
.L120:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L4
.L118:
	movss	xmm0, DWORD PTR p4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed4[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p4_x[rip]
	movss	xmm0, DWORD PTR proposed4[rip]
	comiss	xmm0, xmm1
	jnb	.L123
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L123
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L4
.L123:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L124
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L125
.L124:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L126
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L125
.L126:
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L127
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L125
.L127:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L4
.L125:
	movss	xmm0, DWORD PTR p3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed3[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p3_x[rip]
	movss	xmm0, DWORD PTR proposed3[rip]
	comiss	xmm0, xmm1
	jnb	.L130
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L4
.L130:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L132
.L131:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L132
.L133:
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L134
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L132
.L134:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L4
.L132:
	movss	xmm0, DWORD PTR p2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed2[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p2_x[rip]
	movss	xmm0, DWORD PTR proposed2[rip]
	comiss	xmm0, xmm1
	jnb	.L137
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L137
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L4
.L137:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L139
.L138:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L139
.L140:
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L139
.L141:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L4
.L139:
	movss	xmm0, DWORD PTR p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed1[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p1_x[rip]
	movss	xmm0, DWORD PTR proposed1[rip]
	comiss	xmm0, xmm1
	jnb	.L144
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L4
.L144:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L145
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L146
.L145:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L147
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L146
.L147:
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L146
.L148:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L4
.L146:
	movss	xmm0, DWORD PTR p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed0[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p0_x[rip]
	movss	xmm0, DWORD PTR proposed0[rip]
	comiss	xmm0, xmm1
	jnb	.L151
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L4
.L151:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L152:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L154:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L155
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L155
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L155
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L155
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L153
.L155:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L156
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L153
.L156:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L157
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L157
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L157:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L158:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L153
.L159:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L160
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L160
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L160
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L160
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L153
.L160:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L161
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L161:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L162:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L163
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L163
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L163
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L163
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L153
.L163:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L164
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L164
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L153
.L164:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L165
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L165
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L165:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L166
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L166:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L167
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L167
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L167
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L167
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L153
.L167:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L168
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L168
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L153
.L168:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L169
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L169:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L170
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L170
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L170
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L170
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L170:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L171
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L171
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L171
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L171
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L153
.L171:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L172
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L172
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L172
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L153
.L172:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L153
.L173:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L4
.L153:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L174
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L174
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L174:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L176
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L176
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L175
.L176:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L177
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L177
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L177
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L177
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L175
.L177:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L178
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L178
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L178:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L179
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L179
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L179:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L175
.L180:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L181
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L175
.L181:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L182:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L183
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L183
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L183
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L183
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L183:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L184
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L184
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L184
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L184
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L175
.L184:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L185
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L185
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L175
.L185:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L186:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L187
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L187
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L187
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L187:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L175
.L188:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L189
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L189
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L175
.L189:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L190:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L191
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L191
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L191
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L191
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L191:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L192
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L192
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L192
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L175
.L192:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L175
.L193:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L175
.L194:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L4
.L175:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR inc_max_prop[rip]
	test	al, al
	je	.L4
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed0[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed1[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed2[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed3[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed4[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed5[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed6[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed7[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed8[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed9[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed10[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed11[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed12[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed13[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed14[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed15[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed16[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed17[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed18[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed19[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed20[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1158
	ucomiss	xmm0, xmm1
	je	.L217
.L1158:
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1159
	ucomiss	xmm0, xmm1
	je	.L217
.L1159:
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1160
	ucomiss	xmm0, xmm1
	je	.L217
.L1160:
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1161
	ucomiss	xmm0, xmm1
	je	.L217
.L1161:
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1162
	ucomiss	xmm0, xmm1
	je	.L217
.L1162:
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1163
	ucomiss	xmm0, xmm1
	je	.L217
.L1163:
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1164
	ucomiss	xmm0, xmm1
	je	.L217
.L1164:
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1165
	ucomiss	xmm0, xmm1
	je	.L217
.L1165:
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1166
	ucomiss	xmm0, xmm1
	je	.L217
.L1166:
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1167
	ucomiss	xmm0, xmm1
	je	.L217
.L1167:
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1168
	ucomiss	xmm0, xmm1
	je	.L217
.L1168:
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1169
	ucomiss	xmm0, xmm1
	je	.L217
.L1169:
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1170
	ucomiss	xmm0, xmm1
	je	.L217
.L1170:
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1171
	ucomiss	xmm0, xmm1
	je	.L217
.L1171:
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1172
	ucomiss	xmm0, xmm1
	je	.L217
.L1172:
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1173
	ucomiss	xmm0, xmm1
	je	.L217
.L1173:
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1174
	ucomiss	xmm0, xmm1
	je	.L217
.L1174:
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1175
	ucomiss	xmm0, xmm1
	je	.L217
.L1175:
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1176
	ucomiss	xmm0, xmm1
	je	.L217
.L1176:
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1177
	ucomiss	xmm0, xmm1
	je	.L217
.L1177:
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
.L217:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L240
.L4:
	mov	eax, 0
.L240:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L241
.L1092:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p20_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p20_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p19_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p19_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p17_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p17_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p16_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p16_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p20_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p15_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p20_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p15_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p19_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p14_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p19_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p14_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p17_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p12_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p17_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p12_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p16_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p15_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p10_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p15_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p10_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p14_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p9_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p14_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p9_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p7_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p12_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p7_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p6_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed15[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed14[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed13[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed5[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed4[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn4[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_max_prop[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p18_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed2[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed11[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id3[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn3[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed3[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed12[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id4[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p13_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p8_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed8[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p7_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p2_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p18_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p13_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed9[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p8_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed0[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p18_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p13_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed1[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p18_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed10[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed16[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed17[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed18[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed19[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed20[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p3_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p4_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p0_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p3_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p9_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p4_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p11_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p6_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p4_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p5_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p16_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p11_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p4_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p10_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p5_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_inc_max_prop[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed6[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p8_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed7[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p3_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p5_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p1_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p5_l1[rip], al
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	jne	.L242
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L243
.L242:
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L244
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L243
.L244:
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L243
.L245:
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L246
.L243:
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p20_x[rip]
	movss	xmm0, DWORD PTR _x_proposed20[rip]
	comiss	xmm0, xmm1
	jnb	.L247
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L247
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L246
.L247:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L248
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L248
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p20_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p20_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L248
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L248
	movss	xmm0, DWORD PTR p20_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L248
	ucomiss	xmm0, xmm1
	jne	.L248
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	ucomiss	xmm0, xmm1
	jp	.L248
	ucomiss	xmm0, xmm1
	je	.L251
.L248:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L251:
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	jne	.L254
	movss	xmm0, DWORD PTR _x_p20_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L254
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L254
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L254
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	ucomiss	xmm0, xmm1
	jp	.L254
	ucomiss	xmm0, xmm1
	jne	.L254
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L254
	ucomiss	xmm0, xmm1
	je	.L257
.L254:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L257
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L257
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L257
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L257:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L260
	ucomiss	xmm0, xmm1
	jne	.L260
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L260
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	jne	.L260
	movss	xmm0, DWORD PTR _x_p20_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L260
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L260
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L260
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L260
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L260
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L260
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L260
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	ucomiss	xmm0, xmm1
	jp	.L260
	ucomiss	xmm0, xmm1
	je	.L263
.L260:
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L263
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	jne	.L263
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L263
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L263
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L263
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L263
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L263
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L263
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L263:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L266
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	ucomiss	xmm0, xmm1
	jp	.L266
	ucomiss	xmm0, xmm1
	jne	.L266
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L266
	ucomiss	xmm0, xmm1
	jne	.L266
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	jne	.L269
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	jne	.L269
	movss	xmm0, DWORD PTR _x_p20_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L269
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L270
.L269:
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L266
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L266
	movss	xmm0, DWORD PTR p20_x[rip]
	movss	xmm1, DWORD PTR _x_p20_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L266
	ucomiss	xmm0, xmm1
	je	.L270
.L266:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L270
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	jne	.L270
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L270
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L270
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L270
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L270
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L270
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L270
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L270:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L274
	ucomiss	xmm0, xmm1
	jne	.L274
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	jne	.L274
	movss	xmm0, DWORD PTR p20_x[rip]
	movss	xmm1, DWORD PTR _x_p20_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L274
	ucomiss	xmm0, xmm1
	jne	.L274
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L274
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L274
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L274
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L274
	movss	xmm1, DWORD PTR proposed20[rip]
	movss	xmm0, DWORD PTR _x_proposed20[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L277
.L274:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L277
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L277
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L277
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L277
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L277:
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	jne	.L279
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L280
.L279:
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L281
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L280
.L281:
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L282
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L280
.L282:
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L246
.L280:
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p19_x[rip]
	movss	xmm0, DWORD PTR _x_proposed19[rip]
	comiss	xmm0, xmm1
	jnb	.L283
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L283
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L246
.L283:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L284
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p19_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p19_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L284
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L284
	movss	xmm0, DWORD PTR p19_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L284
	ucomiss	xmm0, xmm1
	jne	.L284
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	ucomiss	xmm0, xmm1
	jp	.L284
	ucomiss	xmm0, xmm1
	je	.L287
.L284:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
.L287:
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	jne	.L290
	movss	xmm0, DWORD PTR _x_p19_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L290
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L290
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L290
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	ucomiss	xmm0, xmm1
	jp	.L290
	ucomiss	xmm0, xmm1
	jne	.L290
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L290
	ucomiss	xmm0, xmm1
	je	.L293
.L290:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	jne	.L293
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	jne	.L293
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L293
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L293
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L293
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L293
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L293:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L296
	ucomiss	xmm0, xmm1
	jne	.L296
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L296
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	jne	.L296
	movss	xmm0, DWORD PTR _x_p19_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L296
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L296
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L296
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L296
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L296
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L296
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L296
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	ucomiss	xmm0, xmm1
	jp	.L296
	ucomiss	xmm0, xmm1
	je	.L299
.L296:
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L299
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L299
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L299:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L302
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	ucomiss	xmm0, xmm1
	jp	.L302
	ucomiss	xmm0, xmm1
	jne	.L302
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L302
	ucomiss	xmm0, xmm1
	jne	.L302
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	jne	.L305
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	jne	.L305
	movss	xmm0, DWORD PTR _x_p19_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L305
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L306
.L305:
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L302
	movss	xmm0, DWORD PTR p19_x[rip]
	movss	xmm1, DWORD PTR _x_p19_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L302
	ucomiss	xmm0, xmm1
	je	.L306
.L302:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L306
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L306
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L306
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L306
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L306
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L306:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L310
	ucomiss	xmm0, xmm1
	jne	.L310
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	jne	.L310
	movss	xmm0, DWORD PTR p19_x[rip]
	movss	xmm1, DWORD PTR _x_p19_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L310
	ucomiss	xmm0, xmm1
	jne	.L310
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L310
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L310
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L310
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L310
	movss	xmm1, DWORD PTR proposed19[rip]
	movss	xmm0, DWORD PTR _x_proposed19[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L313
.L310:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L313
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L313
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L313
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L313
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L313:
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	jne	.L315
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L316
.L315:
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L317
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L316
.L317:
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L318
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L316
.L318:
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L246
.L316:
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p18_x[rip]
	movss	xmm0, DWORD PTR _x_proposed18[rip]
	comiss	xmm0, xmm1
	jnb	.L319
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L319
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L246
.L319:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L320
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L320
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p18_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p18_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L320
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L320
	movss	xmm0, DWORD PTR p18_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L320
	ucomiss	xmm0, xmm1
	jne	.L320
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	ucomiss	xmm0, xmm1
	jp	.L320
	ucomiss	xmm0, xmm1
	je	.L323
.L320:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
.L323:
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L326
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	jne	.L326
	movss	xmm0, DWORD PTR _x_p18_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L326
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L326
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L326
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L326
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L326
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L326
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L326
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	ucomiss	xmm0, xmm1
	jp	.L326
	ucomiss	xmm0, xmm1
	jne	.L326
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L326
	ucomiss	xmm0, xmm1
	je	.L329
.L326:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	jne	.L329
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	jne	.L329
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L329
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L329
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L329
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L329
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L329:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L332
	ucomiss	xmm0, xmm1
	jne	.L332
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	jne	.L332
	movss	xmm0, DWORD PTR _x_p18_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L332
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L332
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L332
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L332
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L332
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	ucomiss	xmm0, xmm1
	jp	.L332
	ucomiss	xmm0, xmm1
	je	.L335
.L332:
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	jne	.L335
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L335
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L335
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L335
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L335
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L335
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L335:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L338
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L338
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L338
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L338
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L338
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	ucomiss	xmm0, xmm1
	jp	.L338
	ucomiss	xmm0, xmm1
	jne	.L338
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L338
	ucomiss	xmm0, xmm1
	jne	.L338
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	jne	.L341
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	jne	.L341
	movss	xmm0, DWORD PTR _x_p18_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L341
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L342
.L341:
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L338
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L338
	movss	xmm0, DWORD PTR p18_x[rip]
	movss	xmm1, DWORD PTR _x_p18_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L338
	ucomiss	xmm0, xmm1
	je	.L342
.L338:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L342
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	jne	.L342
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L342
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L342
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L342
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L342
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L342
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L342
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L342:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L346
	ucomiss	xmm0, xmm1
	jne	.L346
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	jne	.L346
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	jne	.L346
	movss	xmm0, DWORD PTR p18_x[rip]
	movss	xmm1, DWORD PTR _x_p18_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L346
	ucomiss	xmm0, xmm1
	jne	.L346
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L346
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L346
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L346
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L346
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L346
	movss	xmm1, DWORD PTR proposed18[rip]
	movss	xmm0, DWORD PTR _x_proposed18[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L349
.L346:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L349
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L349
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L349
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L349
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L349
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L349:
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	jne	.L351
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L352
.L351:
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L353
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L352
.L353:
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L354
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L352
.L354:
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L246
.L352:
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p17_x[rip]
	movss	xmm0, DWORD PTR _x_proposed17[rip]
	comiss	xmm0, xmm1
	jnb	.L355
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L355
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L246
.L355:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L356
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L356
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p17_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p17_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L356
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L356
	movss	xmm0, DWORD PTR p17_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L356
	ucomiss	xmm0, xmm1
	jne	.L356
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	ucomiss	xmm0, xmm1
	jp	.L356
	ucomiss	xmm0, xmm1
	je	.L359
.L356:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L359:
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L362
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	jne	.L362
	movss	xmm0, DWORD PTR _x_p17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L362
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L362
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L362
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L362
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L362
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L362
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L362
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	ucomiss	xmm0, xmm1
	jp	.L362
	ucomiss	xmm0, xmm1
	jne	.L362
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L362
	ucomiss	xmm0, xmm1
	je	.L365
.L362:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	jne	.L365
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	jne	.L365
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L365
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L365
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L365
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L365
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L365:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L368
	ucomiss	xmm0, xmm1
	jne	.L368
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	jne	.L368
	movss	xmm0, DWORD PTR _x_p17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L368
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L368
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L368
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L368
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L368
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	ucomiss	xmm0, xmm1
	jp	.L368
	ucomiss	xmm0, xmm1
	je	.L371
.L368:
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L371
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	jne	.L371
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L371
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L371
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L371
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L371
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L371
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L371
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L371:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L374
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L374
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L374
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L374
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L374
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	ucomiss	xmm0, xmm1
	jp	.L374
	ucomiss	xmm0, xmm1
	jne	.L374
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L374
	ucomiss	xmm0, xmm1
	jne	.L374
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	jne	.L377
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	jne	.L377
	movss	xmm0, DWORD PTR _x_p17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L377
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L378
.L377:
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L374
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L374
	movss	xmm0, DWORD PTR p17_x[rip]
	movss	xmm1, DWORD PTR _x_p17_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L374
	ucomiss	xmm0, xmm1
	je	.L378
.L374:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L378
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	jne	.L378
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L378
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L378
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L378
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L378
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L378
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L378
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L378:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L382
	ucomiss	xmm0, xmm1
	jne	.L382
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	jne	.L382
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	jne	.L382
	movss	xmm0, DWORD PTR p17_x[rip]
	movss	xmm1, DWORD PTR _x_p17_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L382
	ucomiss	xmm0, xmm1
	jne	.L382
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L382
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L382
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L382
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L382
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L382
	movss	xmm1, DWORD PTR proposed17[rip]
	movss	xmm0, DWORD PTR _x_proposed17[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L385
.L382:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L385
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L385
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L385
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L385
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L385:
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	jne	.L387
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L388
.L387:
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L389
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L388
.L389:
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L390
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L388
.L390:
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L246
.L388:
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p16_x[rip]
	movss	xmm0, DWORD PTR _x_proposed16[rip]
	comiss	xmm0, xmm1
	jnb	.L391
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L391
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L246
.L391:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L392
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L392
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p16_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p16_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L392
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L392
	movss	xmm0, DWORD PTR p16_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L392
	ucomiss	xmm0, xmm1
	jne	.L392
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	ucomiss	xmm0, xmm1
	jp	.L392
	ucomiss	xmm0, xmm1
	je	.L395
.L392:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L395:
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L398
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	jne	.L398
	movss	xmm0, DWORD PTR _x_p16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L398
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L398
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L398
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L398
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L398
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L398
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L398
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	ucomiss	xmm0, xmm1
	jp	.L398
	ucomiss	xmm0, xmm1
	jne	.L398
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L398
	ucomiss	xmm0, xmm1
	je	.L401
.L398:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	jne	.L401
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	jne	.L401
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L401
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L401
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L401
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L401
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L401
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L401:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L404
	ucomiss	xmm0, xmm1
	jne	.L404
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	jne	.L404
	movss	xmm0, DWORD PTR _x_p16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L404
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L404
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L404
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L404
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L404
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L404
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	ucomiss	xmm0, xmm1
	jp	.L404
	ucomiss	xmm0, xmm1
	je	.L407
.L404:
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L407
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	jne	.L407
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L407
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L407
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L407
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L407
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L407
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L407
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L407:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L410
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L410
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L410
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L410
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L410
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	ucomiss	xmm0, xmm1
	jp	.L410
	ucomiss	xmm0, xmm1
	jne	.L410
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L410
	ucomiss	xmm0, xmm1
	jne	.L410
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	jne	.L413
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	jne	.L413
	movss	xmm0, DWORD PTR _x_p16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L413
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L414
.L413:
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L410
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L410
	movss	xmm0, DWORD PTR p16_x[rip]
	movss	xmm1, DWORD PTR _x_p16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L410
	ucomiss	xmm0, xmm1
	je	.L414
.L410:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L414
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	jne	.L414
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L414
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L414
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L414
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L414
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L414
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L414
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L414:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L418
	ucomiss	xmm0, xmm1
	jne	.L418
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	jne	.L418
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	jne	.L418
	movss	xmm0, DWORD PTR p16_x[rip]
	movss	xmm1, DWORD PTR _x_p16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L418
	ucomiss	xmm0, xmm1
	jne	.L418
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L418
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L418
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L418
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L418
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L418
	movss	xmm1, DWORD PTR proposed16[rip]
	movss	xmm0, DWORD PTR _x_proposed16[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L421
.L418:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L421
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L421
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L421
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L421
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L421
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L421:
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	jne	.L423
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L424
.L423:
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L425
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L424
.L425:
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L426
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L424
.L426:
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L246
.L424:
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p15_x[rip]
	movss	xmm0, DWORD PTR _x_proposed15[rip]
	comiss	xmm0, xmm1
	jnb	.L427
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L427
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L246
.L427:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L428
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L428
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p15_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p15_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L428
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L428
	movss	xmm0, DWORD PTR p15_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L428
	ucomiss	xmm0, xmm1
	jne	.L428
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	ucomiss	xmm0, xmm1
	jp	.L428
	ucomiss	xmm0, xmm1
	je	.L431
.L428:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
.L431:
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L434
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	jne	.L434
	movss	xmm0, DWORD PTR _x_p15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L434
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L434
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L434
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L434
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L434
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L434
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L434
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	ucomiss	xmm0, xmm1
	jp	.L434
	ucomiss	xmm0, xmm1
	jne	.L434
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L434
	ucomiss	xmm0, xmm1
	je	.L437
.L434:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	jne	.L437
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	jne	.L437
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L437
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L437
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L437
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L437:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L440
	ucomiss	xmm0, xmm1
	jne	.L440
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	jne	.L440
	movss	xmm0, DWORD PTR _x_p15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L440
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L440
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L440
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L440
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	ucomiss	xmm0, xmm1
	jp	.L440
	ucomiss	xmm0, xmm1
	je	.L443
.L440:
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L443
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	jne	.L443
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L443
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L443
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L443
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L443
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L443
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L443
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L443:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L446
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L446
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L446
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L446
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L446
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	ucomiss	xmm0, xmm1
	jp	.L446
	ucomiss	xmm0, xmm1
	jne	.L446
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L446
	ucomiss	xmm0, xmm1
	jne	.L446
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	jne	.L449
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	jne	.L449
	movss	xmm0, DWORD PTR _x_p15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L449
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L450
.L449:
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L446
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L446
	movss	xmm0, DWORD PTR p15_x[rip]
	movss	xmm1, DWORD PTR _x_p15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L446
	ucomiss	xmm0, xmm1
	je	.L450
.L446:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L450
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L450
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L450
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L450
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L450
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L450
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L450:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L454
	ucomiss	xmm0, xmm1
	jne	.L454
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	jne	.L454
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	jne	.L454
	movss	xmm0, DWORD PTR p15_x[rip]
	movss	xmm1, DWORD PTR _x_p15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L454
	ucomiss	xmm0, xmm1
	jne	.L454
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L454
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L454
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L454
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L454
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L454
	movss	xmm1, DWORD PTR proposed15[rip]
	movss	xmm0, DWORD PTR _x_proposed15[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L457
.L454:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L457
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L457
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L457
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L457:
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	jne	.L459
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L460
.L459:
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L461
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L460
.L461:
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L462
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L460
.L462:
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L246
.L460:
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p14_x[rip]
	movss	xmm0, DWORD PTR _x_proposed14[rip]
	comiss	xmm0, xmm1
	jnb	.L463
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L463
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L246
.L463:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L464
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L464
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p14_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p14_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L464
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L464
	movss	xmm0, DWORD PTR p14_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L464
	ucomiss	xmm0, xmm1
	jne	.L464
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	ucomiss	xmm0, xmm1
	jp	.L464
	ucomiss	xmm0, xmm1
	je	.L467
.L464:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
.L467:
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L470
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	jne	.L470
	movss	xmm0, DWORD PTR _x_p14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L470
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L470
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L470
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L470
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L470
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L470
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L470
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	ucomiss	xmm0, xmm1
	jp	.L470
	ucomiss	xmm0, xmm1
	jne	.L470
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L470
	ucomiss	xmm0, xmm1
	je	.L473
.L470:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	jne	.L473
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	jne	.L473
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L473
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L473
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L473
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L473:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L476
	ucomiss	xmm0, xmm1
	jne	.L476
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	jne	.L476
	movss	xmm0, DWORD PTR _x_p14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L476
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L476
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L476
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L476
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	ucomiss	xmm0, xmm1
	jp	.L476
	ucomiss	xmm0, xmm1
	je	.L479
.L476:
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L479
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	jne	.L479
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L479
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L479
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L479
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L479
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L479
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L479
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L479:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L482
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L482
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L482
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L482
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L482
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	ucomiss	xmm0, xmm1
	jp	.L482
	ucomiss	xmm0, xmm1
	jne	.L482
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L482
	ucomiss	xmm0, xmm1
	jne	.L482
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	jne	.L485
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	jne	.L485
	movss	xmm0, DWORD PTR _x_p14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L485
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L486
.L485:
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L482
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L482
	movss	xmm0, DWORD PTR p14_x[rip]
	movss	xmm1, DWORD PTR _x_p14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L482
	ucomiss	xmm0, xmm1
	je	.L486
.L482:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L486
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	jne	.L486
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L486
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L486
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L486
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L486
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L486
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L486
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L486:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L490
	ucomiss	xmm0, xmm1
	jne	.L490
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	jne	.L490
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	jne	.L490
	movss	xmm0, DWORD PTR p14_x[rip]
	movss	xmm1, DWORD PTR _x_p14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L490
	ucomiss	xmm0, xmm1
	jne	.L490
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L490
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L490
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L490
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L490
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L490
	movss	xmm1, DWORD PTR proposed14[rip]
	movss	xmm0, DWORD PTR _x_proposed14[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L493
.L490:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L493
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L493
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L493
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L493:
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	jne	.L495
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L496
.L495:
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L497
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L496
.L497:
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L498
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L496
.L498:
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L246
.L496:
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p13_x[rip]
	movss	xmm0, DWORD PTR _x_proposed13[rip]
	comiss	xmm0, xmm1
	jnb	.L499
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L499
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L246
.L499:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L500
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L500
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p13_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p13_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L500
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L500
	movss	xmm0, DWORD PTR p13_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L500
	ucomiss	xmm0, xmm1
	jne	.L500
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	ucomiss	xmm0, xmm1
	jp	.L500
	ucomiss	xmm0, xmm1
	je	.L503
.L500:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L503:
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L506
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	jne	.L506
	movss	xmm0, DWORD PTR _x_p13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L506
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L506
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L506
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L506
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L506
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L506
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L506
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	ucomiss	xmm0, xmm1
	jp	.L506
	ucomiss	xmm0, xmm1
	jne	.L506
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L506
	ucomiss	xmm0, xmm1
	je	.L509
.L506:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	jne	.L509
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	jne	.L509
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L509
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L509
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L509
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L509:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L512
	ucomiss	xmm0, xmm1
	jne	.L512
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	jne	.L512
	movss	xmm0, DWORD PTR _x_p13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L512
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L512
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L512
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L512
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	ucomiss	xmm0, xmm1
	jp	.L512
	ucomiss	xmm0, xmm1
	je	.L515
.L512:
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L515
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	jne	.L515
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L515
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L515
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L515
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L515
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L515
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L515
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L515:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L518
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L518
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L518
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L518
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L518
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	ucomiss	xmm0, xmm1
	jp	.L518
	ucomiss	xmm0, xmm1
	jne	.L518
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L518
	ucomiss	xmm0, xmm1
	jne	.L518
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	jne	.L521
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	jne	.L521
	movss	xmm0, DWORD PTR _x_p13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L521
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L522
.L521:
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L518
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L518
	movss	xmm0, DWORD PTR p13_x[rip]
	movss	xmm1, DWORD PTR _x_p13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L518
	ucomiss	xmm0, xmm1
	je	.L522
.L518:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L522
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	jne	.L522
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L522
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L522
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L522
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L522
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L522
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L522
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L522:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L526
	ucomiss	xmm0, xmm1
	jne	.L526
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	jne	.L526
	movss	xmm0, DWORD PTR p13_x[rip]
	movss	xmm1, DWORD PTR _x_p13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L526
	ucomiss	xmm0, xmm1
	jne	.L526
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L526
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L526
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L526
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L526
	movss	xmm1, DWORD PTR proposed13[rip]
	movss	xmm0, DWORD PTR _x_proposed13[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L529
.L526:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L529
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L529
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L529
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L529:
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	jne	.L531
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L532
.L531:
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L533
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L532
.L533:
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L534
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L532
.L534:
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L246
.L532:
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p12_x[rip]
	movss	xmm0, DWORD PTR _x_proposed12[rip]
	comiss	xmm0, xmm1
	jnb	.L535
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L535
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L246
.L535:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L536
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L536
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L536
	movss	xmm0, DWORD PTR p12_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L536
	ucomiss	xmm0, xmm1
	jne	.L536
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	ucomiss	xmm0, xmm1
	jp	.L536
	ucomiss	xmm0, xmm1
	je	.L539
.L536:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L539:
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L542
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	jne	.L542
	movss	xmm0, DWORD PTR _x_p12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L542
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L542
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L542
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L542
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L542
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L542
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L542
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	ucomiss	xmm0, xmm1
	jp	.L542
	ucomiss	xmm0, xmm1
	jne	.L542
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L542
	ucomiss	xmm0, xmm1
	je	.L545
.L542:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	jne	.L545
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	jne	.L545
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L545
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L545
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L545
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L545
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L545:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L548
	ucomiss	xmm0, xmm1
	jne	.L548
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	jne	.L548
	movss	xmm0, DWORD PTR _x_p12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L548
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L548
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L548
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L548
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L548
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	ucomiss	xmm0, xmm1
	jp	.L548
	ucomiss	xmm0, xmm1
	je	.L551
.L548:
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L551
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	jne	.L551
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L551
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L551
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L551
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L551
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L551
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L551
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L551:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L554
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L554
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L554
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L554
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L554
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	ucomiss	xmm0, xmm1
	jp	.L554
	ucomiss	xmm0, xmm1
	jne	.L554
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L554
	ucomiss	xmm0, xmm1
	jne	.L554
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	jne	.L557
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	jne	.L557
	movss	xmm0, DWORD PTR _x_p12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L557
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L558
.L557:
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L554
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L554
	movss	xmm0, DWORD PTR p12_x[rip]
	movss	xmm1, DWORD PTR _x_p12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L554
	ucomiss	xmm0, xmm1
	je	.L558
.L554:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L558
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	jne	.L558
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L558
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L558
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L558
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L558
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L558
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L558
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L558:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L562
	ucomiss	xmm0, xmm1
	jne	.L562
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	jne	.L562
	movss	xmm0, DWORD PTR p12_x[rip]
	movss	xmm1, DWORD PTR _x_p12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L562
	ucomiss	xmm0, xmm1
	jne	.L562
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L562
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L562
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L562
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L562
	movss	xmm1, DWORD PTR proposed12[rip]
	movss	xmm0, DWORD PTR _x_proposed12[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L565
.L562:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L565
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L565
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L565
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L565
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L565
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L565
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L565
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L565
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L565:
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	jne	.L567
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L568
.L567:
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L569
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L568
.L569:
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L570
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L568
.L570:
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L246
.L568:
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p11_x[rip]
	movss	xmm0, DWORD PTR _x_proposed11[rip]
	comiss	xmm0, xmm1
	jnb	.L571
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L571
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L246
.L571:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L572
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L572
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L572
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L572
	movss	xmm0, DWORD PTR p11_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L572
	ucomiss	xmm0, xmm1
	jne	.L572
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	ucomiss	xmm0, xmm1
	jp	.L572
	ucomiss	xmm0, xmm1
	je	.L575
.L572:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
.L575:
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	jne	.L578
	movss	xmm0, DWORD PTR _x_p11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L578
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L578
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L578
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L578
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	ucomiss	xmm0, xmm1
	jp	.L578
	ucomiss	xmm0, xmm1
	jne	.L578
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L578
	ucomiss	xmm0, xmm1
	je	.L581
.L578:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	jne	.L581
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	jne	.L581
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L581
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L581
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L581
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L581
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L581:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L584
	ucomiss	xmm0, xmm1
	jne	.L584
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	jne	.L584
	movss	xmm0, DWORD PTR _x_p11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L584
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L584
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L584
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L584
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L584
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	ucomiss	xmm0, xmm1
	jp	.L584
	ucomiss	xmm0, xmm1
	je	.L587
.L584:
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L587
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	jne	.L587
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L587
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L587
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L587
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L587
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L587
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L587
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L587:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L590
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	ucomiss	xmm0, xmm1
	jp	.L590
	ucomiss	xmm0, xmm1
	jne	.L590
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L590
	ucomiss	xmm0, xmm1
	jne	.L590
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	jne	.L593
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	jne	.L593
	movss	xmm0, DWORD PTR _x_p11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L593
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L594
.L593:
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L590
	movss	xmm0, DWORD PTR p11_x[rip]
	movss	xmm1, DWORD PTR _x_p11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L590
	ucomiss	xmm0, xmm1
	je	.L594
.L590:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L594
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	jne	.L594
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L594
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L594
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L594
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L594
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L594
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L594
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L594:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L598
	ucomiss	xmm0, xmm1
	jne	.L598
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	jne	.L598
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	jne	.L598
	movss	xmm0, DWORD PTR p11_x[rip]
	movss	xmm1, DWORD PTR _x_p11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L598
	ucomiss	xmm0, xmm1
	jne	.L598
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L598
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L598
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L598
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L598
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L598
	movss	xmm1, DWORD PTR proposed11[rip]
	movss	xmm0, DWORD PTR _x_proposed11[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L601
.L598:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L601
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L601
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L601
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L601
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L601
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L601:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L603
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L604
.L603:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L605
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L604
.L605:
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L606
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L604
.L606:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L246
.L604:
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p10_x[rip]
	movss	xmm0, DWORD PTR _x_proposed10[rip]
	comiss	xmm0, xmm1
	jnb	.L607
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L607
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L246
.L607:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L608
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L608
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L608
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L608
	movss	xmm0, DWORD PTR p10_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L608
	ucomiss	xmm0, xmm1
	jne	.L608
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	ucomiss	xmm0, xmm1
	jp	.L608
	ucomiss	xmm0, xmm1
	je	.L611
.L608:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
.L611:
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L614
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L614
	movss	xmm0, DWORD PTR _x_p10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L614
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L614
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L614
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	ucomiss	xmm0, xmm1
	jp	.L614
	ucomiss	xmm0, xmm1
	jne	.L614
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L614
	ucomiss	xmm0, xmm1
	je	.L617
.L614:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L617
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L617
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L617:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L620
	ucomiss	xmm0, xmm1
	jne	.L620
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L620
	movss	xmm0, DWORD PTR _x_p10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L620
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L620
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L620
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L620
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L620
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	ucomiss	xmm0, xmm1
	jp	.L620
	ucomiss	xmm0, xmm1
	je	.L623
.L620:
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L623
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L623
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L623
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L623
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L623
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L623
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L623
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L623
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L623:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L626
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	ucomiss	xmm0, xmm1
	jp	.L626
	ucomiss	xmm0, xmm1
	jne	.L626
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L626
	ucomiss	xmm0, xmm1
	jne	.L626
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L629
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L629
	movss	xmm0, DWORD PTR _x_p10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L629
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L630
.L629:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L626
	movss	xmm0, DWORD PTR p10_x[rip]
	movss	xmm1, DWORD PTR _x_p10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L626
	ucomiss	xmm0, xmm1
	je	.L630
.L626:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L630
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L630
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L630
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L630
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L630
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L630
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L630
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L630
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L630:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L634
	ucomiss	xmm0, xmm1
	jne	.L634
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L634
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L634
	movss	xmm0, DWORD PTR p10_x[rip]
	movss	xmm1, DWORD PTR _x_p10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L634
	ucomiss	xmm0, xmm1
	jne	.L634
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L634
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L634
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L634
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L634
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L634
	movss	xmm1, DWORD PTR proposed10[rip]
	movss	xmm0, DWORD PTR _x_proposed10[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L637
.L634:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L637
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L637
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L637
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L637
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L637:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L639
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L640
.L639:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L641
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L640
.L641:
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L642
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L640
.L642:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L246
.L640:
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p9_x[rip]
	movss	xmm0, DWORD PTR _x_proposed9[rip]
	comiss	xmm0, xmm1
	jnb	.L643
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L643
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L246
.L643:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L644
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L644
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L644
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L644
	movss	xmm0, DWORD PTR p9_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L644
	ucomiss	xmm0, xmm1
	jne	.L644
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	ucomiss	xmm0, xmm1
	jp	.L644
	ucomiss	xmm0, xmm1
	je	.L647
.L644:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L647:
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L650
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L650
	movss	xmm0, DWORD PTR _x_p9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L650
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L650
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L650
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L650
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L650
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L650
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L650
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	ucomiss	xmm0, xmm1
	jp	.L650
	ucomiss	xmm0, xmm1
	jne	.L650
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L650
	ucomiss	xmm0, xmm1
	je	.L653
.L650:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L653
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L653
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L653:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L656
	ucomiss	xmm0, xmm1
	jne	.L656
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L656
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L656
	movss	xmm0, DWORD PTR _x_p9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L656
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L656
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L656
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L656
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L656
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L656
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L656
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	ucomiss	xmm0, xmm1
	jp	.L656
	ucomiss	xmm0, xmm1
	je	.L659
.L656:
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L659
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L659
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L659
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L659
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L659
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L659
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L659
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L659
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L659:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L662
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	ucomiss	xmm0, xmm1
	jp	.L662
	ucomiss	xmm0, xmm1
	jne	.L662
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L662
	ucomiss	xmm0, xmm1
	jne	.L662
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L665
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L665
	movss	xmm0, DWORD PTR _x_p9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L665
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L666
.L665:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L662
	movss	xmm0, DWORD PTR p9_x[rip]
	movss	xmm1, DWORD PTR _x_p9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L662
	ucomiss	xmm0, xmm1
	je	.L666
.L662:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L666
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L666
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L666
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L666
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L666
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L666
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L666
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L666
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L666:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L670
	ucomiss	xmm0, xmm1
	jne	.L670
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L670
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L670
	movss	xmm0, DWORD PTR p9_x[rip]
	movss	xmm1, DWORD PTR _x_p9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L670
	ucomiss	xmm0, xmm1
	jne	.L670
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L670
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L670
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L670
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L670
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L670
	movss	xmm1, DWORD PTR proposed9[rip]
	movss	xmm0, DWORD PTR _x_proposed9[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L673
.L670:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L673
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L673
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L673
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L673
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L673
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L673
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L673
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L673
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L673:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L675
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L676
.L675:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L677
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L676
.L677:
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L678
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L676
.L678:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L246
.L676:
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p8_x[rip]
	movss	xmm0, DWORD PTR _x_proposed8[rip]
	comiss	xmm0, xmm1
	jnb	.L679
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L679
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L246
.L679:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L680
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L680
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L680
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L680
	movss	xmm0, DWORD PTR p8_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L680
	ucomiss	xmm0, xmm1
	jne	.L680
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	ucomiss	xmm0, xmm1
	jp	.L680
	ucomiss	xmm0, xmm1
	je	.L683
.L680:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L683:
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L686
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L686
	movss	xmm0, DWORD PTR _x_p8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L686
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L686
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L686
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L686
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L686
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L686
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L686
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	ucomiss	xmm0, xmm1
	jp	.L686
	ucomiss	xmm0, xmm1
	jne	.L686
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L686
	ucomiss	xmm0, xmm1
	je	.L689
.L686:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L689
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L689
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L689
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L689
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L689
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L689
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L689
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L689
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L689:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L692
	ucomiss	xmm0, xmm1
	jne	.L692
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L692
	movss	xmm0, DWORD PTR _x_p8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L692
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L692
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L692
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L692
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L692
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L692
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	ucomiss	xmm0, xmm1
	jp	.L692
	ucomiss	xmm0, xmm1
	je	.L695
.L692:
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L695
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L695
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L695
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L695
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L695
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L695
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L695
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L695
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L695:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L698
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L698
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L698
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L698
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L698
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	ucomiss	xmm0, xmm1
	jp	.L698
	ucomiss	xmm0, xmm1
	jne	.L698
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L698
	ucomiss	xmm0, xmm1
	jne	.L698
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L701
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L701
	movss	xmm0, DWORD PTR _x_p8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L701
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L702
.L701:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L698
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L698
	movss	xmm0, DWORD PTR p8_x[rip]
	movss	xmm1, DWORD PTR _x_p8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L698
	ucomiss	xmm0, xmm1
	je	.L702
.L698:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L702
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L702
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L702
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L702
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L702
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L702
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L702
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L702
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L702:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L706
	ucomiss	xmm0, xmm1
	jne	.L706
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L706
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L706
	movss	xmm0, DWORD PTR p8_x[rip]
	movss	xmm1, DWORD PTR _x_p8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L706
	ucomiss	xmm0, xmm1
	jne	.L706
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L706
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L706
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L706
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L706
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L706
	movss	xmm1, DWORD PTR proposed8[rip]
	movss	xmm0, DWORD PTR _x_proposed8[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L709
.L706:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L709
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L709
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L709
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L709
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L709
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L709
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L709
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L709
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L709:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L711
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L712
.L711:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L713
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L712
.L713:
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L714
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L712
.L714:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L246
.L712:
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p7_x[rip]
	movss	xmm0, DWORD PTR _x_proposed7[rip]
	comiss	xmm0, xmm1
	jnb	.L715
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L715
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L246
.L715:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L716
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L716
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L716
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L716
	movss	xmm0, DWORD PTR p7_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L716
	ucomiss	xmm0, xmm1
	jne	.L716
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	ucomiss	xmm0, xmm1
	jp	.L716
	ucomiss	xmm0, xmm1
	je	.L719
.L716:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
.L719:
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L722
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L722
	movss	xmm0, DWORD PTR _x_p7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L722
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L722
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L722
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L722
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L722
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L722
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L722
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	ucomiss	xmm0, xmm1
	jp	.L722
	ucomiss	xmm0, xmm1
	jne	.L722
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L722
	ucomiss	xmm0, xmm1
	je	.L725
.L722:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L725
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L725
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L725
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L725
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L725
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L725
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L725
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L725
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L725:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L728
	ucomiss	xmm0, xmm1
	jne	.L728
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L728
	movss	xmm0, DWORD PTR _x_p7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L728
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L728
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L728
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L728
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L728
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	ucomiss	xmm0, xmm1
	jp	.L728
	ucomiss	xmm0, xmm1
	je	.L731
.L728:
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L731
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L731
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L731
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L731
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L731
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L731
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L731
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L731
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L731:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L734
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L734
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L734
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L734
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L734
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	ucomiss	xmm0, xmm1
	jp	.L734
	ucomiss	xmm0, xmm1
	jne	.L734
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L734
	ucomiss	xmm0, xmm1
	jne	.L734
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L737
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L737
	movss	xmm0, DWORD PTR _x_p7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L737
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L738
.L737:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L734
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L734
	movss	xmm0, DWORD PTR p7_x[rip]
	movss	xmm1, DWORD PTR _x_p7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L734
	ucomiss	xmm0, xmm1
	je	.L738
.L734:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L738
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L738
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L738
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L738
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L738
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L738:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L742
	ucomiss	xmm0, xmm1
	jne	.L742
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L742
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L742
	movss	xmm0, DWORD PTR p7_x[rip]
	movss	xmm1, DWORD PTR _x_p7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L742
	ucomiss	xmm0, xmm1
	jne	.L742
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L742
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L742
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L742
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L742
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L742
	movss	xmm1, DWORD PTR proposed7[rip]
	movss	xmm0, DWORD PTR _x_proposed7[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L745
.L742:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L745
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L745
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L745
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L745
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L745
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L745
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L745
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L745
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L745:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L747
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L748
.L747:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L749
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L748
.L749:
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L750
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L748
.L750:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L246
.L748:
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p6_x[rip]
	movss	xmm0, DWORD PTR _x_proposed6[rip]
	comiss	xmm0, xmm1
	jnb	.L751
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L751
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L246
.L751:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L752
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L752
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L752
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L752
	movss	xmm0, DWORD PTR p6_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L752
	ucomiss	xmm0, xmm1
	jne	.L752
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	ucomiss	xmm0, xmm1
	jp	.L752
	ucomiss	xmm0, xmm1
	je	.L755
.L752:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
.L755:
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L758
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L758
	movss	xmm0, DWORD PTR _x_p6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L758
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L758
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L758
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L758
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L758
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L758
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L758
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	ucomiss	xmm0, xmm1
	jp	.L758
	ucomiss	xmm0, xmm1
	jne	.L758
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L758
	ucomiss	xmm0, xmm1
	je	.L761
.L758:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L761
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L761
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L761:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L764
	ucomiss	xmm0, xmm1
	jne	.L764
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L764
	movss	xmm0, DWORD PTR _x_p6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L764
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L764
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L764
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L764
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L764
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	ucomiss	xmm0, xmm1
	jp	.L764
	ucomiss	xmm0, xmm1
	je	.L767
.L764:
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L767
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L767
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L767
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L767
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L767
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L767
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L767
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L767
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L767:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L770
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	ucomiss	xmm0, xmm1
	jp	.L770
	ucomiss	xmm0, xmm1
	jne	.L770
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L770
	ucomiss	xmm0, xmm1
	jne	.L770
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L773
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L773
	movss	xmm0, DWORD PTR _x_p6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L773
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L774
.L773:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L770
	movss	xmm0, DWORD PTR p6_x[rip]
	movss	xmm1, DWORD PTR _x_p6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L770
	ucomiss	xmm0, xmm1
	je	.L774
.L770:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L774
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L774
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L774
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L774
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L774
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L774
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L774
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L774
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L774:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L778
	ucomiss	xmm0, xmm1
	jne	.L778
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L778
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L778
	movss	xmm0, DWORD PTR p6_x[rip]
	movss	xmm1, DWORD PTR _x_p6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L778
	ucomiss	xmm0, xmm1
	jne	.L778
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L778
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L778
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L778
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L778
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L778
	movss	xmm1, DWORD PTR proposed6[rip]
	movss	xmm0, DWORD PTR _x_proposed6[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L781
.L778:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L781
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L781
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L781
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L781
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L781
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L781
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L781
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L781
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L781:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L783
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L784
.L783:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L785
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L784
.L785:
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L784
.L786:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L246
.L784:
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p5_x[rip]
	movss	xmm0, DWORD PTR _x_proposed5[rip]
	comiss	xmm0, xmm1
	jnb	.L787
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L787
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L246
.L787:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L788
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L788
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L788
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L788
	movss	xmm0, DWORD PTR p5_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L788
	ucomiss	xmm0, xmm1
	jne	.L788
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	ucomiss	xmm0, xmm1
	jp	.L788
	ucomiss	xmm0, xmm1
	je	.L791
.L788:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L791:
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L794
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L794
	movss	xmm0, DWORD PTR _x_p5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L794
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L794
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L794
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L794
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L794
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L794
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L794
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	ucomiss	xmm0, xmm1
	jp	.L794
	ucomiss	xmm0, xmm1
	jne	.L794
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L794
	ucomiss	xmm0, xmm1
	je	.L797
.L794:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L797
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L797
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L797
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L797
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L797
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L797
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L797
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L797
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L797:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L800
	ucomiss	xmm0, xmm1
	jne	.L800
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L800
	movss	xmm0, DWORD PTR _x_p5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L800
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L800
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L800
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L800
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L800
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	ucomiss	xmm0, xmm1
	jp	.L800
	ucomiss	xmm0, xmm1
	je	.L803
.L800:
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L803
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L803
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L803
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L803
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L803
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L803
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L803:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L806
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L806
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L806
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L806
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L806
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	ucomiss	xmm0, xmm1
	jp	.L806
	ucomiss	xmm0, xmm1
	jne	.L806
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L806
	ucomiss	xmm0, xmm1
	jne	.L806
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L809
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L809
	movss	xmm0, DWORD PTR _x_p5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L809
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L810
.L809:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L806
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L806
	movss	xmm0, DWORD PTR p5_x[rip]
	movss	xmm1, DWORD PTR _x_p5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L806
	ucomiss	xmm0, xmm1
	je	.L810
.L806:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L810
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L810
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L810
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L810
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L810
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L810
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L810
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L810
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L810:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L814
	ucomiss	xmm0, xmm1
	jne	.L814
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L814
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L814
	movss	xmm0, DWORD PTR p5_x[rip]
	movss	xmm1, DWORD PTR _x_p5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L814
	ucomiss	xmm0, xmm1
	jne	.L814
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L814
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L814
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L814
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L814
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L814
	movss	xmm1, DWORD PTR proposed5[rip]
	movss	xmm0, DWORD PTR _x_proposed5[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L817
.L814:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L817
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L817
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L817
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L817
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L817
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L817
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L817
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L817
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L817:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L819
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L820
.L819:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L821
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L820
.L821:
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L820
.L822:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L246
.L820:
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p4_x[rip]
	movss	xmm0, DWORD PTR _x_proposed4[rip]
	comiss	xmm0, xmm1
	jnb	.L823
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L823
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L246
.L823:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L824
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L824
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L824
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L824
	movss	xmm0, DWORD PTR p4_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L824
	ucomiss	xmm0, xmm1
	jne	.L824
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	ucomiss	xmm0, xmm1
	jp	.L824
	ucomiss	xmm0, xmm1
	je	.L827
.L824:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L827:
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L830
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L830
	movss	xmm0, DWORD PTR _x_p4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L830
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L830
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L830
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L830
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L830
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L830
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L830
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	ucomiss	xmm0, xmm1
	jp	.L830
	ucomiss	xmm0, xmm1
	jne	.L830
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L830
	ucomiss	xmm0, xmm1
	je	.L833
.L830:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L833
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L833
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L833
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L833
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L833
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L833
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L833
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L833
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L833:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L836
	ucomiss	xmm0, xmm1
	jne	.L836
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L836
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L836
	movss	xmm0, DWORD PTR _x_p4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L836
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L836
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L836
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L836
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L836
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L836
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L836
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	ucomiss	xmm0, xmm1
	jp	.L836
	ucomiss	xmm0, xmm1
	je	.L839
.L836:
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L839
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L839
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L839
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L839
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L839
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L839
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L839
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L839
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L839:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L842
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L842
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L842
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L842
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L842
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	ucomiss	xmm0, xmm1
	jp	.L842
	ucomiss	xmm0, xmm1
	jne	.L842
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L842
	ucomiss	xmm0, xmm1
	jne	.L842
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L845
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L845
	movss	xmm0, DWORD PTR _x_p4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L845
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L846
.L845:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L842
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L842
	movss	xmm0, DWORD PTR p4_x[rip]
	movss	xmm1, DWORD PTR _x_p4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L842
	ucomiss	xmm0, xmm1
	je	.L846
.L842:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L846
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L846
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L846
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L846
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L846
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L846
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L846
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L846
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L846:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L850
	ucomiss	xmm0, xmm1
	jne	.L850
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L850
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L850
	movss	xmm0, DWORD PTR p4_x[rip]
	movss	xmm1, DWORD PTR _x_p4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L850
	ucomiss	xmm0, xmm1
	jne	.L850
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L850
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L850
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L850
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L850
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L850
	movss	xmm1, DWORD PTR proposed4[rip]
	movss	xmm0, DWORD PTR _x_proposed4[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L853
.L850:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L853
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L853
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L853
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L853
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L853
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L853
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L853
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L853
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L853:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L855
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L856
.L855:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L857
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L856
.L857:
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L858
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L856
.L858:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L246
.L856:
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p3_x[rip]
	movss	xmm0, DWORD PTR _x_proposed3[rip]
	comiss	xmm0, xmm1
	jnb	.L859
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L859
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L246
.L859:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L860
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L860
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L860
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L860
	movss	xmm0, DWORD PTR p3_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L860
	ucomiss	xmm0, xmm1
	jne	.L860
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	ucomiss	xmm0, xmm1
	jp	.L860
	ucomiss	xmm0, xmm1
	je	.L863
.L860:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
.L863:
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L866
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L866
	movss	xmm0, DWORD PTR _x_p3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L866
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L866
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L866
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L866
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L866
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L866
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L866
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	ucomiss	xmm0, xmm1
	jp	.L866
	ucomiss	xmm0, xmm1
	jne	.L866
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L866
	ucomiss	xmm0, xmm1
	je	.L869
.L866:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L869
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L869
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L869
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L869
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L869
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L869
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L869
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L869
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L869:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L872
	ucomiss	xmm0, xmm1
	jne	.L872
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L872
	movss	xmm0, DWORD PTR _x_p3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L872
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L872
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L872
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L872
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L872
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L872
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	ucomiss	xmm0, xmm1
	jp	.L872
	ucomiss	xmm0, xmm1
	je	.L875
.L872:
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L875
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L875
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L875
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L875
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L875
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L875
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L875
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L875
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L875:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L878
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L878
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L878
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L878
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L878
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	ucomiss	xmm0, xmm1
	jp	.L878
	ucomiss	xmm0, xmm1
	jne	.L878
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L878
	ucomiss	xmm0, xmm1
	jne	.L878
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L881
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L881
	movss	xmm0, DWORD PTR _x_p3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L881
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L882
.L881:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L878
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L878
	movss	xmm0, DWORD PTR p3_x[rip]
	movss	xmm1, DWORD PTR _x_p3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L878
	ucomiss	xmm0, xmm1
	je	.L882
.L878:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L882
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L882
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L882
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L882
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L882
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L882
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L882
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L882
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L882:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L886
	ucomiss	xmm0, xmm1
	jne	.L886
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L886
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L886
	movss	xmm0, DWORD PTR p3_x[rip]
	movss	xmm1, DWORD PTR _x_p3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L886
	ucomiss	xmm0, xmm1
	jne	.L886
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L886
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L886
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L886
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L886
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L886
	movss	xmm1, DWORD PTR proposed3[rip]
	movss	xmm0, DWORD PTR _x_proposed3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L889
.L886:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L889
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L889
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L889
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L889
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L889
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L889
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L889
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L889
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L889:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L891
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L892
.L891:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L893
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L892
.L893:
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L894
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L892
.L894:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L246
.L892:
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p2_x[rip]
	movss	xmm0, DWORD PTR _x_proposed2[rip]
	comiss	xmm0, xmm1
	jnb	.L895
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L895
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L246
.L895:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L896
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L896
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L896
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L896
	movss	xmm0, DWORD PTR p2_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L896
	ucomiss	xmm0, xmm1
	jne	.L896
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	ucomiss	xmm0, xmm1
	jp	.L896
	ucomiss	xmm0, xmm1
	je	.L899
.L896:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
.L899:
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L902
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L902
	movss	xmm0, DWORD PTR _x_p2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L902
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L902
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L902
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L902
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L902
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L902
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L902
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	ucomiss	xmm0, xmm1
	jp	.L902
	ucomiss	xmm0, xmm1
	jne	.L902
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L902
	ucomiss	xmm0, xmm1
	je	.L905
.L902:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L905
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L905
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L905
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L905:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L908
	ucomiss	xmm0, xmm1
	jne	.L908
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L908
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L908
	movss	xmm0, DWORD PTR _x_p2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L908
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L908
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L908
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L908
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L908
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L908
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L908
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	ucomiss	xmm0, xmm1
	jp	.L908
	ucomiss	xmm0, xmm1
	je	.L911
.L908:
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L911
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L911
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L911
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L911
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L911
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L911
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L911
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L911
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L911:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L914
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L914
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L914
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L914
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L914
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	ucomiss	xmm0, xmm1
	jp	.L914
	ucomiss	xmm0, xmm1
	jne	.L914
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L914
	ucomiss	xmm0, xmm1
	jne	.L914
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L917
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L917
	movss	xmm0, DWORD PTR _x_p2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L917
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L918
.L917:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L914
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L914
	movss	xmm0, DWORD PTR p2_x[rip]
	movss	xmm1, DWORD PTR _x_p2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L914
	ucomiss	xmm0, xmm1
	je	.L918
.L914:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L918
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L918
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L918
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L918
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L918
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L918
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L918
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L918
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L918:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L922
	ucomiss	xmm0, xmm1
	jne	.L922
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L922
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L922
	movss	xmm0, DWORD PTR p2_x[rip]
	movss	xmm1, DWORD PTR _x_p2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L922
	ucomiss	xmm0, xmm1
	jne	.L922
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L922
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L922
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L922
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L922
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L922
	movss	xmm1, DWORD PTR proposed2[rip]
	movss	xmm0, DWORD PTR _x_proposed2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L925
.L922:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L925
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L925
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L925
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L925
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L925
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L925
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L925
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L925
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L925:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L927
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L928
.L927:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L929
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L928
.L929:
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L930
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L928
.L930:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L246
.L928:
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	movss	xmm0, DWORD PTR _x_proposed1[rip]
	comiss	xmm0, xmm1
	jnb	.L931
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L931
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L246
.L931:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L932
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L932
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L932
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L932
	movss	xmm0, DWORD PTR p1_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L932
	ucomiss	xmm0, xmm1
	jne	.L932
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	ucomiss	xmm0, xmm1
	jp	.L932
	ucomiss	xmm0, xmm1
	je	.L935
.L932:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L935:
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L938
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L938
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L938
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L938
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L938
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L938
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L938
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L938
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L938
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	ucomiss	xmm0, xmm1
	jp	.L938
	ucomiss	xmm0, xmm1
	jne	.L938
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L938
	ucomiss	xmm0, xmm1
	je	.L941
.L938:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L941
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L941
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L941
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L941:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L944
	ucomiss	xmm0, xmm1
	jne	.L944
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L944
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L944
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L944
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L944
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L944
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L944
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L944
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L944
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L944
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	ucomiss	xmm0, xmm1
	jp	.L944
	ucomiss	xmm0, xmm1
	je	.L947
.L944:
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L947
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L947
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L947
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L947
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L947
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L947
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L947
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L947
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L947:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L950
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L950
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L950
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L950
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L950
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	ucomiss	xmm0, xmm1
	jp	.L950
	ucomiss	xmm0, xmm1
	jne	.L950
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L950
	ucomiss	xmm0, xmm1
	jne	.L950
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L953
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L953
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L953
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L954
.L953:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L950
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L950
	movss	xmm0, DWORD PTR p1_x[rip]
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L950
	ucomiss	xmm0, xmm1
	je	.L954
.L950:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L954
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L954
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L954
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L954
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L954
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L954
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L954
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L954
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L954:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L958
	ucomiss	xmm0, xmm1
	jne	.L958
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L958
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L958
	movss	xmm0, DWORD PTR p1_x[rip]
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L958
	ucomiss	xmm0, xmm1
	jne	.L958
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L958
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L958
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L958
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L958
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L958
	movss	xmm1, DWORD PTR proposed1[rip]
	movss	xmm0, DWORD PTR _x_proposed1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L961
.L958:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L961
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L961
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L961
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L961
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L961
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L961
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L961
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L961
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L961:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L963
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L964
.L963:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L965
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L964
.L965:
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L966
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L964
.L966:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L246
.L964:
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	movss	xmm0, DWORD PTR _x_proposed0[rip]
	comiss	xmm0, xmm1
	jnb	.L967
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L967
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L246
.L967:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L968
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L968
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L968
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L968
	movss	xmm0, DWORD PTR p0_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L968
	ucomiss	xmm0, xmm1
	jne	.L968
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	ucomiss	xmm0, xmm1
	jp	.L968
	ucomiss	xmm0, xmm1
	je	.L971
.L968:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L246
.L971:
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L974
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L974
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L974
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L974
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L974
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L974
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L974
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L974
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L974
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	ucomiss	xmm0, xmm1
	jp	.L974
	ucomiss	xmm0, xmm1
	jne	.L974
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L974
	ucomiss	xmm0, xmm1
	je	.L977
.L974:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L977
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L977
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L977:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L980
	ucomiss	xmm0, xmm1
	jne	.L980
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L980
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L980
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L980
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L980
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L980
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L980
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L980
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L980
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L980
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	ucomiss	xmm0, xmm1
	jp	.L980
	ucomiss	xmm0, xmm1
	je	.L983
.L980:
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L983
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L983
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L983
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L983
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L983
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L983
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L983
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L983
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L983:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L986
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L986
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L986
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L986
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L986
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	ucomiss	xmm0, xmm1
	jp	.L986
	ucomiss	xmm0, xmm1
	jne	.L986
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L986
	ucomiss	xmm0, xmm1
	jne	.L986
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L989
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L989
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L989
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L990
.L989:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L986
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L986
	movss	xmm0, DWORD PTR p0_x[rip]
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L986
	ucomiss	xmm0, xmm1
	je	.L990
.L986:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L990
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L990
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L990
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L990
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L990
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L990
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L990
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L990
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L990:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L994
	ucomiss	xmm0, xmm1
	jne	.L994
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L994
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L994
	movss	xmm0, DWORD PTR p0_x[rip]
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L994
	ucomiss	xmm0, xmm1
	jne	.L994
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L994
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L994
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L994
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L994
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L994
	movss	xmm1, DWORD PTR proposed0[rip]
	movss	xmm0, DWORD PTR _x_proposed0[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L997
.L994:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L997
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L997
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L997
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L997
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L997
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L997
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L997
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L997
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L246
.L997:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L999
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L999:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1001
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1001
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1001
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1001
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1001:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1002
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1002
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1002
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1002
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1000
.L1002:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1003
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1003
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1003
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1003
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1000
.L1003:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1004
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1004
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1004
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1004
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1004:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1005
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1005
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1005
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1005
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1005:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1006
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1006
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1006
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1006
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1000
.L1006:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1007
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1007
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1007
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1007
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1000
.L1007:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1008
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1008
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1008
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1008
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1008:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1009
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1009
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1009
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1009
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1009:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1010
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1010
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1010
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1010
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1000
.L1010:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1011
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1011
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1011
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1011
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1000
.L1011:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1012
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1012
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1012
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1012
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1012:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1013
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1013
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1013
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1013
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1013:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1014
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1014
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1014
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1014
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1000
.L1014:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1015
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1015
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1015
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1015
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1000
.L1015:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1016
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1016
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1016
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1016
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1016:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1017
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1017
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1017
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1017
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1017:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1018
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1018
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1018
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1018
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1000
.L1018:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1019
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1019
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1019
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1019
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1000
.L1019:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1020
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1020
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1020
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1020
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1000
.L1020:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L246
.L1000:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1021
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1021
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1021
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1021
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1021:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1023
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1023
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1023
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1023
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1022
.L1023:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1024
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1024
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1024
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1024
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1022
.L1024:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1025
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1025
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1025
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1025
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1025:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1026
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1026
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1026
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1026
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1026:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1027
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1027
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1027
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1027
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1022
.L1027:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1028
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1028
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1028
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1028
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1022
.L1028:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1029
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1029:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1030
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1030
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1030
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1030
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1030:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1031
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1031
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1031
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1031
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1022
.L1031:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1032
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1032
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1032
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1032
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1022
.L1032:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1033
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1033
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1033
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1033
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1033:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1034
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1034
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1034
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1034
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1034:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1035
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1035
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1035
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1035
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1022
.L1035:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1036
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1036
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1036
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1036
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1022
.L1036:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1037
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1037
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1037
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1037
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1037:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1038
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1038
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1038
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1038
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1038:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1039
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1039
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1039
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1039
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1022
.L1039:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1040
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1040
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1040
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1040
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1022
.L1040:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1041
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1041
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1041
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1041
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1022
.L1041:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L246
.L1022:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L1042
	movzx	eax, BYTE PTR _x_inc_max_prop[rip]
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L246
.L1042:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L246
	movss	xmm0, DWORD PTR _x_proposed0[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1432
	ucomiss	xmm0, xmm1
	je	.L1065
.L1432:
	movss	xmm0, DWORD PTR _x_proposed1[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1433
	ucomiss	xmm0, xmm1
	je	.L1065
.L1433:
	movss	xmm0, DWORD PTR _x_proposed2[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1434
	ucomiss	xmm0, xmm1
	je	.L1065
.L1434:
	movss	xmm0, DWORD PTR _x_proposed3[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1435
	ucomiss	xmm0, xmm1
	je	.L1065
.L1435:
	movss	xmm0, DWORD PTR _x_proposed4[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1436
	ucomiss	xmm0, xmm1
	je	.L1065
.L1436:
	movss	xmm0, DWORD PTR _x_proposed5[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1437
	ucomiss	xmm0, xmm1
	je	.L1065
.L1437:
	movss	xmm0, DWORD PTR _x_proposed6[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1438
	ucomiss	xmm0, xmm1
	je	.L1065
.L1438:
	movss	xmm0, DWORD PTR _x_proposed7[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1439
	ucomiss	xmm0, xmm1
	je	.L1065
.L1439:
	movss	xmm0, DWORD PTR _x_proposed8[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1440
	ucomiss	xmm0, xmm1
	je	.L1065
.L1440:
	movss	xmm0, DWORD PTR _x_proposed9[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1441
	ucomiss	xmm0, xmm1
	je	.L1065
.L1441:
	movss	xmm0, DWORD PTR _x_proposed10[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1442
	ucomiss	xmm0, xmm1
	je	.L1065
.L1442:
	movss	xmm0, DWORD PTR _x_proposed11[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1443
	ucomiss	xmm0, xmm1
	je	.L1065
.L1443:
	movss	xmm0, DWORD PTR _x_proposed12[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1444
	ucomiss	xmm0, xmm1
	je	.L1065
.L1444:
	movss	xmm0, DWORD PTR _x_proposed13[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1445
	ucomiss	xmm0, xmm1
	je	.L1065
.L1445:
	movss	xmm0, DWORD PTR _x_proposed14[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1446
	ucomiss	xmm0, xmm1
	je	.L1065
.L1446:
	movss	xmm0, DWORD PTR _x_proposed15[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1447
	ucomiss	xmm0, xmm1
	je	.L1065
.L1447:
	movss	xmm0, DWORD PTR _x_proposed16[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1448
	ucomiss	xmm0, xmm1
	je	.L1065
.L1448:
	movss	xmm0, DWORD PTR _x_proposed17[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1449
	ucomiss	xmm0, xmm1
	je	.L1065
.L1449:
	movss	xmm0, DWORD PTR _x_proposed18[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1450
	ucomiss	xmm0, xmm1
	je	.L1065
.L1450:
	movss	xmm0, DWORD PTR _x_proposed19[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1451
	ucomiss	xmm0, xmm1
	je	.L1065
.L1451:
	movss	xmm0, DWORD PTR _x_proposed20[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L246
	ucomiss	xmm0, xmm1
	jne	.L246
.L1065:
	movzx	eax, BYTE PTR _x_inc_max_prop[rip]
	test	al, al
	sete	dl
	movss	xmm1, DWORD PTR max_prop[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, edx
	test	al, al
	je	.L246
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L1452
	ucomiss	xmm0, xmm1
	je	.L1087
.L1452:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L246
.L1087:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L1089
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L246
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L246
.L1089:
	mov	eax, 1
	jmp	.L1091
.L246:
	mov	eax, 0
.L1091:
	mov	DWORD PTR -4[rbp], eax
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	mov	BYTE PTR p20_l1[rip], al
	movss	xmm0, DWORD PTR _x_p20_saved_max[rip]
	movss	DWORD PTR p20_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	mov	BYTE PTR p19_l1[rip], al
	movss	xmm0, DWORD PTR _x_p19_saved_max[rip]
	movss	DWORD PTR p19_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	mov	BYTE PTR p17_l1[rip], al
	movss	xmm0, DWORD PTR _x_p17_saved_max[rip]
	movss	DWORD PTR p17_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	mov	BYTE PTR p16_l1[rip], al
	movss	xmm0, DWORD PTR _x_p16_saved_max[rip]
	movss	DWORD PTR p16_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	mov	BYTE PTR p20_l0[rip], al
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	mov	BYTE PTR p15_l1[rip], al
	movss	xmm0, DWORD PTR _x_p20_x[rip]
	movss	DWORD PTR p20_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p15_saved_max[rip]
	movss	DWORD PTR p15_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	mov	BYTE PTR p19_l0[rip], al
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	mov	BYTE PTR p14_l1[rip], al
	movss	xmm0, DWORD PTR _x_p19_x[rip]
	movss	DWORD PTR p19_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p14_saved_max[rip]
	movss	DWORD PTR p14_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	mov	BYTE PTR p17_l0[rip], al
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	mov	BYTE PTR p12_l1[rip], al
	movss	xmm0, DWORD PTR _x_p17_x[rip]
	movss	DWORD PTR p17_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p12_saved_max[rip]
	movss	DWORD PTR p12_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	mov	BYTE PTR p16_l0[rip], al
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	mov	BYTE PTR p11_l1[rip], al
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	mov	BYTE PTR p15_l0[rip], al
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	mov	BYTE PTR p10_l1[rip], al
	movss	xmm0, DWORD PTR _x_p15_x[rip]
	movss	DWORD PTR p15_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p10_saved_max[rip]
	movss	DWORD PTR p10_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	mov	BYTE PTR p14_l0[rip], al
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	mov	BYTE PTR p9_l1[rip], al
	movss	xmm0, DWORD PTR _x_p14_x[rip]
	movss	DWORD PTR p14_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p9_saved_max[rip]
	movss	DWORD PTR p9_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	mov	BYTE PTR p12_l0[rip], al
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	mov	BYTE PTR p7_l1[rip], al
	movss	xmm0, DWORD PTR _x_p12_x[rip]
	movss	DWORD PTR p12_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p7_saved_max[rip]
	movss	DWORD PTR p7_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	mov	BYTE PTR p11_l0[rip], al
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	mov	BYTE PTR p6_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed15[rip]
	movss	DWORD PTR proposed15[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed14[rip]
	movss	DWORD PTR proposed14[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed13[rip]
	movss	DWORD PTR proposed13[rip], xmm0
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	movss	DWORD PTR p1_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed5[rip]
	movss	DWORD PTR proposed5[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed4[rip]
	movss	DWORD PTR proposed4[rip], xmm0
	movzx	eax, BYTE PTR _x_turn4[rip]
	mov	BYTE PTR turn4[rip], al
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	movss	DWORD PTR max_prop[rip], xmm0
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	mov	BYTE PTR p18_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed2[rip]
	movss	DWORD PTR proposed2[rip], xmm0
	movzx	eax, BYTE PTR _x_turn2[rip]
	mov	BYTE PTR turn2[rip], al
	movss	xmm0, DWORD PTR _x_proposed11[rip]
	movss	DWORD PTR proposed11[rip], xmm0
	movzx	eax, BYTE PTR _x_id3[rip]
	mov	BYTE PTR id3[rip], al
	movzx	eax, BYTE PTR _x_turn3[rip]
	mov	BYTE PTR turn3[rip], al
	movss	xmm0, DWORD PTR _x_proposed3[rip]
	movss	DWORD PTR proposed3[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed12[rip]
	movss	DWORD PTR proposed12[rip], xmm0
	movzx	eax, BYTE PTR _x_id4[rip]
	mov	BYTE PTR id4[rip], al
	movss	xmm0, DWORD PTR _x_p13_x[rip]
	movss	DWORD PTR p13_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p8_saved_max[rip]
	movss	DWORD PTR p8_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed8[rip]
	movss	DWORD PTR proposed8[rip], xmm0
	movzx	eax, BYTE PTR _x_id0[rip]
	mov	BYTE PTR id0[rip], al
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	mov	BYTE PTR p6_l0[rip], al
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	mov	BYTE PTR p1_l1[rip], al
	movss	xmm0, DWORD PTR _x_p7_x[rip]
	movss	DWORD PTR p7_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p2_saved_max[rip]
	movss	DWORD PTR p2_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p18_x[rip]
	movss	DWORD PTR p18_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p13_saved_max[rip]
	movss	DWORD PTR p13_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed9[rip]
	movss	DWORD PTR proposed9[rip], xmm0
	movzx	eax, BYTE PTR _x_id1[rip]
	mov	BYTE PTR id1[rip], al
	movzx	eax, BYTE PTR _x_turn0[rip]
	mov	BYTE PTR turn0[rip], al
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	mov	BYTE PTR p13_l0[rip], al
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	mov	BYTE PTR p8_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed0[rip]
	movss	DWORD PTR proposed0[rip], xmm0
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	mov	BYTE PTR p18_l0[rip], al
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	mov	BYTE PTR p13_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed1[rip]
	movss	DWORD PTR proposed1[rip], xmm0
	movss	xmm0, DWORD PTR _x_p18_saved_max[rip]
	movss	DWORD PTR p18_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed10[rip]
	movss	DWORD PTR proposed10[rip], xmm0
	movzx	eax, BYTE PTR _x_id2[rip]
	mov	BYTE PTR id2[rip], al
	movzx	eax, BYTE PTR _x_turn1[rip]
	mov	BYTE PTR turn1[rip], al
	movss	xmm0, DWORD PTR _x_proposed16[rip]
	movss	DWORD PTR proposed16[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed17[rip]
	movss	DWORD PTR proposed17[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed18[rip]
	movss	DWORD PTR proposed18[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed19[rip]
	movss	DWORD PTR proposed19[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed20[rip]
	movss	DWORD PTR proposed20[rip], xmm0
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	movss	DWORD PTR p0_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	mov	BYTE PTR p3_l0[rip], al
	movss	xmm0, DWORD PTR _x_p4_x[rip]
	movss	DWORD PTR p4_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p0_saved_max[rip]
	movss	DWORD PTR p0_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	mov	BYTE PTR p8_l0[rip], al
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	mov	BYTE PTR p3_l1[rip], al
	movss	xmm0, DWORD PTR _x_p9_x[rip]
	movss	DWORD PTR p9_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p4_saved_max[rip]
	movss	DWORD PTR p4_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p11_x[rip]
	movss	DWORD PTR p11_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p6_saved_max[rip]
	movss	DWORD PTR p6_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	mov	BYTE PTR p0_l0[rip], al
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	mov	BYTE PTR p4_l0[rip], al
	movss	xmm0, DWORD PTR _x_p5_x[rip]
	movss	DWORD PTR p5_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p16_x[rip]
	movss	DWORD PTR p16_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p11_saved_max[rip]
	movss	DWORD PTR p11_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	mov	BYTE PTR p0_l1[rip], al
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	mov	BYTE PTR p9_l0[rip], al
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	mov	BYTE PTR p4_l1[rip], al
	movss	xmm0, DWORD PTR _x_p10_x[rip]
	movss	DWORD PTR p10_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p5_saved_max[rip]
	movss	DWORD PTR p5_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_inc_max_prop[rip]
	mov	BYTE PTR inc_max_prop[rip], al
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	mov	BYTE PTR p1_l0[rip], al
	movss	xmm0, DWORD PTR _x_p2_x[rip]
	movss	DWORD PTR p2_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	mov	BYTE PTR p2_l0[rip], al
	movss	xmm0, DWORD PTR _x_proposed6[rip]
	movss	DWORD PTR proposed6[rip], xmm0
	movss	xmm0, DWORD PTR _x_p3_x[rip]
	movss	DWORD PTR p3_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	mov	BYTE PTR p7_l0[rip], al
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	mov	BYTE PTR p2_l1[rip], al
	movss	xmm0, DWORD PTR _x_p8_x[rip]
	movss	DWORD PTR p8_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed7[rip]
	movss	DWORD PTR proposed7[rip], xmm0
	movss	xmm0, DWORD PTR _x_p3_saved_max[rip]
	movss	DWORD PTR p3_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	mov	BYTE PTR p5_l0[rip], al
	movss	xmm0, DWORD PTR _x_p1_saved_max[rip]
	movss	DWORD PTR p1_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p6_x[rip]
	movss	DWORD PTR p6_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	mov	BYTE PTR p10_l0[rip], al
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	mov	BYTE PTR p5_l1[rip], al
.L241:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L1092
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC2:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"99777.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	p20_l1,1,1
	.comm	_x_p20_l1,1,1
	.comm	p20_saved_max,4,4
	.comm	_x_p20_saved_max,4,4
	.comm	p19_l1,1,1
	.comm	_x_p19_l1,1,1
	.comm	p19_saved_max,4,4
	.comm	_x_p19_saved_max,4,4
	.comm	p17_l1,1,1
	.comm	_x_p17_l1,1,1
	.comm	p17_saved_max,4,4
	.comm	_x_p17_saved_max,4,4
	.comm	p16_l1,1,1
	.comm	_x_p16_l1,1,1
	.comm	p16_saved_max,4,4
	.comm	_x_p16_saved_max,4,4
	.comm	p20_l0,1,1
	.comm	_x_p20_l0,1,1
	.comm	p15_l1,1,1
	.comm	_x_p15_l1,1,1
	.comm	p20_x,4,4
	.comm	_x_p20_x,4,4
	.comm	p15_saved_max,4,4
	.comm	_x_p15_saved_max,4,4
	.comm	p19_l0,1,1
	.comm	_x_p19_l0,1,1
	.comm	p14_l1,1,1
	.comm	_x_p14_l1,1,1
	.comm	p19_x,4,4
	.comm	_x_p19_x,4,4
	.comm	p14_saved_max,4,4
	.comm	_x_p14_saved_max,4,4
	.comm	p17_l0,1,1
	.comm	_x_p17_l0,1,1
	.comm	p12_l1,1,1
	.comm	_x_p12_l1,1,1
	.comm	p17_x,4,4
	.comm	_x_p17_x,4,4
	.comm	p12_saved_max,4,4
	.comm	_x_p12_saved_max,4,4
	.comm	p16_l0,1,1
	.comm	_x_p16_l0,1,1
	.comm	p11_l1,1,1
	.comm	_x_p11_l1,1,1
	.comm	p15_l0,1,1
	.comm	_x_p15_l0,1,1
	.comm	p10_l1,1,1
	.comm	_x_p10_l1,1,1
	.comm	p15_x,4,4
	.comm	_x_p15_x,4,4
	.comm	p10_saved_max,4,4
	.comm	_x_p10_saved_max,4,4
	.comm	p14_l0,1,1
	.comm	_x_p14_l0,1,1
	.comm	p9_l1,1,1
	.comm	_x_p9_l1,1,1
	.comm	p14_x,4,4
	.comm	_x_p14_x,4,4
	.comm	p9_saved_max,4,4
	.comm	_x_p9_saved_max,4,4
	.comm	p12_l0,1,1
	.comm	_x_p12_l0,1,1
	.comm	p7_l1,1,1
	.comm	_x_p7_l1,1,1
	.comm	p12_x,4,4
	.comm	_x_p12_x,4,4
	.comm	p7_saved_max,4,4
	.comm	_x_p7_saved_max,4,4
	.comm	p11_l0,1,1
	.comm	_x_p11_l0,1,1
	.comm	p6_l1,1,1
	.comm	_x_p6_l1,1,1
	.comm	proposed15,4,4
	.comm	_x_proposed15,4,4
	.comm	proposed14,4,4
	.comm	_x_proposed14,4,4
	.comm	proposed13,4,4
	.comm	_x_proposed13,4,4
	.comm	p1_x,4,4
	.comm	_x_p1_x,4,4
	.comm	proposed5,4,4
	.comm	_x_proposed5,4,4
	.comm	proposed4,4,4
	.comm	_x_proposed4,4,4
	.comm	turn4,1,1
	.comm	_x_turn4,1,1
	.comm	max_prop,4,4
	.comm	_x_max_prop,4,4
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	p18_l1,1,1
	.comm	_x_p18_l1,1,1
	.comm	proposed2,4,4
	.comm	_x_proposed2,4,4
	.comm	turn2,1,1
	.comm	_x_turn2,1,1
	.comm	proposed11,4,4
	.comm	_x_proposed11,4,4
	.comm	id3,1,1
	.comm	_x_id3,1,1
	.comm	turn3,1,1
	.comm	_x_turn3,1,1
	.comm	proposed3,4,4
	.comm	_x_proposed3,4,4
	.comm	proposed12,4,4
	.comm	_x_proposed12,4,4
	.comm	id4,1,1
	.comm	_x_id4,1,1
	.comm	p13_x,4,4
	.comm	_x_p13_x,4,4
	.comm	p8_saved_max,4,4
	.comm	_x_p8_saved_max,4,4
	.comm	proposed8,4,4
	.comm	_x_proposed8,4,4
	.comm	id0,1,1
	.comm	_x_id0,1,1
	.comm	p6_l0,1,1
	.comm	_x_p6_l0,1,1
	.comm	p1_l1,1,1
	.comm	_x_p1_l1,1,1
	.comm	p7_x,4,4
	.comm	_x_p7_x,4,4
	.comm	p2_saved_max,4,4
	.comm	_x_p2_saved_max,4,4
	.comm	p18_x,4,4
	.comm	_x_p18_x,4,4
	.comm	p13_saved_max,4,4
	.comm	_x_p13_saved_max,4,4
	.comm	proposed9,4,4
	.comm	_x_proposed9,4,4
	.comm	id1,1,1
	.comm	_x_id1,1,1
	.comm	turn0,1,1
	.comm	_x_turn0,1,1
	.comm	p13_l0,1,1
	.comm	_x_p13_l0,1,1
	.comm	p8_l1,1,1
	.comm	_x_p8_l1,1,1
	.comm	proposed0,4,4
	.comm	_x_proposed0,4,4
	.comm	p18_l0,1,1
	.comm	_x_p18_l0,1,1
	.comm	p13_l1,1,1
	.comm	_x_p13_l1,1,1
	.comm	proposed1,4,4
	.comm	_x_proposed1,4,4
	.comm	p18_saved_max,4,4
	.comm	_x_p18_saved_max,4,4
	.comm	proposed10,4,4
	.comm	_x_proposed10,4,4
	.comm	id2,1,1
	.comm	_x_id2,1,1
	.comm	turn1,1,1
	.comm	_x_turn1,1,1
	.comm	proposed16,4,4
	.comm	_x_proposed16,4,4
	.comm	proposed17,4,4
	.comm	_x_proposed17,4,4
	.comm	proposed18,4,4
	.comm	_x_proposed18,4,4
	.comm	proposed19,4,4
	.comm	_x_proposed19,4,4
	.comm	proposed20,4,4
	.comm	_x_proposed20,4,4
	.comm	p0_x,4,4
	.comm	_x_p0_x,4,4
	.comm	p3_l0,1,1
	.comm	_x_p3_l0,1,1
	.comm	p4_x,4,4
	.comm	_x_p4_x,4,4
	.comm	p0_saved_max,4,4
	.comm	_x_p0_saved_max,4,4
	.comm	p8_l0,1,1
	.comm	_x_p8_l0,1,1
	.comm	p3_l1,1,1
	.comm	_x_p3_l1,1,1
	.comm	p9_x,4,4
	.comm	_x_p9_x,4,4
	.comm	p4_saved_max,4,4
	.comm	_x_p4_saved_max,4,4
	.comm	p11_x,4,4
	.comm	_x_p11_x,4,4
	.comm	p6_saved_max,4,4
	.comm	_x_p6_saved_max,4,4
	.comm	p0_l0,1,1
	.comm	_x_p0_l0,1,1
	.comm	p4_l0,1,1
	.comm	_x_p4_l0,1,1
	.comm	p5_x,4,4
	.comm	_x_p5_x,4,4
	.comm	p16_x,4,4
	.comm	_x_p16_x,4,4
	.comm	p11_saved_max,4,4
	.comm	_x_p11_saved_max,4,4
	.comm	p0_l1,1,1
	.comm	_x_p0_l1,1,1
	.comm	p9_l0,1,1
	.comm	_x_p9_l0,1,1
	.comm	p4_l1,1,1
	.comm	_x_p4_l1,1,1
	.comm	p10_x,4,4
	.comm	_x_p10_x,4,4
	.comm	p5_saved_max,4,4
	.comm	_x_p5_saved_max,4,4
	.comm	inc_max_prop,1,1
	.comm	_x_inc_max_prop,1,1
	.comm	p1_l0,1,1
	.comm	_x_p1_l0,1,1
	.comm	p2_x,4,4
	.comm	_x_p2_x,4,4
	.comm	p2_l0,1,1
	.comm	_x_p2_l0,1,1
	.comm	proposed6,4,4
	.comm	_x_proposed6,4,4
	.comm	p3_x,4,4
	.comm	_x_p3_x,4,4
	.comm	p7_l0,1,1
	.comm	_x_p7_l0,1,1
	.comm	p2_l1,1,1
	.comm	_x_p2_l1,1,1
	.comm	p8_x,4,4
	.comm	_x_p8_x,4,4
	.comm	proposed7,4,4
	.comm	_x_proposed7,4,4
	.comm	p3_saved_max,4,4
	.comm	_x_p3_saved_max,4,4
	.comm	p5_l0,1,1
	.comm	_x_p5_l0,1,1
	.comm	p1_saved_max,4,4
	.comm	_x_p1_saved_max,4,4
	.comm	p6_x,4,4
	.comm	_x_p6_x,4,4
	.comm	p10_l0,1,1
	.comm	_x_p10_l0,1,1
	.comm	p5_l1,1,1
	.comm	_x_p5_l1,1,1
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+8
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+16
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+24
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+32
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+36
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+44
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+48
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+60
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+64
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+76
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+80
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+88
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+100
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+104
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+320
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+416
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+468
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+360
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+456
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+488
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+300
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+324
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+344
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+112
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+508
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+116
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+496
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+124
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+132
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+384
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+148
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+364
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+340
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+436
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+444
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+492
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+460
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+164
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+168
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+336
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+424
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+448
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+180
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+188
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+192
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+404
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+204
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+208
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+212
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+216
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+220
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+224
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+228
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+232
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+236
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+452
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+420
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+244
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+380
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+476
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+524
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+504
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+252
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+376
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+432
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+520
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+400
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+500
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+260
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+268
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+484
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+276
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+472
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+280
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+440
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+464
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+284
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+516
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+288
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1331+480
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+412
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1331+512
	strb	r2, [r3]
	ldr	r3, .L1331+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L5
	ldr	r3, .L1331+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L5:
	ldr	r3, .L1331+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
	ldr	r3, .L1331+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L7:
	ldr	r3, .L1331+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1331+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L8:
	ldr	r3, .L1331+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L6:
	ldr	r3, .L1331+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+220
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L11
	mov	r3, #0
	mov	r4, r3
.L11:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L1331+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L1331+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L12:
	ldr	r3, .L1331+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L13
	ldr	r3, .L1331+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L13:
	ldr	r3, .L1331+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L1331+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L15:
	ldr	r3, .L1331+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L1331+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L16:
	ldr	r3, .L1331+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L14:
	ldr	r3, .L1331+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+216
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L19
	mov	r3, #0
	mov	r4, r3
.L19:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L1331+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L1331+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L20:
	ldr	r3, .L1331+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L21
	ldr	r3, .L1331+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L21:
	ldr	r3, .L1331+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
	ldr	r3, .L1331+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L23:
	ldr	r3, .L1331+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L1331+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L24:
	ldr	r3, .L1331+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L22:
	ldr	r3, .L1331+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+192
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+212
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
	mov	r3, #0
	mov	r4, r3
.L27:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+212
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L1331+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L1331+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L28:
	ldr	r3, .L1331+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L29
	ldr	r3, .L1331+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L29:
	ldr	r3, .L1331+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
	ldr	r3, .L1331+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L31:
	ldr	r3, .L1331+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L1331+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L32:
	ldr	r3, .L1331+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L30:
	ldr	r3, .L1331+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+208
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	mov	r3, #0
	mov	r4, r3
.L35:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+208
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L1331+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L1331+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L36:
	ldr	r3, .L1331+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L1331+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L37:
	ldr	r3, .L1331+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L1331+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L39:
	ldr	r3, .L1331+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L1331+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L40:
	ldr	r3, .L1331+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L38:
	ldr	r3, .L1331+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+204
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L43
	mov	r3, #0
	mov	r4, r3
.L43:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+204
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L1331+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L1331+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L44:
	ldr	r3, .L1331+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L45
	ldr	r3, .L1331+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
.L45:
	ldr	r3, .L1331+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
	ldr	r3, .L1331+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
.L47:
	ldr	r3, .L1331+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L1331+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	b	.L1332
.L1333:
	.align	2
.L1331:
	.word	_diverge_delta
	.word	p20_l1
	.word	p20_saved_max
	.word	p19_l1
	.word	p19_saved_max
	.word	p17_l1
	.word	p17_saved_max
	.word	p16_l1
	.word	p16_saved_max
	.word	p20_l0
	.word	p15_l1
	.word	p20_x
	.word	p15_saved_max
	.word	p19_l0
	.word	p14_l1
	.word	p19_x
	.word	p14_saved_max
	.word	p17_l0
	.word	p12_l1
	.word	p17_x
	.word	p12_saved_max
	.word	p16_l0
	.word	p11_l1
	.word	p15_l0
	.word	p10_l1
	.word	p15_x
	.word	p10_saved_max
	.word	p9_l1
	.word	p1_x
	.word	proposed4
	.word	turn4
	.word	delta
	.word	p18_l1
	.word	proposed2
	.word	turn2
	.word	id3
	.word	turn3
	.word	proposed3
	.word	id4
	.word	id0
	.word	p1_l1
	.word	p2_saved_max
	.word	p18_x
	.word	id1
	.word	turn0
	.word	proposed0
	.word	p18_l0
	.word	proposed1
	.word	p18_saved_max
	.word	id2
	.word	turn1
	.word	proposed16
	.word	proposed17
	.word	proposed18
	.word	proposed19
	.word	proposed20
	.word	p0_x
	.word	p3_l0
	.word	p4_x
	.word	p0_saved_max
	.word	p3_l1
	.word	p4_saved_max
	.word	p0_l0
	.word	p16_x
	.word	p0_l1
	.word	inc_max_prop
	.word	p1_l0
	.word	p2_x
	.word	p2_l0
	.word	p3_x
	.word	p2_l1
	.word	p3_saved_max
	.word	p1_saved_max
	.word	p15_saved_max
	.word	p15_x
	.word	proposed15
	.word	p15_l1
	.word	p15_l0
	.word	p14_l0
	.word	p14_saved_max
	.word	p14_x
	.word	proposed14
	.word	p14_l1
	.word	p14_l0
	.word	p13_saved_max
	.word	p13_x
	.word	proposed13
	.word	p13_l1
	.word	p13_l0
	.word	p12_saved_max
	.word	p12_x
	.word	proposed12
	.word	p12_l1
	.word	p12_l0
	.word	p11_saved_max
	.word	p11_x
	.word	proposed11
	.word	p11_l1
	.word	p11_l0
	.word	p10_saved_max
	.word	p10_x
	.word	proposed10
	.word	p10_l1
	.word	p10_l0
	.word	p9_saved_max
	.word	p9_x
	.word	proposed9
	.word	p9_l1
	.word	p9_l0
	.word	p8_saved_max
	.word	p8_x
	.word	proposed8
	.word	p8_l1
	.word	p8_l0
	.word	p7_saved_max
	.word	p7_x
	.word	proposed7
	.word	p7_l1
	.word	p7_l0
	.word	p6_saved_max
	.word	p6_x
	.word	proposed6
	.word	p6_l1
	.word	p6_l0
	.word	max_prop
	.word	p5_saved_max
	.word	p5_x
	.word	proposed5
	.word	p5_l1
	.word	p5_l0
	.word	p4_l1
	.word	p4_l0
.L1332:
	beq	.L46
.L48:
	ldr	r3, .L1331+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L46:
	ldr	r3, .L1331+296
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+292
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+300
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	mov	r3, #0
	mov	r4, r3
.L51:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+296
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+300
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L1331+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L1331+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L52:
	ldr	r3, .L1331+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L53
	ldr	r3, .L1331+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L53:
	ldr	r3, .L1331+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L1331+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L55:
	ldr	r3, .L1331+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L1331+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L56:
	ldr	r3, .L1331+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L54:
	ldr	r3, .L1331+320
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+316
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+324
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	mov	r3, #0
	mov	r4, r3
.L59:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+320
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L1331+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L1331+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L60:
	ldr	r3, .L1331+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L1331+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
.L61:
	ldr	r3, .L1331+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L1331+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
.L63:
	ldr	r3, .L1331+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L64
	ldr	r3, .L1331+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
.L64:
	ldr	r3, .L1331+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L62:
	ldr	r3, .L1331+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+336
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+344
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L67
	mov	r3, #0
	mov	r4, r3
.L67:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+340
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+344
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L68
	ldr	r3, .L1331+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L1331+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L68:
	ldr	r3, .L1331+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L69
	ldr	r3, .L1331+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L69:
	ldr	r3, .L1331+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
	ldr	r3, .L1331+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L71:
	ldr	r3, .L1331+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L1331+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L72:
	ldr	r3, .L1331+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L70:
	ldr	r3, .L1331+360
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+356
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+364
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L75
	mov	r3, #0
	mov	r4, r3
.L75:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+360
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+364
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L1331+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L1331+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L76:
	ldr	r3, .L1331+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L77
	ldr	r3, .L1331+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L77:
	ldr	r3, .L1331+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L1331+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L79:
	ldr	r3, .L1331+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L1331+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L80:
	ldr	r3, .L1331+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L78:
	ldr	r3, .L1331+380
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+376
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+384
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	mov	r3, #0
	mov	r4, r3
.L83:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+380
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+384
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L1331+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L1331+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L84:
	ldr	r3, .L1331+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L1331+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L85:
	ldr	r3, .L1331+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L1331+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L87:
	ldr	r3, .L1331+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L1331+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L88:
	ldr	r3, .L1331+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L86:
	ldr	r3, .L1331+400
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+396
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+404
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L91
	mov	r3, #0
	mov	r4, r3
.L91:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+400
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+404
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L92
	ldr	r3, .L1331+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L1331+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L92:
	ldr	r3, .L1331+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L93
	ldr	r3, .L1331+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
.L93:
	ldr	r3, .L1331+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L1331+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
.L95:
	ldr	r3, .L1331+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L1331+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
.L96:
	ldr	r3, .L1331+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L94:
	ldr	r3, .L1331+420
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+416
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+424
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L99
	mov	r3, #0
	mov	r4, r3
.L99:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+420
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+424
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L1331+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L1331+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L100:
	ldr	r3, .L1331+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L101
	ldr	r3, .L1331+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L101:
	ldr	r3, .L1331+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
	ldr	r3, .L1331+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L103:
	ldr	r3, .L1331+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L1331+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L104:
	ldr	r3, .L1331+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L102:
	ldr	r3, .L1331+440
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+436
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+444
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	mov	r3, #0
	mov	r4, r3
.L107:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+440
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+444
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L108
	ldr	r3, .L1331+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L1331+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L108:
	ldr	r3, .L1331+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
	ldr	r3, .L1331+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L109:
	ldr	r3, .L1331+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
	ldr	r3, .L1331+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L111:
	ldr	r3, .L1331+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L112
	ldr	r3, .L1331+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L112:
	ldr	r3, .L1331+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L110:
	ldr	r3, .L1331+460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+456
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+464
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L115
	mov	r3, #0
	mov	r4, r3
.L115:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+460
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+464
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L1331+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L1331+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L116:
	ldr	r3, .L1331+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L117
	ldr	r3, .L1331+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L117:
	ldr	r3, .L1331+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L1331+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L119:
	ldr	r3, .L1331+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L1331+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L120:
	ldr	r3, .L1331+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L118:
	ldr	r3, .L1331+480
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+476
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+484
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L123
	mov	r3, #0
	mov	r4, r3
.L123:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+480
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+484
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L1331+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L1331+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L124:
	ldr	r3, .L1331+516
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+516
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L125
	ldr	r3, .L1331+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
.L125:
	ldr	r3, .L1331+516
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
	ldr	r3, .L1331+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
.L127:
	ldr	r3, .L1331+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L1331+516
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
.L128:
	ldr	r3, .L1331+516
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L126:
	ldr	r3, .L1331+504
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+496
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+500
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+508
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	mov	r3, #0
	mov	r4, r3
.L131:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1331+504
	ldr	r3, [r3]	@ float
	ldr	r2, .L1331+508
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L1331+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L1331+516
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L132:
	ldr	r3, .L1331+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+520
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1331+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L133
	ldr	r3, .L1331+520
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L133:
	ldr	r3, .L1331+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L1331+520
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L135:
	ldr	r3, .L1331+520
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L1331+524
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L136:
	ldr	r3, .L1334
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L134:
	ldr	r3, .L1334+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+20
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L139
	mov	r3, #0
	mov	r4, r3
.L139:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L1334+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L1334
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L140:
	ldr	r3, .L1334+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L1334+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L141:
	ldr	r3, .L1334+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L1334+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L143:
	ldr	r3, .L1334+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L1334+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L144:
	ldr	r3, .L1334+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L142:
	ldr	r3, .L1334+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+144
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L147
	mov	r3, #0
	mov	r4, r3
.L147:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L1334+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L1334+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L148:
	ldr	r3, .L1334+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L1334+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L149:
	ldr	r3, .L1334+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L1334+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L151:
	ldr	r3, .L1334+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L1334+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L152:
	ldr	r3, .L1334+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L150:
	ldr	r3, .L1334+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+140
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	mov	r3, #0
	mov	r4, r3
.L155:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r3, .L1334+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L1334+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L156:
	ldr	r3, .L1334+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L157
	ldr	r3, .L1334+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L157:
	ldr	r3, .L1334+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L1334+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L159:
	ldr	r3, .L1334+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
	ldr	r3, .L1334+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L160:
	ldr	r3, .L1334+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L158:
	ldr	r3, .L1334+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+136
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L163
	mov	r3, #0
	mov	r4, r3
.L163:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L1334+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L1334+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L164:
	ldr	r3, .L1334+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L165
	ldr	r3, .L1334+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L165:
	ldr	r3, .L1334+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
	ldr	r3, .L1334+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L167:
	ldr	r3, .L1334+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L1334+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L168:
	ldr	r3, .L1334+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L166:
	ldr	r3, .L1334+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+132
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L171
	mov	r3, #0
	mov	r4, r3
.L171:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L1334+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L1334+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L172:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L173
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L173:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L175
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L175
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L175:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L176
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L176
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
.L176:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L177:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L178:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L179
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L179
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L179
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L179:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
.L180:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L181:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L182:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L183
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L183
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L183:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
.L184:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L185
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L185
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L185:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L186
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L186:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L187
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L187
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L187
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L187:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
.L188:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L189
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L189
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L189:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L190:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L191
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L191
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L191
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L191:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
.L192:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L193:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L194:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L174:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L195
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L195:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
.L197:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L198:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L199:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L200
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L200
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L200
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L200:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L201
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
.L201:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L202:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L203
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L1335
.L1336:
	.align	2
.L1334:
	.word	p4_l0
	.word	p4_l1
	.word	p4_x
	.word	max_prop
	.word	p4_saved_max
	.word	proposed4
	.word	p3_l0
	.word	p3_l1
	.word	p3_x
	.word	p3_saved_max
	.word	p2_l0
	.word	p2_l1
	.word	p2_x
	.word	p2_saved_max
	.word	p1_l0
	.word	p1_l1
	.word	p1_x
	.word	p1_saved_max
	.word	p0_l0
	.word	p0_l1
	.word	p0_x
	.word	p0_saved_max
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	id4
	.word	id3
	.word	id2
	.word	id0
	.word	id1
	.word	inc_max_prop
	.word	proposed0
	.word	proposed1
	.word	proposed2
	.word	proposed3
	.word	proposed4
	.word	proposed5
	.word	proposed6
	.word	proposed7
	.word	proposed8
	.word	proposed9
	.word	proposed10
	.word	proposed11
	.word	proposed12
	.word	proposed13
	.word	proposed14
	.word	proposed15
	.word	proposed16
	.word	proposed17
	.word	proposed18
	.word	proposed19
	.word	proposed20
	.word	max_prop
	.word	delta
	.word	_diverge_delta
	.word	_x__diverge_delta
	.word	_x_p20_l1
	.word	_x_p20_saved_max
	.word	_x_p19_l1
	.word	_x_p19_saved_max
	.word	_x_p17_l1
	.word	_x_p17_saved_max
	.word	_x_p16_l1
	.word	_x_p16_saved_max
	.word	_x_p20_l0
	.word	_x_p15_l1
	.word	_x_p20_x
	.word	_x_p15_saved_max
	.word	_x_p19_l0
	.word	_x_p14_l1
	.word	_x_p19_x
	.word	_x_p14_saved_max
	.word	_x_p17_l0
	.word	_x_p12_l1
	.word	_x_p17_x
	.word	_x_p12_saved_max
	.word	_x_p16_l0
	.word	_x_p11_l1
	.word	_x_p15_l0
	.word	_x_p10_l1
	.word	_x_p15_x
	.word	_x_p10_saved_max
	.word	_x_p14_l0
	.word	_x_p9_l1
	.word	_x_p14_x
	.word	_x_p9_saved_max
	.word	_x_p12_l0
	.word	_x_p7_l1
	.word	_x_p12_x
	.word	_x_p7_saved_max
	.word	_x_p11_l0
	.word	_x_p6_l1
	.word	_x_proposed15
	.word	_x_proposed14
	.word	_x_proposed13
	.word	_x_p1_x
	.word	_x_proposed5
	.word	_x_proposed4
	.word	_x_turn4
	.word	_x_max_prop
	.word	_x_delta
	.word	_x_p18_l1
	.word	_x_proposed2
	.word	_x_turn2
	.word	_x_proposed11
	.word	_x_id3
	.word	_x_turn3
	.word	_x_proposed3
	.word	_x_proposed12
	.word	_x_id4
	.word	_x_p13_x
	.word	_x_p8_saved_max
	.word	_x_proposed8
	.word	_x_id0
	.word	_x_p6_l0
	.word	_x_p1_l1
	.word	_x_p7_x
	.word	_x_p2_saved_max
	.word	_x_p18_x
.L1335:
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L203:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L204:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
.L205:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L206:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L207
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L207
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L207:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L208:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L209
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
.L209:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L210:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L211:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L212:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
.L213:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L214:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
.L215:
	ldr	r3, .L1334+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L196:
	ldr	r3, .L1334+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1334+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+200
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+204
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1334+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+200
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+204
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1334+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L238:
	ldr	r3, .L1334+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L1334+224
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L241
.L4:
	mov	r3, #0
.L241:
	str	r3, [fp, #-24]
	b	.L242
.L1011:
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+228
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+236
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+244
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+252
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+272
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+276
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+280
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+288
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+292
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+300
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+304
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+308
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+320
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+324
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+328
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+332
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+336
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+340
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+344
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+348
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+356
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+360
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+364
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+368
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+376
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+380
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+384
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+388
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+392
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+396
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+400
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+404
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+408
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+412
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+416
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+420
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+424
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+428
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+432
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+436
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+440
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+444
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+448
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+452
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+456
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+460
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+464
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1334+468
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+472
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+476
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1334+480
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+4
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+24
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+40
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+44
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+56
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+60
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+64
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+68
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+72
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+76
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+84
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+88
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+100
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+104
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+108
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+112
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+124
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+128
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+132
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+148
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+152
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+164
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+172
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+176
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+188
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+192
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+196
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+204
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1337+208
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1337+216
	strb	r2, [r3]
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
.L243:
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
.L245:
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
.L246:
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L244:
	ldr	r3, .L1337+72
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L248
	mov	r3, #0
	mov	r4, r3
.L248:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+228
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L249
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L249:
	ldr	r3, .L1337+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L250
	ldr	r3, .L1337+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L250
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1337+240
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1337+228
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L250
	ldr	r3, .L1337+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+248
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L250
	ldr	r3, .L1337+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L253
.L250:
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L253:
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L255
	ldr	r3, .L1337+228
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1337+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1337+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1337+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1337+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1337+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1337+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+248
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L258
.L255:
	ldr	r3, .L1337+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L1337+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L258
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L258
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L258:
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+248
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L1337+228
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L1337+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L1337+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L1337+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L263
.L260:
	ldr	r3, .L1337+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1337+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L263:
	ldr	r3, .L1337+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+248
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L268
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L268
	ldr	r3, .L1337+228
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L269
.L268:
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L1337+240
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L269
.L265:
	ldr	r3, .L1337+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L1337+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L269
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L269
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L269
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L269
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L269:
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+248
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L1337+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L1337+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L1337+240
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L1337+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L1337+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L1337+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+72
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L274
	mov	r3, #0
	mov	r4, r3
.L274:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L275
.L271:
	ldr	r3, .L1337+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L1337+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L275
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L275
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L275
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L275:
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
.L277:
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
.L279:
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
.L280:
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L278:
	ldr	r3, .L1337+68
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L281
	mov	r3, #0
	mov	r4, r3
.L281:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+276
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L282
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L282:
	ldr	r3, .L1337+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	b	.L1338
.L1339:
	.align	2
.L1337:
	.word	_x_p13_saved_max
	.word	_x_proposed9
	.word	_x_id1
	.word	_x_turn0
	.word	_x_p13_l0
	.word	_x_p8_l1
	.word	_x_proposed0
	.word	_x_p18_l0
	.word	_x_p13_l1
	.word	_x_proposed1
	.word	_x_p18_saved_max
	.word	_x_proposed10
	.word	_x_id2
	.word	_x_turn1
	.word	_x_proposed16
	.word	_x_proposed17
	.word	_x_proposed18
	.word	_x_proposed19
	.word	_x_proposed20
	.word	_x_p0_x
	.word	_x_p3_l0
	.word	_x_p4_x
	.word	_x_p0_saved_max
	.word	_x_p8_l0
	.word	_x_p3_l1
	.word	_x_p9_x
	.word	_x_p4_saved_max
	.word	_x_p11_x
	.word	_x_p6_saved_max
	.word	_x_p0_l0
	.word	_x_p4_l0
	.word	_x_p5_x
	.word	_x_p16_x
	.word	_x_p11_saved_max
	.word	_x_p0_l1
	.word	_x_p9_l0
	.word	_x_p4_l1
	.word	_x_p10_x
	.word	_x_p5_saved_max
	.word	_x_inc_max_prop
	.word	_x_p1_l0
	.word	_x_p2_x
	.word	_x_p2_l0
	.word	_x_proposed6
	.word	_x_p3_x
	.word	_x_p7_l0
	.word	_x_p2_l1
	.word	_x_p8_x
	.word	_x_proposed7
	.word	_x_p3_saved_max
	.word	_x_p5_l0
	.word	_x_p1_saved_max
	.word	_x_p6_x
	.word	_x_p10_l0
	.word	_x_p5_l1
	.word	_x_p20_l0
	.word	_x_p20_l1
	.word	_x_p20_x
	.word	p20_l0
	.word	p20_l1
	.word	p20_x
	.word	p20_saved_max
	.word	_x_p20_saved_max
	.word	proposed20
	.word	p19_saved_max
	.word	_x_p19_saved_max
	.word	_x_p19_l0
	.word	_x_p19_l1
	.word	p19_x
	.word	_x_p19_x
	.word	proposed19
	.word	_x_proposed19
	.word	p19_l0
	.word	p19_l1
	.word	p18_x
	.word	p18_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	turn3
	.word	turn2
	.word	turn1
	.word	turn0
	.word	delta
	.word	max_prop
	.word	_x_p18_saved_max
	.word	_x_p18_l0
	.word	_x_p18_l1
	.word	_x_p18_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id1
	.word	_x_id0
	.word	proposed18
	.word	_x_proposed18
	.word	p18_l1
	.word	p18_l0
	.word	turn4
.L1338:
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L1337+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1337+272
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1337+276
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L1337+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+260
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L283
	ldr	r3, .L1337+280
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+284
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L286
.L283:
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L286:
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L288
	ldr	r3, .L1337+276
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1337+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1337+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1337+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1337+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1337+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1337+280
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+284
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L288
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+260
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L291
.L288:
	ldr	r3, .L1337+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L1337+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L291:
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+260
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1337+276
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1337+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L1337+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
	ldr	r3, .L1337+280
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+284
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L296
.L293:
	ldr	r3, .L1337+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L1337+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L296
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L296
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L296
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L296
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L296:
	ldr	r3, .L1337+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+280
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+284
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+260
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L301
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L301
	ldr	r3, .L1337+276
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L301:
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L298
	ldr	r3, .L1337+272
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+276
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L298:
	ldr	r3, .L1337+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1337+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L302:
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+260
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L1337+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L1337+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L1337+272
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+276
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L1337+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L1337+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L1337+280
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+284
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L307
	mov	r3, #0
	mov	r4, r3
.L307:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L308
.L304:
	ldr	r3, .L1337+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
	ldr	r3, .L1337+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L308
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L308
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L308
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L308:
	ldr	r3, .L1337+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L1337+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
.L310:
	ldr	r3, .L1337+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L1337+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
.L312:
	ldr	r3, .L1337+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L1337+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L311
.L313:
	ldr	r3, .L1337+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L311:
	ldr	r3, .L1337+388
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L314
	mov	r3, #0
	mov	r4, r3
.L314:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+360
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+388
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L1337+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L1337+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L315:
	ldr	r3, .L1337+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L1337+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1337+296
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1337+360
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L1337+300
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+348
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L1337+384
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+388
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L319
.L316:
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L319:
	ldr	r3, .L1337+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1337+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L321
	ldr	r3, .L1337+360
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1337+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1337+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1337+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1337+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1337+320
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1337+384
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+388
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L321
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+348
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L324
.L321:
	ldr	r3, .L1337+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1337+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L1337+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1337+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1337+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L1337+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1337+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L324:
	ldr	r3, .L1337+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+348
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1337+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1337+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1337+360
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1337+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1337+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1337+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1337+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1337+380
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1337+384
	ldr	r3, [r3]	@ float
	ldr	r2, .L1337+388
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L329
.L326:
	ldr	r3, .L1337+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L1337+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L1337+400
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L1340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L1340+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L1340+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L1340+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L329:
	ldr	r3, .L1340+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L334
	ldr	r3, .L1340+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L334
	ldr	r3, .L1340+56
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L335
.L334:
	ldr	r3, .L1340+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L1340+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L335
.L331:
	ldr	r3, .L1340+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L335
	ldr	r3, .L1340+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L335
	ldr	r3, .L1340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L1340+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L1340+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L335
	ldr	r3, .L1340+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L335:
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1340+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L1340+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L1340+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1340+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1340+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L1340+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+40
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L340
	mov	r3, #0
	mov	r4, r3
.L340:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L341
.L337:
	ldr	r3, .L1340+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L1340+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L1340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L341
	ldr	r3, .L1340+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L341
	ldr	r3, .L1340+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L1340+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L341
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L341:
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L343
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
.L343:
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L345
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
.L345:
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
.L346:
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L344:
	ldr	r3, .L1340+80
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L347
	mov	r3, #0
	mov	r4, r3
.L347:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L348:
	ldr	r3, .L1340+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L1340+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1340+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1340+84
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L1340+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L1340+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L352
.L349:
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1340+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1340+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L352:
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L354
	ldr	r3, .L1340+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1340+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1340+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1340+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1340+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1340+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1340+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L357
.L354:
	ldr	r3, .L1340+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1340+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1340+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1340+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1340+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L357:
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1340+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1340+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1340+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1340+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L362
.L359:
	ldr	r3, .L1340+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L1340+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L1340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L1340+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L1340+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L1340+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L362
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L362:
	ldr	r3, .L1340+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L367
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L367
	ldr	r3, .L1340+84
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L368
.L367:
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
	ldr	r3, .L1340+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L368
.L364:
	ldr	r3, .L1340+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L1340+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L368
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L1340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L368
	ldr	r3, .L1340+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L368
	ldr	r3, .L1340+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L1340+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L368
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L368:
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L1340+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L1340+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L1340+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L1340+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L1340+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L1340+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+80
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L373
	mov	r3, #0
	mov	r4, r3
.L373:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L374
.L370:
	ldr	r3, .L1340+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L1340+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L1340
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L374
	ldr	r3, .L1340+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L374
	ldr	r3, .L1340+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L1340+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L374
	ldr	r3, .L1340+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L374:
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L376
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
.L376:
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L378
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
.L378:
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
.L379:
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L1341
.L1342:
	.align	2
.L1340:
	.word	turn3
	.word	turn2
	.word	turn1
	.word	turn0
	.word	delta
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
	.word	proposed18
	.word	_x_proposed18
	.word	_x_p18_saved_max
	.word	_x_p18_l0
	.word	_x_p18_l1
	.word	_x_p18_x
	.word	p18_x
	.word	p18_l0
	.word	p18_l1
	.word	_x_p17_l0
	.word	_x_p17_l1
	.word	_x_proposed17
	.word	_x_p17_x
	.word	p17_l0
	.word	p17_l1
	.word	p17_x
	.word	p17_saved_max
	.word	_x_p17_saved_max
	.word	proposed17
	.word	p16_saved_max
	.word	id2
	.word	_x_p16_saved_max
	.word	_x_p16_l0
	.word	_x_p16_l1
	.word	p16_x
	.word	_x_p16_x
	.word	_x_id2
	.word	proposed16
	.word	_x_proposed16
	.word	p16_l0
	.word	p16_l1
	.word	p15_x
	.word	p15_saved_max
	.word	_x_p15_l1
	.word	_x_p15_x
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
	.word	id2
	.word	_x_id2
	.word	id3
	.word	_x_id3
	.word	id4
	.word	_x_id4
	.word	proposed15
	.word	_x_proposed15
	.word	p15_l0
	.word	p15_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	delta
	.word	max_prop
	.word	_x_p15_saved_max
	.word	_x_p15_l0
.L1341:
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L377:
	ldr	r3, .L1340+148
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L380
	mov	r3, #0
	mov	r4, r3
.L380:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L381
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L381:
	ldr	r3, .L1340+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L1340+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1340+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1340+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L1340+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L1340+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L385
.L382:
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1340+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1340+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L385:
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L387
	ldr	r3, .L1340+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1340+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1340+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1340+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1340+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1340+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L390
.L387:
	ldr	r3, .L1340+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1340+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1340+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1340+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1340+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L390:
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1340+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1340+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1340+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L395
.L392:
	ldr	r3, .L1340+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L1340+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L395
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L1340+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L395
	ldr	r3, .L1340+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L395
	ldr	r3, .L1340+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L395
	ldr	r3, .L1340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L395
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L395:
	ldr	r3, .L1340+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L400
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L400
	ldr	r3, .L1340+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L401
.L400:
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L397
	ldr	r3, .L1340+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L401
.L397:
	ldr	r3, .L1340+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L1340+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L401
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L1340+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L401
	ldr	r3, .L1340+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L401
	ldr	r3, .L1340+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L401
	ldr	r3, .L1340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L401
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L401:
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L1340+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L403
	ldr	r3, .L1340+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L403
	ldr	r3, .L1340+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L403
	ldr	r3, .L1340+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L1340+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L1340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L403
	ldr	r3, .L1340+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+148
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L406
	mov	r3, #0
	mov	r4, r3
.L406:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L407
.L403:
	ldr	r3, .L1340+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L1340+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L1340+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L407
	ldr	r3, .L1340+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L407
	ldr	r3, .L1340+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L407
	ldr	r3, .L1340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L407
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L407:
	ldr	r3, .L1340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L409
	ldr	r3, .L1340+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L410
.L409:
	ldr	r3, .L1340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L411
	ldr	r3, .L1340+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L410
.L411:
	ldr	r3, .L1340+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L1340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L410
.L412:
	ldr	r3, .L1340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L410:
	ldr	r3, .L1340+220
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L413
	mov	r3, #0
	mov	r4, r3
.L413:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1340+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L414:
	ldr	r3, .L1340+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L415
	ldr	r3, .L1340+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L415
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1340+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1340+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L415
	ldr	r3, .L1340+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+260
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L415
	ldr	r3, .L1340+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L418
.L415:
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1340+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L418:
	ldr	r3, .L1340+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L420
	ldr	r3, .L1340+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1340+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1340+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1340+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1340+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1340+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1340+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1340+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+260
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L423
.L420:
	ldr	r3, .L1340+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
	ldr	r3, .L1340+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
	ldr	r3, .L1340+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
	ldr	r3, .L1340+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L1340+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L1340+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L1340+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L1340+252
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L423:
	ldr	r3, .L1340+256
	ldr	r3, [r3]	@ float
	ldr	r2, .L1340+260
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1340+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1343
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L1343+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1343+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L1343+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1343+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1343+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1343+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1343+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L428
.L425:
	ldr	r3, .L1343+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L1343+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L428
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L428
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L428:
	ldr	r3, .L1343+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L433
	ldr	r3, .L1343
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L433
	ldr	r3, .L1343+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L434
.L433:
	ldr	r3, .L1343+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L430
	ldr	r3, .L1343+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L434
.L430:
	ldr	r3, .L1343+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L1343+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L434
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L434
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L434:
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L1343+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L436
	ldr	r3, .L1343
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L436
	ldr	r3, .L1343+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L1343+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L1343+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L436
	ldr	r3, .L1343+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L1343+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L1343+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L436
	ldr	r3, .L1343+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+32
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L439
	mov	r3, #0
	mov	r4, r3
.L439:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L440
.L436:
	ldr	r3, .L1343+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1343+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L440
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L440:
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L442
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
.L442:
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L444
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
.L444:
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
.L445:
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L443:
	ldr	r3, .L1343+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L446
	mov	r3, #0
	mov	r4, r3
.L446:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L447
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L447:
	ldr	r3, .L1343+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L448
	ldr	r3, .L1343+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L448
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1343+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1343+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L448
	ldr	r3, .L1343+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L448
	ldr	r3, .L1343+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L451
.L448:
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L451:
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L453
	ldr	r3, .L1343+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1343+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1343+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1343+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1343+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1343+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1343+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L456
.L453:
	ldr	r3, .L1343+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1343+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L456:
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L1343+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1343+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L1343+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1343+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1343+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1343+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L1343+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L461
.L458:
	ldr	r3, .L1343+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L461
	ldr	r3, .L1343+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L461
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L461
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L461
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L461
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L461
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L461
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L461:
	ldr	r3, .L1343+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L466
	ldr	r3, .L1343+68
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L467
.L466:
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L463
	ldr	r3, .L1343+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L467
.L463:
	ldr	r3, .L1343+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1343+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L467:
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L1343+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L469
	ldr	r3, .L1343+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L469
	ldr	r3, .L1343+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L1343+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L1343+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L469
	ldr	r3, .L1343+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L1343+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L1343+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L469
	ldr	r3, .L1343+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+64
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L472
	mov	r3, #0
	mov	r4, r3
.L472:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L473
.L469:
	ldr	r3, .L1343+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L1343+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L473
	b	.L1344
.L1345:
	.align	2
.L1343:
	.word	_x_p15_l1
	.word	_x_p15_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id0
	.word	_x_id1
	.word	proposed15
	.word	_x_proposed15
	.word	p15_l1
	.word	p15_l0
	.word	_x_p15_saved_max
	.word	_x_p15_l0
	.word	p15_x
	.word	_x_p14_l0
	.word	_x_p14_l1
	.word	_x_proposed14
	.word	_x_p14_x
	.word	p14_l0
	.word	p14_l1
	.word	p14_x
	.word	p14_saved_max
	.word	_x_p14_saved_max
	.word	proposed14
	.word	p13_saved_max
	.word	turn4
	.word	_x_p13_saved_max
	.word	_x_p13_l0
	.word	_x_p13_l1
	.word	p13_x
	.word	_x_p13_x
	.word	proposed13
	.word	_x_proposed13
	.word	p13_l0
	.word	p13_l1
	.word	turn3
	.word	turn2
	.word	turn0
	.word	p12_l0
	.word	p12_l1
	.word	p12_x
	.word	p12_saved_max
	.word	delta
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	_x_p12_l1
	.word	_x_p12_l0
	.word	_x_p12_x
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
	.word	id2
	.word	_x_id2
	.word	id3
	.word	_x_id3
	.word	id4
	.word	_x_id4
	.word	proposed12
	.word	_x_proposed12
	.word	max_prop
	.word	_x_p12_saved_max
.L1344:
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L473
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L473
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L473
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L473:
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L475
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
.L475:
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L477
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
.L477:
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L478
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L476
.L478:
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L476:
	ldr	r3, .L1343+128
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L479
	mov	r3, #0
	mov	r4, r3
.L479:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L480:
	ldr	r3, .L1343+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L1343+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1343+116
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1343+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L1343+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L1343+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L484
.L481:
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L484:
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L486
	ldr	r3, .L1343+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1343+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1343+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1343+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1343+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1343+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1343+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L486
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L489
.L486:
	ldr	r3, .L1343+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1343+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1343+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L489:
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L1343+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1343+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L1343+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1343+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1343+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1343+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L1343+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L494
.L491:
	ldr	r3, .L1343+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1343+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L494
	ldr	r3, .L1343+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L494
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L494
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L494:
	ldr	r3, .L1343+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L499
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L499
	ldr	r3, .L1343+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L500
.L499:
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L496
	ldr	r3, .L1343+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L500
.L496:
	ldr	r3, .L1343+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L500
	ldr	r3, .L1343+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L500
	ldr	r3, .L1343+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L500
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L500
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L500
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L500
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L500
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L500:
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1343+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L1343+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L1343+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1343+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1343+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L1343+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1343+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1343+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L1343+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+128
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L505
	mov	r3, #0
	mov	r4, r3
.L505:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L506
.L502:
	ldr	r3, .L1343+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L1343+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L1343+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L506
	ldr	r3, .L1343+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L1343+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L1343+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L506
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L506:
	ldr	r3, .L1343+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L508
	ldr	r3, .L1343+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
.L508:
	ldr	r3, .L1343+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L510
	ldr	r3, .L1343+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
.L510:
	ldr	r3, .L1343+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L511
	ldr	r3, .L1343+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
.L511:
	ldr	r3, .L1343+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L509:
	ldr	r3, .L1343+248
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L512
	mov	r3, #0
	mov	r4, r3
.L512:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+200
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+248
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L513
	ldr	r3, .L1343+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1343+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L513:
	ldr	r3, .L1343+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L1343+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1343+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1343+200
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L1343+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+256
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L514
	ldr	r3, .L1343+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+248
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L517
.L514:
	ldr	r3, .L1343+168
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1343+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1343+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1343+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L517:
	ldr	r3, .L1343+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1343+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L519
	ldr	r3, .L1343+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1343+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1343+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1343+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1343+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1343+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1343+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1343+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+248
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L1343+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1343+256
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L522
.L519:
	ldr	r3, .L1346
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1346+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1346+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1346+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L1346+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L1346+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1346+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L522:
	ldr	r3, .L1346+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1346+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1346+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1346+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1346+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L527
.L524:
	ldr	r3, .L1346+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L1346
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L527
	ldr	r3, .L1346+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L527
	ldr	r3, .L1346+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L1346+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L1346+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L527
	ldr	r3, .L1346+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L527
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L527:
	ldr	r3, .L1346+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L532
	ldr	r3, .L1346+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L532
	ldr	r3, .L1346+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L533
.L532:
	ldr	r3, .L1346+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L1346+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L533
.L529:
	ldr	r3, .L1346
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L533
	ldr	r3, .L1346+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L533
	ldr	r3, .L1346+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L533
	ldr	r3, .L1346+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L533
	ldr	r3, .L1346+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L533
	ldr	r3, .L1346+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L533
	ldr	r3, .L1346+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L533
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L533:
	ldr	r3, .L1346+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1346+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L1346+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L1346+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L1346+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+56
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L538
	mov	r3, #0
	mov	r4, r3
.L538:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L539
.L535:
	ldr	r3, .L1346
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L1346+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L1346+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L1346+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L1346+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
	ldr	r3, .L1346+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L1346+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L539
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L539:
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L541
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
.L541:
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L543
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
.L543:
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L542
.L544:
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L542:
	ldr	r3, .L1346+92
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L545
	mov	r3, #0
	mov	r4, r3
.L545:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L546
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L546:
	ldr	r3, .L1346+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L547
	ldr	r3, .L1346+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L547
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1346+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1346+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L547
	ldr	r3, .L1346+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L547
	ldr	r3, .L1346+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L550
.L547:
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1346+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1346+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L550:
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L1346+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1346+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1346+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1346+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1346+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1346+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1346+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L1346+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L555
.L552:
	ldr	r3, .L1346+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1346+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1346+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1346+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L1346+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1346+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L1346+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L555:
	ldr	r3, .L1346+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1346+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1346+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L560
.L557:
	ldr	r3, .L1346+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L1346+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
	ldr	r3, .L1346+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
	ldr	r3, .L1346+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L1346+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
	ldr	r3, .L1346+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L1346+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L560:
	ldr	r3, .L1346+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L565
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L565
	ldr	r3, .L1346+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L566
.L565:
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L1346+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L566
.L562:
	ldr	r3, .L1346+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L1346+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L1346+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L1346+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L1346+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L566
	ldr	r3, .L1346+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L1346+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L1346+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L566:
	ldr	r3, .L1346+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L1346+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L1346+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L1346+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	b	.L1347
.L1348:
	.align	2
.L1346:
	.word	p12_l0
	.word	p12_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	delta
	.word	max_prop
	.word	_x_p12_saved_max
	.word	_x_p12_l0
	.word	_x_p12_l1
	.word	_x_p12_x
	.word	proposed12
	.word	_x_proposed12
	.word	p12_x
	.word	_x_p11_l0
	.word	_x_p11_l1
	.word	_x_p11_x
	.word	p11_x
	.word	p11_saved_max
	.word	_x_p11_saved_max
	.word	proposed11
	.word	_x_proposed11
	.word	p11_l0
	.word	p11_l1
	.word	p10_saved_max
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p10_saved_max
	.word	_x_p10_l0
	.word	_x_p10_l1
	.word	p10_x
	.word	_x_p10_x
	.word	_x_id4
	.word	_x_id3
	.word	proposed10
	.word	_x_proposed10
	.word	p10_l0
	.word	p10_l1
	.word	p9_l0
	.word	p9_l1
	.word	p9_x
	.word	p9_saved_max
	.word	_x_p9_saved_max
	.word	proposed9
	.word	_x_proposed9
	.word	delta
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	_x_p9_l1
	.word	_x_p9_l0
	.word	_x_p9_x
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
	.word	id2
	.word	_x_id2
.L1347:
	mov	r3, r0
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L1346+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+92
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L571
	mov	r3, #0
	mov	r4, r3
.L571:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L572
.L568:
	ldr	r3, .L1346+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L1346+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L1346+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L572
	ldr	r3, .L1346+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L1346+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L572
	ldr	r3, .L1346+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L1346+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L572
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L572:
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L574
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
.L574:
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L576
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
.L576:
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L575
.L577:
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L575:
	ldr	r3, .L1346+152
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L578
	mov	r3, #0
	mov	r4, r3
.L578:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L579:
	ldr	r3, .L1346+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L1346+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1346+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1346+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L1346+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L580
	ldr	r3, .L1346+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L583
.L580:
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1346+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1346+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L583:
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L585
	ldr	r3, .L1346+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1346+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1346+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1346+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1346+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1346+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1346+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L1346+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L588
.L585:
	ldr	r3, .L1346+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1346+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1346+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1346+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1346+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1346+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1346+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L588:
	ldr	r3, .L1346+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1346+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1346+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L593
.L590:
	ldr	r3, .L1346+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L593
	ldr	r3, .L1346+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L1346+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L1346+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L593
	ldr	r3, .L1346+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L1346+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L593
	ldr	r3, .L1346+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L593
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L593:
	ldr	r3, .L1346+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+152
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L598
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L598
	ldr	r3, .L1346+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L599
.L598:
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L1346+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L599
.L595:
	ldr	r3, .L1346+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1346+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L599
	ldr	r3, .L1346+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L599
	ldr	r3, .L1346+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1346+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L599
	ldr	r3, .L1346+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1346+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L599
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L599:
	ldr	r3, .L1346+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L601
	ldr	r3, .L1346+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L601
	ldr	r3, .L1346+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L601
	ldr	r3, .L1346+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L601
	ldr	r3, .L1346+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
	ldr	r3, .L1346+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L601
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L601
	ldr	r3, .L1346+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+152
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L604
	mov	r3, #0
	mov	r4, r3
.L604:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L605
.L601:
	ldr	r3, .L1346+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L605
	ldr	r3, .L1346+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L605
	ldr	r3, .L1346+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L605
	ldr	r3, .L1346+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L605
	ldr	r3, .L1346+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L605
	ldr	r3, .L1346+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L605
	ldr	r3, .L1346+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L605
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L605:
	ldr	r3, .L1346+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L607
	ldr	r3, .L1346+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L608
.L607:
	ldr	r3, .L1346+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L609
	ldr	r3, .L1346+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L608
.L609:
	ldr	r3, .L1346+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L610
	ldr	r3, .L1346+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L608
.L610:
	ldr	r3, .L1346+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L608:
	ldr	r3, .L1346+188
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L611
	mov	r3, #0
	mov	r4, r3
.L611:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+188
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1346+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L1346+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L612:
	ldr	r3, .L1346+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L1346+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1346+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1346+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L1346+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+180
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L613
	ldr	r3, .L1346+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L1346+188
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L616
.L613:
	ldr	r3, .L1346+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1346+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1346+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1346+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L616:
	ldr	r3, .L1346+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1346+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L618
	ldr	r3, .L1346+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1346+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1346+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1346+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1346+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1349
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1349+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1349+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L618
	ldr	r3, .L1349+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L621
.L618:
	ldr	r3, .L1349+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1349+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L621:
	ldr	r3, .L1349+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1349+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1349+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L623
	ldr	r3, .L1349+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1349+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L623
	ldr	r3, .L1349+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L623
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L623
	ldr	r3, .L1349+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L626
.L623:
	ldr	r3, .L1349+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1349+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L626
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L626
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L626:
	ldr	r3, .L1349+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L631
	ldr	r3, .L1349+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L631
	ldr	r3, .L1349+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L632
.L631:
	ldr	r3, .L1349+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L1349+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L632
.L628:
	ldr	r3, .L1349+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L1349+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L632
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L632
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L632
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L632
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L632:
	ldr	r3, .L1349+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L1349+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L1349+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L1349+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L1349+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L1349+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L1349+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+20
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L637
	mov	r3, #0
	mov	r4, r3
.L637:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L638
.L634:
	ldr	r3, .L1349+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L638
	ldr	r3, .L1349+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L638
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L638
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L638
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L638
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L638
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L638
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L638:
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L640
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
.L640:
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L642
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
.L642:
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
.L643:
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L641:
	ldr	r3, .L1349+84
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L644
	mov	r3, #0
	mov	r4, r3
.L644:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L645
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L645:
	ldr	r3, .L1349+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L646
	ldr	r3, .L1349+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L646
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1349+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1349+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L646
	ldr	r3, .L1349+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L646
	ldr	r3, .L1349+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L649
.L646:
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L649:
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L651
	ldr	r3, .L1349+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1349+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1349+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1349+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1349
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1349+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1349+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L651
	ldr	r3, .L1349+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L654
.L651:
	ldr	r3, .L1349+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1349+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L654:
	ldr	r3, .L1349+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1349+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1349+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1349+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1349+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L659
.L656:
	ldr	r3, .L1349+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L659
	ldr	r3, .L1349+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L659
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L659:
	ldr	r3, .L1349+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L664
	ldr	r3, .L1349+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L665
.L664:
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L661
	ldr	r3, .L1349+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L665
.L661:
	ldr	r3, .L1349+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L665
	ldr	r3, .L1349+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L665
	b	.L1350
.L1351:
	.align	2
.L1349:
	.word	id3
	.word	_x_id3
	.word	id4
	.word	_x_id4
	.word	proposed9
	.word	_x_proposed9
	.word	_x_p9_saved_max
	.word	p9_l0
	.word	p9_l1
	.word	_x_p9_l0
	.word	_x_p9_l1
	.word	_x_p9_x
	.word	p9_x
	.word	p8_saved_max
	.word	max_prop
	.word	_x_p8_saved_max
	.word	_x_p8_l0
	.word	_x_p8_l1
	.word	p8_x
	.word	_x_p8_x
	.word	proposed8
	.word	_x_proposed8
	.word	p8_l0
	.word	p8_l1
	.word	p7_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p7_saved_max
	.word	_x_p7_l0
	.word	_x_p7_l1
	.word	p7_x
	.word	_x_p7_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id0
	.word	_x_id1
	.word	proposed7
	.word	_x_proposed7
	.word	p7_l0
	.word	p7_l1
	.word	p6_l0
	.word	p6_l1
	.word	p6_x
	.word	_x_p6_x
	.word	p6_saved_max
	.word	_x_p6_saved_max
	.word	proposed6
	.word	_x_proposed6
	.word	delta
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn1
	.word	turn0
	.word	_x_p6_l1
	.word	_x_p6_l0
.L1350:
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L665
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L665
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L665
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L665
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L665
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L665:
	ldr	r3, .L1349+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1349+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L667
	ldr	r3, .L1349+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L667
	ldr	r3, .L1349+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1349+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1349+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L667
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L667
	ldr	r3, .L1349+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+84
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L670
	mov	r3, #0
	mov	r4, r3
.L670:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L671
.L667:
	ldr	r3, .L1349+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1349+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L671:
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L673
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L674
.L673:
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L675
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L674
.L675:
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L674
.L676:
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L674:
	ldr	r3, .L1349+168
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L677
	mov	r3, #0
	mov	r4, r3
.L677:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L678
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L678:
	ldr	r3, .L1349+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L679
	ldr	r3, .L1349+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L679
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1349+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1349+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L679
	ldr	r3, .L1349+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L679
	ldr	r3, .L1349+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L682
.L679:
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L682:
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L684
	ldr	r3, .L1349+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1349+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1349+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1349+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1349+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1349+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1349+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L1349+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L687
.L684:
	ldr	r3, .L1349+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L1349+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L687:
	ldr	r3, .L1349+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1349+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1349+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1349+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1349+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L692
.L689:
	ldr	r3, .L1349+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
	ldr	r3, .L1349+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L692
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L692
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L692
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L692:
	ldr	r3, .L1349+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+168
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L697
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L697
	ldr	r3, .L1349+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L698
.L697:
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L1349+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L698
.L694:
	ldr	r3, .L1349+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1349+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L698
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L698
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L698
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L698:
	ldr	r3, .L1349+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L700
	ldr	r3, .L1349+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L1349+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L1349+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L700
	ldr	r3, .L1349+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L700
	ldr	r3, .L1349+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L1349+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L700
	ldr	r3, .L1349+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L700
	ldr	r3, .L1349+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L1349+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+168
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L703
	mov	r3, #0
	mov	r4, r3
.L703:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L704
.L700:
	ldr	r3, .L1349+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L704
	ldr	r3, .L1349+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L704
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L704
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L704
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L704
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L704
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L704
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L704:
	ldr	r3, .L1349+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L706
	ldr	r3, .L1349+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
.L706:
	ldr	r3, .L1349+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L708
	ldr	r3, .L1349+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
.L708:
	ldr	r3, .L1349+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L709
	ldr	r3, .L1349+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
.L709:
	ldr	r3, .L1349+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L707:
	ldr	r3, .L1349+208
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L710
	mov	r3, #0
	mov	r4, r3
.L710:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+208
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L711
	ldr	r3, .L1349+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1349+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L711:
	ldr	r3, .L1349+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L1349+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1349+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1349+188
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1349+192
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L1349+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+200
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L1349+204
	ldr	r3, [r3]	@ float
	ldr	r2, .L1349+208
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L715
.L712:
	ldr	r3, .L1349+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1349+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1349+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1349+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L715:
	ldr	r3, .L1349+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1349+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L717
	ldr	r3, .L1352
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1352+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1352+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1352+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1352+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1352+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1352+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L720
.L717:
	ldr	r3, .L1352+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1352+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L720:
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1352+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1352+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1352
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1352+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1352+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1352+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1352+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L725
.L722:
	ldr	r3, .L1352+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L725
	ldr	r3, .L1352+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L725
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L725
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L725:
	ldr	r3, .L1352+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L730
	ldr	r3, .L1352+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L730
	ldr	r3, .L1352
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L731
.L730:
	ldr	r3, .L1352+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L727
	ldr	r3, .L1352+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L731
.L727:
	ldr	r3, .L1352+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L1352+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L731
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L731
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L731
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L731
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L731:
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L733
	ldr	r3, .L1352+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L733
	ldr	r3, .L1352+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L733
	ldr	r3, .L1352+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L733
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L733
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L733
	ldr	r3, .L1352+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L733
	ldr	r3, .L1352+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L733
	ldr	r3, .L1352+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L733
	ldr	r3, .L1352+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+28
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L736
	mov	r3, #0
	mov	r4, r3
.L736:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L737
.L733:
	ldr	r3, .L1352+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L737
	ldr	r3, .L1352+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L737
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L737
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L737
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L737
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L737
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L737
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L737:
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L740
.L739:
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L741
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L740
.L741:
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L742
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L740
.L742:
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L740:
	ldr	r3, .L1352+88
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L743
	mov	r3, #0
	mov	r4, r3
.L743:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L744
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L744:
	ldr	r3, .L1352+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L1352+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1352+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1352+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L1352+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L745
	ldr	r3, .L1352+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L748
.L745:
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L748:
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L750
	ldr	r3, .L1352+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L1352+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L1352+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L1352+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L1352+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L1352+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L1352+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L753
.L750:
	ldr	r3, .L1352+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1352+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L753
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L753
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L753:
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1352+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1352+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1352+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1352+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1352+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L758
.L755:
	ldr	r3, .L1352+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L1352+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L758
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L758
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L758
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L758
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L758:
	ldr	r3, .L1352+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	b	.L1353
.L1354:
	.align	2
.L1352:
	.word	_x_p6_x
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
	.word	id2
	.word	proposed6
	.word	_x_proposed6
	.word	_x_p6_saved_max
	.word	p6_l0
	.word	p6_l1
	.word	_x_p6_l0
	.word	_x_p6_l1
	.word	p6_x
	.word	p5_saved_max
	.word	_x_p5_saved_max
	.word	_x_p5_l0
	.word	_x_p5_l1
	.word	p5_x
	.word	_x_p5_x
	.word	_x_id2
	.word	proposed5
	.word	_x_proposed5
	.word	p5_l0
	.word	p5_l1
	.word	p4_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p4_saved_max
	.word	_x_p4_l0
	.word	_x_p4_l1
	.word	p4_x
	.word	_x_p4_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id0
	.word	_x_id1
	.word	proposed4
	.word	_x_proposed4
	.word	p4_l0
	.word	p4_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	_x_proposed3
	.word	p3_l0
	.word	_x_p3_l0
	.word	p3_l1
	.word	_x_p3_l1
	.word	delta
	.word	p3_x
	.word	_x_p3_x
.L1353:
	mov	r3, r0
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L763
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L763
	ldr	r3, .L1352+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L764
.L763:
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L1352+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L764
.L760:
	ldr	r3, .L1352+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L764
	ldr	r3, .L1352+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L764
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L764
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L764
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L764
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L764
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L764
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L764:
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1352+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L766
	ldr	r3, .L1352+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L766
	ldr	r3, .L1352+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L766
	ldr	r3, .L1352+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1352+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1352+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L766
	ldr	r3, .L1352+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+88
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L769
	mov	r3, #0
	mov	r4, r3
.L769:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L770
.L766:
	ldr	r3, .L1352+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L770
	ldr	r3, .L1352+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L770
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L770
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L770
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L770
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L770
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L770
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L770:
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L772
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L773
.L772:
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L774
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L773
.L774:
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L773
.L775:
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L773:
	ldr	r3, .L1352+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L776
	mov	r3, #0
	mov	r4, r3
.L776:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L777
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L777:
	ldr	r3, .L1352+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L778
	ldr	r3, .L1352+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L778
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1352+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1352+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L778
	ldr	r3, .L1352+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L778
	ldr	r3, .L1352+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L781
.L778:
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L781:
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L783
	ldr	r3, .L1352+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1352+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1352+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1352+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1352+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1352+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1352+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L786
.L783:
	ldr	r3, .L1352+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1352+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L786:
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1352+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1352+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1352+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1352+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1352+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L791
.L788:
	ldr	r3, .L1352+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
	ldr	r3, .L1352+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L791
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L791
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L791
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L791
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L791
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L791:
	ldr	r3, .L1352+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L796
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L796
	ldr	r3, .L1352+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L797
.L796:
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L1352+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L797
.L793:
	ldr	r3, .L1352+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L797
	ldr	r3, .L1352+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L797
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L797
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L797
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L797
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L797
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L797
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L797:
	ldr	r3, .L1352+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L799
	ldr	r3, .L1352+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L799
	ldr	r3, .L1352+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L799
	ldr	r3, .L1352+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L799
	ldr	r3, .L1352+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L799
	ldr	r3, .L1352+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L799
	ldr	r3, .L1352+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L799
	ldr	r3, .L1352+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L799
	ldr	r3, .L1352+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L799
	ldr	r3, .L1352+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+172
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L802
	mov	r3, #0
	mov	r4, r3
.L802:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L803
.L799:
	ldr	r3, .L1352+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L1352+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L1352+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L803
	ldr	r3, .L1352+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L803
	ldr	r3, .L1352+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L803
	ldr	r3, .L1352+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L803
	ldr	r3, .L1352+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L803
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L803:
	ldr	r3, .L1352+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L805
	ldr	r3, .L1352+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L806
.L805:
	ldr	r3, .L1352+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L1352+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L806
.L807:
	ldr	r3, .L1352+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
	ldr	r3, .L1352+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L806
.L808:
	ldr	r3, .L1352+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L806:
	ldr	r3, .L1352+204
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L809
	mov	r3, #0
	mov	r4, r3
.L809:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1352+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L1352+204
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L810
	ldr	r3, .L1352+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1352+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L810:
	ldr	r3, .L1352+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L811
	ldr	r3, .L1352+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1352+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L811
	ldr	r3, .L1352+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1352+228
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1352+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L811
	ldr	r3, .L1355
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L811
	ldr	r3, .L1355+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L814
.L811:
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L814:
	ldr	r3, .L1355+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1355+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L816
	ldr	r3, .L1355+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1355+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1355+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1355+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1355+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1355+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1355+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L819
.L816:
	ldr	r3, .L1355+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1355+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1355+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1355+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1355+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L819:
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1355+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1355+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1355+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1355+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L824
.L821:
	ldr	r3, .L1355+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L824
	ldr	r3, .L1355+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
	ldr	r3, .L1355+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
	ldr	r3, .L1355+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
	ldr	r3, .L1355+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L824
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L824
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L824:
	ldr	r3, .L1355+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L829
	ldr	r3, .L1355+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L829
	ldr	r3, .L1355+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L830
.L829:
	ldr	r3, .L1355+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L826
	ldr	r3, .L1355+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L830
.L826:
	ldr	r3, .L1355+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1355+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L830
	ldr	r3, .L1355+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L830
	ldr	r3, .L1355+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L830
	ldr	r3, .L1355+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L830
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L830:
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L832
	ldr	r3, .L1355+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L832
	ldr	r3, .L1355+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L832
	ldr	r3, .L1355+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L832
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L832
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L832
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L832
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L832
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L832
	ldr	r3, .L1355+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+12
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L835
	mov	r3, #0
	mov	r4, r3
.L835:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L836
.L832:
	ldr	r3, .L1355+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L836
	ldr	r3, .L1355+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L836
	ldr	r3, .L1355+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L836
	ldr	r3, .L1355+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L836
	ldr	r3, .L1355+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L836
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L836
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L836
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L836:
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L838
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L839
.L838:
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L840
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L839
.L840:
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L841
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L839
.L841:
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L839:
	ldr	r3, .L1355+88
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L842
	mov	r3, #0
	mov	r4, r3
.L842:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L843:
	ldr	r3, .L1355+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L844
	ldr	r3, .L1355+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L844
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1355+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1355+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L844
	ldr	r3, .L1355+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L844
	ldr	r3, .L1355+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L847
.L844:
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L847:
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L849
	ldr	r3, .L1355+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1355+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1355+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1355+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1355+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1355+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1355+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L849
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L852
.L849:
	ldr	r3, .L1355+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1355+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1355+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1355+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1355+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L852:
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1355+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1355+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L857
.L854:
	ldr	r3, .L1355+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L857
	ldr	r3, .L1355+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L857
	ldr	r3, .L1355+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L857
	ldr	r3, .L1355+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L857
	ldr	r3, .L1355+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L857
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L857
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L857
	ldr	r3, .L1355+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L857:
	ldr	r3, .L1355+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L1355+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	b	.L1356
.L1357:
	.align	2
.L1355:
	.word	p3_saved_max
	.word	_x_p3_saved_max
	.word	proposed3
	.word	_x_proposed3
	.word	delta
	.word	turn4
	.word	turn3
	.word	turn2
	.word	_x_p3_l1
	.word	_x_p3_l0
	.word	_x_p3_x
	.word	p3_l0
	.word	p3_l1
	.word	p3_x
	.word	p2_saved_max
	.word	turn0
	.word	_x_p2_saved_max
	.word	_x_p2_l0
	.word	_x_p2_l1
	.word	p2_x
	.word	_x_p2_x
	.word	proposed2
	.word	_x_proposed2
	.word	p2_l0
	.word	p2_l1
	.word	turn1
	.word	p1_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p1_saved_max
	.word	_x_p1_l0
	.word	_x_p1_l1
	.word	p1_x
	.word	_x_p1_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id0
	.word	_x_id1
	.word	proposed1
	.word	_x_proposed1
	.word	p1_l0
	.word	p1_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	delta
	.word	_x_p0_x
	.word	_x_proposed0
	.word	_x_p0_l1
	.word	p0_l0
	.word	_x_p0_l0
.L1356:
	beq	.L859
	ldr	r3, .L1355+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L1355+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L1355+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L1355+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L862
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L862
	ldr	r3, .L1355+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L863
.L862:
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L859
	ldr	r3, .L1355+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L863
.L859:
	ldr	r3, .L1355+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L863
	ldr	r3, .L1355+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L863
	ldr	r3, .L1355+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L863
	ldr	r3, .L1355+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L863
	ldr	r3, .L1355+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L863
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L863
	ldr	r3, .L1355+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L863
	ldr	r3, .L1355+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L863:
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L1355+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L865
	ldr	r3, .L1355+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L865
	ldr	r3, .L1355+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L865
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L865
	ldr	r3, .L1355+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+88
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L868
	mov	r3, #0
	mov	r4, r3
.L868:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L869
.L865:
	ldr	r3, .L1355+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L869
	ldr	r3, .L1355+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L869
	ldr	r3, .L1355+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L869
	ldr	r3, .L1355+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L869
	ldr	r3, .L1355+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L869
	ldr	r3, .L1355+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L869
	ldr	r3, .L1355+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L869
	ldr	r3, .L1355+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L869:
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L871
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L872
.L871:
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L873
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L872
.L873:
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L874
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L872
.L874:
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L872:
	ldr	r3, .L1355+176
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L875
	mov	r3, #0
	mov	r4, r3
.L875:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L876
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L876
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L876:
	ldr	r3, .L1355+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L877
	ldr	r3, .L1355+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L877
	ldr	r3, .L1355+208
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1355+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1355+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L877
	ldr	r3, .L1355+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L877
	ldr	r3, .L1355+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L880
.L877:
	ldr	r3, .L1355+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1355+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L880:
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L882
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L882
	ldr	r3, .L1355+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L882
	ldr	r3, .L1355+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L882
	ldr	r3, .L1355+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L882
	ldr	r3, .L1355+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L882
	ldr	r3, .L1355+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L882
	ldr	r3, .L1355+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L882
	ldr	r3, .L1355+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L882
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L885
.L882:
	ldr	r3, .L1355+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1355+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1355+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1355+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1355+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1355+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L885
	ldr	r3, .L1355+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1355+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L885:
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1355+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1355+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L890
.L887:
	ldr	r3, .L1355+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L890
	ldr	r3, .L1355+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L890
	ldr	r3, .L1355+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L890
	ldr	r3, .L1355+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L890
	ldr	r3, .L1355+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L890
	ldr	r3, .L1355+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L890
	ldr	r3, .L1355+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L890
	ldr	r3, .L1355+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L890:
	ldr	r3, .L1355+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L895
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L895
	ldr	r3, .L1355+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L896
.L895:
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L892
	ldr	r3, .L1355+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L896
.L892:
	ldr	r3, .L1355+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L896
	ldr	r3, .L1355+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L896
	ldr	r3, .L1355+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L896
	ldr	r3, .L1355+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L896
	ldr	r3, .L1355+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L896
	ldr	r3, .L1355+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L896
	ldr	r3, .L1355+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L896
	ldr	r3, .L1355+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L896:
	ldr	r3, .L1355+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1355+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L898
	ldr	r3, .L1355+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L898
	ldr	r3, .L1355+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1355+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1355+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L898
	ldr	r3, .L1355+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1355+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1355+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L898
	ldr	r3, .L1355+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+176
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L901
	mov	r3, #0
	mov	r4, r3
.L901:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L902
.L898:
	ldr	r3, .L1355+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1355+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1355+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L902
	ldr	r3, .L1355+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L902
	ldr	r3, .L1355+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L902
	ldr	r3, .L1355+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L902
	ldr	r3, .L1355+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L902
	ldr	r3, .L1355+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L902:
	ldr	r3, .L1355+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L904
	ldr	r3, .L1355+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L905
.L904:
	ldr	r3, .L1355+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L906
	ldr	r3, .L1355+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L905
.L906:
	ldr	r3, .L1355+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L907
	ldr	r3, .L1355+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L905
.L907:
	ldr	r3, .L1355+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L905:
	ldr	r3, .L1355+216
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L908
	mov	r3, #0
	mov	r4, r3
.L908:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1355+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1355+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L909
	ldr	r3, .L1355+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L909
	ldr	r3, .L1355+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L909:
	ldr	r3, .L1355+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1355+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L910
	ldr	r3, .L1358
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L910
	ldr	r3, .L1358+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1358+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1358+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L910
	ldr	r3, .L1358+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L910
	ldr	r3, .L1358+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L913
.L910:
	ldr	r3, .L1358+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L913:
	ldr	r3, .L1358+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1358+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L915
	ldr	r3, .L1358+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1358+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1358+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1358+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1358+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1358+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1358+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L915
	ldr	r3, .L1358+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L918
.L915:
	ldr	r3, .L1358+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1358
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1358+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1358+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1358+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1358+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1358+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1358+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L918:
	ldr	r3, .L1358+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L920
	ldr	r3, .L1358+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L920
	ldr	r3, .L1358+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1358+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L920
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1358+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L923
.L920:
	ldr	r3, .L1358
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L923
	ldr	r3, .L1358+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L923
	ldr	r3, .L1358+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L923
	ldr	r3, .L1358+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L923
	ldr	r3, .L1358+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L923
	ldr	r3, .L1358+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L923
	ldr	r3, .L1358+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L923
	ldr	r3, .L1358+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L923:
	ldr	r3, .L1358+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L928
	ldr	r3, .L1358+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L928
	ldr	r3, .L1358+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L929
.L928:
	ldr	r3, .L1358+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L925
	ldr	r3, .L1358+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L929
.L925:
	ldr	r3, .L1358+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L929
	ldr	r3, .L1358
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1358+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1358+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1358+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1358+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1358+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L929
	ldr	r3, .L1358+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L929:
	ldr	r3, .L1358+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1358+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L931
	ldr	r3, .L1358+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L931
	ldr	r3, .L1358+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L931
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L931
	ldr	r3, .L1358+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+148
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L934
	mov	r3, #0
	mov	r4, r3
.L934:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L935
.L931:
	ldr	r3, .L1358+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L935
	ldr	r3, .L1358
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L935
	ldr	r3, .L1358+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L935
	ldr	r3, .L1358+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L935
	ldr	r3, .L1358+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L935
	ldr	r3, .L1358+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L935
	ldr	r3, .L1358+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L935
	ldr	r3, .L1358+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L247
.L935:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L937
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L937:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L939
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L939
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L939
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L939
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L939:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L940
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L940
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L938
.L940:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L941
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L941
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L941
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L941
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L941:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L942
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L942
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L942
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L942
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L942:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L943
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L943
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L943
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L943
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L943:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L944
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L944
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L944
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L944
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L938
.L944:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L945
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L945
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L945
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L945
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L945:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L946
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L946
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L946
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L946
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L946:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L947
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L947
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L947:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L948
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L948
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L948
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L948
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L938
.L948:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L949
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L949
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L949
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L949
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L949:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L950
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L950
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L950
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L950
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L950:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L951
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L951:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L952
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L952
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L952
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L952
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L938
.L952:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L953:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L954
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L954
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L954
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L954
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L954:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L955
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L955
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L955
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L955
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L955:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L956
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L956
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L956
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L956
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L938
.L956:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L957
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L957:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L958
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L1359
.L1360:
	.align	2
.L1358:
	.word	p0_l1
	.word	_x_p0_l1
	.word	delta
	.word	p0_x
	.word	_x_p0_x
	.word	p0_saved_max
	.word	_x_p0_saved_max
	.word	proposed0
	.word	_x_p0_l0
	.word	max_prop
	.word	p0_l0
	.word	delta
	.word	_x_inc_max_prop
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
	.word	id2
	.word	_x_id2
	.word	id3
	.word	_x_id3
	.word	id4
	.word	_x_id4
	.word	turn0
	.word	_x_turn0
	.word	turn1
	.word	_x_turn1
	.word	turn2
	.word	_x_turn2
	.word	turn3
	.word	_x_turn3
	.word	turn4
	.word	_x_turn4
	.word	_x_delta
	.word	_x_proposed18
	.word	_x_proposed19
	.word	_x_proposed20
	.word	_x_proposed0
	.word	_x_proposed1
	.word	_x_proposed2
	.word	_x_proposed3
	.word	_x_proposed4
	.word	_x_proposed5
	.word	_x_proposed6
	.word	_x_proposed7
	.word	_x_proposed8
	.word	_x_proposed9
	.word	_x_proposed10
	.word	_x_proposed11
	.word	_x_proposed12
	.word	_x_proposed13
	.word	_x_proposed14
	.word	_x_proposed15
	.word	_x_proposed16
	.word	_x_proposed17
	.word	_x_max_prop
.L1359:
	cmp	r3, #0
	bne	.L958
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L958
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L958
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L938
.L958:
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L938:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L959
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L959
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L959
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L959
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L959:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L961
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L961
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L961
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L961
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L960
.L961:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L962
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L962
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L962
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L962
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L962:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L963
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L963
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L963
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L963
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L963:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L964
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L964
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L964
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L964
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L964:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L965
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L960
.L965:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L966
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L966
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L966
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L966
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L966:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L967
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L967
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L967
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L967
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L967:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L968
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L968
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L968
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L968
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L968:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L969
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L969
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L969
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L969
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L960
.L969:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L970
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L970
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L970:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L971
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L971
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L971
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L971
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L971:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L972
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L972
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L972
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L972
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L972:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L973
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L973
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L960
.L973:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L974
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L974
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L974
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L974
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L974:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L975:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L976
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L976
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L976
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L976
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L976:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L977
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L977
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L977
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L977
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L960
.L977:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L978
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L978
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L978
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L978
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L978:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L979
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L979
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L979
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L979
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L979:
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
.L960:
	ldr	r3, .L1358+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L980
	ldr	r3, .L1358+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1358+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
.L980:
	ldr	r3, .L1358+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+200
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+204
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1358+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+164
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+176
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+200
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+204
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1358+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L1358+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1361
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1361+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1361+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
.L1003:
	ldr	r3, .L1361+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r4, r3, #255
	ldr	r3, .L1361+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+4
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r5, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1005
	mov	r3, #0
	mov	r5, r3
.L1005:
	and	r3, r5, #255
	eor	r3, r3, r4
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1361+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1006
	ldr	r3, .L1361+32
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1007
	mov	r3, #0
	mov	r4, r3
.L1007:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L247
.L1006:
	ldr	r3, .L1361+32
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1008
	ldr	r3, .L1361+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1361+32
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1361+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
.L1008:
	mov	r3, #1
	b	.L1010
.L247:
	mov	r3, #0
.L1010:
	str	r3, [fp, #-24]
	ldr	r3, .L1361+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+32
	str	r3, [r2]	@ float
	ldr	r3, .L1361+36
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+40
	strb	r2, [r3]
	ldr	r3, .L1361+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+48
	str	r3, [r2]	@ float
	ldr	r3, .L1361+52
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+56
	strb	r2, [r3]
	ldr	r3, .L1361+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+64
	str	r3, [r2]	@ float
	ldr	r3, .L1361+68
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+72
	strb	r2, [r3]
	ldr	r3, .L1361+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+80
	str	r3, [r2]	@ float
	ldr	r3, .L1361+84
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+88
	strb	r2, [r3]
	ldr	r3, .L1361+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+96
	str	r3, [r2]	@ float
	ldr	r3, .L1361+100
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+104
	strb	r2, [r3]
	ldr	r3, .L1361+108
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+112
	strb	r2, [r3]
	ldr	r3, .L1361+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+120
	str	r3, [r2]	@ float
	ldr	r3, .L1361+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+128
	str	r3, [r2]	@ float
	ldr	r3, .L1361+132
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+136
	strb	r2, [r3]
	ldr	r3, .L1361+140
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+144
	strb	r2, [r3]
	ldr	r3, .L1361+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+152
	str	r3, [r2]	@ float
	ldr	r3, .L1361+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+160
	str	r3, [r2]	@ float
	ldr	r3, .L1361+164
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+168
	strb	r2, [r3]
	ldr	r3, .L1361+172
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+176
	strb	r2, [r3]
	ldr	r3, .L1361+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+184
	str	r3, [r2]	@ float
	ldr	r3, .L1361+188
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+192
	str	r3, [r2]	@ float
	ldr	r3, .L1361+196
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+200
	strb	r2, [r3]
	ldr	r3, .L1361+204
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+208
	strb	r2, [r3]
	ldr	r3, .L1361+212
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+216
	strb	r2, [r3]
	ldr	r3, .L1361+220
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+224
	strb	r2, [r3]
	ldr	r3, .L1361+228
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+232
	str	r3, [r2]	@ float
	ldr	r3, .L1361+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+240
	str	r3, [r2]	@ float
	ldr	r3, .L1361+244
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+248
	strb	r2, [r3]
	ldr	r3, .L1361+252
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+256
	strb	r2, [r3]
	ldr	r3, .L1361+260
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+264
	str	r3, [r2]	@ float
	ldr	r3, .L1361+268
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+272
	str	r3, [r2]	@ float
	ldr	r3, .L1361+276
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+280
	strb	r2, [r3]
	ldr	r3, .L1361+284
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+288
	strb	r2, [r3]
	ldr	r3, .L1361+292
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+296
	str	r3, [r2]	@ float
	ldr	r3, .L1361+300
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+304
	str	r3, [r2]	@ float
	ldr	r3, .L1361+308
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+312
	strb	r2, [r3]
	ldr	r3, .L1361+316
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+320
	strb	r2, [r3]
	ldr	r3, .L1361+324
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+328
	str	r3, [r2]	@ float
	ldr	r3, .L1361+332
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+336
	str	r3, [r2]	@ float
	ldr	r3, .L1361+340
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+344
	str	r3, [r2]	@ float
	ldr	r3, .L1361+348
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+352
	str	r3, [r2]	@ float
	ldr	r3, .L1361+356
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+360
	str	r3, [r2]	@ float
	ldr	r3, .L1361+364
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+368
	str	r3, [r2]	@ float
	ldr	r3, .L1361+372
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+376
	strb	r2, [r3]
	ldr	r3, .L1361+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+20
	str	r3, [r2]	@ float
	ldr	r3, .L1361+380
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+24
	str	r3, [r2]	@ float
	ldr	r3, .L1361+384
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+388
	strb	r2, [r3]
	ldr	r3, .L1361+392
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+396
	str	r3, [r2]	@ float
	ldr	r3, .L1361+400
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+404
	strb	r2, [r3]
	ldr	r3, .L1361+408
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+412
	str	r3, [r2]	@ float
	ldr	r3, .L1361+416
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+420
	strb	r2, [r3]
	ldr	r3, .L1361+424
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+428
	strb	r2, [r3]
	ldr	r3, .L1361+432
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+436
	str	r3, [r2]	@ float
	ldr	r3, .L1361+440
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+444
	str	r3, [r2]	@ float
	ldr	r3, .L1361+448
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+452
	strb	r2, [r3]
	ldr	r3, .L1361+456
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+460
	str	r3, [r2]	@ float
	ldr	r3, .L1361+464
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+468
	str	r3, [r2]	@ float
	ldr	r3, .L1361+472
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+476
	str	r3, [r2]	@ float
	ldr	r3, .L1361+480
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+484
	strb	r2, [r3]
	ldr	r3, .L1361+488
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+492
	strb	r2, [r3]
	ldr	r3, .L1361+496
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+500
	strb	r2, [r3]
	ldr	r3, .L1361+504
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+508
	str	r3, [r2]	@ float
	ldr	r3, .L1361+512
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+516
	str	r3, [r2]	@ float
	ldr	r3, .L1361+520
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+524
	str	r3, [r2]	@ float
	ldr	r3, .L1361+528
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+532
	str	r3, [r2]	@ float
	ldr	r3, .L1361+536
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+540
	str	r3, [r2]	@ float
	ldr	r3, .L1361+544
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+548
	strb	r2, [r3]
	ldr	r3, .L1361+552
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+556
	strb	r2, [r3]
	ldr	r3, .L1361+560
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+564
	strb	r2, [r3]
	ldr	r3, .L1361+568
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+572
	strb	r2, [r3]
	ldr	r3, .L1361+576
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+580
	str	r3, [r2]	@ float
	ldr	r3, .L1361+584
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+588
	strb	r2, [r3]
	ldr	r3, .L1361+592
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+596
	strb	r2, [r3]
	ldr	r3, .L1361+600
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+604
	str	r3, [r2]	@ float
	ldr	r3, .L1361+608
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+612
	str	r3, [r2]	@ float
	ldr	r3, .L1361+616
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+620
	str	r3, [r2]	@ float
	ldr	r3, .L1361+624
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+628
	strb	r2, [r3]
	ldr	r3, .L1361+632
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+636
	strb	r2, [r3]
	ldr	r3, .L1361+640
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+644
	str	r3, [r2]	@ float
	ldr	r3, .L1361+648
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+652
	str	r3, [r2]	@ float
	ldr	r3, .L1361
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+656
	str	r3, [r2]	@ float
	ldr	r3, .L1361+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+660
	str	r3, [r2]	@ float
	ldr	r3, .L1361+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+664
	str	r3, [r2]	@ float
	ldr	r3, .L1361+668
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+672
	str	r3, [r2]	@ float
	ldr	r3, .L1361+676
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+680
	strb	r2, [r3]
	ldr	r3, .L1361+684
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+688
	str	r3, [r2]	@ float
	ldr	r3, .L1361+692
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+696
	str	r3, [r2]	@ float
	ldr	r3, .L1361+700
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+704
	strb	r2, [r3]
	ldr	r3, .L1361+708
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+712
	strb	r2, [r3]
	ldr	r3, .L1361+716
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+720
	str	r3, [r2]	@ float
	ldr	r3, .L1361+724
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+728
	str	r3, [r2]	@ float
	ldr	r3, .L1361+732
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+736
	str	r3, [r2]	@ float
	ldr	r3, .L1361+740
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+744
	str	r3, [r2]	@ float
	ldr	r3, .L1361+748
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+752
	strb	r2, [r3]
	ldr	r3, .L1361+756
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+760
	strb	r2, [r3]
	ldr	r3, .L1361+764
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+768
	str	r3, [r2]	@ float
	ldr	r3, .L1361+772
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+776
	str	r3, [r2]	@ float
	ldr	r3, .L1361+780
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+784
	str	r3, [r2]	@ float
	ldr	r3, .L1361+788
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+792
	strb	r2, [r3]
	ldr	r3, .L1361+796
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+800
	strb	r2, [r3]
	ldr	r3, .L1361+804
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+808
	strb	r2, [r3]
	ldr	r3, .L1361+812
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+816
	str	r3, [r2]	@ float
	ldr	r3, .L1361+820
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+824
	str	r3, [r2]	@ float
	ldr	r3, .L1361+16
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+828
	strb	r2, [r3]
	ldr	r3, .L1361+832
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+836
	strb	r2, [r3]
	ldr	r3, .L1361+840
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+844
	str	r3, [r2]	@ float
	ldr	r3, .L1361+848
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+852
	strb	r2, [r3]
	ldr	r3, .L1361+856
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+860
	str	r3, [r2]	@ float
	ldr	r3, .L1361+864
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+868
	str	r3, [r2]	@ float
	ldr	r3, .L1361+872
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+876
	strb	r2, [r3]
	ldr	r3, .L1361+880
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+884
	strb	r2, [r3]
	ldr	r3, .L1361+888
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+892
	str	r3, [r2]	@ float
	ldr	r3, .L1361+896
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+900
	str	r3, [r2]	@ float
	ldr	r3, .L1361+904
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+908
	str	r3, [r2]	@ float
	ldr	r3, .L1361+912
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+916
	strb	r2, [r3]
	ldr	r3, .L1361+920
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+924
	str	r3, [r2]	@ float
	ldr	r3, .L1361+928
	ldr	r3, [r3]	@ float
	ldr	r2, .L1361+932
	str	r3, [r2]	@ float
	ldr	r3, .L1361+936
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+940
	strb	r2, [r3]
	ldr	r3, .L1361+944
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1361+948
	strb	r2, [r3]
.L242:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L1011
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
.L1362:
	.align	2
.L1361:
	.word	_x_proposed18
	.word	_x_max_prop
	.word	_x_proposed19
	.word	_x_proposed20
	.word	_x_inc_max_prop
	.word	max_prop
	.word	delta
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_p20_l1
	.word	p20_l1
	.word	_x_p20_saved_max
	.word	p20_saved_max
	.word	_x_p19_l1
	.word	p19_l1
	.word	_x_p19_saved_max
	.word	p19_saved_max
	.word	_x_p17_l1
	.word	p17_l1
	.word	_x_p17_saved_max
	.word	p17_saved_max
	.word	_x_p16_l1
	.word	p16_l1
	.word	_x_p16_saved_max
	.word	p16_saved_max
	.word	_x_p20_l0
	.word	p20_l0
	.word	_x_p15_l1
	.word	p15_l1
	.word	_x_p20_x
	.word	p20_x
	.word	_x_p15_saved_max
	.word	p15_saved_max
	.word	_x_p19_l0
	.word	p19_l0
	.word	_x_p14_l1
	.word	p14_l1
	.word	_x_p19_x
	.word	p19_x
	.word	_x_p14_saved_max
	.word	p14_saved_max
	.word	_x_p17_l0
	.word	p17_l0
	.word	_x_p12_l1
	.word	p12_l1
	.word	_x_p17_x
	.word	p17_x
	.word	_x_p12_saved_max
	.word	p12_saved_max
	.word	_x_p16_l0
	.word	p16_l0
	.word	_x_p11_l1
	.word	p11_l1
	.word	_x_p15_l0
	.word	p15_l0
	.word	_x_p10_l1
	.word	p10_l1
	.word	_x_p15_x
	.word	p15_x
	.word	_x_p10_saved_max
	.word	p10_saved_max
	.word	_x_p14_l0
	.word	p14_l0
	.word	_x_p9_l1
	.word	p9_l1
	.word	_x_p14_x
	.word	p14_x
	.word	_x_p9_saved_max
	.word	p9_saved_max
	.word	_x_p12_l0
	.word	p12_l0
	.word	_x_p7_l1
	.word	p7_l1
	.word	_x_p12_x
	.word	p12_x
	.word	_x_p7_saved_max
	.word	p7_saved_max
	.word	_x_p11_l0
	.word	p11_l0
	.word	_x_p6_l1
	.word	p6_l1
	.word	_x_proposed15
	.word	proposed15
	.word	_x_proposed14
	.word	proposed14
	.word	_x_proposed13
	.word	proposed13
	.word	_x_p1_x
	.word	p1_x
	.word	_x_proposed5
	.word	proposed5
	.word	_x_proposed4
	.word	proposed4
	.word	_x_turn4
	.word	turn4
	.word	_x_delta
	.word	_x_p18_l1
	.word	p18_l1
	.word	_x_proposed2
	.word	proposed2
	.word	_x_turn2
	.word	turn2
	.word	_x_proposed11
	.word	proposed11
	.word	_x_id3
	.word	id3
	.word	_x_turn3
	.word	turn3
	.word	_x_proposed3
	.word	proposed3
	.word	_x_proposed12
	.word	proposed12
	.word	_x_id4
	.word	id4
	.word	_x_p13_x
	.word	p13_x
	.word	_x_p8_saved_max
	.word	p8_saved_max
	.word	_x_proposed8
	.word	proposed8
	.word	_x_id0
	.word	id0
	.word	_x_p6_l0
	.word	p6_l0
	.word	_x_p1_l1
	.word	p1_l1
	.word	_x_p7_x
	.word	p7_x
	.word	_x_p2_saved_max
	.word	p2_saved_max
	.word	_x_p18_x
	.word	p18_x
	.word	_x_p13_saved_max
	.word	p13_saved_max
	.word	_x_proposed9
	.word	proposed9
	.word	_x_id1
	.word	id1
	.word	_x_turn0
	.word	turn0
	.word	_x_p13_l0
	.word	p13_l0
	.word	_x_p8_l1
	.word	p8_l1
	.word	_x_proposed0
	.word	proposed0
	.word	_x_p18_l0
	.word	p18_l0
	.word	_x_p13_l1
	.word	p13_l1
	.word	_x_proposed1
	.word	proposed1
	.word	_x_p18_saved_max
	.word	p18_saved_max
	.word	_x_proposed10
	.word	proposed10
	.word	_x_id2
	.word	id2
	.word	_x_turn1
	.word	turn1
	.word	_x_proposed16
	.word	proposed16
	.word	_x_proposed17
	.word	proposed17
	.word	proposed18
	.word	proposed19
	.word	proposed20
	.word	_x_p0_x
	.word	p0_x
	.word	_x_p3_l0
	.word	p3_l0
	.word	_x_p4_x
	.word	p4_x
	.word	_x_p0_saved_max
	.word	p0_saved_max
	.word	_x_p8_l0
	.word	p8_l0
	.word	_x_p3_l1
	.word	p3_l1
	.word	_x_p9_x
	.word	p9_x
	.word	_x_p4_saved_max
	.word	p4_saved_max
	.word	_x_p11_x
	.word	p11_x
	.word	_x_p6_saved_max
	.word	p6_saved_max
	.word	_x_p0_l0
	.word	p0_l0
	.word	_x_p4_l0
	.word	p4_l0
	.word	_x_p5_x
	.word	p5_x
	.word	_x_p16_x
	.word	p16_x
	.word	_x_p11_saved_max
	.word	p11_saved_max
	.word	_x_p0_l1
	.word	p0_l1
	.word	_x_p9_l0
	.word	p9_l0
	.word	_x_p4_l1
	.word	p4_l1
	.word	_x_p10_x
	.word	p10_x
	.word	_x_p5_saved_max
	.word	p5_saved_max
	.word	inc_max_prop
	.word	_x_p1_l0
	.word	p1_l0
	.word	_x_p2_x
	.word	p2_x
	.word	_x_p2_l0
	.word	p2_l0
	.word	_x_proposed6
	.word	proposed6
	.word	_x_p3_x
	.word	p3_x
	.word	_x_p7_l0
	.word	p7_l0
	.word	_x_p2_l1
	.word	p2_l1
	.word	_x_p8_x
	.word	p8_x
	.word	_x_proposed7
	.word	proposed7
	.word	_x_p3_saved_max
	.word	p3_saved_max
	.word	_x_p5_l0
	.word	p5_l0
	.word	_x_p1_saved_max
	.word	p1_saved_max
	.word	_x_p6_x
	.word	p6_x
	.word	_x_p10_l0
	.word	p10_l0
	.word	_x_p5_l1
	.word	p5_l1
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
