	.file	"362029.c"
	.intel_syntax noprefix
	.text
	.globl	__fenv_fegetround
	.type	__fenv_fegetround, @function
__fenv_fegetround:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	fegetround@PLT
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__fenv_fegetround, .-__fenv_fegetround
	.globl	__fenv_fesetround
	.type	__fenv_fesetround, @function
__fenv_fesetround:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	edi, eax
	call	fesetround@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	__fenv_fesetround, .-__fenv_fesetround
	.globl	__fenv_fegetexceptflag
	.type	__fenv_fegetexceptflag, @function
__fenv_fegetexceptflag:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	DWORD PTR -12[rbp], esi
	mov	edx, DWORD PTR -12[rbp]
	mov	rax, QWORD PTR -8[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	fegetexceptflag@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	__fenv_fegetexceptflag, .-__fenv_fegetexceptflag
	.globl	__fenv_fesetexceptflag
	.type	__fenv_fesetexceptflag, @function
__fenv_fesetexceptflag:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	DWORD PTR -12[rbp], esi
	mov	edx, DWORD PTR -12[rbp]
	mov	rax, QWORD PTR -8[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	fesetexceptflag@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	__fenv_fesetexceptflag, .-__fenv_fesetexceptflag
	.globl	__fenv_fetestexcept
	.type	__fenv_fetestexcept, @function
__fenv_fetestexcept:
.LFB4:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	edi, eax
	call	fetestexcept@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE4:
	.size	__fenv_fetestexcept, .-__fenv_fetestexcept
	.globl	__fenv_feclearexcept
	.type	__fenv_feclearexcept, @function
__fenv_feclearexcept:
.LFB5:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	edi, eax
	call	feclearexcept@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE5:
	.size	__fenv_feclearexcept, .-__fenv_feclearexcept
	.globl	__fenv_feraiseexcept
	.type	__fenv_feraiseexcept, @function
__fenv_feraiseexcept:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	edi, eax
	call	feraiseexcept@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	__fenv_feraiseexcept, .-__fenv_feraiseexcept
	.globl	__fenv_feenableexcept
	.type	__fenv_feenableexcept, @function
__fenv_feenableexcept:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	edi, eax
	mov	eax, 0
	call	feenableexcept@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	__fenv_feenableexcept, .-__fenv_feenableexcept
	.globl	__fenv_fedisableexcept
	.type	__fenv_fedisableexcept, @function
__fenv_fedisableexcept:
.LFB8:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	DWORD PTR -4[rbp], edi
	mov	eax, DWORD PTR -4[rbp]
	mov	edi, eax
	mov	eax, 0
	call	fedisableexcept@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE8:
	.size	__fenv_fedisableexcept, .-__fenv_fedisableexcept
	.globl	__fenv_fegetexcept
	.type	__fenv_fegetexcept, @function
__fenv_fegetexcept:
.LFB9:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, 0
	call	fegetexcept@PLT
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE9:
	.size	__fenv_fegetexcept, .-__fenv_fegetexcept
	.globl	__fenv_fegetenv
	.type	__fenv_fegetenv, @function
__fenv_fegetenv:
.LFB10:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	fegetenv@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE10:
	.size	__fenv_fegetenv, .-__fenv_fegetenv
	.globl	__fenv_feholdexcept
	.type	__fenv_feholdexcept, @function
__fenv_feholdexcept:
.LFB11:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	feholdexcept@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE11:
	.size	__fenv_feholdexcept, .-__fenv_feholdexcept
	.globl	__fenv_fesetenv
	.type	__fenv_fesetenv, @function
__fenv_fesetenv:
.LFB12:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	fesetenv@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE12:
	.size	__fenv_fesetenv, .-__fenv_fesetenv
	.globl	__fenv_feupdateenv
	.type	__fenv_feupdateenv, @function
__fenv_feupdateenv:
.LFB13:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	mov	QWORD PTR -8[rbp], rdi
	mov	rax, QWORD PTR -8[rbp]
	mov	rdi, rax
	call	feupdateenv@PLT
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE13:
	.size	__fenv_feupdateenv, .-__fenv_feupdateenv
	.globl	__fenv_fesetzerodenorm
	.type	__fenv_fesetzerodenorm, @function
__fenv_fesetzerodenorm:
.LFB14:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -4[rbp], edi
	mov	eax, 0
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE14:
	.size	__fenv_fesetzerodenorm, .-__fenv_fesetzerodenorm
	.globl	__fenv_fegetzerodenorm
	.type	__fenv_fegetzerodenorm, @function
__fenv_fegetzerodenorm:
.LFB15:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	eax, 0
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE15:
	.size	__fenv_fegetzerodenorm, .-__fenv_fegetzerodenorm
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"362029.c"
	.text
	.align	2
	.global	__fenv_fegetround
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fegetround, %function
__fenv_fegetround:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	fegetround
	mov	r3, r0
	mov	r0, r3
	pop	{fp, pc}
	.size	__fenv_fegetround, .-__fenv_fegetround
	.align	2
	.global	__fenv_fesetround
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fesetround, %function
__fenv_fesetround:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	fesetround
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_fesetround, .-__fenv_fesetround
	.align	2
	.global	__fenv_fegetexceptflag
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fegetexceptflag, %function
__fenv_fegetexceptflag:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r1, [fp, #-12]
	ldr	r0, [fp, #-8]
	bl	fegetexceptflag
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_fegetexceptflag, .-__fenv_fegetexceptflag
	.align	2
	.global	__fenv_fesetexceptflag
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fesetexceptflag, %function
__fenv_fesetexceptflag:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	str	r1, [fp, #-12]
	ldr	r1, [fp, #-12]
	ldr	r0, [fp, #-8]
	bl	fesetexceptflag
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_fesetexceptflag, .-__fenv_fesetexceptflag
	.align	2
	.global	__fenv_fetestexcept
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fetestexcept, %function
__fenv_fetestexcept:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	fetestexcept
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_fetestexcept, .-__fenv_fetestexcept
	.align	2
	.global	__fenv_feclearexcept
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_feclearexcept, %function
__fenv_feclearexcept:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	feclearexcept
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_feclearexcept, .-__fenv_feclearexcept
	.align	2
	.global	__fenv_feraiseexcept
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_feraiseexcept, %function
__fenv_feraiseexcept:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	feraiseexcept
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_feraiseexcept, .-__fenv_feraiseexcept
	.align	2
	.global	__fenv_feenableexcept
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_feenableexcept, %function
__fenv_feenableexcept:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	feenableexcept
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_feenableexcept, .-__fenv_feenableexcept
	.align	2
	.global	__fenv_fedisableexcept
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fedisableexcept, %function
__fenv_fedisableexcept:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	fedisableexcept
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_fedisableexcept, .-__fenv_fedisableexcept
	.align	2
	.global	__fenv_fegetexcept
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fegetexcept, %function
__fenv_fegetexcept:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	fegetexcept
	mov	r3, r0
	mov	r0, r3
	pop	{fp, pc}
	.size	__fenv_fegetexcept, .-__fenv_fegetexcept
	.align	2
	.global	__fenv_fegetenv
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fegetenv, %function
__fenv_fegetenv:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	fegetenv
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_fegetenv, .-__fenv_fegetenv
	.align	2
	.global	__fenv_feholdexcept
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_feholdexcept, %function
__fenv_feholdexcept:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	feholdexcept
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_feholdexcept, .-__fenv_feholdexcept
	.align	2
	.global	__fenv_fesetenv
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fesetenv, %function
__fenv_fesetenv:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	fesetenv
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_fesetenv, .-__fenv_fesetenv
	.align	2
	.global	__fenv_feupdateenv
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_feupdateenv, %function
__fenv_feupdateenv:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #8
	str	r0, [fp, #-8]
	ldr	r0, [fp, #-8]
	bl	feupdateenv
	mov	r3, r0
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
	.size	__fenv_feupdateenv, .-__fenv_feupdateenv
	.align	2
	.global	__fenv_fesetzerodenorm
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fesetzerodenorm, %function
__fenv_fesetzerodenorm:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #12
	str	r0, [fp, #-8]
	mov	r3, #0
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	__fenv_fesetzerodenorm, .-__fenv_fesetzerodenorm
	.align	2
	.global	__fenv_fegetzerodenorm
	.syntax unified
	.arm
	.fpu softvfp
	.type	__fenv_fegetzerodenorm, %function
__fenv_fegetzerodenorm:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	mov	r3, #0
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	__fenv_fegetzerodenorm, .-__fenv_fegetzerodenorm
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
