	.file	"495.c"
	.intel_syntax noprefix
	.text
	.globl	isChekinPass
	.type	isChekinPass, @function
isChekinPass:
.LFB6:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	DWORD PTR -20[rbp], edi
	mov	QWORD PTR -32[rbp], rsi
	mov	DWORD PTR -24[rbp], edx
	mov	DWORD PTR -4[rbp], 0
	jmp	.L2
.L5:
	mov	eax, DWORD PTR -4[rbp]
	cdqe
	lea	rdx, 0[0+rax*4]
	mov	rax, QWORD PTR -32[rbp]
	add	rax, rdx
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -24[rbp], eax
	jne	.L3
	mov	eax, 0
	jmp	.L4
.L3:
	add	DWORD PTR -4[rbp], 1
.L2:
	mov	eax, DWORD PTR -4[rbp]
	cmp	eax, DWORD PTR -20[rbp]
	jl	.L5
	mov	eax, 1
.L4:
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE6:
	.size	isChekinPass, .-isChekinPass
	.section	.rodata
.LC0:
	.string	"Error"
.LC1:
	.string	"\n\347\254\254%d\347\276\244<\344\275\215\346\225\270%d>:\n"
.LC2:
	.string	"%d "
.LC3:
	.string	""
	.text
	.globl	main
	.type	main, @function
main:
.LFB7:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 4096
	or	QWORD PTR [rsp], 0
	sub	rsp, 416
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	lea	rdx, -4016[rbp]
	mov	eax, 0
	mov	ecx, 500
	mov	rdi, rdx
	rep stosq
	mov	DWORD PTR -4016[rbp], -1
	mov	QWORD PTR -4464[rbp], 0
	mov	QWORD PTR -4456[rbp], 0
	mov	QWORD PTR -4448[rbp], 0
	mov	QWORD PTR -4440[rbp], 0
	mov	QWORD PTR -4432[rbp], 0
	mov	edi, 0
	call	time@PLT
	mov	edi, eax
	call	srand@PLT
	mov	DWORD PTR -4500[rbp], 0
	jmp	.L7
.L10:
	call	rand@PLT
	movsx	rdx, eax
	imul	rdx, rdx, -2093742815
	shr	rdx, 32
	add	edx, eax
	sar	edx, 9
	mov	ecx, eax
	sar	ecx, 31
	sub	edx, ecx
	mov	DWORD PTR -4468[rbp], edx
	mov	edx, DWORD PTR -4468[rbp]
	imul	edx, edx, 999
	sub	eax, edx
	mov	DWORD PTR -4468[rbp], eax
	mov	edx, DWORD PTR -4468[rbp]
	lea	rcx, -4416[rbp]
	mov	eax, DWORD PTR -4500[rbp]
	mov	rsi, rcx
	mov	edi, eax
	call	isChekinPass
	test	eax, eax
	je	.L8
	mov	eax, DWORD PTR -4500[rbp]
	cdqe
	mov	edx, DWORD PTR -4468[rbp]
	mov	DWORD PTR -4416[rbp+rax*4], edx
	jmp	.L9
.L8:
	sub	DWORD PTR -4500[rbp], 1
.L9:
	add	DWORD PTR -4500[rbp], 1
.L7:
	cmp	DWORD PTR -4500[rbp], 99
	jle	.L10
	mov	DWORD PTR -4496[rbp], 0
	jmp	.L11
.L25:
	mov	eax, DWORD PTR -4496[rbp]
	cdqe
	mov	ecx, DWORD PTR -4416[rbp+rax*4]
	movsx	rax, ecx
	imul	rax, rax, 1717986919
	shr	rax, 32
	sar	eax, 2
	mov	esi, ecx
	sar	esi, 31
	sub	eax, esi
	mov	edx, eax
	mov	eax, edx
	sal	eax, 2
	add	eax, edx
	add	eax, eax
	sub	ecx, eax
	mov	edx, ecx
	cmp	edx, 9
	ja	.L12
	mov	eax, edx
	lea	rdx, 0[0+rax*4]
	lea	rax, .L14[rip]
	mov	eax, DWORD PTR [rdx+rax]
	cdqe
	lea	rdx, .L14[rip]
	add	rax, rdx
	notrack jmp	rax
	.section	.rodata
	.align 4
	.align 4
.L14:
	.long	.L23-.L14
	.long	.L22-.L14
	.long	.L21-.L14
	.long	.L20-.L14
	.long	.L19-.L14
	.long	.L18-.L14
	.long	.L17-.L14
	.long	.L16-.L14
	.long	.L15-.L14
	.long	.L13-.L14
	.text
.L23:
	mov	eax, DWORD PTR -4464[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4464[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L22:
	mov	eax, DWORD PTR -4460[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4460[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 100
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L21:
	mov	eax, DWORD PTR -4456[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4456[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 200
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L20:
	mov	eax, DWORD PTR -4452[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4452[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 300
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L19:
	mov	eax, DWORD PTR -4448[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4448[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 400
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L18:
	mov	eax, DWORD PTR -4444[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4444[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 500
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L17:
	mov	eax, DWORD PTR -4440[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4440[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 600
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L16:
	mov	eax, DWORD PTR -4436[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4436[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 700
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L15:
	mov	eax, DWORD PTR -4432[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4432[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 800
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L13:
	mov	eax, DWORD PTR -4428[rbp]
	lea	edx, 1[rax]
	mov	DWORD PTR -4428[rbp], edx
	mov	edx, DWORD PTR -4496[rbp]
	movsx	rdx, edx
	mov	edx, DWORD PTR -4416[rbp+rdx*4]
	cdqe
	add	rax, 900
	mov	DWORD PTR -4016[rbp+rax*4], edx
	jmp	.L24
.L12:
	lea	rdi, .LC0[rip]
	call	puts@PLT
	nop
.L24:
	add	DWORD PTR -4496[rbp], 1
.L11:
	cmp	DWORD PTR -4496[rbp], 99
	jle	.L25
	mov	DWORD PTR -4472[rbp], 0
	mov	DWORD PTR -4492[rbp], 0
	jmp	.L26
.L32:
	mov	DWORD PTR -4488[rbp], 0
	jmp	.L27
.L31:
	mov	DWORD PTR -4484[rbp], 0
	jmp	.L28
.L30:
	mov	eax, DWORD PTR -4484[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -4492[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, 0[0+rax*4]
	add	rax, rdx
	sal	rax, 2
	add	rax, rcx
	mov	ecx, DWORD PTR -4016[rbp+rax*4]
	mov	eax, DWORD PTR -4484[rbp]
	add	eax, 1
	movsx	rsi, eax
	mov	eax, DWORD PTR -4492[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, 0[0+rax*4]
	add	rax, rdx
	sal	rax, 2
	add	rax, rsi
	mov	eax, DWORD PTR -4016[rbp+rax*4]
	cmp	ecx, eax
	jle	.L29
	mov	eax, DWORD PTR -4484[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -4492[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, 0[0+rax*4]
	add	rax, rdx
	sal	rax, 2
	add	rax, rcx
	mov	eax, DWORD PTR -4016[rbp+rax*4]
	mov	DWORD PTR -4472[rbp], eax
	mov	eax, DWORD PTR -4484[rbp]
	add	eax, 1
	movsx	rcx, eax
	mov	eax, DWORD PTR -4492[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, 0[0+rax*4]
	add	rax, rdx
	sal	rax, 2
	add	rax, rcx
	mov	edx, DWORD PTR -4016[rbp+rax*4]
	mov	eax, DWORD PTR -4484[rbp]
	movsx	rsi, eax
	mov	eax, DWORD PTR -4492[rbp]
	movsx	rcx, eax
	mov	rax, rcx
	sal	rax, 2
	add	rax, rcx
	lea	rcx, 0[0+rax*4]
	add	rax, rcx
	sal	rax, 2
	add	rax, rsi
	mov	DWORD PTR -4016[rbp+rax*4], edx
	mov	eax, DWORD PTR -4484[rbp]
	add	eax, 1
	movsx	rcx, eax
	mov	eax, DWORD PTR -4492[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, 0[0+rax*4]
	add	rax, rdx
	sal	rax, 2
	lea	rdx, [rax+rcx]
	mov	eax, DWORD PTR -4472[rbp]
	mov	DWORD PTR -4016[rbp+rdx*4], eax
.L29:
	add	DWORD PTR -4484[rbp], 1
.L28:
	mov	eax, DWORD PTR -4492[rbp]
	cdqe
	mov	eax, DWORD PTR -4464[rbp+rax*4]
	sub	eax, 1
	cmp	DWORD PTR -4484[rbp], eax
	jl	.L30
	add	DWORD PTR -4488[rbp], 1
.L27:
	mov	eax, DWORD PTR -4492[rbp]
	cdqe
	mov	eax, DWORD PTR -4464[rbp+rax*4]
	cmp	DWORD PTR -4488[rbp], eax
	jl	.L31
	add	DWORD PTR -4492[rbp], 1
.L26:
	cmp	DWORD PTR -4492[rbp], 9
	jle	.L32
	mov	DWORD PTR -4480[rbp], 0
	jmp	.L33
.L38:
	mov	edx, DWORD PTR -4480[rbp]
	mov	eax, DWORD PTR -4480[rbp]
	mov	esi, eax
	lea	rdi, .LC1[rip]
	mov	eax, 0
	call	printf@PLT
	mov	DWORD PTR -4476[rbp], 0
	jmp	.L34
.L37:
	mov	eax, DWORD PTR -4480[rbp]
	cdqe
	mov	eax, DWORD PTR -4464[rbp+rax*4]
	cmp	DWORD PTR -4476[rbp], eax
	je	.L41
	mov	eax, DWORD PTR -4476[rbp]
	movsx	rcx, eax
	mov	eax, DWORD PTR -4480[rbp]
	movsx	rdx, eax
	mov	rax, rdx
	sal	rax, 2
	add	rax, rdx
	lea	rdx, 0[0+rax*4]
	add	rax, rdx
	sal	rax, 2
	add	rax, rcx
	mov	eax, DWORD PTR -4016[rbp+rax*4]
	mov	esi, eax
	lea	rdi, .LC2[rip]
	mov	eax, 0
	call	printf@PLT
	add	DWORD PTR -4476[rbp], 1
.L34:
	cmp	DWORD PTR -4476[rbp], 99
	jle	.L37
	jmp	.L36
.L41:
	nop
.L36:
	lea	rdi, .LC3[rip]
	call	puts@PLT
	add	DWORD PTR -4480[rbp], 1
.L33:
	cmp	DWORD PTR -4480[rbp], 9
	jle	.L38
	mov	eax, 0
	mov	rdi, QWORD PTR -8[rbp]
	sub	rdi, QWORD PTR fs:40
	je	.L40
	call	__stack_chk_fail@PLT
.L40:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE7:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"495.c"
	.text
	.align	2
	.global	isChekinPass
	.syntax unified
	.arm
	.fpu softvfp
	.type	isChekinPass, %function
isChekinPass:
	@ args = 0, pretend = 0, frame = 24
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #28
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	str	r2, [fp, #-24]
	mov	r3, #0
	str	r3, [fp, #-8]
	b	.L2
.L5:
	ldr	r3, [fp, #-8]
	lsl	r3, r3, #2
	ldr	r2, [fp, #-20]
	add	r3, r2, r3
	ldr	r3, [r3]
	ldr	r2, [fp, #-24]
	cmp	r2, r3
	bne	.L3
	mov	r3, #0
	b	.L4
.L3:
	ldr	r3, [fp, #-8]
	add	r3, r3, #1
	str	r3, [fp, #-8]
.L2:
	ldr	r2, [fp, #-8]
	ldr	r3, [fp, #-16]
	cmp	r2, r3
	blt	.L5
	mov	r3, #1
.L4:
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	isChekinPass, .-isChekinPass
	.section	.rodata
	.align	2
.LC0:
	.ascii	"Error\000"
	.align	2
.LC1:
	.ascii	"\012\347\254\254%d\347\276\244<\344\275\215\346\225"
	.ascii	"\270%d>:\012\000"
	.align	2
.LC2:
	.ascii	"%d \000"
	.align	2
.LC3:
	.ascii	"\000"
	.align	2
.LC4:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 4480
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #4480
	ldr	r3, .L42
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	mov	r3,#0
	sub	r3, fp, #4000
	sub	r3, r3, #4
	sub	r3, r3, #4
	mov	r2, #4000
	mov	r1, #0
	mov	r0, r3
	bl	memset
	mvn	r3, #0
	str	r3, [fp, #-4008]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	sub	r3, r3, #348
	mov	r2, #40
	mov	r1, #0
	mov	r0, r3
	bl	memset
	mov	r0, #0
	bl	time
	mov	r3, r0
	mov	r0, r3
	bl	srand
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-384]
	b	.L7
.L10:
	bl	rand
	mov	r2, r0
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r0, r3
	ldr	r3, .L42+4
	smull	r1, r3, r2, r3
	add	r3, r3, r2
	asr	r1, r3, #9
	asr	r3, r2, #31
	sub	r1, r1, r3
	mov	r3, r1
	lsl	r3, r3, #3
	sub	r3, r3, r1
	lsl	r3, r3, #4
	sub	r3, r3, r1
	lsl	r1, r3, #3
	add	r3, r3, r1
	sub	r3, r2, r3
	str	r3, [r0, #-352]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4352
	sub	r3, r3, #4
	sub	r3, r3, #52
	sub	r1, fp, #4096
	sub	r1, r1, #4
	mov	r0, r1
	ldr	r2, [r2, #-352]
	mov	r1, r3
	ldr	r0, [r0, #-384]
	bl	isChekinPass
	mov	r3, r0
	cmp	r3, #0
	beq	.L8
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-384]
	lsl	r3, r3, #2
	add	r3, r2, r3
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-352]
	str	r2, [r3, #-308]
	b	.L9
.L8:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-384]
	sub	r3, r3, #1
	str	r3, [r2, #-384]
.L9:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-384]
	add	r3, r3, #1
	str	r3, [r2, #-384]
.L7:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-384]
	cmp	r3, #99
	ble	.L10
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-380]
	b	.L11
.L25:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r1, [r3, #-308]
	ldr	r3, .L42+8
	smull	r2, r3, r1, r3
	asr	r2, r3, #2
	asr	r3, r1, #31
	sub	r2, r2, r3
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #1
	sub	r2, r1, r3
	cmp	r2, #9
	ldrls	pc, [pc, r2, asl #2]
	b	.L12
.L14:
	.word	.L23
	.word	.L22
	.word	.L21
	.word	.L20
	.word	.L19
	.word	.L18
	.word	.L17
	.word	.L16
	.word	.L15
	.word	.L13
.L23:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-348]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-348]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	lsl	r3, r2, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L22:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-344]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-344]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #100
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L21:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-340]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-340]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #200
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L20:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-336]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-336]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #300
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L19:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-332]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-332]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #400
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L18:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-328]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-328]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #500
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L17:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-324]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-324]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #600
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L16:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-320]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-320]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #700
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L15:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-316]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-316]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #800
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L13:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-312]
	add	r3, r2, #1
	sub	r1, fp, #4096
	sub	r1, r1, #4
	str	r3, [r1, #-312]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r1, [r3, #-308]
	add	r3, r2, #900
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	b	.L24
.L12:
	ldr	r0, .L42+12
	bl	puts
	nop
.L24:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	add	r3, r3, #1
	str	r3, [r2, #-380]
.L11:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-380]
	cmp	r3, #99
	ble	.L25
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-356]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-376]
	b	.L26
.L32:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-372]
	b	.L27
.L31:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-368]
	b	.L28
.L30:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-376]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r2, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-368]
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	ldr	r1, [r3, #-4004]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-368]
	add	r0, r3, #1
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-376]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r2, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r0
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	ldr	r3, [r3, #-4004]
	cmp	r1, r3
	ble	.L29
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r1, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-376]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r2, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-368]
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	ldr	r3, [r3, #-4004]
	str	r3, [r1, #-356]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-368]
	add	r1, r3, #1
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-376]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r2, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r1
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	ldr	r1, [r3, #-4004]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-376]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r2, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-368]
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	str	r1, [r3, #-4004]
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-368]
	add	r1, r3, #1
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-376]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r2, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r1
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-356]
	str	r2, [r3, #-4004]
.L29:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-368]
	add	r3, r3, #1
	str	r3, [r2, #-368]
.L28:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-376]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-348]
	sub	r3, r3, #1
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-368]
	cmp	r2, r3
	blt	.L30
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-372]
	add	r3, r3, #1
	str	r3, [r2, #-372]
.L27:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-376]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-348]
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-372]
	cmp	r2, r3
	blt	.L31
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-376]
	add	r3, r3, #1
	str	r3, [r2, #-376]
.L26:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-376]
	cmp	r3, #9
	ble	.L32
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-364]
	b	.L33
.L38:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r2, #-364]
	ldr	r1, [r3, #-364]
	ldr	r0, .L42+16
	bl	printf
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-360]
	b	.L34
.L37:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-364]
	lsl	r3, r3, #2
	add	r3, r2, r3
	ldr	r3, [r3, #-348]
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-360]
	cmp	r2, r3
	beq	.L41
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r2, [r3, #-364]
	mov	r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r2, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4096
	sub	r2, r2, #4
	ldr	r2, [r2, #-360]
	add	r3, r3, r2
	lsl	r3, r3, #2
	sub	r2, fp, #4
	add	r3, r2, r3
	ldr	r3, [r3, #-4004]
	mov	r1, r3
	ldr	r0, .L42+20
	bl	printf
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-360]
	add	r3, r3, #1
	str	r3, [r2, #-360]
.L34:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-360]
	cmp	r3, #99
	ble	.L37
	b	.L36
.L41:
	nop
.L36:
	ldr	r0, .L42+24
	bl	puts
	sub	r3, fp, #4096
	sub	r3, r3, #4
	mov	r2, r3
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-364]
	add	r3, r3, #1
	str	r3, [r2, #-364]
.L33:
	sub	r3, fp, #4096
	sub	r3, r3, #4
	ldr	r3, [r3, #-364]
	cmp	r3, #9
	ble	.L38
	mov	r3, #0
	ldr	r2, .L42
	ldr	r1, [r2]
	ldr	r2, [fp, #-8]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L40
	bl	__stack_chk_fail
.L40:
	mov	r0, r3
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L43:
	.align	2
.L42:
	.word	.LC4
	.word	-2093742815
	.word	1717986919
	.word	.LC0
	.word	.LC1
	.word	.LC2
	.word	.LC3
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
