	.file	"63700.c"
	.intel_syntax noprefix
	.text
	.globl	IFCOUNTER_COLLISIONS
	.bss
	.align 4
	.type	IFCOUNTER_COLLISIONS, @object
	.size	IFCOUNTER_COLLISIONS, 4
IFCOUNTER_COLLISIONS:
	.zero	4
	.globl	IFCOUNTER_IERRORS
	.align 4
	.type	IFCOUNTER_IERRORS, @object
	.size	IFCOUNTER_IERRORS, 4
IFCOUNTER_IERRORS:
	.zero	4
	.globl	IFCOUNTER_IPACKETS
	.align 4
	.type	IFCOUNTER_IPACKETS, @object
	.size	IFCOUNTER_IPACKETS, 4
IFCOUNTER_IPACKETS:
	.zero	4
	.globl	IFCOUNTER_OERRORS
	.align 4
	.type	IFCOUNTER_OERRORS, @object
	.size	IFCOUNTER_OERRORS, 4
IFCOUNTER_OERRORS:
	.zero	4
	.globl	IFCOUNTER_OPACKETS
	.align 4
	.type	IFCOUNTER_OPACKETS, @object
	.size	IFCOUNTER_OPACKETS, 4
IFCOUNTER_OPACKETS:
	.zero	4
	.globl	VGE_MIBCSR
	.align 4
	.type	VGE_MIBCSR, @object
	.size	VGE_MIBCSR, 4
VGE_MIBCSR:
	.zero	4
	.globl	VGE_MIBCSR_FLUSH
	.align 4
	.type	VGE_MIBCSR_FLUSH, @object
	.size	VGE_MIBCSR_FLUSH, 4
VGE_MIBCSR_FLUSH:
	.zero	4
	.globl	VGE_MIBCSR_RINI
	.align 4
	.type	VGE_MIBCSR_RINI, @object
	.size	VGE_MIBCSR_RINI, 4
VGE_MIBCSR_RINI:
	.zero	4
	.globl	VGE_MIBDATA
	.align 4
	.type	VGE_MIBDATA, @object
	.size	VGE_MIBDATA, 4
VGE_MIBDATA:
	.zero	4
	.globl	VGE_MIB_CNT
	.align 4
	.type	VGE_MIB_CNT, @object
	.size	VGE_MIB_CNT, 4
VGE_MIB_CNT:
	.zero	4
	.globl	VGE_MIB_DATA_MASK
	.align 4
	.type	VGE_MIB_DATA_MASK, @object
	.size	VGE_MIB_DATA_MASK, 4
VGE_MIB_DATA_MASK:
	.zero	4
	.globl	VGE_MIB_RX_ALIGNERRS
	.align 8
	.type	VGE_MIB_RX_ALIGNERRS, @object
	.size	VGE_MIB_RX_ALIGNERRS, 8
VGE_MIB_RX_ALIGNERRS:
	.zero	8
	.globl	VGE_MIB_RX_CRCERRS
	.align 8
	.type	VGE_MIB_RX_CRCERRS, @object
	.size	VGE_MIB_RX_CRCERRS, 8
VGE_MIB_RX_CRCERRS:
	.zero	8
	.globl	VGE_MIB_RX_FIFO_OVERRUNS
	.align 8
	.type	VGE_MIB_RX_FIFO_OVERRUNS, @object
	.size	VGE_MIB_RX_FIFO_OVERRUNS, 8
VGE_MIB_RX_FIFO_OVERRUNS:
	.zero	8
	.globl	VGE_MIB_RX_FRAMES
	.align 8
	.type	VGE_MIB_RX_FRAMES, @object
	.size	VGE_MIB_RX_FRAMES, 8
VGE_MIB_RX_FRAMES:
	.zero	8
	.globl	VGE_MIB_RX_GOOD_FRAMES
	.align 8
	.type	VGE_MIB_RX_GOOD_FRAMES, @object
	.size	VGE_MIB_RX_GOOD_FRAMES, 8
VGE_MIB_RX_GOOD_FRAMES:
	.zero	8
	.globl	VGE_MIB_RX_JUMBOS
	.align 8
	.type	VGE_MIB_RX_JUMBOS, @object
	.size	VGE_MIB_RX_JUMBOS, 8
VGE_MIB_RX_JUMBOS:
	.zero	8
	.globl	VGE_MIB_RX_LENERRS
	.align 8
	.type	VGE_MIB_RX_LENERRS, @object
	.size	VGE_MIB_RX_LENERRS, 8
VGE_MIB_RX_LENERRS:
	.zero	8
	.globl	VGE_MIB_RX_NOBUFS
	.align 8
	.type	VGE_MIB_RX_NOBUFS, @object
	.size	VGE_MIB_RX_NOBUFS, 8
VGE_MIB_RX_NOBUFS:
	.zero	8
	.globl	VGE_MIB_RX_PAUSE
	.align 8
	.type	VGE_MIB_RX_PAUSE, @object
	.size	VGE_MIB_RX_PAUSE, 8
VGE_MIB_RX_PAUSE:
	.zero	8
	.globl	VGE_MIB_RX_PKTS_1024_1518
	.align 8
	.type	VGE_MIB_RX_PKTS_1024_1518, @object
	.size	VGE_MIB_RX_PKTS_1024_1518, 8
VGE_MIB_RX_PKTS_1024_1518:
	.zero	8
	.globl	VGE_MIB_RX_PKTS_128_255
	.align 8
	.type	VGE_MIB_RX_PKTS_128_255, @object
	.size	VGE_MIB_RX_PKTS_128_255, 8
VGE_MIB_RX_PKTS_128_255:
	.zero	8
	.globl	VGE_MIB_RX_PKTS_1519_MAX
	.align 8
	.type	VGE_MIB_RX_PKTS_1519_MAX, @object
	.size	VGE_MIB_RX_PKTS_1519_MAX, 8
VGE_MIB_RX_PKTS_1519_MAX:
	.zero	8
	.globl	VGE_MIB_RX_PKTS_1519_MAX_ERRS
	.align 8
	.type	VGE_MIB_RX_PKTS_1519_MAX_ERRS, @object
	.size	VGE_MIB_RX_PKTS_1519_MAX_ERRS, 8
VGE_MIB_RX_PKTS_1519_MAX_ERRS:
	.zero	8
	.globl	VGE_MIB_RX_PKTS_256_511
	.align 8
	.type	VGE_MIB_RX_PKTS_256_511, @object
	.size	VGE_MIB_RX_PKTS_256_511, 8
VGE_MIB_RX_PKTS_256_511:
	.zero	8
	.globl	VGE_MIB_RX_PKTS_512_1023
	.align 8
	.type	VGE_MIB_RX_PKTS_512_1023, @object
	.size	VGE_MIB_RX_PKTS_512_1023, 8
VGE_MIB_RX_PKTS_512_1023:
	.zero	8
	.globl	VGE_MIB_RX_PKTS_64
	.align 8
	.type	VGE_MIB_RX_PKTS_64, @object
	.size	VGE_MIB_RX_PKTS_64, 8
VGE_MIB_RX_PKTS_64:
	.zero	8
	.globl	VGE_MIB_RX_PKTS_65_127
	.align 8
	.type	VGE_MIB_RX_PKTS_65_127, @object
	.size	VGE_MIB_RX_PKTS_65_127, 8
VGE_MIB_RX_PKTS_65_127:
	.zero	8
	.globl	VGE_MIB_RX_RUNTS
	.align 8
	.type	VGE_MIB_RX_RUNTS, @object
	.size	VGE_MIB_RX_RUNTS, 8
VGE_MIB_RX_RUNTS:
	.zero	8
	.globl	VGE_MIB_RX_RUNTS_ERRS
	.align 8
	.type	VGE_MIB_RX_RUNTS_ERRS, @object
	.size	VGE_MIB_RX_RUNTS_ERRS, 8
VGE_MIB_RX_RUNTS_ERRS:
	.zero	8
	.globl	VGE_MIB_RX_SYMERRS
	.align 8
	.type	VGE_MIB_RX_SYMERRS, @object
	.size	VGE_MIB_RX_SYMERRS, 8
VGE_MIB_RX_SYMERRS:
	.zero	8
	.globl	VGE_MIB_TX_COLLS
	.align 8
	.type	VGE_MIB_TX_COLLS, @object
	.size	VGE_MIB_TX_COLLS, 8
VGE_MIB_TX_COLLS:
	.zero	8
	.globl	VGE_MIB_TX_GOOD_FRAMES
	.align 8
	.type	VGE_MIB_TX_GOOD_FRAMES, @object
	.size	VGE_MIB_TX_GOOD_FRAMES, 8
VGE_MIB_TX_GOOD_FRAMES:
	.zero	8
	.globl	VGE_MIB_TX_JUMBOS
	.align 8
	.type	VGE_MIB_TX_JUMBOS, @object
	.size	VGE_MIB_TX_JUMBOS, 8
VGE_MIB_TX_JUMBOS:
	.zero	8
	.globl	VGE_MIB_TX_LATECOLLS
	.align 8
	.type	VGE_MIB_TX_LATECOLLS, @object
	.size	VGE_MIB_TX_LATECOLLS, 8
VGE_MIB_TX_LATECOLLS:
	.zero	8
	.globl	VGE_MIB_TX_PAUSE
	.align 8
	.type	VGE_MIB_TX_PAUSE, @object
	.size	VGE_MIB_TX_PAUSE, 8
VGE_MIB_TX_PAUSE:
	.zero	8
	.globl	VGE_MIB_TX_PKTS_1024_1518
	.align 8
	.type	VGE_MIB_TX_PKTS_1024_1518, @object
	.size	VGE_MIB_TX_PKTS_1024_1518, 8
VGE_MIB_TX_PKTS_1024_1518:
	.zero	8
	.globl	VGE_MIB_TX_PKTS_128_255
	.align 8
	.type	VGE_MIB_TX_PKTS_128_255, @object
	.size	VGE_MIB_TX_PKTS_128_255, 8
VGE_MIB_TX_PKTS_128_255:
	.zero	8
	.globl	VGE_MIB_TX_PKTS_256_511
	.align 8
	.type	VGE_MIB_TX_PKTS_256_511, @object
	.size	VGE_MIB_TX_PKTS_256_511, 8
VGE_MIB_TX_PKTS_256_511:
	.zero	8
	.globl	VGE_MIB_TX_PKTS_512_1023
	.align 8
	.type	VGE_MIB_TX_PKTS_512_1023, @object
	.size	VGE_MIB_TX_PKTS_512_1023, 8
VGE_MIB_TX_PKTS_512_1023:
	.zero	8
	.globl	VGE_MIB_TX_PKTS_64
	.align 8
	.type	VGE_MIB_TX_PKTS_64, @object
	.size	VGE_MIB_TX_PKTS_64, 8
VGE_MIB_TX_PKTS_64:
	.zero	8
	.globl	VGE_MIB_TX_PKTS_65_127
	.align 8
	.type	VGE_MIB_TX_PKTS_65_127, @object
	.size	VGE_MIB_TX_PKTS_65_127, 8
VGE_MIB_TX_PKTS_65_127:
	.zero	8
	.globl	VGE_MIB_TX_SQEERRS
	.align 8
	.type	VGE_MIB_TX_SQEERRS, @object
	.size	VGE_MIB_TX_SQEERRS, 8
VGE_MIB_TX_SQEERRS:
	.zero	8
	.globl	VGE_TIMEOUT
	.align 4
	.type	VGE_TIMEOUT, @object
	.size	VGE_TIMEOUT, 4
VGE_TIMEOUT:
	.zero	4
	.section	.rodata
.LC0:
	.string	"MIB counter dump timed out!\n"
	.text
	.type	vge_stats_update, @function
vge_stats_update:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	push	r12
	push	rbx
	sub	rsp, 64
	.cfi_offset 12, -24
	.cfi_offset 3, -32
	mov	QWORD PTR -72[rbp], rdi
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -24[rbp], rax
	xor	eax, eax
	mov	rax, rsp
	mov	r12, rax
	mov	ebx, DWORD PTR VGE_MIB_CNT[rip]
	movsx	rax, ebx
	sub	rax, 1
	mov	QWORD PTR -56[rbp], rax
	movsx	rax, ebx
	mov	r10, rax
	mov	r11d, 0
	movsx	rax, ebx
	mov	r8, rax
	mov	r9d, 0
	movsx	rax, ebx
	lea	rdx, 0[0+rax*4]
	mov	eax, 16
	sub	rax, 1
	add	rax, rdx
	mov	esi, 16
	mov	edx, 0
	div	rsi
	imul	rax, rax, 16
	mov	rcx, rax
	and	rcx, -4096
	mov	rdx, rsp
	sub	rdx, rcx
.L2:
	cmp	rsp, rdx
	je	.L3
	sub	rsp, 4096
	or	QWORD PTR 4088[rsp], 0
	jmp	.L2
.L3:
	mov	rdx, rax
	and	edx, 4095
	sub	rsp, rdx
	mov	rdx, rax
	and	edx, 4095
	test	rdx, rdx
	je	.L4
	and	eax, 4095
	sub	rax, 8
	add	rax, rsp
	or	QWORD PTR [rax], 0
.L4:
	mov	rax, rsp
	add	rax, 3
	shr	rax, 2
	sal	rax, 2
	mov	QWORD PTR -48[rbp], rax
	mov	rax, QWORD PTR -72[rbp]
	mov	rdi, rax
	call	VGE_LOCK_ASSERT@PLT
	mov	rax, QWORD PTR -72[rbp]
	add	rax, 16
	mov	QWORD PTR -40[rbp], rax
	mov	rax, QWORD PTR -72[rbp]
	mov	rax, QWORD PTR 8[rax]
	mov	QWORD PTR -32[rbp], rax
	mov	edx, DWORD PTR VGE_MIBCSR[rip]
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	CSR_READ_1@PLT
	mov	edx, DWORD PTR VGE_MIBCSR_FLUSH[rip]
	or	edx, eax
	mov	ecx, DWORD PTR VGE_MIBCSR[rip]
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	CSR_WRITE_1@PLT
	mov	eax, DWORD PTR VGE_TIMEOUT[rip]
	mov	DWORD PTR -64[rbp], eax
	jmp	.L5
.L8:
	mov	edi, 1
	call	DELAY@PLT
	mov	edx, DWORD PTR VGE_MIBCSR[rip]
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	CSR_READ_1@PLT
	mov	edx, DWORD PTR VGE_MIBCSR_FLUSH[rip]
	and	eax, edx
	test	eax, eax
	je	.L16
	sub	DWORD PTR -64[rbp], 1
.L5:
	cmp	DWORD PTR -64[rbp], 0
	jg	.L8
	jmp	.L7
.L16:
	nop
.L7:
	cmp	DWORD PTR -64[rbp], 0
	jne	.L9
	mov	rax, QWORD PTR -72[rbp]
	mov	eax, DWORD PTR [rax]
	lea	rsi, .LC0[rip]
	mov	edi, eax
	call	device_printf@PLT
	mov	rax, QWORD PTR -72[rbp]
	mov	rdi, rax
	call	vge_stats_clear@PLT
	mov	rsp, r12
	jmp	.L1
.L9:
	movsx	rax, ebx
	sal	eax, 2
	mov	edx, eax
	mov	rax, QWORD PTR -48[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	bzero@PLT
.L11:
	mov	edx, DWORD PTR VGE_MIBCSR[rip]
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	CSR_READ_1@PLT
	mov	edx, DWORD PTR VGE_MIBCSR_RINI[rip]
	or	edx, eax
	mov	ecx, DWORD PTR VGE_MIBCSR[rip]
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	CSR_WRITE_1@PLT
	mov	DWORD PTR -64[rbp], 0
	jmp	.L12
.L14:
	mov	edx, DWORD PTR VGE_MIBDATA[rip]
	mov	rax, QWORD PTR -72[rbp]
	mov	esi, edx
	mov	rdi, rax
	call	CSR_READ_4@PLT
	mov	DWORD PTR -60[rbp], eax
	mov	eax, DWORD PTR -60[rbp]
	mov	edi, eax
	call	VGE_MIB_DATA_IDX@PLT
	cmp	DWORD PTR -64[rbp], eax
	je	.L13
	jmp	.L11
.L13:
	mov	eax, DWORD PTR VGE_MIB_DATA_MASK[rip]
	and	eax, DWORD PTR -60[rbp]
	mov	ecx, eax
	mov	rax, QWORD PTR -48[rbp]
	mov	edx, DWORD PTR -64[rbp]
	movsx	rdx, edx
	mov	DWORD PTR [rax+rdx*4], ecx
	add	DWORD PTR -64[rbp], 1
.L12:
	mov	eax, DWORD PTR VGE_MIB_CNT[rip]
	cmp	DWORD PTR -64[rbp], eax
	jl	.L14
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR [rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_FRAMES[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 4[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_GOOD_FRAMES[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 4[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 8[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_FIFO_OVERRUNS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 8[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 12[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_RUNTS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 12[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 16[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_RUNTS_ERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 16[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 20[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PKTS_64[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 20[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 24[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PKTS_65_127[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 24[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 28[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PKTS_128_255[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 28[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 32[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PKTS_256_511[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 32[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 36[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PKTS_512_1023[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 36[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 40[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PKTS_1024_1518[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 40[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 44[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PKTS_1519_MAX[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 44[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 48[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PKTS_1519_MAX_ERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 48[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 52[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_JUMBOS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 52[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 56[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_CRCERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 56[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 60[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_PAUSE[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 60[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 64[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_ALIGNERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 64[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 68[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_NOBUFS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 68[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 72[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_SYMERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 72[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 76[rax]
	mov	rdx, QWORD PTR VGE_MIB_RX_LENERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 76[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 80[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_GOOD_FRAMES[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 80[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 84[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_PKTS_64[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 84[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 88[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_PKTS_65_127[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 88[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 92[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_PKTS_128_255[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 92[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 96[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_PKTS_256_511[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 96[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 100[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_PKTS_512_1023[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 100[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 104[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_PKTS_1024_1518[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 104[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 108[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_JUMBOS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 108[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 112[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_COLLS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 112[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 116[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_PAUSE[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 116[rax], edx
	mov	rax, QWORD PTR -40[rbp]
	mov	ecx, DWORD PTR 124[rax]
	mov	rdx, QWORD PTR VGE_MIB_TX_LATECOLLS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	rax, QWORD PTR -40[rbp]
	mov	DWORD PTR 124[rax], edx
	mov	rdx, QWORD PTR VGE_MIB_TX_GOOD_FRAMES[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	edx, DWORD PTR [rax+rdx*4]
	mov	ecx, DWORD PTR IFCOUNTER_OPACKETS[rip]
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	if_inc_counter@PLT
	mov	rdx, QWORD PTR VGE_MIB_TX_COLLS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	ecx, DWORD PTR [rax+rdx*4]
	mov	rdx, QWORD PTR VGE_MIB_TX_LATECOLLS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	ecx, DWORD PTR IFCOUNTER_COLLISIONS[rip]
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	if_inc_counter@PLT
	mov	rdx, QWORD PTR VGE_MIB_TX_COLLS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	ecx, DWORD PTR [rax+rdx*4]
	mov	rdx, QWORD PTR VGE_MIB_TX_LATECOLLS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	ecx, DWORD PTR IFCOUNTER_OERRORS[rip]
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	if_inc_counter@PLT
	mov	rdx, QWORD PTR VGE_MIB_RX_GOOD_FRAMES[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	edx, DWORD PTR [rax+rdx*4]
	mov	ecx, DWORD PTR IFCOUNTER_IPACKETS[rip]
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	if_inc_counter@PLT
	mov	rdx, QWORD PTR VGE_MIB_RX_FIFO_OVERRUNS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	ecx, DWORD PTR [rax+rdx*4]
	mov	rdx, QWORD PTR VGE_MIB_RX_RUNTS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	add	ecx, eax
	mov	rdx, QWORD PTR VGE_MIB_RX_RUNTS_ERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	add	ecx, eax
	mov	rdx, QWORD PTR VGE_MIB_RX_CRCERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	add	ecx, eax
	mov	rdx, QWORD PTR VGE_MIB_RX_ALIGNERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	add	ecx, eax
	mov	rdx, QWORD PTR VGE_MIB_RX_NOBUFS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	add	ecx, eax
	mov	rdx, QWORD PTR VGE_MIB_RX_SYMERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	add	ecx, eax
	mov	rdx, QWORD PTR VGE_MIB_RX_LENERRS[rip]
	mov	rax, QWORD PTR -48[rbp]
	mov	eax, DWORD PTR [rax+rdx*4]
	lea	edx, [rcx+rax]
	mov	ecx, DWORD PTR IFCOUNTER_IERRORS[rip]
	mov	rax, QWORD PTR -32[rbp]
	mov	esi, ecx
	mov	rdi, rax
	call	if_inc_counter@PLT
	mov	rsp, r12
.L1:
	mov	rax, QWORD PTR -24[rbp]
	sub	rax, QWORD PTR fs:40
	je	.L15
	call	__stack_chk_fail@PLT
.L15:
	lea	rsp, -16[rbp]
	pop	rbx
	pop	r12
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	vge_stats_update, .-vge_stats_update
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"63700.c"
	.text
	.comm	IFCOUNTER_COLLISIONS,4,4
	.comm	IFCOUNTER_IERRORS,4,4
	.comm	IFCOUNTER_IPACKETS,4,4
	.comm	IFCOUNTER_OERRORS,4,4
	.comm	IFCOUNTER_OPACKETS,4,4
	.comm	VGE_MIBCSR,4,4
	.comm	VGE_MIBCSR_FLUSH,4,4
	.comm	VGE_MIBCSR_RINI,4,4
	.comm	VGE_MIBDATA,4,4
	.comm	VGE_MIB_CNT,4,4
	.comm	VGE_MIB_DATA_MASK,4,4
	.comm	VGE_MIB_RX_ALIGNERRS,4,4
	.comm	VGE_MIB_RX_CRCERRS,4,4
	.comm	VGE_MIB_RX_FIFO_OVERRUNS,4,4
	.comm	VGE_MIB_RX_FRAMES,4,4
	.comm	VGE_MIB_RX_GOOD_FRAMES,4,4
	.comm	VGE_MIB_RX_JUMBOS,4,4
	.comm	VGE_MIB_RX_LENERRS,4,4
	.comm	VGE_MIB_RX_NOBUFS,4,4
	.comm	VGE_MIB_RX_PAUSE,4,4
	.comm	VGE_MIB_RX_PKTS_1024_1518,4,4
	.comm	VGE_MIB_RX_PKTS_128_255,4,4
	.comm	VGE_MIB_RX_PKTS_1519_MAX,4,4
	.comm	VGE_MIB_RX_PKTS_1519_MAX_ERRS,4,4
	.comm	VGE_MIB_RX_PKTS_256_511,4,4
	.comm	VGE_MIB_RX_PKTS_512_1023,4,4
	.comm	VGE_MIB_RX_PKTS_64,4,4
	.comm	VGE_MIB_RX_PKTS_65_127,4,4
	.comm	VGE_MIB_RX_RUNTS,4,4
	.comm	VGE_MIB_RX_RUNTS_ERRS,4,4
	.comm	VGE_MIB_RX_SYMERRS,4,4
	.comm	VGE_MIB_TX_COLLS,4,4
	.comm	VGE_MIB_TX_GOOD_FRAMES,4,4
	.comm	VGE_MIB_TX_JUMBOS,4,4
	.comm	VGE_MIB_TX_LATECOLLS,4,4
	.comm	VGE_MIB_TX_PAUSE,4,4
	.comm	VGE_MIB_TX_PKTS_1024_1518,4,4
	.comm	VGE_MIB_TX_PKTS_128_255,4,4
	.comm	VGE_MIB_TX_PKTS_256_511,4,4
	.comm	VGE_MIB_TX_PKTS_512_1023,4,4
	.comm	VGE_MIB_TX_PKTS_64,4,4
	.comm	VGE_MIB_TX_PKTS_65_127,4,4
	.comm	VGE_MIB_TX_SQEERRS,4,4
	.comm	VGE_TIMEOUT,4,4
	.section	.rodata
	.align	2
.LC0:
	.ascii	"MIB counter dump timed out!\012\000"
	.align	2
.LC1:
	.word	__stack_chk_guard
	.text
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	vge_stats_update, %function
vge_stats_update:
	@ args = 0, pretend = 0, frame = 40
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, fp, lr}
	add	fp, sp, #16
	sub	sp, sp, #44
	str	r0, [fp, #-56]
	ldr	r3, .L14
	ldr	r3, [r3]
	str	r3, [fp, #-24]
	mov	r3,#0
	mov	r3, sp
	mov	r6, r3
	ldr	r3, .L14+4
	ldr	r4, [r3]
	sub	r3, r4, #1
	str	r3, [fp, #-44]
	mov	r3, r4
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #5
	orr	r3, r3, r0, lsr #27
	lsl	r2, r0, #5
	mov	r3, r4
	mov	r0, r3
	mov	r1, #0
	mov	r2, #0
	mov	r3, #0
	lsl	r3, r1, #5
	orr	r3, r3, r0, lsr #27
	lsl	r2, r0, #5
	mov	r3, r4
	lsl	r3, r3, #2
	add	r3, r3, #7
	lsr	r3, r3, #3
	lsl	r3, r3, #3
	sub	sp, sp, r3
	mov	r3, sp
	add	r3, r3, #3
	lsr	r3, r3, #2
	lsl	r3, r3, #2
	str	r3, [fp, #-40]
	ldr	r0, [fp, #-56]
	bl	VGE_LOCK_ASSERT
	ldr	r3, [fp, #-56]
	add	r3, r3, #8
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-56]
	ldr	r3, [r3, #4]
	str	r3, [fp, #-32]
	ldr	r3, .L14+8
	ldr	r5, [r3]
	ldr	r3, .L14+8
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, [fp, #-56]
	bl	CSR_READ_1
	mov	r2, r0
	ldr	r3, .L14+12
	ldr	r3, [r3]
	orr	r3, r2, r3
	mov	r2, r3
	mov	r1, r5
	ldr	r0, [fp, #-56]
	bl	CSR_WRITE_1
	ldr	r3, .L14+16
	ldr	r3, [r3]
	str	r3, [fp, #-48]
	b	.L2
.L5:
	mov	r0, #1
	bl	DELAY
	ldr	r3, .L14+8
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, [fp, #-56]
	bl	CSR_READ_1
	mov	r2, r0
	ldr	r3, .L14+12
	ldr	r3, [r3]
	and	r3, r3, r2
	cmp	r3, #0
	beq	.L13
	ldr	r3, [fp, #-48]
	sub	r3, r3, #1
	str	r3, [fp, #-48]
.L2:
	ldr	r3, [fp, #-48]
	cmp	r3, #0
	bgt	.L5
	b	.L4
.L13:
	nop
.L4:
	ldr	r3, [fp, #-48]
	cmp	r3, #0
	bne	.L6
	ldr	r3, [fp, #-56]
	ldr	r3, [r3]
	ldr	r1, .L14+20
	mov	r0, r3
	bl	device_printf
	ldr	r0, [fp, #-56]
	bl	vge_stats_clear
	mov	sp, r6
	b	.L1
.L6:
	mov	r3, r4
	lsl	r3, r3, #2
	mov	r1, r3
	ldr	r0, [fp, #-40]
	bl	bzero
.L8:
	ldr	r3, .L14+8
	ldr	r4, [r3]
	ldr	r3, .L14+8
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, [fp, #-56]
	bl	CSR_READ_1
	mov	r2, r0
	ldr	r3, .L14+24
	ldr	r3, [r3]
	orr	r3, r2, r3
	mov	r2, r3
	mov	r1, r4
	ldr	r0, [fp, #-56]
	bl	CSR_WRITE_1
	mov	r3, #0
	str	r3, [fp, #-48]
	b	.L9
.L11:
	ldr	r3, .L14+28
	ldr	r3, [r3]
	mov	r1, r3
	ldr	r0, [fp, #-56]
	bl	CSR_READ_4
	str	r0, [fp, #-28]
	ldr	r0, [fp, #-28]
	bl	VGE_MIB_DATA_IDX
	mov	r2, r0
	ldr	r3, [fp, #-48]
	cmp	r3, r2
	beq	.L10
	b	.L8
.L10:
	ldr	r3, .L14+32
	ldr	r2, [r3]
	ldr	r3, [fp, #-28]
	and	r1, r2, r3
	ldr	r3, [fp, #-40]
	ldr	r2, [fp, #-48]
	str	r1, [r3, r2, lsl #2]
	ldr	r3, [fp, #-48]
	add	r3, r3, #1
	str	r3, [fp, #-48]
.L9:
	ldr	r3, .L14+4
	ldr	r3, [r3]
	ldr	r2, [fp, #-48]
	cmp	r2, r3
	blt	.L11
	ldr	r3, [fp, #-36]
	ldr	r2, [r3]
	ldr	r3, .L14+36
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #4]
	ldr	r3, .L14+40
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #4]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #8]
	ldr	r3, .L14+44
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #8]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #12]
	ldr	r3, .L14+48
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #12]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #16]
	ldr	r3, .L14+52
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #16]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #20]
	ldr	r3, .L14+56
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #20]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #24]
	ldr	r3, .L14+60
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #24]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #28]
	ldr	r3, .L14+64
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #28]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #32]
	ldr	r3, .L14+68
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #32]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #36]
	ldr	r3, .L14+72
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #36]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #40]
	ldr	r3, .L14+76
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #40]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #44]
	ldr	r3, .L14+80
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #44]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #48]
	ldr	r3, .L14+84
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #48]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #52]
	ldr	r3, .L14+88
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #52]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #56]
	ldr	r3, .L14+92
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #56]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #60]
	ldr	r3, .L14+96
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #60]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #64]
	ldr	r3, .L14+100
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #64]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #68]
	ldr	r3, .L14+104
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #68]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #72]
	ldr	r3, .L14+108
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #72]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #76]
	ldr	r3, .L14+112
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #76]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #80]
	ldr	r3, .L14+116
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #80]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #84]
	ldr	r3, .L14+120
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #84]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #88]
	ldr	r3, .L14+124
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #88]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #92]
	ldr	r3, .L14+128
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #92]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #96]
	ldr	r3, .L14+132
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #96]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #100]
	ldr	r3, .L14+136
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #100]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #104]
	ldr	r3, .L14+140
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #104]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #108]
	ldr	r3, .L14+144
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #108]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #112]
	ldr	r3, .L14+148
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #112]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #116]
	ldr	r3, .L14+152
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #116]
	ldr	r3, [fp, #-36]
	ldr	r2, [r3, #124]
	ldr	r3, .L14+156
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, [fp, #-36]
	str	r2, [r3, #124]
	ldr	r3, .L14+160
	ldr	r1, [r3]
	ldr	r3, .L14+116
	ldr	r2, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r2, lsl #2]
	mov	r2, r3
	ldr	r0, [fp, #-32]
	bl	if_inc_counter
	ldr	r3, .L14+164
	ldr	r0, [r3]
	ldr	r3, .L14+148
	ldr	r2, [r3]
	ldr	r3, [fp, #-40]
	ldr	r2, [r3, r2, lsl #2]
	ldr	r3, .L14+156
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r3, r2, r3
	mov	r2, r3
	mov	r1, r0
	ldr	r0, [fp, #-32]
	bl	if_inc_counter
	ldr	r3, .L14+168
	ldr	r0, [r3]
	ldr	r3, .L14+148
	ldr	r2, [r3]
	ldr	r3, [fp, #-40]
	ldr	r2, [r3, r2, lsl #2]
	ldr	r3, .L14+156
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r3, r2, r3
	mov	r2, r3
	mov	r1, r0
	ldr	r0, [fp, #-32]
	bl	if_inc_counter
	ldr	r3, .L14+172
	ldr	r1, [r3]
	ldr	r3, .L14+40
	ldr	r2, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r2, lsl #2]
	mov	r2, r3
	ldr	r0, [fp, #-32]
	bl	if_inc_counter
	ldr	r3, .L14+176
	ldr	r0, [r3]
	ldr	r3, .L14+44
	ldr	r2, [r3]
	ldr	r3, [fp, #-40]
	ldr	r2, [r3, r2, lsl #2]
	ldr	r3, .L14+48
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, .L14+52
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, .L14+92
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, .L14+100
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, .L14+104
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, .L14+108
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r2, r2, r3
	ldr	r3, .L14+112
	ldr	r1, [r3]
	ldr	r3, [fp, #-40]
	ldr	r3, [r3, r1, lsl #2]
	add	r3, r2, r3
	mov	r2, r3
	mov	r1, r0
	ldr	r0, [fp, #-32]
	bl	if_inc_counter
	mov	sp, r6
.L1:
	ldr	r3, .L14
	ldr	r2, [r3]
	ldr	r3, [fp, #-24]
	eors	r2, r3, r2
	mov	r3, #0
	beq	.L12
	bl	__stack_chk_fail
.L12:
	sub	sp, fp, #16
	@ sp needed
	pop	{r4, r5, r6, fp, pc}
.L15:
	.align	2
.L14:
	.word	.LC1
	.word	VGE_MIB_CNT
	.word	VGE_MIBCSR
	.word	VGE_MIBCSR_FLUSH
	.word	VGE_TIMEOUT
	.word	.LC0
	.word	VGE_MIBCSR_RINI
	.word	VGE_MIBDATA
	.word	VGE_MIB_DATA_MASK
	.word	VGE_MIB_RX_FRAMES
	.word	VGE_MIB_RX_GOOD_FRAMES
	.word	VGE_MIB_RX_FIFO_OVERRUNS
	.word	VGE_MIB_RX_RUNTS
	.word	VGE_MIB_RX_RUNTS_ERRS
	.word	VGE_MIB_RX_PKTS_64
	.word	VGE_MIB_RX_PKTS_65_127
	.word	VGE_MIB_RX_PKTS_128_255
	.word	VGE_MIB_RX_PKTS_256_511
	.word	VGE_MIB_RX_PKTS_512_1023
	.word	VGE_MIB_RX_PKTS_1024_1518
	.word	VGE_MIB_RX_PKTS_1519_MAX
	.word	VGE_MIB_RX_PKTS_1519_MAX_ERRS
	.word	VGE_MIB_RX_JUMBOS
	.word	VGE_MIB_RX_CRCERRS
	.word	VGE_MIB_RX_PAUSE
	.word	VGE_MIB_RX_ALIGNERRS
	.word	VGE_MIB_RX_NOBUFS
	.word	VGE_MIB_RX_SYMERRS
	.word	VGE_MIB_RX_LENERRS
	.word	VGE_MIB_TX_GOOD_FRAMES
	.word	VGE_MIB_TX_PKTS_64
	.word	VGE_MIB_TX_PKTS_65_127
	.word	VGE_MIB_TX_PKTS_128_255
	.word	VGE_MIB_TX_PKTS_256_511
	.word	VGE_MIB_TX_PKTS_512_1023
	.word	VGE_MIB_TX_PKTS_1024_1518
	.word	VGE_MIB_TX_JUMBOS
	.word	VGE_MIB_TX_COLLS
	.word	VGE_MIB_TX_PAUSE
	.word	VGE_MIB_TX_LATECOLLS
	.word	IFCOUNTER_OPACKETS
	.word	IFCOUNTER_COLLISIONS
	.word	IFCOUNTER_OERRORS
	.word	IFCOUNTER_IPACKETS
	.word	IFCOUNTER_IERRORS
	.size	vge_stats_update, .-vge_stats_update
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
