	.file	"437729.c"
	.intel_syntax noprefix
	.text
	.globl	is_vertical
	.type	is_vertical, @function
is_vertical:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	rax, rdi
	mov	rcx, rsi
	mov	rdx, rcx
	mov	QWORD PTR -16[rbp], rax
	mov	QWORD PTR -8[rbp], rdx
	mov	edx, DWORD PTR -16[rbp]
	mov	eax, DWORD PTR -8[rbp]
	cmp	edx, eax
	sete	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	is_vertical, .-is_vertical
	.globl	is_horizontal
	.type	is_horizontal, @function
is_horizontal:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	rax, rdi
	mov	rcx, rsi
	mov	rdx, rcx
	mov	QWORD PTR -16[rbp], rax
	mov	QWORD PTR -8[rbp], rdx
	mov	edx, DWORD PTR -12[rbp]
	mov	eax, DWORD PTR -4[rbp]
	cmp	edx, eax
	sete	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	is_horizontal, .-is_horizontal
	.globl	swap_if_unordered
	.type	swap_if_unordered, @function
swap_if_unordered:
.LFB2:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	mov	QWORD PTR -24[rbp], rdi
	mov	QWORD PTR -32[rbp], rsi
	mov	rax, QWORD PTR -24[rbp]
	mov	edx, DWORD PTR [rax]
	mov	rax, QWORD PTR -32[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	edx, eax
	jle	.L6
	mov	rax, QWORD PTR -24[rbp]
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -4[rbp], eax
	mov	rax, QWORD PTR -32[rbp]
	mov	edx, DWORD PTR [rax]
	mov	rax, QWORD PTR -24[rbp]
	mov	DWORD PTR [rax], edx
	mov	rax, QWORD PTR -32[rbp]
	mov	edx, DWORD PTR -4[rbp]
	mov	DWORD PTR [rax], edx
	mov	eax, 1
	jmp	.L7
.L6:
	mov	eax, 0
.L7:
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE2:
	.size	swap_if_unordered, .-swap_if_unordered
	.section	.rodata
.LC0:
	.string	"r"
.LC1:
	.string	"inputs/input5"
.LC2:
	.string	"%d,%d -> %d,%d"
.LC3:
	.string	"%d\n"
	.text
	.globl	main
	.type	main, @function
main:
.LFB3:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	lea	r11, -4079616[rsp]
.LPSRL0:
	sub	rsp, 4096
	or	DWORD PTR [rsp], 0
	cmp	rsp, r11
	jne	.LPSRL0
	sub	rsp, 464
	mov	rax, QWORD PTR fs:40
	mov	QWORD PTR -8[rbp], rax
	xor	eax, eax
	lea	rsi, .LC0[rip]
	lea	rdi, .LC1[rip]
	call	fopen@PLT
	mov	QWORD PTR -4080024[rbp], rax
	mov	DWORD PTR -4080068[rbp], 0
	jmp	.L9
.L10:
	add	DWORD PTR -4080068[rbp], 1
.L9:
	lea	rdx, -4080016[rbp]
	mov	eax, DWORD PTR -4080068[rbp]
	cdqe
	sal	rax, 4
	add	rax, rdx
	lea	rdi, 12[rax]
	lea	rdx, -4080016[rbp]
	mov	eax, DWORD PTR -4080068[rbp]
	cdqe
	sal	rax, 4
	add	rax, rdx
	lea	rsi, 8[rax]
	lea	rdx, -4080016[rbp]
	mov	eax, DWORD PTR -4080068[rbp]
	cdqe
	sal	rax, 4
	add	rax, rdx
	lea	rcx, 4[rax]
	lea	rdx, -4080016[rbp]
	mov	eax, DWORD PTR -4080068[rbp]
	cdqe
	sal	rax, 4
	add	rdx, rax
	mov	rax, QWORD PTR -4080024[rbp]
	mov	r9, rdi
	mov	r8, rsi
	lea	rsi, .LC2[rip]
	mov	rdi, rax
	mov	eax, 0
	call	__isoc99_fscanf@PLT
	cmp	eax, -1
	jne	.L10
	lea	rax, -4000016[rbp]
	mov	edx, 4000000
	mov	esi, 0
	mov	rdi, rax
	call	memset@PLT
	mov	DWORD PTR -4080064[rbp], 0
	jmp	.L11
.L28:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080016
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR 8[rax]
	mov	rdi, rdx
	mov	rsi, rax
	call	is_vertical
	test	al, al
	je	.L12
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080012
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -4080076[rbp], eax
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080004
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -4080072[rbp], eax
	lea	rdx, -4080072[rbp]
	lea	rax, -4080076[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	swap_if_unordered
	mov	eax, DWORD PTR -4080076[rbp]
	mov	DWORD PTR -4080060[rbp], eax
	jmp	.L13
.L14:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080016
	mov	eax, DWORD PTR [rax]
	mov	edx, DWORD PTR -4080060[rbp]
	movsx	rcx, edx
	movsx	rdx, eax
	imul	rdx, rdx, 1000
	add	rdx, rcx
	mov	edx, DWORD PTR -4000016[rbp+rdx*4]
	add	edx, 1
	mov	ecx, DWORD PTR -4080060[rbp]
	movsx	rcx, ecx
	cdqe
	imul	rax, rax, 1000
	add	rax, rcx
	mov	DWORD PTR -4000016[rbp+rax*4], edx
	add	DWORD PTR -4080060[rbp], 1
.L13:
	mov	eax, DWORD PTR -4080072[rbp]
	cmp	DWORD PTR -4080060[rbp], eax
	jle	.L14
	jmp	.L15
.L12:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080016
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR 8[rax]
	mov	rdi, rdx
	mov	rsi, rax
	call	is_horizontal
	test	al, al
	je	.L16
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080016
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -4080076[rbp], eax
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080008
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -4080072[rbp], eax
	lea	rdx, -4080072[rbp]
	lea	rax, -4080076[rbp]
	mov	rsi, rdx
	mov	rdi, rax
	call	swap_if_unordered
	mov	eax, DWORD PTR -4080076[rbp]
	mov	DWORD PTR -4080056[rbp], eax
	jmp	.L17
.L18:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080012
	mov	eax, DWORD PTR [rax]
	movsx	rcx, eax
	mov	edx, DWORD PTR -4080056[rbp]
	movsx	rdx, edx
	imul	rdx, rdx, 1000
	add	rdx, rcx
	mov	edx, DWORD PTR -4000016[rbp+rdx*4]
	add	edx, 1
	movsx	rcx, eax
	mov	eax, DWORD PTR -4080056[rbp]
	cdqe
	imul	rax, rax, 1000
	add	rax, rcx
	mov	DWORD PTR -4000016[rbp+rax*4], edx
	add	DWORD PTR -4080056[rbp], 1
.L17:
	mov	eax, DWORD PTR -4080072[rbp]
	cmp	DWORD PTR -4080056[rbp], eax
	jle	.L18
	jmp	.L15
.L16:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080016
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -4080032[rbp], eax
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080008
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -4080028[rbp], eax
	mov	eax, DWORD PTR -4080032[rbp]
	cmp	eax, DWORD PTR -4080028[rbp]
	jle	.L19
	mov	eax, DWORD PTR -4080032[rbp]
	mov	DWORD PTR -4080052[rbp], eax
	jmp	.L20
.L23:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080012
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080004
	mov	eax, DWORD PTR [rax]
	cmp	edx, eax
	jle	.L21
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080012
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR -4080032[rbp]
	sub	eax, DWORD PTR -4080052[rbp]
	mov	ecx, eax
	mov	eax, edx
	sub	eax, ecx
	movsx	rcx, eax
	mov	edx, DWORD PTR -4080052[rbp]
	movsx	rdx, edx
	imul	rdx, rdx, 1000
	add	rdx, rcx
	mov	edx, DWORD PTR -4000016[rbp+rdx*4]
	add	edx, 1
	movsx	rcx, eax
	mov	eax, DWORD PTR -4080052[rbp]
	cdqe
	imul	rax, rax, 1000
	add	rax, rcx
	mov	DWORD PTR -4000016[rbp+rax*4], edx
	jmp	.L22
.L21:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080012
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR -4080032[rbp]
	sub	eax, DWORD PTR -4080052[rbp]
	add	eax, edx
	movsx	rcx, eax
	mov	edx, DWORD PTR -4080052[rbp]
	movsx	rdx, edx
	imul	rdx, rdx, 1000
	add	rdx, rcx
	mov	edx, DWORD PTR -4000016[rbp+rdx*4]
	add	edx, 1
	movsx	rcx, eax
	mov	eax, DWORD PTR -4080052[rbp]
	cdqe
	imul	rax, rax, 1000
	add	rax, rcx
	mov	DWORD PTR -4000016[rbp+rax*4], edx
.L22:
	sub	DWORD PTR -4080052[rbp], 1
.L20:
	mov	eax, DWORD PTR -4080052[rbp]
	cmp	eax, DWORD PTR -4080028[rbp]
	jge	.L23
	jmp	.L15
.L19:
	mov	eax, DWORD PTR -4080032[rbp]
	mov	DWORD PTR -4080048[rbp], eax
	jmp	.L24
.L27:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080012
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080004
	mov	eax, DWORD PTR [rax]
	cmp	edx, eax
	jle	.L25
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080012
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR -4080048[rbp]
	sub	eax, DWORD PTR -4080032[rbp]
	mov	ecx, eax
	mov	eax, edx
	sub	eax, ecx
	movsx	rcx, eax
	mov	edx, DWORD PTR -4080048[rbp]
	movsx	rdx, edx
	imul	rdx, rdx, 1000
	add	rdx, rcx
	mov	edx, DWORD PTR -4000016[rbp+rdx*4]
	add	edx, 1
	movsx	rcx, eax
	mov	eax, DWORD PTR -4080048[rbp]
	cdqe
	imul	rax, rax, 1000
	add	rax, rcx
	mov	DWORD PTR -4000016[rbp+rax*4], edx
	jmp	.L26
.L25:
	mov	eax, DWORD PTR -4080064[rbp]
	cdqe
	sal	rax, 4
	add	rax, rbp
	sub	rax, 4080012
	mov	edx, DWORD PTR [rax]
	mov	eax, DWORD PTR -4080048[rbp]
	sub	eax, DWORD PTR -4080032[rbp]
	add	eax, edx
	movsx	rcx, eax
	mov	edx, DWORD PTR -4080048[rbp]
	movsx	rdx, edx
	imul	rdx, rdx, 1000
	add	rdx, rcx
	mov	edx, DWORD PTR -4000016[rbp+rdx*4]
	add	edx, 1
	movsx	rcx, eax
	mov	eax, DWORD PTR -4080048[rbp]
	cdqe
	imul	rax, rax, 1000
	add	rax, rcx
	mov	DWORD PTR -4000016[rbp+rax*4], edx
.L26:
	add	DWORD PTR -4080048[rbp], 1
.L24:
	mov	eax, DWORD PTR -4080048[rbp]
	cmp	eax, DWORD PTR -4080028[rbp]
	jle	.L27
.L15:
	add	DWORD PTR -4080064[rbp], 1
.L11:
	mov	eax, DWORD PTR -4080064[rbp]
	cmp	eax, DWORD PTR -4080068[rbp]
	jl	.L28
	mov	DWORD PTR -4080044[rbp], 0
	mov	DWORD PTR -4080040[rbp], 0
	jmp	.L29
.L33:
	mov	DWORD PTR -4080036[rbp], 0
	jmp	.L30
.L32:
	mov	eax, DWORD PTR -4080036[rbp]
	movsx	rdx, eax
	mov	eax, DWORD PTR -4080040[rbp]
	cdqe
	imul	rax, rax, 1000
	add	rax, rdx
	mov	eax, DWORD PTR -4000016[rbp+rax*4]
	cmp	eax, 1
	jle	.L31
	add	DWORD PTR -4080044[rbp], 1
.L31:
	add	DWORD PTR -4080036[rbp], 1
.L30:
	cmp	DWORD PTR -4080036[rbp], 999
	jle	.L32
	add	DWORD PTR -4080040[rbp], 1
.L29:
	cmp	DWORD PTR -4080040[rbp], 999
	jle	.L33
	mov	eax, DWORD PTR -4080044[rbp]
	mov	esi, eax
	lea	rdi, .LC3[rip]
	mov	eax, 0
	call	printf@PLT
	mov	rax, QWORD PTR -4080024[rbp]
	mov	rdi, rax
	call	fclose@PLT
	mov	eax, 0
	mov	rsi, QWORD PTR -8[rbp]
	sub	rsi, QWORD PTR fs:40
	je	.L35
	call	__stack_chk_fail@PLT
.L35:
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE3:
	.size	main, .-main
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"437729.c"
	.text
	.align	2
	.global	is_vertical
	.syntax unified
	.arm
	.fpu softvfp
	.type	is_vertical, %function
is_vertical:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	sub	ip, fp, #20
	stm	ip, {r0, r1, r2, r3}
	ldr	r2, [fp, #-20]
	ldr	r3, [fp, #-12]
	cmp	r2, r3
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	is_vertical, .-is_vertical
	.align	2
	.global	is_horizontal
	.syntax unified
	.arm
	.fpu softvfp
	.type	is_horizontal, %function
is_horizontal:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	sub	ip, fp, #20
	stm	ip, {r0, r1, r2, r3}
	ldr	r2, [fp, #-16]
	ldr	r3, [fp, #-8]
	cmp	r2, r3
	moveq	r3, #1
	movne	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	is_horizontal, .-is_horizontal
	.align	2
	.global	swap_if_unordered
	.syntax unified
	.arm
	.fpu softvfp
	.type	swap_if_unordered, %function
swap_if_unordered:
	@ args = 0, pretend = 0, frame = 16
	@ frame_needed = 1, uses_anonymous_args = 0
	@ link register save eliminated.
	str	fp, [sp, #-4]!
	add	fp, sp, #0
	sub	sp, sp, #20
	str	r0, [fp, #-16]
	str	r1, [fp, #-20]
	ldr	r3, [fp, #-16]
	ldr	r2, [r3]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	cmp	r2, r3
	ble	.L6
	ldr	r3, [fp, #-16]
	ldr	r3, [r3]
	str	r3, [fp, #-8]
	ldr	r3, [fp, #-20]
	ldr	r2, [r3]
	ldr	r3, [fp, #-16]
	str	r2, [r3]
	ldr	r3, [fp, #-20]
	ldr	r2, [fp, #-8]
	str	r2, [r3]
	mov	r3, #1
	b	.L7
.L6:
	mov	r3, #0
.L7:
	mov	r0, r3
	add	sp, fp, #0
	@ sp needed
	ldr	fp, [sp], #4
	bx	lr
	.size	swap_if_unordered, .-swap_if_unordered
	.section	.rodata
	.align	2
.LC0:
	.ascii	"r\000"
	.align	2
.LC1:
	.ascii	"inputs/input5\000"
	.align	2
.LC2:
	.ascii	"%d,%d -> %d,%d\000"
	.align	2
.LC3:
	.ascii	"%d\012\000"
	.align	2
.LC4:
	.word	__stack_chk_guard
	.text
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 4080064
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, fp, lr}
	add	fp, sp, #8
	sub	sp, sp, #4079616
	sub	sp, sp, #460
	ldr	r3, .L36
	ldr	r3, [r3]
	str	r3, [fp, #-16]
	mov	r3,#0
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r4, r3
	ldr	r1, .L36+4
	ldr	r0, .L36+8
	bl	fopen
	str	r0, [r4, #-400]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-436]
	b	.L9
.L10:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-436]
	add	r3, r3, #1
	str	r3, [r2, #-436]
.L9:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	sub	r3, r3, #388
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	ldr	r2, [r2, #-436]
	lsl	r2, r2, #4
	add	r0, r3, r2
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	sub	r3, r3, #388
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	ldr	r2, [r2, #-436]
	lsl	r2, r2, #4
	add	r3, r3, r2
	add	ip, r3, #4
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	sub	r3, r3, #388
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	ldr	r2, [r2, #-436]
	lsl	r2, r2, #4
	add	r2, r2, #8
	add	r2, r3, r2
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	sub	r3, r3, #388
	sub	r1, fp, #4079616
	sub	r1, r1, #12
	ldr	r1, [r1, #-436]
	lsl	r1, r1, #4
	add	r1, r1, #8
	add	r3, r3, r1
	add	r3, r3, #4
	sub	r1, fp, #4079616
	sub	r1, r1, #12
	mov	lr, r1
	str	r3, [sp, #4]
	str	r2, [sp]
	mov	r3, ip
	mov	r2, r0
	ldr	r1, .L36+12
	ldr	r0, [lr, #-400]
	bl	__isoc99_fscanf
	mov	r3, r0
	cmn	r3, #1
	bne	.L10
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	sub	r3, r3, #2304
	sub	r3, r3, #4
	ldr	r2, .L36+16
	mov	r1, #0
	mov	r0, r3
	bl	memset
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-432]
	b	.L11
.L28:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	sub	r3, r3, #388
	ldm	r3, {r0, r1, r2, r3}
	bl	is_vertical
	mov	r3, r0
	cmp	r3, #0
	beq	.L12
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r3, [r3, #-384]
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	str	r3, [r2, #-444]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r3, [r3, #-376]
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	str	r3, [r2, #-440]
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	sub	r2, r2, #440
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	sub	r3, r3, #444
	mov	r1, r2
	mov	r0, r3
	bl	swap_if_unordered
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-444]
	str	r3, [r2, #-428]
	b	.L13
.L14:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r2, [r3, #-388]
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	r0, r3
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r1, fp, #4079616
	sub	r1, r1, #12
	ldr	r1, [r1, #-428]
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r3, [r3, #-2308]
	add	r1, r3, #1
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	r0, r3
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	ldr	r2, [r2, #-428]
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r0, r3
	str	r1, [r3, #-2308]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-428]
	add	r3, r3, #1
	str	r3, [r2, #-428]
.L13:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-440]
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	ldr	r2, [r2, #-428]
	cmp	r2, r3
	ble	.L14
	b	.L15
.L12:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	sub	r3, r3, #388
	ldm	r3, {r0, r1, r2, r3}
	bl	is_horizontal
	mov	r3, r0
	cmp	r3, #0
	beq	.L16
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r3, [r3, #-388]
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	str	r3, [r2, #-444]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r3, [r3, #-380]
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	str	r3, [r2, #-440]
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	sub	r2, r2, #440
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	sub	r3, r3, #444
	mov	r1, r2
	mov	r0, r3
	bl	swap_if_unordered
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-444]
	str	r3, [r2, #-424]
	b	.L17
.L18:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r1, [r3, #-384]
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	r0, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-424]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r3, [r3, #-2308]
	add	r0, r3, #1
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	ip, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-424]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, ip, r3
	str	r0, [r3, #-2308]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-424]
	add	r3, r3, #1
	str	r3, [r2, #-424]
.L17:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-440]
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	ldr	r2, [r2, #-424]
	cmp	r2, r3
	ble	.L18
	b	.L15
.L16:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r1, r3
	ldr	r3, [r3, #-388]
	str	r3, [r2, #-396]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r1, r3
	ldr	r3, [r3, #-380]
	str	r3, [r2, #-392]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r2, #-396]
	ldr	r3, [r3, #-392]
	cmp	r2, r3
	ble	.L19
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-396]
	str	r3, [r2, #-420]
	b	.L20
.L23:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r2, [r3, #-384]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r1, r3
	ldr	r3, [r3, #-376]
	cmp	r2, r3
	ble	.L21
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r2, [r3, #-384]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r1, [r1, #-396]
	ldr	r3, [r3, #-420]
	sub	r3, r1, r3
	sub	r1, r2, r3
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	r0, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-420]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r3, [r3, #-2308]
	add	r0, r3, #1
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	ip, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-420]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, ip, r3
	str	r0, [r3, #-2308]
	b	.L22
.L21:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r2, [r3, #-384]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r1, [r1, #-396]
	ldr	r3, [r3, #-420]
	sub	r3, r1, r3
	add	r1, r2, r3
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	r0, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-420]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r3, [r3, #-2308]
	add	r0, r3, #1
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	ip, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-420]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, ip, r3
	str	r0, [r3, #-2308]
.L22:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-420]
	sub	r3, r3, #1
	str	r3, [r2, #-420]
.L20:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r2, #-420]
	ldr	r3, [r3, #-392]
	cmp	r2, r3
	bge	.L23
	b	.L15
.L19:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-396]
	str	r3, [r2, #-416]
	b	.L24
.L27:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r2, [r3, #-384]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r1, r3
	ldr	r3, [r3, #-376]
	cmp	r2, r3
	ble	.L25
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r2, [r3, #-384]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r1, [r1, #-416]
	ldr	r3, [r3, #-396]
	sub	r3, r1, r3
	sub	r1, r2, r3
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	r0, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-416]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r3, [r3, #-2308]
	add	r0, r3, #1
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	ip, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-416]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, ip, r3
	str	r0, [r3, #-2308]
	b	.L26
.L25:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	lsl	r3, r3, #4
	add	r3, r2, r3
	ldr	r2, [r3, #-384]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r1, [r1, #-416]
	ldr	r3, [r3, #-396]
	sub	r3, r1, r3
	add	r1, r2, r3
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	r0, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-416]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, r0, r3
	ldr	r3, [r3, #-2308]
	add	r0, r3, #1
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	ip, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-416]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	add	r3, r3, r1
	lsl	r3, r3, #2
	add	r3, ip, r3
	str	r0, [r3, #-2308]
.L26:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-416]
	add	r3, r3, #1
	str	r3, [r2, #-416]
.L24:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r2, #-416]
	ldr	r3, [r3, #-392]
	cmp	r2, r3
	ble	.L27
.L15:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-432]
	add	r3, r3, #1
	str	r3, [r2, #-432]
.L11:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r2, #-432]
	ldr	r3, [r3, #-436]
	cmp	r2, r3
	blt	.L28
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-412]
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-408]
	b	.L29
.L33:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	mov	r3, #0
	str	r3, [r2, #-404]
	b	.L30
.L32:
	sub	r3, fp, #3997696
	sub	r3, r3, #12
	mov	r1, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r2, [r3, #-408]
	mov	r3, r2
	lsl	r3, r3, #5
	sub	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r3, r2
	lsl	r3, r3, #3
	sub	r2, fp, #4079616
	sub	r2, r2, #12
	ldr	r2, [r2, #-404]
	add	r3, r3, r2
	lsl	r3, r3, #2
	add	r3, r1, r3
	ldr	r3, [r3, #-2308]
	cmp	r3, #1
	ble	.L31
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-412]
	add	r3, r3, #1
	str	r3, [r2, #-412]
.L31:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-404]
	add	r3, r3, #1
	str	r3, [r2, #-404]
.L30:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-404]
	cmp	r3, #1000
	blt	.L32
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	mov	r2, r3
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-408]
	add	r3, r3, #1
	str	r3, [r2, #-408]
.L29:
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r3, [r3, #-408]
	cmp	r3, #1000
	blt	.L33
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r1, [r3, #-412]
	ldr	r0, .L36+20
	bl	printf
	sub	r3, fp, #4079616
	sub	r3, r3, #12
	ldr	r0, [r3, #-400]
	bl	fclose
	mov	r3, #0
	ldr	r2, .L36
	ldr	r1, [r2]
	ldr	r2, [fp, #-16]
	eors	r1, r2, r1
	mov	r2, #0
	beq	.L35
	bl	__stack_chk_fail
.L35:
	mov	r0, r3
	sub	sp, fp, #8
	@ sp needed
	pop	{r4, fp, pc}
.L37:
	.align	2
.L36:
	.word	.LC4
	.word	.LC0
	.word	.LC1
	.word	.LC2
	.word	4000000
	.word	.LC3
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
