	.file	"737441.c"
	.intel_syntax noprefix
	.text
	.globl	CHIP_RS100
	.bss
	.align 8
	.type	CHIP_RS100, @object
	.size	CHIP_RS100, 8
CHIP_RS100:
	.zero	8
	.globl	CHIP_RS200
	.align 8
	.type	CHIP_RS200, @object
	.size	CHIP_RS200, 8
CHIP_RS200:
	.zero	8
	.globl	DRM_MODE_FLAG_NHSYNC
	.align 4
	.type	DRM_MODE_FLAG_NHSYNC, @object
	.size	DRM_MODE_FLAG_NHSYNC, 4
DRM_MODE_FLAG_NHSYNC:
	.zero	4
	.globl	DRM_MODE_FLAG_NVSYNC
	.align 4
	.type	DRM_MODE_FLAG_NVSYNC, @object
	.size	DRM_MODE_FLAG_NVSYNC, 4
DRM_MODE_FLAG_NVSYNC:
	.zero	4
	.globl	RADEON_CRTC_AUTO_HORZ_CENTER_EN
	.align 4
	.type	RADEON_CRTC_AUTO_HORZ_CENTER_EN, @object
	.size	RADEON_CRTC_AUTO_HORZ_CENTER_EN, 4
RADEON_CRTC_AUTO_HORZ_CENTER_EN:
	.zero	4
	.globl	RADEON_CRTC_AUTO_VERT_CENTER_EN
	.align 4
	.type	RADEON_CRTC_AUTO_VERT_CENTER_EN, @object
	.size	RADEON_CRTC_AUTO_VERT_CENTER_EN, 4
RADEON_CRTC_AUTO_VERT_CENTER_EN:
	.zero	4
	.globl	RADEON_CRTC_H_CUTOFF_ACTIVE_EN
	.align 4
	.type	RADEON_CRTC_H_CUTOFF_ACTIVE_EN, @object
	.size	RADEON_CRTC_H_CUTOFF_ACTIVE_EN, 4
RADEON_CRTC_H_CUTOFF_ACTIVE_EN:
	.zero	4
	.globl	RADEON_CRTC_H_SYNC_POL
	.align 4
	.type	RADEON_CRTC_H_SYNC_POL, @object
	.size	RADEON_CRTC_H_SYNC_POL, 4
RADEON_CRTC_H_SYNC_POL:
	.zero	4
	.globl	RADEON_CRTC_MORE_CNTL
	.align 4
	.type	RADEON_CRTC_MORE_CNTL, @object
	.size	RADEON_CRTC_MORE_CNTL, 4
RADEON_CRTC_MORE_CNTL:
	.zero	4
	.globl	RADEON_CRTC_V_SYNC_POL
	.align 4
	.type	RADEON_CRTC_V_SYNC_POL, @object
	.size	RADEON_CRTC_V_SYNC_POL, 4
RADEON_CRTC_V_SYNC_POL:
	.zero	4
	.globl	RADEON_FP_CRTC_H_TOTAL_DISP
	.align 4
	.type	RADEON_FP_CRTC_H_TOTAL_DISP, @object
	.size	RADEON_FP_CRTC_H_TOTAL_DISP, 4
RADEON_FP_CRTC_H_TOTAL_DISP:
	.zero	4
	.globl	RADEON_FP_CRTC_V_TOTAL_DISP
	.align 4
	.type	RADEON_FP_CRTC_V_TOTAL_DISP, @object
	.size	RADEON_FP_CRTC_V_TOTAL_DISP, 4
RADEON_FP_CRTC_V_TOTAL_DISP:
	.zero	4
	.globl	RADEON_FP_HORZ_STRETCH
	.align 4
	.type	RADEON_FP_HORZ_STRETCH, @object
	.size	RADEON_FP_HORZ_STRETCH, 4
RADEON_FP_HORZ_STRETCH:
	.zero	4
	.globl	RADEON_FP_HORZ_VERT_ACTIVE
	.align 4
	.type	RADEON_FP_HORZ_VERT_ACTIVE, @object
	.size	RADEON_FP_HORZ_VERT_ACTIVE, 4
RADEON_FP_HORZ_VERT_ACTIVE:
	.zero	4
	.globl	RADEON_FP_H_SYNC_STRT_WID
	.align 4
	.type	RADEON_FP_H_SYNC_STRT_WID, @object
	.size	RADEON_FP_H_SYNC_STRT_WID, 4
RADEON_FP_H_SYNC_STRT_WID:
	.zero	4
	.globl	RADEON_FP_VERT_STRETCH
	.align 4
	.type	RADEON_FP_VERT_STRETCH, @object
	.size	RADEON_FP_VERT_STRETCH, 4
RADEON_FP_VERT_STRETCH:
	.zero	4
	.globl	RADEON_FP_V_SYNC_STRT_WID
	.align 4
	.type	RADEON_FP_V_SYNC_STRT_WID, @object
	.size	RADEON_FP_V_SYNC_STRT_WID, 4
RADEON_FP_V_SYNC_STRT_WID:
	.zero	4
	.globl	RADEON_HORZ_AUTO_RATIO_INC
	.align 4
	.type	RADEON_HORZ_AUTO_RATIO_INC, @object
	.size	RADEON_HORZ_AUTO_RATIO_INC, 4
RADEON_HORZ_AUTO_RATIO_INC:
	.zero	4
	.globl	RADEON_HORZ_FP_LOOP_STRETCH
	.align 4
	.type	RADEON_HORZ_FP_LOOP_STRETCH, @object
	.size	RADEON_HORZ_FP_LOOP_STRETCH, 4
RADEON_HORZ_FP_LOOP_STRETCH:
	.zero	4
	.globl	RADEON_HORZ_STRETCH_BLEND
	.align 4
	.type	RADEON_HORZ_STRETCH_BLEND, @object
	.size	RADEON_HORZ_STRETCH_BLEND, 4
RADEON_HORZ_STRETCH_BLEND:
	.zero	4
	.globl	RADEON_HORZ_STRETCH_ENABLE
	.align 4
	.type	RADEON_HORZ_STRETCH_ENABLE, @object
	.size	RADEON_HORZ_STRETCH_ENABLE, 4
RADEON_HORZ_STRETCH_ENABLE:
	.zero	4
	.globl	RADEON_HORZ_STRETCH_RATIO_MASK
	.align 4
	.type	RADEON_HORZ_STRETCH_RATIO_MASK, @object
	.size	RADEON_HORZ_STRETCH_RATIO_MASK, 4
RADEON_HORZ_STRETCH_RATIO_MASK:
	.zero	4
	.globl	RADEON_HORZ_STRETCH_RATIO_MAX
	.align 4
	.type	RADEON_HORZ_STRETCH_RATIO_MAX, @object
	.size	RADEON_HORZ_STRETCH_RATIO_MAX, 4
RADEON_HORZ_STRETCH_RATIO_MAX:
	.zero	4
	.globl	RADEON_VERT_AUTO_RATIO_INC
	.align 4
	.type	RADEON_VERT_AUTO_RATIO_INC, @object
	.size	RADEON_VERT_AUTO_RATIO_INC, 4
RADEON_VERT_AUTO_RATIO_INC:
	.zero	4
	.globl	RADEON_VERT_STRETCH_BLEND
	.align 4
	.type	RADEON_VERT_STRETCH_BLEND, @object
	.size	RADEON_VERT_STRETCH_BLEND, 4
RADEON_VERT_STRETCH_BLEND:
	.zero	4
	.globl	RADEON_VERT_STRETCH_ENABLE
	.align 4
	.type	RADEON_VERT_STRETCH_ENABLE, @object
	.size	RADEON_VERT_STRETCH_ENABLE, 4
RADEON_VERT_STRETCH_ENABLE:
	.zero	4
	.globl	RADEON_VERT_STRETCH_RATIO_MASK
	.align 4
	.type	RADEON_VERT_STRETCH_RATIO_MASK, @object
	.size	RADEON_VERT_STRETCH_RATIO_MASK, 4
RADEON_VERT_STRETCH_RATIO_MASK:
	.zero	4
	.globl	RADEON_VERT_STRETCH_RATIO_MAX
	.align 4
	.type	RADEON_VERT_STRETCH_RATIO_MAX, @object
	.size	RADEON_VERT_STRETCH_RATIO_MAX, 4
RADEON_VERT_STRETCH_RATIO_MAX:
	.zero	4
	.globl	RADEON_VERT_STRETCH_RESERVED
	.align 4
	.type	RADEON_VERT_STRETCH_RESERVED, @object
	.size	RADEON_VERT_STRETCH_RESERVED, 4
RADEON_VERT_STRETCH_RESERVED:
	.zero	4
	.text
	.type	radeon_legacy_rmx_mode_set, @function
radeon_legacy_rmx_mode_set:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	add	rsp, -128
	mov	QWORD PTR -120[rbp], rdi
	mov	QWORD PTR -128[rbp], rsi
	mov	rax, QWORD PTR -120[rbp]
	mov	rax, QWORD PTR [rax]
	mov	QWORD PTR -32[rbp], rax
	mov	rax, QWORD PTR -32[rbp]
	mov	rax, QWORD PTR [rax]
	mov	QWORD PTR -24[rbp], rax
	mov	rax, QWORD PTR -120[rbp]
	mov	rdi, rax
	call	to_radeon_crtc@PLT
	mov	QWORD PTR -16[rbp], rax
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -104[rbp], eax
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 4[rax]
	mov	DWORD PTR -100[rbp], eax
	mov	DWORD PTR -96[rbp], 1
	mov	DWORD PTR -92[rbp], 1
	mov	rax, QWORD PTR -16[rbp]
	add	rax, 4
	mov	QWORD PTR -8[rbp], rax
	mov	eax, DWORD PTR RADEON_FP_VERT_STRETCH[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	ecx, DWORD PTR RADEON_VERT_STRETCH_RESERVED[rip]
	mov	edx, DWORD PTR RADEON_VERT_AUTO_RATIO_INC[rip]
	or	edx, ecx
	and	eax, edx
	mov	DWORD PTR -68[rbp], eax
	mov	eax, DWORD PTR RADEON_FP_HORZ_STRETCH[rip]
	mov	edi, eax
	call	RREG32@PLT
	mov	ecx, DWORD PTR RADEON_HORZ_FP_LOOP_STRETCH[rip]
	mov	edx, DWORD PTR RADEON_HORZ_AUTO_RATIO_INC[rip]
	or	edx, ecx
	and	eax, edx
	mov	DWORD PTR -72[rbp], eax
	mov	DWORD PTR -76[rbp], 0
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR CHIP_RS100[rip]
	cmp	rdx, rax
	je	.L2
	mov	rax, QWORD PTR -24[rbp]
	mov	rdx, QWORD PTR [rax]
	mov	rax, QWORD PTR CHIP_RS200[rip]
	cmp	rdx, rax
	jne	.L3
.L2:
	mov	eax, DWORD PTR RADEON_CRTC_H_CUTOFF_ACTIVE_EN[rip]
	or	DWORD PTR -76[rbp], eax
.L3:
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 8[rax]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	sub	eax, 1
	and	eax, 1023
	mov	ecx, eax
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 12[rax]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	sub	eax, 1
	sal	eax, 16
	and	eax, 33488896
	or	eax, ecx
	mov	DWORD PTR -56[rbp], eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -128[rbp]
	mov	ecx, DWORD PTR 20[rax]
	mov	eax, edx
	sub	eax, ecx
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	mov	DWORD PTR -88[rbp], eax
	cmp	DWORD PTR -88[rbp], 0
	jne	.L4
	mov	DWORD PTR -88[rbp], 1
.L4:
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 20[rax]
	sub	eax, 8
	mov	DWORD PTR -44[rbp], eax
	mov	eax, DWORD PTR -44[rbp]
	and	eax, 8191
	mov	edx, eax
	mov	eax, DWORD PTR -88[rbp]
	sal	eax, 16
	and	eax, 4128768
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR DRM_MODE_FLAG_NHSYNC[rip]
	and	eax, edx
	test	eax, eax
	je	.L5
	mov	eax, DWORD PTR RADEON_CRTC_H_SYNC_POL[rip]
	jmp	.L6
.L5:
	mov	eax, 0
.L6:
	or	eax, ecx
	mov	DWORD PTR -60[rbp], eax
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 28[rax]
	sub	eax, 1
	movzx	edx, ax
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 32[rax]
	sub	eax, 1
	sal	eax, 16
	or	eax, edx
	mov	DWORD PTR -48[rbp], eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 36[rax]
	mov	rax, QWORD PTR -128[rbp]
	mov	ecx, DWORD PTR 40[rax]
	mov	eax, edx
	sub	eax, ecx
	mov	DWORD PTR -84[rbp], eax
	cmp	DWORD PTR -84[rbp], 0
	jne	.L7
	mov	DWORD PTR -84[rbp], 1
.L7:
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 40[rax]
	sub	eax, 1
	and	eax, 4095
	mov	edx, eax
	mov	eax, DWORD PTR -84[rbp]
	sal	eax, 16
	and	eax, 2031616
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR DRM_MODE_FLAG_NVSYNC[rip]
	and	eax, edx
	test	eax, eax
	je	.L8
	mov	eax, DWORD PTR RADEON_CRTC_V_SYNC_POL[rip]
	jmp	.L9
.L8:
	mov	eax, 0
.L9:
	or	eax, ecx
	mov	DWORD PTR -52[rbp], eax
	mov	DWORD PTR -64[rbp], 0
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	test	eax, eax
	je	.L10
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	test	eax, eax
	jne	.L11
.L10:
	mov	DWORD PTR -96[rbp], 0
	mov	DWORD PTR -92[rbp], 0
	jmp	.L12
.L11:
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -104[rbp], eax
	jle	.L13
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	mov	DWORD PTR -104[rbp], eax
.L13:
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	cmp	DWORD PTR -100[rbp], eax
	jle	.L14
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	mov	DWORD PTR -100[rbp], eax
.L14:
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	DWORD PTR -104[rbp], eax
	jne	.L15
	mov	DWORD PTR -96[rbp], 0
.L15:
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	cmp	DWORD PTR -100[rbp], eax
	jne	.L12
	mov	DWORD PTR -92[rbp], 0
.L12:
	mov	rax, QWORD PTR -16[rbp]
	mov	eax, DWORD PTR [rax]
	cmp	eax, 131
	je	.L16
	cmp	eax, 131
	jg	.L17
	cmp	eax, 129
	je	.L16
	cmp	eax, 130
	je	.L18
	jmp	.L17
.L16:
	cmp	DWORD PTR -96[rbp], 0
	jne	.L19
	mov	eax, DWORD PTR -104[rbp]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	sub	eax, 1
	sal	eax, 16
	or	DWORD PTR -72[rbp], eax
	jmp	.L20
.L19:
	mov	eax, DWORD PTR RADEON_HORZ_AUTO_RATIO_INC[rip]
	and	eax, DWORD PTR -72[rbp]
	test	eax, eax
	setne	al
	movzx	eax, al
	mov	DWORD PTR -40[rbp], eax
	mov	edx, DWORD PTR -104[rbp]
	mov	eax, DWORD PTR -40[rbp]
	add	edx, eax
	mov	eax, DWORD PTR RADEON_HORZ_STRETCH_RATIO_MAX[rip]
	imul	eax, edx
	mov	rdx, QWORD PTR -8[rbp]
	mov	esi, DWORD PTR [rdx]
	cdq
	idiv	esi
	add	eax, 1
	mov	DWORD PTR -36[rbp], eax
	mov	eax, DWORD PTR RADEON_HORZ_STRETCH_RATIO_MASK[rip]
	and	eax, DWORD PTR -36[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR RADEON_HORZ_STRETCH_BLEND[rip]
	or	edx, eax
	mov	eax, DWORD PTR RADEON_HORZ_STRETCH_ENABLE[rip]
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	sub	eax, 1
	sal	eax, 16
	or	eax, ecx
	or	DWORD PTR -72[rbp], eax
.L20:
	cmp	DWORD PTR -92[rbp], 0
	jne	.L21
	mov	eax, DWORD PTR -100[rbp]
	sub	eax, 1
	sal	eax, 12
	or	DWORD PTR -68[rbp], eax
	jmp	.L23
.L21:
	mov	eax, DWORD PTR RADEON_VERT_AUTO_RATIO_INC[rip]
	and	eax, DWORD PTR -68[rbp]
	test	eax, eax
	setne	al
	movzx	eax, al
	mov	DWORD PTR -40[rbp], eax
	mov	edx, DWORD PTR -100[rbp]
	mov	eax, DWORD PTR -40[rbp]
	add	edx, eax
	mov	eax, DWORD PTR RADEON_VERT_STRETCH_RATIO_MAX[rip]
	imul	eax, edx
	mov	rdx, QWORD PTR -8[rbp]
	mov	esi, DWORD PTR 4[rdx]
	cdq
	idiv	esi
	add	eax, 1
	mov	DWORD PTR -36[rbp], eax
	mov	eax, DWORD PTR RADEON_VERT_STRETCH_RATIO_MASK[rip]
	and	eax, DWORD PTR -36[rbp]
	mov	edx, eax
	mov	eax, DWORD PTR RADEON_VERT_STRETCH_ENABLE[rip]
	or	edx, eax
	mov	eax, DWORD PTR RADEON_VERT_STRETCH_BLEND[rip]
	or	edx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	sub	eax, 1
	sal	eax, 12
	or	eax, edx
	or	DWORD PTR -68[rbp], eax
	jmp	.L23
.L18:
	mov	eax, DWORD PTR -104[rbp]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	sub	eax, 1
	sal	eax, 16
	or	DWORD PTR -72[rbp], eax
	mov	eax, DWORD PTR -100[rbp]
	sub	eax, 1
	sal	eax, 12
	or	DWORD PTR -68[rbp], eax
	mov	edx, DWORD PTR RADEON_CRTC_AUTO_HORZ_CENTER_EN[rip]
	mov	eax, DWORD PTR RADEON_CRTC_AUTO_VERT_CENTER_EN[rip]
	or	eax, edx
	or	DWORD PTR -76[rbp], eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 44[rax]
	mov	rax, QWORD PTR -128[rbp]
	mov	ecx, DWORD PTR 48[rax]
	mov	eax, edx
	sub	eax, ecx
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	mov	DWORD PTR -80[rbp], eax
	cmp	DWORD PTR -80[rbp], 110
	jle	.L24
	mov	DWORD PTR -80[rbp], 110
.L24:
	mov	eax, DWORD PTR -80[rbp]
	and	eax, 1023
	mov	ecx, eax
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 12[rax]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	sub	eax, 1
	sal	eax, 16
	and	eax, 33488896
	or	eax, ecx
	mov	DWORD PTR -56[rbp], eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 16[rax]
	mov	rax, QWORD PTR -128[rbp]
	mov	ecx, DWORD PTR 20[rax]
	mov	eax, edx
	sub	eax, ecx
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	mov	DWORD PTR -88[rbp], eax
	cmp	DWORD PTR -88[rbp], 0
	jne	.L25
	mov	DWORD PTR -88[rbp], 1
.L25:
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 20[rax]
	mov	rax, QWORD PTR -128[rbp]
	mov	ecx, DWORD PTR 48[rax]
	mov	eax, edx
	sub	eax, ecx
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	and	eax, 8191
	mov	edx, eax
	mov	eax, DWORD PTR -88[rbp]
	sal	eax, 16
	and	eax, 4128768
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR DRM_MODE_FLAG_NHSYNC[rip]
	and	eax, edx
	test	eax, eax
	je	.L26
	mov	eax, DWORD PTR RADEON_CRTC_H_SYNC_POL[rip]
	jmp	.L27
.L26:
	mov	eax, 0
.L27:
	or	eax, ecx
	mov	DWORD PTR -60[rbp], eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 52[rax]
	mov	rax, QWORD PTR -128[rbp]
	mov	ecx, DWORD PTR 56[rax]
	mov	eax, edx
	sub	eax, ecx
	movzx	edx, ax
	mov	rax, QWORD PTR -128[rbp]
	mov	eax, DWORD PTR 32[rax]
	sub	eax, 1
	sal	eax, 16
	or	eax, edx
	mov	DWORD PTR -48[rbp], eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 36[rax]
	mov	rax, QWORD PTR -128[rbp]
	mov	ecx, DWORD PTR 40[rax]
	mov	eax, edx
	sub	eax, ecx
	mov	DWORD PTR -84[rbp], eax
	cmp	DWORD PTR -84[rbp], 0
	jne	.L28
	mov	DWORD PTR -84[rbp], 1
.L28:
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 40[rax]
	mov	rax, QWORD PTR -128[rbp]
	mov	ecx, DWORD PTR 56[rax]
	mov	eax, edx
	sub	eax, ecx
	and	eax, 4095
	mov	edx, eax
	mov	eax, DWORD PTR -84[rbp]
	sal	eax, 16
	and	eax, 2031616
	mov	ecx, edx
	or	ecx, eax
	mov	rax, QWORD PTR -128[rbp]
	mov	edx, DWORD PTR 24[rax]
	mov	eax, DWORD PTR DRM_MODE_FLAG_NVSYNC[rip]
	and	eax, edx
	test	eax, eax
	je	.L29
	mov	eax, DWORD PTR RADEON_CRTC_V_SYNC_POL[rip]
	jmp	.L30
.L29:
	mov	eax, 0
.L30:
	or	eax, ecx
	mov	DWORD PTR -52[rbp], eax
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR 4[rax]
	and	eax, 4095
	mov	ecx, eax
	mov	rax, QWORD PTR -8[rbp]
	mov	eax, DWORD PTR [rax]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	sal	eax, 16
	and	eax, 33488896
	or	eax, ecx
	mov	DWORD PTR -64[rbp], eax
	jmp	.L23
.L17:
	mov	eax, DWORD PTR -104[rbp]
	lea	edx, 7[rax]
	test	eax, eax
	cmovs	eax, edx
	sar	eax, 3
	sub	eax, 1
	sal	eax, 16
	or	DWORD PTR -72[rbp], eax
	mov	eax, DWORD PTR -100[rbp]
	sub	eax, 1
	sal	eax, 12
	or	DWORD PTR -68[rbp], eax
	nop
.L23:
	mov	eax, DWORD PTR RADEON_FP_HORZ_STRETCH[rip]
	mov	edx, DWORD PTR -72[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR RADEON_FP_VERT_STRETCH[rip]
	mov	edx, DWORD PTR -68[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR RADEON_CRTC_MORE_CNTL[rip]
	mov	edx, DWORD PTR -76[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR RADEON_FP_HORZ_VERT_ACTIVE[rip]
	mov	edx, DWORD PTR -64[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR RADEON_FP_H_SYNC_STRT_WID[rip]
	mov	edx, DWORD PTR -60[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR RADEON_FP_V_SYNC_STRT_WID[rip]
	mov	edx, DWORD PTR -52[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR RADEON_FP_CRTC_H_TOTAL_DISP[rip]
	mov	edx, DWORD PTR -56[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	mov	eax, DWORD PTR RADEON_FP_CRTC_V_TOTAL_DISP[rip]
	mov	edx, DWORD PTR -48[rbp]
	mov	esi, edx
	mov	edi, eax
	call	WREG32@PLT
	nop
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	radeon_legacy_rmx_mode_set, .-radeon_legacy_rmx_mode_set
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"737441.c"
	.text
	.comm	CHIP_RS100,4,4
	.comm	CHIP_RS200,4,4
	.comm	DRM_MODE_FLAG_NHSYNC,4,4
	.comm	DRM_MODE_FLAG_NVSYNC,4,4
	.comm	RADEON_CRTC_AUTO_HORZ_CENTER_EN,4,4
	.comm	RADEON_CRTC_AUTO_VERT_CENTER_EN,4,4
	.comm	RADEON_CRTC_H_CUTOFF_ACTIVE_EN,4,4
	.comm	RADEON_CRTC_H_SYNC_POL,4,4
	.comm	RADEON_CRTC_MORE_CNTL,4,4
	.comm	RADEON_CRTC_V_SYNC_POL,4,4
	.comm	RADEON_FP_CRTC_H_TOTAL_DISP,4,4
	.comm	RADEON_FP_CRTC_V_TOTAL_DISP,4,4
	.comm	RADEON_FP_HORZ_STRETCH,4,4
	.comm	RADEON_FP_HORZ_VERT_ACTIVE,4,4
	.comm	RADEON_FP_H_SYNC_STRT_WID,4,4
	.comm	RADEON_FP_VERT_STRETCH,4,4
	.comm	RADEON_FP_V_SYNC_STRT_WID,4,4
	.comm	RADEON_HORZ_AUTO_RATIO_INC,4,4
	.comm	RADEON_HORZ_FP_LOOP_STRETCH,4,4
	.comm	RADEON_HORZ_STRETCH_BLEND,4,4
	.comm	RADEON_HORZ_STRETCH_ENABLE,4,4
	.comm	RADEON_HORZ_STRETCH_RATIO_MASK,4,4
	.comm	RADEON_HORZ_STRETCH_RATIO_MAX,4,4
	.comm	RADEON_VERT_AUTO_RATIO_INC,4,4
	.comm	RADEON_VERT_STRETCH_BLEND,4,4
	.comm	RADEON_VERT_STRETCH_ENABLE,4,4
	.comm	RADEON_VERT_STRETCH_RATIO_MASK,4,4
	.comm	RADEON_VERT_STRETCH_RATIO_MAX,4,4
	.comm	RADEON_VERT_STRETCH_RESERVED,4,4
	.global	__aeabi_idiv
	.align	2
	.syntax unified
	.arm
	.fpu softvfp
	.type	radeon_legacy_rmx_mode_set, %function
radeon_legacy_rmx_mode_set:
	@ args = 0, pretend = 0, frame = 96
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	sub	sp, sp, #96
	str	r0, [fp, #-96]
	str	r1, [fp, #-100]
	ldr	r3, [fp, #-96]
	ldr	r3, [r3]
	str	r3, [fp, #-32]
	ldr	r3, [fp, #-32]
	ldr	r3, [r3]
	str	r3, [fp, #-28]
	ldr	r0, [fp, #-96]
	bl	to_radeon_crtc
	str	r0, [fp, #-24]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3]
	str	r3, [fp, #-92]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #4]
	str	r3, [fp, #-88]
	mov	r3, #1
	str	r3, [fp, #-84]
	mov	r3, #1
	str	r3, [fp, #-80]
	ldr	r3, [fp, #-24]
	add	r3, r3, #4
	str	r3, [fp, #-20]
	ldr	r3, .L31
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r1, r0
	ldr	r3, .L31+4
	ldr	r2, [r3]
	ldr	r3, .L31+8
	ldr	r3, [r3]
	orr	r3, r2, r3
	and	r3, r3, r1
	str	r3, [fp, #-56]
	ldr	r3, .L31+12
	ldr	r3, [r3]
	mov	r0, r3
	bl	RREG32
	mov	r1, r0
	ldr	r3, .L31+16
	ldr	r2, [r3]
	ldr	r3, .L31+20
	ldr	r3, [r3]
	orr	r3, r2, r3
	and	r3, r3, r1
	str	r3, [fp, #-60]
	mov	r3, #0
	str	r3, [fp, #-64]
	ldr	r3, [fp, #-28]
	ldr	r2, [r3]
	ldr	r3, .L31+24
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L2
	ldr	r3, [fp, #-28]
	ldr	r2, [r3]
	ldr	r3, .L31+28
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L3
.L2:
	ldr	r3, .L31+32
	ldr	r3, [r3]
	ldr	r2, [fp, #-64]
	orr	r3, r2, r3
	str	r3, [fp, #-64]
.L3:
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #8]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	sub	r3, r3, #1
	lsl	r2, r3, #22
	lsr	r2, r2, #22
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #12]
	add	r1, r3, #7
	cmp	r3, #0
	movlt	r3, r1
	movge	r3, r3
	asr	r3, r3, #3
	sub	r3, r3, #1
	lsl	r1, r3, #16
	ldr	r3, .L31+36
	and	r3, r3, r1
	orr	r3, r2, r3
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-100]
	ldr	r2, [r3, #16]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #20]
	sub	r3, r2, r3
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	str	r3, [fp, #-76]
	ldr	r3, [fp, #-76]
	cmp	r3, #0
	bne	.L4
	mov	r3, #1
	str	r3, [fp, #-76]
.L4:
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #20]
	sub	r3, r3, #8
	str	r3, [fp, #-16]
	ldr	r3, [fp, #-16]
	lsl	r3, r3, #19
	lsr	r3, r3, #19
	ldr	r2, [fp, #-76]
	lsl	r2, r2, #16
	and	r2, r2, #4128768
	orr	r2, r3, r2
	ldr	r3, [fp, #-100]
	ldr	r1, [r3, #24]
	ldr	r3, .L31+40
	ldr	r3, [r3]
	and	r3, r3, r1
	cmp	r3, #0
	beq	.L5
	ldr	r3, .L31+44
	ldr	r3, [r3]
	b	.L6
.L5:
	mov	r3, #0
.L6:
	orr	r3, r3, r2
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #28]
	sub	r3, r3, #1
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-100]
	ldr	r2, [r2, #32]
	sub	r2, r2, #1
	lsl	r2, r2, #16
	orr	r3, r3, r2
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-100]
	ldr	r2, [r3, #36]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #40]
	sub	r3, r2, r3
	str	r3, [fp, #-72]
	ldr	r3, [fp, #-72]
	cmp	r3, #0
	bne	.L7
	mov	r3, #1
	str	r3, [fp, #-72]
.L7:
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #40]
	sub	r3, r3, #1
	lsl	r3, r3, #20
	lsr	r3, r3, #20
	ldr	r2, [fp, #-72]
	lsl	r2, r2, #16
	and	r2, r2, #2031616
	orr	r2, r3, r2
	ldr	r3, [fp, #-100]
	ldr	r1, [r3, #24]
	ldr	r3, .L31+48
	ldr	r3, [r3]
	and	r3, r3, r1
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L31+52
	ldr	r3, [r3]
	b	.L9
.L8:
	mov	r3, #0
.L9:
	orr	r3, r3, r2
	str	r3, [fp, #-40]
	mov	r3, #0
	str	r3, [fp, #-52]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L10
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	cmp	r3, #0
	bne	.L11
.L10:
	mov	r3, #0
	str	r3, [fp, #-84]
	mov	r3, #0
	str	r3, [fp, #-80]
	b	.L12
.L11:
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	ldr	r2, [fp, #-92]
	cmp	r2, r3
	ble	.L13
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	str	r3, [fp, #-92]
.L13:
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-88]
	cmp	r2, r3
	ble	.L14
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	str	r3, [fp, #-88]
.L14:
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	ldr	r2, [fp, #-92]
	cmp	r2, r3
	bne	.L15
	mov	r3, #0
	str	r3, [fp, #-84]
.L15:
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	ldr	r2, [fp, #-88]
	cmp	r2, r3
	bne	.L12
	mov	r3, #0
	str	r3, [fp, #-80]
.L12:
	ldr	r3, [fp, #-24]
	ldr	r3, [r3]
	cmp	r3, #131
	beq	.L16
	cmp	r3, #131
	bgt	.L17
	cmp	r3, #129
	beq	.L16
	cmp	r3, #130
	beq	.L18
	b	.L17
.L16:
	ldr	r3, [fp, #-84]
	cmp	r3, #0
	bne	.L19
	ldr	r3, [fp, #-92]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	sub	r3, r3, #1
	lsl	r3, r3, #16
	ldr	r2, [fp, #-60]
	orr	r3, r2, r3
	str	r3, [fp, #-60]
	b	.L20
.L19:
	ldr	r3, .L31+20
	ldr	r2, [r3]
	ldr	r3, [fp, #-60]
	and	r3, r3, r2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	str	r3, [fp, #-12]
	ldr	r2, [fp, #-92]
	ldr	r3, [fp, #-12]
	add	r3, r2, r3
	ldr	r2, .L31+56
	ldr	r2, [r2]
	mul	r2, r3, r2
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	mov	r1, r3
	mov	r0, r2
	bl	__aeabi_idiv
	mov	r3, r0
	add	r3, r3, #1
	str	r3, [fp, #-8]
	ldr	r3, .L31+60
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	and	r2, r2, r3
	ldr	r3, .L31+64
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, .L31+68
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	add	r1, r3, #7
	cmp	r3, #0
	movlt	r3, r1
	movge	r3, r3
	asr	r3, r3, #3
	sub	r3, r3, #1
	lsl	r3, r3, #16
	orr	r3, r2, r3
	ldr	r2, [fp, #-60]
	orr	r3, r2, r3
	str	r3, [fp, #-60]
.L20:
	ldr	r3, [fp, #-80]
	cmp	r3, #0
	bne	.L21
	ldr	r3, [fp, #-88]
	sub	r3, r3, #1
	lsl	r3, r3, #12
	ldr	r2, [fp, #-56]
	orr	r3, r2, r3
	str	r3, [fp, #-56]
	b	.L23
.L21:
	ldr	r3, .L31+8
	ldr	r2, [r3]
	ldr	r3, [fp, #-56]
	and	r3, r3, r2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	str	r3, [fp, #-12]
	ldr	r2, [fp, #-88]
	ldr	r3, [fp, #-12]
	add	r3, r2, r3
	ldr	r2, .L31+72
	ldr	r2, [r2]
	mul	r2, r3, r2
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	mov	r1, r3
	mov	r0, r2
	bl	__aeabi_idiv
	mov	r3, r0
	add	r3, r3, #1
	str	r3, [fp, #-8]
	ldr	r3, .L31+76
	ldr	r2, [r3]
	ldr	r3, [fp, #-8]
	and	r2, r2, r3
	ldr	r3, .L31+80
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, .L31+84
	ldr	r3, [r3]
	orr	r2, r2, r3
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	sub	r3, r3, #1
	lsl	r3, r3, #12
	orr	r3, r2, r3
	ldr	r2, [fp, #-56]
	orr	r3, r2, r3
	str	r3, [fp, #-56]
	b	.L23
.L18:
	ldr	r3, [fp, #-92]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	sub	r3, r3, #1
	lsl	r3, r3, #16
	ldr	r2, [fp, #-60]
	orr	r3, r2, r3
	str	r3, [fp, #-60]
	ldr	r3, [fp, #-88]
	sub	r3, r3, #1
	lsl	r3, r3, #12
	ldr	r2, [fp, #-56]
	orr	r3, r2, r3
	str	r3, [fp, #-56]
	ldr	r3, .L31+88
	ldr	r2, [r3]
	ldr	r3, .L31+92
	ldr	r3, [r3]
	orr	r3, r2, r3
	ldr	r2, [fp, #-64]
	orr	r3, r2, r3
	str	r3, [fp, #-64]
	ldr	r3, [fp, #-100]
	ldr	r2, [r3, #44]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #48]
	sub	r3, r2, r3
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	str	r3, [fp, #-68]
	ldr	r3, [fp, #-68]
	cmp	r3, #110
	ble	.L24
	mov	r3, #110
	str	r3, [fp, #-68]
.L24:
	ldr	r3, [fp, #-68]
	lsl	r2, r3, #22
	lsr	r2, r2, #22
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #12]
	add	r1, r3, #7
	cmp	r3, #0
	movlt	r3, r1
	movge	r3, r3
	asr	r3, r3, #3
	sub	r3, r3, #1
	lsl	r1, r3, #16
	ldr	r3, .L31+36
	and	r3, r3, r1
	orr	r3, r2, r3
	str	r3, [fp, #-44]
	ldr	r3, [fp, #-100]
	ldr	r2, [r3, #16]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #20]
	sub	r3, r2, r3
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	str	r3, [fp, #-76]
	ldr	r3, [fp, #-76]
	cmp	r3, #0
	bne	.L25
	mov	r3, #1
	str	r3, [fp, #-76]
.L25:
	ldr	r3, [fp, #-100]
	ldr	r2, [r3, #20]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #48]
	sub	r3, r2, r3
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	lsl	r3, r3, #19
	lsr	r3, r3, #19
	ldr	r2, [fp, #-76]
	lsl	r2, r2, #16
	and	r2, r2, #4128768
	orr	r2, r3, r2
	ldr	r3, [fp, #-100]
	ldr	r1, [r3, #24]
	ldr	r3, .L31+40
	ldr	r3, [r3]
	and	r3, r3, r1
	cmp	r3, #0
	beq	.L26
	ldr	r3, .L31+44
	ldr	r3, [r3]
	b	.L27
.L26:
	mov	r3, #0
.L27:
	orr	r3, r3, r2
	str	r3, [fp, #-48]
	ldr	r3, [fp, #-100]
	ldr	r2, [r3, #52]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #56]
	sub	r3, r2, r3
	lsl	r3, r3, #16
	lsr	r3, r3, #16
	ldr	r2, [fp, #-100]
	ldr	r2, [r2, #32]
	sub	r2, r2, #1
	lsl	r2, r2, #16
	orr	r3, r3, r2
	str	r3, [fp, #-36]
	ldr	r3, [fp, #-100]
	ldr	r2, [r3, #36]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #40]
	sub	r3, r2, r3
	str	r3, [fp, #-72]
	ldr	r3, [fp, #-72]
	cmp	r3, #0
	bne	.L28
	mov	r3, #1
	str	r3, [fp, #-72]
.L28:
	ldr	r3, [fp, #-100]
	ldr	r2, [r3, #40]
	ldr	r3, [fp, #-100]
	ldr	r3, [r3, #56]
	sub	r3, r2, r3
	lsl	r3, r3, #20
	lsr	r3, r3, #20
	ldr	r2, [fp, #-72]
	lsl	r2, r2, #16
	and	r2, r2, #2031616
	orr	r2, r3, r2
	ldr	r3, [fp, #-100]
	ldr	r1, [r3, #24]
	ldr	r3, .L31+48
	ldr	r3, [r3]
	and	r3, r3, r1
	cmp	r3, #0
	beq	.L29
	ldr	r3, .L31+52
	ldr	r3, [r3]
	b	.L30
.L29:
	mov	r3, #0
.L30:
	orr	r3, r3, r2
	str	r3, [fp, #-40]
	ldr	r3, [fp, #-20]
	ldr	r3, [r3, #4]
	lsl	r2, r3, #20
	lsr	r2, r2, #20
	ldr	r3, [fp, #-20]
	ldr	r3, [r3]
	add	r1, r3, #7
	cmp	r3, #0
	movlt	r3, r1
	movge	r3, r3
	asr	r3, r3, #3
	lsl	r1, r3, #16
	ldr	r3, .L31+36
	and	r3, r3, r1
	orr	r3, r2, r3
	str	r3, [fp, #-52]
	b	.L23
.L17:
	ldr	r3, [fp, #-92]
	add	r2, r3, #7
	cmp	r3, #0
	movlt	r3, r2
	movge	r3, r3
	asr	r3, r3, #3
	sub	r3, r3, #1
	lsl	r3, r3, #16
	ldr	r2, [fp, #-60]
	orr	r3, r2, r3
	str	r3, [fp, #-60]
	ldr	r3, [fp, #-88]
	sub	r3, r3, #1
	lsl	r3, r3, #12
	ldr	r2, [fp, #-56]
	orr	r3, r2, r3
	str	r3, [fp, #-56]
	nop
.L23:
	ldr	r3, .L31+12
	ldr	r3, [r3]
	ldr	r1, [fp, #-60]
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L31
	ldr	r3, [r3]
	ldr	r1, [fp, #-56]
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L31+96
	ldr	r3, [r3]
	ldr	r1, [fp, #-64]
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L31+100
	ldr	r3, [r3]
	ldr	r1, [fp, #-52]
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L31+104
	ldr	r3, [r3]
	ldr	r1, [fp, #-48]
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L31+108
	ldr	r3, [r3]
	ldr	r1, [fp, #-40]
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L31+112
	ldr	r3, [r3]
	ldr	r1, [fp, #-44]
	mov	r0, r3
	bl	WREG32
	ldr	r3, .L31+116
	ldr	r3, [r3]
	ldr	r1, [fp, #-36]
	mov	r0, r3
	bl	WREG32
	nop
	sub	sp, fp, #4
	@ sp needed
	pop	{fp, pc}
.L32:
	.align	2
.L31:
	.word	RADEON_FP_VERT_STRETCH
	.word	RADEON_VERT_STRETCH_RESERVED
	.word	RADEON_VERT_AUTO_RATIO_INC
	.word	RADEON_FP_HORZ_STRETCH
	.word	RADEON_HORZ_FP_LOOP_STRETCH
	.word	RADEON_HORZ_AUTO_RATIO_INC
	.word	CHIP_RS100
	.word	CHIP_RS200
	.word	RADEON_CRTC_H_CUTOFF_ACTIVE_EN
	.word	33488896
	.word	DRM_MODE_FLAG_NHSYNC
	.word	RADEON_CRTC_H_SYNC_POL
	.word	DRM_MODE_FLAG_NVSYNC
	.word	RADEON_CRTC_V_SYNC_POL
	.word	RADEON_HORZ_STRETCH_RATIO_MAX
	.word	RADEON_HORZ_STRETCH_RATIO_MASK
	.word	RADEON_HORZ_STRETCH_BLEND
	.word	RADEON_HORZ_STRETCH_ENABLE
	.word	RADEON_VERT_STRETCH_RATIO_MAX
	.word	RADEON_VERT_STRETCH_RATIO_MASK
	.word	RADEON_VERT_STRETCH_ENABLE
	.word	RADEON_VERT_STRETCH_BLEND
	.word	RADEON_CRTC_AUTO_HORZ_CENTER_EN
	.word	RADEON_CRTC_AUTO_VERT_CENTER_EN
	.word	RADEON_CRTC_MORE_CNTL
	.word	RADEON_FP_HORZ_VERT_ACTIVE
	.word	RADEON_FP_H_SYNC_STRT_WID
	.word	RADEON_FP_V_SYNC_STRT_WID
	.word	RADEON_FP_CRTC_H_TOTAL_DISP
	.word	RADEON_FP_CRTC_V_TOTAL_DISP
	.size	radeon_legacy_rmx_mode_set, .-radeon_legacy_rmx_mode_set
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
