	.file	"496924.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	t16_l1
	.bss
	.type	t16_l1, @object
	.size	t16_l1, 1
t16_l1:
	.zero	1
	.globl	_x_t16_l1
	.type	_x_t16_l1, @object
	.size	_x_t16_l1, 1
_x_t16_l1:
	.zero	1
	.globl	t16_l0
	.type	t16_l0, @object
	.size	t16_l0, 1
t16_l0:
	.zero	1
	.globl	_x_t16_l0
	.type	_x_t16_l0, @object
	.size	_x_t16_l0, 1
_x_t16_l0:
	.zero	1
	.globl	t16_evt1
	.type	t16_evt1, @object
	.size	t16_evt1, 1
t16_evt1:
	.zero	1
	.globl	_x_t16_evt1
	.type	_x_t16_evt1, @object
	.size	_x_t16_evt1, 1
_x_t16_evt1:
	.zero	1
	.globl	t16_evt0
	.type	t16_evt0, @object
	.size	t16_evt0, 1
t16_evt0:
	.zero	1
	.globl	_x_t16_evt0
	.type	_x_t16_evt0, @object
	.size	_x_t16_evt0, 1
_x_t16_evt0:
	.zero	1
	.globl	t16_x
	.align 4
	.type	t16_x, @object
	.size	t16_x, 4
t16_x:
	.zero	4
	.globl	_x_t16_x
	.align 4
	.type	_x_t16_x, @object
	.size	_x_t16_x, 4
_x_t16_x:
	.zero	4
	.globl	t15_l1
	.type	t15_l1, @object
	.size	t15_l1, 1
t15_l1:
	.zero	1
	.globl	_x_t15_l1
	.type	_x_t15_l1, @object
	.size	_x_t15_l1, 1
_x_t15_l1:
	.zero	1
	.globl	t15_l0
	.type	t15_l0, @object
	.size	t15_l0, 1
t15_l0:
	.zero	1
	.globl	_x_t15_l0
	.type	_x_t15_l0, @object
	.size	_x_t15_l0, 1
_x_t15_l0:
	.zero	1
	.globl	t15_evt1
	.type	t15_evt1, @object
	.size	t15_evt1, 1
t15_evt1:
	.zero	1
	.globl	_x_t15_evt1
	.type	_x_t15_evt1, @object
	.size	_x_t15_evt1, 1
_x_t15_evt1:
	.zero	1
	.globl	t15_evt0
	.type	t15_evt0, @object
	.size	t15_evt0, 1
t15_evt0:
	.zero	1
	.globl	_x_t15_evt0
	.type	_x_t15_evt0, @object
	.size	_x_t15_evt0, 1
_x_t15_evt0:
	.zero	1
	.globl	t15_x
	.align 4
	.type	t15_x, @object
	.size	t15_x, 4
t15_x:
	.zero	4
	.globl	_x_t15_x
	.align 4
	.type	_x_t15_x, @object
	.size	_x_t15_x, 4
_x_t15_x:
	.zero	4
	.globl	t14_l1
	.type	t14_l1, @object
	.size	t14_l1, 1
t14_l1:
	.zero	1
	.globl	_x_t14_l1
	.type	_x_t14_l1, @object
	.size	_x_t14_l1, 1
_x_t14_l1:
	.zero	1
	.globl	t14_l0
	.type	t14_l0, @object
	.size	t14_l0, 1
t14_l0:
	.zero	1
	.globl	_x_t14_l0
	.type	_x_t14_l0, @object
	.size	_x_t14_l0, 1
_x_t14_l0:
	.zero	1
	.globl	t14_evt1
	.type	t14_evt1, @object
	.size	t14_evt1, 1
t14_evt1:
	.zero	1
	.globl	_x_t14_evt1
	.type	_x_t14_evt1, @object
	.size	_x_t14_evt1, 1
_x_t14_evt1:
	.zero	1
	.globl	t14_evt0
	.type	t14_evt0, @object
	.size	t14_evt0, 1
t14_evt0:
	.zero	1
	.globl	_x_t14_evt0
	.type	_x_t14_evt0, @object
	.size	_x_t14_evt0, 1
_x_t14_evt0:
	.zero	1
	.globl	t14_x
	.align 4
	.type	t14_x, @object
	.size	t14_x, 4
t14_x:
	.zero	4
	.globl	_x_t14_x
	.align 4
	.type	_x_t14_x, @object
	.size	_x_t14_x, 4
_x_t14_x:
	.zero	4
	.globl	t13_l1
	.type	t13_l1, @object
	.size	t13_l1, 1
t13_l1:
	.zero	1
	.globl	_x_t13_l1
	.type	_x_t13_l1, @object
	.size	_x_t13_l1, 1
_x_t13_l1:
	.zero	1
	.globl	t13_l0
	.type	t13_l0, @object
	.size	t13_l0, 1
t13_l0:
	.zero	1
	.globl	_x_t13_l0
	.type	_x_t13_l0, @object
	.size	_x_t13_l0, 1
_x_t13_l0:
	.zero	1
	.globl	t13_evt1
	.type	t13_evt1, @object
	.size	t13_evt1, 1
t13_evt1:
	.zero	1
	.globl	_x_t13_evt1
	.type	_x_t13_evt1, @object
	.size	_x_t13_evt1, 1
_x_t13_evt1:
	.zero	1
	.globl	t13_evt0
	.type	t13_evt0, @object
	.size	t13_evt0, 1
t13_evt0:
	.zero	1
	.globl	_x_t13_evt0
	.type	_x_t13_evt0, @object
	.size	_x_t13_evt0, 1
_x_t13_evt0:
	.zero	1
	.globl	t13_x
	.align 4
	.type	t13_x, @object
	.size	t13_x, 4
t13_x:
	.zero	4
	.globl	_x_t13_x
	.align 4
	.type	_x_t13_x, @object
	.size	_x_t13_x, 4
_x_t13_x:
	.zero	4
	.globl	t12_l1
	.type	t12_l1, @object
	.size	t12_l1, 1
t12_l1:
	.zero	1
	.globl	_x_t12_l1
	.type	_x_t12_l1, @object
	.size	_x_t12_l1, 1
_x_t12_l1:
	.zero	1
	.globl	t12_l0
	.type	t12_l0, @object
	.size	t12_l0, 1
t12_l0:
	.zero	1
	.globl	_x_t12_l0
	.type	_x_t12_l0, @object
	.size	_x_t12_l0, 1
_x_t12_l0:
	.zero	1
	.globl	t12_evt0
	.type	t12_evt0, @object
	.size	t12_evt0, 1
t12_evt0:
	.zero	1
	.globl	_x_t12_evt0
	.type	_x_t12_evt0, @object
	.size	_x_t12_evt0, 1
_x_t12_evt0:
	.zero	1
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	t12_x
	.align 4
	.type	t12_x, @object
	.size	t12_x, 4
t12_x:
	.zero	4
	.globl	_x_t12_x
	.align 4
	.type	_x_t12_x, @object
	.size	_x_t12_x, 4
_x_t12_x:
	.zero	4
	.globl	t10_l1
	.type	t10_l1, @object
	.size	t10_l1, 1
t10_l1:
	.zero	1
	.globl	_x_t10_l1
	.type	_x_t10_l1, @object
	.size	_x_t10_l1, 1
_x_t10_l1:
	.zero	1
	.globl	t10_l0
	.type	t10_l0, @object
	.size	t10_l0, 1
t10_l0:
	.zero	1
	.globl	_x_t10_l0
	.type	_x_t10_l0, @object
	.size	_x_t10_l0, 1
_x_t10_l0:
	.zero	1
	.globl	t10_evt1
	.type	t10_evt1, @object
	.size	t10_evt1, 1
t10_evt1:
	.zero	1
	.globl	_x_t10_evt1
	.type	_x_t10_evt1, @object
	.size	_x_t10_evt1, 1
_x_t10_evt1:
	.zero	1
	.globl	t10_evt0
	.type	t10_evt0, @object
	.size	t10_evt0, 1
t10_evt0:
	.zero	1
	.globl	_x_t10_evt0
	.type	_x_t10_evt0, @object
	.size	_x_t10_evt0, 1
_x_t10_evt0:
	.zero	1
	.globl	t10_x
	.align 4
	.type	t10_x, @object
	.size	t10_x, 4
t10_x:
	.zero	4
	.globl	_x_t10_x
	.align 4
	.type	_x_t10_x, @object
	.size	_x_t10_x, 4
_x_t10_x:
	.zero	4
	.globl	t9_l1
	.type	t9_l1, @object
	.size	t9_l1, 1
t9_l1:
	.zero	1
	.globl	_x_t9_l1
	.type	_x_t9_l1, @object
	.size	_x_t9_l1, 1
_x_t9_l1:
	.zero	1
	.globl	t9_l0
	.type	t9_l0, @object
	.size	t9_l0, 1
t9_l0:
	.zero	1
	.globl	_x_t9_l0
	.type	_x_t9_l0, @object
	.size	_x_t9_l0, 1
_x_t9_l0:
	.zero	1
	.globl	t9_evt1
	.type	t9_evt1, @object
	.size	t9_evt1, 1
t9_evt1:
	.zero	1
	.globl	_x_t9_evt1
	.type	_x_t9_evt1, @object
	.size	_x_t9_evt1, 1
_x_t9_evt1:
	.zero	1
	.globl	t9_evt0
	.type	t9_evt0, @object
	.size	t9_evt0, 1
t9_evt0:
	.zero	1
	.globl	_x_t9_evt0
	.type	_x_t9_evt0, @object
	.size	_x_t9_evt0, 1
_x_t9_evt0:
	.zero	1
	.globl	t3_x
	.align 4
	.type	t3_x, @object
	.size	t3_x, 4
t3_x:
	.zero	4
	.globl	_x_t3_x
	.align 4
	.type	_x_t3_x, @object
	.size	_x_t3_x, 4
_x_t3_x:
	.zero	4
	.globl	t2_evt1
	.type	t2_evt1, @object
	.size	t2_evt1, 1
t2_evt1:
	.zero	1
	.globl	_x_t2_evt1
	.type	_x_t2_evt1, @object
	.size	_x_t2_evt1, 1
_x_t2_evt1:
	.zero	1
	.globl	t11_evt0
	.type	t11_evt0, @object
	.size	t11_evt0, 1
t11_evt0:
	.zero	1
	.globl	_x_t11_evt0
	.type	_x_t11_evt0, @object
	.size	_x_t11_evt0, 1
_x_t11_evt0:
	.zero	1
	.globl	gate_evt0
	.type	gate_evt0, @object
	.size	gate_evt0, 1
gate_evt0:
	.zero	1
	.globl	_x_gate_evt0
	.type	_x_gate_evt0, @object
	.size	_x_gate_evt0, 1
_x_gate_evt0:
	.zero	1
	.globl	t2_l1
	.type	t2_l1, @object
	.size	t2_l1, 1
t2_l1:
	.zero	1
	.globl	_x_t2_l1
	.type	_x_t2_l1, @object
	.size	_x_t2_l1, 1
_x_t2_l1:
	.zero	1
	.globl	t11_l0
	.type	t11_l0, @object
	.size	t11_l0, 1
t11_l0:
	.zero	1
	.globl	_x_t11_l0
	.type	_x_t11_l0, @object
	.size	_x_t11_l0, 1
_x_t11_l0:
	.zero	1
	.globl	gate_l0
	.type	gate_l0, @object
	.size	gate_l0, 1
gate_l0:
	.zero	1
	.globl	_x_gate_l0
	.type	_x_gate_l0, @object
	.size	_x_gate_l0, 1
_x_gate_l0:
	.zero	1
	.globl	t3_evt0
	.type	t3_evt0, @object
	.size	t3_evt0, 1
t3_evt0:
	.zero	1
	.globl	_x_t3_evt0
	.type	_x_t3_evt0, @object
	.size	_x_t3_evt0, 1
_x_t3_evt0:
	.zero	1
	.globl	t2_l0
	.type	t2_l0, @object
	.size	t2_l0, 1
t2_l0:
	.zero	1
	.globl	_x_t2_l0
	.type	_x_t2_l0, @object
	.size	_x_t2_l0, 1
_x_t2_l0:
	.zero	1
	.globl	t2_x
	.align 4
	.type	t2_x, @object
	.size	t2_x, 4
t2_x:
	.zero	4
	.globl	_x_t2_x
	.align 4
	.type	_x_t2_x, @object
	.size	_x_t2_x, 4
_x_t2_x:
	.zero	4
	.globl	t1_evt1
	.type	t1_evt1, @object
	.size	t1_evt1, 1
t1_evt1:
	.zero	1
	.globl	_x_t1_evt1
	.type	_x_t1_evt1, @object
	.size	_x_t1_evt1, 1
_x_t1_evt1:
	.zero	1
	.globl	t1_l1
	.type	t1_l1, @object
	.size	t1_l1, 1
t1_l1:
	.zero	1
	.globl	_x_t1_l1
	.type	_x_t1_l1, @object
	.size	_x_t1_l1, 1
_x_t1_l1:
	.zero	1
	.globl	t2_evt0
	.type	t2_evt0, @object
	.size	t2_evt0, 1
t2_evt0:
	.zero	1
	.globl	_x_t2_evt0
	.type	_x_t2_evt0, @object
	.size	_x_t2_evt0, 1
_x_t2_evt0:
	.zero	1
	.globl	t0_l1
	.type	t0_l1, @object
	.size	t0_l1, 1
t0_l1:
	.zero	1
	.globl	_x_t0_l1
	.type	_x_t0_l1, @object
	.size	_x_t0_l1, 1
_x_t0_l1:
	.zero	1
	.globl	t0_evt1
	.type	t0_evt1, @object
	.size	t0_evt1, 1
t0_evt1:
	.zero	1
	.globl	_x_t0_evt1
	.type	_x_t0_evt1, @object
	.size	_x_t0_evt1, 1
_x_t0_evt1:
	.zero	1
	.globl	t0_x
	.align 4
	.type	t0_x, @object
	.size	t0_x, 4
t0_x:
	.zero	4
	.globl	_x_t0_x
	.align 4
	.type	_x_t0_x, @object
	.size	_x_t0_x, 4
_x_t0_x:
	.zero	4
	.globl	t12_evt1
	.type	t12_evt1, @object
	.size	t12_evt1, 1
t12_evt1:
	.zero	1
	.globl	_x_t12_evt1
	.type	_x_t12_evt1, @object
	.size	_x_t12_evt1, 1
_x_t12_evt1:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	t11_l1
	.type	t11_l1, @object
	.size	t11_l1, 1
t11_l1:
	.zero	1
	.globl	_x_t11_l1
	.type	_x_t11_l1, @object
	.size	_x_t11_l1, 1
_x_t11_l1:
	.zero	1
	.globl	gate_l1
	.type	gate_l1, @object
	.size	gate_l1, 1
gate_l1:
	.zero	1
	.globl	_x_gate_l1
	.type	_x_gate_l1, @object
	.size	_x_gate_l1, 1
_x_gate_l1:
	.zero	1
	.globl	t3_evt1
	.type	t3_evt1, @object
	.size	t3_evt1, 1
t3_evt1:
	.zero	1
	.globl	_x_t3_evt1
	.type	_x_t3_evt1, @object
	.size	_x_t3_evt1, 1
_x_t3_evt1:
	.zero	1
	.globl	t4_x
	.align 4
	.type	t4_x, @object
	.size	t4_x, 4
t4_x:
	.zero	4
	.globl	_x_t4_x
	.align 4
	.type	_x_t4_x, @object
	.size	_x_t4_x, 4
_x_t4_x:
	.zero	4
	.globl	t0_l0
	.type	t0_l0, @object
	.size	t0_l0, 1
t0_l0:
	.zero	1
	.globl	_x_t0_l0
	.type	_x_t0_l0, @object
	.size	_x_t0_l0, 1
_x_t0_l0:
	.zero	1
	.globl	t11_x
	.align 4
	.type	t11_x, @object
	.size	t11_x, 4
t11_x:
	.zero	4
	.globl	_x_t11_x
	.align 4
	.type	_x_t11_x, @object
	.size	_x_t11_x, 4
_x_t11_x:
	.zero	4
	.globl	gate_y
	.align 4
	.type	gate_y, @object
	.size	gate_y, 4
gate_y:
	.zero	4
	.globl	_x_gate_y
	.align 4
	.type	_x_gate_y, @object
	.size	_x_gate_y, 4
_x_gate_y:
	.zero	4
	.globl	t8_l0
	.type	t8_l0, @object
	.size	t8_l0, 1
t8_l0:
	.zero	1
	.globl	_x_t8_l0
	.type	_x_t8_l0, @object
	.size	_x_t8_l0, 1
_x_t8_l0:
	.zero	1
	.globl	t1_evt0
	.type	t1_evt0, @object
	.size	t1_evt0, 1
t1_evt0:
	.zero	1
	.globl	_x_t1_evt0
	.type	_x_t1_evt0, @object
	.size	_x_t1_evt0, 1
_x_t1_evt0:
	.zero	1
	.globl	controller_l1
	.type	controller_l1, @object
	.size	controller_l1, 1
controller_l1:
	.zero	1
	.globl	_x_controller_l1
	.type	_x_controller_l1, @object
	.size	_x_controller_l1, 1
_x_controller_l1:
	.zero	1
	.globl	t6_l0
	.type	t6_l0, @object
	.size	t6_l0, 1
t6_l0:
	.zero	1
	.globl	_x_t6_l0
	.type	_x_t6_l0, @object
	.size	_x_t6_l0, 1
_x_t6_l0:
	.zero	1
	.globl	t5_l0
	.type	t5_l0, @object
	.size	t5_l0, 1
t5_l0:
	.zero	1
	.globl	_x_t5_l0
	.type	_x_t5_l0, @object
	.size	_x_t5_l0, 1
_x_t5_l0:
	.zero	1
	.globl	t0_evt0
	.type	t0_evt0, @object
	.size	t0_evt0, 1
t0_evt0:
	.zero	1
	.globl	_x_t0_evt0
	.type	_x_t0_evt0, @object
	.size	_x_t0_evt0, 1
_x_t0_evt0:
	.zero	1
	.globl	t1_x
	.align 4
	.type	t1_x, @object
	.size	t1_x, 4
t1_x:
	.zero	4
	.globl	_x_t1_x
	.align 4
	.type	_x_t1_x, @object
	.size	_x_t1_x, 4
_x_t1_x:
	.zero	4
	.globl	controller_evt1
	.type	controller_evt1, @object
	.size	controller_evt1, 1
controller_evt1:
	.zero	1
	.globl	_x_controller_evt1
	.type	_x_controller_evt1, @object
	.size	_x_controller_evt1, 1
_x_controller_evt1:
	.zero	1
	.globl	t5_l1
	.type	t5_l1, @object
	.size	t5_l1, 1
t5_l1:
	.zero	1
	.globl	_x_t5_l1
	.type	_x_t5_l1, @object
	.size	_x_t5_l1, 1
_x_t5_l1:
	.zero	1
	.globl	t6_evt0
	.type	t6_evt0, @object
	.size	t6_evt0, 1
t6_evt0:
	.zero	1
	.globl	_x_t6_evt0
	.type	_x_t6_evt0, @object
	.size	_x_t6_evt0, 1
_x_t6_evt0:
	.zero	1
	.globl	t11_evt1
	.type	t11_evt1, @object
	.size	t11_evt1, 1
t11_evt1:
	.zero	1
	.globl	_x_t11_evt1
	.type	_x_t11_evt1, @object
	.size	_x_t11_evt1, 1
_x_t11_evt1:
	.zero	1
	.globl	gate_evt1
	.type	gate_evt1, @object
	.size	gate_evt1, 1
gate_evt1:
	.zero	1
	.globl	_x_gate_evt1
	.type	_x_gate_evt1, @object
	.size	_x_gate_evt1, 1
_x_gate_evt1:
	.zero	1
	.globl	t3_l1
	.type	t3_l1, @object
	.size	t3_l1, 1
t3_l1:
	.zero	1
	.globl	_x_t3_l1
	.type	_x_t3_l1, @object
	.size	_x_t3_l1, 1
_x_t3_l1:
	.zero	1
	.globl	t4_evt0
	.type	t4_evt0, @object
	.size	t4_evt0, 1
t4_evt0:
	.zero	1
	.globl	_x_t4_evt0
	.type	_x_t4_evt0, @object
	.size	_x_t4_evt0, 1
_x_t4_evt0:
	.zero	1
	.globl	controller_evt2
	.type	controller_evt2, @object
	.size	controller_evt2, 1
controller_evt2:
	.zero	1
	.globl	_x_controller_evt2
	.type	_x_controller_evt2, @object
	.size	_x_controller_evt2, 1
_x_controller_evt2:
	.zero	1
	.globl	controller_evt0
	.type	controller_evt0, @object
	.size	controller_evt0, 1
controller_evt0:
	.zero	1
	.globl	_x_controller_evt0
	.type	_x_controller_evt0, @object
	.size	_x_controller_evt0, 1
_x_controller_evt0:
	.zero	1
	.globl	t6_evt1
	.type	t6_evt1, @object
	.size	t6_evt1, 1
t6_evt1:
	.zero	1
	.globl	_x_t6_evt1
	.type	_x_t6_evt1, @object
	.size	_x_t6_evt1, 1
_x_t6_evt1:
	.zero	1
	.globl	t7_x
	.align 4
	.type	t7_x, @object
	.size	t7_x, 4
t7_x:
	.zero	4
	.globl	_x_t7_x
	.align 4
	.type	_x_t7_x, @object
	.size	_x_t7_x, 4
_x_t7_x:
	.zero	4
	.globl	t1_l0
	.type	t1_l0, @object
	.size	t1_l0, 1
t1_l0:
	.zero	1
	.globl	_x_t1_l0
	.type	_x_t1_l0, @object
	.size	_x_t1_l0, 1
_x_t1_l0:
	.zero	1
	.globl	controller_cnt
	.align 4
	.type	controller_cnt, @object
	.size	controller_cnt, 4
controller_cnt:
	.zero	4
	.globl	_x_controller_cnt
	.align 4
	.type	_x_controller_cnt, @object
	.size	_x_controller_cnt, 4
_x_controller_cnt:
	.zero	4
	.globl	t4_evt1
	.type	t4_evt1, @object
	.size	t4_evt1, 1
t4_evt1:
	.zero	1
	.globl	_x_t4_evt1
	.type	_x_t4_evt1, @object
	.size	_x_t4_evt1, 1
_x_t4_evt1:
	.zero	1
	.globl	t5_x
	.align 4
	.type	t5_x, @object
	.size	t5_x, 4
t5_x:
	.zero	4
	.globl	_x_t5_x
	.align 4
	.type	_x_t5_x, @object
	.size	_x_t5_x, 4
_x_t5_x:
	.zero	4
	.globl	t3_l0
	.type	t3_l0, @object
	.size	t3_l0, 1
t3_l0:
	.zero	1
	.globl	_x_t3_l0
	.type	_x_t3_l0, @object
	.size	_x_t3_l0, 1
_x_t3_l0:
	.zero	1
	.globl	t4_l0
	.type	t4_l0, @object
	.size	t4_l0, 1
t4_l0:
	.zero	1
	.globl	_x_t4_l0
	.type	_x_t4_l0, @object
	.size	_x_t4_l0, 1
_x_t4_l0:
	.zero	1
	.globl	controller_z
	.align 4
	.type	controller_z, @object
	.size	controller_z, 4
controller_z:
	.zero	4
	.globl	_x_controller_z
	.align 4
	.type	_x_controller_z, @object
	.size	_x_controller_z, 4
_x_controller_z:
	.zero	4
	.globl	t4_l1
	.type	t4_l1, @object
	.size	t4_l1, 1
t4_l1:
	.zero	1
	.globl	_x_t4_l1
	.type	_x_t4_l1, @object
	.size	_x_t4_l1, 1
_x_t4_l1:
	.zero	1
	.globl	t5_evt0
	.type	t5_evt0, @object
	.size	t5_evt0, 1
t5_evt0:
	.zero	1
	.globl	_x_t5_evt0
	.type	_x_t5_evt0, @object
	.size	_x_t5_evt0, 1
_x_t5_evt0:
	.zero	1
	.globl	t5_evt1
	.type	t5_evt1, @object
	.size	t5_evt1, 1
t5_evt1:
	.zero	1
	.globl	_x_t5_evt1
	.type	_x_t5_evt1, @object
	.size	_x_t5_evt1, 1
_x_t5_evt1:
	.zero	1
	.globl	t6_x
	.align 4
	.type	t6_x, @object
	.size	t6_x, 4
t6_x:
	.zero	4
	.globl	_x_t6_x
	.align 4
	.type	_x_t6_x, @object
	.size	_x_t6_x, 4
_x_t6_x:
	.zero	4
	.globl	controller_l0
	.type	controller_l0, @object
	.size	controller_l0, 1
controller_l0:
	.zero	1
	.globl	_x_controller_l0
	.type	_x_controller_l0, @object
	.size	_x_controller_l0, 1
_x_controller_l0:
	.zero	1
	.globl	t6_l1
	.type	t6_l1, @object
	.size	t6_l1, 1
t6_l1:
	.zero	1
	.globl	_x_t6_l1
	.type	_x_t6_l1, @object
	.size	_x_t6_l1, 1
_x_t6_l1:
	.zero	1
	.globl	t7_evt0
	.type	t7_evt0, @object
	.size	t7_evt0, 1
t7_evt0:
	.zero	1
	.globl	_x_t7_evt0
	.type	_x_t7_evt0, @object
	.size	_x_t7_evt0, 1
_x_t7_evt0:
	.zero	1
	.globl	t7_evt1
	.type	t7_evt1, @object
	.size	t7_evt1, 1
t7_evt1:
	.zero	1
	.globl	_x_t7_evt1
	.type	_x_t7_evt1, @object
	.size	_x_t7_evt1, 1
_x_t7_evt1:
	.zero	1
	.globl	t8_x
	.align 4
	.type	t8_x, @object
	.size	t8_x, 4
t8_x:
	.zero	4
	.globl	_x_t8_x
	.align 4
	.type	_x_t8_x, @object
	.size	_x_t8_x, 4
_x_t8_x:
	.zero	4
	.globl	t7_l0
	.type	t7_l0, @object
	.size	t7_l0, 1
t7_l0:
	.zero	1
	.globl	_x_t7_l0
	.type	_x_t7_l0, @object
	.size	_x_t7_l0, 1
_x_t7_l0:
	.zero	1
	.globl	t7_l1
	.type	t7_l1, @object
	.size	t7_l1, 1
t7_l1:
	.zero	1
	.globl	_x_t7_l1
	.type	_x_t7_l1, @object
	.size	_x_t7_l1, 1
_x_t7_l1:
	.zero	1
	.globl	t8_evt0
	.type	t8_evt0, @object
	.size	t8_evt0, 1
t8_evt0:
	.zero	1
	.globl	_x_t8_evt0
	.type	_x_t8_evt0, @object
	.size	_x_t8_evt0, 1
_x_t8_evt0:
	.zero	1
	.globl	t8_evt1
	.type	t8_evt1, @object
	.size	t8_evt1, 1
t8_evt1:
	.zero	1
	.globl	_x_t8_evt1
	.type	_x_t8_evt1, @object
	.size	_x_t8_evt1, 1
_x_t8_evt1:
	.zero	1
	.globl	t9_x
	.align 4
	.type	t9_x, @object
	.size	t9_x, 4
t9_x:
	.zero	4
	.globl	_x_t9_x
	.align 4
	.type	_x_t9_x, @object
	.size	_x_t9_x, 4
_x_t9_x:
	.zero	4
	.globl	t8_l1
	.type	t8_l1, @object
	.size	t8_l1, 1
t8_l1:
	.zero	1
	.globl	_x_t8_l1
	.type	_x_t8_l1, @object
	.size	_x_t8_l1, 1
_x_t8_l1:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t16_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t16_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t16_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t16_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t16_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t15_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t15_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t15_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t15_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t15_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t14_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t14_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t14_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t14_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t14_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t13_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t13_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t12_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t4_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t11_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t0_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR gate_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t1_l0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR controller_cnt[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t5_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR controller_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR t9_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR t8_l1[rip], al
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L4
.L7:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L11
.L10:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L12
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L11
.L12:
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L11
.L13:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L4
.L11:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L14
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L15
.L14:
	movss	xmm1, DWORD PTR t16_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L15:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L18
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L19
.L18:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L19
.L20:
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L19
.L21:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L4
.L19:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L23
.L22:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L23
.L24:
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L23
.L25:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L4
.L23:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L27
.L26:
	movss	xmm1, DWORD PTR t15_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L27:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L31
.L30:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L31
.L32:
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L33
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L31
.L33:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L4
.L31:
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L34
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L35
.L34:
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L35
.L36:
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L35
.L37:
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L4
.L35:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L39
.L38:
	movss	xmm1, DWORD PTR t14_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L39:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L42
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L43
.L42:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L44
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L43
.L44:
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L43
.L45:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L4
.L43:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L46
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L47
.L46:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L47
.L48:
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L47
.L49:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L4
.L47:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L50
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L51
.L50:
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L51:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L55
.L54:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L55
.L56:
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L55
.L57:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L4
.L55:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L59
.L58:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L59
.L60:
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L61
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L59
.L61:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L4
.L59:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L62
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L63
.L62:
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L63:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L66
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L67
.L66:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L68
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L67
.L68:
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L69
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L67
.L69:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L4
.L67:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L70
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L71
.L70:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L71
.L72:
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L73
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L71
.L73:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L4
.L71:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L75
.L74:
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L75:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L78
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L79
.L78:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L80
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L79
.L80:
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L79
.L81:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L4
.L79:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L83
.L82:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L83
.L84:
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L85
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L83
.L85:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L4
.L83:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L86
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L87
.L86:
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L87:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L90
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L91
.L90:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L91
.L92:
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L91
.L93:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L4
.L91:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L94
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L95
.L94:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L95
.L96:
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L95
.L97:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L4
.L95:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L98
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L99
.L98:
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L99:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L102
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L103
.L102:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L104
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L103
.L104:
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L103
.L105:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L4
.L103:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L107
.L106:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L107
.L108:
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L107
.L109:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L4
.L107:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L111
.L110:
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L111:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L115
.L114:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L115
.L116:
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L117
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L115
.L117:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L4
.L115:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L118
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L119
.L118:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L119
.L120:
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L121
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L119
.L121:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L4
.L119:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L123
.L122:
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L123:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L126
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L127
.L126:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L127
.L128:
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L129
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L127
.L129:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L4
.L127:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L131
.L130:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L132
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L131
.L132:
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L131
.L133:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L4
.L131:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L134
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L135
.L134:
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L135:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L139
.L138:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L139
.L140:
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L139
.L141:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L4
.L139:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L142
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L143
.L142:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L143
.L144:
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L143
.L145:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L4
.L143:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L147
.L146:
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L147:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L150
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L151
.L150:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L152
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L151
.L152:
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L151
.L153:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L4
.L151:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L154
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L155
.L154:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L155
.L156:
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L157
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L155
.L157:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L4
.L155:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L159
.L158:
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L159:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L163
.L162:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L164
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L163
.L164:
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L163
.L165:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L4
.L163:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L167
.L166:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L167
.L168:
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L167
.L169:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L4
.L167:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L170
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L171
.L170:
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L171:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L174
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L175
.L174:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L175
.L176:
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L177
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L175
.L177:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L4
.L175:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L178
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L179
.L178:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L180
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L179
.L180:
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L179
.L181:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L4
.L179:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L182
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L183
.L182:
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L183:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L187
.L186:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L187
.L188:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L187
.L189:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L4
.L187:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L191
.L190:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L191
.L192:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L191
.L193:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L4
.L191:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L195
.L194:
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L195:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L199
.L198:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L199
.L200:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L199
.L201:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L4
.L199:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L202
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L203
.L202:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L203
.L204:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L203
.L205:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L4
.L203:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L207
.L206:
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L4
.L207:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L211
.L210:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L211
.L212:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L213
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L211
.L213:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L211:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L215
.L214:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L216
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L215
.L216:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L215
.L217:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L218
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L218
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L215
.L218:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L4
.L215:
	mov	eax, DWORD PTR controller_cnt[rip]
	test	eax, eax
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 2
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 3
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 4
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 5
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 6
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 7
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 8
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 9
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 10
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 11
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 12
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 13
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 14
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 15
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 16
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 17
	je	.L219
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 18
	jne	.L4
.L219:
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L220
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L4
.L221:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L4
.L220:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L223
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L224
.L223:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L224
.L225:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L224
.L226:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L224:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L227
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L228
.L227:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L228
.L229:
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L230
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L228
.L230:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L4
.L228:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L231
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L231
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L4
.L231:
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L232
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L4
.L232:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L235
.L4:
	mov	eax, 0
.L235:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L236
.L888:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t16_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t16_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t16_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t16_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t16_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t15_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t15_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t15_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t15_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t15_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t14_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t14_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t14_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t14_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t14_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t13_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t13_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t12_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t10_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t10_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t9_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t2_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t2_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t12_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t4_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t11_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_gate_y[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t0_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t11_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_gate_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t1_l0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_controller_cnt[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t5_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t3_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_controller_z[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t5_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t6_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_controller_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t8_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t7_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_t9_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_t8_l1[rip], al
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	jne	.L237
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L238
.L237:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L239
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L238
.L239:
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L240
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L238
.L240:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L241
.L238:
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	test	al, al
	jne	.L242
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	test	al, al
	je	.L243
.L242:
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	test	al, al
	je	.L244
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	test	al, al
	je	.L243
.L244:
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	test	al, al
	je	.L243
.L245:
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	test	al, al
	je	.L241
.L243:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	jne	.L246
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L247
.L246:
	movss	xmm1, DWORD PTR _x_t16_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L247:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L249
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t16_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t16_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L249
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L250
.L249:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L250
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L241
.L250:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	jne	.L253
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L253
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L253
	movss	xmm0, DWORD PTR _x_t16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L253
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L254
.L253:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L254
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	jne	.L254
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L254
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L254
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L241
.L254:
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	jne	.L256
	movss	xmm1, DWORD PTR t16_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L256
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L256
	movss	xmm0, DWORD PTR t16_x[rip]
	movss	xmm1, DWORD PTR _x_t16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L256
	ucomiss	xmm0, xmm1
	je	.L257
.L256:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	jne	.L257
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L257
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L257
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L241
.L257:
	movss	xmm0, DWORD PTR t16_x[rip]
	movss	xmm1, DWORD PTR _x_t16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L259
	ucomiss	xmm0, xmm1
	jne	.L259
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	je	.L259
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	je	.L259
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L259
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L261
.L259:
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L261
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	jne	.L261
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L261
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L261
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L241
.L261:
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	test	al, al
	jne	.L262
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	test	al, al
	jne	.L262
	movss	xmm1, DWORD PTR t16_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L262
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L262
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L262
	movss	xmm0, DWORD PTR t16_x[rip]
	movss	xmm1, DWORD PTR _x_t16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L262
	ucomiss	xmm0, xmm1
	je	.L264
.L262:
	movzx	eax, BYTE PTR t16_l0[rip]
	test	al, al
	je	.L264
	movzx	eax, BYTE PTR t16_l1[rip]
	test	al, al
	je	.L264
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L264
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L264
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L241
.L264:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L267
.L266:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L268
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L267
.L268:
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L269
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L267
.L269:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L241
.L267:
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	test	al, al
	jne	.L270
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	test	al, al
	je	.L271
.L270:
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	test	al, al
	je	.L272
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	test	al, al
	je	.L271
.L272:
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	test	al, al
	je	.L273
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	test	al, al
	je	.L271
.L273:
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	test	al, al
	je	.L241
.L271:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L275
.L274:
	movss	xmm1, DWORD PTR _x_t15_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L275:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L277
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L277
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t15_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t15_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L277
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L278
.L277:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L241
.L278:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L281
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	jne	.L281
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L281
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L281
	movss	xmm0, DWORD PTR _x_t15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L281
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L282
.L281:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L282
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	jne	.L282
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L282
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L282
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L241
.L282:
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	jne	.L284
	movss	xmm1, DWORD PTR t15_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L284
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L284
	movss	xmm0, DWORD PTR t15_x[rip]
	movss	xmm1, DWORD PTR _x_t15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L284
	ucomiss	xmm0, xmm1
	je	.L285
.L284:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L285
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	jne	.L285
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L285
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L285
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L241
.L285:
	movss	xmm0, DWORD PTR t15_x[rip]
	movss	xmm1, DWORD PTR _x_t15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L287
	ucomiss	xmm0, xmm1
	jne	.L287
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	je	.L287
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	je	.L287
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L287
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L289
.L287:
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L289
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	jne	.L289
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L289
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L289
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L241
.L289:
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	test	al, al
	jne	.L290
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	test	al, al
	jne	.L290
	movss	xmm1, DWORD PTR t15_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L290
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L290
	movss	xmm0, DWORD PTR t15_x[rip]
	movss	xmm1, DWORD PTR _x_t15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L290
	ucomiss	xmm0, xmm1
	je	.L292
.L290:
	movzx	eax, BYTE PTR t15_l0[rip]
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR t15_l1[rip]
	test	al, al
	je	.L292
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L292
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L292
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L241
.L292:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	jne	.L294
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L295
.L294:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L296
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L295
.L296:
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L297
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L295
.L297:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L241
.L295:
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	test	al, al
	jne	.L298
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	test	al, al
	je	.L299
.L298:
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	test	al, al
	je	.L300
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	test	al, al
	je	.L299
.L300:
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	test	al, al
	je	.L299
.L301:
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	test	al, al
	je	.L241
.L299:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	jne	.L302
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L303
.L302:
	movss	xmm1, DWORD PTR _x_t14_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L303:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L305
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L305
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t14_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t14_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L305
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L306
.L305:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L306
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L241
.L306:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	jne	.L309
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L309
	movss	xmm0, DWORD PTR _x_t14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L309
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L310
.L309:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L310
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	jne	.L310
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L310
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L310
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L241
.L310:
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	jne	.L312
	movss	xmm1, DWORD PTR t14_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L312
	movss	xmm0, DWORD PTR t14_x[rip]
	movss	xmm1, DWORD PTR _x_t14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L312
	ucomiss	xmm0, xmm1
	je	.L313
.L312:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	jne	.L313
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L313
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L313
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L241
.L313:
	movss	xmm0, DWORD PTR t14_x[rip]
	movss	xmm1, DWORD PTR _x_t14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L315
	ucomiss	xmm0, xmm1
	jne	.L315
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L317
.L315:
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L317
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	jne	.L317
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L317
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L317
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L241
.L317:
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	test	al, al
	jne	.L318
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	test	al, al
	jne	.L318
	movss	xmm1, DWORD PTR t14_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L318
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L318
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L318
	movss	xmm0, DWORD PTR t14_x[rip]
	movss	xmm1, DWORD PTR _x_t14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L318
	ucomiss	xmm0, xmm1
	je	.L320
.L318:
	movzx	eax, BYTE PTR t14_l0[rip]
	test	al, al
	je	.L320
	movzx	eax, BYTE PTR t14_l1[rip]
	test	al, al
	je	.L320
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L320
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L320
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L241
.L320:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L322
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L323
.L322:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L324
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L323
.L324:
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L323
.L325:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L241
.L323:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	jne	.L326
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L327
.L326:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L328
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L327
.L328:
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L327
.L329:
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	test	al, al
	je	.L241
.L327:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L330
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L331
.L330:
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L331:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L333
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L333
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t13_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t13_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L333
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L334
.L333:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L334
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L241
.L334:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L337
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	jne	.L337
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L337
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L337
	movss	xmm0, DWORD PTR _x_t13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L337
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L338
.L337:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L338
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L338
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L338
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L338
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L241
.L338:
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L340
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L340
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L340
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L340
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L340
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L340
	ucomiss	xmm0, xmm1
	je	.L341
.L340:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L341
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	jne	.L341
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L341
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L341
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L241
.L341:
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L343
	ucomiss	xmm0, xmm1
	jne	.L343
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	je	.L343
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	je	.L343
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L343
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L345
.L343:
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	jne	.L345
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L345
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L345
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L241
.L345:
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	test	al, al
	jne	.L346
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	test	al, al
	jne	.L346
	movss	xmm1, DWORD PTR t13_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L346
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L346
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L346
	movss	xmm0, DWORD PTR t13_x[rip]
	movss	xmm1, DWORD PTR _x_t13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L346
	ucomiss	xmm0, xmm1
	je	.L348
.L346:
	movzx	eax, BYTE PTR t13_l0[rip]
	test	al, al
	je	.L348
	movzx	eax, BYTE PTR t13_l1[rip]
	test	al, al
	je	.L348
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L348
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L348
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L241
.L348:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L350
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L351
.L350:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L352
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L351
.L352:
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L353
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L351
.L353:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L241
.L351:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	jne	.L354
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L355
.L354:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L356
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L355
.L356:
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L355
.L357:
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	test	al, al
	je	.L241
.L355:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L358
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L359
.L358:
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L359:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L361
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L361
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L361
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L362
.L361:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L362
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L241
.L362:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	jne	.L365
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L365
	movss	xmm0, DWORD PTR _x_t12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L365
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L366
.L365:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L366
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L366
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L366
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L366
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L241
.L366:
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L368
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L368
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L368
	ucomiss	xmm0, xmm1
	je	.L369
.L368:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L369
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	jne	.L369
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L369
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L369
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L241
.L369:
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L371
	ucomiss	xmm0, xmm1
	jne	.L371
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	je	.L371
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	je	.L371
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L371
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L373
.L371:
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	jne	.L373
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L373
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L373
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L241
.L373:
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	test	al, al
	jne	.L374
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	test	al, al
	jne	.L374
	movss	xmm1, DWORD PTR t12_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L374
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L374
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L374
	movss	xmm0, DWORD PTR t12_x[rip]
	movss	xmm1, DWORD PTR _x_t12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L374
	ucomiss	xmm0, xmm1
	je	.L376
.L374:
	movzx	eax, BYTE PTR t12_l0[rip]
	test	al, al
	je	.L376
	movzx	eax, BYTE PTR t12_l1[rip]
	test	al, al
	je	.L376
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L376
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L376
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L241
.L376:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L378
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L379
.L378:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L380
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L379
.L380:
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L379
.L381:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L241
.L379:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	jne	.L382
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L383
.L382:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L384
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L383
.L384:
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L385
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L383
.L385:
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	test	al, al
	je	.L241
.L383:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L386
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L387
.L386:
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L387:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L389
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L389
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L389
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L390
.L389:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L390
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L241
.L390:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	jne	.L393
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L393
	movss	xmm0, DWORD PTR _x_t11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L393
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L394
.L393:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L394
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L394
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L394
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L394
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L241
.L394:
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L396
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L396
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L396
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L396
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L396
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L396
	ucomiss	xmm0, xmm1
	je	.L397
.L396:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L397
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	jne	.L397
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L397
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L397
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L241
.L397:
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L399
	ucomiss	xmm0, xmm1
	jne	.L399
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	je	.L399
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	je	.L399
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L399
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L401
.L399:
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	jne	.L401
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L401
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L401
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L241
.L401:
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	test	al, al
	jne	.L402
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	test	al, al
	jne	.L402
	movss	xmm1, DWORD PTR t11_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L402
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L402
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L402
	movss	xmm0, DWORD PTR t11_x[rip]
	movss	xmm1, DWORD PTR _x_t11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L402
	ucomiss	xmm0, xmm1
	je	.L404
.L402:
	movzx	eax, BYTE PTR t11_l0[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR t11_l1[rip]
	test	al, al
	je	.L404
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L404
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L404
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L241
.L404:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L406
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L407
.L406:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L408
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L407
.L408:
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L409
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L407
.L409:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L241
.L407:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	jne	.L410
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L411
.L410:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L412
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L411
.L412:
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L413
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L411
.L413:
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	test	al, al
	je	.L241
.L411:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L414
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L415
.L414:
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L415:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L417
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L417
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L418
.L417:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L418
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L241
.L418:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	jne	.L421
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L421
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L421
	movss	xmm0, DWORD PTR _x_t10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L421
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L422
.L421:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L422
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L422
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L422
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L422
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L241
.L422:
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L424
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L424
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L424
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L424
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L424
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L424
	ucomiss	xmm0, xmm1
	je	.L425
.L424:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L425
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	jne	.L425
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L425
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L425
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L241
.L425:
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L427
	ucomiss	xmm0, xmm1
	jne	.L427
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	je	.L427
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	je	.L427
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L427
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L429
.L427:
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	jne	.L429
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L429
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L429
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L241
.L429:
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	test	al, al
	jne	.L430
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	test	al, al
	jne	.L430
	movss	xmm1, DWORD PTR t10_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L430
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L430
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L430
	movss	xmm0, DWORD PTR t10_x[rip]
	movss	xmm1, DWORD PTR _x_t10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L430
	ucomiss	xmm0, xmm1
	je	.L432
.L430:
	movzx	eax, BYTE PTR t10_l0[rip]
	test	al, al
	je	.L432
	movzx	eax, BYTE PTR t10_l1[rip]
	test	al, al
	je	.L432
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L432
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L432
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L241
.L432:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L434
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L435
.L434:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L436
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L435
.L436:
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L435
.L437:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L241
.L435:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	jne	.L438
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L439
.L438:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L439
.L440:
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L441
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L439
.L441:
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	test	al, al
	je	.L241
.L439:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L442
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L443
.L442:
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L443:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L445
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L445
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L445
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L446
.L445:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L446
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L241
.L446:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L449
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	jne	.L449
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L449
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L449
	movss	xmm0, DWORD PTR _x_t9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L449
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L450
.L449:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L450
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L450
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L450
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L450
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L241
.L450:
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L452
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L452
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L452
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L452
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L452
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L452
	ucomiss	xmm0, xmm1
	je	.L453
.L452:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L453
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	jne	.L453
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L453
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L453
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L241
.L453:
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L455
	ucomiss	xmm0, xmm1
	jne	.L455
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	je	.L455
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	je	.L455
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L455
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L457
.L455:
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L457
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	jne	.L457
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L457
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L457
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L241
.L457:
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	test	al, al
	jne	.L458
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	test	al, al
	jne	.L458
	movss	xmm1, DWORD PTR t9_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L458
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L458
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L458
	movss	xmm0, DWORD PTR t9_x[rip]
	movss	xmm1, DWORD PTR _x_t9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L458
	ucomiss	xmm0, xmm1
	je	.L460
.L458:
	movzx	eax, BYTE PTR t9_l0[rip]
	test	al, al
	je	.L460
	movzx	eax, BYTE PTR t9_l1[rip]
	test	al, al
	je	.L460
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L460
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L460
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L241
.L460:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L462
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L463
.L462:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L464
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L463
.L464:
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L463
.L465:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L241
.L463:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	jne	.L466
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L467
.L466:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L468
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L467
.L468:
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L467
.L469:
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	test	al, al
	je	.L241
.L467:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L470
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L471
.L470:
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L471:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L473
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L473
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L474
.L473:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L474
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L241
.L474:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L477
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	jne	.L477
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L477
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L477
	movss	xmm0, DWORD PTR _x_t8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L477
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L478
.L477:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L478
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L478
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L478
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L478
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L241
.L478:
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L480
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L480
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L480
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L480
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L480
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L480
	ucomiss	xmm0, xmm1
	je	.L481
.L480:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L481
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	jne	.L481
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L481
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L481
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L241
.L481:
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L483
	ucomiss	xmm0, xmm1
	jne	.L483
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	je	.L483
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	je	.L483
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L483
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L485
.L483:
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L485
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	jne	.L485
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L485
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L485
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L241
.L485:
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	test	al, al
	jne	.L486
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	test	al, al
	jne	.L486
	movss	xmm1, DWORD PTR t8_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L486
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L486
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L486
	movss	xmm0, DWORD PTR t8_x[rip]
	movss	xmm1, DWORD PTR _x_t8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L486
	ucomiss	xmm0, xmm1
	je	.L488
.L486:
	movzx	eax, BYTE PTR t8_l0[rip]
	test	al, al
	je	.L488
	movzx	eax, BYTE PTR t8_l1[rip]
	test	al, al
	je	.L488
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L488
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L488
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L241
.L488:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L490
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L491
.L490:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L492
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L491
.L492:
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L493
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L491
.L493:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L241
.L491:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	jne	.L494
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L495
.L494:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L496
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L495
.L496:
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L497
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L495
.L497:
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	test	al, al
	je	.L241
.L495:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L498
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L499
.L498:
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L499:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L501
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L501
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L501
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L502
.L501:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L502
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L241
.L502:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	jne	.L505
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L505
	movss	xmm0, DWORD PTR _x_t7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L505
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L506
.L505:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L506
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L506
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L506
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L506
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L241
.L506:
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L508
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L508
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L508
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L508
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L508
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L508
	ucomiss	xmm0, xmm1
	je	.L509
.L508:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	jne	.L509
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L509
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L509
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L241
.L509:
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L511
	ucomiss	xmm0, xmm1
	jne	.L511
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	je	.L511
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	je	.L511
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L511
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L513
.L511:
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L513
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	jne	.L513
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L513
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L513
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L241
.L513:
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	test	al, al
	jne	.L514
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	test	al, al
	jne	.L514
	movss	xmm1, DWORD PTR t7_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L514
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L514
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L514
	movss	xmm0, DWORD PTR t7_x[rip]
	movss	xmm1, DWORD PTR _x_t7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L514
	ucomiss	xmm0, xmm1
	je	.L516
.L514:
	movzx	eax, BYTE PTR t7_l0[rip]
	test	al, al
	je	.L516
	movzx	eax, BYTE PTR t7_l1[rip]
	test	al, al
	je	.L516
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L516
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L516
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L241
.L516:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L518
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L519
.L518:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L520
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L519
.L520:
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L521
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L519
.L521:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L241
.L519:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	jne	.L522
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L523
.L522:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L524
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L523
.L524:
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L523
.L525:
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	test	al, al
	je	.L241
.L523:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L526
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L527
.L526:
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L527:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L529
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L529
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L529
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L530
.L529:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L530
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L241
.L530:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L533
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	jne	.L533
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L533
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L533
	movss	xmm0, DWORD PTR _x_t6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L533
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L534
.L533:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L534
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L534
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L534
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L241
.L534:
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L536
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L536
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L536
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L536
	ucomiss	xmm0, xmm1
	je	.L537
.L536:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	jne	.L537
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L537
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L537
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L241
.L537:
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L539
	ucomiss	xmm0, xmm1
	jne	.L539
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	je	.L539
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	je	.L539
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L539
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L541
.L539:
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L541
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	jne	.L541
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L541
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L541
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L241
.L541:
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	test	al, al
	jne	.L542
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	test	al, al
	jne	.L542
	movss	xmm1, DWORD PTR t6_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L542
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L542
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L542
	movss	xmm0, DWORD PTR t6_x[rip]
	movss	xmm1, DWORD PTR _x_t6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L542
	ucomiss	xmm0, xmm1
	je	.L544
.L542:
	movzx	eax, BYTE PTR t6_l0[rip]
	test	al, al
	je	.L544
	movzx	eax, BYTE PTR t6_l1[rip]
	test	al, al
	je	.L544
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L544
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L544
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L241
.L544:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L546
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L547
.L546:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L547
.L548:
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L549
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L547
.L549:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L241
.L547:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	jne	.L550
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L551
.L550:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L552
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L551
.L552:
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L553
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L551
.L553:
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	test	al, al
	je	.L241
.L551:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L554
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L555
.L554:
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L555:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L557
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L557
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L557
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L558
.L557:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L558
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L241
.L558:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	jne	.L561
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L561
	movss	xmm0, DWORD PTR _x_t5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L561
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L562
.L561:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L562
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L562
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L562
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L562
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L241
.L562:
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L564
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L564
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L564
	ucomiss	xmm0, xmm1
	je	.L565
.L564:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L565
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	jne	.L565
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L565
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L565
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L241
.L565:
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L567
	ucomiss	xmm0, xmm1
	jne	.L567
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	je	.L567
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	je	.L567
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L567
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L569
.L567:
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L569
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	jne	.L569
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L569
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L569
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L241
.L569:
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	test	al, al
	jne	.L570
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	test	al, al
	jne	.L570
	movss	xmm1, DWORD PTR t5_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L570
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L570
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L570
	movss	xmm0, DWORD PTR t5_x[rip]
	movss	xmm1, DWORD PTR _x_t5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L570
	ucomiss	xmm0, xmm1
	je	.L572
.L570:
	movzx	eax, BYTE PTR t5_l0[rip]
	test	al, al
	je	.L572
	movzx	eax, BYTE PTR t5_l1[rip]
	test	al, al
	je	.L572
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L572
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L572
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L241
.L572:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L574
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L575
.L574:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L576
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L575
.L576:
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L577
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L575
.L577:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L241
.L575:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	jne	.L578
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L579
.L578:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L580
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L579
.L580:
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L579
.L581:
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	test	al, al
	je	.L241
.L579:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L582
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L583
.L582:
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L583:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L585
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L585
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L585
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L586
.L585:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L586
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L241
.L586:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L589
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	jne	.L589
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L589
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L589
	movss	xmm0, DWORD PTR _x_t4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L589
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L590
.L589:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L590
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L590
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L590
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L590
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L241
.L590:
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L592
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L592
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L592
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L592
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L592
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L592
	ucomiss	xmm0, xmm1
	je	.L593
.L592:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L593
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	jne	.L593
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L593
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L593
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L241
.L593:
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L595
	ucomiss	xmm0, xmm1
	jne	.L595
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	je	.L595
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	je	.L595
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L595
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L597
.L595:
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	jne	.L597
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L597
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L597
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L241
.L597:
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	test	al, al
	jne	.L598
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	test	al, al
	jne	.L598
	movss	xmm1, DWORD PTR t4_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L598
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L598
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L598
	movss	xmm0, DWORD PTR t4_x[rip]
	movss	xmm1, DWORD PTR _x_t4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L598
	ucomiss	xmm0, xmm1
	je	.L600
.L598:
	movzx	eax, BYTE PTR t4_l0[rip]
	test	al, al
	je	.L600
	movzx	eax, BYTE PTR t4_l1[rip]
	test	al, al
	je	.L600
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L600
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L600
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L241
.L600:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L602
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L603
.L602:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L604
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L603
.L604:
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L605
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L603
.L605:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L241
.L603:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	jne	.L606
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L607
.L606:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L608
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L607
.L608:
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L607
.L609:
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	test	al, al
	je	.L241
.L607:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L610
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L611
.L610:
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L611:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L613
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L613
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L613
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L614
.L613:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L614
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L241
.L614:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L617
	movss	xmm0, DWORD PTR _x_t3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L617
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L618
.L617:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L618
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L618
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L618
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L618
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L241
.L618:
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L620
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L620
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L620
	ucomiss	xmm0, xmm1
	je	.L621
.L620:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L621
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	jne	.L621
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L621
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L621
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L241
.L621:
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L623
	ucomiss	xmm0, xmm1
	jne	.L623
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	je	.L623
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	je	.L623
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L623
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L625
.L623:
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L625
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	jne	.L625
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L625
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L625
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L241
.L625:
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	test	al, al
	jne	.L626
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	test	al, al
	jne	.L626
	movss	xmm1, DWORD PTR t3_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L626
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L626
	movss	xmm0, DWORD PTR t3_x[rip]
	movss	xmm1, DWORD PTR _x_t3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L626
	ucomiss	xmm0, xmm1
	je	.L628
.L626:
	movzx	eax, BYTE PTR t3_l0[rip]
	test	al, al
	je	.L628
	movzx	eax, BYTE PTR t3_l1[rip]
	test	al, al
	je	.L628
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L628
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L628
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L241
.L628:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L630
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L631
.L630:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L632
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L631
.L632:
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L631
.L633:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L241
.L631:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	jne	.L634
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L635
.L634:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L636
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L635
.L636:
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L637
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L635
.L637:
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	test	al, al
	je	.L241
.L635:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L638
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L639
.L638:
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L639:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L641
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L641
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L641
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L642
.L641:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L241
.L642:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	jne	.L645
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L645
	movss	xmm0, DWORD PTR _x_t2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L645
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L646
.L645:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L646
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L646
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L646
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L646
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L241
.L646:
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L648
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L648
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L648
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L648
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L648
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L648
	ucomiss	xmm0, xmm1
	je	.L649
.L648:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L649
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	jne	.L649
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L649
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L649
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L241
.L649:
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L651
	ucomiss	xmm0, xmm1
	jne	.L651
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	je	.L651
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	je	.L651
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L651
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L653
.L651:
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	jne	.L653
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L653
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L653
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L241
.L653:
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	test	al, al
	jne	.L654
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	test	al, al
	jne	.L654
	movss	xmm1, DWORD PTR t2_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L654
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L654
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L654
	movss	xmm0, DWORD PTR t2_x[rip]
	movss	xmm1, DWORD PTR _x_t2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L654
	ucomiss	xmm0, xmm1
	je	.L656
.L654:
	movzx	eax, BYTE PTR t2_l0[rip]
	test	al, al
	je	.L656
	movzx	eax, BYTE PTR t2_l1[rip]
	test	al, al
	je	.L656
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L656
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L656
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L241
.L656:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L658
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L659
.L658:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L660
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L659
.L660:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L661
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L659
.L661:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L241
.L659:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	jne	.L662
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L663
.L662:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L664
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L663
.L664:
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L665
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L663
.L665:
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	test	al, al
	je	.L241
.L663:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L666
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L667
.L666:
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L667:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L669
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L669
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L669
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L670
.L669:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L670
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L241
.L670:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L673
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L673
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L673
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L673
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L673
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L674
.L673:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L674
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L674
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L674
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L674
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L241
.L674:
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L676
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L676
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L676
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L676
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L676
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L676
	ucomiss	xmm0, xmm1
	je	.L677
.L676:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L677
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	jne	.L677
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L677
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L677
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L241
.L677:
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L679
	ucomiss	xmm0, xmm1
	jne	.L679
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	je	.L679
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	je	.L679
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L679
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L681
.L679:
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	jne	.L681
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L681
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L681
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L241
.L681:
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	test	al, al
	jne	.L682
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	test	al, al
	jne	.L682
	movss	xmm1, DWORD PTR t1_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L682
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L682
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L682
	movss	xmm0, DWORD PTR t1_x[rip]
	movss	xmm1, DWORD PTR _x_t1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L682
	ucomiss	xmm0, xmm1
	je	.L684
.L682:
	movzx	eax, BYTE PTR t1_l0[rip]
	test	al, al
	je	.L684
	movzx	eax, BYTE PTR t1_l1[rip]
	test	al, al
	je	.L684
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L684
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L684
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L241
.L684:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L686
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L687
.L686:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L688
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L687
.L688:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L689
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L687
.L689:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L241
.L687:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	jne	.L690
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L691
.L690:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L691
.L692:
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L693
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L691
.L693:
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	test	al, al
	je	.L241
.L691:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L694
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L695
.L694:
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L241
.L695:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L697
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L697
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR t0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_t0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L697
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L698
.L697:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L698
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L241
.L698:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L701
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L701
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L701
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L701
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L701
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L702
.L701:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L702
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L702
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L702
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L702
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L241
.L702:
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L704
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L704
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L704
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L704
	ucomiss	xmm0, xmm1
	je	.L705
.L704:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	jne	.L705
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L705
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L705
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L241
.L705:
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L707
	ucomiss	xmm0, xmm1
	jne	.L707
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	je	.L707
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	je	.L707
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L707
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L709
.L707:
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L709
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	jne	.L709
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L709
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L709
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L241
.L709:
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	test	al, al
	jne	.L710
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	test	al, al
	jne	.L710
	movss	xmm1, DWORD PTR t0_x[rip]
	movss	xmm0, DWORD PTR .LC1[rip]
	comiss	xmm0, xmm1
	jb	.L710
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L710
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L710
	movss	xmm0, DWORD PTR t0_x[rip]
	movss	xmm1, DWORD PTR _x_t0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L710
	ucomiss	xmm0, xmm1
	je	.L712
.L710:
	movzx	eax, BYTE PTR t0_l0[rip]
	test	al, al
	je	.L712
	movzx	eax, BYTE PTR t0_l1[rip]
	test	al, al
	je	.L712
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L712
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L712
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L241
.L712:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L714
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L715
.L714:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L716
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L715
.L716:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L717
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L715
.L717:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L241
.L715:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L718
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L718
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L719
.L718:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L720
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L720
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L719
.L720:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L721
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	je	.L721
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L719
.L721:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	jne	.L722
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	je	.L722
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L719
.L722:
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	test	al, al
	jne	.L241
.L719:
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 2
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 3
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 4
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 5
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 6
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 7
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 8
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 9
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 10
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 11
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 12
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 13
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 14
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 15
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 16
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 17
	je	.L723
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 18
	jne	.L241
.L723:
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L724
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L725
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L241
.L725:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L724
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L241
.L724:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L726
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L726
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR controller_z[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_controller_z[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L726
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L726
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	je	.L728
.L726:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L728
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L728
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L241
.L728:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L730
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L730
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L730
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L730
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L730
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	eax, 1
	jne	.L730
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L730
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L731
.L730:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L731
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L731
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L731
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L731
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L241
.L731:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L733
	ucomiss	xmm0, xmm1
	jne	.L733
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L735
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L736
.L735:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L733
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L736
.L733:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L736
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L736
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L736
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L736
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L241
.L736:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L737
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L737
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L737
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L738
.L737:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L739
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L739
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L739
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	je	.L738
.L739:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L738
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L738
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L740
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L740
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L738
.L740:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L738
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L738
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L241
.L738:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L741
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L741
	mov	edx, DWORD PTR controller_cnt[rip]
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	cmp	edx, eax
	jne	.L741
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	jp	.L741
	movss	xmm1, DWORD PTR .LC2[rip]
	ucomiss	xmm0, xmm1
	je	.L742
.L741:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L742
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L742
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L744
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L744
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L742
.L744:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L742
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L742
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L742
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L241
.L742:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L745
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L746
.L745:
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L746
.L747:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L746
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L746
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L746
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L746
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L241
.L746:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L748
	ucomiss	xmm0, xmm1
	jne	.L748
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L750
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L750
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L750
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L751
.L750:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L748
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L748
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L748
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, 1
	jne	.L748
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jg	.L751
.L748:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L751
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L751
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L752
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L752
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L751
.L752:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L751
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L751
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L751
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L241
.L751:
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L753
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L753
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L753
	mov	eax, DWORD PTR controller_cnt[rip]
	cmp	eax, 1
	jne	.L753
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	test	eax, eax
	jne	.L753
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L753
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L754
.L753:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L754
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L754
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L756
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L756
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L754
.L756:
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L754
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	jne	.L754
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L754
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	jne	.L241
.L754:
	movss	xmm0, DWORD PTR controller_z[rip]
	movss	xmm1, DWORD PTR _x_controller_z[rip]
	ucomiss	xmm0, xmm1
	jp	.L757
	ucomiss	xmm0, xmm1
	jne	.L757
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L759
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L760
.L759:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L757
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	je	.L760
.L757:
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L760
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	je	.L760
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L760
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L760
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L241
.L760:
	mov	eax, DWORD PTR controller_cnt[rip]
	mov	edx, DWORD PTR _x_controller_cnt[rip]
	sub	eax, edx
	cmp	eax, -1
	jne	.L761
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L761
	movss	xmm1, DWORD PTR controller_z[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L762
.L761:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L762
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L762
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L763
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L763
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L762
.L763:
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	test	al, al
	je	.L762
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	test	al, al
	jne	.L762
	movzx	eax, BYTE PTR controller_l0[rip]
	test	al, al
	je	.L762
	movzx	eax, BYTE PTR controller_l1[rip]
	test	al, al
	jne	.L241
.L762:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L764
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L765
.L764:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L766
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L765
.L766:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L767
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L765
.L767:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L241
.L765:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	jne	.L768
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L769
.L768:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L769
.L770:
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L771
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L769
.L771:
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	test	al, al
	je	.L241
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	test	al, al
	je	.L241
.L769:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L772
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L772
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L241
.L772:
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L773
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L773
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L241
.L773:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L774
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L774
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR gate_y[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_gate_y[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L774
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	je	.L775
.L774:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L777
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L241
.L777:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L241
.L775:
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L779
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L779
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L779
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L779
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L779
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L780
.L779:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L780
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L780
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L780
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L780
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L241
.L780:
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L782
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L782
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L782
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L782
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L782
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L782
	ucomiss	xmm0, xmm1
	je	.L784
.L782:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L784
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	jne	.L784
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L784
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L784
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L241
.L784:
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L786
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L786
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L788
.L786:
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L788
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	jne	.L788
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L788
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L788
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L241
.L788:
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR _x_gate_y[rip]
	ucomiss	xmm0, xmm1
	jp	.L789
	ucomiss	xmm0, xmm1
	jne	.L789
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	test	al, al
	jne	.L789
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	test	al, al
	jne	.L789
	movss	xmm0, DWORD PTR gate_y[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jb	.L789
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L789
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L789
	movss	xmm1, DWORD PTR gate_y[rip]
	movss	xmm0, DWORD PTR .LC3[rip]
	comiss	xmm0, xmm1
	jnb	.L792
.L789:
	movzx	eax, BYTE PTR gate_l0[rip]
	test	al, al
	je	.L792
	movzx	eax, BYTE PTR gate_l1[rip]
	test	al, al
	je	.L792
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L792
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L792
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L241
.L792:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L241
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L794
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L795
.L794:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L795
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L795
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	jne	.L241
.L795:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L796
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L797
.L796:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L797
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L797
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L241
.L797:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L798
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L799
.L798:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L799
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L799
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	jne	.L241
.L799:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L800
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L801
.L800:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L801
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L801
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	jne	.L241
.L801:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L802
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L803
.L802:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L803
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L803
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	jne	.L241
.L803:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L804
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L805
.L804:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L805
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L805
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	jne	.L241
.L805:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L806
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L807
.L806:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L807
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L807
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	jne	.L241
.L807:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L808
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L809
.L808:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L809
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L809
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	jne	.L241
.L809:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L810
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L811
.L810:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L811
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L811
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	jne	.L241
.L811:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L812
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L813
.L812:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L813
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L813
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	jne	.L241
.L813:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L814
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L815
.L814:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L815
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L815
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	jne	.L241
.L815:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L816
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L817
.L816:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L817
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L817
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	jne	.L241
.L817:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L818
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L819
.L818:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L819
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L819
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	jne	.L241
.L819:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L820
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L821
.L820:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L821
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L821
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	jne	.L241
.L821:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L822
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L823
.L822:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L823
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L823
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	jne	.L241
.L823:
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L824
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L825
.L824:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L825
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L825
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	jne	.L241
.L825:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	jne	.L826
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L827
.L826:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L827
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L827
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	jne	.L241
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	jne	.L241
.L827:
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	je	.L828
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	jne	.L828
	mov	eax, 1
	jmp	.L829
.L828:
	mov	eax, 0
.L829:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L830
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L830
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L830
	mov	eax, 1
	jmp	.L831
.L830:
	mov	eax, 0
.L831:
	and	eax, 1
	xor	eax, edx
	test	al, al
	jne	.L832
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L832
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L241
.L832:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L834
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L834
	movzx	eax, BYTE PTR gate_evt1[rip]
	test	al, al
	je	.L835
	movzx	eax, BYTE PTR gate_evt0[rip]
	test	al, al
	jne	.L835
	mov	eax, 1
	jmp	.L836
.L835:
	mov	eax, 0
.L836:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	je	.L837
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L837
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L837
	mov	eax, 1
	jmp	.L838
.L837:
	mov	eax, 0
.L838:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L241
.L834:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L839
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L839
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L840
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	je	.L840
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	jne	.L840
	mov	eax, 1
	jmp	.L841
.L840:
	mov	eax, 0
.L841:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L842
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L843
.L842:
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L844
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L843
.L844:
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L845
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L843
.L845:
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L846
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L843
.L846:
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L847
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L843
.L847:
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L848
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L843
.L848:
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L849
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L843
.L849:
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L850
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L843
.L850:
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L851
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L843
.L851:
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L852
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L843
.L852:
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L853
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L843
.L853:
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L854
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L843
.L854:
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L855
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L843
.L855:
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L856
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L843
.L856:
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L857
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L843
.L857:
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L858
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L843
.L858:
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	je	.L859
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	jne	.L859
.L843:
	mov	eax, 1
	jmp	.L860
.L859:
	mov	eax, 0
.L860:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L241
.L839:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L861
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L861
	movzx	eax, BYTE PTR controller_evt2[rip]
	test	al, al
	jne	.L862
	movzx	eax, BYTE PTR controller_evt1[rip]
	test	al, al
	je	.L862
	movzx	eax, BYTE PTR controller_evt0[rip]
	test	al, al
	jne	.L862
	mov	eax, 1
	jmp	.L863
.L862:
	mov	eax, 0
.L863:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR t16_evt1[rip]
	test	al, al
	je	.L864
	movzx	eax, BYTE PTR t16_evt0[rip]
	test	al, al
	je	.L865
.L864:
	movzx	eax, BYTE PTR t15_evt1[rip]
	test	al, al
	je	.L866
	movzx	eax, BYTE PTR t15_evt0[rip]
	test	al, al
	je	.L865
.L866:
	movzx	eax, BYTE PTR t14_evt1[rip]
	test	al, al
	je	.L867
	movzx	eax, BYTE PTR t14_evt0[rip]
	test	al, al
	je	.L865
.L867:
	movzx	eax, BYTE PTR t13_evt1[rip]
	test	al, al
	je	.L868
	movzx	eax, BYTE PTR t13_evt0[rip]
	test	al, al
	je	.L865
.L868:
	movzx	eax, BYTE PTR t12_evt1[rip]
	test	al, al
	je	.L869
	movzx	eax, BYTE PTR t12_evt0[rip]
	test	al, al
	je	.L865
.L869:
	movzx	eax, BYTE PTR t11_evt1[rip]
	test	al, al
	je	.L870
	movzx	eax, BYTE PTR t11_evt0[rip]
	test	al, al
	je	.L865
.L870:
	movzx	eax, BYTE PTR t10_evt1[rip]
	test	al, al
	je	.L871
	movzx	eax, BYTE PTR t10_evt0[rip]
	test	al, al
	je	.L865
.L871:
	movzx	eax, BYTE PTR t9_evt1[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR t9_evt0[rip]
	test	al, al
	je	.L865
.L872:
	movzx	eax, BYTE PTR t8_evt1[rip]
	test	al, al
	je	.L873
	movzx	eax, BYTE PTR t8_evt0[rip]
	test	al, al
	je	.L865
.L873:
	movzx	eax, BYTE PTR t7_evt1[rip]
	test	al, al
	je	.L874
	movzx	eax, BYTE PTR t7_evt0[rip]
	test	al, al
	je	.L865
.L874:
	movzx	eax, BYTE PTR t6_evt1[rip]
	test	al, al
	je	.L875
	movzx	eax, BYTE PTR t6_evt0[rip]
	test	al, al
	je	.L865
.L875:
	movzx	eax, BYTE PTR t5_evt1[rip]
	test	al, al
	je	.L876
	movzx	eax, BYTE PTR t5_evt0[rip]
	test	al, al
	je	.L865
.L876:
	movzx	eax, BYTE PTR t4_evt1[rip]
	test	al, al
	je	.L877
	movzx	eax, BYTE PTR t4_evt0[rip]
	test	al, al
	je	.L865
.L877:
	movzx	eax, BYTE PTR t3_evt1[rip]
	test	al, al
	je	.L878
	movzx	eax, BYTE PTR t3_evt0[rip]
	test	al, al
	je	.L865
.L878:
	movzx	eax, BYTE PTR t2_evt1[rip]
	test	al, al
	je	.L879
	movzx	eax, BYTE PTR t2_evt0[rip]
	test	al, al
	je	.L865
.L879:
	movzx	eax, BYTE PTR t0_evt1[rip]
	test	al, al
	je	.L880
	movzx	eax, BYTE PTR t0_evt0[rip]
	test	al, al
	je	.L865
.L880:
	movzx	eax, BYTE PTR t1_evt1[rip]
	test	al, al
	je	.L881
	movzx	eax, BYTE PTR t1_evt0[rip]
	test	al, al
	jne	.L881
.L865:
	mov	eax, 1
	jmp	.L882
.L881:
	mov	eax, 0
.L882:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L241
.L861:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L972
	ucomiss	xmm0, xmm1
	je	.L883
.L972:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L241
.L883:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L885
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L241
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L241
.L885:
	mov	eax, 1
	jmp	.L887
.L241:
	mov	eax, 0
.L887:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_t16_l1[rip]
	mov	BYTE PTR t16_l1[rip], al
	movzx	eax, BYTE PTR _x_t16_l0[rip]
	mov	BYTE PTR t16_l0[rip], al
	movzx	eax, BYTE PTR _x_t16_evt1[rip]
	mov	BYTE PTR t16_evt1[rip], al
	movzx	eax, BYTE PTR _x_t16_evt0[rip]
	mov	BYTE PTR t16_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t16_x[rip]
	movss	DWORD PTR t16_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t15_l1[rip]
	mov	BYTE PTR t15_l1[rip], al
	movzx	eax, BYTE PTR _x_t15_l0[rip]
	mov	BYTE PTR t15_l0[rip], al
	movzx	eax, BYTE PTR _x_t15_evt1[rip]
	mov	BYTE PTR t15_evt1[rip], al
	movzx	eax, BYTE PTR _x_t15_evt0[rip]
	mov	BYTE PTR t15_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t15_x[rip]
	movss	DWORD PTR t15_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t14_l1[rip]
	mov	BYTE PTR t14_l1[rip], al
	movzx	eax, BYTE PTR _x_t14_l0[rip]
	mov	BYTE PTR t14_l0[rip], al
	movzx	eax, BYTE PTR _x_t14_evt1[rip]
	mov	BYTE PTR t14_evt1[rip], al
	movzx	eax, BYTE PTR _x_t14_evt0[rip]
	mov	BYTE PTR t14_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t14_x[rip]
	movss	DWORD PTR t14_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t13_l1[rip]
	mov	BYTE PTR t13_l1[rip], al
	movzx	eax, BYTE PTR _x_t13_l0[rip]
	mov	BYTE PTR t13_l0[rip], al
	movzx	eax, BYTE PTR _x_t13_evt1[rip]
	mov	BYTE PTR t13_evt1[rip], al
	movzx	eax, BYTE PTR _x_t13_evt0[rip]
	mov	BYTE PTR t13_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t13_x[rip]
	movss	DWORD PTR t13_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t12_l1[rip]
	mov	BYTE PTR t12_l1[rip], al
	movzx	eax, BYTE PTR _x_t12_l0[rip]
	mov	BYTE PTR t12_l0[rip], al
	movzx	eax, BYTE PTR _x_t12_evt0[rip]
	mov	BYTE PTR t12_evt0[rip], al
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movss	xmm0, DWORD PTR _x_t12_x[rip]
	movss	DWORD PTR t12_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t10_l1[rip]
	mov	BYTE PTR t10_l1[rip], al
	movzx	eax, BYTE PTR _x_t10_l0[rip]
	mov	BYTE PTR t10_l0[rip], al
	movzx	eax, BYTE PTR _x_t10_evt1[rip]
	mov	BYTE PTR t10_evt1[rip], al
	movzx	eax, BYTE PTR _x_t10_evt0[rip]
	mov	BYTE PTR t10_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t10_x[rip]
	movss	DWORD PTR t10_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t9_l1[rip]
	mov	BYTE PTR t9_l1[rip], al
	movzx	eax, BYTE PTR _x_t9_l0[rip]
	mov	BYTE PTR t9_l0[rip], al
	movzx	eax, BYTE PTR _x_t9_evt1[rip]
	mov	BYTE PTR t9_evt1[rip], al
	movzx	eax, BYTE PTR _x_t9_evt0[rip]
	mov	BYTE PTR t9_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t3_x[rip]
	movss	DWORD PTR t3_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t2_evt1[rip]
	mov	BYTE PTR t2_evt1[rip], al
	movzx	eax, BYTE PTR _x_t11_evt0[rip]
	mov	BYTE PTR t11_evt0[rip], al
	movzx	eax, BYTE PTR _x_gate_evt0[rip]
	mov	BYTE PTR gate_evt0[rip], al
	movzx	eax, BYTE PTR _x_t2_l1[rip]
	mov	BYTE PTR t2_l1[rip], al
	movzx	eax, BYTE PTR _x_t11_l0[rip]
	mov	BYTE PTR t11_l0[rip], al
	movzx	eax, BYTE PTR _x_gate_l0[rip]
	mov	BYTE PTR gate_l0[rip], al
	movzx	eax, BYTE PTR _x_t3_evt0[rip]
	mov	BYTE PTR t3_evt0[rip], al
	movzx	eax, BYTE PTR _x_t2_l0[rip]
	mov	BYTE PTR t2_l0[rip], al
	movss	xmm0, DWORD PTR _x_t2_x[rip]
	movss	DWORD PTR t2_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t1_evt1[rip]
	mov	BYTE PTR t1_evt1[rip], al
	movzx	eax, BYTE PTR _x_t1_l1[rip]
	mov	BYTE PTR t1_l1[rip], al
	movzx	eax, BYTE PTR _x_t2_evt0[rip]
	mov	BYTE PTR t2_evt0[rip], al
	movzx	eax, BYTE PTR _x_t0_l1[rip]
	mov	BYTE PTR t0_l1[rip], al
	movzx	eax, BYTE PTR _x_t0_evt1[rip]
	mov	BYTE PTR t0_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t0_x[rip]
	movss	DWORD PTR t0_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t12_evt1[rip]
	mov	BYTE PTR t12_evt1[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_t11_l1[rip]
	mov	BYTE PTR t11_l1[rip], al
	movzx	eax, BYTE PTR _x_gate_l1[rip]
	mov	BYTE PTR gate_l1[rip], al
	movzx	eax, BYTE PTR _x_t3_evt1[rip]
	mov	BYTE PTR t3_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t4_x[rip]
	movss	DWORD PTR t4_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t0_l0[rip]
	mov	BYTE PTR t0_l0[rip], al
	movss	xmm0, DWORD PTR _x_t11_x[rip]
	movss	DWORD PTR t11_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_gate_y[rip]
	movss	DWORD PTR gate_y[rip], xmm0
	movzx	eax, BYTE PTR _x_t8_l0[rip]
	mov	BYTE PTR t8_l0[rip], al
	movzx	eax, BYTE PTR _x_t1_evt0[rip]
	mov	BYTE PTR t1_evt0[rip], al
	movzx	eax, BYTE PTR _x_controller_l1[rip]
	mov	BYTE PTR controller_l1[rip], al
	movzx	eax, BYTE PTR _x_t6_l0[rip]
	mov	BYTE PTR t6_l0[rip], al
	movzx	eax, BYTE PTR _x_t5_l0[rip]
	mov	BYTE PTR t5_l0[rip], al
	movzx	eax, BYTE PTR _x_t0_evt0[rip]
	mov	BYTE PTR t0_evt0[rip], al
	movss	xmm0, DWORD PTR _x_t1_x[rip]
	movss	DWORD PTR t1_x[rip], xmm0
	movzx	eax, BYTE PTR _x_controller_evt1[rip]
	mov	BYTE PTR controller_evt1[rip], al
	movzx	eax, BYTE PTR _x_t5_l1[rip]
	mov	BYTE PTR t5_l1[rip], al
	movzx	eax, BYTE PTR _x_t6_evt0[rip]
	mov	BYTE PTR t6_evt0[rip], al
	movzx	eax, BYTE PTR _x_t11_evt1[rip]
	mov	BYTE PTR t11_evt1[rip], al
	movzx	eax, BYTE PTR _x_gate_evt1[rip]
	mov	BYTE PTR gate_evt1[rip], al
	movzx	eax, BYTE PTR _x_t3_l1[rip]
	mov	BYTE PTR t3_l1[rip], al
	movzx	eax, BYTE PTR _x_t4_evt0[rip]
	mov	BYTE PTR t4_evt0[rip], al
	movzx	eax, BYTE PTR _x_controller_evt2[rip]
	mov	BYTE PTR controller_evt2[rip], al
	movzx	eax, BYTE PTR _x_controller_evt0[rip]
	mov	BYTE PTR controller_evt0[rip], al
	movzx	eax, BYTE PTR _x_t6_evt1[rip]
	mov	BYTE PTR t6_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t7_x[rip]
	movss	DWORD PTR t7_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t1_l0[rip]
	mov	BYTE PTR t1_l0[rip], al
	mov	eax, DWORD PTR _x_controller_cnt[rip]
	mov	DWORD PTR controller_cnt[rip], eax
	movzx	eax, BYTE PTR _x_t4_evt1[rip]
	mov	BYTE PTR t4_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t5_x[rip]
	movss	DWORD PTR t5_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t3_l0[rip]
	mov	BYTE PTR t3_l0[rip], al
	movzx	eax, BYTE PTR _x_t4_l0[rip]
	mov	BYTE PTR t4_l0[rip], al
	movss	xmm0, DWORD PTR _x_controller_z[rip]
	movss	DWORD PTR controller_z[rip], xmm0
	movzx	eax, BYTE PTR _x_t4_l1[rip]
	mov	BYTE PTR t4_l1[rip], al
	movzx	eax, BYTE PTR _x_t5_evt0[rip]
	mov	BYTE PTR t5_evt0[rip], al
	movzx	eax, BYTE PTR _x_t5_evt1[rip]
	mov	BYTE PTR t5_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t6_x[rip]
	movss	DWORD PTR t6_x[rip], xmm0
	movzx	eax, BYTE PTR _x_controller_l0[rip]
	mov	BYTE PTR controller_l0[rip], al
	movzx	eax, BYTE PTR _x_t6_l1[rip]
	mov	BYTE PTR t6_l1[rip], al
	movzx	eax, BYTE PTR _x_t7_evt0[rip]
	mov	BYTE PTR t7_evt0[rip], al
	movzx	eax, BYTE PTR _x_t7_evt1[rip]
	mov	BYTE PTR t7_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t8_x[rip]
	movss	DWORD PTR t8_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t7_l0[rip]
	mov	BYTE PTR t7_l0[rip], al
	movzx	eax, BYTE PTR _x_t7_l1[rip]
	mov	BYTE PTR t7_l1[rip], al
	movzx	eax, BYTE PTR _x_t8_evt0[rip]
	mov	BYTE PTR t8_evt0[rip], al
	movzx	eax, BYTE PTR _x_t8_evt1[rip]
	mov	BYTE PTR t8_evt1[rip], al
	movss	xmm0, DWORD PTR _x_t9_x[rip]
	movss	DWORD PTR t9_x[rip], xmm0
	movzx	eax, BYTE PTR _x_t8_l1[rip]
	mov	BYTE PTR t8_l1[rip], al
.L236:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L888
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1084227584
	.align 4
.LC2:
	.long	1065353216
	.align 4
.LC3:
	.long	1073741824
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"496924.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	t16_l1,1,1
	.comm	_x_t16_l1,1,1
	.comm	t16_l0,1,1
	.comm	_x_t16_l0,1,1
	.comm	t16_evt1,1,1
	.comm	_x_t16_evt1,1,1
	.comm	t16_evt0,1,1
	.comm	_x_t16_evt0,1,1
	.comm	t16_x,4,4
	.comm	_x_t16_x,4,4
	.comm	t15_l1,1,1
	.comm	_x_t15_l1,1,1
	.comm	t15_l0,1,1
	.comm	_x_t15_l0,1,1
	.comm	t15_evt1,1,1
	.comm	_x_t15_evt1,1,1
	.comm	t15_evt0,1,1
	.comm	_x_t15_evt0,1,1
	.comm	t15_x,4,4
	.comm	_x_t15_x,4,4
	.comm	t14_l1,1,1
	.comm	_x_t14_l1,1,1
	.comm	t14_l0,1,1
	.comm	_x_t14_l0,1,1
	.comm	t14_evt1,1,1
	.comm	_x_t14_evt1,1,1
	.comm	t14_evt0,1,1
	.comm	_x_t14_evt0,1,1
	.comm	t14_x,4,4
	.comm	_x_t14_x,4,4
	.comm	t13_l1,1,1
	.comm	_x_t13_l1,1,1
	.comm	t13_l0,1,1
	.comm	_x_t13_l0,1,1
	.comm	t13_evt1,1,1
	.comm	_x_t13_evt1,1,1
	.comm	t13_evt0,1,1
	.comm	_x_t13_evt0,1,1
	.comm	t13_x,4,4
	.comm	_x_t13_x,4,4
	.comm	t12_l1,1,1
	.comm	_x_t12_l1,1,1
	.comm	t12_l0,1,1
	.comm	_x_t12_l0,1,1
	.comm	t12_evt0,1,1
	.comm	_x_t12_evt0,1,1
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	t12_x,4,4
	.comm	_x_t12_x,4,4
	.comm	t10_l1,1,1
	.comm	_x_t10_l1,1,1
	.comm	t10_l0,1,1
	.comm	_x_t10_l0,1,1
	.comm	t10_evt1,1,1
	.comm	_x_t10_evt1,1,1
	.comm	t10_evt0,1,1
	.comm	_x_t10_evt0,1,1
	.comm	t10_x,4,4
	.comm	_x_t10_x,4,4
	.comm	t9_l1,1,1
	.comm	_x_t9_l1,1,1
	.comm	t9_l0,1,1
	.comm	_x_t9_l0,1,1
	.comm	t9_evt1,1,1
	.comm	_x_t9_evt1,1,1
	.comm	t9_evt0,1,1
	.comm	_x_t9_evt0,1,1
	.comm	t3_x,4,4
	.comm	_x_t3_x,4,4
	.comm	t2_evt1,1,1
	.comm	_x_t2_evt1,1,1
	.comm	t11_evt0,1,1
	.comm	_x_t11_evt0,1,1
	.comm	gate_evt0,1,1
	.comm	_x_gate_evt0,1,1
	.comm	t2_l1,1,1
	.comm	_x_t2_l1,1,1
	.comm	t11_l0,1,1
	.comm	_x_t11_l0,1,1
	.comm	gate_l0,1,1
	.comm	_x_gate_l0,1,1
	.comm	t3_evt0,1,1
	.comm	_x_t3_evt0,1,1
	.comm	t2_l0,1,1
	.comm	_x_t2_l0,1,1
	.comm	t2_x,4,4
	.comm	_x_t2_x,4,4
	.comm	t1_evt1,1,1
	.comm	_x_t1_evt1,1,1
	.comm	t1_l1,1,1
	.comm	_x_t1_l1,1,1
	.comm	t2_evt0,1,1
	.comm	_x_t2_evt0,1,1
	.comm	t0_l1,1,1
	.comm	_x_t0_l1,1,1
	.comm	t0_evt1,1,1
	.comm	_x_t0_evt1,1,1
	.comm	t0_x,4,4
	.comm	_x_t0_x,4,4
	.comm	t12_evt1,1,1
	.comm	_x_t12_evt1,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	t11_l1,1,1
	.comm	_x_t11_l1,1,1
	.comm	gate_l1,1,1
	.comm	_x_gate_l1,1,1
	.comm	t3_evt1,1,1
	.comm	_x_t3_evt1,1,1
	.comm	t4_x,4,4
	.comm	_x_t4_x,4,4
	.comm	t0_l0,1,1
	.comm	_x_t0_l0,1,1
	.comm	t11_x,4,4
	.comm	_x_t11_x,4,4
	.comm	gate_y,4,4
	.comm	_x_gate_y,4,4
	.comm	t8_l0,1,1
	.comm	_x_t8_l0,1,1
	.comm	t1_evt0,1,1
	.comm	_x_t1_evt0,1,1
	.comm	controller_l1,1,1
	.comm	_x_controller_l1,1,1
	.comm	t6_l0,1,1
	.comm	_x_t6_l0,1,1
	.comm	t5_l0,1,1
	.comm	_x_t5_l0,1,1
	.comm	t0_evt0,1,1
	.comm	_x_t0_evt0,1,1
	.comm	t1_x,4,4
	.comm	_x_t1_x,4,4
	.comm	controller_evt1,1,1
	.comm	_x_controller_evt1,1,1
	.comm	t5_l1,1,1
	.comm	_x_t5_l1,1,1
	.comm	t6_evt0,1,1
	.comm	_x_t6_evt0,1,1
	.comm	t11_evt1,1,1
	.comm	_x_t11_evt1,1,1
	.comm	gate_evt1,1,1
	.comm	_x_gate_evt1,1,1
	.comm	t3_l1,1,1
	.comm	_x_t3_l1,1,1
	.comm	t4_evt0,1,1
	.comm	_x_t4_evt0,1,1
	.comm	controller_evt2,1,1
	.comm	_x_controller_evt2,1,1
	.comm	controller_evt0,1,1
	.comm	_x_controller_evt0,1,1
	.comm	t6_evt1,1,1
	.comm	_x_t6_evt1,1,1
	.comm	t7_x,4,4
	.comm	_x_t7_x,4,4
	.comm	t1_l0,1,1
	.comm	_x_t1_l0,1,1
	.comm	controller_cnt,4,4
	.comm	_x_controller_cnt,4,4
	.comm	t4_evt1,1,1
	.comm	_x_t4_evt1,1,1
	.comm	t5_x,4,4
	.comm	_x_t5_x,4,4
	.comm	t3_l0,1,1
	.comm	_x_t3_l0,1,1
	.comm	t4_l0,1,1
	.comm	_x_t4_l0,1,1
	.comm	controller_z,4,4
	.comm	_x_controller_z,4,4
	.comm	t4_l1,1,1
	.comm	_x_t4_l1,1,1
	.comm	t5_evt0,1,1
	.comm	_x_t5_evt0,1,1
	.comm	t5_evt1,1,1
	.comm	_x_t5_evt1,1,1
	.comm	t6_x,4,4
	.comm	_x_t6_x,4,4
	.comm	controller_l0,1,1
	.comm	_x_controller_l0,1,1
	.comm	t6_l1,1,1
	.comm	_x_t6_l1,1,1
	.comm	t7_evt0,1,1
	.comm	_x_t7_evt0,1,1
	.comm	t7_evt1,1,1
	.comm	_x_t7_evt1,1,1
	.comm	t8_x,4,4
	.comm	_x_t8_x,4,4
	.comm	t7_l0,1,1
	.comm	_x_t7_l0,1,1
	.comm	t7_l1,1,1
	.comm	_x_t7_l1,1,1
	.comm	t8_evt0,1,1
	.comm	_x_t8_evt0,1,1
	.comm	t8_evt1,1,1
	.comm	_x_t8_evt1,1,1
	.comm	t9_x,4,4
	.comm	_x_t9_x,4,4
	.comm	t8_l1,1,1
	.comm	_x_t8_l1,1,1
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+16
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+40
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+44
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+56
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+64
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+68
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+76
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+88
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+92
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+96
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+200
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+204
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+340
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+356
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+324
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+360
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+368
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+376
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+388
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+116
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+328
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+320
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+396
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+180
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+124
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+364
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+292
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+380
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+168
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+336
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L915+152
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+308
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+300
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+332
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+156
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+288
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+280
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+240
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+228
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L915+220
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L915+236
	strb	r2, [r3]
	ldr	r3, .L915+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L915
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L915+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L915
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L915
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L915+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L915+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L7:
	ldr	r3, .L915+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L915+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L10:
	ldr	r3, .L915+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L915+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L12:
	ldr	r3, .L915+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L915+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L11
.L13:
	ldr	r3, .L915+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L11:
	ldr	r3, .L915+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L14
	ldr	r3, .L915
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
.L14:
	ldr	r3, .L915+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L15:
	ldr	r3, .L915+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L915+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L18:
	ldr	r3, .L915+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L915+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L20:
	ldr	r3, .L915+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L915+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L21:
	ldr	r3, .L915+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L19:
	ldr	r3, .L915+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L915+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L22:
	ldr	r3, .L915+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L915+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L24:
	ldr	r3, .L915+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L915+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
.L25:
	ldr	r3, .L915+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L23:
	ldr	r3, .L915+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L26
	ldr	r3, .L915+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L27
.L26:
	ldr	r3, .L915+36
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L27:
	ldr	r3, .L915+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+56
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L915+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L30:
	ldr	r3, .L915+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L915+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L32:
	ldr	r3, .L915+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L915+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L33:
	ldr	r3, .L915+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L31:
	ldr	r3, .L915+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L915+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L34:
	ldr	r3, .L915+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L915+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L36:
	ldr	r3, .L915+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L915+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L35
.L37:
	ldr	r3, .L915+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L35:
	ldr	r3, .L915+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L38
	ldr	r3, .L915+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
.L38:
	ldr	r3, .L915+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L39:
	ldr	r3, .L915+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L42
	ldr	r3, .L915+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L42:
	ldr	r3, .L915+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L915+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L44:
	ldr	r3, .L915+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L915+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
.L45:
	ldr	r3, .L915+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L43:
	ldr	r3, .L915+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L46
	ldr	r3, .L915+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L46:
	ldr	r3, .L915+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L915+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L48:
	ldr	r3, .L915+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L915+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L49:
	ldr	r3, .L915+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L47:
	ldr	r3, .L915+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L50
	ldr	r3, .L915+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L51
.L50:
	ldr	r3, .L915+76
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L51:
	ldr	r3, .L915+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+96
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L54
	ldr	r3, .L915+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L54:
	ldr	r3, .L915+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L915+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L56:
	ldr	r3, .L915+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L57
	ldr	r3, .L915+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
.L57:
	ldr	r3, .L915+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L55:
	ldr	r3, .L915+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L915+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L58:
	ldr	r3, .L915+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L915+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L60:
	ldr	r3, .L915+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L915+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L61:
	ldr	r3, .L915+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L59:
	ldr	r3, .L915+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L915+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L62:
	ldr	r3, .L915+96
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L63:
	ldr	r3, .L915+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+180
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L66
	ldr	r3, .L915+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L66:
	ldr	r3, .L915+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L915+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L68:
	ldr	r3, .L915+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L915+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L67
.L69:
	ldr	r3, .L915+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L67:
	ldr	r3, .L915+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L70
	ldr	r3, .L915+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L70:
	ldr	r3, .L915+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L915+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
.L72:
	ldr	r3, .L915+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L73
	ldr	r3, .L915+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
	b	.L916
.L917:
	.align	2
.L915:
	.word	t16_l1
	.word	t16_l0
	.word	t16_evt1
	.word	t16_evt0
	.word	t16_x
	.word	t15_l1
	.word	t15_l0
	.word	t15_evt1
	.word	t15_evt0
	.word	t15_x
	.word	t14_l1
	.word	t14_l0
	.word	t14_evt1
	.word	t14_evt0
	.word	t14_x
	.word	t13_l1
	.word	t13_l0
	.word	t13_evt1
	.word	t13_evt0
	.word	t13_x
	.word	t12_l1
	.word	t12_l0
	.word	t12_evt0
	.word	_diverge_delta
	.word	t12_x
	.word	gate_evt0
	.word	gate_l0
	.word	t0_evt1
	.word	t12_evt1
	.word	delta
	.word	gate_l1
	.word	gate_y
	.word	controller_l1
	.word	t0_evt0
	.word	controller_evt1
	.word	gate_evt1
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_cnt
	.word	controller_z
	.word	controller_l0
	.word	t11_evt0
	.word	t11_evt1
	.word	t11_l0
	.word	t11_l1
	.word	t11_x
	.word	t10_evt0
	.word	t10_evt1
	.word	t10_l0
	.word	t10_l1
	.word	t10_x
	.word	t9_evt0
	.word	t9_evt1
	.word	t9_l0
	.word	t9_l1
	.word	t9_x
	.word	t8_evt0
	.word	t8_evt1
	.word	t8_l0
	.word	t8_l1
	.word	t8_x
	.word	t7_evt0
	.word	t7_evt1
	.word	t7_l0
	.word	t7_l1
	.word	t7_x
	.word	t6_evt0
	.word	t6_evt1
	.word	t6_l0
	.word	t6_l1
	.word	t6_x
	.word	t5_evt0
	.word	t5_evt1
	.word	t5_l0
	.word	t5_l1
	.word	t5_x
	.word	t4_evt0
	.word	t4_evt1
	.word	t4_l0
	.word	t4_l1
	.word	t4_x
	.word	t3_evt0
	.word	t3_evt1
	.word	t3_l0
	.word	t3_l1
	.word	t3_x
	.word	t2_evt0
	.word	t2_evt1
	.word	t2_l0
	.word	t2_l1
	.word	t2_x
	.word	t1_evt0
	.word	t1_evt1
	.word	t1_l0
	.word	t1_l1
	.word	t1_x
	.word	1084227584
	.word	t0_x
	.word	t0_l1
	.word	t0_l0
.L916:
.L73:
	ldr	r3, .L915+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L71:
	ldr	r3, .L915+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L74
	ldr	r3, .L915+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
.L74:
	ldr	r3, .L915+180
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L75:
	ldr	r3, .L915+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
	ldr	r3, .L915+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L78:
	ldr	r3, .L915+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L915+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L80:
	ldr	r3, .L915+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L915+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
.L81:
	ldr	r3, .L915+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L79:
	ldr	r3, .L915+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L915+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L82:
	ldr	r3, .L915+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L915+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L84:
	ldr	r3, .L915+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L915+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
.L85:
	ldr	r3, .L915+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L83:
	ldr	r3, .L915+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L86
	ldr	r3, .L915+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
.L86:
	ldr	r3, .L915+200
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L87:
	ldr	r3, .L915+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L90
	ldr	r3, .L915+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L90:
	ldr	r3, .L915+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L915+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L92:
	ldr	r3, .L915+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
	ldr	r3, .L915+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L91
.L93:
	ldr	r3, .L915+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L91:
	ldr	r3, .L915+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L915+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L94:
	ldr	r3, .L915+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L915+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L96:
	ldr	r3, .L915+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L915+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
.L97:
	ldr	r3, .L915+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L95:
	ldr	r3, .L915+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L915+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
.L98:
	ldr	r3, .L915+220
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L99:
	ldr	r3, .L915+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+240
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L102
	ldr	r3, .L915+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L102:
	ldr	r3, .L915+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L915+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L104:
	ldr	r3, .L915+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L915+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
.L105:
	ldr	r3, .L915+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L103:
	ldr	r3, .L915+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L915+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L106:
	ldr	r3, .L915+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L915+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L108:
	ldr	r3, .L915+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L915+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
.L109:
	ldr	r3, .L915+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L107:
	ldr	r3, .L915+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L110
	ldr	r3, .L915+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
.L110:
	ldr	r3, .L915+240
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L111:
	ldr	r3, .L915+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L915+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L114:
	ldr	r3, .L915+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L915+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L116:
	ldr	r3, .L915+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L117
	ldr	r3, .L915+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L117:
	ldr	r3, .L915+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L115:
	ldr	r3, .L915+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L118
	ldr	r3, .L915+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L118:
	ldr	r3, .L915+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L915+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L120:
	ldr	r3, .L915+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L121
	ldr	r3, .L915+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
.L121:
	ldr	r3, .L915+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L119:
	ldr	r3, .L915+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L122
	ldr	r3, .L915+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L123
.L122:
	ldr	r3, .L915+260
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L123:
	ldr	r3, .L915+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+280
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L126
	ldr	r3, .L915+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L126:
	ldr	r3, .L915+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L915+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L128:
	ldr	r3, .L915+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L129
	ldr	r3, .L915+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
.L129:
	ldr	r3, .L915+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L127:
	ldr	r3, .L915+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L915+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L130:
	ldr	r3, .L915+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L915+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L132:
	ldr	r3, .L915+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L133
	ldr	r3, .L915+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
.L133:
	ldr	r3, .L915+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L131:
	ldr	r3, .L915+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L915+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
.L134:
	ldr	r3, .L915+280
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L135:
	ldr	r3, .L915+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+300
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L915+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L138:
	ldr	r3, .L915+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L915+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L140:
	ldr	r3, .L915+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L141
	ldr	r3, .L915+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
.L141:
	ldr	r3, .L915+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L139:
	ldr	r3, .L915+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L915+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L142:
	ldr	r3, .L915+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L915+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L144:
	ldr	r3, .L915+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L145
	ldr	r3, .L915+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L145:
	ldr	r3, .L915+284
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+288
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L143:
	ldr	r3, .L915+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L915+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
.L146:
	ldr	r3, .L915+300
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L147:
	ldr	r3, .L915+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+320
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L150
	ldr	r3, .L915+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L150:
	ldr	r3, .L915+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L915+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L152:
	ldr	r3, .L915+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L153
	ldr	r3, .L915+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
.L153:
	ldr	r3, .L915+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L151:
	ldr	r3, .L915+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L915+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L154:
	ldr	r3, .L915+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L915+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L156:
	ldr	r3, .L915+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L915+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
.L157:
	ldr	r3, .L915+304
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+308
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L155:
	ldr	r3, .L915+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
	ldr	r3, .L915+316
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
.L158:
	ldr	r3, .L915+320
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L159:
	ldr	r3, .L915+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+340
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L915+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L162:
	ldr	r3, .L915+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L915+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L164:
	ldr	r3, .L915+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
	ldr	r3, .L915+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
.L165:
	ldr	r3, .L915+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L163:
	ldr	r3, .L915+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L166
	ldr	r3, .L915+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L166:
	ldr	r3, .L915+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L915+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L168:
	ldr	r3, .L915+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L915+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
.L169:
	ldr	r3, .L915+324
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+328
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L167:
	ldr	r3, .L915+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L170
	ldr	r3, .L915+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L171
.L170:
	ldr	r3, .L915+340
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L171:
	ldr	r3, .L915+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+360
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L174
	ldr	r3, .L915+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L174:
	ldr	r3, .L915+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L915+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L176:
	ldr	r3, .L915+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L177
	ldr	r3, .L915+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
.L177:
	ldr	r3, .L915+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L175:
	ldr	r3, .L915+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
	ldr	r3, .L915+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L178:
	ldr	r3, .L915+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L915+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L180:
	ldr	r3, .L915+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L915+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L179
.L181:
	ldr	r3, .L915+344
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+348
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L179:
	ldr	r3, .L915+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L915+356
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
.L182:
	ldr	r3, .L915+360
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L183:
	ldr	r3, .L915+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+380
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L186
	ldr	r3, .L915+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
.L186:
	ldr	r3, .L915+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L915+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
.L188:
	ldr	r3, .L915+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L915+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
.L189:
	ldr	r3, .L915+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L187:
	ldr	r3, .L915+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L190
	ldr	r3, .L915+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L190:
	ldr	r3, .L915+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L915+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L192:
	ldr	r3, .L915+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L915+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
.L193:
	ldr	r3, .L915+364
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L191:
	ldr	r3, .L915+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L915+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L195
.L194:
	ldr	r3, .L915+380
	ldr	r3, [r3]	@ float
	ldr	r1, .L915+384
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L195:
	ldr	r3, .L915+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L915+388
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L915+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L915+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
.L198:
	ldr	r3, .L915+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L915+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
.L200:
	ldr	r3, .L915+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L915+396
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
.L201:
	ldr	r3, .L918
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L199:
	ldr	r3, .L918+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L202
	ldr	r3, .L918+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
.L202:
	ldr	r3, .L918+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L918+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
.L204:
	ldr	r3, .L918+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L918+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L203
.L205:
	ldr	r3, .L918+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L203:
	ldr	r3, .L918
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L918+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
.L206:
	ldr	r3, .L918+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L918+476
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L207:
	ldr	r3, .L918+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L918+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L918+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L210
	ldr	r3, .L918+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
.L210:
	ldr	r3, .L918+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L918+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
.L212:
	ldr	r3, .L918+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L918+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
.L213:
	ldr	r3, .L918+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L211:
	ldr	r3, .L918+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L918+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L918+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L214:
	ldr	r3, .L918+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	ldr	r3, .L918+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L918+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L216:
	ldr	r3, .L918+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L918+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L918+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L217:
	ldr	r3, .L918+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L218
	ldr	r3, .L918+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L918+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
.L218:
	ldr	r3, .L918+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L918+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L215:
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #14
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #15
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #16
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #17
	beq	.L219
	ldr	r3, .L918+44
	ldr	r3, [r3]
	cmp	r3, #18
	bne	.L4
.L219:
	ldr	r3, .L918+28
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L918+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L918+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L221:
	ldr	r3, .L918+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L918+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L220:
	ldr	r3, .L918+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L918+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L918+56
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L223
	ldr	r3, .L918+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
.L223:
	ldr	r3, .L918+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L225
	ldr	r3, .L918+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
.L225:
	ldr	r3, .L918+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L918+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
.L226:
	ldr	r3, .L918+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L224:
	ldr	r3, .L918+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L918+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
.L227:
	ldr	r3, .L918+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L918+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
.L229:
	ldr	r3, .L918+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L918+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
.L230:
	ldr	r3, .L918+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L228:
	ldr	r3, .L918+56
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L231
	ldr	r3, .L918+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L918+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L231:
	ldr	r3, .L918+56
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L918+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
	ldr	r3, .L918+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L232:
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	ldr	r2, .L918+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L235
.L4:
	mov	r3, #0
.L235:
	str	r3, [fp, #-24]
	b	.L236
.L919:
	.align	2
.L918:
	.word	t0_l0
	.word	t0_l1
	.word	t0_evt0
	.word	t0_evt1
	.word	t0_x
	.word	controller_l0
	.word	controller_l1
	.word	controller_z
	.word	controller_evt2
	.word	controller_evt0
	.word	controller_evt1
	.word	controller_cnt
	.word	gate_l0
	.word	gate_l1
	.word	gate_y
	.word	gate_evt0
	.word	gate_evt1
	.word	_diverge_delta
	.word	_x_t14_l1
	.word	_x_t14_l0
	.word	_x_t14_evt1
	.word	_x_t14_evt0
	.word	_x_t14_x
	.word	_x_t13_l1
	.word	_x_t13_l0
	.word	_x_t13_evt1
	.word	_x_t13_evt0
	.word	_x_t13_x
	.word	_x_t12_l1
	.word	_x_t12_l0
	.word	_x_t12_evt0
	.word	_x__diverge_delta
	.word	_x_t12_x
	.word	_x_t10_l1
	.word	_x_t10_l0
	.word	_x_t10_evt1
	.word	_x_t10_evt0
	.word	_x_t10_x
	.word	_x_t9_l1
	.word	_x_t9_l0
	.word	_x_t9_evt1
	.word	_x_t9_evt0
	.word	_x_t3_x
	.word	_x_t2_evt1
	.word	_x_t11_evt0
	.word	_x_gate_evt0
	.word	_x_t2_l1
	.word	_x_t11_l0
	.word	_x_gate_l0
	.word	_x_t3_evt0
	.word	_x_t2_l0
	.word	_x_t2_x
	.word	_x_t1_evt1
	.word	_x_t1_l1
	.word	_x_t2_evt0
	.word	_x_t0_l1
	.word	_x_t0_evt1
	.word	_x_t0_x
	.word	_x_t12_evt1
	.word	_x_delta
	.word	_x_t11_l1
	.word	_x_gate_l1
	.word	_x_t3_evt1
	.word	_x_t4_x
	.word	_x_t0_l0
	.word	_x_t11_x
	.word	_x_gate_y
	.word	_x_t8_l0
	.word	_x_t1_evt0
	.word	_x_controller_l1
	.word	_x_t6_l0
	.word	_x_t5_l0
	.word	_x_t0_evt0
	.word	_x_t1_x
	.word	_x_controller_evt1
	.word	_x_t5_l1
	.word	_x_t6_evt0
	.word	_x_t11_evt1
	.word	_x_gate_evt1
	.word	_x_t3_l1
	.word	_x_t4_evt0
	.word	_x_controller_evt2
	.word	_x_controller_evt0
	.word	_x_t6_evt1
	.word	_x_t7_x
	.word	_x_t1_l0
	.word	_x_controller_cnt
	.word	_x_t4_evt1
	.word	_x_t5_x
	.word	_x_t3_l0
	.word	_x_t4_l0
	.word	_x_controller_z
	.word	_x_t4_l1
	.word	_x_t5_evt0
	.word	_x_t5_evt1
	.word	_x_t6_x
	.word	_x_controller_l0
	.word	_x_t6_l1
	.word	_x_t7_evt0
	.word	_x_t7_evt1
	.word	_x_t8_x
	.word	_x_t7_l0
	.word	_x_t7_l1
	.word	_x_t8_evt0
	.word	_x_t8_evt1
	.word	_x_t9_x
	.word	_x_t8_l1
	.word	_x_t16_evt0
	.word	_x_t16_evt1
	.word	_x_t16_l0
	.word	_x_t16_l1
	.word	t16_x
	.word	_x_t16_x
	.word	t16_l0
	.word	t16_l1
	.word	t16_evt0
	.word	t16_evt1
	.word	_x_t15_evt0
	.word	_x_t15_evt1
	.word	1084227584
	.word	t15_l0
	.word	_x_t15_l0
	.word	t15_l1
	.word	_x_t15_l1
	.word	t15_x
	.word	_x_t15_x
	.word	delta
	.word	t15_evt0
	.word	t15_evt1
.L831:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+440
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+436
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+432
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+428
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+448
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+492
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+484
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+472
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+468
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+500
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+88
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+100
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+108
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+124
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+128
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+140
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+148
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+168
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+204
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+212
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+216
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+220
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+228
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+236
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+240
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+252
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+264
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+280
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+288
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+292
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+300
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+308
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+320
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+324
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+328
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+332
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+336
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+340
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L918+344
	str	r3, [r2]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+348
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+352
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+356
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+360
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+364
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+368
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+376
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+380
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+384
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+388
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+396
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+400
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+404
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+408
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+412
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+416
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L918+420
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L918+424
	strb	r2, [r3]
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L238
.L237:
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L238
.L239:
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L238
.L240:
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L238:
	ldr	r3, .L918+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L242
	ldr	r3, .L918+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
.L242:
	ldr	r3, .L918+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
	ldr	r3, .L918+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
.L244:
	ldr	r3, .L918+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L918+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
.L245:
	ldr	r3, .L918+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L918+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L243:
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L246
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
.L246:
	ldr	r3, .L918+448
	ldr	r3, [r3]	@ float
	ldr	r1, .L918+476
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L247:
	ldr	r3, .L918+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L918+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L918+444
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L918+448
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L250
.L249:
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L250:
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L252
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L252
	ldr	r3, .L918+448
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L253
.L252:
	ldr	r3, .L918+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L918+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L253:
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L918+444
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L255
	mov	r3, #0
	mov	r4, r3
.L255:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L918+444
	ldr	r3, [r3]	@ float
	ldr	r2, .L918+448
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L256
.L254:
	ldr	r3, .L918+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L918+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L256:
	ldr	r3, .L918+444
	ldr	r3, [r3]	@ float
	ldr	r2, .L918+448
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L259
.L257:
	ldr	r3, .L918+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L918+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L259
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L259:
	ldr	r3, .L918+436
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L918+440
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L918+444
	ldr	r3, [r3]	@ float
	ldr	r1, .L918+476
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L918+444
	ldr	r3, [r3]	@ float
	ldr	r2, .L918+448
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L262
.L260:
	ldr	r3, .L918+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L918+456
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L918+460
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L918+464
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L262:
	ldr	r3, .L918+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L918+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
.L263:
	ldr	r3, .L918+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L918+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
.L265:
	ldr	r3, .L918+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L918+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
.L266:
	ldr	r3, .L918+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L918+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L264:
	ldr	r3, .L918+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L267
	ldr	r3, .L918+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
.L267:
	ldr	r3, .L918+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
	ldr	r3, .L918+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
.L269:
	ldr	r3, .L918+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
	ldr	r3, .L918+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
.L270:
	ldr	r3, .L918+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L918+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L268:
	ldr	r3, .L918+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L918+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L272
.L271:
	ldr	r3, .L918+500
	ldr	r3, [r3]	@ float
	ldr	r1, .L918+476
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L272:
	ldr	r3, .L918+480
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L918+484
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L274
	ldr	r3, .L918+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L918+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L274
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L918+496
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L918+500
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L275
.L274:
	ldr	r3, .L918+504
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L918+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L275
	ldr	r3, .L918+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L275:
	ldr	r3, .L920
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L277
	ldr	r3, .L920+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L920+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L277
	ldr	r3, .L920+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L920+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L278
.L277:
	ldr	r3, .L920+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L920+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L920+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L278:
	ldr	r3, .L920+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L920
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L279
	ldr	r3, .L920+32
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L280
	mov	r3, #0
	mov	r4, r3
.L280:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L920+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L920+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L279
	ldr	r3, .L920+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L281
.L279:
	ldr	r3, .L920+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L920+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L281
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L281
	ldr	r3, .L920+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L281:
	ldr	r3, .L920+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L920
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L920+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L920+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L920+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L284
.L282:
	ldr	r3, .L920+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L920+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L284
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L920+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L284:
	ldr	r3, .L920
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L920+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L920+32
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L285
	ldr	r3, .L920+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L285
	ldr	r3, .L920+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
	ldr	r3, .L920+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L287
.L285:
	ldr	r3, .L920+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L920+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L920+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L287:
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L288
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
.L288:
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L290
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
.L290:
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
.L291:
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L289:
	ldr	r3, .L920+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L292
	ldr	r3, .L920+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
.L292:
	ldr	r3, .L920+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L294
	ldr	r3, .L920+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
.L294:
	ldr	r3, .L920+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
	ldr	r3, .L920+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L293
.L295:
	ldr	r3, .L920+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L293:
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L296
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L297
.L296:
	ldr	r3, .L920+52
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L297:
	ldr	r3, .L920+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L920+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L920+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L920+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L300
.L299:
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L300
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L300:
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L920+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L303
.L302:
	ldr	r3, .L920+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L303
	ldr	r3, .L920+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L303
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L303
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L303:
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L920+64
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L305
	mov	r3, #0
	mov	r4, r3
.L305:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L920+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L306
.L304:
	ldr	r3, .L920+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L306
	ldr	r3, .L920+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L306
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L306
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L306:
	ldr	r3, .L920+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L307
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L307
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L309
.L307:
	ldr	r3, .L920+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L920+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L309
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L309
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L309:
	ldr	r3, .L920+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L920+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L920+64
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L920+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+52
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L312
.L310:
	ldr	r3, .L920+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L920+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L312
	ldr	r3, .L920+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L312:
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L313
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L314
.L313:
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L314
.L315:
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L316
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L314
.L316:
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L314:
	ldr	r3, .L920+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L317
	ldr	r3, .L920+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
.L317:
	ldr	r3, .L920+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L319
	ldr	r3, .L920+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
.L319:
	ldr	r3, .L920+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L920+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
.L320:
	ldr	r3, .L920+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L318:
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L321
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L322
.L321:
	ldr	r3, .L920+92
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L322:
	ldr	r3, .L920+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L920+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L920+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L920+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L325
.L324:
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L325
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L325:
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L327
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L327
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L327
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L327
	ldr	r3, .L920+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L328
.L327:
	ldr	r3, .L920+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L328
	ldr	r3, .L920+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L328
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L328
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L328:
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L329
	ldr	r3, .L920+104
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L330
	mov	r3, #0
	mov	r4, r3
.L330:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L329
	ldr	r3, .L920+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L331
.L329:
	ldr	r3, .L920+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L920+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L331
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L331
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L331:
	ldr	r3, .L920+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L332
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L332
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L332
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L332
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L334
.L332:
	ldr	r3, .L920+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L920+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L334
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L334:
	ldr	r3, .L920+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L920+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L920+104
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L335
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L335
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L335
	ldr	r3, .L920+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L337
.L335:
	ldr	r3, .L920+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L920+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L920+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L920+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L337:
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L338
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L339
.L338:
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L340
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L339
.L340:
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L341
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L339
.L341:
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L921
.L922:
	.align	2
.L920:
	.word	_x_t15_l0
	.word	_x_t15_l1
	.word	t15_evt0
	.word	t15_evt1
	.word	_x_t15_x
	.word	t15_l0
	.word	t15_l1
	.word	delta
	.word	t15_x
	.word	_x_t14_l0
	.word	_x_t14_l1
	.word	_x_t14_evt0
	.word	_x_t14_evt1
	.word	_x_t14_x
	.word	t14_l0
	.word	t14_l1
	.word	t14_x
	.word	t14_evt0
	.word	t14_evt1
	.word	_x_t13_l0
	.word	_x_t13_l1
	.word	_x_t13_evt0
	.word	_x_t13_evt1
	.word	_x_t13_x
	.word	t13_l0
	.word	t13_l1
	.word	t13_x
	.word	t13_evt0
	.word	t13_evt1
	.word	_x_t12_evt0
	.word	_x_t12_evt1
	.word	_x_t12_l0
	.word	_x_t12_l1
	.word	t12_x
	.word	_x_t12_x
	.word	t12_l0
	.word	t12_l1
	.word	t12_evt0
	.word	t12_evt1
	.word	_x_t11_evt0
	.word	_x_t11_evt1
	.word	_x_t11_l0
	.word	_x_t11_l1
	.word	t11_x
	.word	_x_t11_x
	.word	t11_l0
	.word	t11_l1
	.word	t11_evt0
	.word	t11_evt1
	.word	_x_t10_evt0
	.word	_x_t10_evt1
	.word	1084227584
	.word	_x_t10_l1
	.word	_x_t10_l0
	.word	t10_evt1
	.word	t10_x
	.word	_x_t10_x
	.word	t10_l0
	.word	t10_l1
	.word	delta
	.word	t10_evt0
.L921:
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L339:
	ldr	r3, .L920+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L342
	ldr	r3, .L920+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
.L342:
	ldr	r3, .L920+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L344
	ldr	r3, .L920+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
.L344:
	ldr	r3, .L920+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L345
	ldr	r3, .L920+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
.L345:
	ldr	r3, .L920+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L343:
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L347
.L346:
	ldr	r3, .L920+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L347:
	ldr	r3, .L920+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L920+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L349
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L920+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L920+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L350
.L349:
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L350
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L350:
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L352
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L352
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L352
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L352
	ldr	r3, .L920+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L353
.L352:
	ldr	r3, .L920+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L353
	ldr	r3, .L920+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L353
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L353:
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L354
	ldr	r3, .L920+132
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L355
	mov	r3, #0
	mov	r4, r3
.L355:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L354
	ldr	r3, .L920+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L356
.L354:
	ldr	r3, .L920+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L356
	ldr	r3, .L920+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L356
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L356
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L356:
	ldr	r3, .L920+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
.L357:
	ldr	r3, .L920+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L920+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L359:
	ldr	r3, .L920+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L360
	ldr	r3, .L920+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L360
	ldr	r3, .L920+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L360
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L360
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L360
	ldr	r3, .L920+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L362
.L360:
	ldr	r3, .L920+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L920+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L362
	ldr	r3, .L920+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L362:
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L363
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
.L363:
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L365
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
.L365:
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L364
.L366:
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L364:
	ldr	r3, .L920+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L367
	ldr	r3, .L920+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
.L367:
	ldr	r3, .L920+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L369
	ldr	r3, .L920+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
.L369:
	ldr	r3, .L920+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L920+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
.L370:
	ldr	r3, .L920+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L368:
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L371
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L372
.L371:
	ldr	r3, .L920+176
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L372:
	ldr	r3, .L920+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L920+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L374
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L920+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L920+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L375
.L374:
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L375
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L375:
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L377
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L377
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L377
	ldr	r3, .L920+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L378
.L377:
	ldr	r3, .L920+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L378
	ldr	r3, .L920+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L378
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L378
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L378:
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L920+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L380
	mov	r3, #0
	mov	r4, r3
.L380:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L920+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L381
.L379:
	ldr	r3, .L920+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L920+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L381
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L381:
	ldr	r3, .L920+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L382
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L384
.L382:
	ldr	r3, .L920+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L920+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L384
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L384:
	ldr	r3, .L920+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L385
	ldr	r3, .L920+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L385
	ldr	r3, .L920+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L385
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L385
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L385
	ldr	r3, .L920+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L387
.L385:
	ldr	r3, .L920+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L920+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L387
	ldr	r3, .L920+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L387:
	ldr	r3, .L920+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L388
	ldr	r3, .L920+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
.L388:
	ldr	r3, .L920+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L920+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
.L390:
	ldr	r3, .L920+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L391
	ldr	r3, .L920+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L389
.L391:
	ldr	r3, .L920+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L389:
	ldr	r3, .L920+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L920+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L393
.L392:
	ldr	r3, .L920+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L394
	ldr	r3, .L920+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L393
.L394:
	ldr	r3, .L920+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L395
	ldr	r3, .L920+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L393
.L395:
	ldr	r3, .L920+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L393:
	ldr	r3, .L920+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L396
	ldr	r3, .L920+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L397
.L396:
	ldr	r3, .L920+224
	ldr	r3, [r3]	@ float
	ldr	r1, .L920+204
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L397:
	ldr	r3, .L920+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L920+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L920+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L399
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L920+220
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L920+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L400
.L399:
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L920+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L400
	ldr	r3, .L920+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L400:
	ldr	r3, .L920+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L402
	ldr	r3, .L920+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L402
	ldr	r3, .L920+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L402
	ldr	r3, .L920+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L402
	ldr	r3, .L920+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L403
.L402:
	ldr	r3, .L920+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L403
	ldr	r3, .L920+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L403
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L920+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L920+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L403:
	ldr	r3, .L920+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L920+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L404
	ldr	r3, .L920+220
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L405
	mov	r3, #0
	mov	r4, r3
.L405:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L920+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L920+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L920+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L920+224
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L406
.L404:
	ldr	r3, .L920+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L406
	ldr	r3, .L920+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L406
	ldr	r3, .L920+236
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L406
	ldr	r3, .L920+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L406:
	ldr	r3, .L923+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L923+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L923+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L923+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L407
	ldr	r3, .L923
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L409
.L407:
	ldr	r3, .L923+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L923+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L409
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L923+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L409:
	ldr	r3, .L923+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L410
	ldr	r3, .L923+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L410
	ldr	r3, .L923+4
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L410
	ldr	r3, .L923
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L410
	ldr	r3, .L923+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L410
	ldr	r3, .L923+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L412
.L410:
	ldr	r3, .L923+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L923+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L923+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L412:
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L413
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
.L413:
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L415
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
.L415:
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L416
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
.L416:
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L414:
	ldr	r3, .L923+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L417
	ldr	r3, .L923+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
.L417:
	ldr	r3, .L923+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L923+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
.L419:
	ldr	r3, .L923+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L420
	ldr	r3, .L923+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L418
.L420:
	ldr	r3, .L923+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L418:
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L421
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L422
.L421:
	ldr	r3, .L923+48
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L422:
	ldr	r3, .L923+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L424
	ldr	r3, .L923+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L424
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L923+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L923+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L425
.L424:
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L425:
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L427
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L427
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L427
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L427
	ldr	r3, .L923+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L428
.L427:
	ldr	r3, .L923+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L428
	ldr	r3, .L923+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L428
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L428
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L428:
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L429
	ldr	r3, .L923+60
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L430
	mov	r3, #0
	mov	r4, r3
.L430:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L923+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L431
.L429:
	ldr	r3, .L923+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L923+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L431
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L431
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L431:
	ldr	r3, .L923+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L432
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L434
.L432:
	ldr	r3, .L923+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L923+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L434
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L434:
	ldr	r3, .L923+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L435
	ldr	r3, .L923+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L435
	ldr	r3, .L923+60
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L435
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L435
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L435
	ldr	r3, .L923+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L437
.L435:
	ldr	r3, .L923+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L923+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L923+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L437:
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L438
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
.L438:
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L440
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
.L440:
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L441
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L439
.L441:
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L439:
	ldr	r3, .L923+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L442
	ldr	r3, .L923+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
.L442:
	ldr	r3, .L923+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L444
	ldr	r3, .L923+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
.L444:
	ldr	r3, .L923+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L923+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L443
.L445:
	ldr	r3, .L923+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L443:
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L446
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
.L446:
	ldr	r3, .L923+88
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L447:
	ldr	r3, .L923+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L449
	ldr	r3, .L923+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L449
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L923+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L923+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L450
.L449:
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L450
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L450:
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L452
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L452
	ldr	r3, .L923+88
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L453
.L452:
	ldr	r3, .L923+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L453
	ldr	r3, .L923+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L453
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L453
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L453:
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L454
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L454
	ldr	r3, .L923+100
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L455
	mov	r3, #0
	mov	r4, r3
.L455:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L454
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L454
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L454
	ldr	r3, .L923+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L456
.L454:
	ldr	r3, .L923+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L923+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L456:
	ldr	r3, .L923+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L457
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L457
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L459
.L457:
	ldr	r3, .L923+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L459
	ldr	r3, .L923+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L459
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L459
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L459:
	ldr	r3, .L923+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L460
	ldr	r3, .L923+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L460
	ldr	r3, .L923+100
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L460
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L460
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L460
	ldr	r3, .L923+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L462
.L460:
	ldr	r3, .L923+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L923+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L923+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L462:
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L463
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L464
.L463:
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L465
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L464
.L465:
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L464
.L466:
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L464:
	ldr	r3, .L923+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L467
	ldr	r3, .L923+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L468
.L467:
	ldr	r3, .L923+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L923+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L468
.L469:
	ldr	r3, .L923+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L923+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L468
.L470:
	ldr	r3, .L923+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L468:
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L471
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L472
.L471:
	ldr	r3, .L923+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L472:
	ldr	r3, .L923+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L474
	ldr	r3, .L923+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L474
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L923+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L923+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	b	.L924
.L925:
	.align	2
.L923:
	.word	t10_evt1
	.word	t10_x
	.word	_x_t10_x
	.word	_x_t10_l0
	.word	_x_t10_l1
	.word	t10_evt0
	.word	t10_l1
	.word	t10_l0
	.word	_x_t9_l0
	.word	_x_t9_l1
	.word	_x_t9_evt0
	.word	_x_t9_evt1
	.word	_x_t9_x
	.word	t9_l0
	.word	t9_l1
	.word	t9_x
	.word	t9_evt0
	.word	t9_evt1
	.word	_x_t8_l0
	.word	_x_t8_l1
	.word	_x_t8_evt0
	.word	_x_t8_evt1
	.word	_x_t8_x
	.word	t8_l0
	.word	t8_l1
	.word	t8_x
	.word	t8_evt0
	.word	t8_evt1
	.word	_x_t7_evt0
	.word	_x_t7_evt1
	.word	delta
	.word	_x_t7_l0
	.word	_x_t7_l1
	.word	t7_x
	.word	_x_t7_x
	.word	t7_l0
	.word	t7_l1
	.word	t7_evt0
	.word	t7_evt1
	.word	_x_t6_evt0
	.word	_x_t6_evt1
	.word	_x_t6_l0
	.word	_x_t6_l1
	.word	t6_x
	.word	_x_t6_x
	.word	t6_l0
	.word	t6_l1
	.word	t6_evt0
	.word	t6_evt1
	.word	_x_t5_evt0
	.word	_x_t5_evt1
	.word	_x_t5_l0
	.word	_x_t5_l1
	.word	1084227584
	.word	t5_x
	.word	_x_t5_x
	.word	t5_l0
	.word	t5_l1
	.word	delta
	.word	t5_evt0
	.word	t5_evt1
.L924:
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L475
.L474:
	ldr	r3, .L923+120
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L475
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L475:
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L477
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L477
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L477
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L477
	ldr	r3, .L923+136
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L478
.L477:
	ldr	r3, .L923+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L923+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L478
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L478:
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L479
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L479
	ldr	r3, .L923+132
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L480
	mov	r3, #0
	mov	r4, r3
.L480:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L479
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L479
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L479
	ldr	r3, .L923+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L481
.L479:
	ldr	r3, .L923+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L923+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L481
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L481
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L481:
	ldr	r3, .L923+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L482
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L482
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L482
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L482
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L484
.L482:
	ldr	r3, .L923+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L923+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L484
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L484
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L484:
	ldr	r3, .L923+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L485
	ldr	r3, .L923+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L485
	ldr	r3, .L923+132
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L485
	ldr	r3, .L923+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L487
.L485:
	ldr	r3, .L923+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L487
	ldr	r3, .L923+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L487
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L487
	ldr	r3, .L923+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L487:
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L488
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
.L488:
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L490
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
.L490:
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
.L491:
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L489:
	ldr	r3, .L923+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L492
	ldr	r3, .L923+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
.L492:
	ldr	r3, .L923+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L494
	ldr	r3, .L923+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
.L494:
	ldr	r3, .L923+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
	ldr	r3, .L923+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L493
.L495:
	ldr	r3, .L923+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L493:
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L496
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L497
.L496:
	ldr	r3, .L923+176
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L497:
	ldr	r3, .L923+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L923+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L923+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L923+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L500
.L499:
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L500
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L500:
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L923+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L503
.L502:
	ldr	r3, .L923+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L503
	ldr	r3, .L923+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L503
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L503:
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L504
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L504
	ldr	r3, .L923+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L505
	mov	r3, #0
	mov	r4, r3
.L505:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L504
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L504
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L504
	ldr	r3, .L923+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L506
.L504:
	ldr	r3, .L923+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L923+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L506
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L506
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L506:
	ldr	r3, .L923+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L507
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L507
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L509
.L507:
	ldr	r3, .L923+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L923+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L509
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L509
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L509:
	ldr	r3, .L923+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L510
	ldr	r3, .L923+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L510
	ldr	r3, .L923+172
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L510
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L510
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L510
	ldr	r3, .L923+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L512
.L510:
	ldr	r3, .L923+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L512
	ldr	r3, .L923+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L512
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L512
	ldr	r3, .L923+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L512:
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L513
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L514
.L513:
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L515
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L514
.L515:
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L514
.L516:
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L514:
	ldr	r3, .L923+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L517
	ldr	r3, .L923+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
.L517:
	ldr	r3, .L923+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L519
	ldr	r3, .L923+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
.L519:
	ldr	r3, .L923+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L520
	ldr	r3, .L923+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
.L520:
	ldr	r3, .L923+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L518:
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L521
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
.L521:
	ldr	r3, .L923+220
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L522:
	ldr	r3, .L923+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L923+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L923+216
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L923+220
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L525
.L524:
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L525
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L525:
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L527
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L527
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L527
	ldr	r3, .L923+220
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L528
.L527:
	ldr	r3, .L923+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L528
	ldr	r3, .L923+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L528
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L528:
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L529
	ldr	r3, .L923+216
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L530
	mov	r3, #0
	mov	r4, r3
.L530:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L529
	ldr	r3, .L923+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L531
.L529:
	ldr	r3, .L923+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L923+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L531
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L531
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L531:
	ldr	r3, .L923+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L532
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L532
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L532
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L532
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L534
.L532:
	ldr	r3, .L923+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L534
	ldr	r3, .L923+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L534
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L534
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L534:
	ldr	r3, .L923+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L923+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L923+216
	ldr	r3, [r3]	@ float
	ldr	r1, .L923+212
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L923+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L923+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L537
.L535:
	ldr	r3, .L923+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L537
	ldr	r3, .L923+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L537
	ldr	r3, .L923+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L537
	ldr	r3, .L923+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L923+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L537:
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L538
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
.L538:
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L540
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
.L540:
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L539
.L541:
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L539:
	ldr	r3, .L926+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L542
	ldr	r3, .L926+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L543
.L542:
	ldr	r3, .L926+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L926+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L543
.L544:
	ldr	r3, .L926+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L545
	ldr	r3, .L926+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L543
.L545:
	ldr	r3, .L926+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L543:
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L546
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L547
.L546:
	ldr	r3, .L926+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L547:
	ldr	r3, .L926+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L926+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L926+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L926+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L550
.L549:
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L550
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L550:
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L552
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L552
	ldr	r3, .L926+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L553
.L552:
	ldr	r3, .L926+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L553
	ldr	r3, .L926+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L553
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L553
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L553:
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L554
	ldr	r3, .L926+28
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L555
	mov	r3, #0
	mov	r4, r3
.L555:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L554
	ldr	r3, .L926+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L556
.L554:
	ldr	r3, .L926+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L556
	ldr	r3, .L926+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L556
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L556
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L556:
	ldr	r3, .L926+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L559
.L557:
	ldr	r3, .L926+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L559
	ldr	r3, .L926+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L559
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L559
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L559:
	ldr	r3, .L926
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
	ldr	r3, .L926+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
	ldr	r3, .L926+28
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L560
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L560
	ldr	r3, .L926+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L562
.L560:
	ldr	r3, .L926+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L926+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L562
	ldr	r3, .L926+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L562:
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L563
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
.L563:
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L565
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
.L565:
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
.L566:
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L564:
	ldr	r3, .L926+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L567
	ldr	r3, .L926+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
.L567:
	ldr	r3, .L926+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L926+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
.L569:
	ldr	r3, .L926+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L570
	ldr	r3, .L926+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
.L570:
	ldr	r3, .L926+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L568:
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L571
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L572
.L571:
	ldr	r3, .L926+56
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L572:
	ldr	r3, .L926+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L926+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L926+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L926+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L575
.L574:
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L575
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L575:
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L926+56
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L578
.L577:
	ldr	r3, .L926+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L578
	ldr	r3, .L926+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L578
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L578
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L578:
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L926+68
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L580
	mov	r3, #0
	mov	r4, r3
.L580:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L926+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L581
.L579:
	ldr	r3, .L926+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L926+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L581
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L581
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L581:
	ldr	r3, .L926+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L584
.L582:
	ldr	r3, .L926+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L926+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L584
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L584:
	ldr	r3, .L926+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L585
	ldr	r3, .L926+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L585
	ldr	r3, .L926+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L585
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L585
	ldr	r3, .L926+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L587
.L585:
	ldr	r3, .L926+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L926+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L587
	ldr	r3, .L926+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L587:
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L589
.L588:
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L589
.L590:
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L591
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L589
.L591:
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L589:
	ldr	r3, .L926+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L592
	ldr	r3, .L926+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L593
.L592:
	ldr	r3, .L926+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L926+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L593
.L594:
	ldr	r3, .L926+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L595
	ldr	r3, .L926+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L593
.L595:
	ldr	r3, .L926+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L593:
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L596
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
.L596:
	ldr	r3, .L926+100
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L597:
	ldr	r3, .L926+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L926+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L926+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L926+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L600
.L599:
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L600
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L600:
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L602
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L602
	ldr	r3, .L926+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L603
.L602:
	ldr	r3, .L926+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L603
	ldr	r3, .L926+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L603
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L603
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L603:
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L604
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L604
	ldr	r3, .L926+96
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L605
	mov	r3, #0
	mov	r4, r3
.L605:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L604
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L604
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L604
	ldr	r3, .L926+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+100
	ldr	r2, [r2]	@ float
	b	.L927
.L928:
	.align	2
.L926:
	.word	_x_t4_l0
	.word	_x_t4_l1
	.word	_x_t4_evt0
	.word	_x_t4_evt1
	.word	_x_t4_x
	.word	t4_l0
	.word	t4_l1
	.word	t4_x
	.word	t4_evt0
	.word	t4_evt1
	.word	_x_t3_l0
	.word	_x_t3_l1
	.word	_x_t3_evt0
	.word	_x_t3_evt1
	.word	_x_t3_x
	.word	t3_l0
	.word	t3_l1
	.word	t3_x
	.word	t3_evt0
	.word	t3_evt1
	.word	_x_t2_evt0
	.word	_x_t2_evt1
	.word	_x_t2_l0
	.word	_x_t2_l1
	.word	t2_x
	.word	_x_t2_x
	.word	t2_l0
	.word	t2_l1
	.word	t2_evt0
	.word	t2_evt1
	.word	_x_t1_evt0
	.word	_x_t1_evt1
	.word	_x_t1_l0
	.word	_x_t1_l1
	.word	t1_x
	.word	_x_t1_x
	.word	t1_l0
	.word	t1_l1
	.word	t1_evt0
	.word	t1_evt1
	.word	_x_t0_evt0
	.word	_x_t0_evt1
	.word	_x_t0_l0
	.word	_x_t0_l1
	.word	1084227584
	.word	t0_x
	.word	_x_t0_x
	.word	t0_l0
	.word	t0_l1
	.word	delta
	.word	t0_evt0
	.word	t0_evt1
	.word	_x_controller_l0
	.word	_x_controller_l1
	.word	_x_controller_evt2
	.word	_x_controller_evt0
	.word	_x_controller_evt1
	.word	_x_controller_cnt
.L927:
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L606
.L604:
	ldr	r3, .L926+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L606
	ldr	r3, .L926+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L606
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L606
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L606:
	ldr	r3, .L926+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L609
.L607:
	ldr	r3, .L926+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L609
	ldr	r3, .L926+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L609
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L609
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L609:
	ldr	r3, .L926+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L926+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L926+96
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L610
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L610
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L926+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L612
.L610:
	ldr	r3, .L926+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L926+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L926+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L612:
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L613
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L614
.L613:
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L614
.L615:
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L616
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L614
.L616:
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L614:
	ldr	r3, .L926+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L617
	ldr	r3, .L926+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
.L617:
	ldr	r3, .L926+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L619
	ldr	r3, .L926+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
.L619:
	ldr	r3, .L926+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L620
	ldr	r3, .L926+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L618
.L620:
	ldr	r3, .L926+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L618:
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L622
.L621:
	ldr	r3, .L926+140
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L622:
	ldr	r3, .L926+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L926+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L624
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L926+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L926+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L625
.L624:
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L625
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L625:
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L627
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L627
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L627
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L627
	ldr	r3, .L926+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L628
.L627:
	ldr	r3, .L926+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L628
	ldr	r3, .L926+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L628
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L628
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L628:
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L629
	ldr	r3, .L926+136
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L630
	mov	r3, #0
	mov	r4, r3
.L630:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L629
	ldr	r3, .L926+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L631
.L629:
	ldr	r3, .L926+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L926+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L631
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L631:
	ldr	r3, .L926+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
.L632:
	ldr	r3, .L926+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L926+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L634:
	ldr	r3, .L926+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L635
	ldr	r3, .L926+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L635
	ldr	r3, .L926+136
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L635
	ldr	r3, .L926+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L637
.L635:
	ldr	r3, .L926+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L637
	ldr	r3, .L926+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L637
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L637
	ldr	r3, .L926+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L637:
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L638
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
.L638:
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
.L640:
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L641
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L639
.L641:
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L639:
	ldr	r3, .L926+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L642
	ldr	r3, .L926+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
.L642:
	ldr	r3, .L926+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L644
	ldr	r3, .L926+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
.L644:
	ldr	r3, .L926+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L926+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
.L645:
	ldr	r3, .L926+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L643:
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L646
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L647
.L646:
	ldr	r3, .L926+184
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L647:
	ldr	r3, .L926+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L926+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L649
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L926+180
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L926+184
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L650
.L649:
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L650
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L650:
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L652
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L652
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L652
	ldr	r3, .L926+184
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L653
.L652:
	ldr	r3, .L926+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L653
	ldr	r3, .L926+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L653
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L653
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L653:
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L926+180
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L655
	mov	r3, #0
	mov	r4, r3
.L655:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L926+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+184
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L656
.L654:
	ldr	r3, .L926+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L926+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L656:
	ldr	r3, .L926+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+184
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L657
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L657
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L657
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L657
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
.L657:
	ldr	r3, .L926+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L659
	ldr	r3, .L926+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L659
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L659
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L659:
	ldr	r3, .L926+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L660
	ldr	r3, .L926+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L660
	ldr	r3, .L926+180
	ldr	r3, [r3]	@ float
	ldr	r1, .L926+176
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L660
	ldr	r3, .L926+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L926+184
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L662
.L660:
	ldr	r3, .L926+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L662
	ldr	r3, .L926+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L662
	ldr	r3, .L926+196
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L662
	ldr	r3, .L926+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L662:
	ldr	r3, .L926+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L663
	ldr	r3, .L926+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L664
.L663:
	ldr	r3, .L926+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L665
	ldr	r3, .L926+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L664
.L665:
	ldr	r3, .L926+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L666
	ldr	r3, .L926+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L664
.L666:
	ldr	r3, .L926+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L664:
	ldr	r3, .L926+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L667
	ldr	r3, .L926+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L667
	ldr	r3, .L926+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L668
.L667:
	ldr	r3, .L926+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L669
	ldr	r3, .L926+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L669
	ldr	r3, .L926+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L668
.L669:
	ldr	r3, .L926+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L670
	ldr	r3, .L926+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L670
	ldr	r3, .L926+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L668
.L670:
	ldr	r3, .L926+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L671
	ldr	r3, .L926+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L671
	ldr	r3, .L926+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L668
.L671:
	ldr	r3, .L926+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L926+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L926+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L668:
	ldr	r3, .L926+228
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L672
	ldr	r3, .L926+228
	ldr	r3, [r3]
	cmp	r3, #1
	beq	.L672
	ldr	r3, .L926+228
	ldr	r3, [r3]
	cmp	r3, #2
	beq	.L672
	ldr	r3, .L926+228
	ldr	r3, [r3]
	cmp	r3, #3
	beq	.L672
	ldr	r3, .L926+228
	ldr	r3, [r3]
	cmp	r3, #4
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #5
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #6
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #7
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #8
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #9
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #10
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #11
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #12
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #13
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #14
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #15
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #16
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #17
	beq	.L672
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #18
	bne	.L241
.L672:
	ldr	r3, .L929+4
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L673
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L674
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L674:
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L673:
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L675
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L675
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L929+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L929+4
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L675
	ldr	r3, .L929+28
	ldr	r2, [r3]
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L677
.L675:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L677
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L677
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L677:
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L679
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L679
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L679
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L679
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L679
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L679
	ldr	r3, .L929+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L680
.L679:
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L680
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L680
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L680
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L680:
	ldr	r3, .L929+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L929+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
.L683:
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
.L681:
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L684
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L684
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L684:
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L685
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L685
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L685
	ldr	r3, .L929+28
	ldr	r2, [r3]
	ldr	r3, .L929
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L686
.L685:
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L929+28
	ldr	r2, [r3]
	ldr	r3, .L929
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	beq	.L686
.L687:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L688
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L688
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L686
.L688:
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L686
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L686
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L686:
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L929+28
	ldr	r2, [r3]
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L689
	ldr	r3, .L929+24
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L690
.L689:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L691
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L691
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
.L691:
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L690
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L690
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L690:
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L692
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
.L692:
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L694
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
.L694:
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L693:
	ldr	r3, .L929+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L929+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L695
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L697
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L697
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L697
	ldr	r3, .L929+28
	ldr	r2, [r3]
	ldr	r3, .L929
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L698
.L697:
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L695
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L695
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L695
	ldr	r3, .L929+28
	ldr	r2, [r3]
	ldr	r3, .L929
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmp	r3, #1
	bne	.L695
	ldr	r3, .L929+28
	ldr	r3, [r3]
	cmp	r3, #1
	bgt	.L698
.L695:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L699
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L699
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
.L699:
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L698
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L698:
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L700
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L929+28
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L700
	ldr	r3, .L929
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L929+4
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L701
.L700:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L702
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L702
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L701
.L702:
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L701
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L701:
	ldr	r3, .L929+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L929+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L703
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L705
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L706
.L705:
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L703
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L706
.L703:
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L706:
	ldr	r3, .L929+28
	ldr	r2, [r3]
	ldr	r3, .L929
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	bne	.L707
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L707
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L707
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L707
	ldr	r3, .L929+24
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L708
.L707:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L708
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L709
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L709
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L708
.L709:
	ldr	r3, .L929+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L708
	ldr	r3, .L929+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L708
	ldr	r3, .L929+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L708
	ldr	r3, .L929+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L708:
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L710
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
.L710:
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L712
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
.L712:
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L713
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
.L713:
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L711:
	ldr	r3, .L929+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L929+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L715
.L714:
	ldr	r3, .L929+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L929+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L715
.L716:
	ldr	r3, .L929+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L717
	ldr	r3, .L929+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L715
.L717:
	ldr	r3, .L929+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L929+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L715:
	ldr	r3, .L929+40
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L718
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L718
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L718:
	ldr	r3, .L929+40
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L719
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L719
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L719:
	ldr	r3, .L929+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L929+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L929+52
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L929+40
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L721
.L720:
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L722:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L721:
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L724
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L724
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L724
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L724
	ldr	r3, .L929+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L725
.L724:
	ldr	r3, .L929+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L929+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L725
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L725
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L725:
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L726
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L929+52
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L929+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L929+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L728
.L726:
	ldr	r3, .L929+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L728
	ldr	r3, .L929+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L728
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	b	.L930
.L931:
	.align	2
.L929:
	.word	_x_controller_cnt
	.word	_x_controller_z
	.word	_x_controller_l0
	.word	_x_controller_l1
	.word	controller_l0
	.word	controller_l1
	.word	controller_z
	.word	controller_cnt
	.word	_x_gate_evt0
	.word	_x_gate_evt1
	.word	_x_gate_y
	.word	_x_gate_l0
	.word	_x_gate_l1
	.word	gate_y
	.word	gate_l0
	.word	gate_l1
	.word	_x_delta
	.word	gate_evt1
	.word	gate_evt0
	.word	controller_evt2
	.word	controller_evt1
	.word	controller_evt0
	.word	t16_evt1
	.word	t16_evt0
	.word	t15_evt1
	.word	t15_evt0
	.word	t14_evt1
	.word	t14_evt0
	.word	t13_evt1
	.word	t13_evt0
	.word	t12_evt1
	.word	t12_evt0
	.word	t11_evt1
	.word	t11_evt0
	.word	t10_evt1
	.word	t10_evt0
	.word	t9_evt1
	.word	t9_evt0
	.word	t8_evt1
	.word	t8_evt0
	.word	t7_evt1
	.word	t7_evt0
	.word	t6_evt1
	.word	t6_evt0
	.word	t5_evt1
	.word	t5_evt0
	.word	t4_evt1
	.word	t4_evt0
	.word	t3_evt1
	.word	t3_evt0
	.word	t2_evt1
	.word	t2_evt0
	.word	t0_evt1
	.word	t0_evt0
	.word	t1_evt1
	.word	t1_evt0
	.word	delta
	.word	_diverge_delta
	.word	_x__diverge_delta
.L930:
.L728:
	ldr	r3, .L929+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L729
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L731
.L729:
	ldr	r3, .L929+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L929+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L731
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L731:
	ldr	r3, .L929+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L929+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L732
	ldr	r3, .L929+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L732
	ldr	r3, .L929+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L732
	ldr	r3, .L929+52
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L732
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L732
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L732
	ldr	r3, .L929+52
	ldr	r3, [r3]	@ float
	mov	r1, #1073741824
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L735
.L732:
	ldr	r3, .L929+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L929+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L735
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L735:
	ldr	r3, .L929+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L737
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L738
.L737:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L738
	ldr	r3, .L929+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L738:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L740
.L739:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L740
	ldr	r3, .L929+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L740:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L741
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L742
.L741:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L742
	ldr	r3, .L929+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L742:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L743
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L744
.L743:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L929+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L744:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L745
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L746
.L745:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L746
	ldr	r3, .L929+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L746:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L747
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L748
.L747:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L748
	ldr	r3, .L929+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L748:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L749
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L750
.L749:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L750
	ldr	r3, .L929+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L750:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L751
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L752
.L751:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L752
	ldr	r3, .L929+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L752:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L754
.L753:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L754
	ldr	r3, .L929+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L754:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L756
.L755:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L756
	ldr	r3, .L929+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L756:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L757
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L758
.L757:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L758
	ldr	r3, .L929+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L758:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L759
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L760
.L759:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L760
	ldr	r3, .L929+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L760:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L761
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L762
.L761:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L762
	ldr	r3, .L929+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L762:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L763
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L764
.L763:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L764
	ldr	r3, .L929+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L764:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L765
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
.L765:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L929+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L766:
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L767
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L768
.L767:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L768
	ldr	r3, .L929+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L768:
	ldr	r3, .L929+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L769
	ldr	r3, .L929+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L770
.L769:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L770
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L770:
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L771
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L771
	mov	r3, #1
	b	.L772
.L771:
	mov	r3, #0
.L772:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L773
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L773
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L773
	mov	r3, #1
	b	.L774
.L773:
	mov	r3, #0
.L774:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L775
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L241
.L775:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L929+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L778
	ldr	r3, .L929+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L778
	mov	r3, #1
	b	.L779
.L778:
	mov	r3, #0
.L779:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L780
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	mov	r3, #1
	b	.L781
.L780:
	mov	r3, #0
.L781:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L241
.L777:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L783
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L783
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L783
	mov	r3, #1
	b	.L784
.L783:
	mov	r3, #0
.L784:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L785
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L785:
	ldr	r3, .L929+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L787
	ldr	r3, .L929+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L787:
	ldr	r3, .L929+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L929+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L788:
	ldr	r3, .L929+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L789
	ldr	r3, .L929+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L789:
	ldr	r3, .L929+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L790
	ldr	r3, .L929+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L790:
	ldr	r3, .L929+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L791
	ldr	r3, .L929+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L791:
	ldr	r3, .L929+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
	ldr	r3, .L929+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L792:
	ldr	r3, .L929+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L793
	ldr	r3, .L929+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L793:
	ldr	r3, .L929+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L794
	ldr	r3, .L929+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L794:
	ldr	r3, .L929+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L795
	ldr	r3, .L929+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L795:
	ldr	r3, .L929+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L796
	ldr	r3, .L929+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L796:
	ldr	r3, .L929+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L797
	ldr	r3, .L929+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L797:
	ldr	r3, .L929+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L798
	ldr	r3, .L929+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L798:
	ldr	r3, .L929+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L799
	ldr	r3, .L929+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L799:
	ldr	r3, .L929+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L800
	ldr	r3, .L929+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L800:
	ldr	r3, .L929+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L801
	ldr	r3, .L929+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
.L801:
	ldr	r3, .L929+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L802
	ldr	r3, .L929+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L802
.L786:
	mov	r3, #1
	b	.L803
.L802:
	mov	r3, #0
.L803:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L241
.L782:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L804
	ldr	r3, .L929+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L805
	ldr	r3, .L929+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L929+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L805
	mov	r3, #1
	b	.L806
.L805:
	mov	r3, #0
.L806:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L929+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L807
	ldr	r3, .L929+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L807:
	ldr	r3, .L929+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L809
	ldr	r3, .L929+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L809:
	ldr	r3, .L929+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L929+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L810:
	ldr	r3, .L929+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L811
	ldr	r3, .L929+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L811:
	ldr	r3, .L929+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L812
	ldr	r3, .L929+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L812:
	ldr	r3, .L929+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L813
	ldr	r3, .L929+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L813:
	ldr	r3, .L929+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L814
	ldr	r3, .L929+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L814:
	ldr	r3, .L929+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L929+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L815:
	ldr	r3, .L929+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L816
	ldr	r3, .L929+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L816:
	ldr	r3, .L929+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L817
	ldr	r3, .L929+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L817:
	ldr	r3, .L929+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L818
	ldr	r3, .L929+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L818:
	ldr	r3, .L929+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L929+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L819:
	ldr	r3, .L929+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L820
	ldr	r3, .L929+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L820:
	ldr	r3, .L929+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L929+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L821:
	ldr	r3, .L929+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L822
	ldr	r3, .L929+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L822:
	ldr	r3, .L929+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L823
	ldr	r3, .L929+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
.L823:
	ldr	r3, .L929+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L824
	ldr	r3, .L929+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L824
.L808:
	mov	r3, #1
	b	.L825
.L824:
	mov	r3, #0
.L825:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L241
.L804:
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L929+232
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L826
	ldr	r3, .L929+228
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L827
	mov	r3, #0
	mov	r4, r3
.L827:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L241
.L826:
	ldr	r3, .L929+228
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L828
	ldr	r3, .L929+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L929+228
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L929+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
.L828:
	mov	r3, #1
	b	.L830
.L241:
	mov	r3, #0
.L830:
	str	r3, [fp, #-24]
	ldr	r3, .L932
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+4
	strb	r2, [r3]
	ldr	r3, .L932+8
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+12
	strb	r2, [r3]
	ldr	r3, .L932+16
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+20
	strb	r2, [r3]
	ldr	r3, .L932+24
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+28
	strb	r2, [r3]
	ldr	r3, .L932+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+36
	str	r3, [r2]	@ float
	ldr	r3, .L932+40
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+44
	strb	r2, [r3]
	ldr	r3, .L932+48
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+52
	strb	r2, [r3]
	ldr	r3, .L932+56
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+60
	strb	r2, [r3]
	ldr	r3, .L932+64
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+68
	strb	r2, [r3]
	ldr	r3, .L932+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+76
	str	r3, [r2]	@ float
	ldr	r3, .L932+80
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+84
	strb	r2, [r3]
	ldr	r3, .L932+88
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+92
	strb	r2, [r3]
	ldr	r3, .L932+96
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+100
	strb	r2, [r3]
	ldr	r3, .L932+104
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+108
	strb	r2, [r3]
	ldr	r3, .L932+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+116
	str	r3, [r2]	@ float
	ldr	r3, .L932+120
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+124
	strb	r2, [r3]
	ldr	r3, .L932+128
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+132
	strb	r2, [r3]
	ldr	r3, .L932+136
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+140
	strb	r2, [r3]
	ldr	r3, .L932+144
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+148
	strb	r2, [r3]
	ldr	r3, .L932+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+156
	str	r3, [r2]	@ float
	ldr	r3, .L932+160
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+164
	strb	r2, [r3]
	ldr	r3, .L932+168
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+172
	strb	r2, [r3]
	ldr	r3, .L932+176
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+180
	strb	r2, [r3]
	ldr	r3, .L932+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+188
	str	r3, [r2]	@ float
	ldr	r3, .L932+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+196
	str	r3, [r2]	@ float
	ldr	r3, .L932+200
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+204
	strb	r2, [r3]
	ldr	r3, .L932+208
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+212
	strb	r2, [r3]
	ldr	r3, .L932+216
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+220
	strb	r2, [r3]
	ldr	r3, .L932+224
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+228
	strb	r2, [r3]
	ldr	r3, .L932+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+236
	str	r3, [r2]	@ float
	ldr	r3, .L932+240
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+244
	strb	r2, [r3]
	ldr	r3, .L932+248
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+252
	strb	r2, [r3]
	ldr	r3, .L932+256
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+260
	strb	r2, [r3]
	ldr	r3, .L932+264
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+268
	strb	r2, [r3]
	ldr	r3, .L932+272
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+276
	str	r3, [r2]	@ float
	ldr	r3, .L932+280
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+284
	strb	r2, [r3]
	ldr	r3, .L932+288
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+292
	strb	r2, [r3]
	ldr	r3, .L932+296
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+300
	strb	r2, [r3]
	ldr	r3, .L932+304
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+308
	strb	r2, [r3]
	ldr	r3, .L932+312
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+316
	strb	r2, [r3]
	ldr	r3, .L932+320
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+324
	strb	r2, [r3]
	ldr	r3, .L932+328
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+332
	strb	r2, [r3]
	ldr	r3, .L932+336
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+340
	strb	r2, [r3]
	ldr	r3, .L932+344
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+348
	str	r3, [r2]	@ float
	ldr	r3, .L932+352
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+356
	strb	r2, [r3]
	ldr	r3, .L932+360
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+364
	strb	r2, [r3]
	ldr	r3, .L932+368
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+372
	strb	r2, [r3]
	ldr	r3, .L932+376
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+380
	strb	r2, [r3]
	ldr	r3, .L932+384
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+388
	strb	r2, [r3]
	ldr	r3, .L932+392
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+396
	str	r3, [r2]	@ float
	ldr	r3, .L932+400
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+404
	strb	r2, [r3]
	ldr	r3, .L932+408
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+412
	str	r3, [r2]	@ float
	ldr	r3, .L932+416
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+420
	strb	r2, [r3]
	ldr	r3, .L932+424
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+428
	strb	r2, [r3]
	ldr	r3, .L932+432
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+436
	strb	r2, [r3]
	ldr	r3, .L932+440
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+444
	str	r3, [r2]	@ float
	ldr	r3, .L932+448
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+452
	strb	r2, [r3]
	ldr	r3, .L932+456
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+460
	str	r3, [r2]	@ float
	ldr	r3, .L932+464
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+468
	str	r3, [r2]	@ float
	ldr	r3, .L932+472
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+476
	strb	r2, [r3]
	ldr	r3, .L932+480
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+484
	strb	r2, [r3]
	ldr	r3, .L932+488
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+492
	strb	r2, [r3]
	ldr	r3, .L932+496
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+500
	strb	r2, [r3]
	ldr	r3, .L932+504
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+508
	strb	r2, [r3]
	ldr	r3, .L932+512
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+516
	strb	r2, [r3]
	ldr	r3, .L932+520
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+524
	str	r3, [r2]	@ float
	ldr	r3, .L932+528
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+532
	strb	r2, [r3]
	ldr	r3, .L932+536
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+540
	strb	r2, [r3]
	ldr	r3, .L932+544
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+548
	strb	r2, [r3]
	ldr	r3, .L932+552
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+556
	strb	r2, [r3]
	ldr	r3, .L932+560
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+564
	strb	r2, [r3]
	ldr	r3, .L932+568
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+572
	strb	r2, [r3]
	ldr	r3, .L932+576
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+580
	strb	r2, [r3]
	ldr	r3, .L932+584
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+588
	strb	r2, [r3]
	ldr	r3, .L932+592
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+596
	strb	r2, [r3]
	ldr	r3, .L932+600
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+604
	strb	r2, [r3]
	ldr	r3, .L932+608
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+612
	str	r3, [r2]	@ float
	ldr	r3, .L932+616
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+620
	strb	r2, [r3]
	ldr	r3, .L932+624
	ldr	r3, [r3]
	ldr	r2, .L932+628
	str	r3, [r2]
	ldr	r3, .L932+632
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+636
	strb	r2, [r3]
	ldr	r3, .L932+640
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+644
	str	r3, [r2]	@ float
	ldr	r3, .L932+648
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+652
	strb	r2, [r3]
	ldr	r3, .L932+656
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+660
	strb	r2, [r3]
	ldr	r3, .L932+664
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+668
	str	r3, [r2]	@ float
	ldr	r3, .L932+672
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+676
	strb	r2, [r3]
	ldr	r3, .L932+680
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+684
	strb	r2, [r3]
	ldr	r3, .L932+688
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+692
	strb	r2, [r3]
	ldr	r3, .L932+696
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+700
	str	r3, [r2]	@ float
	ldr	r3, .L932+704
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+708
	strb	r2, [r3]
	ldr	r3, .L932+712
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+716
	strb	r2, [r3]
	ldr	r3, .L932+720
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+724
	strb	r2, [r3]
	ldr	r3, .L932+728
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+732
	strb	r2, [r3]
	ldr	r3, .L932+736
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+740
	str	r3, [r2]	@ float
	ldr	r3, .L932+744
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+748
	strb	r2, [r3]
	ldr	r3, .L932+752
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+756
	strb	r2, [r3]
	ldr	r3, .L932+760
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+764
	strb	r2, [r3]
	ldr	r3, .L932+768
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+772
	strb	r2, [r3]
	ldr	r3, .L932+776
	ldr	r3, [r3]	@ float
	ldr	r2, .L932+780
	str	r3, [r2]	@ float
	ldr	r3, .L932+784
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L932+788
	strb	r2, [r3]
.L236:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L831
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
.L933:
	.align	2
.L932:
	.word	_x_t16_l1
	.word	t16_l1
	.word	_x_t16_l0
	.word	t16_l0
	.word	_x_t16_evt1
	.word	t16_evt1
	.word	_x_t16_evt0
	.word	t16_evt0
	.word	_x_t16_x
	.word	t16_x
	.word	_x_t15_l1
	.word	t15_l1
	.word	_x_t15_l0
	.word	t15_l0
	.word	_x_t15_evt1
	.word	t15_evt1
	.word	_x_t15_evt0
	.word	t15_evt0
	.word	_x_t15_x
	.word	t15_x
	.word	_x_t14_l1
	.word	t14_l1
	.word	_x_t14_l0
	.word	t14_l0
	.word	_x_t14_evt1
	.word	t14_evt1
	.word	_x_t14_evt0
	.word	t14_evt0
	.word	_x_t14_x
	.word	t14_x
	.word	_x_t13_l1
	.word	t13_l1
	.word	_x_t13_l0
	.word	t13_l0
	.word	_x_t13_evt1
	.word	t13_evt1
	.word	_x_t13_evt0
	.word	t13_evt0
	.word	_x_t13_x
	.word	t13_x
	.word	_x_t12_l1
	.word	t12_l1
	.word	_x_t12_l0
	.word	t12_l0
	.word	_x_t12_evt0
	.word	t12_evt0
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_t12_x
	.word	t12_x
	.word	_x_t10_l1
	.word	t10_l1
	.word	_x_t10_l0
	.word	t10_l0
	.word	_x_t10_evt1
	.word	t10_evt1
	.word	_x_t10_evt0
	.word	t10_evt0
	.word	_x_t10_x
	.word	t10_x
	.word	_x_t9_l1
	.word	t9_l1
	.word	_x_t9_l0
	.word	t9_l0
	.word	_x_t9_evt1
	.word	t9_evt1
	.word	_x_t9_evt0
	.word	t9_evt0
	.word	_x_t3_x
	.word	t3_x
	.word	_x_t2_evt1
	.word	t2_evt1
	.word	_x_t11_evt0
	.word	t11_evt0
	.word	_x_gate_evt0
	.word	gate_evt0
	.word	_x_t2_l1
	.word	t2_l1
	.word	_x_t11_l0
	.word	t11_l0
	.word	_x_gate_l0
	.word	gate_l0
	.word	_x_t3_evt0
	.word	t3_evt0
	.word	_x_t2_l0
	.word	t2_l0
	.word	_x_t2_x
	.word	t2_x
	.word	_x_t1_evt1
	.word	t1_evt1
	.word	_x_t1_l1
	.word	t1_l1
	.word	_x_t2_evt0
	.word	t2_evt0
	.word	_x_t0_l1
	.word	t0_l1
	.word	_x_t0_evt1
	.word	t0_evt1
	.word	_x_t0_x
	.word	t0_x
	.word	_x_t12_evt1
	.word	t12_evt1
	.word	_x_delta
	.word	delta
	.word	_x_t11_l1
	.word	t11_l1
	.word	_x_gate_l1
	.word	gate_l1
	.word	_x_t3_evt1
	.word	t3_evt1
	.word	_x_t4_x
	.word	t4_x
	.word	_x_t0_l0
	.word	t0_l0
	.word	_x_t11_x
	.word	t11_x
	.word	_x_gate_y
	.word	gate_y
	.word	_x_t8_l0
	.word	t8_l0
	.word	_x_t1_evt0
	.word	t1_evt0
	.word	_x_controller_l1
	.word	controller_l1
	.word	_x_t6_l0
	.word	t6_l0
	.word	_x_t5_l0
	.word	t5_l0
	.word	_x_t0_evt0
	.word	t0_evt0
	.word	_x_t1_x
	.word	t1_x
	.word	_x_controller_evt1
	.word	controller_evt1
	.word	_x_t5_l1
	.word	t5_l1
	.word	_x_t6_evt0
	.word	t6_evt0
	.word	_x_t11_evt1
	.word	t11_evt1
	.word	_x_gate_evt1
	.word	gate_evt1
	.word	_x_t3_l1
	.word	t3_l1
	.word	_x_t4_evt0
	.word	t4_evt0
	.word	_x_controller_evt2
	.word	controller_evt2
	.word	_x_controller_evt0
	.word	controller_evt0
	.word	_x_t6_evt1
	.word	t6_evt1
	.word	_x_t7_x
	.word	t7_x
	.word	_x_t1_l0
	.word	t1_l0
	.word	_x_controller_cnt
	.word	controller_cnt
	.word	_x_t4_evt1
	.word	t4_evt1
	.word	_x_t5_x
	.word	t5_x
	.word	_x_t3_l0
	.word	t3_l0
	.word	_x_t4_l0
	.word	t4_l0
	.word	_x_controller_z
	.word	controller_z
	.word	_x_t4_l1
	.word	t4_l1
	.word	_x_t5_evt0
	.word	t5_evt0
	.word	_x_t5_evt1
	.word	t5_evt1
	.word	_x_t6_x
	.word	t6_x
	.word	_x_controller_l0
	.word	controller_l0
	.word	_x_t6_l1
	.word	t6_l1
	.word	_x_t7_evt0
	.word	t7_evt0
	.word	_x_t7_evt1
	.word	t7_evt1
	.word	_x_t8_x
	.word	t8_x
	.word	_x_t7_l0
	.word	t7_l0
	.word	_x_t7_l1
	.word	t7_l1
	.word	_x_t8_evt0
	.word	t8_evt0
	.word	_x_t8_evt1
	.word	t8_evt1
	.word	_x_t9_x
	.word	t9_x
	.word	_x_t8_l1
	.word	t8_l1
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
