	.file	"392008.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	_diverge_delta
	.bss
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	s2_l1
	.type	s2_l1, @object
	.size	s2_l1, 1
s2_l1:
	.zero	1
	.globl	_x_s2_l1
	.type	_x_s2_l1, @object
	.size	_x_s2_l1, 1
_x_s2_l1:
	.zero	1
	.globl	s2_l0
	.type	s2_l0, @object
	.size	s2_l0, 1
s2_l0:
	.zero	1
	.globl	_x_s2_l0
	.type	_x_s2_l0, @object
	.size	_x_s2_l0, 1
_x_s2_l0:
	.zero	1
	.globl	s2_evt2
	.type	s2_evt2, @object
	.size	s2_evt2, 1
s2_evt2:
	.zero	1
	.globl	_x_s2_evt2
	.type	_x_s2_evt2, @object
	.size	_x_s2_evt2, 1
_x_s2_evt2:
	.zero	1
	.globl	s0_evt0
	.type	s0_evt0, @object
	.size	s0_evt0, 1
s0_evt0:
	.zero	1
	.globl	_x_s0_evt0
	.type	_x_s0_evt0, @object
	.size	_x_s0_evt0, 1
_x_s0_evt0:
	.zero	1
	.globl	bus_l1
	.type	bus_l1, @object
	.size	bus_l1, 1
bus_l1:
	.zero	1
	.globl	_x_bus_l1
	.type	_x_bus_l1, @object
	.size	_x_bus_l1, 1
_x_bus_l1:
	.zero	1
	.globl	bus_evt2
	.type	bus_evt2, @object
	.size	bus_evt2, 1
bus_evt2:
	.zero	1
	.globl	_x_bus_evt2
	.type	_x_bus_evt2, @object
	.size	_x_bus_evt2, 1
_x_bus_evt2:
	.zero	1
	.globl	s0_backoff
	.align 4
	.type	s0_backoff, @object
	.size	s0_backoff, 4
s0_backoff:
	.zero	4
	.globl	_x_s0_backoff
	.align 4
	.type	_x_s0_backoff, @object
	.size	_x_s0_backoff, 4
_x_s0_backoff:
	.zero	4
	.globl	s0_lambda
	.align 4
	.type	s0_lambda, @object
	.size	s0_lambda, 4
s0_lambda:
	.zero	4
	.globl	_x_s0_lambda
	.align 4
	.type	_x_s0_lambda, @object
	.size	_x_s0_lambda, 4
_x_s0_lambda:
	.zero	4
	.globl	s1_evt0
	.type	s1_evt0, @object
	.size	s1_evt0, 1
s1_evt0:
	.zero	1
	.globl	_x_s1_evt0
	.type	_x_s1_evt0, @object
	.size	_x_s1_evt0, 1
_x_s1_evt0:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	s2_evt1
	.type	s2_evt1, @object
	.size	s2_evt1, 1
s2_evt1:
	.zero	1
	.globl	_x_s2_evt1
	.type	_x_s2_evt1, @object
	.size	_x_s2_evt1, 1
_x_s2_evt1:
	.zero	1
	.globl	bus_x
	.align 4
	.type	bus_x, @object
	.size	bus_x, 4
bus_x:
	.zero	4
	.globl	_x_bus_x
	.align 4
	.type	_x_bus_x, @object
	.size	_x_bus_x, 4
_x_bus_x:
	.zero	4
	.globl	s1_lambda
	.align 4
	.type	s1_lambda, @object
	.size	s1_lambda, 4
s1_lambda:
	.zero	4
	.globl	_x_s1_lambda
	.align 4
	.type	_x_s1_lambda, @object
	.size	_x_s1_lambda, 4
_x_s1_lambda:
	.zero	4
	.globl	s0_x
	.align 4
	.type	s0_x, @object
	.size	s0_x, 4
s0_x:
	.zero	4
	.globl	_x_s0_x
	.align 4
	.type	_x_s0_x, @object
	.size	_x_s0_x, 4
_x_s0_x:
	.zero	4
	.globl	s2_evt0
	.type	s2_evt0, @object
	.size	s2_evt0, 1
s2_evt0:
	.zero	1
	.globl	_x_s2_evt0
	.type	_x_s2_evt0, @object
	.size	_x_s2_evt0, 1
_x_s2_evt0:
	.zero	1
	.globl	bus_j
	.align 4
	.type	bus_j, @object
	.size	bus_j, 4
bus_j:
	.zero	4
	.globl	_x_bus_j
	.align 4
	.type	_x_bus_j, @object
	.size	_x_bus_j, 4
_x_bus_j:
	.zero	4
	.globl	s1_x
	.align 4
	.type	s1_x, @object
	.size	s1_x, 4
s1_x:
	.zero	4
	.globl	_x_s1_x
	.align 4
	.type	_x_s1_x, @object
	.size	_x_s1_x, 4
_x_s1_x:
	.zero	4
	.globl	s0_evt1
	.type	s0_evt1, @object
	.size	s0_evt1, 1
s0_evt1:
	.zero	1
	.globl	_x_s0_evt1
	.type	_x_s0_evt1, @object
	.size	_x_s0_evt1, 1
_x_s0_evt1:
	.zero	1
	.globl	s0_evt2
	.type	s0_evt2, @object
	.size	s0_evt2, 1
s0_evt2:
	.zero	1
	.globl	_x_s0_evt2
	.type	_x_s0_evt2, @object
	.size	_x_s0_evt2, 1
_x_s0_evt2:
	.zero	1
	.globl	s0_l0
	.type	s0_l0, @object
	.size	s0_l0, 1
s0_l0:
	.zero	1
	.globl	_x_s0_l0
	.type	_x_s0_l0, @object
	.size	_x_s0_l0, 1
_x_s0_l0:
	.zero	1
	.globl	s2_lambda
	.align 4
	.type	s2_lambda, @object
	.size	s2_lambda, 4
s2_lambda:
	.zero	4
	.globl	_x_s2_lambda
	.align 4
	.type	_x_s2_lambda, @object
	.size	_x_s2_lambda, 4
_x_s2_lambda:
	.zero	4
	.globl	s0_l1
	.type	s0_l1, @object
	.size	s0_l1, 1
s0_l1:
	.zero	1
	.globl	_x_s0_l1
	.type	_x_s0_l1, @object
	.size	_x_s0_l1, 1
_x_s0_l1:
	.zero	1
	.globl	s2_backoff
	.align 4
	.type	s2_backoff, @object
	.size	s2_backoff, 4
s2_backoff:
	.zero	4
	.globl	_x_s2_backoff
	.align 4
	.type	_x_s2_backoff, @object
	.size	_x_s2_backoff, 4
_x_s2_backoff:
	.zero	4
	.globl	bus_cd_id
	.align 4
	.type	bus_cd_id, @object
	.size	bus_cd_id, 4
bus_cd_id:
	.zero	4
	.globl	_x_bus_cd_id
	.align 4
	.type	_x_bus_cd_id, @object
	.size	_x_bus_cd_id, 4
_x_bus_cd_id:
	.zero	4
	.globl	s1_backoff
	.align 4
	.type	s1_backoff, @object
	.size	s1_backoff, 4
s1_backoff:
	.zero	4
	.globl	_x_s1_backoff
	.align 4
	.type	_x_s1_backoff, @object
	.size	_x_s1_backoff, 4
_x_s1_backoff:
	.zero	4
	.globl	bus_evt0
	.type	bus_evt0, @object
	.size	bus_evt0, 1
bus_evt0:
	.zero	1
	.globl	_x_bus_evt0
	.type	_x_bus_evt0, @object
	.size	_x_bus_evt0, 1
_x_bus_evt0:
	.zero	1
	.globl	s1_evt1
	.type	s1_evt1, @object
	.size	s1_evt1, 1
s1_evt1:
	.zero	1
	.globl	_x_s1_evt1
	.type	_x_s1_evt1, @object
	.size	_x_s1_evt1, 1
_x_s1_evt1:
	.zero	1
	.globl	bus_evt1
	.type	bus_evt1, @object
	.size	bus_evt1, 1
bus_evt1:
	.zero	1
	.globl	_x_bus_evt1
	.type	_x_bus_evt1, @object
	.size	_x_bus_evt1, 1
_x_bus_evt1:
	.zero	1
	.globl	s1_evt2
	.type	s1_evt2, @object
	.size	s1_evt2, 1
s1_evt2:
	.zero	1
	.globl	_x_s1_evt2
	.type	_x_s1_evt2, @object
	.size	_x_s1_evt2, 1
_x_s1_evt2:
	.zero	1
	.globl	s1_l0
	.type	s1_l0, @object
	.size	s1_l0, 1
s1_l0:
	.zero	1
	.globl	_x_s1_l0
	.type	_x_s1_l0, @object
	.size	_x_s1_l0, 1
_x_s1_l0:
	.zero	1
	.globl	bus_l0
	.type	bus_l0, @object
	.size	bus_l0, 1
bus_l0:
	.zero	1
	.globl	_x_bus_l0
	.type	_x_bus_l0, @object
	.size	_x_bus_l0, 1
_x_bus_l0:
	.zero	1
	.globl	s1_l1
	.type	s1_l1, @object
	.size	s1_l1, 1
s1_l1:
	.zero	1
	.globl	_x_s1_l1
	.type	_x_s1_l1, @object
	.size	_x_s1_l1, 1
_x_s1_l1:
	.zero	1
	.globl	s2_x
	.align 4
	.type	s2_x, @object
	.size	s2_x, 4
s2_x:
	.zero	4
	.globl	_x_s2_x
	.align 4
	.type	_x_s2_x, @object
	.size	_x_s2_x, 4
_x_s2_x:
	.zero	4
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR bus_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s2_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR bus_j[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s0_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_backoff[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR bus_cd_id[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s1_backoff[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR bus_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR s1_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR s2_x[rip], eax
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L6
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L6
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L7
.L6:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L8
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L7
.L8:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L9
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L9
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L7
.L9:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L10
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L10
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L7
.L10:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L4
.L7:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L11
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L12
.L11:
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L13
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L12
.L13:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L4
.L12:
	movss	xmm0, DWORD PTR s2_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s2_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s2_x[rip]
	movss	xmm0, DWORD PTR s2_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L15
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L4
.L15:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L17
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L17
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L18
.L17:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L19
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L19
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L18
.L19:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L20
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L20
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L18
.L20:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L21
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L18
.L21:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L4
.L18:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L22
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L23
.L22:
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L24
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L23
.L24:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L4
.L23:
	movss	xmm0, DWORD PTR s1_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s1_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s1_x[rip]
	movss	xmm0, DWORD PTR s1_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L26
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L26
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L4
.L26:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L4
	movss	xmm0, DWORD PTR s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L28
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L29
.L28:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L30
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L29
.L30:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L31
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L31
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L29
.L31:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L32
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L29
.L32:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L4
.L29:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L33
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L34
.L33:
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L35
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L34
.L35:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L4
.L34:
	movss	xmm0, DWORD PTR s0_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L4
	movss	xmm1, DWORD PTR s0_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR s0_x[rip]
	movss	xmm0, DWORD PTR s0_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L37
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L37
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L4
.L37:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L38
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L39
.L38:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L40
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L40
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L39
.L40:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L41
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L41
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L39
.L41:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L42
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L42
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L39
.L42:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L4
.L39:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L43
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L44
.L43:
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L45
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L44
.L45:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L44
.L46:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L4
.L44:
	mov	eax, DWORD PTR bus_j[rip]
	test	eax, eax
	jne	.L4
	movss	xmm0, DWORD PTR bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L48
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L48
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L4
.L48:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L329
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L49
.L329:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L4
.L49:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L53
.L4:
	mov	eax, 0
.L53:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L54
.L320:
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_evt2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_backoff[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_evt0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_evt1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_bus_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_lambda[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s0_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s2_evt0[rip], al
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_bus_j[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_lambda[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s0_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_backoff[rip], eax
	call	__VERIFIER_nondet_int@PLT
	mov	DWORD PTR _x_bus_cd_id[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s1_backoff[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_evt0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_evt1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_evt2[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_bus_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_s1_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_s2_x[rip], eax
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	jne	.L55
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	je	.L55
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L56
.L55:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	jne	.L57
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L56
.L57:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	je	.L58
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	jne	.L58
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L56
.L58:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	jne	.L59
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L59
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	je	.L56
.L59:
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	test	al, al
	jne	.L60
.L56:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L62
.L61:
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L63
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L62
.L63:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L60
.L62:
	movss	xmm0, DWORD PTR _x_s2_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L60
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L60
	movss	xmm1, DWORD PTR _x_s2_x[rip]
	movss	xmm0, DWORD PTR _x_s2_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L65
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L65
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L60
.L65:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L66
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L66
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L66
	ucomiss	xmm0, xmm1
	jne	.L66
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L66
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L66
	movss	xmm0, DWORD PTR s2_backoff[rip]
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L66
	ucomiss	xmm0, xmm1
	je	.L69
.L66:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L60
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L69
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L69
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L60
.L69:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L72
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L73
.L72:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L74
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L73
.L74:
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L75
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L75
.L73:
	movss	xmm0, DWORD PTR s2_backoff[rip]
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L75
	ucomiss	xmm0, xmm1
	jne	.L75
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L75
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L77
.L75:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L77
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L77
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L77
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L77
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L77:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L79
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L79
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L79
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L79
	ucomiss	xmm0, xmm1
	je	.L80
.L79:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L80
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L80
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L80
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L80
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L80
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L80
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L80:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L82
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L83
.L82:
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L83
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L83
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L83
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L83
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L83
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L83
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L83:
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L84
	ucomiss	xmm0, xmm1
	jne	.L84
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L86
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L86
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L87
.L86:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L84
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L87
.L84:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L87
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L87
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L87
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L87
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L87
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L87
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L87:
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L88
	ucomiss	xmm0, xmm1
	jne	.L88
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L88
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L88
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L91
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L92
.L91:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L92
.L88:
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L92
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L92
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L92
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L92:
	movss	xmm1, DWORD PTR s2_lambda[rip]
	movss	xmm0, DWORD PTR s2_x[rip]
	comiss	xmm0, xmm1
	jb	.L93
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L93
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L93
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L93
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	movss	xmm0, DWORD PTR s2_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L95
.L93:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L95
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L95
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L95
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L95
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L95
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L95
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L95:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L96
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L96
	movss	xmm0, DWORD PTR s2_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L97
.L96:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L97
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	je	.L97
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	jne	.L97
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L97
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L97
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L97:
	movss	xmm0, DWORD PTR s2_lambda[rip]
	movss	xmm1, DWORD PTR _x_s2_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L98
	ucomiss	xmm0, xmm1
	jne	.L98
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L100
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L101
.L100:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L98
.L101:
	movss	xmm0, DWORD PTR s2_backoff[rip]
	movss	xmm1, DWORD PTR _x_s2_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L98
	ucomiss	xmm0, xmm1
	jne	.L98
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L98
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L103
.L98:
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L103
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L103
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L103
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L103
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L103:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L105
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L106
.L105:
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	je	.L106
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	jne	.L106
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L106
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L106
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L106
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L106
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L106:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L107
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L107
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L107
	movss	xmm1, DWORD PTR s2_backoff[rip]
	movss	xmm0, DWORD PTR s2_x[rip]
	comiss	xmm0, xmm1
	jnb	.L108
.L107:
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	test	al, al
	jne	.L108
	movzx	eax, BYTE PTR s2_l0[rip]
	test	al, al
	je	.L108
	movzx	eax, BYTE PTR s2_l1[rip]
	test	al, al
	jne	.L108
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L108
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L108
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L60
.L108:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	jne	.L109
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L110
.L109:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	jne	.L111
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	jne	.L111
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L110
.L111:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	je	.L112
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	jne	.L112
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L110
.L112:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	jne	.L113
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L113
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	je	.L110
.L113:
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	test	al, al
	jne	.L60
.L110:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L114
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L115
.L114:
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L115
.L116:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L60
.L115:
	movss	xmm0, DWORD PTR _x_s1_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L60
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L60
	movss	xmm1, DWORD PTR _x_s1_x[rip]
	movss	xmm0, DWORD PTR _x_s1_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L118
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L118
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L60
.L118:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L119
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L119
	ucomiss	xmm0, xmm1
	jne	.L119
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L119
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L119
	movss	xmm0, DWORD PTR s1_backoff[rip]
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L119
	ucomiss	xmm0, xmm1
	je	.L122
.L119:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L60
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L122
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L60
.L122:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L125
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L126
.L125:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L127
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L126
.L127:
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L128
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L128
.L126:
	movss	xmm0, DWORD PTR s1_backoff[rip]
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L128
	ucomiss	xmm0, xmm1
	jne	.L128
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L128
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L130
.L128:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L130
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L130
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L130
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L130
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L130:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L132
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L132
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L132
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L132
	ucomiss	xmm0, xmm1
	je	.L133
.L132:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L133
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L133
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L133
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L133
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L133:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L135
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L135
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L136
.L135:
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L136
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L136
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L136
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L136
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L136
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L136
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L136:
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L137
	ucomiss	xmm0, xmm1
	jne	.L137
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L139
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L139
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L140
.L139:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L137
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L137
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L140
.L137:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L140
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L140
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L140
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L140
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L140:
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L141
	ucomiss	xmm0, xmm1
	jne	.L141
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L141
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L141
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L144
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L145
.L144:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L145
.L141:
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L145
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L145
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L145
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L145
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L145:
	movss	xmm1, DWORD PTR s1_lambda[rip]
	movss	xmm0, DWORD PTR s1_x[rip]
	comiss	xmm0, xmm1
	jb	.L146
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L146
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L146
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L146
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	movss	xmm0, DWORD PTR s1_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L148
.L146:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L148
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L148
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L148
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L148
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L148
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L148:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L149
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L149
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L149
	movss	xmm0, DWORD PTR s1_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L150
.L149:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L150
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L150
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	je	.L150
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	jne	.L150
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L150
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L150
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L150:
	movss	xmm0, DWORD PTR s1_lambda[rip]
	movss	xmm1, DWORD PTR _x_s1_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L151
	ucomiss	xmm0, xmm1
	jne	.L151
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L153
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L154
.L153:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L151
.L154:
	movss	xmm0, DWORD PTR s1_backoff[rip]
	movss	xmm1, DWORD PTR _x_s1_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L151
	ucomiss	xmm0, xmm1
	jne	.L151
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L151
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L156
.L151:
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L156
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L156
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L156
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L156
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L156:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L158
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L159
.L158:
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L159
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L159
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L159
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L159
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L159:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L160
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L160
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L160
	movss	xmm1, DWORD PTR s1_backoff[rip]
	movss	xmm0, DWORD PTR s1_x[rip]
	comiss	xmm0, xmm1
	jnb	.L161
.L160:
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	test	al, al
	jne	.L161
	movzx	eax, BYTE PTR s1_l0[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR s1_l1[rip]
	test	al, al
	jne	.L161
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L161
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L161
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L60
.L161:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	jne	.L162
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L163
.L162:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	jne	.L164
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	jne	.L164
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L163
.L164:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	jne	.L165
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L163
.L165:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L166
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	je	.L163
.L166:
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	test	al, al
	jne	.L60
.L163:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L167
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L168
.L167:
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L168
.L169:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L60
.L168:
	movss	xmm0, DWORD PTR _x_s0_backoff[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L60
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L60
	movss	xmm1, DWORD PTR _x_s0_x[rip]
	movss	xmm0, DWORD PTR _x_s0_lambda[rip]
	comiss	xmm0, xmm1
	jnb	.L171
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L171
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L60
.L171:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L172
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L172
	ucomiss	xmm0, xmm1
	jne	.L172
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR s0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_s0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L172
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L172
	movss	xmm0, DWORD PTR s0_backoff[rip]
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L172
	ucomiss	xmm0, xmm1
	je	.L175
.L172:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L60
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L175
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L175
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L60
.L175:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L178
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L179
.L178:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L179
.L180:
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L181
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L181
.L179:
	movss	xmm0, DWORD PTR s0_backoff[rip]
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L181
	ucomiss	xmm0, xmm1
	jne	.L181
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L181
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L183
.L181:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L183
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L183
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L183
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L183
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L183:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L185
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L185
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L185
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L185
	ucomiss	xmm0, xmm1
	je	.L186
.L185:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L186
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L186
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L186
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L186
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L186:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L188
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L188
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L189
.L188:
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L189
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L189
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L189
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L189
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L189
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L189:
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L190
	ucomiss	xmm0, xmm1
	jne	.L190
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L193
.L192:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L193
.L190:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L193
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L193
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L193
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L193:
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L194
	ucomiss	xmm0, xmm1
	jne	.L194
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L194
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L194
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L197
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L198
.L197:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L198
.L194:
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L198
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L198
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L198
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L198
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L198:
	movss	xmm1, DWORD PTR s0_lambda[rip]
	movss	xmm0, DWORD PTR s0_x[rip]
	comiss	xmm0, xmm1
	jb	.L199
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L199
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L199
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L199
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	movss	xmm0, DWORD PTR s0_backoff[rip]
	comiss	xmm0, xmm1
	jnb	.L201
.L199:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L201
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L201
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L201
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L201:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L202
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L202
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L202
	movss	xmm0, DWORD PTR s0_backoff[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	pxor	xmm2, xmm2
	cvtss2sd	xmm2, xmm1
	movapd	xmm1, xmm0
	subsd	xmm1, xmm2
	movsd	xmm0, QWORD PTR .LC3[rip]
	comisd	xmm0, xmm1
	jnb	.L203
.L202:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	jne	.L203
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L203
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L203
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L203:
	movss	xmm0, DWORD PTR s0_lambda[rip]
	movss	xmm1, DWORD PTR _x_s0_lambda[rip]
	ucomiss	xmm0, xmm1
	jp	.L204
	ucomiss	xmm0, xmm1
	jne	.L204
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L206
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L207
.L206:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L204
.L207:
	movss	xmm0, DWORD PTR s0_backoff[rip]
	movss	xmm1, DWORD PTR _x_s0_backoff[rip]
	ucomiss	xmm0, xmm1
	jp	.L204
	ucomiss	xmm0, xmm1
	jne	.L204
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L204
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L209
.L204:
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L209
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L209
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L209
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L209
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L209:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L212
.L211:
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	jne	.L212
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L212
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L212
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L212
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L212:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L213
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L213
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L213
	movss	xmm1, DWORD PTR s0_backoff[rip]
	movss	xmm0, DWORD PTR s0_x[rip]
	comiss	xmm0, xmm1
	jnb	.L214
.L213:
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR s0_l0[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR s0_l1[rip]
	test	al, al
	jne	.L214
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L214
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L214
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L60
.L214:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	jne	.L215
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	jne	.L215
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	je	.L216
.L215:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	je	.L216
.L217:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	jne	.L218
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	je	.L218
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	je	.L216
.L218:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	je	.L216
.L219:
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	test	al, al
	jne	.L60
.L216:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L220
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L221
.L220:
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L221
.L222:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L223
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L221
.L223:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L60
.L221:
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L60
.L224:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L365
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L225
.L365:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	jne	.L60
.L225:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L227
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR bus_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_bus_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L60
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L60
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L60
	mov	edx, DWORD PTR bus_j[rip]
	mov	eax, DWORD PTR _x_bus_j[rip]
	cmp	edx, eax
	jne	.L60
.L227:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR bus_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_bus_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L229
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L229
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L229
	mov	edx, DWORD PTR bus_j[rip]
	mov	eax, DWORD PTR _x_bus_j[rip]
	cmp	edx, eax
	je	.L231
.L229:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L231
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L231
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L60
.L231:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L232
	mov	edx, DWORD PTR bus_j[rip]
	mov	eax, DWORD PTR _x_bus_j[rip]
	cmp	edx, eax
	jne	.L232
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L232
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L233
.L232:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L233
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L233
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L233
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L233
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L60
.L233:
	mov	edx, DWORD PTR bus_j[rip]
	mov	eax, DWORD PTR _x_bus_j[rip]
	cmp	edx, eax
	jne	.L235
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L237
.L236:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L238
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L237
.L238:
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L237
.L235:
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L237
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L237
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L237
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L60
.L237:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L239
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L239
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L239
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L239
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L240
.L239:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L240
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L240
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L242
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L242
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L240
.L242:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L240
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	jne	.L240
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L240
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L60
.L240:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L243
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L243
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L243
	movss	xmm0, DWORD PTR bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	jb	.L243
	movss	xmm0, DWORD PTR bus_x[rip]
	movss	xmm1, DWORD PTR _x_bus_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L243
	ucomiss	xmm0, xmm1
	je	.L245
.L243:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L245
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L245
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L247
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L247
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L245
.L247:
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L245
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L245
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L60
.L245:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L248
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L248
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L248
	movss	xmm0, DWORD PTR bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L248
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L248
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L249
.L248:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L249
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L249
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L251
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L251
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L249
.L251:
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	jne	.L249
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L249
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L60
.L249:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L252
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	je	.L252
	movss	xmm0, DWORD PTR bus_x[rip]
	comiss	xmm0, DWORD PTR .LC1[rip]
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L252
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L252
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L252
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L252
	mov	edx, DWORD PTR bus_cd_id[rip]
	mov	eax, DWORD PTR bus_j[rip]
	cmp	edx, eax
	jne	.L252
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L252
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L252
	mov	eax, DWORD PTR bus_j[rip]
	mov	edx, DWORD PTR _x_bus_j[rip]
	sub	eax, edx
	cmp	eax, -1
	je	.L254
.L252:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L254
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L254
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L254
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L254
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L60
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L60
.L254:
	mov	eax, DWORD PTR bus_j[rip]
	mov	edx, DWORD PTR _x_bus_j[rip]
	sub	eax, edx
	cmp	eax, -1
	jne	.L255
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L255
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L255
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L255
	mov	edx, DWORD PTR bus_cd_id[rip]
	mov	eax, DWORD PTR bus_j[rip]
	cmp	edx, eax
	jne	.L255
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L255
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L255
	mov	eax, DWORD PTR bus_j[rip]
	cmp	eax, 1
	jle	.L257
.L255:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L257
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L257
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L258
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L258
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L257
.L258:
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	je	.L257
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	jne	.L60
.L257:
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L259
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L259
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L259
	mov	eax, DWORD PTR bus_j[rip]
	cmp	eax, 2
	jne	.L259
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L259
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L259
	mov	edx, DWORD PTR bus_cd_id[rip]
	mov	eax, DWORD PTR bus_j[rip]
	cmp	edx, eax
	jne	.L259
	mov	eax, DWORD PTR _x_bus_j[rip]
	test	eax, eax
	je	.L261
.L259:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L261
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L261
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L262
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L262
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L261
.L262:
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	test	al, al
	jne	.L261
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	test	al, al
	jne	.L261
	movzx	eax, BYTE PTR bus_l0[rip]
	test	al, al
	je	.L261
	movzx	eax, BYTE PTR bus_l1[rip]
	test	al, al
	jne	.L60
.L261:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L60
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L264
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L264
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L265
.L264:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L266
.L265:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L267
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L267
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L268
.L267:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L266
.L268:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L269
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L269
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L270
.L269:
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L266
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L270
.L266:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L270
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L60
.L270:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L272
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L272
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L272
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L60
.L272:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L273
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L273
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L274
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L274
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L274
	mov	eax, 1
	jmp	.L275
.L274:
	mov	eax, 0
.L275:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L276
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	jne	.L276
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L277
.L276:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L278
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	jne	.L278
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L277
.L278:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L279
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L279
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L279
.L277:
	mov	eax, 1
	jmp	.L280
.L279:
	mov	eax, 0
.L280:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L281
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L281
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L281
	mov	eax, 1
	jmp	.L282
.L281:
	mov	eax, 0
.L282:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L283
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L283
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L284
.L283:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L285
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L285
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L284
.L285:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L286
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L286
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L286
.L284:
	mov	eax, 1
	jmp	.L287
.L286:
	mov	eax, 0
.L287:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	je	.L288
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	je	.L288
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	jne	.L288
	mov	eax, 1
	jmp	.L289
.L288:
	mov	eax, 0
.L289:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L290
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L291
.L290:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L292
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L291
.L292:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	je	.L293
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	jne	.L293
.L291:
	mov	eax, 1
	jmp	.L294
.L293:
	mov	eax, 0
.L294:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L295
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L295
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L295
	mov	eax, 1
	jmp	.L296
.L295:
	mov	eax, 0
.L296:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L297
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L297
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	je	.L298
.L297:
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L299
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	je	.L298
.L299:
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L300
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L300
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L300
.L298:
	mov	eax, 1
	jmp	.L301
.L300:
	mov	eax, 0
.L301:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L60
.L273:
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L302
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jne	.L302
	movzx	eax, BYTE PTR s0_evt2[rip]
	test	al, al
	jne	.L303
	movzx	eax, BYTE PTR s0_evt0[rip]
	test	al, al
	je	.L303
	movzx	eax, BYTE PTR s0_evt1[rip]
	test	al, al
	jne	.L303
	mov	eax, 1
	jmp	.L304
.L303:
	mov	eax, 0
.L304:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L305
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L305
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L305
	mov	eax, DWORD PTR bus_cd_id[rip]
	test	eax, eax
	jne	.L305
	mov	eax, 1
	jmp	.L306
.L305:
	mov	eax, 0
.L306:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR s1_evt2[rip]
	test	al, al
	jne	.L307
	movzx	eax, BYTE PTR s1_evt0[rip]
	test	al, al
	je	.L307
	movzx	eax, BYTE PTR s1_evt1[rip]
	test	al, al
	jne	.L307
	mov	eax, 1
	jmp	.L308
.L307:
	mov	eax, 0
.L308:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L309
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L309
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 1
	jne	.L309
	mov	eax, 1
	jmp	.L310
.L309:
	mov	eax, 0
.L310:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR s2_evt2[rip]
	test	al, al
	jne	.L311
	movzx	eax, BYTE PTR s2_evt0[rip]
	test	al, al
	je	.L311
	movzx	eax, BYTE PTR s2_evt1[rip]
	test	al, al
	jne	.L311
	mov	eax, 1
	jmp	.L312
.L311:
	mov	eax, 0
.L312:
	and	eax, 1
	xor	eax, 1
	mov	edx, eax
	movzx	eax, BYTE PTR bus_evt2[rip]
	test	al, al
	jne	.L313
	movzx	eax, BYTE PTR bus_evt0[rip]
	test	al, al
	je	.L313
	movzx	eax, BYTE PTR bus_evt1[rip]
	test	al, al
	jne	.L313
	mov	eax, DWORD PTR bus_cd_id[rip]
	cmp	eax, 2
	jne	.L313
	mov	eax, 1
	jmp	.L314
.L313:
	mov	eax, 0
.L314:
	and	eax, 1
	xor	eax, edx
	test	al, al
	je	.L60
.L302:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L373
	ucomiss	xmm0, xmm1
	je	.L315
.L373:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L60
.L315:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC4[rip]
	comiss	xmm0, xmm1
	jnb	.L317
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L60
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L60
.L317:
	mov	eax, 1
	jmp	.L319
.L60:
	mov	eax, 0
.L319:
	mov	DWORD PTR -4[rbp], eax
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movzx	eax, BYTE PTR _x_s2_l1[rip]
	mov	BYTE PTR s2_l1[rip], al
	movzx	eax, BYTE PTR _x_s2_l0[rip]
	mov	BYTE PTR s2_l0[rip], al
	movzx	eax, BYTE PTR _x_s2_evt2[rip]
	mov	BYTE PTR s2_evt2[rip], al
	movzx	eax, BYTE PTR _x_s0_evt0[rip]
	mov	BYTE PTR s0_evt0[rip], al
	movzx	eax, BYTE PTR _x_bus_l1[rip]
	mov	BYTE PTR bus_l1[rip], al
	movzx	eax, BYTE PTR _x_bus_evt2[rip]
	mov	BYTE PTR bus_evt2[rip], al
	movss	xmm0, DWORD PTR _x_s0_backoff[rip]
	movss	DWORD PTR s0_backoff[rip], xmm0
	movss	xmm0, DWORD PTR _x_s0_lambda[rip]
	movss	DWORD PTR s0_lambda[rip], xmm0
	movzx	eax, BYTE PTR _x_s1_evt0[rip]
	mov	BYTE PTR s1_evt0[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_s2_evt1[rip]
	mov	BYTE PTR s2_evt1[rip], al
	movss	xmm0, DWORD PTR _x_bus_x[rip]
	movss	DWORD PTR bus_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_s1_lambda[rip]
	movss	DWORD PTR s1_lambda[rip], xmm0
	movss	xmm0, DWORD PTR _x_s0_x[rip]
	movss	DWORD PTR s0_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s2_evt0[rip]
	mov	BYTE PTR s2_evt0[rip], al
	mov	eax, DWORD PTR _x_bus_j[rip]
	mov	DWORD PTR bus_j[rip], eax
	movss	xmm0, DWORD PTR _x_s1_x[rip]
	movss	DWORD PTR s1_x[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_evt1[rip]
	mov	BYTE PTR s0_evt1[rip], al
	movzx	eax, BYTE PTR _x_s0_evt2[rip]
	mov	BYTE PTR s0_evt2[rip], al
	movzx	eax, BYTE PTR _x_s0_l0[rip]
	mov	BYTE PTR s0_l0[rip], al
	movss	xmm0, DWORD PTR _x_s2_lambda[rip]
	movss	DWORD PTR s2_lambda[rip], xmm0
	movzx	eax, BYTE PTR _x_s0_l1[rip]
	mov	BYTE PTR s0_l1[rip], al
	movss	xmm0, DWORD PTR _x_s2_backoff[rip]
	movss	DWORD PTR s2_backoff[rip], xmm0
	mov	eax, DWORD PTR _x_bus_cd_id[rip]
	mov	DWORD PTR bus_cd_id[rip], eax
	movss	xmm0, DWORD PTR _x_s1_backoff[rip]
	movss	DWORD PTR s1_backoff[rip], xmm0
	movzx	eax, BYTE PTR _x_bus_evt0[rip]
	mov	BYTE PTR bus_evt0[rip], al
	movzx	eax, BYTE PTR _x_s1_evt1[rip]
	mov	BYTE PTR s1_evt1[rip], al
	movzx	eax, BYTE PTR _x_bus_evt1[rip]
	mov	BYTE PTR bus_evt1[rip], al
	movzx	eax, BYTE PTR _x_s1_evt2[rip]
	mov	BYTE PTR s1_evt2[rip], al
	movzx	eax, BYTE PTR _x_s1_l0[rip]
	mov	BYTE PTR s1_l0[rip], al
	movzx	eax, BYTE PTR _x_bus_l0[rip]
	mov	BYTE PTR bus_l0[rip], al
	movzx	eax, BYTE PTR _x_s1_l1[rip]
	mov	BYTE PTR s1_l1[rip], al
	movss	xmm0, DWORD PTR _x_s2_x[rip]
	movss	DWORD PTR s2_x[rip], xmm0
.L54:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L320
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC1:
	.long	1095761920
	.align 8
.LC3:
	.long	0
	.long	-1074790400
	.align 4
.LC4:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"392008.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	s2_l1,1,1
	.comm	_x_s2_l1,1,1
	.comm	s2_l0,1,1
	.comm	_x_s2_l0,1,1
	.comm	s2_evt2,1,1
	.comm	_x_s2_evt2,1,1
	.comm	s0_evt0,1,1
	.comm	_x_s0_evt0,1,1
	.comm	bus_l1,1,1
	.comm	_x_bus_l1,1,1
	.comm	bus_evt2,1,1
	.comm	_x_bus_evt2,1,1
	.comm	s0_backoff,4,4
	.comm	_x_s0_backoff,4,4
	.comm	s0_lambda,4,4
	.comm	_x_s0_lambda,4,4
	.comm	s1_evt0,1,1
	.comm	_x_s1_evt0,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	s2_evt1,1,1
	.comm	_x_s2_evt1,1,1
	.comm	bus_x,4,4
	.comm	_x_bus_x,4,4
	.comm	s1_lambda,4,4
	.comm	_x_s1_lambda,4,4
	.comm	s0_x,4,4
	.comm	_x_s0_x,4,4
	.comm	s2_evt0,1,1
	.comm	_x_s2_evt0,1,1
	.comm	bus_j,4,4
	.comm	_x_bus_j,4,4
	.comm	s1_x,4,4
	.comm	_x_s1_x,4,4
	.comm	s0_evt1,1,1
	.comm	_x_s0_evt1,1,1
	.comm	s0_evt2,1,1
	.comm	_x_s0_evt2,1,1
	.comm	s0_l0,1,1
	.comm	_x_s0_l0,1,1
	.comm	s2_lambda,4,4
	.comm	_x_s2_lambda,4,4
	.comm	s0_l1,1,1
	.comm	_x_s0_l1,1,1
	.comm	s2_backoff,4,4
	.comm	_x_s2_backoff,4,4
	.comm	bus_cd_id,4,4
	.comm	_x_bus_cd_id,4,4
	.comm	s1_backoff,4,4
	.comm	_x_s1_backoff,4,4
	.comm	bus_evt0,1,1
	.comm	_x_bus_evt0,1,1
	.comm	s1_evt1,1,1
	.comm	_x_s1_evt1,1,1
	.comm	bus_evt1,1,1
	.comm	_x_bus_evt1,1,1
	.comm	s1_evt2,1,1
	.comm	_x_s1_evt2,1,1
	.comm	s1_l0,1,1
	.comm	_x_s1_l0,1,1
	.comm	bus_l0,1,1
	.comm	_x_bus_l0,1,1
	.comm	s1_l1,1,1
	.comm	_x_s1_l1,1,1
	.comm	s2_x,4,4
	.comm	_x_s2_x,4,4
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmpge
	.global	__aeabi_fcmple
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.global	__aeabi_dcmple
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+256
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+264
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+16
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+20
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+24
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+272
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+28
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+32
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+36
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+268
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L363+40
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+44
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+48
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+220
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+60
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+236
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L363+64
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+68
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+76
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+80
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+88
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+96
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+240
	str	r3, [r2]	@ float
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+240
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L6
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L6:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L8
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L8:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L9
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L9
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L9:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L10
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L10
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
.L10:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L7:
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L11
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
.L11:
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L13
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
.L13:
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L12:
	ldr	r3, .L363+236
	ldr	r3, [r3]	@ float
	ldr	r1, .L363+212
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+220
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L15
	mov	r3, #0
	mov	r4, r3
.L15:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+240
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L16
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L16:
	ldr	r3, .L363+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L18
	ldr	r3, .L363+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L18
	ldr	r3, .L363+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L18:
	ldr	r3, .L363+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L363+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L363+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L20:
	ldr	r3, .L363+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L21
	ldr	r3, .L363+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L21
	ldr	r3, .L363+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L21:
	ldr	r3, .L363+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L22
	ldr	r3, .L363+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
	ldr	r3, .L363+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L19
.L22:
	ldr	r3, .L363+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L19:
	ldr	r3, .L363+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L23
	ldr	r3, .L363+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
.L23:
	ldr	r3, .L363+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L25
	ldr	r3, .L363+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
.L25:
	ldr	r3, .L363+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L24:
	ldr	r3, .L363+68
	ldr	r3, [r3]	@ float
	ldr	r1, .L363+212
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+32
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
	mov	r3, #0
	mov	r4, r3
.L27:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L363+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L363+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L28:
	ldr	r3, .L363+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L30
	ldr	r3, .L363+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
	ldr	r3, .L363+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L30:
	ldr	r3, .L363+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L32
	ldr	r3, .L363+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L32
	ldr	r3, .L363+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L32:
	ldr	r3, .L363+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L33
	ldr	r3, .L363+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L33
	ldr	r3, .L363+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L33:
	ldr	r3, .L363+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L34
	ldr	r3, .L363+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L34
	ldr	r3, .L363+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
.L34:
	ldr	r3, .L363+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L31:
	ldr	r3, .L363+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L35
	ldr	r3, .L363+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
.L35:
	ldr	r3, .L363+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L37
	ldr	r3, .L363+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
.L37:
	ldr	r3, .L363+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L36:
	ldr	r3, .L363+16
	ldr	r3, [r3]	@ float
	ldr	r1, .L363+212
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+20
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L39
	mov	r3, #0
	mov	r4, r3
.L39:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L40
	ldr	r3, .L363+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L363+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L40:
	ldr	r3, .L363+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L363+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L41
	ldr	r3, .L363+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L41:
	ldr	r3, .L363+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L43
	ldr	r3, .L363+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L43
	ldr	r3, .L363+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L43:
	ldr	r3, .L363+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L363+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L363+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L44:
	ldr	r3, .L363+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L363+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L45
	ldr	r3, .L363+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L42
.L45:
	ldr	r3, .L363+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L42:
	ldr	r3, .L363+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L46
	ldr	r3, .L363+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L46:
	ldr	r3, .L363+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L363+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L48:
	ldr	r3, .L363+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L49
	ldr	r3, .L363+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
.L49:
	ldr	r3, .L363+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L47:
	ldr	r3, .L363+40
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L363+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+28
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L363+212
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	mov	r3, #0
	mov	r4, r3
.L51:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L363+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L363+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L52:
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L53
	ldr	r3, .L363+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L53
	ldr	r3, .L363+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L53:
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	ldr	r2, .L363
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L56
.L4:
	mov	r3, #0
.L56:
	str	r3, [fp, #-24]
	b	.L57
.L364:
	.align	2
.L363:
	.word	_diverge_delta
	.word	s0_evt0
	.word	bus_l1
	.word	bus_evt2
	.word	s0_backoff
	.word	s0_lambda
	.word	s1_evt0
	.word	bus_x
	.word	s1_lambda
	.word	s0_x
	.word	bus_j
	.word	s1_x
	.word	s0_evt1
	.word	s0_evt2
	.word	s0_l0
	.word	s0_l1
	.word	bus_cd_id
	.word	s1_backoff
	.word	bus_evt0
	.word	s1_evt1
	.word	bus_evt1
	.word	s1_evt2
	.word	s1_l0
	.word	bus_l0
	.word	s1_l1
	.word	_x__diverge_delta
	.word	_x_s0_evt0
	.word	_x_bus_l1
	.word	_x_bus_evt2
	.word	_x_s0_backoff
	.word	_x_s0_lambda
	.word	_x_s1_evt0
	.word	_x_delta
	.word	_x_bus_x
	.word	_x_s1_lambda
	.word	_x_s0_x
	.word	_x_bus_j
	.word	_x_s1_x
	.word	_x_s0_evt1
	.word	_x_s0_evt2
	.word	_x_s0_l0
	.word	_x_s0_l1
	.word	_x_bus_cd_id
	.word	_x_s1_backoff
	.word	_x_bus_evt0
	.word	_x_s1_evt1
	.word	_x_bus_evt1
	.word	_x_s1_l0
	.word	_x_bus_l0
	.word	_x_s1_l1
	.word	_x_s2_evt2
	.word	_x_s2_evt1
	.word	_x_s2_evt0
	.word	1095761920
	.word	-1074790400
	.word	s2_lambda
	.word	_x_s2_lambda
	.word	_x_s2_backoff
	.word	_x_s2_x
	.word	s2_backoff
	.word	s2_x
	.word	_x_s2_l1
	.word	_x_s2_l0
	.word	s2_l0
	.word	s2_l1
	.word	delta
	.word	s2_evt2
	.word	s2_evt0
	.word	s2_evt1
	.word	_x_s1_evt2
.L312:
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+100
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+248
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+104
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+116
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+120
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+124
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+128
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+204
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+132
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+136
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+140
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L363+144
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+148
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+224
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+164
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+228
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	ldr	r2, .L363+168
	str	r3, [r2]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+172
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L363+196
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L363+232
	str	r3, [r2]	@ float
	ldr	r3, .L363+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L58
	ldr	r3, .L363+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L58
	ldr	r3, .L363+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L58:
	ldr	r3, .L363+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L363+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L363+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L60:
	ldr	r3, .L363+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L61
	ldr	r3, .L363+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L363+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L61:
	ldr	r3, .L363+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L62
	ldr	r3, .L363+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
	ldr	r3, .L363+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L59
.L62:
	ldr	r3, .L363+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L363+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L363+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L59:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L64
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
.L64:
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L66
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L65
.L66:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L65:
	ldr	r3, .L363+228
	ldr	r3, [r3]	@ float
	ldr	r1, .L363+212
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L363+224
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L68
	mov	r3, #0
	mov	r4, r3
.L68:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L363+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+224
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L69
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L69
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L69:
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L363+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+224
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L363+240
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L363+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L70
	ldr	r3, .L363+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L73
.L70:
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L73
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L73:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L75
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
.L75:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L77
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
.L77:
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L78
.L76:
	ldr	r3, .L363+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L78
	ldr	r3, .L363+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L80
.L78:
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L80
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L80:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L81
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L81
	ldr	r3, .L363+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+224
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L82
.L81:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L82
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L82
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L82:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L83
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L83
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
.L83:
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L84:
	ldr	r3, .L363+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+224
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
.L87:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L85
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
.L85:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L88
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L88:
	ldr	r3, .L363+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+224
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L363+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L92
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
.L92:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L89
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
.L89:
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L93
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L93
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L93
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L93:
	ldr	r3, .L363+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+240
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L94
	ldr	r3, .L363+228
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+236
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L96
.L94:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L96
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L96:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L97
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L97
	ldr	r3, .L363+236
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L363+228
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L363+216
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L98
.L97:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L98
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L98
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L98:
	ldr	r3, .L363+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+224
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L101
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L101:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L99
.L102:
	ldr	r3, .L363+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L99
	ldr	r3, .L363+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L104
.L99:
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L104
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L104:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L105
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L105
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
.L105:
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L106
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L106
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L106
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L106:
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L107
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L107
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L107
	ldr	r3, .L363+236
	ldr	r3, [r3]	@ float
	ldr	r2, .L363+240
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L108
.L107:
	ldr	r3, .L363+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L363+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L108
	ldr	r3, .L363+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L363+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L108
	ldr	r3, .L363+260
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L363+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+268
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L363+272
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L108:
	ldr	r3, .L363+276
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
	ldr	r3, .L365
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L109
	ldr	r3, .L365+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L109:
	ldr	r3, .L365+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L111
	ldr	r3, .L365
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L111
	ldr	r3, .L365+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L111:
	ldr	r3, .L365+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L112
	ldr	r3, .L365
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L112
	ldr	r3, .L365+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L112:
	ldr	r3, .L365+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L113
	ldr	r3, .L365+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L113
	ldr	r3, .L365
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L113:
	ldr	r3, .L365+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L110:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L114
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L114:
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L115
.L116:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L115:
	ldr	r3, .L365+20
	ldr	r3, [r3]	@ float
	ldr	r1, .L365+144
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+24
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L118
	mov	r3, #0
	mov	r4, r3
.L118:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L119
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L119:
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L365+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L365+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L365+28
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L365+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L123
.L120:
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L123
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L123:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L125
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
.L125:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L127
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
.L127:
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L128
.L126:
	ldr	r3, .L365+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L365+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L130
.L128:
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L130
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L130
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L130:
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L131
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L131
	ldr	r3, .L365+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L132
.L131:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L132:
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L133
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L133
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L133:
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L134
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L134
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L134:
	ldr	r3, .L365+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L137
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
.L137:
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L135
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
.L135:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L138
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L138
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L138:
	ldr	r3, .L365+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L139
	ldr	r3, .L365+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L139
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L142
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L142:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L139
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
.L139:
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L143
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L143:
	ldr	r3, .L365+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L144
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L144
	ldr	r3, .L365+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L146
.L144:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L146
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L146
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L146
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L146:
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L147
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L147
	ldr	r3, .L365+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L365+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L365+76
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L148
.L147:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L148:
	ldr	r3, .L365+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
.L151:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
.L152:
	ldr	r3, .L365+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L149
	ldr	r3, .L365+28
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L154
.L149:
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L154
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L154
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L154
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L154:
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L155
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L155
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
.L155:
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L156
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L156
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L156:
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L157
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L157
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L157
	ldr	r3, .L365+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L158
.L157:
	ldr	r3, .L365+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
	ldr	r3, .L365+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
	ldr	r3, .L365+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
	ldr	r3, .L365+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L158
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L158
	ldr	r3, .L365+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L158:
	ldr	r3, .L365+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L159
	ldr	r3, .L365+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L365+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
.L159:
	ldr	r3, .L365+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L161
	ldr	r3, .L365+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L161
	ldr	r3, .L365+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
.L161:
	ldr	r3, .L365+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L162
	ldr	r3, .L365+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L162
	ldr	r3, .L365+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
.L162:
	ldr	r3, .L365+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L163
	ldr	r3, .L365+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L163
	ldr	r3, .L365+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
.L163:
	ldr	r3, .L365+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L160:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
.L164:
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L165
.L166:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L165:
	ldr	r3, .L365+88
	ldr	r3, [r3]	@ float
	ldr	r1, .L365+144
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+84
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L168
	mov	r3, #0
	mov	r4, r3
.L168:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L169
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L169
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L169:
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L170
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L170
	ldr	r3, .L365+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	b	.L366
.L367:
	.align	2
.L365:
	.word	_x_s1_evt0
	.word	_x_s1_evt1
	.word	_x_s1_evt2
	.word	_x_s1_l0
	.word	_x_s1_l1
	.word	_x_s1_backoff
	.word	_x_s1_lambda
	.word	_x_s1_x
	.word	s1_l0
	.word	s1_l1
	.word	s1_lambda
	.word	s1_x
	.word	s1_backoff
	.word	s1_evt2
	.word	s1_evt0
	.word	s1_evt1
	.word	_x_s0_evt2
	.word	_x_s0_evt0
	.word	_x_s0_evt1
	.word	-1074790400
	.word	s0_lambda
	.word	_x_s0_lambda
	.word	_x_s0_backoff
	.word	_x_s0_x
	.word	s0_backoff
	.word	s0_x
	.word	_x_s0_l1
	.word	_x_s0_l0
	.word	s0_l0
	.word	s0_l1
	.word	s0_evt2
	.word	s0_evt0
	.word	s0_evt1
	.word	_x_bus_evt2
	.word	_x_bus_evt0
	.word	_x_bus_evt1
	.word	1095761920
	.word	_x_delta
	.word	delta
	.word	bus_x
	.word	_x_bus_x
	.word	bus_l0
	.word	bus_l1
	.word	bus_evt2
	.word	bus_evt0
	.word	bus_evt1
	.word	_x_bus_l1
	.word	_x_bus_l0
	.word	bus_j
	.word	_x_bus_j
.L366:
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L170
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L365+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L365+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L170
	ldr	r3, .L365+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L173
.L170:
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L173:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
.L175:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L177
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
.L177:
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L178
.L176:
	ldr	r3, .L365+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L178
	ldr	r3, .L365+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L180
.L178:
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L180:
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L181
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L365+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L182
.L181:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L182
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L182
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L182:
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L183
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
.L183:
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L184
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L184:
	ldr	r3, .L365+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L187
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
.L187:
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L185
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L185
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
.L185:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L188:
	ldr	r3, .L365+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L365+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L192
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L192:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L189
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
.L189:
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L193
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L193
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L193:
	ldr	r3, .L365+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L194
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L194
	ldr	r3, .L365+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L196
.L194:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L196:
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L197
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L365+96
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L365+88
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	ldr	r3, .L365+76
	bl	__aeabi_dcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L198
.L197:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L198
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L198
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L198:
	ldr	r3, .L365+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L201
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L202
.L201:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L199
.L202:
	ldr	r3, .L365+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L365+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L204
.L199:
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L204:
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L205
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
.L205:
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L206
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L206
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L206:
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L207
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L207
	ldr	r3, .L365+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L365+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L208
.L207:
	ldr	r3, .L365+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L365+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L365+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L365+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L208
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L365+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L208:
	ldr	r3, .L365+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L365+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L209
	ldr	r3, .L365+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
.L209:
	ldr	r3, .L365+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L211
	ldr	r3, .L365+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L211
	ldr	r3, .L365+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
.L211:
	ldr	r3, .L365+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L365+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L365+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
.L212:
	ldr	r3, .L365+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L365+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L365+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L210
.L213:
	ldr	r3, .L365+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L365+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L210:
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L214:
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L216:
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
.L217:
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L215:
	ldr	r3, .L365+160
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L365+144
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L218
	mov	r3, #0
	mov	r4, r3
.L218:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L219
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L219:
	ldr	r3, .L365+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L220:
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L365+156
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L365+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L365+192
	ldr	r2, [r3]
	ldr	r3, .L365+196
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L63
.L221:
	ldr	r3, .L365+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L365+156
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L365+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L365+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L365+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L365+192
	ldr	r2, [r3]
	ldr	r3, .L365+196
	ldr	r3, [r3]
	cmp	r2, r3
	beq	.L225
.L223:
	ldr	r3, .L365+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L225
	ldr	r3, .L365+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L225
	ldr	r3, .L365+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L225:
	ldr	r3, .L365+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L365+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L365+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L365+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L365+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L365+192
	ldr	r2, [r3]
	ldr	r3, .L365+196
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L226
	ldr	r3, .L368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L227
.L226:
	ldr	r3, .L368+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L368+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L227
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L227:
	ldr	r3, .L368+12
	ldr	r2, [r3]
	ldr	r3, .L368+16
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L228
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
.L229:
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L231
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
.L231:
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
.L228:
	ldr	r3, .L368+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L368+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L230:
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L233
.L232:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L234
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L234
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
.L234:
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L233
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L233
	ldr	r3, .L368+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L368+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L233:
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
	ldr	r3, .L368+144
	ldr	r3, [r3]	@ float
	ldr	r1, .L368+24
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L368+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L368
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L237
.L235:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
.L238:
	ldr	r3, .L368+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L368+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L237:
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L368+144
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L368+24
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L240
	mov	r3, #0
	mov	r4, r3
.L240:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L239
	ldr	r3, .L368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L241
.L239:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L242
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L242
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L242:
	ldr	r3, .L368+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L368+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L241:
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L368+144
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	ldr	r1, .L368+24
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L244
	mov	r3, #0
	mov	r4, r3
.L244:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L368+240
	ldr	r2, [r3]
	ldr	r3, .L368+12
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L243
	ldr	r3, .L368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L368+12
	ldr	r2, [r3]
	ldr	r3, .L368+16
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	beq	.L246
.L243:
	ldr	r3, .L368+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L368+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L246
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L246:
	ldr	r3, .L368+12
	ldr	r2, [r3]
	ldr	r3, .L368+16
	ldr	r3, [r3]
	sub	r3, r2, r3
	cmn	r3, #1
	bne	.L247
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L368+240
	ldr	r2, [r3]
	ldr	r3, .L368+12
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L247
	ldr	r3, .L368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L368+12
	ldr	r3, [r3]
	cmp	r3, #1
	ble	.L249
.L247:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
.L250:
	ldr	r3, .L368+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L368+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L249:
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L251
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L251
	ldr	r3, .L368+12
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L251
	ldr	r3, .L368
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L368+240
	ldr	r2, [r3]
	ldr	r3, .L368+12
	ldr	r3, [r3]
	cmp	r2, r3
	bne	.L251
	ldr	r3, .L368+16
	ldr	r3, [r3]
	cmp	r3, #0
	beq	.L253
.L251:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
.L254:
	ldr	r3, .L368+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L368+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L368+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L368+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L63
.L253:
	ldr	r3, .L368+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L368+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L368+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L368+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
.L256:
	ldr	r3, .L368+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L368+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L368+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
.L257:
	ldr	r3, .L368+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L259
	ldr	r3, .L368+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L259
	ldr	r3, .L368+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L260
.L259:
	ldr	r3, .L368+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L368+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L368+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
.L260:
	ldr	r3, .L368+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L261
	ldr	r3, .L368+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L261
	ldr	r3, .L368+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L262
.L261:
	ldr	r3, .L368+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L368+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L368+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L262
.L258:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L63
.L262:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L368+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L368+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
.L264:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L265
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L266
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L266
	mov	r3, #1
	b	.L267
.L266:
	mov	r3, #0
.L267:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L368+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L268
	ldr	r3, .L368+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L268
	ldr	r3, .L368+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
.L268:
	ldr	r3, .L368+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L270
	ldr	r3, .L368+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L270
	ldr	r3, .L368+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L269
.L270:
	ldr	r3, .L368+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L271
	ldr	r3, .L368+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
	ldr	r3, .L368+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L271
.L269:
	mov	r3, #1
	b	.L272
.L271:
	mov	r3, #0
.L272:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L273
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L273
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L273
	mov	r3, #1
	b	.L274
.L273:
	mov	r3, #0
.L274:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L368+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L275
	ldr	r3, .L368+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L275
	ldr	r3, .L368+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
.L275:
	ldr	r3, .L368+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L277
	ldr	r3, .L368+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L277
	ldr	r3, .L368+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L276
.L277:
	ldr	r3, .L368+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
	ldr	r3, .L368+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L278
	ldr	r3, .L368+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L278
.L276:
	mov	r3, #1
	b	.L279
.L278:
	mov	r3, #0
.L279:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L280
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L280
	mov	r3, #1
	b	.L281
.L280:
	mov	r3, #0
.L281:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L368+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L368+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L282
	ldr	r3, .L368+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L283
.L282:
	ldr	r3, .L368+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L368+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L284
	ldr	r3, .L368+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L283
.L284:
	ldr	r3, .L368+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L285
	ldr	r3, .L368+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L285
	ldr	r3, .L368+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L285
.L283:
	mov	r3, #1
	b	.L286
.L285:
	mov	r3, #0
.L286:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L287
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L287
	mov	r3, #1
	b	.L288
.L287:
	mov	r3, #0
.L288:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L368+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L289
	ldr	r3, .L368+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L289
	ldr	r3, .L368+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L290
.L289:
	ldr	r3, .L368+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L291
	ldr	r3, .L368+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L291
	ldr	r3, .L368+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L290
.L291:
	ldr	r3, .L368+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L292
	ldr	r3, .L368+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L292
	ldr	r3, .L368+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L292
.L290:
	mov	r3, #1
	b	.L293
.L292:
	mov	r3, #0
.L293:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
.L265:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L294
	ldr	r3, .L368+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	ldr	r3, .L368+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L295
	ldr	r3, .L368+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L295
	mov	r3, #1
	b	.L296
.L295:
	mov	r3, #0
.L296:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L297
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L297
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L297
	ldr	r3, .L368+240
	ldr	r3, [r3]
	cmp	r3, #0
	bne	.L297
	mov	r3, #1
	b	.L298
.L297:
	mov	r3, #0
.L298:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L368+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	ldr	r3, .L368+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
	ldr	r3, .L368+264
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L299
	mov	r3, #1
	b	.L300
.L299:
	mov	r3, #0
.L300:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L301
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L301
	ldr	r3, .L368+240
	ldr	r3, [r3]
	cmp	r3, #1
	bne	.L301
	mov	r3, #1
	b	.L302
.L369:
	.align	2
.L368:
	.word	_x_bus_x
	.word	bus_l0
	.word	bus_l1
	.word	bus_j
	.word	_x_bus_j
	.word	_x_bus_l0
	.word	1095761920
	.word	bus_evt2
	.word	bus_evt0
	.word	bus_evt1
	.word	delta
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_s2_l1
	.word	s2_l1
	.word	_x_s2_l0
	.word	s2_l0
	.word	_x_s2_evt2
	.word	s2_evt2
	.word	_x_s0_evt0
	.word	s0_evt0
	.word	_x_bus_l1
	.word	bus_l1
	.word	_x_bus_evt2
	.word	bus_evt2
	.word	_x_s0_backoff
	.word	s0_backoff
	.word	_x_s0_lambda
	.word	s0_lambda
	.word	_x_s1_evt0
	.word	s1_evt0
	.word	_x_delta
	.word	delta
	.word	_x_s2_evt1
	.word	s2_evt1
	.word	_x_bus_x
	.word	bus_x
	.word	_x_s1_lambda
	.word	s1_lambda
	.word	_x_s0_x
	.word	s0_x
	.word	_x_s2_evt0
	.word	s2_evt0
	.word	_x_bus_j
	.word	bus_j
	.word	_x_s1_x
	.word	s1_x
	.word	_x_s0_evt1
	.word	s0_evt1
	.word	_x_s0_evt2
	.word	s0_evt2
	.word	_x_s0_l0
	.word	s0_l0
	.word	_x_s2_lambda
	.word	s2_lambda
	.word	_x_s0_l1
	.word	s0_l1
	.word	_x_s2_backoff
	.word	s2_backoff
	.word	_x_bus_cd_id
	.word	bus_cd_id
	.word	_x_s1_backoff
	.word	s1_backoff
	.word	_x_bus_evt0
	.word	bus_evt0
	.word	_x_s1_evt1
	.word	s1_evt1
	.word	_x_bus_evt1
	.word	bus_evt1
	.word	_x_s1_evt2
	.word	s1_evt2
	.word	_x_s1_l0
	.word	s1_l0
	.word	_x_bus_l0
	.word	bus_l0
	.word	_x_s1_l1
	.word	s1_l1
	.word	_x_s2_x
	.word	s2_x
.L301:
	mov	r3, #0
.L302:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L368+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L303
	ldr	r3, .L368+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L303
	ldr	r3, .L368+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L303
	mov	r3, #1
	b	.L304
.L303:
	mov	r3, #0
.L304:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, #1
	and	r2, r3, #255
	ldr	r3, .L368+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L368+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L368+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L305
	ldr	r3, .L368+240
	ldr	r3, [r3]
	cmp	r3, #2
	bne	.L305
	mov	r3, #1
	b	.L306
.L305:
	mov	r3, #0
.L306:
	and	r3, r3, #1
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
.L294:
	ldr	r3, .L368+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L307
	ldr	r3, .L368+48
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L308
	mov	r3, #0
	mov	r4, r3
.L308:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L63
.L307:
	ldr	r3, .L368+48
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L309
	ldr	r3, .L368+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L368+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L368+44
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L63
.L309:
	mov	r3, #1
	b	.L311
.L63:
	mov	r3, #0
.L311:
	str	r3, [fp, #-24]
	ldr	r3, .L368+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+48
	str	r3, [r2]	@ float
	ldr	r3, .L368+52
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+56
	strb	r2, [r3]
	ldr	r3, .L368+60
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+64
	strb	r2, [r3]
	ldr	r3, .L368+68
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+72
	strb	r2, [r3]
	ldr	r3, .L368+76
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+80
	strb	r2, [r3]
	ldr	r3, .L368+84
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+88
	strb	r2, [r3]
	ldr	r3, .L368+92
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+96
	strb	r2, [r3]
	ldr	r3, .L368+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+104
	str	r3, [r2]	@ float
	ldr	r3, .L368+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+112
	str	r3, [r2]	@ float
	ldr	r3, .L368+116
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+120
	strb	r2, [r3]
	ldr	r3, .L368+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+128
	str	r3, [r2]	@ float
	ldr	r3, .L368+132
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+136
	strb	r2, [r3]
	ldr	r3, .L368+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+144
	str	r3, [r2]	@ float
	ldr	r3, .L368+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+152
	str	r3, [r2]	@ float
	ldr	r3, .L368+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+160
	str	r3, [r2]	@ float
	ldr	r3, .L368+164
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+168
	strb	r2, [r3]
	ldr	r3, .L368+172
	ldr	r3, [r3]
	ldr	r2, .L368+176
	str	r3, [r2]
	ldr	r3, .L368+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+184
	str	r3, [r2]	@ float
	ldr	r3, .L368+188
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+192
	strb	r2, [r3]
	ldr	r3, .L368+196
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+200
	strb	r2, [r3]
	ldr	r3, .L368+204
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+208
	strb	r2, [r3]
	ldr	r3, .L368+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+216
	str	r3, [r2]	@ float
	ldr	r3, .L368+220
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+224
	strb	r2, [r3]
	ldr	r3, .L368+228
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+232
	str	r3, [r2]	@ float
	ldr	r3, .L368+236
	ldr	r3, [r3]
	ldr	r2, .L368+240
	str	r3, [r2]
	ldr	r3, .L368+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+248
	str	r3, [r2]	@ float
	ldr	r3, .L368+252
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+256
	strb	r2, [r3]
	ldr	r3, .L368+260
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+264
	strb	r2, [r3]
	ldr	r3, .L368+268
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+272
	strb	r2, [r3]
	ldr	r3, .L368+276
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+280
	strb	r2, [r3]
	ldr	r3, .L368+284
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+288
	strb	r2, [r3]
	ldr	r3, .L368+292
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+296
	strb	r2, [r3]
	ldr	r3, .L368+300
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L368+304
	strb	r2, [r3]
	ldr	r3, .L368+308
	ldr	r3, [r3]	@ float
	ldr	r2, .L368+312
	str	r3, [r2]	@ float
.L57:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L312
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
