	.file	"952107.c"
	.intel_syntax noprefix
	.text
	.globl	__VERIFIER_nondet_bool
	.type	__VERIFIER_nondet_bool, @function
__VERIFIER_nondet_bool:
.LFB0:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	call	__VERIFIER_nondet_int@PLT
	test	eax, eax
	setne	al
	pop	rbp
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE0:
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.globl	p25_l1
	.bss
	.type	p25_l1, @object
	.size	p25_l1, 1
p25_l1:
	.zero	1
	.globl	_x_p25_l1
	.type	_x_p25_l1, @object
	.size	_x_p25_l1, 1
_x_p25_l1:
	.zero	1
	.globl	p25_l0
	.type	p25_l0, @object
	.size	p25_l0, 1
p25_l0:
	.zero	1
	.globl	_x_p25_l0
	.type	_x_p25_l0, @object
	.size	_x_p25_l0, 1
_x_p25_l0:
	.zero	1
	.globl	p24_l1
	.type	p24_l1, @object
	.size	p24_l1, 1
p24_l1:
	.zero	1
	.globl	_x_p24_l1
	.type	_x_p24_l1, @object
	.size	_x_p24_l1, 1
_x_p24_l1:
	.zero	1
	.globl	p24_l0
	.type	p24_l0, @object
	.size	p24_l0, 1
p24_l0:
	.zero	1
	.globl	_x_p24_l0
	.type	_x_p24_l0, @object
	.size	_x_p24_l0, 1
_x_p24_l0:
	.zero	1
	.globl	p23_l1
	.type	p23_l1, @object
	.size	p23_l1, 1
p23_l1:
	.zero	1
	.globl	_x_p23_l1
	.type	_x_p23_l1, @object
	.size	_x_p23_l1, 1
_x_p23_l1:
	.zero	1
	.globl	p23_l0
	.type	p23_l0, @object
	.size	p23_l0, 1
p23_l0:
	.zero	1
	.globl	_x_p23_l0
	.type	_x_p23_l0, @object
	.size	_x_p23_l0, 1
_x_p23_l0:
	.zero	1
	.globl	p24_saved_max
	.align 4
	.type	p24_saved_max, @object
	.size	p24_saved_max, 4
p24_saved_max:
	.zero	4
	.globl	_x_p24_saved_max
	.align 4
	.type	_x_p24_saved_max, @object
	.size	_x_p24_saved_max, 4
_x_p24_saved_max:
	.zero	4
	.globl	p4_l1
	.type	p4_l1, @object
	.size	p4_l1, 1
p4_l1:
	.zero	1
	.globl	_x_p4_l1
	.type	_x_p4_l1, @object
	.size	_x_p4_l1, 1
_x_p4_l1:
	.zero	1
	.globl	p9_l0
	.type	p9_l0, @object
	.size	p9_l0, 1
p9_l0:
	.zero	1
	.globl	_x_p9_l0
	.type	_x_p9_l0, @object
	.size	_x_p9_l0, 1
_x_p9_l0:
	.zero	1
	.globl	p0_l1
	.type	p0_l1, @object
	.size	p0_l1, 1
p0_l1:
	.zero	1
	.globl	_x_p0_l1
	.type	_x_p0_l1, @object
	.size	_x_p0_l1, 1
_x_p0_l1:
	.zero	1
	.globl	p11_saved_max
	.align 4
	.type	p11_saved_max, @object
	.size	p11_saved_max, 4
p11_saved_max:
	.zero	4
	.globl	_x_p11_saved_max
	.align 4
	.type	_x_p11_saved_max, @object
	.size	_x_p11_saved_max, 4
_x_p11_saved_max:
	.zero	4
	.globl	p16_x
	.align 4
	.type	p16_x, @object
	.size	p16_x, 4
p16_x:
	.zero	4
	.globl	_x_p16_x
	.align 4
	.type	_x_p16_x, @object
	.size	_x_p16_x, 4
_x_p16_x:
	.zero	4
	.globl	p24_x
	.align 4
	.type	p24_x, @object
	.size	p24_x, 4
p24_x:
	.zero	4
	.globl	_x_p24_x
	.align 4
	.type	_x_p24_x, @object
	.size	_x_p24_x, 4
_x_p24_x:
	.zero	4
	.globl	p4_l0
	.type	p4_l0, @object
	.size	p4_l0, 1
p4_l0:
	.zero	1
	.globl	_x_p4_l0
	.type	_x_p4_l0, @object
	.size	_x_p4_l0, 1
_x_p4_l0:
	.zero	1
	.globl	p0_l0
	.type	p0_l0, @object
	.size	p0_l0, 1
p0_l0:
	.zero	1
	.globl	_x_p0_l0
	.type	_x_p0_l0, @object
	.size	_x_p0_l0, 1
_x_p0_l0:
	.zero	1
	.globl	p6_saved_max
	.align 4
	.type	p6_saved_max, @object
	.size	p6_saved_max, 4
p6_saved_max:
	.zero	4
	.globl	_x_p6_saved_max
	.align 4
	.type	_x_p6_saved_max, @object
	.size	_x_p6_saved_max, 4
_x_p6_saved_max:
	.zero	4
	.globl	p11_x
	.align 4
	.type	p11_x, @object
	.size	p11_x, 4
p11_x:
	.zero	4
	.globl	_x_p11_x
	.align 4
	.type	_x_p11_x, @object
	.size	_x_p11_x, 4
_x_p11_x:
	.zero	4
	.globl	p4_saved_max
	.align 4
	.type	p4_saved_max, @object
	.size	p4_saved_max, 4
p4_saved_max:
	.zero	4
	.globl	_x_p4_saved_max
	.align 4
	.type	_x_p4_saved_max, @object
	.size	_x_p4_saved_max, 4
_x_p4_saved_max:
	.zero	4
	.globl	turn0
	.type	turn0, @object
	.size	turn0, 1
turn0:
	.zero	1
	.globl	_x_turn0
	.type	_x_turn0, @object
	.size	_x_turn0, 1
_x_turn0:
	.zero	1
	.globl	p9_x
	.align 4
	.type	p9_x, @object
	.size	p9_x, 4
p9_x:
	.zero	4
	.globl	_x_p9_x
	.align 4
	.type	_x_p9_x, @object
	.size	_x_p9_x, 4
_x_p9_x:
	.zero	4
	.globl	p23_saved_max
	.align 4
	.type	p23_saved_max, @object
	.size	p23_saved_max, 4
p23_saved_max:
	.zero	4
	.globl	_x_p23_saved_max
	.align 4
	.type	_x_p23_saved_max, @object
	.size	_x_p23_saved_max, 4
_x_p23_saved_max:
	.zero	4
	.globl	p3_l1
	.type	p3_l1, @object
	.size	p3_l1, 1
p3_l1:
	.zero	1
	.globl	_x_p3_l1
	.type	_x_p3_l1, @object
	.size	_x_p3_l1, 1
_x_p3_l1:
	.zero	1
	.globl	proposed4
	.align 4
	.type	proposed4, @object
	.size	proposed4, 4
proposed4:
	.zero	4
	.globl	_x_proposed4
	.align 4
	.type	_x_proposed4, @object
	.size	_x_proposed4, 4
_x_proposed4:
	.zero	4
	.globl	p8_l0
	.type	p8_l0, @object
	.size	p8_l0, 1
p8_l0:
	.zero	1
	.globl	_x_p8_l0
	.type	_x_p8_l0, @object
	.size	_x_p8_l0, 1
_x_p8_l0:
	.zero	1
	.globl	p0_saved_max
	.align 4
	.type	p0_saved_max, @object
	.size	p0_saved_max, 4
p0_saved_max:
	.zero	4
	.globl	_x_p0_saved_max
	.align 4
	.type	_x_p0_saved_max, @object
	.size	_x_p0_saved_max, 4
_x_p0_saved_max:
	.zero	4
	.globl	p4_x
	.align 4
	.type	p4_x, @object
	.size	p4_x, 4
p4_x:
	.zero	4
	.globl	_x_p4_x
	.align 4
	.type	_x_p4_x, @object
	.size	_x_p4_x, 4
_x_p4_x:
	.zero	4
	.globl	p23_x
	.align 4
	.type	p23_x, @object
	.size	p23_x, 4
p23_x:
	.zero	4
	.globl	_x_p23_x
	.align 4
	.type	_x_p23_x, @object
	.size	_x_p23_x, 4
_x_p23_x:
	.zero	4
	.globl	p3_l0
	.type	p3_l0, @object
	.size	p3_l0, 1
p3_l0:
	.zero	1
	.globl	_x_p3_l0
	.type	_x_p3_l0, @object
	.size	_x_p3_l0, 1
_x_p3_l0:
	.zero	1
	.globl	proposed3
	.align 4
	.type	proposed3, @object
	.size	proposed3, 4
proposed3:
	.zero	4
	.globl	_x_proposed3
	.align 4
	.type	_x_proposed3, @object
	.size	_x_proposed3, 4
_x_proposed3:
	.zero	4
	.globl	p0_x
	.align 4
	.type	p0_x, @object
	.size	p0_x, 4
p0_x:
	.zero	4
	.globl	_x_p0_x
	.align 4
	.type	_x_p0_x, @object
	.size	_x_p0_x, 4
_x_p0_x:
	.zero	4
	.globl	proposed25
	.align 4
	.type	proposed25, @object
	.size	proposed25, 4
proposed25:
	.zero	4
	.globl	_x_proposed25
	.align 4
	.type	_x_proposed25, @object
	.size	_x_proposed25, 4
_x_proposed25:
	.zero	4
	.globl	proposed24
	.align 4
	.type	proposed24, @object
	.size	proposed24, 4
proposed24:
	.zero	4
	.globl	_x_proposed24
	.align 4
	.type	_x_proposed24, @object
	.size	_x_proposed24, 4
_x_proposed24:
	.zero	4
	.globl	turn4
	.type	turn4, @object
	.size	turn4, 1
turn4:
	.zero	1
	.globl	_x_turn4
	.type	_x_turn4, @object
	.size	_x_turn4, 1
_x_turn4:
	.zero	1
	.globl	delta
	.align 4
	.type	delta, @object
	.size	delta, 4
delta:
	.zero	4
	.globl	_x_delta
	.align 4
	.type	_x_delta, @object
	.size	_x_delta, 4
_x_delta:
	.zero	4
	.globl	id4
	.type	id4, @object
	.size	id4, 1
id4:
	.zero	1
	.globl	_x_id4
	.type	_x_id4, @object
	.size	_x_id4, 1
_x_id4:
	.zero	1
	.globl	proposed2
	.align 4
	.type	proposed2, @object
	.size	proposed2, 4
proposed2:
	.zero	4
	.globl	_x_proposed2
	.align 4
	.type	_x_proposed2, @object
	.size	_x_proposed2, 4
_x_proposed2:
	.zero	4
	.globl	turn3
	.type	turn3, @object
	.size	turn3, 1
turn3:
	.zero	1
	.globl	_x_turn3
	.type	_x_turn3, @object
	.size	_x_turn3, 1
_x_turn3:
	.zero	1
	.globl	p19_saved_max
	.align 4
	.type	p19_saved_max, @object
	.size	p19_saved_max, 4
p19_saved_max:
	.zero	4
	.globl	_x_p19_saved_max
	.align 4
	.type	_x_p19_saved_max, @object
	.size	_x_p19_saved_max, 4
_x_p19_saved_max:
	.zero	4
	.globl	max_prop
	.align 4
	.type	max_prop, @object
	.size	max_prop, 4
max_prop:
	.zero	4
	.globl	_x_max_prop
	.align 4
	.type	_x_max_prop, @object
	.size	_x_max_prop, 4
_x_max_prop:
	.zero	4
	.globl	id3
	.type	id3, @object
	.size	id3, 1
id3:
	.zero	1
	.globl	_x_id3
	.type	_x_id3, @object
	.size	_x_id3, 1
_x_id3:
	.zero	1
	.globl	proposed1
	.align 4
	.type	proposed1, @object
	.size	proposed1, 4
proposed1:
	.zero	4
	.globl	_x_proposed1
	.align 4
	.type	_x_proposed1, @object
	.size	_x_proposed1, 4
_x_proposed1:
	.zero	4
	.globl	turn2
	.type	turn2, @object
	.size	turn2, 1
turn2:
	.zero	1
	.globl	_x_turn2
	.type	_x_turn2, @object
	.size	_x_turn2, 1
_x_turn2:
	.zero	1
	.globl	p14_saved_max
	.align 4
	.type	p14_saved_max, @object
	.size	p14_saved_max, 4
p14_saved_max:
	.zero	4
	.globl	_x_p14_saved_max
	.align 4
	.type	_x_p14_saved_max, @object
	.size	_x_p14_saved_max, 4
_x_p14_saved_max:
	.zero	4
	.globl	p19_x
	.align 4
	.type	p19_x, @object
	.size	p19_x, 4
p19_x:
	.zero	4
	.globl	_x_p19_x
	.align 4
	.type	_x_p19_x, @object
	.size	_x_p19_x, 4
_x_p19_x:
	.zero	4
	.globl	id2
	.type	id2, @object
	.size	id2, 1
id2:
	.zero	1
	.globl	_x_id2
	.type	_x_id2, @object
	.size	_x_id2, 1
_x_id2:
	.zero	1
	.globl	proposed0
	.align 4
	.type	proposed0, @object
	.size	proposed0, 4
proposed0:
	.zero	4
	.globl	_x_proposed0
	.align 4
	.type	_x_proposed0, @object
	.size	_x_proposed0, 4
_x_proposed0:
	.zero	4
	.globl	p3_saved_max
	.align 4
	.type	p3_saved_max, @object
	.size	p3_saved_max, 4
p3_saved_max:
	.zero	4
	.globl	_x_p3_saved_max
	.align 4
	.type	_x_p3_saved_max, @object
	.size	_x_p3_saved_max, 4
_x_p3_saved_max:
	.zero	4
	.globl	p8_x
	.align 4
	.type	p8_x, @object
	.size	p8_x, 4
p8_x:
	.zero	4
	.globl	_x_p8_x
	.align 4
	.type	_x_p8_x, @object
	.size	_x_p8_x, 4
_x_p8_x:
	.zero	4
	.globl	proposed12
	.align 4
	.type	proposed12, @object
	.size	proposed12, 4
proposed12:
	.zero	4
	.globl	_x_proposed12
	.align 4
	.type	_x_proposed12, @object
	.size	_x_proposed12, 4
_x_proposed12:
	.zero	4
	.globl	p7_l0
	.type	p7_l0, @object
	.size	p7_l0, 1
p7_l0:
	.zero	1
	.globl	_x_p7_l0
	.type	_x_p7_l0, @object
	.size	_x_p7_l0, 1
_x_p7_l0:
	.zero	1
	.globl	turn1
	.type	turn1, @object
	.size	turn1, 1
turn1:
	.zero	1
	.globl	_x_turn1
	.type	_x_turn1, @object
	.size	_x_turn1, 1
_x_turn1:
	.zero	1
	.globl	p9_saved_max
	.align 4
	.type	p9_saved_max, @object
	.size	p9_saved_max, 4
p9_saved_max:
	.zero	4
	.globl	_x_p9_saved_max
	.align 4
	.type	_x_p9_saved_max, @object
	.size	_x_p9_saved_max, 4
_x_p9_saved_max:
	.zero	4
	.globl	p14_x
	.align 4
	.type	p14_x, @object
	.size	p14_x, 4
p14_x:
	.zero	4
	.globl	_x_p14_x
	.align 4
	.type	_x_p14_x, @object
	.size	_x_p14_x, 4
_x_p14_x:
	.zero	4
	.globl	id1
	.type	id1, @object
	.size	id1, 1
id1:
	.zero	1
	.globl	_x_id1
	.type	_x_id1, @object
	.size	_x_id1, 1
_x_id1:
	.zero	1
	.globl	inc_max_prop
	.type	inc_max_prop, @object
	.size	inc_max_prop, 1
inc_max_prop:
	.zero	1
	.globl	_x_inc_max_prop
	.type	_x_inc_max_prop, @object
	.size	_x_inc_max_prop, 1
_x_inc_max_prop:
	.zero	1
	.globl	p3_x
	.align 4
	.type	p3_x, @object
	.size	p3_x, 4
p3_x:
	.zero	4
	.globl	_x_p3_x
	.align 4
	.type	_x_p3_x, @object
	.size	_x_p3_x, 4
_x_p3_x:
	.zero	4
	.globl	id0
	.type	id0, @object
	.size	id0, 1
id0:
	.zero	1
	.globl	_x_id0
	.type	_x_id0, @object
	.size	_x_id0, 1
_x_id0:
	.zero	1
	.globl	proposed22
	.align 4
	.type	proposed22, @object
	.size	proposed22, 4
proposed22:
	.zero	4
	.globl	_x_proposed22
	.align 4
	.type	_x_proposed22, @object
	.size	_x_proposed22, 4
_x_proposed22:
	.zero	4
	.globl	p2_x
	.align 4
	.type	p2_x, @object
	.size	p2_x, 4
p2_x:
	.zero	4
	.globl	_x_p2_x
	.align 4
	.type	_x_p2_x, @object
	.size	_x_p2_x, 4
_x_p2_x:
	.zero	4
	.globl	proposed23
	.align 4
	.type	proposed23, @object
	.size	proposed23, 4
proposed23:
	.zero	4
	.globl	_x_proposed23
	.align 4
	.type	_x_proposed23, @object
	.size	_x_proposed23, 4
_x_proposed23:
	.zero	4
	.globl	p2_saved_max
	.align 4
	.type	p2_saved_max, @object
	.size	p2_saved_max, 4
p2_saved_max:
	.zero	4
	.globl	_x_p2_saved_max
	.align 4
	.type	_x_p2_saved_max, @object
	.size	_x_p2_saved_max, 4
_x_p2_saved_max:
	.zero	4
	.globl	proposed20
	.align 4
	.type	proposed20, @object
	.size	proposed20, 4
proposed20:
	.zero	4
	.globl	_x_proposed20
	.align 4
	.type	_x_proposed20, @object
	.size	_x_proposed20, 4
_x_proposed20:
	.zero	4
	.globl	p7_x
	.align 4
	.type	p7_x, @object
	.size	p7_x, 4
p7_x:
	.zero	4
	.globl	_x_p7_x
	.align 4
	.type	_x_p7_x, @object
	.size	_x_p7_x, 4
_x_p7_x:
	.zero	4
	.globl	p6_l0
	.type	p6_l0, @object
	.size	p6_l0, 1
p6_l0:
	.zero	1
	.globl	_x_p6_l0
	.type	_x_p6_l0, @object
	.size	_x_p6_l0, 1
_x_p6_l0:
	.zero	1
	.globl	proposed5
	.align 4
	.type	proposed5, @object
	.size	proposed5, 4
proposed5:
	.zero	4
	.globl	_x_proposed5
	.align 4
	.type	_x_proposed5, @object
	.size	_x_proposed5, 4
_x_proposed5:
	.zero	4
	.globl	p8_l1
	.type	p8_l1, @object
	.size	p8_l1, 1
p8_l1:
	.zero	1
	.globl	_x_p8_l1
	.type	_x_p8_l1, @object
	.size	_x_p8_l1, 1
_x_p8_l1:
	.zero	1
	.globl	p13_l0
	.type	p13_l0, @object
	.size	p13_l0, 1
p13_l0:
	.zero	1
	.globl	_x_p13_l0
	.type	_x_p13_l0, @object
	.size	_x_p13_l0, 1
_x_p13_l0:
	.zero	1
	.globl	p22_l0
	.type	p22_l0, @object
	.size	p22_l0, 1
p22_l0:
	.zero	1
	.globl	_x_p22_l0
	.type	_x_p22_l0, @object
	.size	_x_p22_l0, 1
_x_p22_l0:
	.zero	1
	.globl	proposed6
	.align 4
	.type	proposed6, @object
	.size	proposed6, 4
proposed6:
	.zero	4
	.globl	_x_proposed6
	.align 4
	.type	_x_proposed6, @object
	.size	_x_proposed6, 4
_x_proposed6:
	.zero	4
	.globl	p13_l1
	.type	p13_l1, @object
	.size	p13_l1, 1
p13_l1:
	.zero	1
	.globl	_x_p13_l1
	.type	_x_p13_l1, @object
	.size	_x_p13_l1, 1
_x_p13_l1:
	.zero	1
	.globl	p18_l0
	.type	p18_l0, @object
	.size	p18_l0, 1
p18_l0:
	.zero	1
	.globl	_x_p18_l0
	.type	_x_p18_l0, @object
	.size	_x_p18_l0, 1
_x_p18_l0:
	.zero	1
	.globl	p22_l1
	.type	p22_l1, @object
	.size	p22_l1, 1
p22_l1:
	.zero	1
	.globl	_x_p22_l1
	.type	_x_p22_l1, @object
	.size	_x_p22_l1, 1
_x_p22_l1:
	.zero	1
	.globl	proposed7
	.align 4
	.type	proposed7, @object
	.size	proposed7, 4
proposed7:
	.zero	4
	.globl	_x_proposed7
	.align 4
	.type	_x_proposed7, @object
	.size	_x_proposed7, 4
_x_proposed7:
	.zero	4
	.globl	p18_l1
	.type	p18_l1, @object
	.size	p18_l1, 1
p18_l1:
	.zero	1
	.globl	_x_p18_l1
	.type	_x_p18_l1, @object
	.size	_x_p18_l1, 1
_x_p18_l1:
	.zero	1
	.globl	p1_x
	.align 4
	.type	p1_x, @object
	.size	p1_x, 4
p1_x:
	.zero	4
	.globl	_x_p1_x
	.align 4
	.type	_x_p1_x, @object
	.size	_x_p1_x, 4
_x_p1_x:
	.zero	4
	.globl	p1_saved_max
	.align 4
	.type	p1_saved_max, @object
	.size	p1_saved_max, 4
p1_saved_max:
	.zero	4
	.globl	_x_p1_saved_max
	.align 4
	.type	_x_p1_saved_max, @object
	.size	_x_p1_saved_max, 4
_x_p1_saved_max:
	.zero	4
	.globl	p6_x
	.align 4
	.type	p6_x, @object
	.size	p6_x, 4
p6_x:
	.zero	4
	.globl	_x_p6_x
	.align 4
	.type	_x_p6_x, @object
	.size	_x_p6_x, 4
_x_p6_x:
	.zero	4
	.globl	p8_saved_max
	.align 4
	.type	p8_saved_max, @object
	.size	p8_saved_max, 4
p8_saved_max:
	.zero	4
	.globl	_x_p8_saved_max
	.align 4
	.type	_x_p8_saved_max, @object
	.size	_x_p8_saved_max, 4
_x_p8_saved_max:
	.zero	4
	.globl	p13_x
	.align 4
	.type	p13_x, @object
	.size	p13_x, 4
p13_x:
	.zero	4
	.globl	_x_p13_x
	.align 4
	.type	_x_p13_x, @object
	.size	_x_p13_x, 4
_x_p13_x:
	.zero	4
	.globl	_diverge_delta
	.align 4
	.type	_diverge_delta, @object
	.size	_diverge_delta, 4
_diverge_delta:
	.zero	4
	.globl	_x__diverge_delta
	.align 4
	.type	_x__diverge_delta, @object
	.size	_x__diverge_delta, 4
_x__diverge_delta:
	.zero	4
	.globl	p22_x
	.align 4
	.type	p22_x, @object
	.size	p22_x, 4
p22_x:
	.zero	4
	.globl	_x_p22_x
	.align 4
	.type	_x_p22_x, @object
	.size	_x_p22_x, 4
_x_p22_x:
	.zero	4
	.globl	p2_l0
	.type	p2_l0, @object
	.size	p2_l0, 1
p2_l0:
	.zero	1
	.globl	_x_p2_l0
	.type	_x_p2_l0, @object
	.size	_x_p2_l0, 1
_x_p2_l0:
	.zero	1
	.globl	proposed14
	.align 4
	.type	proposed14, @object
	.size	proposed14, 4
proposed14:
	.zero	4
	.globl	_x_proposed14
	.align 4
	.type	_x_proposed14, @object
	.size	_x_proposed14, 4
_x_proposed14:
	.zero	4
	.globl	p13_saved_max
	.align 4
	.type	p13_saved_max, @object
	.size	p13_saved_max, 4
p13_saved_max:
	.zero	4
	.globl	_x_p13_saved_max
	.align 4
	.type	_x_p13_saved_max, @object
	.size	_x_p13_saved_max, 4
_x_p13_saved_max:
	.zero	4
	.globl	p18_x
	.align 4
	.type	p18_x, @object
	.size	p18_x, 4
p18_x:
	.zero	4
	.globl	_x_p18_x
	.align 4
	.type	_x_p18_x, @object
	.size	_x_p18_x, 4
_x_p18_x:
	.zero	4
	.globl	p22_saved_max
	.align 4
	.type	p22_saved_max, @object
	.size	p22_saved_max, 4
p22_saved_max:
	.zero	4
	.globl	_x_p22_saved_max
	.align 4
	.type	_x_p22_saved_max, @object
	.size	_x_p22_saved_max, 4
_x_p22_saved_max:
	.zero	4
	.globl	p2_l1
	.type	p2_l1, @object
	.size	p2_l1, 1
p2_l1:
	.zero	1
	.globl	_x_p2_l1
	.type	_x_p2_l1, @object
	.size	_x_p2_l1, 1
_x_p2_l1:
	.zero	1
	.globl	proposed15
	.align 4
	.type	proposed15, @object
	.size	proposed15, 4
proposed15:
	.zero	4
	.globl	_x_proposed15
	.align 4
	.type	_x_proposed15, @object
	.size	_x_proposed15, 4
_x_proposed15:
	.zero	4
	.globl	p18_saved_max
	.align 4
	.type	p18_saved_max, @object
	.size	p18_saved_max, 4
p18_saved_max:
	.zero	4
	.globl	_x_p18_saved_max
	.align 4
	.type	_x_p18_saved_max, @object
	.size	_x_p18_saved_max, 4
_x_p18_saved_max:
	.zero	4
	.globl	p5_x
	.align 4
	.type	p5_x, @object
	.size	p5_x, 4
p5_x:
	.zero	4
	.globl	_x_p5_x
	.align 4
	.type	_x_p5_x, @object
	.size	_x_p5_x, 4
_x_p5_x:
	.zero	4
	.globl	p5_saved_max
	.align 4
	.type	p5_saved_max, @object
	.size	p5_saved_max, 4
p5_saved_max:
	.zero	4
	.globl	_x_p5_saved_max
	.align 4
	.type	_x_p5_saved_max, @object
	.size	_x_p5_saved_max, 4
_x_p5_saved_max:
	.zero	4
	.globl	p10_x
	.align 4
	.type	p10_x, @object
	.size	p10_x, 4
p10_x:
	.zero	4
	.globl	_x_p10_x
	.align 4
	.type	_x_p10_x, @object
	.size	_x_p10_x, 4
_x_p10_x:
	.zero	4
	.globl	p25_x
	.align 4
	.type	p25_x, @object
	.size	p25_x, 4
p25_x:
	.zero	4
	.globl	_x_p25_x
	.align 4
	.type	_x_p25_x, @object
	.size	_x_p25_x, 4
_x_p25_x:
	.zero	4
	.globl	p5_l0
	.type	p5_l0, @object
	.size	p5_l0, 1
p5_l0:
	.zero	1
	.globl	_x_p5_l0
	.type	_x_p5_l0, @object
	.size	_x_p5_l0, 1
_x_p5_l0:
	.zero	1
	.globl	p25_saved_max
	.align 4
	.type	p25_saved_max, @object
	.size	p25_saved_max, 4
p25_saved_max:
	.zero	4
	.globl	_x_p25_saved_max
	.align 4
	.type	_x_p25_saved_max, @object
	.size	_x_p25_saved_max, 4
_x_p25_saved_max:
	.zero	4
	.globl	p5_l1
	.type	p5_l1, @object
	.size	p5_l1, 1
p5_l1:
	.zero	1
	.globl	_x_p5_l1
	.type	_x_p5_l1, @object
	.size	_x_p5_l1, 1
_x_p5_l1:
	.zero	1
	.globl	p10_l0
	.type	p10_l0, @object
	.size	p10_l0, 1
p10_l0:
	.zero	1
	.globl	_x_p10_l0
	.type	_x_p10_l0, @object
	.size	_x_p10_l0, 1
_x_p10_l0:
	.zero	1
	.globl	p6_l1
	.type	p6_l1, @object
	.size	p6_l1, 1
p6_l1:
	.zero	1
	.globl	_x_p6_l1
	.type	_x_p6_l1, @object
	.size	_x_p6_l1, 1
_x_p6_l1:
	.zero	1
	.globl	p11_l0
	.type	p11_l0, @object
	.size	p11_l0, 1
p11_l0:
	.zero	1
	.globl	_x_p11_l0
	.type	_x_p11_l0, @object
	.size	_x_p11_l0, 1
_x_p11_l0:
	.zero	1
	.globl	proposed21
	.align 4
	.type	proposed21, @object
	.size	proposed21, 4
proposed21:
	.zero	4
	.globl	_x_proposed21
	.align 4
	.type	_x_proposed21, @object
	.size	_x_proposed21, 4
_x_proposed21:
	.zero	4
	.globl	p7_saved_max
	.align 4
	.type	p7_saved_max, @object
	.size	p7_saved_max, 4
p7_saved_max:
	.zero	4
	.globl	_x_p7_saved_max
	.align 4
	.type	_x_p7_saved_max, @object
	.size	_x_p7_saved_max, 4
_x_p7_saved_max:
	.zero	4
	.globl	proposed18
	.align 4
	.type	proposed18, @object
	.size	proposed18, 4
proposed18:
	.zero	4
	.globl	_x_proposed18
	.align 4
	.type	_x_proposed18, @object
	.size	_x_proposed18, 4
_x_proposed18:
	.zero	4
	.globl	p12_x
	.align 4
	.type	p12_x, @object
	.size	p12_x, 4
p12_x:
	.zero	4
	.globl	_x_p12_x
	.align 4
	.type	_x_p12_x, @object
	.size	_x_p12_x, 4
_x_p12_x:
	.zero	4
	.globl	proposed13
	.align 4
	.type	proposed13, @object
	.size	proposed13, 4
proposed13:
	.zero	4
	.globl	_x_proposed13
	.align 4
	.type	_x_proposed13, @object
	.size	_x_proposed13, 4
_x_proposed13:
	.zero	4
	.globl	p7_l1
	.type	p7_l1, @object
	.size	p7_l1, 1
p7_l1:
	.zero	1
	.globl	_x_p7_l1
	.type	_x_p7_l1, @object
	.size	_x_p7_l1, 1
_x_p7_l1:
	.zero	1
	.globl	proposed10
	.align 4
	.type	proposed10, @object
	.size	proposed10, 4
proposed10:
	.zero	4
	.globl	_x_proposed10
	.align 4
	.type	_x_proposed10, @object
	.size	_x_proposed10, 4
_x_proposed10:
	.zero	4
	.globl	p12_l0
	.type	p12_l0, @object
	.size	p12_l0, 1
p12_l0:
	.zero	1
	.globl	_x_p12_l0
	.type	_x_p12_l0, @object
	.size	_x_p12_l0, 1
_x_p12_l0:
	.zero	1
	.globl	p9_l1
	.type	p9_l1, @object
	.size	p9_l1, 1
p9_l1:
	.zero	1
	.globl	_x_p9_l1
	.type	_x_p9_l1, @object
	.size	_x_p9_l1, 1
_x_p9_l1:
	.zero	1
	.globl	p14_l0
	.type	p14_l0, @object
	.size	p14_l0, 1
p14_l0:
	.zero	1
	.globl	_x_p14_l0
	.type	_x_p14_l0, @object
	.size	_x_p14_l0, 1
_x_p14_l0:
	.zero	1
	.globl	p10_saved_max
	.align 4
	.type	p10_saved_max, @object
	.size	p10_saved_max, 4
p10_saved_max:
	.zero	4
	.globl	_x_p10_saved_max
	.align 4
	.type	_x_p10_saved_max, @object
	.size	_x_p10_saved_max, 4
_x_p10_saved_max:
	.zero	4
	.globl	p15_x
	.align 4
	.type	p15_x, @object
	.size	p15_x, 4
p15_x:
	.zero	4
	.globl	_x_p15_x
	.align 4
	.type	_x_p15_x, @object
	.size	_x_p15_x, 4
_x_p15_x:
	.zero	4
	.globl	p10_l1
	.type	p10_l1, @object
	.size	p10_l1, 1
p10_l1:
	.zero	1
	.globl	_x_p10_l1
	.type	_x_p10_l1, @object
	.size	_x_p10_l1, 1
_x_p10_l1:
	.zero	1
	.globl	p15_l0
	.type	p15_l0, @object
	.size	p15_l0, 1
p15_l0:
	.zero	1
	.globl	_x_p15_l0
	.type	_x_p15_l0, @object
	.size	_x_p15_l0, 1
_x_p15_l0:
	.zero	1
	.globl	p11_l1
	.type	p11_l1, @object
	.size	p11_l1, 1
p11_l1:
	.zero	1
	.globl	_x_p11_l1
	.type	_x_p11_l1, @object
	.size	_x_p11_l1, 1
_x_p11_l1:
	.zero	1
	.globl	p16_l0
	.type	p16_l0, @object
	.size	p16_l0, 1
p16_l0:
	.zero	1
	.globl	_x_p16_l0
	.type	_x_p16_l0, @object
	.size	_x_p16_l0, 1
_x_p16_l0:
	.zero	1
	.globl	proposed19
	.align 4
	.type	proposed19, @object
	.size	proposed19, 4
proposed19:
	.zero	4
	.globl	_x_proposed19
	.align 4
	.type	_x_proposed19, @object
	.size	_x_proposed19, 4
_x_proposed19:
	.zero	4
	.globl	p12_saved_max
	.align 4
	.type	p12_saved_max, @object
	.size	p12_saved_max, 4
p12_saved_max:
	.zero	4
	.globl	_x_p12_saved_max
	.align 4
	.type	_x_p12_saved_max, @object
	.size	_x_p12_saved_max, 4
_x_p12_saved_max:
	.zero	4
	.globl	proposed16
	.align 4
	.type	proposed16, @object
	.size	proposed16, 4
proposed16:
	.zero	4
	.globl	_x_proposed16
	.align 4
	.type	_x_proposed16, @object
	.size	_x_proposed16, 4
_x_proposed16:
	.zero	4
	.globl	p17_x
	.align 4
	.type	p17_x, @object
	.size	p17_x, 4
p17_x:
	.zero	4
	.globl	_x_p17_x
	.align 4
	.type	_x_p17_x, @object
	.size	_x_p17_x, 4
_x_p17_x:
	.zero	4
	.globl	proposed11
	.align 4
	.type	proposed11, @object
	.size	proposed11, 4
proposed11:
	.zero	4
	.globl	_x_proposed11
	.align 4
	.type	_x_proposed11, @object
	.size	_x_proposed11, 4
_x_proposed11:
	.zero	4
	.globl	p12_l1
	.type	p12_l1, @object
	.size	p12_l1, 1
p12_l1:
	.zero	1
	.globl	_x_p12_l1
	.type	_x_p12_l1, @object
	.size	_x_p12_l1, 1
_x_p12_l1:
	.zero	1
	.globl	proposed8
	.align 4
	.type	proposed8, @object
	.size	proposed8, 4
proposed8:
	.zero	4
	.globl	_x_proposed8
	.align 4
	.type	_x_proposed8, @object
	.size	_x_proposed8, 4
_x_proposed8:
	.zero	4
	.globl	p17_l0
	.type	p17_l0, @object
	.size	p17_l0, 1
p17_l0:
	.zero	1
	.globl	_x_p17_l0
	.type	_x_p17_l0, @object
	.size	_x_p17_l0, 1
_x_p17_l0:
	.zero	1
	.globl	p14_l1
	.type	p14_l1, @object
	.size	p14_l1, 1
p14_l1:
	.zero	1
	.globl	_x_p14_l1
	.type	_x_p14_l1, @object
	.size	_x_p14_l1, 1
_x_p14_l1:
	.zero	1
	.globl	p19_l0
	.type	p19_l0, @object
	.size	p19_l0, 1
p19_l0:
	.zero	1
	.globl	_x_p19_l0
	.type	_x_p19_l0, @object
	.size	_x_p19_l0, 1
_x_p19_l0:
	.zero	1
	.globl	p15_saved_max
	.align 4
	.type	p15_saved_max, @object
	.size	p15_saved_max, 4
p15_saved_max:
	.zero	4
	.globl	_x_p15_saved_max
	.align 4
	.type	_x_p15_saved_max, @object
	.size	_x_p15_saved_max, 4
_x_p15_saved_max:
	.zero	4
	.globl	p20_x
	.align 4
	.type	p20_x, @object
	.size	p20_x, 4
p20_x:
	.zero	4
	.globl	_x_p20_x
	.align 4
	.type	_x_p20_x, @object
	.size	_x_p20_x, 4
_x_p20_x:
	.zero	4
	.globl	p15_l1
	.type	p15_l1, @object
	.size	p15_l1, 1
p15_l1:
	.zero	1
	.globl	_x_p15_l1
	.type	_x_p15_l1, @object
	.size	_x_p15_l1, 1
_x_p15_l1:
	.zero	1
	.globl	p20_l0
	.type	p20_l0, @object
	.size	p20_l0, 1
p20_l0:
	.zero	1
	.globl	_x_p20_l0
	.type	_x_p20_l0, @object
	.size	_x_p20_l0, 1
_x_p20_l0:
	.zero	1
	.globl	p16_saved_max
	.align 4
	.type	p16_saved_max, @object
	.size	p16_saved_max, 4
p16_saved_max:
	.zero	4
	.globl	_x_p16_saved_max
	.align 4
	.type	_x_p16_saved_max, @object
	.size	_x_p16_saved_max, 4
_x_p16_saved_max:
	.zero	4
	.globl	p1_l0
	.type	p1_l0, @object
	.size	p1_l0, 1
p1_l0:
	.zero	1
	.globl	_x_p1_l0
	.type	_x_p1_l0, @object
	.size	_x_p1_l0, 1
_x_p1_l0:
	.zero	1
	.globl	p21_x
	.align 4
	.type	p21_x, @object
	.size	p21_x, 4
p21_x:
	.zero	4
	.globl	_x_p21_x
	.align 4
	.type	_x_p21_x, @object
	.size	_x_p21_x, 4
_x_p21_x:
	.zero	4
	.globl	p16_l1
	.type	p16_l1, @object
	.size	p16_l1, 1
p16_l1:
	.zero	1
	.globl	_x_p16_l1
	.type	_x_p16_l1, @object
	.size	_x_p16_l1, 1
_x_p16_l1:
	.zero	1
	.globl	p21_l0
	.type	p21_l0, @object
	.size	p21_l0, 1
p21_l0:
	.zero	1
	.globl	_x_p21_l0
	.type	_x_p21_l0, @object
	.size	_x_p21_l0, 1
_x_p21_l0:
	.zero	1
	.globl	proposed17
	.align 4
	.type	proposed17, @object
	.size	proposed17, 4
proposed17:
	.zero	4
	.globl	_x_proposed17
	.align 4
	.type	_x_proposed17, @object
	.size	_x_proposed17, 4
_x_proposed17:
	.zero	4
	.globl	p17_saved_max
	.align 4
	.type	p17_saved_max, @object
	.size	p17_saved_max, 4
p17_saved_max:
	.zero	4
	.globl	_x_p17_saved_max
	.align 4
	.type	_x_p17_saved_max, @object
	.size	_x_p17_saved_max, 4
_x_p17_saved_max:
	.zero	4
	.globl	proposed9
	.align 4
	.type	proposed9, @object
	.size	proposed9, 4
proposed9:
	.zero	4
	.globl	_x_proposed9
	.align 4
	.type	_x_proposed9, @object
	.size	_x_proposed9, 4
_x_proposed9:
	.zero	4
	.globl	p17_l1
	.type	p17_l1, @object
	.size	p17_l1, 1
p17_l1:
	.zero	1
	.globl	_x_p17_l1
	.type	_x_p17_l1, @object
	.size	_x_p17_l1, 1
_x_p17_l1:
	.zero	1
	.globl	p19_l1
	.type	p19_l1, @object
	.size	p19_l1, 1
p19_l1:
	.zero	1
	.globl	_x_p19_l1
	.type	_x_p19_l1, @object
	.size	_x_p19_l1, 1
_x_p19_l1:
	.zero	1
	.globl	p20_saved_max
	.align 4
	.type	p20_saved_max, @object
	.size	p20_saved_max, 4
p20_saved_max:
	.zero	4
	.globl	_x_p20_saved_max
	.align 4
	.type	_x_p20_saved_max, @object
	.size	_x_p20_saved_max, 4
_x_p20_saved_max:
	.zero	4
	.globl	p20_l1
	.type	p20_l1, @object
	.size	p20_l1, 1
p20_l1:
	.zero	1
	.globl	_x_p20_l1
	.type	_x_p20_l1, @object
	.size	_x_p20_l1, 1
_x_p20_l1:
	.zero	1
	.globl	p1_l1
	.type	p1_l1, @object
	.size	p1_l1, 1
p1_l1:
	.zero	1
	.globl	_x_p1_l1
	.type	_x_p1_l1, @object
	.size	_x_p1_l1, 1
_x_p1_l1:
	.zero	1
	.globl	p21_saved_max
	.align 4
	.type	p21_saved_max, @object
	.size	p21_saved_max, 4
p21_saved_max:
	.zero	4
	.globl	_x_p21_saved_max
	.align 4
	.type	_x_p21_saved_max, @object
	.size	_x_p21_saved_max, 4
_x_p21_saved_max:
	.zero	4
	.globl	p21_l1
	.type	p21_l1, @object
	.size	p21_l1, 1
p21_l1:
	.zero	1
	.globl	_x_p21_l1
	.type	_x_p21_l1, @object
	.size	_x_p21_l1, 1
_x_p21_l1:
	.zero	1
	.text
	.globl	main
	.type	main, @function
main:
.LFB1:
	.cfi_startproc
	endbr64
	push	rbp
	.cfi_def_cfa_offset 16
	.cfi_offset 6, -16
	mov	rbp, rsp
	.cfi_def_cfa_register 6
	sub	rsp, 16
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p25_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p25_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p24_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p24_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p23_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p23_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p24_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p11_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p16_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p24_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p0_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p6_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p11_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p4_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p9_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p23_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p3_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed4[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p8_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p0_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p4_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p23_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p3_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed3[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p0_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed25[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed24[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn4[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id4[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed2[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn3[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p19_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR max_prop[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id3[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed1[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p14_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p19_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed0[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p3_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p8_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed12[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR turn1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p9_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p14_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR inc_max_prop[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR id0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed22[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p2_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed23[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p2_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed20[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p6_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed5[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p8_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p22_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed6[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p18_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p22_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed7[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p18_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p1_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p6_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p8_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p13_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p22_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed14[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p13_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p18_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p22_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p2_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed15[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p18_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p5_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p5_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p10_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p25_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p5_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p25_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p11_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed21[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p7_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed18[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p12_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed13[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p7_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed10[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p14_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p10_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p15_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p15_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p16_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed19[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p12_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed16[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p17_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed11[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p12_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed8[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p17_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p14_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p19_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p15_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p20_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p15_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p20_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p16_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p21_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p16_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p21_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed17[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p17_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR proposed9[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p17_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p19_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p20_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p20_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p1_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR p21_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR p21_l1[rip], al
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	jne	.L5
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	je	.L6
.L5:
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	je	.L7
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	je	.L6
.L7:
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	je	.L8
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	je	.L6
.L8:
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	je	.L4
.L6:
	movss	xmm0, DWORD PTR p25_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p25_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed25[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p25_x[rip]
	movss	xmm0, DWORD PTR proposed25[rip]
	comiss	xmm0, xmm1
	jnb	.L11
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	je	.L11
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	je	.L4
.L11:
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	jne	.L12
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	je	.L13
.L12:
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	je	.L14
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	je	.L13
.L14:
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	je	.L15
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	je	.L13
.L15:
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	je	.L4
.L13:
	movss	xmm0, DWORD PTR p24_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p24_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed24[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p24_x[rip]
	movss	xmm0, DWORD PTR proposed24[rip]
	comiss	xmm0, xmm1
	jnb	.L18
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	je	.L18
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	je	.L4
.L18:
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	jne	.L19
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	je	.L20
.L19:
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	je	.L21
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	je	.L20
.L21:
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	je	.L22
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	je	.L20
.L22:
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	je	.L4
.L20:
	movss	xmm0, DWORD PTR p23_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p23_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed23[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p23_x[rip]
	movss	xmm0, DWORD PTR proposed23[rip]
	comiss	xmm0, xmm1
	jnb	.L25
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	je	.L25
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	je	.L4
.L25:
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	jne	.L26
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	je	.L27
.L26:
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	je	.L28
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	je	.L27
.L28:
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	je	.L29
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	je	.L27
.L29:
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	je	.L4
.L27:
	movss	xmm0, DWORD PTR p22_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p22_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed22[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p22_x[rip]
	movss	xmm0, DWORD PTR proposed22[rip]
	comiss	xmm0, xmm1
	jnb	.L32
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	je	.L32
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	je	.L4
.L32:
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	jne	.L33
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	je	.L34
.L33:
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	je	.L35
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	je	.L34
.L35:
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	je	.L36
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	je	.L34
.L36:
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	je	.L4
.L34:
	movss	xmm0, DWORD PTR p21_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p21_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed21[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p21_x[rip]
	movss	xmm0, DWORD PTR proposed21[rip]
	comiss	xmm0, xmm1
	jnb	.L39
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	je	.L39
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	je	.L4
.L39:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	jne	.L40
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L41
.L40:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L42
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L41
.L42:
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L43
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L41
.L43:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L4
.L41:
	movss	xmm0, DWORD PTR p20_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed20[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p20_x[rip]
	movss	xmm0, DWORD PTR proposed20[rip]
	comiss	xmm0, xmm1
	jnb	.L46
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L46
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L4
.L46:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	jne	.L47
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L48
.L47:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L49
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L48
.L49:
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L50
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L48
.L50:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L4
.L48:
	movss	xmm0, DWORD PTR p19_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed19[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p19_x[rip]
	movss	xmm0, DWORD PTR proposed19[rip]
	comiss	xmm0, xmm1
	jnb	.L53
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L53
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L4
.L53:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	jne	.L54
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L55
.L54:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L56
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L55
.L56:
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L57
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L55
.L57:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L4
.L55:
	movss	xmm0, DWORD PTR p18_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed18[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p18_x[rip]
	movss	xmm0, DWORD PTR proposed18[rip]
	comiss	xmm0, xmm1
	jnb	.L60
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L60
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L4
.L60:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	jne	.L61
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L62
.L61:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L63
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L62
.L63:
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L64
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L62
.L64:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L4
.L62:
	movss	xmm0, DWORD PTR p17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed17[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p17_x[rip]
	movss	xmm0, DWORD PTR proposed17[rip]
	comiss	xmm0, xmm1
	jnb	.L67
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L67
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L4
.L67:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	jne	.L68
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L69
.L68:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L70
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L69
.L70:
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L71
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L69
.L71:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L4
.L69:
	movss	xmm0, DWORD PTR p16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed16[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p16_x[rip]
	movss	xmm0, DWORD PTR proposed16[rip]
	comiss	xmm0, xmm1
	jnb	.L74
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L74
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L4
.L74:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	jne	.L75
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L76
.L75:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L77
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L76
.L77:
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L78
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L76
.L78:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L4
.L76:
	movss	xmm0, DWORD PTR p15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed15[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p15_x[rip]
	movss	xmm0, DWORD PTR proposed15[rip]
	comiss	xmm0, xmm1
	jnb	.L81
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L81
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L4
.L81:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	jne	.L82
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L83
.L82:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L84
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L83
.L84:
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L85
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L83
.L85:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L4
.L83:
	movss	xmm0, DWORD PTR p14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed14[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p14_x[rip]
	movss	xmm0, DWORD PTR proposed14[rip]
	comiss	xmm0, xmm1
	jnb	.L88
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L88
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L4
.L88:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	jne	.L89
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L90
.L89:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L91
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L90
.L91:
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L92
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L90
.L92:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L4
.L90:
	movss	xmm0, DWORD PTR p13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed13[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p13_x[rip]
	movss	xmm0, DWORD PTR proposed13[rip]
	comiss	xmm0, xmm1
	jnb	.L95
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L95
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L4
.L95:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	jne	.L96
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L97
.L96:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L98
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L97
.L98:
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L99
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L97
.L99:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L4
.L97:
	movss	xmm0, DWORD PTR p12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed12[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p12_x[rip]
	movss	xmm0, DWORD PTR proposed12[rip]
	comiss	xmm0, xmm1
	jnb	.L102
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L102
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L4
.L102:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	jne	.L103
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L104
.L103:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L105
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L104
.L105:
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L106
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L104
.L106:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L4
.L104:
	movss	xmm0, DWORD PTR p11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed11[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p11_x[rip]
	movss	xmm0, DWORD PTR proposed11[rip]
	comiss	xmm0, xmm1
	jnb	.L109
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L109
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L4
.L109:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L110
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L111
.L110:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L112
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L111
.L112:
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L113
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L111
.L113:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L4
.L111:
	movss	xmm0, DWORD PTR p10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed10[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p10_x[rip]
	movss	xmm0, DWORD PTR proposed10[rip]
	comiss	xmm0, xmm1
	jnb	.L116
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L116
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L4
.L116:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L117
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L118
.L117:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L119
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L118
.L119:
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L120
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L118
.L120:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L4
.L118:
	movss	xmm0, DWORD PTR p9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed9[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p9_x[rip]
	movss	xmm0, DWORD PTR proposed9[rip]
	comiss	xmm0, xmm1
	jnb	.L123
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L123
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L4
.L123:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L124
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L125
.L124:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L126
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L125
.L126:
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L127
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L125
.L127:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L4
.L125:
	movss	xmm0, DWORD PTR p8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed8[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p8_x[rip]
	movss	xmm0, DWORD PTR proposed8[rip]
	comiss	xmm0, xmm1
	jnb	.L130
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L130
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L4
.L130:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L131
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L132
.L131:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L133
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L132
.L133:
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L134
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L132
.L134:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L4
.L132:
	movss	xmm0, DWORD PTR p7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed7[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p7_x[rip]
	movss	xmm0, DWORD PTR proposed7[rip]
	comiss	xmm0, xmm1
	jnb	.L137
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L137
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L4
.L137:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L138
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L139
.L138:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L140
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L139
.L140:
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L141
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L139
.L141:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L4
.L139:
	movss	xmm0, DWORD PTR p6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed6[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p6_x[rip]
	movss	xmm0, DWORD PTR proposed6[rip]
	comiss	xmm0, xmm1
	jnb	.L144
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L144
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L4
.L144:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L145
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L146
.L145:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L147
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L146
.L147:
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L148
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L146
.L148:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L4
.L146:
	movss	xmm0, DWORD PTR p5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed5[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p5_x[rip]
	movss	xmm0, DWORD PTR proposed5[rip]
	comiss	xmm0, xmm1
	jnb	.L151
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L151
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L4
.L151:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L152
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L153
.L152:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L154
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L153
.L154:
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L155
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L153
.L155:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L4
.L153:
	movss	xmm0, DWORD PTR p4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed4[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p4_x[rip]
	movss	xmm0, DWORD PTR proposed4[rip]
	comiss	xmm0, xmm1
	jnb	.L158
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L158
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L4
.L158:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L159
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L160
.L159:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L161
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L160
.L161:
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L162
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L160
.L162:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L4
.L160:
	movss	xmm0, DWORD PTR p3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed3[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p3_x[rip]
	movss	xmm0, DWORD PTR proposed3[rip]
	comiss	xmm0, xmm1
	jnb	.L165
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L165
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L4
.L165:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L166
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L167
.L166:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L168
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L167
.L168:
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L169
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L167
.L169:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L4
.L167:
	movss	xmm0, DWORD PTR p2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed2[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p2_x[rip]
	movss	xmm0, DWORD PTR proposed2[rip]
	comiss	xmm0, xmm1
	jnb	.L172
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L172
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L4
.L172:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L173
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L174
.L173:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L175
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L174
.L175:
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L176
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L174
.L176:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L4
.L174:
	movss	xmm0, DWORD PTR p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed1[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p1_x[rip]
	movss	xmm0, DWORD PTR proposed1[rip]
	comiss	xmm0, xmm1
	jnb	.L179
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L179
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L4
.L179:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L180
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L181
.L180:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L182
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L181
.L182:
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L183
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L181
.L183:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L4
.L181:
	movss	xmm0, DWORD PTR p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L4
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	movss	xmm1, DWORD PTR proposed0[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L4
	movss	xmm1, DWORD PTR p0_x[rip]
	movss	xmm0, DWORD PTR proposed0[rip]
	comiss	xmm0, xmm1
	jnb	.L186
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L186
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L4
.L186:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L187
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L187
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L188
.L187:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L189
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L189
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L189:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L190
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L190
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L190:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L191
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L191
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L191
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L191
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L188
.L191:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L192
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L192
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L188
.L192:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L193
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L193
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L193:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L194
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L194
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L194:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L195
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L195
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L195
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L195
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L188
.L195:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L196
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L196
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L196
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L188
.L196:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L197
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L197
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L197
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L197
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L197:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	je	.L198
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L198
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L198:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L199
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L199
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L199
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L199
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L188
.L199:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L200
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L200
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L188
.L200:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L201
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L201
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L201:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L202
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L202
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L202
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L202
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L202:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L203
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L203
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L188
.L203:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L204
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L204
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L204
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L188
.L204:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L205
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L205
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L205:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	je	.L206
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L206
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L206:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L207
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L207
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L207
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L188
.L207:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L208
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L208
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L208
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L188
.L208:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L209
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L209
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L209
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L209
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L209:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	je	.L210
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L210
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L210:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L211
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L211
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L188
.L211:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L212
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L212
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L212
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L212
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L188
.L212:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L213
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L213
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L213
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L213
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	je	.L188
.L213:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L4
.L188:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L214
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L214
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L214:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L216
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L216
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L216
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L216:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L217
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L217
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L215
.L217:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L218
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L218
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L218
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L218
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L215
.L218:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L219
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L219
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L219:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L220
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L220
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L220
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L220:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L221
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L221
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L221
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L215
.L221:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L222
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L222
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L215
.L222:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L223
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L223
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L223
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L223
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L223:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L224
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L224
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L224:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L225
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L225
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L215
.L225:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L226
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L226
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L215
.L226:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L227
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L227
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L227:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L228
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L228
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L228
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L228:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L229
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L229
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L229
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L215
.L229:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L230
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L230
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L230
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L215
.L230:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L231
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L231
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L231
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L231
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L231:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L232
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L232
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L232:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L233
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L233
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L233
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L215
.L233:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L234
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L234
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L234
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L234
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L215
.L234:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L235
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L235
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L235:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L236
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L236
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L236
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L236
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L236:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L237
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L237
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L237
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L237
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L215
.L237:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L238
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L238
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L238
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L238
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L215
.L238:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L239
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L239
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L239
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L239
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L215
.L239:
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L4
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L4
.L215:
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	jne	.L4
	movzx	eax, BYTE PTR inc_max_prop[rip]
	test	al, al
	je	.L4
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed0[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed1[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed2[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed3[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed4[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed5[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed6[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed7[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed8[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed9[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed10[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed11[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed12[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed13[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed14[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed15[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed16[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed17[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed18[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed19[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed20[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed21[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed22[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed23[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed24[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm1, DWORD PTR proposed25[rip]
	movss	xmm0, DWORD PTR max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L4
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1428
	ucomiss	xmm0, xmm1
	je	.L267
.L1428:
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1429
	ucomiss	xmm0, xmm1
	je	.L267
.L1429:
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1430
	ucomiss	xmm0, xmm1
	je	.L267
.L1430:
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1431
	ucomiss	xmm0, xmm1
	je	.L267
.L1431:
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1432
	ucomiss	xmm0, xmm1
	je	.L267
.L1432:
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1433
	ucomiss	xmm0, xmm1
	je	.L267
.L1433:
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1434
	ucomiss	xmm0, xmm1
	je	.L267
.L1434:
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1435
	ucomiss	xmm0, xmm1
	je	.L267
.L1435:
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1436
	ucomiss	xmm0, xmm1
	je	.L267
.L1436:
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1437
	ucomiss	xmm0, xmm1
	je	.L267
.L1437:
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1438
	ucomiss	xmm0, xmm1
	je	.L267
.L1438:
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1439
	ucomiss	xmm0, xmm1
	je	.L267
.L1439:
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1440
	ucomiss	xmm0, xmm1
	je	.L267
.L1440:
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1441
	ucomiss	xmm0, xmm1
	je	.L267
.L1441:
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1442
	ucomiss	xmm0, xmm1
	je	.L267
.L1442:
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1443
	ucomiss	xmm0, xmm1
	je	.L267
.L1443:
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1444
	ucomiss	xmm0, xmm1
	je	.L267
.L1444:
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1445
	ucomiss	xmm0, xmm1
	je	.L267
.L1445:
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1446
	ucomiss	xmm0, xmm1
	je	.L267
.L1446:
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1447
	ucomiss	xmm0, xmm1
	je	.L267
.L1447:
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1448
	ucomiss	xmm0, xmm1
	je	.L267
.L1448:
	movss	xmm0, DWORD PTR proposed21[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1449
	ucomiss	xmm0, xmm1
	je	.L267
.L1449:
	movss	xmm0, DWORD PTR proposed22[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1450
	ucomiss	xmm0, xmm1
	je	.L267
.L1450:
	movss	xmm0, DWORD PTR proposed23[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1451
	ucomiss	xmm0, xmm1
	je	.L267
.L1451:
	movss	xmm0, DWORD PTR proposed24[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1452
	ucomiss	xmm0, xmm1
	je	.L267
.L1452:
	movss	xmm0, DWORD PTR proposed25[rip]
	movss	xmm1, DWORD PTR max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
.L267:
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L4
	ucomiss	xmm0, xmm1
	jne	.L4
	mov	eax, 1
	jmp	.L295
.L4:
	mov	eax, 0
.L295:
	mov	DWORD PTR -4[rbp], eax
	jmp	.L296
.L1347:
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p25_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p25_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p24_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p24_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p23_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p23_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p24_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p4_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p9_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p11_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p16_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p24_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p4_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p0_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p6_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p11_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p4_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p9_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p23_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p3_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed4[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p8_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p0_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p4_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p23_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p3_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed3[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p0_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed25[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed24[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn4[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_delta[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id4[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed2[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn3[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p19_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_max_prop[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id3[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed1[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p14_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p19_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id2[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed0[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p3_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p8_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed12[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p7_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_turn1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p9_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p14_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_inc_max_prop[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p3_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_id0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed22[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p2_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed23[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p2_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed20[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p7_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p6_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed5[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p8_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p13_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p22_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed6[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p13_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p18_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p22_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed7[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p18_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p1_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p1_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p6_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p8_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p13_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x__diverge_delta[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p22_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed14[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p13_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p18_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p22_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p2_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed15[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p18_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p5_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p5_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p10_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p25_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p5_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p25_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p5_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p10_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p6_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p11_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed21[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p7_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed18[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p12_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed13[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p7_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed10[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p12_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p9_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p14_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p10_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p15_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p10_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p15_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p11_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p16_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed19[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p12_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed16[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p17_x[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed11[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p12_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed8[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p17_l0[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p14_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p19_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p15_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p20_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p15_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p20_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p16_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p21_x[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p16_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p21_l0[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed17[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p17_saved_max[rip], eax
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_proposed9[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p17_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p19_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p20_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p20_l1[rip], al
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p1_l1[rip], al
	call	__VERIFIER_nondet_float@PLT
	movd	eax, xmm0
	mov	DWORD PTR _x_p21_saved_max[rip], eax
	call	__VERIFIER_nondet_bool
	mov	BYTE PTR _x_p21_l1[rip], al
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	jne	.L297
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	je	.L298
.L297:
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	je	.L299
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	je	.L298
.L299:
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	je	.L300
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	je	.L298
.L300:
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	je	.L301
.L298:
	movss	xmm1, DWORD PTR _x_proposed25[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p25_x[rip]
	movss	xmm0, DWORD PTR _x_proposed25[rip]
	comiss	xmm0, xmm1
	jnb	.L302
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	je	.L302
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	je	.L301
.L302:
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L303
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L303
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p25_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p25_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L303
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L303
	movss	xmm0, DWORD PTR p25_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p25_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L303
	ucomiss	xmm0, xmm1
	jne	.L303
	movss	xmm0, DWORD PTR proposed25[rip]
	movss	xmm1, DWORD PTR _x_proposed25[rip]
	ucomiss	xmm0, xmm1
	jp	.L303
	ucomiss	xmm0, xmm1
	je	.L306
.L303:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L306:
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	jne	.L309
	movss	xmm0, DWORD PTR _x_p25_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L309
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L309
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L309
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L309
	movss	xmm0, DWORD PTR proposed25[rip]
	movss	xmm1, DWORD PTR _x_proposed25[rip]
	ucomiss	xmm0, xmm1
	jp	.L309
	ucomiss	xmm0, xmm1
	jne	.L309
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p25_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L309
	ucomiss	xmm0, xmm1
	je	.L312
.L309:
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	jne	.L312
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	jne	.L312
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L312
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L312
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L312
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L312
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L312:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p25_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L315
	ucomiss	xmm0, xmm1
	jne	.L315
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	jne	.L315
	movss	xmm0, DWORD PTR _x_p25_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L315
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L315
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L315
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L315
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L315
	movss	xmm0, DWORD PTR proposed25[rip]
	movss	xmm1, DWORD PTR _x_proposed25[rip]
	ucomiss	xmm0, xmm1
	jp	.L315
	ucomiss	xmm0, xmm1
	je	.L318
.L315:
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	je	.L318
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	jne	.L318
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L318
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L318
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L318
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L318
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L318
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L318
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L318:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L321
	movss	xmm0, DWORD PTR proposed25[rip]
	movss	xmm1, DWORD PTR _x_proposed25[rip]
	ucomiss	xmm0, xmm1
	jp	.L321
	ucomiss	xmm0, xmm1
	jne	.L321
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p25_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L321
	ucomiss	xmm0, xmm1
	jne	.L321
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	jne	.L324
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	jne	.L324
	movss	xmm0, DWORD PTR _x_p25_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L324
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L325
.L324:
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	je	.L321
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	je	.L321
	movss	xmm0, DWORD PTR p25_x[rip]
	movss	xmm1, DWORD PTR _x_p25_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L321
	ucomiss	xmm0, xmm1
	je	.L325
.L321:
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	jne	.L325
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L325
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L325
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L325
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L325
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L325:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p25_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L329
	ucomiss	xmm0, xmm1
	jne	.L329
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	test	al, al
	jne	.L329
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	test	al, al
	jne	.L329
	movss	xmm0, DWORD PTR p25_x[rip]
	movss	xmm1, DWORD PTR _x_p25_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L329
	ucomiss	xmm0, xmm1
	jne	.L329
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L329
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L329
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L329
	movss	xmm1, DWORD PTR proposed25[rip]
	movss	xmm0, DWORD PTR _x_proposed25[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L332
.L329:
	movzx	eax, BYTE PTR p25_l0[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR p25_l1[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L332
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L332
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L332
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L332
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L332:
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	jne	.L334
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	je	.L335
.L334:
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	je	.L336
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	je	.L335
.L336:
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	je	.L337
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	je	.L335
.L337:
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	je	.L301
.L335:
	movss	xmm1, DWORD PTR _x_proposed24[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p24_x[rip]
	movss	xmm0, DWORD PTR _x_proposed24[rip]
	comiss	xmm0, xmm1
	jnb	.L338
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	je	.L338
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	je	.L301
.L338:
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L339
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L339
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p24_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p24_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L339
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L339
	movss	xmm0, DWORD PTR p24_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p24_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L339
	ucomiss	xmm0, xmm1
	jne	.L339
	movss	xmm0, DWORD PTR proposed24[rip]
	movss	xmm1, DWORD PTR _x_proposed24[rip]
	ucomiss	xmm0, xmm1
	jp	.L339
	ucomiss	xmm0, xmm1
	je	.L342
.L339:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L342:
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	jne	.L345
	movss	xmm0, DWORD PTR _x_p24_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L345
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L345
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L345
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L345
	movss	xmm0, DWORD PTR proposed24[rip]
	movss	xmm1, DWORD PTR _x_proposed24[rip]
	ucomiss	xmm0, xmm1
	jp	.L345
	ucomiss	xmm0, xmm1
	jne	.L345
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p24_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L345
	ucomiss	xmm0, xmm1
	je	.L348
.L345:
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	jne	.L348
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	jne	.L348
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L348
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L348
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L348
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L348
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L348
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L348
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L348:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p24_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L351
	ucomiss	xmm0, xmm1
	jne	.L351
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	je	.L351
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	jne	.L351
	movss	xmm0, DWORD PTR _x_p24_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L351
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L351
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L351
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L351
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L351
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L351
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L351
	movss	xmm0, DWORD PTR proposed24[rip]
	movss	xmm1, DWORD PTR _x_proposed24[rip]
	ucomiss	xmm0, xmm1
	jp	.L351
	ucomiss	xmm0, xmm1
	je	.L354
.L351:
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	je	.L354
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	jne	.L354
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L354
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L354
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L354
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L354
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L354
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L354
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L354:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L357
	movss	xmm0, DWORD PTR proposed24[rip]
	movss	xmm1, DWORD PTR _x_proposed24[rip]
	ucomiss	xmm0, xmm1
	jp	.L357
	ucomiss	xmm0, xmm1
	jne	.L357
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p24_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L357
	ucomiss	xmm0, xmm1
	jne	.L357
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	jne	.L360
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	jne	.L360
	movss	xmm0, DWORD PTR _x_p24_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L360
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L361
.L360:
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	je	.L357
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	je	.L357
	movss	xmm0, DWORD PTR p24_x[rip]
	movss	xmm1, DWORD PTR _x_p24_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L357
	ucomiss	xmm0, xmm1
	je	.L361
.L357:
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	je	.L361
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	jne	.L361
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L361
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L361
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L361
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L361
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L361
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L361
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L361:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p24_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L365
	ucomiss	xmm0, xmm1
	jne	.L365
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	test	al, al
	jne	.L365
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	test	al, al
	jne	.L365
	movss	xmm0, DWORD PTR p24_x[rip]
	movss	xmm1, DWORD PTR _x_p24_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L365
	ucomiss	xmm0, xmm1
	jne	.L365
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L365
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L365
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L365
	movss	xmm1, DWORD PTR proposed24[rip]
	movss	xmm0, DWORD PTR _x_proposed24[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L368
.L365:
	movzx	eax, BYTE PTR p24_l0[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR p24_l1[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L368
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L368
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L368
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L368
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L368
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L368:
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	jne	.L370
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	je	.L371
.L370:
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	je	.L372
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	je	.L371
.L372:
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	je	.L373
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	je	.L371
.L373:
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	je	.L301
.L371:
	movss	xmm1, DWORD PTR _x_proposed23[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p23_x[rip]
	movss	xmm0, DWORD PTR _x_proposed23[rip]
	comiss	xmm0, xmm1
	jnb	.L374
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	je	.L374
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	je	.L301
.L374:
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L375
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L375
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p23_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p23_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L375
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L375
	movss	xmm0, DWORD PTR p23_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p23_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L375
	ucomiss	xmm0, xmm1
	jne	.L375
	movss	xmm0, DWORD PTR proposed23[rip]
	movss	xmm1, DWORD PTR _x_proposed23[rip]
	ucomiss	xmm0, xmm1
	jp	.L375
	ucomiss	xmm0, xmm1
	je	.L378
.L375:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
.L378:
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	jne	.L381
	movss	xmm0, DWORD PTR _x_p23_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L381
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L381
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L381
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L381
	movss	xmm0, DWORD PTR proposed23[rip]
	movss	xmm1, DWORD PTR _x_proposed23[rip]
	ucomiss	xmm0, xmm1
	jp	.L381
	ucomiss	xmm0, xmm1
	jne	.L381
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p23_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L381
	ucomiss	xmm0, xmm1
	je	.L384
.L381:
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	jne	.L384
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	jne	.L384
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L384
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L384
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L384
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L384
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L384
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L384
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L384:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p23_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L387
	ucomiss	xmm0, xmm1
	jne	.L387
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	je	.L387
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	jne	.L387
	movss	xmm0, DWORD PTR _x_p23_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L387
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L387
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L387
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L387
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L387
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L387
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L387
	movss	xmm0, DWORD PTR proposed23[rip]
	movss	xmm1, DWORD PTR _x_proposed23[rip]
	ucomiss	xmm0, xmm1
	jp	.L387
	ucomiss	xmm0, xmm1
	je	.L390
.L387:
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	je	.L390
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	jne	.L390
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L390
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L390
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L390
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L390
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L390
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L390
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L390:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L393
	movss	xmm0, DWORD PTR proposed23[rip]
	movss	xmm1, DWORD PTR _x_proposed23[rip]
	ucomiss	xmm0, xmm1
	jp	.L393
	ucomiss	xmm0, xmm1
	jne	.L393
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p23_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L393
	ucomiss	xmm0, xmm1
	jne	.L393
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	jne	.L396
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	jne	.L396
	movss	xmm0, DWORD PTR _x_p23_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L396
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L397
.L396:
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	je	.L393
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	je	.L393
	movss	xmm0, DWORD PTR p23_x[rip]
	movss	xmm1, DWORD PTR _x_p23_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L393
	ucomiss	xmm0, xmm1
	je	.L397
.L393:
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	je	.L397
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	jne	.L397
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L397
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L397
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L397
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L397
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L397
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L397
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L397:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p23_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L401
	ucomiss	xmm0, xmm1
	jne	.L401
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	test	al, al
	jne	.L401
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	test	al, al
	jne	.L401
	movss	xmm0, DWORD PTR p23_x[rip]
	movss	xmm1, DWORD PTR _x_p23_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L401
	ucomiss	xmm0, xmm1
	jne	.L401
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L401
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L401
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L401
	movss	xmm1, DWORD PTR proposed23[rip]
	movss	xmm0, DWORD PTR _x_proposed23[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L404
.L401:
	movzx	eax, BYTE PTR p23_l0[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR p23_l1[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L404
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L404
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L404
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L404
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L404:
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	jne	.L406
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	je	.L407
.L406:
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	je	.L408
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	je	.L407
.L408:
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	je	.L409
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	je	.L407
.L409:
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	je	.L301
.L407:
	movss	xmm1, DWORD PTR _x_proposed22[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p22_x[rip]
	movss	xmm0, DWORD PTR _x_proposed22[rip]
	comiss	xmm0, xmm1
	jnb	.L410
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	je	.L410
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	je	.L301
.L410:
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L411
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L411
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p22_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p22_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L411
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L411
	movss	xmm0, DWORD PTR p22_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p22_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L411
	ucomiss	xmm0, xmm1
	jne	.L411
	movss	xmm0, DWORD PTR proposed22[rip]
	movss	xmm1, DWORD PTR _x_proposed22[rip]
	ucomiss	xmm0, xmm1
	jp	.L411
	ucomiss	xmm0, xmm1
	je	.L414
.L411:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
.L414:
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	jne	.L417
	movss	xmm0, DWORD PTR _x_p22_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L417
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L417
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L417
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L417
	movss	xmm0, DWORD PTR proposed22[rip]
	movss	xmm1, DWORD PTR _x_proposed22[rip]
	ucomiss	xmm0, xmm1
	jp	.L417
	ucomiss	xmm0, xmm1
	jne	.L417
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p22_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L417
	ucomiss	xmm0, xmm1
	je	.L420
.L417:
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	jne	.L420
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	jne	.L420
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L420
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L420
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L420
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L420
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L420
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L420
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L420:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p22_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L423
	ucomiss	xmm0, xmm1
	jne	.L423
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	je	.L423
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	jne	.L423
	movss	xmm0, DWORD PTR _x_p22_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L423
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L423
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L423
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L423
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L423
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L423
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L423
	movss	xmm0, DWORD PTR proposed22[rip]
	movss	xmm1, DWORD PTR _x_proposed22[rip]
	ucomiss	xmm0, xmm1
	jp	.L423
	ucomiss	xmm0, xmm1
	je	.L426
.L423:
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	je	.L426
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	jne	.L426
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L426
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L426
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L426
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L426
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L426
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L426
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L426:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L429
	movss	xmm0, DWORD PTR proposed22[rip]
	movss	xmm1, DWORD PTR _x_proposed22[rip]
	ucomiss	xmm0, xmm1
	jp	.L429
	ucomiss	xmm0, xmm1
	jne	.L429
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p22_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L429
	ucomiss	xmm0, xmm1
	jne	.L429
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	jne	.L432
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	jne	.L432
	movss	xmm0, DWORD PTR _x_p22_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L432
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L433
.L432:
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	je	.L429
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	je	.L429
	movss	xmm0, DWORD PTR p22_x[rip]
	movss	xmm1, DWORD PTR _x_p22_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L429
	ucomiss	xmm0, xmm1
	je	.L433
.L429:
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	jne	.L433
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L433
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L433
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L433
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L433
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L433:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p22_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L437
	ucomiss	xmm0, xmm1
	jne	.L437
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	test	al, al
	jne	.L437
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	test	al, al
	jne	.L437
	movss	xmm0, DWORD PTR p22_x[rip]
	movss	xmm1, DWORD PTR _x_p22_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L437
	ucomiss	xmm0, xmm1
	jne	.L437
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L437
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L437
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L437
	movss	xmm1, DWORD PTR proposed22[rip]
	movss	xmm0, DWORD PTR _x_proposed22[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L440
.L437:
	movzx	eax, BYTE PTR p22_l0[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR p22_l1[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L440
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L440
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L440
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L440
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L440:
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	jne	.L442
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	je	.L443
.L442:
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	je	.L444
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	je	.L443
.L444:
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	je	.L445
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	je	.L443
.L445:
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	je	.L301
.L443:
	movss	xmm1, DWORD PTR _x_proposed21[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p21_x[rip]
	movss	xmm0, DWORD PTR _x_proposed21[rip]
	comiss	xmm0, xmm1
	jnb	.L446
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	je	.L446
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	je	.L301
.L446:
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L447
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L447
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p21_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p21_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L447
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L447
	movss	xmm0, DWORD PTR p21_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p21_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L447
	ucomiss	xmm0, xmm1
	jne	.L447
	movss	xmm0, DWORD PTR proposed21[rip]
	movss	xmm1, DWORD PTR _x_proposed21[rip]
	ucomiss	xmm0, xmm1
	jp	.L447
	ucomiss	xmm0, xmm1
	je	.L450
.L447:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L450:
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	je	.L453
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	jne	.L453
	movss	xmm0, DWORD PTR _x_p21_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L453
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L453
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L453
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L453
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L453
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L453
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L453
	movss	xmm0, DWORD PTR proposed21[rip]
	movss	xmm1, DWORD PTR _x_proposed21[rip]
	ucomiss	xmm0, xmm1
	jp	.L453
	ucomiss	xmm0, xmm1
	jne	.L453
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p21_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L453
	ucomiss	xmm0, xmm1
	je	.L456
.L453:
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	jne	.L456
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	jne	.L456
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L456
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L456
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L456
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L456
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L456
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L456
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L456:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p21_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L459
	ucomiss	xmm0, xmm1
	jne	.L459
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	je	.L459
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	jne	.L459
	movss	xmm0, DWORD PTR _x_p21_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L459
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L459
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L459
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L459
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L459
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L459
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L459
	movss	xmm0, DWORD PTR proposed21[rip]
	movss	xmm1, DWORD PTR _x_proposed21[rip]
	ucomiss	xmm0, xmm1
	jp	.L459
	ucomiss	xmm0, xmm1
	je	.L462
.L459:
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	je	.L462
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	jne	.L462
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L462
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L462
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L462
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L462
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L462
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L462
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L462:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L465
	movss	xmm0, DWORD PTR proposed21[rip]
	movss	xmm1, DWORD PTR _x_proposed21[rip]
	ucomiss	xmm0, xmm1
	jp	.L465
	ucomiss	xmm0, xmm1
	jne	.L465
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p21_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L465
	ucomiss	xmm0, xmm1
	jne	.L465
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	jne	.L468
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	jne	.L468
	movss	xmm0, DWORD PTR _x_p21_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L468
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L469
.L468:
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	je	.L465
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	je	.L465
	movss	xmm0, DWORD PTR p21_x[rip]
	movss	xmm1, DWORD PTR _x_p21_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L465
	ucomiss	xmm0, xmm1
	je	.L469
.L465:
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	jne	.L469
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L469
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L469
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L469
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L469
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L469:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p21_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L473
	ucomiss	xmm0, xmm1
	jne	.L473
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	test	al, al
	jne	.L473
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	test	al, al
	jne	.L473
	movss	xmm0, DWORD PTR p21_x[rip]
	movss	xmm1, DWORD PTR _x_p21_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L473
	ucomiss	xmm0, xmm1
	jne	.L473
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L473
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L473
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L473
	movss	xmm1, DWORD PTR proposed21[rip]
	movss	xmm0, DWORD PTR _x_proposed21[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L476
.L473:
	movzx	eax, BYTE PTR p21_l0[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR p21_l1[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L476
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L476
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L476
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L476
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L476:
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	jne	.L478
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L479
.L478:
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L480
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L479
.L480:
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L481
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L479
.L481:
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L301
.L479:
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p20_x[rip]
	movss	xmm0, DWORD PTR _x_proposed20[rip]
	comiss	xmm0, xmm1
	jnb	.L482
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L482
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L301
.L482:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L483
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L483
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p20_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p20_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L483
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L483
	movss	xmm0, DWORD PTR p20_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L483
	ucomiss	xmm0, xmm1
	jne	.L483
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	ucomiss	xmm0, xmm1
	jp	.L483
	ucomiss	xmm0, xmm1
	je	.L486
.L483:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L486:
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	jne	.L489
	movss	xmm0, DWORD PTR _x_p20_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L489
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L489
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L489
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L489
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	ucomiss	xmm0, xmm1
	jp	.L489
	ucomiss	xmm0, xmm1
	jne	.L489
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L489
	ucomiss	xmm0, xmm1
	je	.L492
.L489:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	jne	.L492
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	jne	.L492
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L492
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L492
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L492
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L492
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L492
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L492
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L492:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L495
	ucomiss	xmm0, xmm1
	jne	.L495
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	jne	.L495
	movss	xmm0, DWORD PTR _x_p20_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L495
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L495
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L495
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L495
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L495
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L495
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	ucomiss	xmm0, xmm1
	jp	.L495
	ucomiss	xmm0, xmm1
	je	.L498
.L495:
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L498
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	jne	.L498
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L498
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L498
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L498
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L498
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L498
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L498
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L498:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L501
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L501
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L501
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L501
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L501
	movss	xmm0, DWORD PTR proposed20[rip]
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	ucomiss	xmm0, xmm1
	jp	.L501
	ucomiss	xmm0, xmm1
	jne	.L501
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L501
	ucomiss	xmm0, xmm1
	jne	.L501
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	jne	.L504
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	jne	.L504
	movss	xmm0, DWORD PTR _x_p20_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L504
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L505
.L504:
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	je	.L501
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	je	.L501
	movss	xmm0, DWORD PTR p20_x[rip]
	movss	xmm1, DWORD PTR _x_p20_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L501
	ucomiss	xmm0, xmm1
	je	.L505
.L501:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	jne	.L505
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L505
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L505
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L505
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L505
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L505
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L505:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p20_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L509
	ucomiss	xmm0, xmm1
	jne	.L509
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	test	al, al
	jne	.L509
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	test	al, al
	jne	.L509
	movss	xmm0, DWORD PTR p20_x[rip]
	movss	xmm1, DWORD PTR _x_p20_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L509
	ucomiss	xmm0, xmm1
	jne	.L509
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L509
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L509
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L509
	movss	xmm1, DWORD PTR proposed20[rip]
	movss	xmm0, DWORD PTR _x_proposed20[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L512
.L509:
	movzx	eax, BYTE PTR p20_l0[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR p20_l1[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L512
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L512
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L512
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L512
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L512
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L512:
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	jne	.L514
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L515
.L514:
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L516
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L515
.L516:
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L517
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L515
.L517:
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L301
.L515:
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p19_x[rip]
	movss	xmm0, DWORD PTR _x_proposed19[rip]
	comiss	xmm0, xmm1
	jnb	.L518
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L518
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L301
.L518:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L519
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L519
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p19_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p19_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L519
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L519
	movss	xmm0, DWORD PTR p19_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L519
	ucomiss	xmm0, xmm1
	jne	.L519
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	ucomiss	xmm0, xmm1
	jp	.L519
	ucomiss	xmm0, xmm1
	je	.L522
.L519:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
.L522:
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	jne	.L525
	movss	xmm0, DWORD PTR _x_p19_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L525
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L525
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L525
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L525
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	ucomiss	xmm0, xmm1
	jp	.L525
	ucomiss	xmm0, xmm1
	jne	.L525
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L525
	ucomiss	xmm0, xmm1
	je	.L528
.L525:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	jne	.L528
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	jne	.L528
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L528
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L528
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L528
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L528
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L528
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L528
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L528:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L531
	ucomiss	xmm0, xmm1
	jne	.L531
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L531
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	jne	.L531
	movss	xmm0, DWORD PTR _x_p19_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L531
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L531
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L531
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L531
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L531
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L531
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L531
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	ucomiss	xmm0, xmm1
	jp	.L531
	ucomiss	xmm0, xmm1
	je	.L534
.L531:
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L534
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L534
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L534
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L534
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L534
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L534
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L534:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L537
	movss	xmm0, DWORD PTR proposed19[rip]
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	ucomiss	xmm0, xmm1
	jp	.L537
	ucomiss	xmm0, xmm1
	jne	.L537
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L537
	ucomiss	xmm0, xmm1
	jne	.L537
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	jne	.L540
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	jne	.L540
	movss	xmm0, DWORD PTR _x_p19_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L540
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L541
.L540:
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	je	.L537
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	je	.L537
	movss	xmm0, DWORD PTR p19_x[rip]
	movss	xmm1, DWORD PTR _x_p19_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L537
	ucomiss	xmm0, xmm1
	je	.L541
.L537:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L541
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	jne	.L541
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L541
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L541
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L541
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L541
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L541
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L541
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L541:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p19_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L545
	ucomiss	xmm0, xmm1
	jne	.L545
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	test	al, al
	jne	.L545
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	test	al, al
	jne	.L545
	movss	xmm0, DWORD PTR p19_x[rip]
	movss	xmm1, DWORD PTR _x_p19_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L545
	ucomiss	xmm0, xmm1
	jne	.L545
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L545
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L545
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L545
	movss	xmm1, DWORD PTR proposed19[rip]
	movss	xmm0, DWORD PTR _x_proposed19[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L548
.L545:
	movzx	eax, BYTE PTR p19_l0[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR p19_l1[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L548
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L548
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L548
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L548
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L548
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L548:
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	jne	.L550
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L551
.L550:
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L552
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L551
.L552:
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L553
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L551
.L553:
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L301
.L551:
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p18_x[rip]
	movss	xmm0, DWORD PTR _x_proposed18[rip]
	comiss	xmm0, xmm1
	jnb	.L554
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L554
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L301
.L554:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L555
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L555
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p18_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p18_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L555
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L555
	movss	xmm0, DWORD PTR p18_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L555
	ucomiss	xmm0, xmm1
	jne	.L555
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	ucomiss	xmm0, xmm1
	jp	.L555
	ucomiss	xmm0, xmm1
	je	.L558
.L555:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
.L558:
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	jne	.L561
	movss	xmm0, DWORD PTR _x_p18_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L561
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L561
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L561
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L561
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	ucomiss	xmm0, xmm1
	jp	.L561
	ucomiss	xmm0, xmm1
	jne	.L561
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L561
	ucomiss	xmm0, xmm1
	je	.L564
.L561:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	jne	.L564
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	jne	.L564
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L564
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L564
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L564
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L564
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L564
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L564:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L567
	ucomiss	xmm0, xmm1
	jne	.L567
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L567
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	jne	.L567
	movss	xmm0, DWORD PTR _x_p18_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L567
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L567
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L567
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L567
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L567
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L567
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L567
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	ucomiss	xmm0, xmm1
	jp	.L567
	ucomiss	xmm0, xmm1
	je	.L570
.L567:
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L570
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	jne	.L570
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L570
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L570
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L570
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L570
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L570
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L570
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L570:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L573
	movss	xmm0, DWORD PTR proposed18[rip]
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	ucomiss	xmm0, xmm1
	jp	.L573
	ucomiss	xmm0, xmm1
	jne	.L573
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L573
	ucomiss	xmm0, xmm1
	jne	.L573
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	jne	.L576
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	jne	.L576
	movss	xmm0, DWORD PTR _x_p18_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L576
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L577
.L576:
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	je	.L573
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	je	.L573
	movss	xmm0, DWORD PTR p18_x[rip]
	movss	xmm1, DWORD PTR _x_p18_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L573
	ucomiss	xmm0, xmm1
	je	.L577
.L573:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L577
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	jne	.L577
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L577
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L577
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L577
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L577
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L577
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L577
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L577:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p18_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L581
	ucomiss	xmm0, xmm1
	jne	.L581
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	test	al, al
	jne	.L581
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	test	al, al
	jne	.L581
	movss	xmm0, DWORD PTR p18_x[rip]
	movss	xmm1, DWORD PTR _x_p18_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L581
	ucomiss	xmm0, xmm1
	jne	.L581
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L581
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L581
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L581
	movss	xmm1, DWORD PTR proposed18[rip]
	movss	xmm0, DWORD PTR _x_proposed18[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L584
.L581:
	movzx	eax, BYTE PTR p18_l0[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR p18_l1[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L584
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L584
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L584
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L584
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L584
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L584:
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	jne	.L586
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L587
.L586:
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L588
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L587
.L588:
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L589
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L587
.L589:
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L301
.L587:
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p17_x[rip]
	movss	xmm0, DWORD PTR _x_proposed17[rip]
	comiss	xmm0, xmm1
	jnb	.L590
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L590
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L301
.L590:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L591
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L591
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p17_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p17_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L591
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L591
	movss	xmm0, DWORD PTR p17_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L591
	ucomiss	xmm0, xmm1
	jne	.L591
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	ucomiss	xmm0, xmm1
	jp	.L591
	ucomiss	xmm0, xmm1
	je	.L594
.L591:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L594:
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	jne	.L597
	movss	xmm0, DWORD PTR _x_p17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L597
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L597
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L597
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L597
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	ucomiss	xmm0, xmm1
	jp	.L597
	ucomiss	xmm0, xmm1
	jne	.L597
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L597
	ucomiss	xmm0, xmm1
	je	.L600
.L597:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	jne	.L600
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	jne	.L600
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L600
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L600
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L600
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L600
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L600
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L600
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L600:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L603
	ucomiss	xmm0, xmm1
	jne	.L603
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L603
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	jne	.L603
	movss	xmm0, DWORD PTR _x_p17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L603
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L603
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L603
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L603
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L603
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L603
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L603
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	ucomiss	xmm0, xmm1
	jp	.L603
	ucomiss	xmm0, xmm1
	je	.L606
.L603:
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L606
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	jne	.L606
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L606
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L606
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L606
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L606
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L606
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L606
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L606:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L609
	movss	xmm0, DWORD PTR proposed17[rip]
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	ucomiss	xmm0, xmm1
	jp	.L609
	ucomiss	xmm0, xmm1
	jne	.L609
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L609
	ucomiss	xmm0, xmm1
	jne	.L609
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	jne	.L612
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	jne	.L612
	movss	xmm0, DWORD PTR _x_p17_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L612
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L613
.L612:
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	je	.L609
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	je	.L609
	movss	xmm0, DWORD PTR p17_x[rip]
	movss	xmm1, DWORD PTR _x_p17_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L609
	ucomiss	xmm0, xmm1
	je	.L613
.L609:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L613
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	jne	.L613
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L613
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L613
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L613
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L613
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L613
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L613
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L613:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p17_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L617
	ucomiss	xmm0, xmm1
	jne	.L617
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	test	al, al
	jne	.L617
	movss	xmm0, DWORD PTR p17_x[rip]
	movss	xmm1, DWORD PTR _x_p17_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L617
	ucomiss	xmm0, xmm1
	jne	.L617
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L617
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L617
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L617
	movss	xmm1, DWORD PTR proposed17[rip]
	movss	xmm0, DWORD PTR _x_proposed17[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L620
.L617:
	movzx	eax, BYTE PTR p17_l0[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR p17_l1[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L620
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L620
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L620
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L620
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L620
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L620:
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	jne	.L622
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L623
.L622:
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L624
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L623
.L624:
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L625
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L623
.L625:
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L301
.L623:
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p16_x[rip]
	movss	xmm0, DWORD PTR _x_proposed16[rip]
	comiss	xmm0, xmm1
	jnb	.L626
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L626
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L301
.L626:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L627
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L627
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p16_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p16_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L627
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L627
	movss	xmm0, DWORD PTR p16_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L627
	ucomiss	xmm0, xmm1
	jne	.L627
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	ucomiss	xmm0, xmm1
	jp	.L627
	ucomiss	xmm0, xmm1
	je	.L630
.L627:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L630:
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	jne	.L633
	movss	xmm0, DWORD PTR _x_p16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L633
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L633
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L633
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L633
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	ucomiss	xmm0, xmm1
	jp	.L633
	ucomiss	xmm0, xmm1
	jne	.L633
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L633
	ucomiss	xmm0, xmm1
	je	.L636
.L633:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L636
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L636
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L636
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L636
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L636:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L639
	ucomiss	xmm0, xmm1
	jne	.L639
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L639
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	jne	.L639
	movss	xmm0, DWORD PTR _x_p16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L639
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L639
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L639
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L639
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L639
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L639
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L639
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	ucomiss	xmm0, xmm1
	jp	.L639
	ucomiss	xmm0, xmm1
	je	.L642
.L639:
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L642
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L642
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L642
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L642
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L642
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L642:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L645
	movss	xmm0, DWORD PTR proposed16[rip]
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	ucomiss	xmm0, xmm1
	jp	.L645
	ucomiss	xmm0, xmm1
	jne	.L645
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L645
	ucomiss	xmm0, xmm1
	jne	.L645
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	jne	.L648
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	jne	.L648
	movss	xmm0, DWORD PTR _x_p16_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L648
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L649
.L648:
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	je	.L645
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	je	.L645
	movss	xmm0, DWORD PTR p16_x[rip]
	movss	xmm1, DWORD PTR _x_p16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L645
	ucomiss	xmm0, xmm1
	je	.L649
.L645:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L649
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	jne	.L649
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L649
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L649
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L649
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L649
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L649
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L649
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L649:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p16_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L653
	ucomiss	xmm0, xmm1
	jne	.L653
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	test	al, al
	jne	.L653
	movss	xmm0, DWORD PTR p16_x[rip]
	movss	xmm1, DWORD PTR _x_p16_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L653
	ucomiss	xmm0, xmm1
	jne	.L653
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L653
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L653
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L653
	movss	xmm1, DWORD PTR proposed16[rip]
	movss	xmm0, DWORD PTR _x_proposed16[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L656
.L653:
	movzx	eax, BYTE PTR p16_l0[rip]
	test	al, al
	je	.L656
	movzx	eax, BYTE PTR p16_l1[rip]
	test	al, al
	je	.L656
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	je	.L656
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L656
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L656
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L656
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L656
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L656
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L656:
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	jne	.L658
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L659
.L658:
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L660
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L659
.L660:
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L661
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L659
.L661:
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L301
.L659:
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p15_x[rip]
	movss	xmm0, DWORD PTR _x_proposed15[rip]
	comiss	xmm0, xmm1
	jnb	.L662
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L662
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L301
.L662:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L663
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L663
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p15_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p15_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L663
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L663
	movss	xmm0, DWORD PTR p15_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L663
	ucomiss	xmm0, xmm1
	jne	.L663
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	ucomiss	xmm0, xmm1
	jp	.L663
	ucomiss	xmm0, xmm1
	je	.L666
.L663:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
.L666:
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L669
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	jne	.L669
	movss	xmm0, DWORD PTR _x_p15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L669
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L669
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L669
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L669
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L669
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L669
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L669
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	ucomiss	xmm0, xmm1
	jp	.L669
	ucomiss	xmm0, xmm1
	jne	.L669
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L669
	ucomiss	xmm0, xmm1
	je	.L672
.L669:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	jne	.L672
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	jne	.L672
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L672
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L672
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L672
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L672
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L672
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L672
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L672:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L675
	ucomiss	xmm0, xmm1
	jne	.L675
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L675
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	jne	.L675
	movss	xmm0, DWORD PTR _x_p15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L675
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L675
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L675
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L675
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L675
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L675
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L675
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	ucomiss	xmm0, xmm1
	jp	.L675
	ucomiss	xmm0, xmm1
	je	.L678
.L675:
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L678
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	jne	.L678
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L678
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L678
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L678
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L678
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L678
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L678
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L678:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L681
	movss	xmm0, DWORD PTR proposed15[rip]
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	ucomiss	xmm0, xmm1
	jp	.L681
	ucomiss	xmm0, xmm1
	jne	.L681
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L681
	ucomiss	xmm0, xmm1
	jne	.L681
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	jne	.L684
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	jne	.L684
	movss	xmm0, DWORD PTR _x_p15_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L684
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L685
.L684:
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	je	.L681
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	je	.L681
	movss	xmm0, DWORD PTR p15_x[rip]
	movss	xmm1, DWORD PTR _x_p15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L681
	ucomiss	xmm0, xmm1
	je	.L685
.L681:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	jne	.L685
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L685
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L685
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L685
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L685
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L685:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p15_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L689
	ucomiss	xmm0, xmm1
	jne	.L689
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	test	al, al
	jne	.L689
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	test	al, al
	jne	.L689
	movss	xmm0, DWORD PTR p15_x[rip]
	movss	xmm1, DWORD PTR _x_p15_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L689
	ucomiss	xmm0, xmm1
	jne	.L689
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L689
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L689
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L689
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L689
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L689
	movss	xmm1, DWORD PTR proposed15[rip]
	movss	xmm0, DWORD PTR _x_proposed15[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L692
.L689:
	movzx	eax, BYTE PTR p15_l0[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR p15_l1[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L692
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L692
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L692
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L692
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L692:
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	jne	.L694
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L695
.L694:
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L696
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L695
.L696:
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L697
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L695
.L697:
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L301
.L695:
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p14_x[rip]
	movss	xmm0, DWORD PTR _x_proposed14[rip]
	comiss	xmm0, xmm1
	jnb	.L698
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L698
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L301
.L698:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L699
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L699
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p14_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p14_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L699
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L699
	movss	xmm0, DWORD PTR p14_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L699
	ucomiss	xmm0, xmm1
	jne	.L699
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	ucomiss	xmm0, xmm1
	jp	.L699
	ucomiss	xmm0, xmm1
	je	.L702
.L699:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
.L702:
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	jne	.L705
	movss	xmm0, DWORD PTR _x_p14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L705
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L705
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L705
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L705
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	ucomiss	xmm0, xmm1
	jp	.L705
	ucomiss	xmm0, xmm1
	jne	.L705
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L705
	ucomiss	xmm0, xmm1
	je	.L708
.L705:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	jne	.L708
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	jne	.L708
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L708
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L708
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L708
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L708
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L708
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L708
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L708:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L711
	ucomiss	xmm0, xmm1
	jne	.L711
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L711
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	jne	.L711
	movss	xmm0, DWORD PTR _x_p14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L711
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L711
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L711
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L711
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L711
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L711
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L711
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	ucomiss	xmm0, xmm1
	jp	.L711
	ucomiss	xmm0, xmm1
	je	.L714
.L711:
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L714
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	jne	.L714
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L714
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L714
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L714
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L714
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L714
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L714
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L714:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L717
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L717
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L717
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L717
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L717
	movss	xmm0, DWORD PTR proposed14[rip]
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	ucomiss	xmm0, xmm1
	jp	.L717
	ucomiss	xmm0, xmm1
	jne	.L717
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L717
	ucomiss	xmm0, xmm1
	jne	.L717
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	jne	.L720
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	jne	.L720
	movss	xmm0, DWORD PTR _x_p14_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L720
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L721
.L720:
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	je	.L717
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	je	.L717
	movss	xmm0, DWORD PTR p14_x[rip]
	movss	xmm1, DWORD PTR _x_p14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L717
	ucomiss	xmm0, xmm1
	je	.L721
.L717:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L721
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	jne	.L721
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L721
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L721
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L721
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L721
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L721
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L721
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L721:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p14_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L725
	ucomiss	xmm0, xmm1
	jne	.L725
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	test	al, al
	jne	.L725
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	test	al, al
	jne	.L725
	movss	xmm0, DWORD PTR p14_x[rip]
	movss	xmm1, DWORD PTR _x_p14_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L725
	ucomiss	xmm0, xmm1
	jne	.L725
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L725
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L725
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L725
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L725
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L725
	movss	xmm1, DWORD PTR proposed14[rip]
	movss	xmm0, DWORD PTR _x_proposed14[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L728
.L725:
	movzx	eax, BYTE PTR p14_l0[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR p14_l1[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L728
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L728
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L728
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L728
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L728:
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	jne	.L730
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L731
.L730:
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L732
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L731
.L732:
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L733
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L731
.L733:
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L301
.L731:
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p13_x[rip]
	movss	xmm0, DWORD PTR _x_proposed13[rip]
	comiss	xmm0, xmm1
	jnb	.L734
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L734
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L301
.L734:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L735
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L735
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p13_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p13_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L735
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L735
	movss	xmm0, DWORD PTR p13_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L735
	ucomiss	xmm0, xmm1
	jne	.L735
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	ucomiss	xmm0, xmm1
	jp	.L735
	ucomiss	xmm0, xmm1
	je	.L738
.L735:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L738:
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	jne	.L741
	movss	xmm0, DWORD PTR _x_p13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L741
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L741
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L741
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L741
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	ucomiss	xmm0, xmm1
	jp	.L741
	ucomiss	xmm0, xmm1
	jne	.L741
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L741
	ucomiss	xmm0, xmm1
	je	.L744
.L741:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	jne	.L744
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	jne	.L744
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L744
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L744
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L744
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L744
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L744
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L744
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L744:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L747
	ucomiss	xmm0, xmm1
	jne	.L747
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	jne	.L747
	movss	xmm0, DWORD PTR _x_p13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L747
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L747
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L747
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L747
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L747
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	ucomiss	xmm0, xmm1
	jp	.L747
	ucomiss	xmm0, xmm1
	je	.L750
.L747:
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L750
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	jne	.L750
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L750
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L750
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L750
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L750
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L750
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L750
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L750:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L753
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L753
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L753
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L753
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L753
	movss	xmm0, DWORD PTR proposed13[rip]
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	ucomiss	xmm0, xmm1
	jp	.L753
	ucomiss	xmm0, xmm1
	jne	.L753
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L753
	ucomiss	xmm0, xmm1
	jne	.L753
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	jne	.L756
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	jne	.L756
	movss	xmm0, DWORD PTR _x_p13_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L756
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L757
.L756:
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	je	.L753
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	je	.L753
	movss	xmm0, DWORD PTR p13_x[rip]
	movss	xmm1, DWORD PTR _x_p13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L753
	ucomiss	xmm0, xmm1
	je	.L757
.L753:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L757
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	jne	.L757
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L757
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L757
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L757
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L757
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L757
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L757
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L757:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p13_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L761
	ucomiss	xmm0, xmm1
	jne	.L761
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	test	al, al
	jne	.L761
	movss	xmm0, DWORD PTR p13_x[rip]
	movss	xmm1, DWORD PTR _x_p13_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L761
	ucomiss	xmm0, xmm1
	jne	.L761
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L761
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L761
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L761
	movss	xmm1, DWORD PTR proposed13[rip]
	movss	xmm0, DWORD PTR _x_proposed13[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L764
.L761:
	movzx	eax, BYTE PTR p13_l0[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR p13_l1[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L764
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L764
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L764
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L764
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L764:
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	jne	.L766
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L767
.L766:
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L768
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L767
.L768:
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L769
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L767
.L769:
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L301
.L767:
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p12_x[rip]
	movss	xmm0, DWORD PTR _x_proposed12[rip]
	comiss	xmm0, xmm1
	jnb	.L770
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L770
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L301
.L770:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L771
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L771
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p12_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p12_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L771
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L771
	movss	xmm0, DWORD PTR p12_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L771
	ucomiss	xmm0, xmm1
	jne	.L771
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	ucomiss	xmm0, xmm1
	jp	.L771
	ucomiss	xmm0, xmm1
	je	.L774
.L771:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L774:
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L777
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	jne	.L777
	movss	xmm0, DWORD PTR _x_p12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L777
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L777
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L777
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L777
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L777
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L777
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L777
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	ucomiss	xmm0, xmm1
	jp	.L777
	ucomiss	xmm0, xmm1
	jne	.L777
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L777
	ucomiss	xmm0, xmm1
	je	.L780
.L777:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	jne	.L780
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	jne	.L780
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L780
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L780
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L780
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L780
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L780
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L780
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L780:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L783
	ucomiss	xmm0, xmm1
	jne	.L783
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L783
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	jne	.L783
	movss	xmm0, DWORD PTR _x_p12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L783
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L783
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L783
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L783
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L783
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L783
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L783
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	ucomiss	xmm0, xmm1
	jp	.L783
	ucomiss	xmm0, xmm1
	je	.L786
.L783:
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	jne	.L786
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L786
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L786
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L786
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L786
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L786
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L786:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L789
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L789
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L789
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L789
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L789
	movss	xmm0, DWORD PTR proposed12[rip]
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	ucomiss	xmm0, xmm1
	jp	.L789
	ucomiss	xmm0, xmm1
	jne	.L789
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L789
	ucomiss	xmm0, xmm1
	jne	.L789
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	jne	.L792
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	jne	.L792
	movss	xmm0, DWORD PTR _x_p12_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L792
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L793
.L792:
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	je	.L789
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	je	.L789
	movss	xmm0, DWORD PTR p12_x[rip]
	movss	xmm1, DWORD PTR _x_p12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L789
	ucomiss	xmm0, xmm1
	je	.L793
.L789:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L793
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	jne	.L793
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L793
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L793
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L793
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L793
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L793
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L793
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L793:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p12_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L797
	ucomiss	xmm0, xmm1
	jne	.L797
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	test	al, al
	jne	.L797
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	test	al, al
	jne	.L797
	movss	xmm0, DWORD PTR p12_x[rip]
	movss	xmm1, DWORD PTR _x_p12_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L797
	ucomiss	xmm0, xmm1
	jne	.L797
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L797
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L797
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L797
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L797
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L797
	movss	xmm1, DWORD PTR proposed12[rip]
	movss	xmm0, DWORD PTR _x_proposed12[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L800
.L797:
	movzx	eax, BYTE PTR p12_l0[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR p12_l1[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L800
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L800
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L800
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L800
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L800
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L800:
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	jne	.L802
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L803
.L802:
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L804
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L803
.L804:
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L805
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L803
.L805:
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L301
.L803:
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p11_x[rip]
	movss	xmm0, DWORD PTR _x_proposed11[rip]
	comiss	xmm0, xmm1
	jnb	.L806
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L806
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L301
.L806:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L807
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L807
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p11_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p11_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L807
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L807
	movss	xmm0, DWORD PTR p11_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L807
	ucomiss	xmm0, xmm1
	jne	.L807
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	ucomiss	xmm0, xmm1
	jp	.L807
	ucomiss	xmm0, xmm1
	je	.L810
.L807:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
.L810:
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L813
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	jne	.L813
	movss	xmm0, DWORD PTR _x_p11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L813
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L813
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L813
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L813
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L813
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L813
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L813
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	ucomiss	xmm0, xmm1
	jp	.L813
	ucomiss	xmm0, xmm1
	jne	.L813
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L813
	ucomiss	xmm0, xmm1
	je	.L816
.L813:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	jne	.L816
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	jne	.L816
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L816
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L816
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L816
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L816
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L816
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L816
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L816:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L819
	ucomiss	xmm0, xmm1
	jne	.L819
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L819
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	jne	.L819
	movss	xmm0, DWORD PTR _x_p11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L819
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L819
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L819
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L819
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L819
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L819
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L819
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	ucomiss	xmm0, xmm1
	jp	.L819
	ucomiss	xmm0, xmm1
	je	.L822
.L819:
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	jne	.L822
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L822
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L822
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L822
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L822
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L822
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L822:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L825
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L825
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L825
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L825
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L825
	movss	xmm0, DWORD PTR proposed11[rip]
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	ucomiss	xmm0, xmm1
	jp	.L825
	ucomiss	xmm0, xmm1
	jne	.L825
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L825
	ucomiss	xmm0, xmm1
	jne	.L825
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	jne	.L828
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	jne	.L828
	movss	xmm0, DWORD PTR _x_p11_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L828
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L829
.L828:
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	je	.L825
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	je	.L825
	movss	xmm0, DWORD PTR p11_x[rip]
	movss	xmm1, DWORD PTR _x_p11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L825
	ucomiss	xmm0, xmm1
	je	.L829
.L825:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L829
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	jne	.L829
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L829
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L829
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L829
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L829
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L829
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L829
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L829:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p11_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L833
	ucomiss	xmm0, xmm1
	jne	.L833
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	test	al, al
	jne	.L833
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	test	al, al
	jne	.L833
	movss	xmm0, DWORD PTR p11_x[rip]
	movss	xmm1, DWORD PTR _x_p11_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L833
	ucomiss	xmm0, xmm1
	jne	.L833
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L833
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L833
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L833
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L833
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L833
	movss	xmm1, DWORD PTR proposed11[rip]
	movss	xmm0, DWORD PTR _x_proposed11[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L836
.L833:
	movzx	eax, BYTE PTR p11_l0[rip]
	test	al, al
	je	.L836
	movzx	eax, BYTE PTR p11_l1[rip]
	test	al, al
	je	.L836
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L836
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L836
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L836
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L836
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L836
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L836
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L836:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L838
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L839
.L838:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L840
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L839
.L840:
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L841
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L839
.L841:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L301
.L839:
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p10_x[rip]
	movss	xmm0, DWORD PTR _x_proposed10[rip]
	comiss	xmm0, xmm1
	jnb	.L842
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L842
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L301
.L842:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L843
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L843
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p10_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p10_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L843
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L843
	movss	xmm0, DWORD PTR p10_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L843
	ucomiss	xmm0, xmm1
	jne	.L843
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	ucomiss	xmm0, xmm1
	jp	.L843
	ucomiss	xmm0, xmm1
	je	.L846
.L843:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
.L846:
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L849
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L849
	movss	xmm0, DWORD PTR _x_p10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L849
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L849
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L849
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L849
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L849
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L849
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L849
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	ucomiss	xmm0, xmm1
	jp	.L849
	ucomiss	xmm0, xmm1
	jne	.L849
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L849
	ucomiss	xmm0, xmm1
	je	.L852
.L849:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L852
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L852
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L852
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L852
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L852
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L852:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L855
	ucomiss	xmm0, xmm1
	jne	.L855
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L855
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L855
	movss	xmm0, DWORD PTR _x_p10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L855
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L855
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L855
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L855
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L855
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L855
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L855
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	ucomiss	xmm0, xmm1
	jp	.L855
	ucomiss	xmm0, xmm1
	je	.L858
.L855:
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L858
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	jne	.L858
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L858
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L858
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L858
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L858
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L858
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L858
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L858:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L861
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L861
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L861
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L861
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L861
	movss	xmm0, DWORD PTR proposed10[rip]
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	ucomiss	xmm0, xmm1
	jp	.L861
	ucomiss	xmm0, xmm1
	jne	.L861
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L861
	ucomiss	xmm0, xmm1
	jne	.L861
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L864
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L864
	movss	xmm0, DWORD PTR _x_p10_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L864
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L865
.L864:
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	je	.L861
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	je	.L861
	movss	xmm0, DWORD PTR p10_x[rip]
	movss	xmm1, DWORD PTR _x_p10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L861
	ucomiss	xmm0, xmm1
	je	.L865
.L861:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L865
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	jne	.L865
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L865
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L865
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L865
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L865
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L865
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L865
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L865:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p10_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L869
	ucomiss	xmm0, xmm1
	jne	.L869
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	test	al, al
	jne	.L869
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	test	al, al
	jne	.L869
	movss	xmm0, DWORD PTR p10_x[rip]
	movss	xmm1, DWORD PTR _x_p10_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L869
	ucomiss	xmm0, xmm1
	jne	.L869
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L869
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L869
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L869
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L869
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L869
	movss	xmm1, DWORD PTR proposed10[rip]
	movss	xmm0, DWORD PTR _x_proposed10[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L872
.L869:
	movzx	eax, BYTE PTR p10_l0[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR p10_l1[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L872
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L872
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L872
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L872
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L872
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L872:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L874
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L875
.L874:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L876
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L875
.L876:
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L877
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L875
.L877:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L301
.L875:
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p9_x[rip]
	movss	xmm0, DWORD PTR _x_proposed9[rip]
	comiss	xmm0, xmm1
	jnb	.L878
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L878
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L301
.L878:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L879
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L879
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p9_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p9_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L879
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L879
	movss	xmm0, DWORD PTR p9_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L879
	ucomiss	xmm0, xmm1
	jne	.L879
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	ucomiss	xmm0, xmm1
	jp	.L879
	ucomiss	xmm0, xmm1
	je	.L882
.L879:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L882:
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L885
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L885
	movss	xmm0, DWORD PTR _x_p9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L885
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L885
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L885
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L885
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L885
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L885
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L885
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	ucomiss	xmm0, xmm1
	jp	.L885
	ucomiss	xmm0, xmm1
	jne	.L885
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L885
	ucomiss	xmm0, xmm1
	je	.L888
.L885:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L888
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L888
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L888
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L888
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L888
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L888
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L888
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L888
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L888:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L891
	ucomiss	xmm0, xmm1
	jne	.L891
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L891
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L891
	movss	xmm0, DWORD PTR _x_p9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L891
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L891
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L891
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L891
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L891
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L891
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L891
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	ucomiss	xmm0, xmm1
	jp	.L891
	ucomiss	xmm0, xmm1
	je	.L894
.L891:
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L894
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	jne	.L894
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L894
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L894
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L894
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L894
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L894
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L894
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L894:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L897
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L897
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L897
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L897
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L897
	movss	xmm0, DWORD PTR proposed9[rip]
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	ucomiss	xmm0, xmm1
	jp	.L897
	ucomiss	xmm0, xmm1
	jne	.L897
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L897
	ucomiss	xmm0, xmm1
	jne	.L897
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L900
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L900
	movss	xmm0, DWORD PTR _x_p9_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L900
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L901
.L900:
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	je	.L897
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	je	.L897
	movss	xmm0, DWORD PTR p9_x[rip]
	movss	xmm1, DWORD PTR _x_p9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L897
	ucomiss	xmm0, xmm1
	je	.L901
.L897:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L901
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	jne	.L901
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L901
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L901
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L901
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L901
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L901
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L901
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L901:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p9_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L905
	ucomiss	xmm0, xmm1
	jne	.L905
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	test	al, al
	jne	.L905
	movss	xmm0, DWORD PTR p9_x[rip]
	movss	xmm1, DWORD PTR _x_p9_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L905
	ucomiss	xmm0, xmm1
	jne	.L905
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L905
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L905
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L905
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L905
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L905
	movss	xmm1, DWORD PTR proposed9[rip]
	movss	xmm0, DWORD PTR _x_proposed9[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L908
.L905:
	movzx	eax, BYTE PTR p9_l0[rip]
	test	al, al
	je	.L908
	movzx	eax, BYTE PTR p9_l1[rip]
	test	al, al
	je	.L908
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L908
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L908
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L908
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L908
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L908
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L908
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L908:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L910
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L911
.L910:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L912
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L911
.L912:
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L913
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L911
.L913:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L301
.L911:
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p8_x[rip]
	movss	xmm0, DWORD PTR _x_proposed8[rip]
	comiss	xmm0, xmm1
	jnb	.L914
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L914
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L301
.L914:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L915
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L915
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p8_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p8_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L915
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L915
	movss	xmm0, DWORD PTR p8_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L915
	ucomiss	xmm0, xmm1
	jne	.L915
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	ucomiss	xmm0, xmm1
	jp	.L915
	ucomiss	xmm0, xmm1
	je	.L918
.L915:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L918:
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L921
	movss	xmm0, DWORD PTR _x_p8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L921
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L921
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L921
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L921
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	ucomiss	xmm0, xmm1
	jp	.L921
	ucomiss	xmm0, xmm1
	jne	.L921
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L921
	ucomiss	xmm0, xmm1
	je	.L924
.L921:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L924
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L924
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L924
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L924
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L924
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L924
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L924
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L924
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L924:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L927
	ucomiss	xmm0, xmm1
	jne	.L927
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L927
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L927
	movss	xmm0, DWORD PTR _x_p8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L927
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L927
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L927
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L927
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L927
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L927
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L927
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	ucomiss	xmm0, xmm1
	jp	.L927
	ucomiss	xmm0, xmm1
	je	.L930
.L927:
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L930
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	jne	.L930
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L930
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L930
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L930
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L930
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L930
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L930
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L930:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L933
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L933
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L933
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L933
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L933
	movss	xmm0, DWORD PTR proposed8[rip]
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	ucomiss	xmm0, xmm1
	jp	.L933
	ucomiss	xmm0, xmm1
	jne	.L933
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L933
	ucomiss	xmm0, xmm1
	jne	.L933
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L936
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L936
	movss	xmm0, DWORD PTR _x_p8_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L936
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L937
.L936:
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	je	.L933
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	je	.L933
	movss	xmm0, DWORD PTR p8_x[rip]
	movss	xmm1, DWORD PTR _x_p8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L933
	ucomiss	xmm0, xmm1
	je	.L937
.L933:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L937
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	jne	.L937
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L937
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L937
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L937
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L937
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L937
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L937
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L937:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p8_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L941
	ucomiss	xmm0, xmm1
	jne	.L941
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	test	al, al
	jne	.L941
	movss	xmm0, DWORD PTR p8_x[rip]
	movss	xmm1, DWORD PTR _x_p8_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L941
	ucomiss	xmm0, xmm1
	jne	.L941
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L941
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L941
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L941
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L941
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L941
	movss	xmm1, DWORD PTR proposed8[rip]
	movss	xmm0, DWORD PTR _x_proposed8[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L944
.L941:
	movzx	eax, BYTE PTR p8_l0[rip]
	test	al, al
	je	.L944
	movzx	eax, BYTE PTR p8_l1[rip]
	test	al, al
	je	.L944
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L944
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	je	.L944
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L944
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L944
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L944
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L944
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L944:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L946
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L947
.L946:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L948
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L947
.L948:
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L949
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L947
.L949:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L301
.L947:
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p7_x[rip]
	movss	xmm0, DWORD PTR _x_proposed7[rip]
	comiss	xmm0, xmm1
	jnb	.L950
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L950
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L301
.L950:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L951
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L951
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p7_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p7_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L951
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L951
	movss	xmm0, DWORD PTR p7_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L951
	ucomiss	xmm0, xmm1
	jne	.L951
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	ucomiss	xmm0, xmm1
	jp	.L951
	ucomiss	xmm0, xmm1
	je	.L954
.L951:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
.L954:
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L957
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L957
	movss	xmm0, DWORD PTR _x_p7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L957
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L957
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L957
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L957
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L957
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L957
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L957
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	ucomiss	xmm0, xmm1
	jp	.L957
	ucomiss	xmm0, xmm1
	jne	.L957
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L957
	ucomiss	xmm0, xmm1
	je	.L960
.L957:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L960
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L960
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L960
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L960
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L960
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L960
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L960
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L960
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L960:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L963
	ucomiss	xmm0, xmm1
	jne	.L963
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L963
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L963
	movss	xmm0, DWORD PTR _x_p7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L963
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L963
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L963
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L963
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L963
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L963
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L963
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	ucomiss	xmm0, xmm1
	jp	.L963
	ucomiss	xmm0, xmm1
	je	.L966
.L963:
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L966
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	jne	.L966
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L966
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L966
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L966
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L966
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L966
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L966
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L966:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L969
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L969
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L969
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L969
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L969
	movss	xmm0, DWORD PTR proposed7[rip]
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	ucomiss	xmm0, xmm1
	jp	.L969
	ucomiss	xmm0, xmm1
	jne	.L969
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L969
	ucomiss	xmm0, xmm1
	jne	.L969
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L972
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L972
	movss	xmm0, DWORD PTR _x_p7_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L972
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L973
.L972:
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	je	.L969
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	je	.L969
	movss	xmm0, DWORD PTR p7_x[rip]
	movss	xmm1, DWORD PTR _x_p7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L969
	ucomiss	xmm0, xmm1
	je	.L973
.L969:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L973
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	jne	.L973
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L973
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L973
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L973
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L973
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L973
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L973
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L973:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p7_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L977
	ucomiss	xmm0, xmm1
	jne	.L977
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	test	al, al
	jne	.L977
	movss	xmm0, DWORD PTR p7_x[rip]
	movss	xmm1, DWORD PTR _x_p7_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L977
	ucomiss	xmm0, xmm1
	jne	.L977
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L977
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L977
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L977
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L977
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L977
	movss	xmm1, DWORD PTR proposed7[rip]
	movss	xmm0, DWORD PTR _x_proposed7[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L980
.L977:
	movzx	eax, BYTE PTR p7_l0[rip]
	test	al, al
	je	.L980
	movzx	eax, BYTE PTR p7_l1[rip]
	test	al, al
	je	.L980
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L980
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L980
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L980
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L980
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L980
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L980
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L980:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L982
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L983
.L982:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L984
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L983
.L984:
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L985
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L983
.L985:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L301
.L983:
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p6_x[rip]
	movss	xmm0, DWORD PTR _x_proposed6[rip]
	comiss	xmm0, xmm1
	jnb	.L986
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L986
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L301
.L986:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L987
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L987
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p6_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p6_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L987
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L987
	movss	xmm0, DWORD PTR p6_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L987
	ucomiss	xmm0, xmm1
	jne	.L987
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	ucomiss	xmm0, xmm1
	jp	.L987
	ucomiss	xmm0, xmm1
	je	.L990
.L987:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
.L990:
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L993
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L993
	movss	xmm0, DWORD PTR _x_p6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L993
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L993
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L993
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L993
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L993
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L993
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L993
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	ucomiss	xmm0, xmm1
	jp	.L993
	ucomiss	xmm0, xmm1
	jne	.L993
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L993
	ucomiss	xmm0, xmm1
	je	.L996
.L993:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L996
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L996
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L996
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L996
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L996
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L996
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L996
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L996
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L996:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L999
	ucomiss	xmm0, xmm1
	jne	.L999
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L999
	movss	xmm0, DWORD PTR _x_p6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L999
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L999
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L999
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L999
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L999
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L999
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	ucomiss	xmm0, xmm1
	jp	.L999
	ucomiss	xmm0, xmm1
	je	.L1002
.L999:
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L1002
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	jne	.L1002
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1002
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1002
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1002
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1002
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1002
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1002
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1002:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1005
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1005
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1005
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1005
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1005
	movss	xmm0, DWORD PTR proposed6[rip]
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	ucomiss	xmm0, xmm1
	jp	.L1005
	ucomiss	xmm0, xmm1
	jne	.L1005
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1005
	ucomiss	xmm0, xmm1
	jne	.L1005
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L1008
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L1008
	movss	xmm0, DWORD PTR _x_p6_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1008
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1009
.L1008:
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	je	.L1005
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	je	.L1005
	movss	xmm0, DWORD PTR p6_x[rip]
	movss	xmm1, DWORD PTR _x_p6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1005
	ucomiss	xmm0, xmm1
	je	.L1009
.L1005:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L1009
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	jne	.L1009
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1009
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1009
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1009
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1009
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1009
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1009
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1009:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p6_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1013
	ucomiss	xmm0, xmm1
	jne	.L1013
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	test	al, al
	jne	.L1013
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	test	al, al
	jne	.L1013
	movss	xmm0, DWORD PTR p6_x[rip]
	movss	xmm1, DWORD PTR _x_p6_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1013
	ucomiss	xmm0, xmm1
	jne	.L1013
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1013
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1013
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1013
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1013
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1013
	movss	xmm1, DWORD PTR proposed6[rip]
	movss	xmm0, DWORD PTR _x_proposed6[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1016
.L1013:
	movzx	eax, BYTE PTR p6_l0[rip]
	test	al, al
	je	.L1016
	movzx	eax, BYTE PTR p6_l1[rip]
	test	al, al
	je	.L1016
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1016
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1016
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1016
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1016
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1016
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1016
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1016:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L1018
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L1019
.L1018:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L1020
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L1019
.L1020:
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L1021
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L1019
.L1021:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L301
.L1019:
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p5_x[rip]
	movss	xmm0, DWORD PTR _x_proposed5[rip]
	comiss	xmm0, xmm1
	jnb	.L1022
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L1022
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L301
.L1022:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1023
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1023
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p5_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p5_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1023
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1023
	movss	xmm0, DWORD PTR p5_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1023
	ucomiss	xmm0, xmm1
	jne	.L1023
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	ucomiss	xmm0, xmm1
	jp	.L1023
	ucomiss	xmm0, xmm1
	je	.L1026
.L1023:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L1026:
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L1029
	movss	xmm0, DWORD PTR _x_p5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1029
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1029
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1029
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1029
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	ucomiss	xmm0, xmm1
	jp	.L1029
	ucomiss	xmm0, xmm1
	jne	.L1029
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1029
	ucomiss	xmm0, xmm1
	je	.L1032
.L1029:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L1032
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L1032
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1032
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1032
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1032
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1032
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1032
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1032
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1032:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1035
	ucomiss	xmm0, xmm1
	jne	.L1035
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L1035
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L1035
	movss	xmm0, DWORD PTR _x_p5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1035
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1035
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1035
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1035
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1035
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1035
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1035
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	ucomiss	xmm0, xmm1
	jp	.L1035
	ucomiss	xmm0, xmm1
	je	.L1038
.L1035:
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L1038
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	jne	.L1038
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1038
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1038
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1038
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1038
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1038
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1038
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1038:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1041
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1041
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1041
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1041
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1041
	movss	xmm0, DWORD PTR proposed5[rip]
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	ucomiss	xmm0, xmm1
	jp	.L1041
	ucomiss	xmm0, xmm1
	jne	.L1041
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1041
	ucomiss	xmm0, xmm1
	jne	.L1041
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L1044
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L1044
	movss	xmm0, DWORD PTR _x_p5_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1044
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1045
.L1044:
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	je	.L1041
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	je	.L1041
	movss	xmm0, DWORD PTR p5_x[rip]
	movss	xmm1, DWORD PTR _x_p5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1041
	ucomiss	xmm0, xmm1
	je	.L1045
.L1041:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L1045
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	jne	.L1045
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1045
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1045
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1045
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1045
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1045
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1045
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1045:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p5_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1049
	ucomiss	xmm0, xmm1
	jne	.L1049
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	test	al, al
	jne	.L1049
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	test	al, al
	jne	.L1049
	movss	xmm0, DWORD PTR p5_x[rip]
	movss	xmm1, DWORD PTR _x_p5_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1049
	ucomiss	xmm0, xmm1
	jne	.L1049
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1049
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1049
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1049
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1049
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1049
	movss	xmm1, DWORD PTR proposed5[rip]
	movss	xmm0, DWORD PTR _x_proposed5[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1052
.L1049:
	movzx	eax, BYTE PTR p5_l0[rip]
	test	al, al
	je	.L1052
	movzx	eax, BYTE PTR p5_l1[rip]
	test	al, al
	je	.L1052
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1052
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1052
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1052
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1052
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1052
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1052
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1052:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L1054
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L1055
.L1054:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L1056
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L1055
.L1056:
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L1057
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L1055
.L1057:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L301
.L1055:
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p4_x[rip]
	movss	xmm0, DWORD PTR _x_proposed4[rip]
	comiss	xmm0, xmm1
	jnb	.L1058
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L1058
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L301
.L1058:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1059
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1059
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p4_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p4_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1059
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1059
	movss	xmm0, DWORD PTR p4_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1059
	ucomiss	xmm0, xmm1
	jne	.L1059
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	ucomiss	xmm0, xmm1
	jp	.L1059
	ucomiss	xmm0, xmm1
	je	.L1062
.L1059:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L1062:
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L1065
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L1065
	movss	xmm0, DWORD PTR _x_p4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1065
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1065
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1065
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1065
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1065
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1065
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1065
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	ucomiss	xmm0, xmm1
	jp	.L1065
	ucomiss	xmm0, xmm1
	jne	.L1065
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1065
	ucomiss	xmm0, xmm1
	je	.L1068
.L1065:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L1068
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L1068
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1068
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1068
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1068
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1068
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1068
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1068
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1068:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1071
	ucomiss	xmm0, xmm1
	jne	.L1071
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L1071
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L1071
	movss	xmm0, DWORD PTR _x_p4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1071
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1071
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1071
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1071
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1071
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1071
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1071
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	ucomiss	xmm0, xmm1
	jp	.L1071
	ucomiss	xmm0, xmm1
	je	.L1074
.L1071:
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L1074
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	jne	.L1074
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1074
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1074
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1074
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1074
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1074
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1074
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1074:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1077
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1077
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1077
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1077
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1077
	movss	xmm0, DWORD PTR proposed4[rip]
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	ucomiss	xmm0, xmm1
	jp	.L1077
	ucomiss	xmm0, xmm1
	jne	.L1077
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1077
	ucomiss	xmm0, xmm1
	jne	.L1077
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L1080
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L1080
	movss	xmm0, DWORD PTR _x_p4_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1080
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1081
.L1080:
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	je	.L1077
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	je	.L1077
	movss	xmm0, DWORD PTR p4_x[rip]
	movss	xmm1, DWORD PTR _x_p4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1077
	ucomiss	xmm0, xmm1
	je	.L1081
.L1077:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L1081
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	jne	.L1081
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1081
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1081
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1081
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1081
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1081
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1081
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1081:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p4_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1085
	ucomiss	xmm0, xmm1
	jne	.L1085
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	test	al, al
	jne	.L1085
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	test	al, al
	jne	.L1085
	movss	xmm0, DWORD PTR p4_x[rip]
	movss	xmm1, DWORD PTR _x_p4_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1085
	ucomiss	xmm0, xmm1
	jne	.L1085
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1085
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1085
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1085
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1085
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1085
	movss	xmm1, DWORD PTR proposed4[rip]
	movss	xmm0, DWORD PTR _x_proposed4[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1088
.L1085:
	movzx	eax, BYTE PTR p4_l0[rip]
	test	al, al
	je	.L1088
	movzx	eax, BYTE PTR p4_l1[rip]
	test	al, al
	je	.L1088
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1088
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1088
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	je	.L1088
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1088
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1088
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1088
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1088:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L1090
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L1091
.L1090:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L1092
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L1091
.L1092:
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L1093
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L1091
.L1093:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L301
.L1091:
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p3_x[rip]
	movss	xmm0, DWORD PTR _x_proposed3[rip]
	comiss	xmm0, xmm1
	jnb	.L1094
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L1094
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L301
.L1094:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1095
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1095
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p3_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p3_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1095
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1095
	movss	xmm0, DWORD PTR p3_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1095
	ucomiss	xmm0, xmm1
	jne	.L1095
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	ucomiss	xmm0, xmm1
	jp	.L1095
	ucomiss	xmm0, xmm1
	je	.L1098
.L1095:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
.L1098:
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L1101
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L1101
	movss	xmm0, DWORD PTR _x_p3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1101
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1101
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1101
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1101
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1101
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1101
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1101
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	ucomiss	xmm0, xmm1
	jp	.L1101
	ucomiss	xmm0, xmm1
	jne	.L1101
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1101
	ucomiss	xmm0, xmm1
	je	.L1104
.L1101:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L1104
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L1104
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1104
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1104
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1104
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1104
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1104
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1104
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1104:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1107
	ucomiss	xmm0, xmm1
	jne	.L1107
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L1107
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L1107
	movss	xmm0, DWORD PTR _x_p3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1107
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1107
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1107
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1107
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1107
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1107
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1107
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	ucomiss	xmm0, xmm1
	jp	.L1107
	ucomiss	xmm0, xmm1
	je	.L1110
.L1107:
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L1110
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	jne	.L1110
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1110
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1110
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1110
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1110
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1110
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1110
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1110:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1113
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1113
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1113
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1113
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1113
	movss	xmm0, DWORD PTR proposed3[rip]
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	ucomiss	xmm0, xmm1
	jp	.L1113
	ucomiss	xmm0, xmm1
	jne	.L1113
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1113
	ucomiss	xmm0, xmm1
	jne	.L1113
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L1116
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L1116
	movss	xmm0, DWORD PTR _x_p3_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1116
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1117
.L1116:
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	je	.L1113
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	je	.L1113
	movss	xmm0, DWORD PTR p3_x[rip]
	movss	xmm1, DWORD PTR _x_p3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1113
	ucomiss	xmm0, xmm1
	je	.L1117
.L1113:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L1117
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	jne	.L1117
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1117
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1117
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1117
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1117
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1117
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1117
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1117:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p3_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1121
	ucomiss	xmm0, xmm1
	jne	.L1121
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	test	al, al
	jne	.L1121
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	test	al, al
	jne	.L1121
	movss	xmm0, DWORD PTR p3_x[rip]
	movss	xmm1, DWORD PTR _x_p3_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1121
	ucomiss	xmm0, xmm1
	jne	.L1121
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1121
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1121
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1121
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1121
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1121
	movss	xmm1, DWORD PTR proposed3[rip]
	movss	xmm0, DWORD PTR _x_proposed3[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1124
.L1121:
	movzx	eax, BYTE PTR p3_l0[rip]
	test	al, al
	je	.L1124
	movzx	eax, BYTE PTR p3_l1[rip]
	test	al, al
	je	.L1124
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1124
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1124
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1124
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1124
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1124
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1124
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1124:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L1126
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L1127
.L1126:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L1128
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L1127
.L1128:
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L1129
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L1127
.L1129:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L301
.L1127:
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p2_x[rip]
	movss	xmm0, DWORD PTR _x_proposed2[rip]
	comiss	xmm0, xmm1
	jnb	.L1130
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L1130
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L301
.L1130:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1131
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1131
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p2_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p2_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1131
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1131
	movss	xmm0, DWORD PTR p2_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1131
	ucomiss	xmm0, xmm1
	jne	.L1131
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	ucomiss	xmm0, xmm1
	jp	.L1131
	ucomiss	xmm0, xmm1
	je	.L1134
.L1131:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
.L1134:
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L1137
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L1137
	movss	xmm0, DWORD PTR _x_p2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1137
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1137
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1137
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1137
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1137
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1137
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1137
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	ucomiss	xmm0, xmm1
	jp	.L1137
	ucomiss	xmm0, xmm1
	jne	.L1137
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1137
	ucomiss	xmm0, xmm1
	je	.L1140
.L1137:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L1140
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L1140
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1140
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1140
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1140
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1140
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1140
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1140
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1140:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1143
	ucomiss	xmm0, xmm1
	jne	.L1143
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L1143
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L1143
	movss	xmm0, DWORD PTR _x_p2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1143
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1143
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1143
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1143
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1143
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1143
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1143
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	ucomiss	xmm0, xmm1
	jp	.L1143
	ucomiss	xmm0, xmm1
	je	.L1146
.L1143:
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L1146
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	jne	.L1146
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1146
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1146
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1146
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1146
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1146
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1146
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1146:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1149
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1149
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1149
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1149
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1149
	movss	xmm0, DWORD PTR proposed2[rip]
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	ucomiss	xmm0, xmm1
	jp	.L1149
	ucomiss	xmm0, xmm1
	jne	.L1149
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1149
	ucomiss	xmm0, xmm1
	jne	.L1149
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L1152
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L1152
	movss	xmm0, DWORD PTR _x_p2_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1152
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1153
.L1152:
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	je	.L1149
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	je	.L1149
	movss	xmm0, DWORD PTR p2_x[rip]
	movss	xmm1, DWORD PTR _x_p2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1149
	ucomiss	xmm0, xmm1
	je	.L1153
.L1149:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L1153
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	jne	.L1153
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1153
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1153
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1153
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1153
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1153
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1153
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1153:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p2_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1157
	ucomiss	xmm0, xmm1
	jne	.L1157
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	test	al, al
	jne	.L1157
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	test	al, al
	jne	.L1157
	movss	xmm0, DWORD PTR p2_x[rip]
	movss	xmm1, DWORD PTR _x_p2_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1157
	ucomiss	xmm0, xmm1
	jne	.L1157
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1157
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1157
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1157
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1157
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1157
	movss	xmm1, DWORD PTR proposed2[rip]
	movss	xmm0, DWORD PTR _x_proposed2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1160
.L1157:
	movzx	eax, BYTE PTR p2_l0[rip]
	test	al, al
	je	.L1160
	movzx	eax, BYTE PTR p2_l1[rip]
	test	al, al
	je	.L1160
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1160
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1160
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1160
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	je	.L1160
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1160
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1160
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1160:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L1162
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L1163
.L1162:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L1164
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L1163
.L1164:
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L1165
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L1163
.L1165:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L301
.L1163:
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	movss	xmm0, DWORD PTR _x_proposed1[rip]
	comiss	xmm0, xmm1
	jnb	.L1166
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L1166
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L301
.L1166:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1167
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1167
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p1_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p1_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1167
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1167
	movss	xmm0, DWORD PTR p1_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1167
	ucomiss	xmm0, xmm1
	jne	.L1167
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	ucomiss	xmm0, xmm1
	jp	.L1167
	ucomiss	xmm0, xmm1
	je	.L1170
.L1167:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L1170:
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L1173
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L1173
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1173
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1173
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1173
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1173
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1173
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1173
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1173
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	ucomiss	xmm0, xmm1
	jp	.L1173
	ucomiss	xmm0, xmm1
	jne	.L1173
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1173
	ucomiss	xmm0, xmm1
	je	.L1176
.L1173:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L1176
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L1176
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1176
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1176
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1176
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1176
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1176
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1176
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1176:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1179
	ucomiss	xmm0, xmm1
	jne	.L1179
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L1179
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L1179
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1179
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1179
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1179
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1179
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1179
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1179
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1179
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	ucomiss	xmm0, xmm1
	jp	.L1179
	ucomiss	xmm0, xmm1
	je	.L1182
.L1179:
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L1182
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	jne	.L1182
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1182
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1182
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1182
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1182
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1182
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1182
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1182:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1185
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1185
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1185
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1185
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1185
	movss	xmm0, DWORD PTR proposed1[rip]
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	ucomiss	xmm0, xmm1
	jp	.L1185
	ucomiss	xmm0, xmm1
	jne	.L1185
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1185
	ucomiss	xmm0, xmm1
	jne	.L1185
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L1188
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L1188
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1188
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1189
.L1188:
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	je	.L1185
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	je	.L1185
	movss	xmm0, DWORD PTR p1_x[rip]
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1185
	ucomiss	xmm0, xmm1
	je	.L1189
.L1185:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L1189
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	jne	.L1189
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1189
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1189
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1189
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1189
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1189
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1189
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1189:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p1_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1193
	ucomiss	xmm0, xmm1
	jne	.L1193
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	test	al, al
	jne	.L1193
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	test	al, al
	jne	.L1193
	movss	xmm0, DWORD PTR p1_x[rip]
	movss	xmm1, DWORD PTR _x_p1_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1193
	ucomiss	xmm0, xmm1
	jne	.L1193
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1193
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1193
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1193
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1193
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1193
	movss	xmm1, DWORD PTR proposed1[rip]
	movss	xmm0, DWORD PTR _x_proposed1[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1196
.L1193:
	movzx	eax, BYTE PTR p1_l0[rip]
	test	al, al
	je	.L1196
	movzx	eax, BYTE PTR p1_l1[rip]
	test	al, al
	je	.L1196
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1196
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1196
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1196
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	je	.L1196
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1196
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1196
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1196:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L1198
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L1199
.L1198:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L1200
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L1199
.L1200:
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L1201
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L1199
.L1201:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L301
.L1199:
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	movss	xmm0, DWORD PTR _x_proposed0[rip]
	comiss	xmm0, xmm1
	jnb	.L1202
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L1202
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L301
.L1202:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1203
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1203
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR p0_x[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x_p0_x[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L1203
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L1203
	movss	xmm0, DWORD PTR p0_saved_max[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1203
	ucomiss	xmm0, xmm1
	jne	.L1203
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	ucomiss	xmm0, xmm1
	jp	.L1203
	ucomiss	xmm0, xmm1
	je	.L1206
.L1203:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jb	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L301
.L1206:
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L1209
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L1209
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1209
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1209
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1209
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1209
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1209
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1209
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1209
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	ucomiss	xmm0, xmm1
	jp	.L1209
	ucomiss	xmm0, xmm1
	jne	.L1209
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1209
	ucomiss	xmm0, xmm1
	je	.L1212
.L1209:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L1212
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L1212
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1212
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1212
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1212
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1212
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1212
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1212
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1212:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1215
	ucomiss	xmm0, xmm1
	jne	.L1215
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L1215
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L1215
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1215
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jne	.L1215
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1215
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1215
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1215
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1215
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1215
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	ucomiss	xmm0, xmm1
	jp	.L1215
	ucomiss	xmm0, xmm1
	je	.L1218
.L1215:
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L1218
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	jne	.L1218
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1218
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1218
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1218
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1218
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1218
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1218
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1218:
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1221
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1221
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1221
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1221
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L1221
	movss	xmm0, DWORD PTR proposed0[rip]
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	ucomiss	xmm0, xmm1
	jp	.L1221
	ucomiss	xmm0, xmm1
	jne	.L1221
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1221
	ucomiss	xmm0, xmm1
	jne	.L1221
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L1224
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L1224
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1224
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	je	.L1225
.L1224:
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	je	.L1221
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	je	.L1221
	movss	xmm0, DWORD PTR p0_x[rip]
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1221
	ucomiss	xmm0, xmm1
	je	.L1225
.L1221:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L1225
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	jne	.L1225
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1225
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1225
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1225
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1225
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1225
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1225
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1225:
	movss	xmm0, DWORD PTR max_prop[rip]
	movss	xmm1, DWORD PTR _x_p0_saved_max[rip]
	ucomiss	xmm0, xmm1
	jp	.L1229
	ucomiss	xmm0, xmm1
	jne	.L1229
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	test	al, al
	jne	.L1229
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	test	al, al
	jne	.L1229
	movss	xmm0, DWORD PTR p0_x[rip]
	movss	xmm1, DWORD PTR _x_p0_x[rip]
	ucomiss	xmm0, xmm1
	jp	.L1229
	ucomiss	xmm0, xmm1
	jne	.L1229
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1229
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1229
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1229
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1229
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1229
	movss	xmm1, DWORD PTR proposed0[rip]
	movss	xmm0, DWORD PTR _x_proposed0[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	jne	.L1232
.L1229:
	movzx	eax, BYTE PTR p0_l0[rip]
	test	al, al
	je	.L1232
	movzx	eax, BYTE PTR p0_l1[rip]
	test	al, al
	je	.L1232
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	jne	.L1232
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	jne	.L1232
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	jne	.L1232
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	jne	.L1232
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	jne	.L1232
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	ucomiss	xmm0, xmm1
	jp	.L1232
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	je	.L301
.L1232:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1234
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1234
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1234
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1234
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1235
.L1234:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1236
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1236
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1236
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1236
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1236:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1237
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1237
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1237
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1237
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1237:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1238
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1238
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1238
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1238
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1235
.L1238:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1239
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1239
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1239
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1239
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1235
.L1239:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1240
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1240
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1240
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1240
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1240:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1241
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1241
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1241
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1241
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1241:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1242
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1242
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1242
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1242
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1235
.L1242:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1243
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1243
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1243
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1243
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1235
.L1243:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1244
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1244
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1244
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1244
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1244:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	je	.L1245
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1245
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1245
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1245
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1245:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1246
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1246
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1246
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1246
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1235
.L1246:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1247
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1247
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1247
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1247
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1235
.L1247:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1248
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1248
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1248
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1248
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1248:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1249
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1249
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1249
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1249
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1249:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1250
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1250
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1250
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1250
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1235
.L1250:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1251
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1251
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1251
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1251
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1235
.L1251:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1252
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1252
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1252
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1252
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1252:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1253
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	je	.L1253
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1253
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1253
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1253:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1254
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1254
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1254
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1254
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1235
.L1254:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1255
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1255
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1255
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1255
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1235
.L1255:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1256
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1256
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1256
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1256
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1256:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1257
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1257
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	je	.L1257
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1257
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1257:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1258
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1258
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1258
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1258
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L1235
.L1258:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1259
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1259
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1259
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1259
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L1235
.L1259:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	jne	.L1260
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	je	.L1235
.L1260:
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	jne	.L301
.L1235:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1261
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1261
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1261
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1261
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1261:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1263
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1263
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1263
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1263
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1263:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1264
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1264
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1264
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1264
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1262
.L1264:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1265
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1265
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1265
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1265
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1262
.L1265:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1266
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1266
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1266
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1266
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1266:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1267
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1267
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1267
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1267
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1267:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1268
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1268
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1268
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1268
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1262
.L1268:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1269
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1269
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1269
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1269
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1262
.L1269:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1270
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1270
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1270
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1270
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1270:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	je	.L1271
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1271
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1271
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1271
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1271:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1272
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1272
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1272
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1272
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1262
.L1272:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1273
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1273
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1273
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1273
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1262
.L1273:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1274
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1274
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1274
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1274
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1274:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1275
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1275
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1275
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1275
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1275:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1276
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1276
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1276
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1276
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1262
.L1276:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1277
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1277
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1277
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1277
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1262
.L1277:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1278
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1278
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1278
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1278
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1278:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1279
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	je	.L1279
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1279
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1279
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1279:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1280
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1280
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1280
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1280
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1262
.L1280:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1281
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1281
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1281
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1281
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1262
.L1281:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1282
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1282
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1282
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1282
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1282:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1283
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1283
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	je	.L1283
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1283
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1283:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1284
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1284
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1284
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1284
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L1262
.L1284:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1285
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1285
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1285
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1285
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L1262
.L1285:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L1286
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L1286
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L1286
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	jne	.L1286
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	je	.L1262
.L1286:
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	jne	.L301
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	jne	.L301
.L1262:
	movss	xmm1, DWORD PTR delta[rip]
	pxor	xmm0, xmm0
	comiss	xmm0, xmm1
	jnb	.L1287
	movzx	eax, BYTE PTR _x_inc_max_prop[rip]
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR id0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR id1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR id2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR id3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR id4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_id4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn0[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn0[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn1[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn1[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn2[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn2[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn3[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn3[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
	movzx	eax, BYTE PTR turn4[rip]
	test	al, al
	sete	dl
	movzx	eax, BYTE PTR _x_turn4[rip]
	test	al, al
	setne	al
	xor	eax, edx
	test	al, al
	je	.L301
.L1287:
	movss	xmm0, DWORD PTR _x_delta[rip]
	pxor	xmm1, xmm1
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed0[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed1[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed2[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed3[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed4[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed5[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed6[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed7[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed8[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed9[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed10[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed11[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed12[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed13[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed14[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed15[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed16[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed17[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed18[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed19[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed20[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed21[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed22[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed23[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed24[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm1, DWORD PTR _x_proposed25[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	jb	.L301
	movss	xmm0, DWORD PTR _x_proposed0[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1767
	ucomiss	xmm0, xmm1
	je	.L1315
.L1767:
	movss	xmm0, DWORD PTR _x_proposed1[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1768
	ucomiss	xmm0, xmm1
	je	.L1315
.L1768:
	movss	xmm0, DWORD PTR _x_proposed2[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1769
	ucomiss	xmm0, xmm1
	je	.L1315
.L1769:
	movss	xmm0, DWORD PTR _x_proposed3[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1770
	ucomiss	xmm0, xmm1
	je	.L1315
.L1770:
	movss	xmm0, DWORD PTR _x_proposed4[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1771
	ucomiss	xmm0, xmm1
	je	.L1315
.L1771:
	movss	xmm0, DWORD PTR _x_proposed5[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1772
	ucomiss	xmm0, xmm1
	je	.L1315
.L1772:
	movss	xmm0, DWORD PTR _x_proposed6[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1773
	ucomiss	xmm0, xmm1
	je	.L1315
.L1773:
	movss	xmm0, DWORD PTR _x_proposed7[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1774
	ucomiss	xmm0, xmm1
	je	.L1315
.L1774:
	movss	xmm0, DWORD PTR _x_proposed8[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1775
	ucomiss	xmm0, xmm1
	je	.L1315
.L1775:
	movss	xmm0, DWORD PTR _x_proposed9[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1776
	ucomiss	xmm0, xmm1
	je	.L1315
.L1776:
	movss	xmm0, DWORD PTR _x_proposed10[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1777
	ucomiss	xmm0, xmm1
	je	.L1315
.L1777:
	movss	xmm0, DWORD PTR _x_proposed11[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1778
	ucomiss	xmm0, xmm1
	je	.L1315
.L1778:
	movss	xmm0, DWORD PTR _x_proposed12[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1779
	ucomiss	xmm0, xmm1
	je	.L1315
.L1779:
	movss	xmm0, DWORD PTR _x_proposed13[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1780
	ucomiss	xmm0, xmm1
	je	.L1315
.L1780:
	movss	xmm0, DWORD PTR _x_proposed14[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1781
	ucomiss	xmm0, xmm1
	je	.L1315
.L1781:
	movss	xmm0, DWORD PTR _x_proposed15[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1782
	ucomiss	xmm0, xmm1
	je	.L1315
.L1782:
	movss	xmm0, DWORD PTR _x_proposed16[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1783
	ucomiss	xmm0, xmm1
	je	.L1315
.L1783:
	movss	xmm0, DWORD PTR _x_proposed17[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1784
	ucomiss	xmm0, xmm1
	je	.L1315
.L1784:
	movss	xmm0, DWORD PTR _x_proposed18[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1785
	ucomiss	xmm0, xmm1
	je	.L1315
.L1785:
	movss	xmm0, DWORD PTR _x_proposed19[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1786
	ucomiss	xmm0, xmm1
	je	.L1315
.L1786:
	movss	xmm0, DWORD PTR _x_proposed20[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1787
	ucomiss	xmm0, xmm1
	je	.L1315
.L1787:
	movss	xmm0, DWORD PTR _x_proposed21[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1788
	ucomiss	xmm0, xmm1
	je	.L1315
.L1788:
	movss	xmm0, DWORD PTR _x_proposed22[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1789
	ucomiss	xmm0, xmm1
	je	.L1315
.L1789:
	movss	xmm0, DWORD PTR _x_proposed23[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1790
	ucomiss	xmm0, xmm1
	je	.L1315
.L1790:
	movss	xmm0, DWORD PTR _x_proposed24[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L1791
	ucomiss	xmm0, xmm1
	je	.L1315
.L1791:
	movss	xmm0, DWORD PTR _x_proposed25[rip]
	movss	xmm1, DWORD PTR _x_max_prop[rip]
	ucomiss	xmm0, xmm1
	jp	.L301
	ucomiss	xmm0, xmm1
	jne	.L301
.L1315:
	movzx	eax, BYTE PTR _x_inc_max_prop[rip]
	test	al, al
	sete	dl
	movss	xmm1, DWORD PTR max_prop[rip]
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, edx
	test	al, al
	je	.L301
	movss	xmm0, DWORD PTR delta[rip]
	movss	xmm1, DWORD PTR _x__diverge_delta[rip]
	ucomiss	xmm0, xmm1
	jp	.L1792
	ucomiss	xmm0, xmm1
	je	.L1342
.L1792:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	setnb	al
	xor	eax, 1
	test	al, al
	je	.L301
.L1342:
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	movss	xmm1, DWORD PTR .LC2[rip]
	comiss	xmm0, xmm1
	jnb	.L1344
	movss	xmm0, DWORD PTR delta[rip]
	pxor	xmm1, xmm1
	cvtss2sd	xmm1, xmm0
	movss	xmm0, DWORD PTR _diverge_delta[rip]
	cvtss2sd	xmm0, xmm0
	movss	xmm2, DWORD PTR _x__diverge_delta[rip]
	cvtss2sd	xmm2, xmm2
	subsd	xmm0, xmm2
	addsd	xmm0, xmm1
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jp	.L301
	pxor	xmm1, xmm1
	ucomisd	xmm0, xmm1
	jne	.L301
.L1344:
	mov	eax, 1
	jmp	.L1346
.L301:
	mov	eax, 0
.L1346:
	mov	DWORD PTR -4[rbp], eax
	movzx	eax, BYTE PTR _x_p25_l1[rip]
	mov	BYTE PTR p25_l1[rip], al
	movzx	eax, BYTE PTR _x_p25_l0[rip]
	mov	BYTE PTR p25_l0[rip], al
	movzx	eax, BYTE PTR _x_p24_l1[rip]
	mov	BYTE PTR p24_l1[rip], al
	movzx	eax, BYTE PTR _x_p24_l0[rip]
	mov	BYTE PTR p24_l0[rip], al
	movzx	eax, BYTE PTR _x_p23_l1[rip]
	mov	BYTE PTR p23_l1[rip], al
	movzx	eax, BYTE PTR _x_p23_l0[rip]
	mov	BYTE PTR p23_l0[rip], al
	movss	xmm0, DWORD PTR _x_p24_saved_max[rip]
	movss	DWORD PTR p24_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p4_l1[rip]
	mov	BYTE PTR p4_l1[rip], al
	movzx	eax, BYTE PTR _x_p9_l0[rip]
	mov	BYTE PTR p9_l0[rip], al
	movzx	eax, BYTE PTR _x_p0_l1[rip]
	mov	BYTE PTR p0_l1[rip], al
	movss	xmm0, DWORD PTR _x_p11_saved_max[rip]
	movss	DWORD PTR p11_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p16_x[rip]
	movss	DWORD PTR p16_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p24_x[rip]
	movss	DWORD PTR p24_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p4_l0[rip]
	mov	BYTE PTR p4_l0[rip], al
	movzx	eax, BYTE PTR _x_p0_l0[rip]
	mov	BYTE PTR p0_l0[rip], al
	movss	xmm0, DWORD PTR _x_p6_saved_max[rip]
	movss	DWORD PTR p6_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p11_x[rip]
	movss	DWORD PTR p11_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p4_saved_max[rip]
	movss	DWORD PTR p4_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_turn0[rip]
	mov	BYTE PTR turn0[rip], al
	movss	xmm0, DWORD PTR _x_p9_x[rip]
	movss	DWORD PTR p9_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p23_saved_max[rip]
	movss	DWORD PTR p23_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p3_l1[rip]
	mov	BYTE PTR p3_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed4[rip]
	movss	DWORD PTR proposed4[rip], xmm0
	movzx	eax, BYTE PTR _x_p8_l0[rip]
	mov	BYTE PTR p8_l0[rip], al
	movss	xmm0, DWORD PTR _x_p0_saved_max[rip]
	movss	DWORD PTR p0_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p4_x[rip]
	movss	DWORD PTR p4_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p23_x[rip]
	movss	DWORD PTR p23_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p3_l0[rip]
	mov	BYTE PTR p3_l0[rip], al
	movss	xmm0, DWORD PTR _x_proposed3[rip]
	movss	DWORD PTR proposed3[rip], xmm0
	movss	xmm0, DWORD PTR _x_p0_x[rip]
	movss	DWORD PTR p0_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed25[rip]
	movss	DWORD PTR proposed25[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed24[rip]
	movss	DWORD PTR proposed24[rip], xmm0
	movzx	eax, BYTE PTR _x_turn4[rip]
	mov	BYTE PTR turn4[rip], al
	movss	xmm0, DWORD PTR _x_delta[rip]
	movss	DWORD PTR delta[rip], xmm0
	movzx	eax, BYTE PTR _x_id4[rip]
	mov	BYTE PTR id4[rip], al
	movss	xmm0, DWORD PTR _x_proposed2[rip]
	movss	DWORD PTR proposed2[rip], xmm0
	movzx	eax, BYTE PTR _x_turn3[rip]
	mov	BYTE PTR turn3[rip], al
	movss	xmm0, DWORD PTR _x_p19_saved_max[rip]
	movss	DWORD PTR p19_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_max_prop[rip]
	movss	DWORD PTR max_prop[rip], xmm0
	movzx	eax, BYTE PTR _x_id3[rip]
	mov	BYTE PTR id3[rip], al
	movss	xmm0, DWORD PTR _x_proposed1[rip]
	movss	DWORD PTR proposed1[rip], xmm0
	movzx	eax, BYTE PTR _x_turn2[rip]
	mov	BYTE PTR turn2[rip], al
	movss	xmm0, DWORD PTR _x_p14_saved_max[rip]
	movss	DWORD PTR p14_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p19_x[rip]
	movss	DWORD PTR p19_x[rip], xmm0
	movzx	eax, BYTE PTR _x_id2[rip]
	mov	BYTE PTR id2[rip], al
	movss	xmm0, DWORD PTR _x_proposed0[rip]
	movss	DWORD PTR proposed0[rip], xmm0
	movss	xmm0, DWORD PTR _x_p3_saved_max[rip]
	movss	DWORD PTR p3_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p8_x[rip]
	movss	DWORD PTR p8_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed12[rip]
	movss	DWORD PTR proposed12[rip], xmm0
	movzx	eax, BYTE PTR _x_p7_l0[rip]
	mov	BYTE PTR p7_l0[rip], al
	movzx	eax, BYTE PTR _x_turn1[rip]
	mov	BYTE PTR turn1[rip], al
	movss	xmm0, DWORD PTR _x_p9_saved_max[rip]
	movss	DWORD PTR p9_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p14_x[rip]
	movss	DWORD PTR p14_x[rip], xmm0
	movzx	eax, BYTE PTR _x_id1[rip]
	mov	BYTE PTR id1[rip], al
	movzx	eax, BYTE PTR _x_inc_max_prop[rip]
	mov	BYTE PTR inc_max_prop[rip], al
	movss	xmm0, DWORD PTR _x_p3_x[rip]
	movss	DWORD PTR p3_x[rip], xmm0
	movzx	eax, BYTE PTR _x_id0[rip]
	mov	BYTE PTR id0[rip], al
	movss	xmm0, DWORD PTR _x_proposed22[rip]
	movss	DWORD PTR proposed22[rip], xmm0
	movss	xmm0, DWORD PTR _x_p2_x[rip]
	movss	DWORD PTR p2_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed23[rip]
	movss	DWORD PTR proposed23[rip], xmm0
	movss	xmm0, DWORD PTR _x_p2_saved_max[rip]
	movss	DWORD PTR p2_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed20[rip]
	movss	DWORD PTR proposed20[rip], xmm0
	movss	xmm0, DWORD PTR _x_p7_x[rip]
	movss	DWORD PTR p7_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p6_l0[rip]
	mov	BYTE PTR p6_l0[rip], al
	movss	xmm0, DWORD PTR _x_proposed5[rip]
	movss	DWORD PTR proposed5[rip], xmm0
	movzx	eax, BYTE PTR _x_p8_l1[rip]
	mov	BYTE PTR p8_l1[rip], al
	movzx	eax, BYTE PTR _x_p13_l0[rip]
	mov	BYTE PTR p13_l0[rip], al
	movzx	eax, BYTE PTR _x_p22_l0[rip]
	mov	BYTE PTR p22_l0[rip], al
	movss	xmm0, DWORD PTR _x_proposed6[rip]
	movss	DWORD PTR proposed6[rip], xmm0
	movzx	eax, BYTE PTR _x_p13_l1[rip]
	mov	BYTE PTR p13_l1[rip], al
	movzx	eax, BYTE PTR _x_p18_l0[rip]
	mov	BYTE PTR p18_l0[rip], al
	movzx	eax, BYTE PTR _x_p22_l1[rip]
	mov	BYTE PTR p22_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed7[rip]
	movss	DWORD PTR proposed7[rip], xmm0
	movzx	eax, BYTE PTR _x_p18_l1[rip]
	mov	BYTE PTR p18_l1[rip], al
	movss	xmm0, DWORD PTR _x_p1_x[rip]
	movss	DWORD PTR p1_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p1_saved_max[rip]
	movss	DWORD PTR p1_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p6_x[rip]
	movss	DWORD PTR p6_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p8_saved_max[rip]
	movss	DWORD PTR p8_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p13_x[rip]
	movss	DWORD PTR p13_x[rip], xmm0
	movss	xmm0, DWORD PTR _x__diverge_delta[rip]
	movss	DWORD PTR _diverge_delta[rip], xmm0
	movss	xmm0, DWORD PTR _x_p22_x[rip]
	movss	DWORD PTR p22_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p2_l0[rip]
	mov	BYTE PTR p2_l0[rip], al
	movss	xmm0, DWORD PTR _x_proposed14[rip]
	movss	DWORD PTR proposed14[rip], xmm0
	movss	xmm0, DWORD PTR _x_p13_saved_max[rip]
	movss	DWORD PTR p13_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p18_x[rip]
	movss	DWORD PTR p18_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p22_saved_max[rip]
	movss	DWORD PTR p22_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p2_l1[rip]
	mov	BYTE PTR p2_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed15[rip]
	movss	DWORD PTR proposed15[rip], xmm0
	movss	xmm0, DWORD PTR _x_p18_saved_max[rip]
	movss	DWORD PTR p18_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p5_x[rip]
	movss	DWORD PTR p5_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p5_saved_max[rip]
	movss	DWORD PTR p5_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p10_x[rip]
	movss	DWORD PTR p10_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_p25_x[rip]
	movss	DWORD PTR p25_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p5_l0[rip]
	mov	BYTE PTR p5_l0[rip], al
	movss	xmm0, DWORD PTR _x_p25_saved_max[rip]
	movss	DWORD PTR p25_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p5_l1[rip]
	mov	BYTE PTR p5_l1[rip], al
	movzx	eax, BYTE PTR _x_p10_l0[rip]
	mov	BYTE PTR p10_l0[rip], al
	movzx	eax, BYTE PTR _x_p6_l1[rip]
	mov	BYTE PTR p6_l1[rip], al
	movzx	eax, BYTE PTR _x_p11_l0[rip]
	mov	BYTE PTR p11_l0[rip], al
	movss	xmm0, DWORD PTR _x_proposed21[rip]
	movss	DWORD PTR proposed21[rip], xmm0
	movss	xmm0, DWORD PTR _x_p7_saved_max[rip]
	movss	DWORD PTR p7_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed18[rip]
	movss	DWORD PTR proposed18[rip], xmm0
	movss	xmm0, DWORD PTR _x_p12_x[rip]
	movss	DWORD PTR p12_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed13[rip]
	movss	DWORD PTR proposed13[rip], xmm0
	movzx	eax, BYTE PTR _x_p7_l1[rip]
	mov	BYTE PTR p7_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed10[rip]
	movss	DWORD PTR proposed10[rip], xmm0
	movzx	eax, BYTE PTR _x_p12_l0[rip]
	mov	BYTE PTR p12_l0[rip], al
	movzx	eax, BYTE PTR _x_p9_l1[rip]
	mov	BYTE PTR p9_l1[rip], al
	movzx	eax, BYTE PTR _x_p14_l0[rip]
	mov	BYTE PTR p14_l0[rip], al
	movss	xmm0, DWORD PTR _x_p10_saved_max[rip]
	movss	DWORD PTR p10_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p15_x[rip]
	movss	DWORD PTR p15_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p10_l1[rip]
	mov	BYTE PTR p10_l1[rip], al
	movzx	eax, BYTE PTR _x_p15_l0[rip]
	mov	BYTE PTR p15_l0[rip], al
	movzx	eax, BYTE PTR _x_p11_l1[rip]
	mov	BYTE PTR p11_l1[rip], al
	movzx	eax, BYTE PTR _x_p16_l0[rip]
	mov	BYTE PTR p16_l0[rip], al
	movss	xmm0, DWORD PTR _x_proposed19[rip]
	movss	DWORD PTR proposed19[rip], xmm0
	movss	xmm0, DWORD PTR _x_p12_saved_max[rip]
	movss	DWORD PTR p12_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed16[rip]
	movss	DWORD PTR proposed16[rip], xmm0
	movss	xmm0, DWORD PTR _x_p17_x[rip]
	movss	DWORD PTR p17_x[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed11[rip]
	movss	DWORD PTR proposed11[rip], xmm0
	movzx	eax, BYTE PTR _x_p12_l1[rip]
	mov	BYTE PTR p12_l1[rip], al
	movss	xmm0, DWORD PTR _x_proposed8[rip]
	movss	DWORD PTR proposed8[rip], xmm0
	movzx	eax, BYTE PTR _x_p17_l0[rip]
	mov	BYTE PTR p17_l0[rip], al
	movzx	eax, BYTE PTR _x_p14_l1[rip]
	mov	BYTE PTR p14_l1[rip], al
	movzx	eax, BYTE PTR _x_p19_l0[rip]
	mov	BYTE PTR p19_l0[rip], al
	movss	xmm0, DWORD PTR _x_p15_saved_max[rip]
	movss	DWORD PTR p15_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_p20_x[rip]
	movss	DWORD PTR p20_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p15_l1[rip]
	mov	BYTE PTR p15_l1[rip], al
	movzx	eax, BYTE PTR _x_p20_l0[rip]
	mov	BYTE PTR p20_l0[rip], al
	movss	xmm0, DWORD PTR _x_p16_saved_max[rip]
	movss	DWORD PTR p16_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p1_l0[rip]
	mov	BYTE PTR p1_l0[rip], al
	movss	xmm0, DWORD PTR _x_p21_x[rip]
	movss	DWORD PTR p21_x[rip], xmm0
	movzx	eax, BYTE PTR _x_p16_l1[rip]
	mov	BYTE PTR p16_l1[rip], al
	movzx	eax, BYTE PTR _x_p21_l0[rip]
	mov	BYTE PTR p21_l0[rip], al
	movss	xmm0, DWORD PTR _x_proposed17[rip]
	movss	DWORD PTR proposed17[rip], xmm0
	movss	xmm0, DWORD PTR _x_p17_saved_max[rip]
	movss	DWORD PTR p17_saved_max[rip], xmm0
	movss	xmm0, DWORD PTR _x_proposed9[rip]
	movss	DWORD PTR proposed9[rip], xmm0
	movzx	eax, BYTE PTR _x_p17_l1[rip]
	mov	BYTE PTR p17_l1[rip], al
	movzx	eax, BYTE PTR _x_p19_l1[rip]
	mov	BYTE PTR p19_l1[rip], al
	movss	xmm0, DWORD PTR _x_p20_saved_max[rip]
	movss	DWORD PTR p20_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p20_l1[rip]
	mov	BYTE PTR p20_l1[rip], al
	movzx	eax, BYTE PTR _x_p1_l1[rip]
	mov	BYTE PTR p1_l1[rip], al
	movss	xmm0, DWORD PTR _x_p21_saved_max[rip]
	movss	DWORD PTR p21_saved_max[rip], xmm0
	movzx	eax, BYTE PTR _x_p21_l1[rip]
	mov	BYTE PTR p21_l1[rip], al
.L296:
	cmp	DWORD PTR -4[rbp], 0
	jne	.L1347
	mov	eax, 0
	leave
	.cfi_def_cfa 7, 8
	ret
	.cfi_endproc
.LFE1:
	.size	main, .-main
	.section	.rodata
	.align 4
.LC2:
	.long	1065353216
	.ident	"GCC: (Ubuntu 10.5.0-1ubuntu1~20.04) 10.5.0"
	.section	.note.GNU-stack,"",@progbits
	.section	.note.gnu.property,"a"
	.align 8
	.long	 1f - 0f
	.long	 4f - 1f
	.long	 5
0:
	.string	 "GNU"
1:
	.align 8
	.long	 0xc0000002
	.long	 3f - 2f
2:
	.long	 0x3
3:
	.align 8
4:

	.arch armv5t
	.eabi_attribute 20, 1
	.eabi_attribute 21, 1
	.eabi_attribute 23, 3
	.eabi_attribute 24, 1
	.eabi_attribute 25, 1
	.eabi_attribute 26, 2
	.eabi_attribute 30, 6
	.eabi_attribute 34, 0
	.eabi_attribute 18, 4
	.file	"952107.c"
	.text
	.align	2
	.global	__VERIFIER_nondet_bool
	.syntax unified
	.arm
	.fpu softvfp
	.type	__VERIFIER_nondet_bool, %function
__VERIFIER_nondet_bool:
	@ args = 0, pretend = 0, frame = 0
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{fp, lr}
	add	fp, sp, #4
	bl	__VERIFIER_nondet_int
	mov	r3, r0
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	mov	r0, r3
	pop	{fp, pc}
	.size	__VERIFIER_nondet_bool, .-__VERIFIER_nondet_bool
	.comm	p25_l1,1,1
	.comm	_x_p25_l1,1,1
	.comm	p25_l0,1,1
	.comm	_x_p25_l0,1,1
	.comm	p24_l1,1,1
	.comm	_x_p24_l1,1,1
	.comm	p24_l0,1,1
	.comm	_x_p24_l0,1,1
	.comm	p23_l1,1,1
	.comm	_x_p23_l1,1,1
	.comm	p23_l0,1,1
	.comm	_x_p23_l0,1,1
	.comm	p24_saved_max,4,4
	.comm	_x_p24_saved_max,4,4
	.comm	p4_l1,1,1
	.comm	_x_p4_l1,1,1
	.comm	p9_l0,1,1
	.comm	_x_p9_l0,1,1
	.comm	p0_l1,1,1
	.comm	_x_p0_l1,1,1
	.comm	p11_saved_max,4,4
	.comm	_x_p11_saved_max,4,4
	.comm	p16_x,4,4
	.comm	_x_p16_x,4,4
	.comm	p24_x,4,4
	.comm	_x_p24_x,4,4
	.comm	p4_l0,1,1
	.comm	_x_p4_l0,1,1
	.comm	p0_l0,1,1
	.comm	_x_p0_l0,1,1
	.comm	p6_saved_max,4,4
	.comm	_x_p6_saved_max,4,4
	.comm	p11_x,4,4
	.comm	_x_p11_x,4,4
	.comm	p4_saved_max,4,4
	.comm	_x_p4_saved_max,4,4
	.comm	turn0,1,1
	.comm	_x_turn0,1,1
	.comm	p9_x,4,4
	.comm	_x_p9_x,4,4
	.comm	p23_saved_max,4,4
	.comm	_x_p23_saved_max,4,4
	.comm	p3_l1,1,1
	.comm	_x_p3_l1,1,1
	.comm	proposed4,4,4
	.comm	_x_proposed4,4,4
	.comm	p8_l0,1,1
	.comm	_x_p8_l0,1,1
	.comm	p0_saved_max,4,4
	.comm	_x_p0_saved_max,4,4
	.comm	p4_x,4,4
	.comm	_x_p4_x,4,4
	.comm	p23_x,4,4
	.comm	_x_p23_x,4,4
	.comm	p3_l0,1,1
	.comm	_x_p3_l0,1,1
	.comm	proposed3,4,4
	.comm	_x_proposed3,4,4
	.comm	p0_x,4,4
	.comm	_x_p0_x,4,4
	.comm	proposed25,4,4
	.comm	_x_proposed25,4,4
	.comm	proposed24,4,4
	.comm	_x_proposed24,4,4
	.comm	turn4,1,1
	.comm	_x_turn4,1,1
	.comm	delta,4,4
	.comm	_x_delta,4,4
	.comm	id4,1,1
	.comm	_x_id4,1,1
	.comm	proposed2,4,4
	.comm	_x_proposed2,4,4
	.comm	turn3,1,1
	.comm	_x_turn3,1,1
	.comm	p19_saved_max,4,4
	.comm	_x_p19_saved_max,4,4
	.comm	max_prop,4,4
	.comm	_x_max_prop,4,4
	.comm	id3,1,1
	.comm	_x_id3,1,1
	.comm	proposed1,4,4
	.comm	_x_proposed1,4,4
	.comm	turn2,1,1
	.comm	_x_turn2,1,1
	.comm	p14_saved_max,4,4
	.comm	_x_p14_saved_max,4,4
	.comm	p19_x,4,4
	.comm	_x_p19_x,4,4
	.comm	id2,1,1
	.comm	_x_id2,1,1
	.comm	proposed0,4,4
	.comm	_x_proposed0,4,4
	.comm	p3_saved_max,4,4
	.comm	_x_p3_saved_max,4,4
	.comm	p8_x,4,4
	.comm	_x_p8_x,4,4
	.comm	proposed12,4,4
	.comm	_x_proposed12,4,4
	.comm	p7_l0,1,1
	.comm	_x_p7_l0,1,1
	.comm	turn1,1,1
	.comm	_x_turn1,1,1
	.comm	p9_saved_max,4,4
	.comm	_x_p9_saved_max,4,4
	.comm	p14_x,4,4
	.comm	_x_p14_x,4,4
	.comm	id1,1,1
	.comm	_x_id1,1,1
	.comm	inc_max_prop,1,1
	.comm	_x_inc_max_prop,1,1
	.comm	p3_x,4,4
	.comm	_x_p3_x,4,4
	.comm	id0,1,1
	.comm	_x_id0,1,1
	.comm	proposed22,4,4
	.comm	_x_proposed22,4,4
	.comm	p2_x,4,4
	.comm	_x_p2_x,4,4
	.comm	proposed23,4,4
	.comm	_x_proposed23,4,4
	.comm	p2_saved_max,4,4
	.comm	_x_p2_saved_max,4,4
	.comm	proposed20,4,4
	.comm	_x_proposed20,4,4
	.comm	p7_x,4,4
	.comm	_x_p7_x,4,4
	.comm	p6_l0,1,1
	.comm	_x_p6_l0,1,1
	.comm	proposed5,4,4
	.comm	_x_proposed5,4,4
	.comm	p8_l1,1,1
	.comm	_x_p8_l1,1,1
	.comm	p13_l0,1,1
	.comm	_x_p13_l0,1,1
	.comm	p22_l0,1,1
	.comm	_x_p22_l0,1,1
	.comm	proposed6,4,4
	.comm	_x_proposed6,4,4
	.comm	p13_l1,1,1
	.comm	_x_p13_l1,1,1
	.comm	p18_l0,1,1
	.comm	_x_p18_l0,1,1
	.comm	p22_l1,1,1
	.comm	_x_p22_l1,1,1
	.comm	proposed7,4,4
	.comm	_x_proposed7,4,4
	.comm	p18_l1,1,1
	.comm	_x_p18_l1,1,1
	.comm	p1_x,4,4
	.comm	_x_p1_x,4,4
	.comm	p1_saved_max,4,4
	.comm	_x_p1_saved_max,4,4
	.comm	p6_x,4,4
	.comm	_x_p6_x,4,4
	.comm	p8_saved_max,4,4
	.comm	_x_p8_saved_max,4,4
	.comm	p13_x,4,4
	.comm	_x_p13_x,4,4
	.comm	_diverge_delta,4,4
	.comm	_x__diverge_delta,4,4
	.comm	p22_x,4,4
	.comm	_x_p22_x,4,4
	.comm	p2_l0,1,1
	.comm	_x_p2_l0,1,1
	.comm	proposed14,4,4
	.comm	_x_proposed14,4,4
	.comm	p13_saved_max,4,4
	.comm	_x_p13_saved_max,4,4
	.comm	p18_x,4,4
	.comm	_x_p18_x,4,4
	.comm	p22_saved_max,4,4
	.comm	_x_p22_saved_max,4,4
	.comm	p2_l1,1,1
	.comm	_x_p2_l1,1,1
	.comm	proposed15,4,4
	.comm	_x_proposed15,4,4
	.comm	p18_saved_max,4,4
	.comm	_x_p18_saved_max,4,4
	.comm	p5_x,4,4
	.comm	_x_p5_x,4,4
	.comm	p5_saved_max,4,4
	.comm	_x_p5_saved_max,4,4
	.comm	p10_x,4,4
	.comm	_x_p10_x,4,4
	.comm	p25_x,4,4
	.comm	_x_p25_x,4,4
	.comm	p5_l0,1,1
	.comm	_x_p5_l0,1,1
	.comm	p25_saved_max,4,4
	.comm	_x_p25_saved_max,4,4
	.comm	p5_l1,1,1
	.comm	_x_p5_l1,1,1
	.comm	p10_l0,1,1
	.comm	_x_p10_l0,1,1
	.comm	p6_l1,1,1
	.comm	_x_p6_l1,1,1
	.comm	p11_l0,1,1
	.comm	_x_p11_l0,1,1
	.comm	proposed21,4,4
	.comm	_x_proposed21,4,4
	.comm	p7_saved_max,4,4
	.comm	_x_p7_saved_max,4,4
	.comm	proposed18,4,4
	.comm	_x_proposed18,4,4
	.comm	p12_x,4,4
	.comm	_x_p12_x,4,4
	.comm	proposed13,4,4
	.comm	_x_proposed13,4,4
	.comm	p7_l1,1,1
	.comm	_x_p7_l1,1,1
	.comm	proposed10,4,4
	.comm	_x_proposed10,4,4
	.comm	p12_l0,1,1
	.comm	_x_p12_l0,1,1
	.comm	p9_l1,1,1
	.comm	_x_p9_l1,1,1
	.comm	p14_l0,1,1
	.comm	_x_p14_l0,1,1
	.comm	p10_saved_max,4,4
	.comm	_x_p10_saved_max,4,4
	.comm	p15_x,4,4
	.comm	_x_p15_x,4,4
	.comm	p10_l1,1,1
	.comm	_x_p10_l1,1,1
	.comm	p15_l0,1,1
	.comm	_x_p15_l0,1,1
	.comm	p11_l1,1,1
	.comm	_x_p11_l1,1,1
	.comm	p16_l0,1,1
	.comm	_x_p16_l0,1,1
	.comm	proposed19,4,4
	.comm	_x_proposed19,4,4
	.comm	p12_saved_max,4,4
	.comm	_x_p12_saved_max,4,4
	.comm	proposed16,4,4
	.comm	_x_proposed16,4,4
	.comm	p17_x,4,4
	.comm	_x_p17_x,4,4
	.comm	proposed11,4,4
	.comm	_x_proposed11,4,4
	.comm	p12_l1,1,1
	.comm	_x_p12_l1,1,1
	.comm	proposed8,4,4
	.comm	_x_proposed8,4,4
	.comm	p17_l0,1,1
	.comm	_x_p17_l0,1,1
	.comm	p14_l1,1,1
	.comm	_x_p14_l1,1,1
	.comm	p19_l0,1,1
	.comm	_x_p19_l0,1,1
	.comm	p15_saved_max,4,4
	.comm	_x_p15_saved_max,4,4
	.comm	p20_x,4,4
	.comm	_x_p20_x,4,4
	.comm	p15_l1,1,1
	.comm	_x_p15_l1,1,1
	.comm	p20_l0,1,1
	.comm	_x_p20_l0,1,1
	.comm	p16_saved_max,4,4
	.comm	_x_p16_saved_max,4,4
	.comm	p1_l0,1,1
	.comm	_x_p1_l0,1,1
	.comm	p21_x,4,4
	.comm	_x_p21_x,4,4
	.comm	p16_l1,1,1
	.comm	_x_p16_l1,1,1
	.comm	p21_l0,1,1
	.comm	_x_p21_l0,1,1
	.comm	proposed17,4,4
	.comm	_x_proposed17,4,4
	.comm	p17_saved_max,4,4
	.comm	_x_p17_saved_max,4,4
	.comm	proposed9,4,4
	.comm	_x_proposed9,4,4
	.comm	p17_l1,1,1
	.comm	_x_p17_l1,1,1
	.comm	p19_l1,1,1
	.comm	_x_p19_l1,1,1
	.comm	p20_saved_max,4,4
	.comm	_x_p20_saved_max,4,4
	.comm	p20_l1,1,1
	.comm	_x_p20_l1,1,1
	.comm	p1_l1,1,1
	.comm	_x_p1_l1,1,1
	.comm	p21_saved_max,4,4
	.comm	_x_p21_saved_max,4,4
	.comm	p21_l1,1,1
	.comm	_x_p21_l1,1,1
	.global	__aeabi_fcmpeq
	.global	__aeabi_fcmple
	.global	__aeabi_fcmpge
	.global	__aeabi_f2d
	.global	__aeabi_dsub
	.global	__aeabi_dadd
	.global	__aeabi_dcmpeq
	.align	2
	.global	main
	.syntax unified
	.arm
	.fpu softvfp
	.type	main, %function
main:
	@ args = 0, pretend = 0, frame = 8
	@ frame_needed = 1, uses_anonymous_args = 0
	push	{r4, r5, r6, r7, fp, lr}
	add	fp, sp, #20
	sub	sp, sp, #8
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+4
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+8
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+12
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+16
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+20
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+24
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+28
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+32
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+36
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+40
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+44
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+48
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+52
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+56
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+60
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+64
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+68
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+72
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+76
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+80
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+84
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+88
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+92
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+96
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+100
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+104
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+112
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+116
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+120
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+124
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+132
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+140
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+144
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+396
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+556
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+148
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+152
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+496
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+400
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+160
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+164
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+168
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+172
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+544
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+176
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+180
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+184
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+500
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+188
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+196
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+200
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+204
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+208
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+212
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+216
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+384
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+220
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+228
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+232
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+532
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+236
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+240
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+528
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+432
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+244
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+248
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+428
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+252
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+256
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+264
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+520
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+268
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+272
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+276
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+504
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+516
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+420
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+280
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+484
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+416
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+288
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+292
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+296
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+300
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+304
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+308
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+312
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+580
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+316
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+576
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+364
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+320
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+424
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+540
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+524
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+324
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+328
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+552
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+332
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+512
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+336
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+480
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+584
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+492
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+572
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+472
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+404
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+536
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+464
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+440
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+568
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+548
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+340
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+452
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+508
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+412
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+476
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+380
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+488
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+392
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+456
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+360
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+468
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+372
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+444
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+436
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+348
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+448
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+408
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+376
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+388
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1641+356
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1641+368
	strb	r2, [r3]
	ldr	r3, .L1641+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L5
	ldr	r3, .L1641
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L5:
	ldr	r3, .L1641+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L7
	ldr	r3, .L1641
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L7:
	ldr	r3, .L1641
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L8
	ldr	r3, .L1641+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L6
.L8:
	ldr	r3, .L1641+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L6:
	ldr	r3, .L1641+300
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+308
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+120
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L11
	mov	r3, #0
	mov	r4, r3
.L11:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+300
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L12
	ldr	r3, .L1641
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L12
	ldr	r3, .L1641+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L12:
	ldr	r3, .L1641+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L13
	ldr	r3, .L1641+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L13:
	ldr	r3, .L1641+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L15
	ldr	r3, .L1641+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L15:
	ldr	r3, .L1641+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L16
	ldr	r3, .L1641+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L14
.L16:
	ldr	r3, .L1641+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L14:
	ldr	r3, .L1641+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+124
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L19
	mov	r3, #0
	mov	r4, r3
.L19:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L20
	ldr	r3, .L1641+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L20
	ldr	r3, .L1641+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L20:
	ldr	r3, .L1641+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L21
	ldr	r3, .L1641+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L21:
	ldr	r3, .L1641+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L23
	ldr	r3, .L1641+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L23:
	ldr	r3, .L1641+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L24
	ldr	r3, .L1641+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L22
.L24:
	ldr	r3, .L1641+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L22:
	ldr	r3, .L1641+104
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+212
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L27
	mov	r3, #0
	mov	r4, r3
.L27:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+212
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L28
	ldr	r3, .L1641+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L28
	ldr	r3, .L1641+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L28:
	ldr	r3, .L1641+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L29
	ldr	r3, .L1641+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L29:
	ldr	r3, .L1641+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L31
	ldr	r3, .L1641+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L31:
	ldr	r3, .L1641+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L32
	ldr	r3, .L1641+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L30
.L32:
	ldr	r3, .L1641+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L30:
	ldr	r3, .L1641+272
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+280
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+204
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L35
	mov	r3, #0
	mov	r4, r3
.L35:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+272
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+204
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L36
	ldr	r3, .L1641+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L36
	ldr	r3, .L1641+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L36:
	ldr	r3, .L1641+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L37
	ldr	r3, .L1641+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	b	.L1642
.L1643:
	.align	2
.L1641:
	.word	p25_l1
	.word	p25_l0
	.word	p24_l1
	.word	p24_l0
	.word	p23_l1
	.word	p23_l0
	.word	p24_saved_max
	.word	p4_l1
	.word	p9_l0
	.word	p0_l1
	.word	p11_saved_max
	.word	p16_x
	.word	p24_x
	.word	p4_l0
	.word	p0_l0
	.word	p6_saved_max
	.word	p11_x
	.word	p4_saved_max
	.word	turn0
	.word	p9_x
	.word	p23_saved_max
	.word	p3_l1
	.word	proposed4
	.word	p8_l0
	.word	p0_saved_max
	.word	p4_x
	.word	p23_x
	.word	p3_l0
	.word	proposed3
	.word	p0_x
	.word	proposed25
	.word	proposed24
	.word	turn4
	.word	delta
	.word	id4
	.word	proposed2
	.word	turn3
	.word	id3
	.word	proposed1
	.word	turn2
	.word	id2
	.word	proposed0
	.word	p3_saved_max
	.word	p8_x
	.word	p7_l0
	.word	turn1
	.word	p9_saved_max
	.word	id1
	.word	inc_max_prop
	.word	p3_x
	.word	id0
	.word	proposed22
	.word	p2_x
	.word	proposed23
	.word	p2_saved_max
	.word	p7_x
	.word	p6_l0
	.word	proposed5
	.word	p8_l1
	.word	p22_l0
	.word	proposed6
	.word	p22_l1
	.word	proposed7
	.word	p1_x
	.word	p1_saved_max
	.word	p6_x
	.word	p8_saved_max
	.word	_diverge_delta
	.word	p22_x
	.word	p2_l0
	.word	p22_saved_max
	.word	p2_l1
	.word	p5_x
	.word	p5_saved_max
	.word	p10_x
	.word	p25_x
	.word	p5_l0
	.word	p25_saved_max
	.word	p5_l1
	.word	p6_l1
	.word	p7_saved_max
	.word	p7_l1
	.word	proposed10
	.word	p9_l1
	.word	p10_saved_max
	.word	proposed8
	.word	p1_l0
	.word	proposed9
	.word	p1_l1
	.word	p21_saved_max
	.word	p21_x
	.word	proposed21
	.word	p21_l1
	.word	p21_l0
	.word	p20_saved_max
	.word	p20_x
	.word	proposed20
	.word	p20_l1
	.word	p20_l0
	.word	p19_saved_max
	.word	p19_x
	.word	proposed19
	.word	p19_l1
	.word	p19_l0
	.word	p18_saved_max
	.word	p18_x
	.word	proposed18
	.word	p18_l1
	.word	p18_l0
	.word	p17_saved_max
	.word	p17_x
	.word	proposed17
	.word	p17_l1
	.word	p17_l0
	.word	p16_saved_max
	.word	p16_x
	.word	proposed16
	.word	p16_l1
	.word	p16_l0
	.word	p15_saved_max
	.word	p15_x
	.word	proposed15
	.word	p15_l1
	.word	p15_l0
	.word	p14_saved_max
	.word	p14_x
	.word	proposed14
	.word	p14_l1
	.word	p14_l0
	.word	p13_saved_max
	.word	p13_x
	.word	proposed13
	.word	p13_l1
	.word	p13_l0
	.word	p12_saved_max
	.word	p12_x
	.word	proposed12
	.word	p12_l1
	.word	p12_l0
	.word	max_prop
	.word	p11_saved_max
	.word	p11_x
	.word	proposed11
	.word	p11_l1
	.word	p11_l0
	.word	p10_l0
	.word	p10_l1
.L1642:
	beq	.L38
.L37:
	ldr	r3, .L1641+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L39
	ldr	r3, .L1641+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L39:
	ldr	r3, .L1641+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L40
	ldr	r3, .L1641+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L38
.L40:
	ldr	r3, .L1641+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L38:
	ldr	r3, .L1641+360
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+356
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+364
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L43
	mov	r3, #0
	mov	r4, r3
.L43:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+360
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+364
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L44
	ldr	r3, .L1641+368
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L44
	ldr	r3, .L1641+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L44:
	ldr	r3, .L1641+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L45
	ldr	r3, .L1641+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
.L45:
	ldr	r3, .L1641+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L47
	ldr	r3, .L1641+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
.L47:
	ldr	r3, .L1641+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L48
	ldr	r3, .L1641+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L46
.L48:
	ldr	r3, .L1641+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L46:
	ldr	r3, .L1641+380
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+376
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+384
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L51
	mov	r3, #0
	mov	r4, r3
.L51:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+380
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+384
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L52
	ldr	r3, .L1641+388
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L52
	ldr	r3, .L1641+392
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L52:
	ldr	r3, .L1641+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L53
	ldr	r3, .L1641+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L53:
	ldr	r3, .L1641+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L55
	ldr	r3, .L1641+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L55:
	ldr	r3, .L1641+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L56
	ldr	r3, .L1641+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L54
.L56:
	ldr	r3, .L1641+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L54:
	ldr	r3, .L1641+400
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+396
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+404
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L59
	mov	r3, #0
	mov	r4, r3
.L59:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+400
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+404
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L60
	ldr	r3, .L1641+408
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L60
	ldr	r3, .L1641+412
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L60:
	ldr	r3, .L1641+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L61
	ldr	r3, .L1641+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
.L61:
	ldr	r3, .L1641+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L63
	ldr	r3, .L1641+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
.L63:
	ldr	r3, .L1641+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L64
	ldr	r3, .L1641+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L62
.L64:
	ldr	r3, .L1641+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L62:
	ldr	r3, .L1641+420
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+416
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+424
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L67
	mov	r3, #0
	mov	r4, r3
.L67:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+420
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+424
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L68
	ldr	r3, .L1641+428
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L68
	ldr	r3, .L1641+432
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L68:
	ldr	r3, .L1641+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L69
	ldr	r3, .L1641+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L69:
	ldr	r3, .L1641+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L71
	ldr	r3, .L1641+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L71:
	ldr	r3, .L1641+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L72
	ldr	r3, .L1641+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L70
.L72:
	ldr	r3, .L1641+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L70:
	ldr	r3, .L1641+440
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+436
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+444
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L75
	mov	r3, #0
	mov	r4, r3
.L75:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+440
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+444
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L76
	ldr	r3, .L1641+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L76
	ldr	r3, .L1641+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L76:
	ldr	r3, .L1641+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L77
	ldr	r3, .L1641+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L77:
	ldr	r3, .L1641+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L79
	ldr	r3, .L1641+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L79:
	ldr	r3, .L1641+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L80
	ldr	r3, .L1641+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L78
.L80:
	ldr	r3, .L1641+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L78:
	ldr	r3, .L1641+460
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+456
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+464
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L83
	mov	r3, #0
	mov	r4, r3
.L83:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+460
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+464
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L84
	ldr	r3, .L1641+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L84
	ldr	r3, .L1641+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L84:
	ldr	r3, .L1641+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L85
	ldr	r3, .L1641+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L85:
	ldr	r3, .L1641+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L87
	ldr	r3, .L1641+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L87:
	ldr	r3, .L1641+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L88
	ldr	r3, .L1641+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L86
.L88:
	ldr	r3, .L1641+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L86:
	ldr	r3, .L1641+480
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+476
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+484
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L91
	mov	r3, #0
	mov	r4, r3
.L91:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+480
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+484
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L92
	ldr	r3, .L1641+488
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L92
	ldr	r3, .L1641+492
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L92:
	ldr	r3, .L1641+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L93
	ldr	r3, .L1641+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
.L93:
	ldr	r3, .L1641+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L95
	ldr	r3, .L1641+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
.L95:
	ldr	r3, .L1641+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L96
	ldr	r3, .L1641+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L94
.L96:
	ldr	r3, .L1641+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L94:
	ldr	r3, .L1641+500
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+496
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+504
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L99
	mov	r3, #0
	mov	r4, r3
.L99:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+500
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+504
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L100
	ldr	r3, .L1641+508
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L100
	ldr	r3, .L1641+512
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L100:
	ldr	r3, .L1641+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L101
	ldr	r3, .L1641+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L101:
	ldr	r3, .L1641+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L103
	ldr	r3, .L1641+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L103:
	ldr	r3, .L1641+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L104
	ldr	r3, .L1641+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L102
.L104:
	ldr	r3, .L1641+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L102:
	ldr	r3, .L1641+520
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+516
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+524
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L107
	mov	r3, #0
	mov	r4, r3
.L107:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+520
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+524
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L108
	ldr	r3, .L1641+528
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L108
	ldr	r3, .L1641+532
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L108:
	ldr	r3, .L1641+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L109
	ldr	r3, .L1641+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L109:
	ldr	r3, .L1641+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L111
	ldr	r3, .L1641+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L111:
	ldr	r3, .L1641+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L112
	ldr	r3, .L1641+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L110
.L112:
	ldr	r3, .L1641+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L110:
	ldr	r3, .L1641+540
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+536
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+544
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L115
	mov	r3, #0
	mov	r4, r3
.L115:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+540
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+544
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L116
	ldr	r3, .L1641+548
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L116
	ldr	r3, .L1641+552
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L116:
	ldr	r3, .L1641+576
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+572
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+576
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L117
	ldr	r3, .L1641+572
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L117:
	ldr	r3, .L1641+576
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L119
	ldr	r3, .L1641+572
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L119:
	ldr	r3, .L1641+572
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L120
	ldr	r3, .L1641+576
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L118
.L120:
	ldr	r3, .L1641+576
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+572
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L118:
	ldr	r3, .L1641+564
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+556
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+560
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+568
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L123
	mov	r3, #0
	mov	r4, r3
.L123:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1641+564
	ldr	r3, [r3]	@ float
	ldr	r2, .L1641+568
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L124
	ldr	r3, .L1641+572
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L124
	ldr	r3, .L1641+576
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L124:
	ldr	r3, .L1641+580
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+584
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1641+580
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L125
	ldr	r3, .L1641+584
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
.L125:
	ldr	r3, .L1644
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L127
	ldr	r3, .L1644+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
.L127:
	ldr	r3, .L1644+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L128
	ldr	r3, .L1644
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L126
.L128:
	ldr	r3, .L1644
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L126:
	ldr	r3, .L1644+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+20
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L131
	mov	r3, #0
	mov	r4, r3
.L131:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L132
	ldr	r3, .L1644+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L132
	ldr	r3, .L1644
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L132:
	ldr	r3, .L1644+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L133
	ldr	r3, .L1644+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L133:
	ldr	r3, .L1644+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L135
	ldr	r3, .L1644+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L135:
	ldr	r3, .L1644+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L136
	ldr	r3, .L1644+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L134
.L136:
	ldr	r3, .L1644+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L134:
	ldr	r3, .L1644+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+40
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L139
	mov	r3, #0
	mov	r4, r3
.L139:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L140
	ldr	r3, .L1644+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L140
	ldr	r3, .L1644+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L140:
	ldr	r3, .L1644+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L141
	ldr	r3, .L1644+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L141:
	ldr	r3, .L1644+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L143
	ldr	r3, .L1644+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L143:
	ldr	r3, .L1644+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L144
	ldr	r3, .L1644+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L142
.L144:
	ldr	r3, .L1644+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L142:
	ldr	r3, .L1644+52
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+60
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L147
	mov	r3, #0
	mov	r4, r3
.L147:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L148
	ldr	r3, .L1644+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L148
	ldr	r3, .L1644+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L148:
	ldr	r3, .L1644+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L149
	ldr	r3, .L1644+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L149:
	ldr	r3, .L1644+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L151
	ldr	r3, .L1644+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L151:
	ldr	r3, .L1644+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L152
	ldr	r3, .L1644+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L150
.L152:
	ldr	r3, .L1644+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L150:
	ldr	r3, .L1644+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+80
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L155
	mov	r3, #0
	mov	r4, r3
.L155:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L156
	ldr	r3, .L1644+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L156
	ldr	r3, .L1644+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L156:
	ldr	r3, .L1644+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L157
	ldr	r3, .L1644+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L157:
	ldr	r3, .L1644+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L159
	ldr	r3, .L1644+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L159:
	ldr	r3, .L1644+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L160
	ldr	r3, .L1644+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L158
.L160:
	ldr	r3, .L1644+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L158:
	ldr	r3, .L1644+92
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+96
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+100
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L163
	mov	r3, #0
	mov	r4, r3
.L163:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L164
	ldr	r3, .L1644+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L164
	ldr	r3, .L1644+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L164:
	ldr	r3, .L1644+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L165
	ldr	r3, .L1644+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L165:
	ldr	r3, .L1644+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L167
	ldr	r3, .L1644+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L167:
	ldr	r3, .L1644+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L168
	ldr	r3, .L1644+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L166
.L168:
	ldr	r3, .L1644+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L166:
	ldr	r3, .L1644+112
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+120
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L171
	mov	r3, #0
	mov	r4, r3
.L171:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+120
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L172
	ldr	r3, .L1644+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L172
	ldr	r3, .L1644+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L172:
	ldr	r3, .L1644+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L173
	ldr	r3, .L1644+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L173:
	ldr	r3, .L1644+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L175
	ldr	r3, .L1644+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L175:
	ldr	r3, .L1644+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L176
	ldr	r3, .L1644+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L174
.L176:
	ldr	r3, .L1644+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L174:
	ldr	r3, .L1644+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+140
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L179
	mov	r3, #0
	mov	r4, r3
.L179:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L180
	ldr	r3, .L1644+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L180
	ldr	r3, .L1644+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L180:
	ldr	r3, .L1644+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L181
	ldr	r3, .L1644+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
.L181:
	ldr	r3, .L1644+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L183
	ldr	r3, .L1644+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
.L183:
	ldr	r3, .L1644+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L184
	ldr	r3, .L1644+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L182
.L184:
	ldr	r3, .L1644+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L182:
	ldr	r3, .L1644+152
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+160
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L187
	mov	r3, #0
	mov	r4, r3
.L187:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L188
	ldr	r3, .L1644+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L188
	ldr	r3, .L1644+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L188:
	ldr	r3, .L1644+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L189
	ldr	r3, .L1644+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
.L189:
	ldr	r3, .L1644+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L191
	ldr	r3, .L1644+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
.L191:
	ldr	r3, .L1644+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L192
	ldr	r3, .L1644+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L190
.L192:
	ldr	r3, .L1644+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L190:
	ldr	r3, .L1644+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+180
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L195
	mov	r3, #0
	mov	r4, r3
.L195:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+180
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L196
	ldr	r3, .L1644+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L196
	ldr	r3, .L1644+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L196:
	ldr	r3, .L1644+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L197
	ldr	r3, .L1644+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
.L197:
	ldr	r3, .L1644+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L199
	ldr	r3, .L1644+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
.L199:
	ldr	r3, .L1644+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L200
	ldr	r3, .L1644+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L198
.L200:
	ldr	r3, .L1644+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L198:
	ldr	r3, .L1644+192
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+196
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+200
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L203
	mov	r3, #0
	mov	r4, r3
.L203:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+200
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L204
	ldr	r3, .L1644+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L204
	ldr	r3, .L1644+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L204:
	ldr	r3, .L1644+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L205
	ldr	r3, .L1644+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
.L205:
	ldr	r3, .L1644+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L207
	ldr	r3, .L1644+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
.L207:
	ldr	r3, .L1644+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L208
	ldr	r3, .L1644+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L206
.L208:
	ldr	r3, .L1644+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L206:
	ldr	r3, .L1644+212
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+220
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L211
	mov	r3, #0
	mov	r4, r3
.L211:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1644+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L212
	ldr	r3, .L1644+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L212
	ldr	r3, .L1644+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
.L212:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L213
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L213
	b	.L1645
.L1646:
	.align	2
.L1644:
	.word	p10_l0
	.word	p10_l1
	.word	p10_x
	.word	max_prop
	.word	p10_saved_max
	.word	proposed10
	.word	p9_l0
	.word	p9_l1
	.word	p9_x
	.word	p9_saved_max
	.word	proposed9
	.word	p8_l0
	.word	p8_l1
	.word	p8_x
	.word	p8_saved_max
	.word	proposed8
	.word	p7_l0
	.word	p7_l1
	.word	p7_x
	.word	p7_saved_max
	.word	proposed7
	.word	p6_l0
	.word	p6_l1
	.word	p6_x
	.word	p6_saved_max
	.word	proposed6
	.word	p5_l0
	.word	p5_l1
	.word	p5_x
	.word	p5_saved_max
	.word	proposed5
	.word	p4_l0
	.word	p4_l1
	.word	p4_x
	.word	p4_saved_max
	.word	proposed4
	.word	p3_l0
	.word	p3_l1
	.word	p3_x
	.word	p3_saved_max
	.word	proposed3
	.word	p2_l0
	.word	p2_l1
	.word	p2_x
	.word	p2_saved_max
	.word	proposed2
	.word	p1_l0
	.word	p1_l1
	.word	p1_x
	.word	p1_saved_max
	.word	proposed1
	.word	p0_l0
	.word	p0_l1
	.word	p0_x
	.word	p0_saved_max
	.word	proposed0
	.word	id4
	.word	id3
	.word	id2
	.word	id0
	.word	id1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
.L1645:
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L213:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L215
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L215
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L215:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L216
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L216
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L216:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L217
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L217
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
.L217:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L218
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L218
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L218:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L219
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L219
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L219:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L220
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L220
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L220:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L221
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L221
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
.L221:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L222
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L222
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L222:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L223
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L223
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L223
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L223:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L224
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L224
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L224:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L225
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L225
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L225
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L225
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
.L225:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L226
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L226
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L226:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L227
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L227
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L227
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L227
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L227:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L228
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L228
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L228
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L228:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L229
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L229
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
.L229:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L230
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L230
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L230:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L231
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L231
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L231
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L231:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L232
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L232
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L232:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L233
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L233
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L233
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
.L233:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L234
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L234
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L234
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L234:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L235
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L235
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L235:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L236
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L236
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L236:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L237
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L237
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L214
.L237:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L238
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L238
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L238:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L239
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L214
.L239:
	ldr	r3, .L1644+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1644+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1644+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L214:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L240
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L240
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L240:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L242
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L242
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L242
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L242:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L243
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L243
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L243:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L244
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L244
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L244:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L245
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L245
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L245:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L246
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L246
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L246
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L246:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L247
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L247
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L247:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L248
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L248
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L248
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L248
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L248:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L249
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L249
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L249
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L249:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L250
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L250
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L250:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L251
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L251
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L251:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L252
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L252
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L252:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L253
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L253
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L253:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L254
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L254
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L254:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L255
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L255
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L255
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L255:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L256
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L256
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L256:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L257
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L257
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L257
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L257:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L258
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L258
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L258:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L259
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L259
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L259
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L259:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L260
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L260
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L260:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L261
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L261
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L261
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L261
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L261:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L262
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L262
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L262:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L263
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L263
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L241
.L263:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L264
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L264
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L264:
	ldr	r3, .L1644+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L1644+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L1644+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L1644+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L265
	ldr	r3, .L1644+260
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L241
.L265:
	ldr	r3, .L1647+684
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1647+688
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1647+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1647+696
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+700
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
.L241:
	ldr	r3, .L1647+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1647+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1647+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1647+652
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1647+656
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L4
	ldr	r3, .L1647
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+704
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+748
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	ldr	r3, .L1647+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+16
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L293
	ldr	r3, .L1647+748
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+708
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
.L293:
	ldr	r3, .L1647+704
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+104
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L4
	mov	r3, #1
	b	.L296
.L4:
	mov	r3, #0
.L296:
	str	r3, [fp, #-24]
	b	.L297
.L1648:
	.align	2
.L1647:
	.word	inc_max_prop
	.word	proposed0
	.word	proposed1
	.word	proposed2
	.word	proposed3
	.word	proposed4
	.word	proposed5
	.word	proposed6
	.word	proposed7
	.word	proposed8
	.word	proposed9
	.word	proposed10
	.word	proposed11
	.word	proposed12
	.word	proposed13
	.word	proposed14
	.word	proposed15
	.word	proposed16
	.word	proposed17
	.word	proposed18
	.word	proposed19
	.word	proposed20
	.word	proposed21
	.word	proposed22
	.word	proposed23
	.word	proposed24
	.word	_diverge_delta
	.word	_x_p24_l1
	.word	_x_p24_l0
	.word	_x_p23_l1
	.word	_x_p23_l0
	.word	_x_p24_saved_max
	.word	_x_p4_l1
	.word	_x_p9_l0
	.word	_x_p0_l1
	.word	_x_p11_saved_max
	.word	_x_p16_x
	.word	_x_p24_x
	.word	_x_p4_l0
	.word	_x_p0_l0
	.word	_x_p6_saved_max
	.word	_x_p11_x
	.word	_x_p4_saved_max
	.word	_x_turn0
	.word	_x_p9_x
	.word	_x_p23_saved_max
	.word	_x_p3_l1
	.word	_x_proposed4
	.word	_x_p8_l0
	.word	_x_p0_saved_max
	.word	_x_p4_x
	.word	_x_p23_x
	.word	_x_p3_l0
	.word	_x_proposed3
	.word	_x_p0_x
	.word	_x_proposed24
	.word	_x_turn4
	.word	_x_delta
	.word	_x_proposed2
	.word	_x_turn3
	.word	_x_p19_saved_max
	.word	_x_max_prop
	.word	_x_proposed1
	.word	_x_turn2
	.word	_x_p14_saved_max
	.word	_x_p19_x
	.word	_x_proposed0
	.word	_x_p3_saved_max
	.word	_x_p8_x
	.word	_x_proposed12
	.word	_x_p7_l0
	.word	_x_turn1
	.word	_x_p9_saved_max
	.word	_x_p14_x
	.word	_x_inc_max_prop
	.word	_x_p3_x
	.word	_x_proposed22
	.word	_x_p2_x
	.word	_x_proposed23
	.word	_x_p2_saved_max
	.word	_x_proposed20
	.word	_x_p7_x
	.word	_x_p6_l0
	.word	_x_proposed5
	.word	_x_p8_l1
	.word	_x_p13_l0
	.word	_x_p22_l0
	.word	_x_proposed6
	.word	_x_p13_l1
	.word	_x_p18_l0
	.word	_x_p22_l1
	.word	_x_proposed7
	.word	_x_p18_l1
	.word	_x_p1_x
	.word	_x_p1_saved_max
	.word	_x_p6_x
	.word	_x_p8_saved_max
	.word	_x_p13_x
	.word	_x__diverge_delta
	.word	_x_p22_x
	.word	_x_p2_l0
	.word	_x_proposed14
	.word	_x_p13_saved_max
	.word	_x_p18_x
	.word	_x_p22_saved_max
	.word	_x_p2_l1
	.word	_x_proposed15
	.word	_x_p18_saved_max
	.word	_x_p5_x
	.word	_x_p5_saved_max
	.word	_x_p10_x
	.word	_x_p5_l0
	.word	_x_p5_l1
	.word	_x_p10_l0
	.word	_x_p6_l1
	.word	_x_p11_l0
	.word	_x_proposed21
	.word	_x_p7_saved_max
	.word	_x_proposed18
	.word	_x_p12_x
	.word	_x_proposed13
	.word	_x_p7_l1
	.word	_x_proposed10
	.word	_x_p12_l0
	.word	_x_p9_l1
	.word	_x_p14_l0
	.word	_x_p10_saved_max
	.word	_x_p15_x
	.word	_x_p10_l1
	.word	_x_p15_l0
	.word	_x_p11_l1
	.word	_x_p16_l0
	.word	_x_proposed19
	.word	_x_p12_saved_max
	.word	_x_proposed16
	.word	_x_p17_x
	.word	_x_proposed11
	.word	_x_p12_l1
	.word	_x_proposed8
	.word	_x_p17_l0
	.word	_x_p14_l1
	.word	_x_p19_l0
	.word	_x_p15_saved_max
	.word	_x_p20_x
	.word	_x_p15_l1
	.word	_x_p20_l0
	.word	_x_p16_saved_max
	.word	_x_p1_l0
	.word	_x_p21_x
	.word	_x_p16_l1
	.word	_x_p21_l0
	.word	_x_proposed17
	.word	_x_p17_saved_max
	.word	_x_proposed9
	.word	_x_p17_l1
	.word	_x_p19_l1
	.word	_x_p20_saved_max
	.word	_x_p20_l1
	.word	_x_p1_l1
	.word	_x_p21_saved_max
	.word	_x_p21_l1
	.word	p25_x
	.word	p25_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	_x_proposed25
	.word	p25_l0
	.word	p25_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	delta
	.word	max_prop
	.word	_x_p25_saved_max
	.word	_x_p25_l0
	.word	_x_p25_l1
	.word	_x_p25_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id0
	.word	_x_id1
	.word	proposed25
.L1246:
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+720
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+716
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+108
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+112
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+116
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+120
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+124
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+128
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+132
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+136
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+140
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+144
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+148
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+152
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+156
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+160
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+164
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+168
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+172
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+176
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+180
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+184
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+188
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+192
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+196
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+200
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+204
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+208
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+212
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+216
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+672
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+220
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+224
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+228
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+728
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+232
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+236
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+240
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+244
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+732
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+248
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+252
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+256
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+260
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+736
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+264
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+268
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+272
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+276
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+280
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+284
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+288
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+292
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+744
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+296
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+300
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+740
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+304
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+308
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+312
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+316
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+320
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+324
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+328
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+332
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+336
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+340
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+344
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+348
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+352
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+356
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+360
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+364
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+368
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+372
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+376
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+380
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+384
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+388
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+392
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+396
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+400
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+404
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+408
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+412
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+416
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+420
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+424
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+428
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+432
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+436
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+440
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+724
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+444
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+712
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+448
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+452
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+456
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+460
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+464
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+468
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+472
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+476
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+480
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+484
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+488
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+492
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+496
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+500
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+504
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+508
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+512
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+516
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+520
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+524
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+528
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+532
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+536
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+540
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+544
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+548
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+552
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+556
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+560
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+564
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+568
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+572
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+576
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+580
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+584
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+588
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+592
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+596
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+600
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+604
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+608
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+612
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+616
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+620
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+624
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+628
	strb	r2, [r3]
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+632
	strb	r2, [r3]
	bl	__VERIFIER_nondet_float
	mov	r3, r0
	ldr	r2, .L1647+636
	str	r3, [r2]	@ float
	bl	__VERIFIER_nondet_bool
	mov	r3, r0
	mov	r2, r3
	ldr	r3, .L1647+640
	strb	r2, [r3]
	ldr	r3, .L1647+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L298
	ldr	r3, .L1647+720
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
.L298:
	ldr	r3, .L1647+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L300
	ldr	r3, .L1647+720
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
.L300:
	ldr	r3, .L1647+720
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L301
	ldr	r3, .L1647+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L299
.L301:
	ldr	r3, .L1647+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1647+720
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L299:
	ldr	r3, .L1647+672
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L303
	mov	r3, #0
	mov	r4, r3
.L303:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1647+724
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+672
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L304
	ldr	r3, .L1647+720
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L304
	ldr	r3, .L1647+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L304:
	ldr	r3, .L1647+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1647+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L1647+680
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1647+720
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L1647+704
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1647+644
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1647+724
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L1647+648
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+712
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L305
	ldr	r3, .L1647+748
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+672
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L308
.L305:
	ldr	r3, .L1647+704
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1647+684
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1647+688
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1647+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1647+696
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1647+700
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L308:
	ldr	r3, .L1647+720
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1647+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L310
	ldr	r3, .L1647+724
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1647+652
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1647+740
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1647+656
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1647+744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1647+660
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1647+736
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1647+664
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1647+732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1647+668
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1647+728
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1647+748
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+672
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L310
	ldr	r3, .L1647+708
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+712
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L313
.L310:
	ldr	r3, .L1647+676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L313
	ldr	r3, .L1647+680
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L313
	ldr	r3, .L1647+684
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L1647+688
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L1647+692
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L313
	ldr	r3, .L1647+696
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L313
	ldr	r3, .L1647+700
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L313
	ldr	r3, .L1647+704
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L313:
	ldr	r3, .L1647+708
	ldr	r3, [r3]	@ float
	ldr	r2, .L1647+712
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L1647+716
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L1647+720
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L1647+724
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L1647+728
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L1647+732
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L1647+736
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L1647+740
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L315
	ldr	r3, .L1647+744
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L315
	ldr	r3, .L1647+748
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L318
.L315:
	ldr	r3, .L1649+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L1649+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L318
	ldr	r3, .L1649+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L1649+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L1649+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L318
	ldr	r3, .L1649+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L318
	ldr	r3, .L1649+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L318
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L318:
	ldr	r3, .L1649+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L323
	ldr	r3, .L1649+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L323
	ldr	r3, .L1649+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L324
.L323:
	ldr	r3, .L1649+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L320
	ldr	r3, .L1649+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L324
.L320:
	ldr	r3, .L1649+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L1649+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1649+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L1649+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L1649+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1649+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L324
	ldr	r3, .L1649+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L324
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L324:
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1649+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1649+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1649+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L326
	ldr	r3, .L1649+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L326
	ldr	r3, .L1649+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L329
	mov	r3, #0
	mov	r4, r3
.L329:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L330
.L326:
	ldr	r3, .L1649+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L1649+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L1649+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L1649+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L1649+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L330
	ldr	r3, .L1649+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L330
	ldr	r3, .L1649+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L330
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L330:
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L332
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L333
.L332:
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L334
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L333
.L334:
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L335
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L333
.L335:
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L333:
	ldr	r3, .L1649+76
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L336
	mov	r3, #0
	mov	r4, r3
.L336:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L337
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L337
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L337:
	ldr	r3, .L1649+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L1649+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1649+92
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1649+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L1649+96
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L338
	ldr	r3, .L1649+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L341
.L338:
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1649+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1649+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L341:
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L343
	ldr	r3, .L1649+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L1649+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L1649+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L1649+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L1649+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L1649+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L1649+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L343
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L346
.L343:
	ldr	r3, .L1649+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L1649+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L1649+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L1649+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L346
	ldr	r3, .L1649+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L1649+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L1649+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L346
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L346:
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L1649+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L348
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L1649+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L348
	ldr	r3, .L1649+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L351
.L348:
	ldr	r3, .L1649+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L1649+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L351
	ldr	r3, .L1649+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L1649+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L351
	ldr	r3, .L1649+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L351
	ldr	r3, .L1649+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L351
	ldr	r3, .L1649+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L351
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L351:
	ldr	r3, .L1649+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L356
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L356
	ldr	r3, .L1649+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L357
.L356:
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L353
	ldr	r3, .L1649+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L357
.L353:
	ldr	r3, .L1649+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1649+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1649+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1649+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L357
	ldr	r3, .L1649+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1649+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1649+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L357
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L357:
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+100
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1649+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1649+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1649+92
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L359
	ldr	r3, .L1649+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L359
	ldr	r3, .L1649+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+76
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L362
	mov	r3, #0
	mov	r4, r3
.L362:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L363
.L359:
	ldr	r3, .L1649+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L1649+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L1649+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L1649+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L363
	ldr	r3, .L1649+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L363
	ldr	r3, .L1649+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L363
	ldr	r3, .L1649+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L363
	ldr	r3, .L1649+32
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L363:
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L365
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L1650
.L1651:
	.align	2
.L1649:
	.word	_x_proposed25
	.word	p25_l1
	.word	p25_l0
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	delta
	.word	id0
	.word	_x_id0
	.word	proposed25
	.word	_x_p25_saved_max
	.word	_x_p25_l0
	.word	_x_p25_l1
	.word	_x_p25_x
	.word	p25_x
	.word	_x_p24_l0
	.word	_x_p24_l1
	.word	_x_proposed24
	.word	_x_p24_x
	.word	p24_l0
	.word	p24_l1
	.word	p24_x
	.word	p24_saved_max
	.word	_x_p24_saved_max
	.word	proposed24
	.word	p23_saved_max
	.word	id1
	.word	_x_p23_saved_max
	.word	_x_p23_l0
	.word	_x_p23_l1
	.word	p23_x
	.word	_x_p23_x
	.word	proposed23
	.word	_x_proposed23
	.word	p23_l0
	.word	p23_l1
	.word	p22_x
	.word	p22_saved_max
	.word	delta
	.word	_x_p22_l1
	.word	_x_p22_l0
	.word	_x_p22_x
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
	.word	id2
	.word	_x_id2
	.word	id3
	.word	_x_id3
	.word	id4
	.word	_x_id4
	.word	proposed22
	.word	_x_proposed22
	.word	max_prop
	.word	_x_p22_saved_max
	.word	p22_l0
	.word	p22_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn1
	.word	turn0
.L1650:
	cmp	r3, #0
	beq	.L366
.L365:
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L367
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
.L367:
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L368
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L366
.L368:
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L366:
	ldr	r3, .L1649+140
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L369
	mov	r3, #0
	mov	r4, r3
.L369:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L370
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L370
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L370:
	ldr	r3, .L1649+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1649+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1649+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1649+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1649+132
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1649+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L371
	ldr	r3, .L1649+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L374
.L371:
	ldr	r3, .L1649+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1649+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L374:
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L376
	ldr	r3, .L1649+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1649+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1649+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1649+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1649+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1649+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1649+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L376
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L379
.L376:
	ldr	r3, .L1649+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L1649+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L1649+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L1649+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L379
	ldr	r3, .L1649+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L1649+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L1649+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L379
	ldr	r3, .L1649+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L379:
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L381
	ldr	r3, .L1649+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L381
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1649+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L381
	ldr	r3, .L1649+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L384
.L381:
	ldr	r3, .L1649+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L1649+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L384
	ldr	r3, .L1649+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L1649+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L384
	ldr	r3, .L1649+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L1649+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L1649+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L384
	ldr	r3, .L1649+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L384:
	ldr	r3, .L1649+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L389
	ldr	r3, .L1649+132
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L390
.L389:
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L386
	ldr	r3, .L1649+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L390
.L386:
	ldr	r3, .L1649+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1649+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1649+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1649+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L390
	ldr	r3, .L1649+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1649+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1649+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L390
	ldr	r3, .L1649+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L390:
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1649+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1649+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1649+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L392
	ldr	r3, .L1649+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L392
	ldr	r3, .L1649+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+140
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L395
	mov	r3, #0
	mov	r4, r3
.L395:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L396
.L392:
	ldr	r3, .L1649+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L1649+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L1649+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L1649+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L396
	ldr	r3, .L1649+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L1649+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L1649+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L396
	ldr	r3, .L1649+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L396:
	ldr	r3, .L1649+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L398
	ldr	r3, .L1649+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
.L398:
	ldr	r3, .L1649+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L400
	ldr	r3, .L1649+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
.L400:
	ldr	r3, .L1649+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L401
	ldr	r3, .L1649+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L399
.L401:
	ldr	r3, .L1649+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L399:
	ldr	r3, .L1649+220
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L402
	mov	r3, #0
	mov	r4, r3
.L402:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L403
	ldr	r3, .L1649+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L403
	ldr	r3, .L1649+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L403:
	ldr	r3, .L1649+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L1649+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L1649+160
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1649+152
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1649+172
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L1649+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L404
	ldr	r3, .L1649+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L407
.L404:
	ldr	r3, .L1649+160
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1649+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1649+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L407:
	ldr	r3, .L1649+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1649+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L409
	ldr	r3, .L1649+172
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1649+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1649+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1649+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1649+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1649+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1649+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1649+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L409
	ldr	r3, .L1649+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1649+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L412
.L409:
	ldr	r3, .L1649+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1649+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1649+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L1649+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1649+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L1649+252
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L412
	ldr	r3, .L1649+256
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L412
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L412:
	ldr	r3, .L1652+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1652+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1652+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1652+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1652+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1652+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1652+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1652+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L414
	ldr	r3, .L1652+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L414
	ldr	r3, .L1652+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L417
.L414:
	ldr	r3, .L1652+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L1652+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L417
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L417
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L417
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L417
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L417:
	ldr	r3, .L1652+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L422
	ldr	r3, .L1652+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L422
	ldr	r3, .L1652+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L423
.L422:
	ldr	r3, .L1652+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L419
	ldr	r3, .L1652+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L423
.L419:
	ldr	r3, .L1652+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L1652+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L423
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L423
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L423:
	ldr	r3, .L1652+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1652+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L1652+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L1652+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+20
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1652+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1652+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1652+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L1652+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L425
	ldr	r3, .L1652+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L425
	ldr	r3, .L1652+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+44
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L428
	mov	r3, #0
	mov	r4, r3
.L428:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L429
.L425:
	ldr	r3, .L1652+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L1652+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L429
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L429
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L429
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L429:
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L431
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
.L431:
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L433
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
.L433:
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L434
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L432
.L434:
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L432:
	ldr	r3, .L1652+68
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L435
	mov	r3, #0
	mov	r4, r3
.L435:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L436
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L436
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L436:
	ldr	r3, .L1652+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L1652+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1652+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1652+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L1652+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L437
	ldr	r3, .L1652+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L440
.L437:
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L440:
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L442
	ldr	r3, .L1652+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L1652+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L1652+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L1652+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L1652+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L1652+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L1652+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L442
	ldr	r3, .L1652+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L445
.L442:
	ldr	r3, .L1652+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L445
	ldr	r3, .L1652+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L445
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L445
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L445
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L445
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L445:
	ldr	r3, .L1652+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L447
	ldr	r3, .L1652+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L1652+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L1652+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L447
	ldr	r3, .L1652+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L1652+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L447
	ldr	r3, .L1652+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L447
	ldr	r3, .L1652+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L450
.L447:
	ldr	r3, .L1652+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L450
	ldr	r3, .L1652+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L450
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L450
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L450
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L450
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L450
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L450
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L450:
	ldr	r3, .L1652+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L455
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L455
	ldr	r3, .L1652+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L456
.L455:
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L452
	ldr	r3, .L1652+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L456
.L452:
	ldr	r3, .L1652+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L1652+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L456
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L456
	ldr	r3, .L1652
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L456:
	ldr	r3, .L1652+4
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+84
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1652+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L1652+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L1652+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1652+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1652+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1652+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L1652+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L458
	ldr	r3, .L1652+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L458
	ldr	r3, .L1652+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+68
	ldr	r2, [r2]	@ float
	mov	r1, #1
	b	.L1653
.L1654:
	.align	2
.L1652:
	.word	delta
	.word	max_prop
	.word	_x_p22_saved_max
	.word	_x_p22_l0
	.word	_x_p22_l1
	.word	_x_p22_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id1
	.word	proposed22
	.word	_x_proposed22
	.word	p22_l1
	.word	p22_l0
	.word	p22_x
	.word	_x_p21_l0
	.word	_x_p21_l1
	.word	_x_proposed21
	.word	_x_p21_x
	.word	p21_x
	.word	p21_saved_max
	.word	_x_p21_saved_max
	.word	proposed21
	.word	p21_l0
	.word	p21_l1
	.word	p20_saved_max
	.word	_x_id0
	.word	max_prop
	.word	_x_p20_saved_max
	.word	_x_p20_l0
	.word	_x_p20_l1
	.word	p20_x
	.word	_x_p20_x
	.word	proposed20
	.word	_x_proposed20
	.word	p20_l0
	.word	p20_l1
	.word	p19_l0
	.word	p19_l1
	.word	p19_x
	.word	p19_saved_max
	.word	_x_p19_saved_max
	.word	proposed19
	.word	_x_proposed19
	.word	delta
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	_x_p19_l1
	.word	_x_p19_l0
	.word	_x_p19_x
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
	.word	id2
	.word	_x_id2
	.word	id3
	.word	_x_id3
	.word	id4
	.word	_x_id4
.L1653:
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L461
	mov	r3, #0
	mov	r4, r3
.L461:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L462
.L458:
	ldr	r3, .L1652+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L1652+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L462
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L462
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L462
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L462:
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L464
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L465
.L464:
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L466
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L465
.L466:
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L467
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L465
.L467:
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L465:
	ldr	r3, .L1652+136
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L468
	mov	r3, #0
	mov	r4, r3
.L468:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L469
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L469
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L469:
	ldr	r3, .L1652+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L1652+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1652+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1652+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L1652+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L470
	ldr	r3, .L1652+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L473
.L470:
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L473:
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L475
	ldr	r3, .L1652+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1652+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1652+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1652+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1652+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1652+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1652+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L475
	ldr	r3, .L1652+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L478
.L475:
	ldr	r3, .L1652+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L1652+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L478
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L478
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L478
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L478:
	ldr	r3, .L1652+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1652+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1652+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1652+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1652+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L480
	ldr	r3, .L1652+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1652+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L480
	ldr	r3, .L1652+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L483
.L480:
	ldr	r3, .L1652+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L483
	ldr	r3, .L1652+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L483
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L483
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L483
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L483
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L483
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L483
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L483:
	ldr	r3, .L1652+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+136
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L488
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L488
	ldr	r3, .L1652+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L489
.L488:
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L485
	ldr	r3, .L1652+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L489
.L485:
	ldr	r3, .L1652+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1652+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L489
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L489
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L489:
	ldr	r3, .L1652+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1652+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L1652+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L1652+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1652+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1652+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1652+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L1652+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L491
	ldr	r3, .L1652+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L491
	ldr	r3, .L1652+132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+136
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L494
	mov	r3, #0
	mov	r4, r3
.L494:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L495
.L491:
	ldr	r3, .L1652+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
	ldr	r3, .L1652+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L495
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L495
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L495
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L495
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L495:
	ldr	r3, .L1652+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L497
	ldr	r3, .L1652+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L498
.L497:
	ldr	r3, .L1652+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L499
	ldr	r3, .L1652+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L498
.L499:
	ldr	r3, .L1652+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L500
	ldr	r3, .L1652+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L498
.L500:
	ldr	r3, .L1652+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L498:
	ldr	r3, .L1652+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L501
	mov	r3, #0
	mov	r4, r3
.L501:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+208
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L502
	ldr	r3, .L1652+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L502
	ldr	r3, .L1652+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L502:
	ldr	r3, .L1652+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L1652+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1652+156
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1652+208
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L1652+160
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+164
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L503
	ldr	r3, .L1652+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1652+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L506
.L503:
	ldr	r3, .L1652+176
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1652+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1652+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1652+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L506:
	ldr	r3, .L1652+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L1652+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L508
	ldr	r3, .L1652+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L1652+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L1652+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L1652+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+232
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L1652+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L1652+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1652+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L1655
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L508
	ldr	r3, .L1655+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L511
.L508:
	ldr	r3, .L1655+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L511
	ldr	r3, .L1655+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L511
	ldr	r3, .L1655+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L511
	ldr	r3, .L1655+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L511
	ldr	r3, .L1655+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L511
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L511
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L511
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L511:
	ldr	r3, .L1655+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1655+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1655+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L513
	ldr	r3, .L1655+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L513
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L513
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L513
	ldr	r3, .L1655
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L516
.L513:
	ldr	r3, .L1655+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L1655+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L1655+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L1655+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L1655+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L516
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L516
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L516:
	ldr	r3, .L1655+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L521
	ldr	r3, .L1655+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L521
	ldr	r3, .L1655+44
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L522
.L521:
	ldr	r3, .L1655+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L518
	ldr	r3, .L1655+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L522
.L518:
	ldr	r3, .L1655+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L1655+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1655+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L1655+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1655+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L522
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L522
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L522:
	ldr	r3, .L1655+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1655+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1655+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1655+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L524
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L524
	ldr	r3, .L1655
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+4
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L527
	mov	r3, #0
	mov	r4, r3
.L527:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L528
.L524:
	ldr	r3, .L1655+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L1655+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L1655+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L1655+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L528
	ldr	r3, .L1655+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L528
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L528
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L528:
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L530
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L531
.L530:
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L532
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L531
.L532:
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L533
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L531
.L533:
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L531:
	ldr	r3, .L1655+80
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L534
	mov	r3, #0
	mov	r4, r3
.L534:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L535
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L535
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L535:
	ldr	r3, .L1655+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L1655+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1655+68
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1655+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L1655+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L536
	ldr	r3, .L1655+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L539
.L536:
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1655+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L539:
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L541
	ldr	r3, .L1655+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1655+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1655+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1655+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1655+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1655+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1655+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L541
	ldr	r3, .L1655+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L544
.L541:
	ldr	r3, .L1655+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L544
	ldr	r3, .L1655+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L544
	ldr	r3, .L1655+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L1655+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L544
	ldr	r3, .L1655+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L544
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L544
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L544
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L544:
	ldr	r3, .L1655+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L546
	ldr	r3, .L1655+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L546
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L546
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L546
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L546
	ldr	r3, .L1655+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L549
.L546:
	ldr	r3, .L1655+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L1655+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L1655+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L1655+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L1655+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L549
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L549
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L549:
	ldr	r3, .L1655+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L554
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L554
	ldr	r3, .L1655+72
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L555
.L554:
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L551
	ldr	r3, .L1655+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L555
.L551:
	ldr	r3, .L1655+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L1655+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1655+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L1655+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1655+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L555
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L555
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L555:
	ldr	r3, .L1655+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	b	.L1656
.L1657:
	.align	2
.L1655:
	.word	proposed19
	.word	_x_proposed19
	.word	max_prop
	.word	_x_p19_saved_max
	.word	p19_l0
	.word	p19_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	_x_p19_l0
	.word	_x_p19_l1
	.word	_x_p19_x
	.word	p19_x
	.word	p18_saved_max
	.word	_x_p18_saved_max
	.word	_x_p18_l0
	.word	_x_p18_l1
	.word	p18_x
	.word	_x_p18_x
	.word	proposed18
	.word	_x_proposed18
	.word	p18_l0
	.word	p18_l1
	.word	turn1
	.word	turn0
	.word	delta
	.word	p17_saved_max
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p17_saved_max
	.word	_x_p17_l0
	.word	_x_p17_l1
	.word	p17_x
	.word	_x_p17_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	proposed17
	.word	_x_proposed17
	.word	p17_l0
	.word	p17_l1
	.word	p16_l0
	.word	p16_l1
	.word	p16_x
	.word	p16_saved_max
	.word	_x_p16_saved_max
	.word	proposed16
	.word	_x_proposed16
	.word	delta
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	_x_p16_l1
	.word	_x_p16_l0
	.word	_x_p16_x
	.word	id0
	.word	_x_id0
	.word	id1
	.word	_x_id1
.L1656:
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1655+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1655+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1655+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L557
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L557
	ldr	r3, .L1655+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+80
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L560
	mov	r3, #0
	mov	r4, r3
.L560:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L561
.L557:
	ldr	r3, .L1655+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L1655+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L1655+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L1655+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L561
	ldr	r3, .L1655+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L561
	ldr	r3, .L1655+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L561
	ldr	r3, .L1655+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L561
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L561:
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L563
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
.L563:
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L565
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
.L565:
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L566
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L564
.L566:
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L564:
	ldr	r3, .L1655+160
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L567
	mov	r3, #0
	mov	r4, r3
.L567:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L568
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L568
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L568:
	ldr	r3, .L1655+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L1655+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L1655+100
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1655+136
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1655+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L1655+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L569
	ldr	r3, .L1655+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L572
.L569:
	ldr	r3, .L1655+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1655+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1655+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L572:
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L574
	ldr	r3, .L1655+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L1655+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L1655+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L1655+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L1655+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L1655+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L1655+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L574
	ldr	r3, .L1655+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L577
.L574:
	ldr	r3, .L1655+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L1655+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L1655+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L1655+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L1655+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L1655+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L577
	ldr	r3, .L1655+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L577
	ldr	r3, .L1655+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L577:
	ldr	r3, .L1655+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L1655+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L579
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L579
	ldr	r3, .L1655+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L582
.L579:
	ldr	r3, .L1655+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L1655+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L582
	ldr	r3, .L1655+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L1655+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L582
	ldr	r3, .L1655+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L582
	ldr	r3, .L1655+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L582
	ldr	r3, .L1655+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L582
	ldr	r3, .L1655+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L582:
	ldr	r3, .L1655+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+160
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L587
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L587
	ldr	r3, .L1655+140
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L588
.L587:
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L584
	ldr	r3, .L1655+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L588
.L584:
	ldr	r3, .L1655+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1655+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1655+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1655+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1655+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1655+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L588
	ldr	r3, .L1655+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L588
	ldr	r3, .L1655+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L588:
	ldr	r3, .L1655+120
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+124
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1655+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1655+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1655+136
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+140
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1655+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1655+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1655+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L590
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L590
	ldr	r3, .L1655+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+160
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L593
	mov	r3, #0
	mov	r4, r3
.L593:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L594
.L590:
	ldr	r3, .L1655+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L1655+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L1655+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L1655+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L594
	ldr	r3, .L1655+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L594
	ldr	r3, .L1655+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L594
	ldr	r3, .L1655+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L594
	ldr	r3, .L1655+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L594:
	ldr	r3, .L1655+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L596
	ldr	r3, .L1655+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
.L596:
	ldr	r3, .L1655+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L598
	ldr	r3, .L1655+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
.L598:
	ldr	r3, .L1655+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L599
	ldr	r3, .L1655+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L597
.L599:
	ldr	r3, .L1655+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L597:
	ldr	r3, .L1655+196
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L600
	mov	r3, #0
	mov	r4, r3
.L600:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+196
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L601
	ldr	r3, .L1655+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L601
	ldr	r3, .L1655+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L601:
	ldr	r3, .L1655+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L1655+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L1655+200
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1655+180
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1655+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L1655+184
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+188
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L602
	ldr	r3, .L1655+192
	ldr	r3, [r3]	@ float
	ldr	r2, .L1655+196
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L605
.L602:
	ldr	r3, .L1655+200
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1655+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1655+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1655+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1655+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L605:
	ldr	r3, .L1655+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1655+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L607
	ldr	r3, .L1655+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1655+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1655+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1655+248
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1658
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1658+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1658+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1658+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L607
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L610
.L607:
	ldr	r3, .L1658+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L1658+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L610
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L610
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L610:
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L1658+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L1658+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1658+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L1658+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L612
	ldr	r3, .L1658+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1658+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L612
	ldr	r3, .L1658+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L615
.L612:
	ldr	r3, .L1658+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L1658+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L615
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L615
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L615:
	ldr	r3, .L1658+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L1658+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L620
	ldr	r3, .L1658+48
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L621
.L620:
	ldr	r3, .L1658+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L617
	ldr	r3, .L1658+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L621
.L617:
	ldr	r3, .L1658+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L1658+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L621
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L621
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L621:
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+28
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1658+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L623
	ldr	r3, .L1658+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L623
	ldr	r3, .L1658+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1658+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1658+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1658+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L623
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L623
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L623
	ldr	r3, .L1658+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+24
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L626
	mov	r3, #0
	mov	r4, r3
.L626:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L627
.L623:
	ldr	r3, .L1658+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L627
	ldr	r3, .L1658+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L627
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L627
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L627
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L627
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L627
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L627
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L627:
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L629
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L629:
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L631
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L631:
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L632
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L630
.L632:
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L630:
	ldr	r3, .L1658+88
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L633
	mov	r3, #0
	mov	r4, r3
.L633:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L634
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L634
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L634:
	ldr	r3, .L1658+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L1658+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1658+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1658+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L1658+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L635
	ldr	r3, .L1658+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L638
.L635:
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L638:
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L640
	ldr	r3, .L1658+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1658+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1658+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1658
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1658+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1658+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1658+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L640
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L643
.L640:
	ldr	r3, .L1658+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1658+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L643
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L643
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L643:
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L645
	ldr	r3, .L1658+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1658+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L645
	ldr	r3, .L1658+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1658+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L645
	ldr	r3, .L1658+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L648
.L645:
	ldr	r3, .L1658+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
	ldr	r3, .L1658+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L648
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L648
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L648
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L648:
	ldr	r3, .L1658+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L653
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L653
	ldr	r3, .L1658+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L654
.L653:
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L650
	ldr	r3, .L1658+72
	ldr	r3, [r3]	@ float
	b	.L1659
.L1660:
	.align	2
.L1658:
	.word	id2
	.word	_x_id2
	.word	id3
	.word	_x_id3
	.word	id4
	.word	proposed16
	.word	_x_proposed16
	.word	_x_p16_saved_max
	.word	p16_l0
	.word	p16_l1
	.word	_x_p16_l0
	.word	_x_p16_l1
	.word	_x_p16_x
	.word	p16_x
	.word	p15_saved_max
	.word	_x_p15_saved_max
	.word	_x_p15_l0
	.word	_x_p15_l1
	.word	p15_x
	.word	_x_p15_x
	.word	_x_id4
	.word	proposed15
	.word	_x_proposed15
	.word	p15_l0
	.word	p15_l1
	.word	p14_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p14_saved_max
	.word	_x_p14_l0
	.word	_x_p14_l1
	.word	p14_x
	.word	_x_p14_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id1
	.word	_x_id0
	.word	proposed14
	.word	_x_proposed14
	.word	p14_l0
	.word	p14_l1
	.word	turn1
	.word	turn0
	.word	p13_l0
	.word	_x_p13_l0
	.word	p13_l1
	.word	_x_p13_l1
	.word	p13_x
	.word	_x_p13_x
	.word	p13_saved_max
	.word	_x_p13_saved_max
	.word	proposed13
	.word	_x_proposed13
	.word	delta
	.word	turn4
	.word	turn3
	.word	turn2
.L1659:
	ldr	r2, .L1658+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L654
.L650:
	ldr	r3, .L1658+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L1658+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L654
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L654
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L654:
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1658+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1658+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1658+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1658+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1658+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1658+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L656
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L656
	ldr	r3, .L1658+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+88
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L659
	mov	r3, #0
	mov	r4, r3
.L659:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L660
.L656:
	ldr	r3, .L1658+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1658+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L660
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L660
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L660:
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L662
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L663
.L662:
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L664
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L663
.L664:
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L665
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L663
.L665:
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L663:
	ldr	r3, .L1658+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L666
	mov	r3, #0
	mov	r4, r3
.L666:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L667
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L667
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L667:
	ldr	r3, .L1658+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L668
	ldr	r3, .L1658+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L668
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1658+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1658+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L668
	ldr	r3, .L1658+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L668
	ldr	r3, .L1658+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L671
.L668:
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L671:
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L673
	ldr	r3, .L1658+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L1658+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L1658+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L1658+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L1658+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L1658+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L1658+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L673
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L676
.L673:
	ldr	r3, .L1658+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L676
	ldr	r3, .L1658+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L676
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L676
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L676
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L676
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L676:
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L678
	ldr	r3, .L1658+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1658+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L678
	ldr	r3, .L1658+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1658+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L678
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L678
	ldr	r3, .L1658+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L681
.L678:
	ldr	r3, .L1658+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1658+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L681
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L681
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L681
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L681
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L681:
	ldr	r3, .L1658+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L686
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L686
	ldr	r3, .L1658+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L687
.L686:
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L683
	ldr	r3, .L1658+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L687
.L683:
	ldr	r3, .L1658+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L1658+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L687
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L687
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L687:
	ldr	r3, .L1658+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1658+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1658+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1658+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1658+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1658+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1658+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1658+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L689
	ldr	r3, .L1658+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L689
	ldr	r3, .L1658+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+172
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L692
	mov	r3, #0
	mov	r4, r3
.L692:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L693
.L689:
	ldr	r3, .L1658+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L1658+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L1658+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L693
	ldr	r3, .L1658+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L693
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L693:
	ldr	r3, .L1658+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L695
	ldr	r3, .L1658+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L696
.L695:
	ldr	r3, .L1658+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L697
	ldr	r3, .L1658+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L696
.L697:
	ldr	r3, .L1658+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L698
	ldr	r3, .L1658+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L696
.L698:
	ldr	r3, .L1658+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L696:
	ldr	r3, .L1658+228
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L699
	mov	r3, #0
	mov	r4, r3
.L699:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L700
	ldr	r3, .L1658+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L700
	ldr	r3, .L1658+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L700:
	ldr	r3, .L1658+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L1658+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1658+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1658+208
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1658+212
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L1658+216
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+220
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L701
	ldr	r3, .L1658+224
	ldr	r3, [r3]	@ float
	ldr	r2, .L1658+228
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L704
.L701:
	ldr	r3, .L1658+232
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+236
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1658+240
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1658+244
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L704:
	ldr	r3, .L1661+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L1661+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L706
	ldr	r3, .L1661+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L1661+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L1661+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L1661+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L1661+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L1661+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L1661+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L706
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L709
.L706:
	ldr	r3, .L1661+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L709
	ldr	r3, .L1661+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L709
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L709
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L709
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L709
	ldr	r3, .L1661
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L709
	ldr	r3, .L1661+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L709
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L709:
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1661+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1661+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L711
	ldr	r3, .L1661+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L711
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1661+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L711
	ldr	r3, .L1661+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L711
	ldr	r3, .L1661+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L714
.L711:
	ldr	r3, .L1661+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L714
	ldr	r3, .L1661+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L714
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L714
	ldr	r3, .L1661
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L714
	ldr	r3, .L1661+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L714
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L714:
	ldr	r3, .L1661+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L719
	ldr	r3, .L1661+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L719
	ldr	r3, .L1661+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L720
.L719:
	ldr	r3, .L1661+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L716
	ldr	r3, .L1661+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L720
.L716:
	ldr	r3, .L1661+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1661+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1661
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L720
	ldr	r3, .L1661+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L720
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L720:
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1661+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1661+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1661+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1661+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L722
	ldr	r3, .L1661+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L722
	ldr	r3, .L1661+32
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+36
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L725
	mov	r3, #0
	mov	r4, r3
.L725:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L726
.L722:
	ldr	r3, .L1661+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L1661+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L726
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L1661
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L726
	ldr	r3, .L1661+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L726
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L726:
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L728
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
.L728:
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L730
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
.L730:
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L731
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L729
.L731:
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L729:
	ldr	r3, .L1661+88
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L732
	mov	r3, #0
	mov	r4, r3
.L732:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L733
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L733
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L733:
	ldr	r3, .L1661+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L734
	ldr	r3, .L1661+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L734
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1661+72
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1661+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L734
	ldr	r3, .L1661+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L734
	ldr	r3, .L1661+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L737
.L734:
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1661+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L737:
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L739
	ldr	r3, .L1661+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1661+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1661+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1661+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1661+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1661+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1661+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L739
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L742
.L739:
	ldr	r3, .L1661+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L1661+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L742
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L742
	ldr	r3, .L1661
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L1661+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L742
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L742:
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L744
	ldr	r3, .L1661+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L744
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L744
	ldr	r3, .L1661+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L744
	ldr	r3, .L1661+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L744
	ldr	r3, .L1661+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L747
.L744:
	ldr	r3, .L1661+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L747
	ldr	r3, .L1661+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L747
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L747
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L747
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L747
	ldr	r3, .L1661
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L747
	ldr	r3, .L1661+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L747
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L747:
	ldr	r3, .L1661+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	b	.L1662
.L1663:
	.align	2
.L1661:
	.word	turn0
	.word	turn1
	.word	_x_p13_l1
	.word	_x_p13_l0
	.word	_x_p13_x
	.word	id0
	.word	_x_id0
	.word	id1
	.word	proposed13
	.word	_x_proposed13
	.word	_x_p13_saved_max
	.word	p13_l0
	.word	p13_l1
	.word	p13_x
	.word	p12_saved_max
	.word	_x_p12_saved_max
	.word	_x_p12_l0
	.word	_x_p12_l1
	.word	p12_x
	.word	_x_p12_x
	.word	_x_id1
	.word	proposed12
	.word	_x_proposed12
	.word	p12_l0
	.word	p12_l1
	.word	p11_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p11_saved_max
	.word	_x_p11_l0
	.word	_x_p11_l1
	.word	p11_x
	.word	_x_p11_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id1
	.word	_x_id0
	.word	proposed11
	.word	_x_proposed11
	.word	p11_l0
	.word	p11_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	_x_proposed10
	.word	p10_l0
	.word	_x_p10_l0
	.word	p10_l1
	.word	_x_p10_l1
	.word	delta
	.word	p10_x
	.word	_x_p10_x
.L1662:
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L752
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L752
	ldr	r3, .L1661+76
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L753
.L752:
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L749
	ldr	r3, .L1661+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L753
.L749:
	ldr	r3, .L1661+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L753
	ldr	r3, .L1661+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L753
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L753
	ldr	r3, .L1661+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1661+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L753
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L753:
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1661+64
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1661+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1661+72
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+76
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1661+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L755
	ldr	r3, .L1661+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L755
	ldr	r3, .L1661+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+88
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L758
	mov	r3, #0
	mov	r4, r3
.L758:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L759
.L755:
	ldr	r3, .L1661+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L759
	ldr	r3, .L1661+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L759
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L759
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L759
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L759
	ldr	r3, .L1661+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L759
	ldr	r3, .L1661+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L759
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L759:
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L761
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L762
.L761:
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L763
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L762
.L763:
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L764
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L762
.L764:
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L762:
	ldr	r3, .L1661+172
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L765
	mov	r3, #0
	mov	r4, r3
.L765:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L766
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L766
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L766:
	ldr	r3, .L1661+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L767
	ldr	r3, .L1661+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L767
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1661+140
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1661+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L767
	ldr	r3, .L1661+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L767
	ldr	r3, .L1661+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L770
.L767:
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1661+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L770:
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L772
	ldr	r3, .L1661+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1661+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1661+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1661+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1661+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1661+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1661+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L772
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L775
.L772:
	ldr	r3, .L1661+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L775
	ldr	r3, .L1661+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L775
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L775
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L775
	ldr	r3, .L1661+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1661+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L775
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L775:
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L777
	ldr	r3, .L1661+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L777
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L777
	ldr	r3, .L1661+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1661+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L777
	ldr	r3, .L1661+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L780
.L777:
	ldr	r3, .L1661+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L780
	ldr	r3, .L1661+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L780
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L780
	ldr	r3, .L1661+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L780
	ldr	r3, .L1661+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L780
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L780:
	ldr	r3, .L1661+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+172
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L785
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L785
	ldr	r3, .L1661+144
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L786
.L785:
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L782
	ldr	r3, .L1661+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L786
.L782:
	ldr	r3, .L1661+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
	ldr	r3, .L1661+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L786
	ldr	r3, .L1661+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
	ldr	r3, .L1661+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L786
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L786:
	ldr	r3, .L1661+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1661+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1661+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1661+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+144
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1661+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1661+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1661+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1661+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L788
	ldr	r3, .L1661+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L788
	ldr	r3, .L1661+168
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+172
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L791
	mov	r3, #0
	mov	r4, r3
.L791:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L792
.L788:
	ldr	r3, .L1661+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
	ldr	r3, .L1661+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
	ldr	r3, .L1661+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L792
	ldr	r3, .L1661+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
	ldr	r3, .L1661+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L792
	ldr	r3, .L1661+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
	ldr	r3, .L1661+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L792
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L792:
	ldr	r3, .L1661+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L794
	ldr	r3, .L1661+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L795
.L794:
	ldr	r3, .L1661+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L796
	ldr	r3, .L1661+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L795
.L796:
	ldr	r3, .L1661+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L797
	ldr	r3, .L1661+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L795
.L797:
	ldr	r3, .L1661+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L795:
	ldr	r3, .L1661+204
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L798
	mov	r3, #0
	mov	r4, r3
.L798:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1661+232
	ldr	r3, [r3]	@ float
	ldr	r2, .L1661+204
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L799
	ldr	r3, .L1661+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L799
	ldr	r3, .L1661+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L799:
	ldr	r3, .L1661+208
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+212
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L800
	ldr	r3, .L1661+216
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1661+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L800
	ldr	r3, .L1661+224
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1661+228
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1661+232
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L800
	ldr	r3, .L1664
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L800
	ldr	r3, .L1664+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L803
.L800:
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1664+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L803:
	ldr	r3, .L1664+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L1664+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L805
	ldr	r3, .L1664+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L1664+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L1664+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L1664+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L1664+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L1664+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L1664+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L805
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L808
.L805:
	ldr	r3, .L1664+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L808
	ldr	r3, .L1664+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L808
	ldr	r3, .L1664+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L808
	ldr	r3, .L1664+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
	ldr	r3, .L1664+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L808
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L808
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L808
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L808:
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1664+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1664+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
	ldr	r3, .L1664+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L810
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L810
	ldr	r3, .L1664+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L813
.L810:
	ldr	r3, .L1664+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L813
	ldr	r3, .L1664+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L813
	ldr	r3, .L1664+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L813
	ldr	r3, .L1664+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L813
	ldr	r3, .L1664+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L813
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L813
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L813
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L813:
	ldr	r3, .L1664+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+12
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L818
	ldr	r3, .L1664+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L818
	ldr	r3, .L1664+40
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L819
.L818:
	ldr	r3, .L1664+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L815
	ldr	r3, .L1664+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L819
.L815:
	ldr	r3, .L1664+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L1664+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1664+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1664+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L1664+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L819
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L819
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L819:
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1664+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1664+32
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1664+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+40
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L821
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L821
	ldr	r3, .L1664+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+12
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L824
	mov	r3, #0
	mov	r4, r3
.L824:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L825
.L821:
	ldr	r3, .L1664+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
	ldr	r3, .L1664+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
	ldr	r3, .L1664+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L825
	ldr	r3, .L1664+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
	ldr	r3, .L1664+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L825
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L825
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L825
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L825:
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L827
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L828
.L827:
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L829
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L828
.L829:
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L830
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L828
.L830:
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L828:
	ldr	r3, .L1664+88
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L831
	mov	r3, #0
	mov	r4, r3
.L831:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L832
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L832
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L832:
	ldr	r3, .L1664+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L1664+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1664+76
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1664+80
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L1664+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L833
	ldr	r3, .L1664+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L836
.L833:
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1664+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L836:
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L838
	ldr	r3, .L1664+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1664+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1664+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1664+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1664+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1664+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1664+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L838
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L841
.L838:
	ldr	r3, .L1664+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L841
	ldr	r3, .L1664+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L841
	ldr	r3, .L1664+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L841
	ldr	r3, .L1664+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L841
	ldr	r3, .L1664+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L841
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L841
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L841
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L841:
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1664+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L843
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L843
	ldr	r3, .L1664+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L846
.L843:
	ldr	r3, .L1664+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L846
	ldr	r3, .L1664+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L846
	ldr	r3, .L1664+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L846
	ldr	r3, .L1664+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L846
	ldr	r3, .L1664+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L846
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L846
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L846
	ldr	r3, .L1664+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L846:
	ldr	r3, .L1664+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1664+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	b	.L1665
.L1666:
	.align	2
.L1664:
	.word	p10_saved_max
	.word	_x_p10_saved_max
	.word	proposed10
	.word	_x_proposed10
	.word	delta
	.word	turn4
	.word	turn3
	.word	turn2
	.word	_x_p10_l1
	.word	_x_p10_l0
	.word	_x_p10_x
	.word	p10_l0
	.word	p10_l1
	.word	p10_x
	.word	p9_saved_max
	.word	turn1
	.word	_x_p9_saved_max
	.word	_x_p9_l0
	.word	_x_p9_l1
	.word	p9_x
	.word	_x_p9_x
	.word	proposed9
	.word	_x_proposed9
	.word	p9_l0
	.word	p9_l1
	.word	turn0
	.word	p8_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p8_saved_max
	.word	_x_p8_l0
	.word	_x_p8_l1
	.word	p8_x
	.word	_x_p8_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id1
	.word	_x_id0
	.word	proposed8
	.word	_x_proposed8
	.word	p8_l0
	.word	p8_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	delta
	.word	_x_p7_x
	.word	_x_proposed7
	.word	_x_p7_l1
	.word	p7_l0
	.word	_x_p7_l0
.L1665:
	beq	.L848
	ldr	r3, .L1664+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1664+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1664+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1664+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+88
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L851
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L851
	ldr	r3, .L1664+80
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L852
.L851:
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L848
	ldr	r3, .L1664+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L852
.L848:
	ldr	r3, .L1664+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L1664+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1664+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1664+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L1664+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L852
	ldr	r3, .L1664+60
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L852
	ldr	r3, .L1664+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L852:
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1664+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1664+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1664+76
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+80
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L854
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L854
	ldr	r3, .L1664+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+88
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L857
	mov	r3, #0
	mov	r4, r3
.L857:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L858
.L854:
	ldr	r3, .L1664+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L858
	ldr	r3, .L1664+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L858
	ldr	r3, .L1664+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L858
	ldr	r3, .L1664+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L858
	ldr	r3, .L1664+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L858
	ldr	r3, .L1664+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L858
	ldr	r3, .L1664+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L858
	ldr	r3, .L1664+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L858:
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L860
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L861
.L860:
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L862
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L861
.L862:
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L863
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L861
.L863:
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L861:
	ldr	r3, .L1664+176
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L864
	mov	r3, #0
	mov	r4, r3
.L864:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L865
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L865
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L865:
	ldr	r3, .L1664+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L866
	ldr	r3, .L1664+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L866
	ldr	r3, .L1664+208
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1664+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1664+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L866
	ldr	r3, .L1664+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L866
	ldr	r3, .L1664+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L869
.L866:
	ldr	r3, .L1664+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1664+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1664+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1664+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L869:
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L871
	ldr	r3, .L1664+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1664+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1664+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1664+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1664+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1664+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1664+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L871
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L874
.L871:
	ldr	r3, .L1664+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L874
	ldr	r3, .L1664+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L874
	ldr	r3, .L1664+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L874
	ldr	r3, .L1664+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L874
	ldr	r3, .L1664+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L874
	ldr	r3, .L1664+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L874
	ldr	r3, .L1664+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L874
	ldr	r3, .L1664+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L874:
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L876
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L876
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L876
	ldr	r3, .L1664+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L876
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L876
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L876
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L876
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L876
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L876
	ldr	r3, .L1664+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L879
.L876:
	ldr	r3, .L1664+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L879
	ldr	r3, .L1664+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L879
	ldr	r3, .L1664+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L879
	ldr	r3, .L1664+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L879
	ldr	r3, .L1664+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L879
	ldr	r3, .L1664+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L879
	ldr	r3, .L1664+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L879
	ldr	r3, .L1664+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L879:
	ldr	r3, .L1664+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L884
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L884
	ldr	r3, .L1664+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L885
.L884:
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L881
	ldr	r3, .L1664+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L885
.L881:
	ldr	r3, .L1664+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L885
	ldr	r3, .L1664+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1664+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1664+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L885
	ldr	r3, .L1664+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1664+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1664+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L885
	ldr	r3, .L1664+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L885:
	ldr	r3, .L1664+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1664+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1664+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1664+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1664+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1664+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1664+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1664+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L887
	ldr	r3, .L1664+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L887
	ldr	r3, .L1664+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+176
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L890
	mov	r3, #0
	mov	r4, r3
.L890:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L891
.L887:
	ldr	r3, .L1664+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L891
	ldr	r3, .L1664+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L891
	ldr	r3, .L1664+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L891
	ldr	r3, .L1664+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L891
	ldr	r3, .L1664+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L891
	ldr	r3, .L1664+200
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L891
	ldr	r3, .L1664+204
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L891
	ldr	r3, .L1664+208
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L891:
	ldr	r3, .L1664+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L893
	ldr	r3, .L1664+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L894
.L893:
	ldr	r3, .L1664+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L895
	ldr	r3, .L1664+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L894
.L895:
	ldr	r3, .L1664+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L896
	ldr	r3, .L1664+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L894
.L896:
	ldr	r3, .L1664+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L894:
	ldr	r3, .L1664+216
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L897
	mov	r3, #0
	mov	r4, r3
.L897:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1664+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1664+216
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L898
	ldr	r3, .L1664+220
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L898
	ldr	r3, .L1664+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L898:
	ldr	r3, .L1664+224
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1664+228
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L899
	ldr	r3, .L1667
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L899
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1667+12
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1667+16
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L899
	ldr	r3, .L1667+20
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L899
	ldr	r3, .L1667+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L902
.L899:
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L902:
	ldr	r3, .L1667+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L904
	ldr	r3, .L1667+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L904
	ldr	r3, .L1667+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L904
	ldr	r3, .L1667+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L904
	ldr	r3, .L1667+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L904
	ldr	r3, .L1667+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L904
	ldr	r3, .L1667+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L904
	ldr	r3, .L1667+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L904
	ldr	r3, .L1667+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L904
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L907
.L904:
	ldr	r3, .L1667+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L907
	ldr	r3, .L1667
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L907
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L907
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L907
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L907
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L907
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L907
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L907:
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L909
	ldr	r3, .L1667+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L909
	ldr	r3, .L1667+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L909
	ldr	r3, .L1667+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L909
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L909
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L909
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L909
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L909
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L909
	ldr	r3, .L1667+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L912
.L909:
	ldr	r3, .L1667
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L912
	ldr	r3, .L1667+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L912
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L912
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L912
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L912
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L912
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L912
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L912:
	ldr	r3, .L1667+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L917
	ldr	r3, .L1667+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L917
	ldr	r3, .L1667+16
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L918
.L917:
	ldr	r3, .L1667+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L914
	ldr	r3, .L1667+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L918
.L914:
	ldr	r3, .L1667+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L918
	ldr	r3, .L1667
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L918
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L918
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L918
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L918
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L918:
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+24
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L920
	ldr	r3, .L1667+36
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1667+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1667+12
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+16
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L920
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L920
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L920
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L920
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L920
	ldr	r3, .L1667+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+32
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L923
	mov	r3, #0
	mov	r4, r3
.L923:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L924
.L920:
	ldr	r3, .L1667+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L924
	ldr	r3, .L1667
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L924
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L924
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L924
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L924
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L924
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L924
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L924:
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L926
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L927
.L926:
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L928
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L927
.L928:
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L929
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L927
.L929:
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L927:
	ldr	r3, .L1667+72
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L930
	mov	r3, #0
	mov	r4, r3
.L930:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L931
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L931
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L931:
	ldr	r3, .L1667+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L932
	ldr	r3, .L1667+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L932
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1667+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1667+64
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L932
	ldr	r3, .L1667+44
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L932
	ldr	r3, .L1667+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L935
.L932:
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L935:
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L937
	ldr	r3, .L1667+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1667+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1667+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1667+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1667+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1667+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1667+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L937
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L940
.L937:
	ldr	r3, .L1667+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1667+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L940
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L940
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L940
	ldr	r3, .L1667+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L940:
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L942
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L942
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L942
	ldr	r3, .L1667+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L942
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L942
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L942
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L942
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L942
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L942
	ldr	r3, .L1667+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L945
.L942:
	ldr	r3, .L1667+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L945
	ldr	r3, .L1667+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L945
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L945
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	b	.L1668
.L1669:
	.align	2
.L1667:
	.word	p7_l1
	.word	_x_p7_l1
	.word	delta
	.word	p7_x
	.word	_x_p7_x
	.word	p7_saved_max
	.word	_x_p7_saved_max
	.word	proposed7
	.word	_x_proposed7
	.word	_x_p7_l0
	.word	p7_l0
	.word	p6_saved_max
	.word	_x_p6_saved_max
	.word	_x_p6_l0
	.word	_x_p6_l1
	.word	p6_x
	.word	_x_p6_x
	.word	proposed6
	.word	_x_proposed6
	.word	p6_l0
	.word	p6_l1
	.word	p5_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p5_saved_max
	.word	_x_p5_l0
	.word	_x_p5_l1
	.word	p5_x
	.word	_x_p5_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id1
	.word	_x_id0
	.word	proposed5
	.word	_x_proposed5
	.word	p5_l0
	.word	p5_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	delta
	.word	_x_p4_l1
	.word	_x_p4_l0
.L1668:
	bne	.L945
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L945
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L945
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L945
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L945:
	ldr	r3, .L1667+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+72
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L950
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L950
	ldr	r3, .L1667+64
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L951
.L950:
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L947
	ldr	r3, .L1667+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L951
.L947:
	ldr	r3, .L1667+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L951
	ldr	r3, .L1667+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L951
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L951
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L951
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L951:
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+48
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1667+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1667+56
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1667+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+64
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L953
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L953
	ldr	r3, .L1667+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+72
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L956
	mov	r3, #0
	mov	r4, r3
.L956:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L957
.L953:
	ldr	r3, .L1667+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L957
	ldr	r3, .L1667+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L957
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L957
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L957
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L957
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L957:
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L959
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L959:
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L961
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L961:
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L962
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L960
.L962:
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L960:
	ldr	r3, .L1667+156
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L963
	mov	r3, #0
	mov	r4, r3
.L963:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L964
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L964
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L964:
	ldr	r3, .L1667+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1667+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1667+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1667+128
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1667+84
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L965
	ldr	r3, .L1667+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L968
.L965:
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L968:
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L970
	ldr	r3, .L1667+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1667+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1667+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1667+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1667+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1667+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1667+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L970
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L973
.L970:
	ldr	r3, .L1667+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1667+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L973
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L973
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L973
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L973:
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1667+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L975
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L975
	ldr	r3, .L1667+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L978
.L975:
	ldr	r3, .L1667+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L978
	ldr	r3, .L1667+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L978
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L978
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L978
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L978
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L978
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L978
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L978:
	ldr	r3, .L1667+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+156
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L983
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L983
	ldr	r3, .L1667+128
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L984
.L983:
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L980
	ldr	r3, .L1667+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L984
.L980:
	ldr	r3, .L1667+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L984
	ldr	r3, .L1667+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L984
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L984
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L984
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L984
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L984
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L984
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L984:
	ldr	r3, .L1667+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+112
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L986
	ldr	r3, .L1667+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L986
	ldr	r3, .L1667+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L986
	ldr	r3, .L1667+124
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+128
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L986
	ldr	r3, .L1667+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L986
	ldr	r3, .L1667+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L986
	ldr	r3, .L1667+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L986
	ldr	r3, .L1667+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L986
	ldr	r3, .L1667+148
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L986
	ldr	r3, .L1667+152
	ldr	r3, [r3]	@ float
	ldr	r2, .L1667+156
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L989
	mov	r3, #0
	mov	r4, r3
.L989:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L990
.L986:
	ldr	r3, .L1667+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L990
	ldr	r3, .L1667+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L990
	ldr	r3, .L1667+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L990
	ldr	r3, .L1667+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L990
	ldr	r3, .L1667+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L990
	ldr	r3, .L1667+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L990
	ldr	r3, .L1667+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L990
	ldr	r3, .L1667+188
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L990:
	ldr	r3, .L1667+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L992
	ldr	r3, .L1667+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L993
.L992:
	ldr	r3, .L1667+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L994
	ldr	r3, .L1667+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L993
.L994:
	ldr	r3, .L1667+192
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L995
	ldr	r3, .L1667+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L993
.L995:
	ldr	r3, .L1667+196
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L993:
	ldr	r3, .L1670+4
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L996
	mov	r3, #0
	mov	r4, r3
.L996:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+8
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L997
	ldr	r3, .L1670
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L997
	ldr	r3, .L1670+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L997:
	ldr	r3, .L1670+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L998
	ldr	r3, .L1670+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L998
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1670+24
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1670+8
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L998
	ldr	r3, .L1670+28
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L998
	ldr	r3, .L1670+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1001
.L998:
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L1001:
	ldr	r3, .L1670
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1003
	ldr	r3, .L1670+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1003
	ldr	r3, .L1670+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1003
	ldr	r3, .L1670+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1003
	ldr	r3, .L1670+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1003
	ldr	r3, .L1670+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1003
	ldr	r3, .L1670+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1003
	ldr	r3, .L1670+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1003
	ldr	r3, .L1670+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1003
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1006
.L1003:
	ldr	r3, .L1670+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1006
	ldr	r3, .L1670+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1006
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1006
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1006
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1006
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1006
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1006
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1006:
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1008
	ldr	r3, .L1670+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1008
	ldr	r3, .L1670
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1008
	ldr	r3, .L1670+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1008
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1008
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1008
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1008
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1008
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1008
	ldr	r3, .L1670+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1011
.L1008:
	ldr	r3, .L1670+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1011
	ldr	r3, .L1670+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1011
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1011
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1011:
	ldr	r3, .L1670+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+4
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1016
	ldr	r3, .L1670
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1016
	ldr	r3, .L1670+8
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1017
.L1016:
	ldr	r3, .L1670+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1013
	ldr	r3, .L1670+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1017
.L1013:
	ldr	r3, .L1670+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1017
	ldr	r3, .L1670+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1017
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1017
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1017
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1017
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1017
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1017
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1017:
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1019
	ldr	r3, .L1670+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1019
	ldr	r3, .L1670
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1019
	ldr	r3, .L1670+24
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+8
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1019
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1019
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1019
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1019
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1019
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1019
	ldr	r3, .L1670+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+4
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1022
	mov	r3, #0
	mov	r4, r3
.L1022:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1023
.L1019:
	ldr	r3, .L1670+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1023
	ldr	r3, .L1670+20
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1023
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1023
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1023
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1023
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1023
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1023
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1023:
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1025
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1026
.L1025:
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1027
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1026
.L1027:
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1028
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1026
.L1028:
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1026:
	ldr	r3, .L1670+68
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1029
	mov	r3, #0
	mov	r4, r3
.L1029:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1030
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1030
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1030:
	ldr	r3, .L1670+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1031
	ldr	r3, .L1670+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1031
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1670+56
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1670+60
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1031
	ldr	r3, .L1670+40
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1031
	ldr	r3, .L1670+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1034
.L1031:
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1034:
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1036
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1036
	ldr	r3, .L1670+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1036
	ldr	r3, .L1670+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1036
	ldr	r3, .L1670+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1036
	ldr	r3, .L1670+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1036
	ldr	r3, .L1670+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1036
	ldr	r3, .L1670+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1036
	ldr	r3, .L1670+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1036
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1039
.L1036:
	ldr	r3, .L1670+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1039
	ldr	r3, .L1670+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1039
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1039
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1039
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1039
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1039
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1039
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1039:
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1041
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1041
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	b	.L1671
.L1672:
	.align	2
.L1670:
	.word	_x_p4_l1
	.word	_x_proposed4
	.word	_x_p4_x
	.word	_x_p4_l0
	.word	p4_l0
	.word	p4_l1
	.word	p4_x
	.word	p4_saved_max
	.word	_x_p4_saved_max
	.word	proposed4
	.word	p3_saved_max
	.word	_x_p3_saved_max
	.word	_x_p3_l0
	.word	_x_p3_l1
	.word	p3_x
	.word	_x_p3_x
	.word	proposed3
	.word	_x_proposed3
	.word	p3_l0
	.word	p3_l1
	.word	p2_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn1
	.word	turn0
	.word	delta
	.word	max_prop
	.word	_x_p2_saved_max
	.word	_x_p2_l0
	.word	_x_p2_l1
	.word	p2_x
	.word	_x_p2_x
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id1
	.word	_x_id0
	.word	proposed2
	.word	_x_proposed2
	.word	p2_l0
	.word	p2_l1
.L1671:
	cmp	r3, #0
	bne	.L1041
	ldr	r3, .L1670+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1041
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1041
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1041
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1041
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1041
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1041
	ldr	r3, .L1670+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1044
.L1041:
	ldr	r3, .L1670+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1044
	ldr	r3, .L1670+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1044
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1044
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1044
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1044
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1044
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1044
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1044:
	ldr	r3, .L1670+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+68
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1049
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1049
	ldr	r3, .L1670+60
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1050
.L1049:
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1046
	ldr	r3, .L1670+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1050
.L1046:
	ldr	r3, .L1670+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1050
	ldr	r3, .L1670+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1050
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1050
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1050
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1050
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1050
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1050
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1050:
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+44
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1052
	ldr	r3, .L1670+48
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1052
	ldr	r3, .L1670+52
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1052
	ldr	r3, .L1670+56
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+60
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1052
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1052
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1052
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1052
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1052
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1052
	ldr	r3, .L1670+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+68
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1055
	mov	r3, #0
	mov	r4, r3
.L1055:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1056
.L1052:
	ldr	r3, .L1670+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1056
	ldr	r3, .L1670+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1056
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1056
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1056
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1056
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1056
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1056
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1056:
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1058
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1059
.L1058:
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1060
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1059
.L1060:
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1061
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1059
.L1061:
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1059:
	ldr	r3, .L1670+176
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1062
	mov	r3, #0
	mov	r4, r3
.L1062:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1063
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1063
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1063:
	ldr	r3, .L1670+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1064
	ldr	r3, .L1670+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1064
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1670+144
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1670+148
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1064
	ldr	r3, .L1670+80
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1064
	ldr	r3, .L1670+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1067
.L1064:
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L1067:
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1069
	ldr	r3, .L1670+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1670+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1670+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1670+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1670+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1670+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1670+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1069
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1072
.L1069:
	ldr	r3, .L1670+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1072
	ldr	r3, .L1670+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1072
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1072
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1072
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1072
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1072
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1072
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1072:
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1074
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1074
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1074
	ldr	r3, .L1670+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1074
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1074
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1074
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1074
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1074
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1074
	ldr	r3, .L1670+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1077
.L1074:
	ldr	r3, .L1670+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1077
	ldr	r3, .L1670+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1077
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1077
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1077
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1077
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1077
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1077
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1077:
	ldr	r3, .L1670+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+88
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+92
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+176
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1082
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1082
	ldr	r3, .L1670+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1083
.L1082:
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1079
	ldr	r3, .L1670+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1083
.L1079:
	ldr	r3, .L1670+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1083
	ldr	r3, .L1670+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1083
	ldr	r3, .L1670+104
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1083
	ldr	r3, .L1670+108
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1083
	ldr	r3, .L1670+112
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1083
	ldr	r3, .L1670+116
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1083
	ldr	r3, .L1670+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1083
	ldr	r3, .L1670+124
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1083:
	ldr	r3, .L1670+128
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+132
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1085
	ldr	r3, .L1670+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1085
	ldr	r3, .L1670+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1085
	ldr	r3, .L1670+144
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+148
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1085
	ldr	r3, .L1670+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1085
	ldr	r3, .L1670+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1085
	ldr	r3, .L1670+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1085
	ldr	r3, .L1670+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1085
	ldr	r3, .L1670+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1085
	ldr	r3, .L1670+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1670+176
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1088
	mov	r3, #0
	mov	r4, r3
.L1088:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1089
.L1085:
	ldr	r3, .L1670+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1089
	ldr	r3, .L1670+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1089
	ldr	r3, .L1673
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1089
	ldr	r3, .L1673+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1089
	ldr	r3, .L1673+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1089
	ldr	r3, .L1673+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1089
	ldr	r3, .L1673+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1089
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1089:
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1091
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1092
.L1091:
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1093
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1092
.L1093:
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1094
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1092
.L1094:
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1092:
	ldr	r3, .L1673+32
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1095
	mov	r3, #0
	mov	r4, r3
.L1095:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1673+36
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1096
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1096
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1096:
	ldr	r3, .L1673+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1097
	ldr	r3, .L1673+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1097
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1673+48
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1673+36
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1097
	ldr	r3, .L1673+52
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1097
	ldr	r3, .L1673+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1100
.L1097:
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1673
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1673+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L1100:
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1102
	ldr	r3, .L1673+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1673+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1673+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1673+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1673+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1673+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1673+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1102
	ldr	r3, .L1673+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1105
.L1102:
	ldr	r3, .L1673+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1673+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1673
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1673+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1673+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1673+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1105
	ldr	r3, .L1673+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1105
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1105:
	ldr	r3, .L1673+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1107
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1107
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1107
	ldr	r3, .L1673+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1107
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1107
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1107
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1107
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1107
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1107
	ldr	r3, .L1673+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1110
.L1107:
	ldr	r3, .L1673+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1110
	ldr	r3, .L1673+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1110
	ldr	r3, .L1673
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1110
	ldr	r3, .L1673+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1110
	ldr	r3, .L1673+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1110
	ldr	r3, .L1673+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1110
	ldr	r3, .L1673+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1110
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1110:
	ldr	r3, .L1673+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+32
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1115
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1115
	ldr	r3, .L1673+36
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1116
.L1115:
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1112
	ldr	r3, .L1673+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1116
.L1112:
	ldr	r3, .L1673+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1116
	ldr	r3, .L1673+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1116
	ldr	r3, .L1673
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1116
	ldr	r3, .L1673+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1116
	ldr	r3, .L1673+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1116
	ldr	r3, .L1673+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1116
	ldr	r3, .L1673+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1116
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1116:
	ldr	r3, .L1673+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+56
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1118
	ldr	r3, .L1673+24
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1118
	ldr	r3, .L1673+28
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1118
	ldr	r3, .L1673+48
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+36
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1118
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1118
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1118
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1118
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1118
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1118
	ldr	r3, .L1673+60
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+32
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1121
	mov	r3, #0
	mov	r4, r3
.L1121:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1122
.L1118:
	ldr	r3, .L1673+40
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1122
	ldr	r3, .L1673+44
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1122
	ldr	r3, .L1673
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1673+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1673+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1673+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1122
	ldr	r3, .L1673+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1122
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1122:
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1124
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1125
.L1124:
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1126
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1125
.L1126:
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1127
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1125
.L1127:
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1125:
	ldr	r3, .L1673+116
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1128
	mov	r3, #0
	mov	r4, r3
.L1128:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1673+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1129
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1129
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
.L1129:
	ldr	r3, .L1673+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1130
	ldr	r3, .L1673+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1130
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1673+104
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1673+108
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1130
	ldr	r3, .L1673+64
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1130
	ldr	r3, .L1673+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1133
.L1130:
	ldr	r3, .L1673+20
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1673
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L1133:
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1135
	ldr	r3, .L1673+108
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1673+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1673+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1673+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1673+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1673+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1673+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1135
	ldr	r3, .L1673+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	b	.L1674
.L1675:
	.align	2
.L1673:
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn1
	.word	turn0
	.word	delta
	.word	_x_p1_l0
	.word	_x_p1_l1
	.word	_x_proposed1
	.word	_x_p1_x
	.word	p1_l0
	.word	p1_l1
	.word	p1_x
	.word	p1_saved_max
	.word	_x_p1_saved_max
	.word	proposed1
	.word	p0_saved_max
	.word	id0
	.word	id1
	.word	id2
	.word	id3
	.word	id4
	.word	max_prop
	.word	_x_p0_saved_max
	.word	_x_p0_l0
	.word	_x_p0_l1
	.word	p0_x
	.word	_x_p0_x
	.word	proposed0
	.word	_x_proposed0
	.word	p0_l0
	.word	p0_l1
	.word	turn4
	.word	turn3
	.word	turn2
	.word	turn0
	.word	turn1
	.word	delta
	.word	_x_id4
	.word	_x_id3
	.word	_x_id2
	.word	_x_id0
	.word	_x_id1
	.word	_x_turn0
	.word	_x_turn4
	.word	_x_turn3
	.word	_x_turn2
	.word	_x_turn1
.L1674:
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1138
.L1135:
	ldr	r3, .L1673+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1673+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1673+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1673+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1673+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1673+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1673+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1138
	ldr	r3, .L1673+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1138:
	ldr	r3, .L1673+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1140
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1140
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1140
	ldr	r3, .L1673+108
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1140
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1140
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1140
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1140
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1140
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1140
	ldr	r3, .L1673+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1143
.L1140:
	ldr	r3, .L1673+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1143
	ldr	r3, .L1673+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1143
	ldr	r3, .L1673+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1143
	ldr	r3, .L1673+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1143
	ldr	r3, .L1673+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1143
	ldr	r3, .L1673+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1143
	ldr	r3, .L1673+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1143
	ldr	r3, .L1673+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1143:
	ldr	r3, .L1673+68
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+72
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+76
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+80
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+84
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+116
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1148
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1148
	ldr	r3, .L1673+108
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1149
.L1148:
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1145
	ldr	r3, .L1673+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+108
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1149
.L1145:
	ldr	r3, .L1673+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1149
	ldr	r3, .L1673+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1149
	ldr	r3, .L1673+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1149
	ldr	r3, .L1673+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1149
	ldr	r3, .L1673+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1149
	ldr	r3, .L1673+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1149
	ldr	r3, .L1673+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1149
	ldr	r3, .L1673+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1149:
	ldr	r3, .L1673+88
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+92
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1151
	ldr	r3, .L1673+96
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1151
	ldr	r3, .L1673+100
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1151
	ldr	r3, .L1673+104
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+108
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L1151
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1151
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1151
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1151
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1151
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1151
	ldr	r3, .L1673+112
	ldr	r3, [r3]	@ float
	ldr	r2, .L1673+116
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r4, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1154
	mov	r3, #0
	mov	r4, r3
.L1154:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	bne	.L1155
.L1151:
	ldr	r3, .L1673+120
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1155
	ldr	r3, .L1673+124
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1155
	ldr	r3, .L1673+128
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1155
	ldr	r3, .L1673+132
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1155
	ldr	r3, .L1673+136
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1155
	ldr	r3, .L1673+140
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1155
	ldr	r3, .L1673+144
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1155
	ldr	r3, .L1673+148
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L302
.L1155:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1157
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1157
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1157
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1157
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1157:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1159
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1159
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1159
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1159
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1159:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1160
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1160
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1160
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1160
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1160:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1161
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1161
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1161
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1161
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1158
.L1161:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1162
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1162
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1162
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1162
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1162:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1163
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1163
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1163:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1164
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1164
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1164
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1164
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1164:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1165
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1165
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1165
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1165
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1158
.L1165:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1166
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1166
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1166
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1166:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1167
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1167
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1167
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1167
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1167:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1168
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1168
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1168
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1168
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1168:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1169
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1169
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1169
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1169
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1158
.L1169:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1170
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1170
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1170:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1171
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1171
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1171
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1171
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1171:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1172
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1172
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1172
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1172
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1172:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1173
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1173
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1173
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1173
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1158
.L1173:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1174
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1174
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1174
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1174:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1175
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1175
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1175
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1175
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1175:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1176
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1176
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1176
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1176
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1176:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1177
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1177
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1177
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1177
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1158
.L1177:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1178
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1178
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1178
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1178
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1178:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1179
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1179
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1179
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1179
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1179:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1180
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1180
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1180
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1180
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1180:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1181
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1181
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1181
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1181
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1158
.L1181:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1182
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1182
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1182
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1182
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1182:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1183
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1183
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1183
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1183
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1158
.L1183:
	ldr	r3, .L1673+152
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+156
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+160
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1673+164
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1673+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L1158:
	ldr	r3, .L1673+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1184
	ldr	r3, .L1673+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1184
	ldr	r3, .L1673+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1184
	ldr	r3, .L1673+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1184
	ldr	r3, .L1673+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1184:
	ldr	r3, .L1673+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1186
	ldr	r3, .L1673+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1186
	ldr	r3, .L1673+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1186
	ldr	r3, .L1673+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1186
	ldr	r3, .L1673+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1186:
	ldr	r3, .L1673+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1187
	ldr	r3, .L1673+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1187
	ldr	r3, .L1673+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1187
	ldr	r3, .L1673+172
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1187
	ldr	r3, .L1673+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1185
.L1187:
	ldr	r3, .L1673+176
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1188
	ldr	r3, .L1673+180
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1188
	ldr	r3, .L1673+184
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1188
	ldr	r3, .L1673+188
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1188
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1188:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1189
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1189
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1189
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1189
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1189:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1190
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1190
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1190
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1190
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1190:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1191
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1191
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1191
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1191
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1185
.L1191:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1192
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1192
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1192
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1192
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1192:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1193
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1193
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1193
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1193
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1193:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1194
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1194
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1194
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1194
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1194:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1195
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1195
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1195
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1195
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1185
.L1195:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1196
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1196
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1196
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1196
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1196:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1197
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1197
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1197
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1197
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1197:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1198
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1198
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1198
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1198
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1198:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1199
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1199
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1199
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1199
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1185
.L1199:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1200
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1200
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1200
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1200
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1200:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1201
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1201
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1201
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1201
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1201:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1202
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1202
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1202
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1202
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1202:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1203
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1203
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1203
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1203
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1185
.L1203:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1204
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1204
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1204
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1204
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1204:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1205
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1205
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1205
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1205
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1205:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1206
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1206
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1206
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1206
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1206:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1207
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1207
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1207
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1207
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1185
.L1207:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1208
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1208
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1208
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1208
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1208:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1209
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1209
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1209
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L1209
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L1185
.L1209:
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	bne	.L302
.L1185:
	ldr	r3, .L1676+288
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1210
	ldr	r3, .L1676+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+472
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+468
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+448
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+444
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+376
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+372
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+336
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+332
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+296
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+292
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+168
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+424
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+16
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+352
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+12
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+312
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+8
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+280
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r2, r3, #255
	ldr	r3, .L1676+4
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	movne	r3, #1
	moveq	r3, #0
	and	r3, r3, #255
	eor	r3, r3, r2
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
.L1210:
	ldr	r3, .L1676+284
	ldr	r3, [r3]	@ float
	mov	r1, #0
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+380
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+340
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+300
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+532
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+564
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+596
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+988
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+1108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+860
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+972
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+404
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+844
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+676
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+716
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+956
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+1092
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+828
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+940
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+508
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+812
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+476
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+492
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+268
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+260
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+380
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+340
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+300
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+532
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+564
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+596
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+988
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+1108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+860
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+972
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+404
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+844
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	b	.L1677
.L1678:
	.align	2
.L1676:
	.word	_x_turn0
	.word	_x_turn4
	.word	_x_turn3
	.word	_x_turn2
	.word	_x_turn1
	.word	_x_p25_l1
	.word	p25_l1
	.word	_x_p25_l0
	.word	p25_l0
	.word	_x_p24_l1
	.word	p24_l1
	.word	_x_p24_l0
	.word	p24_l0
	.word	_x_p23_l1
	.word	p23_l1
	.word	_x_p23_l0
	.word	p23_l0
	.word	_x_p24_saved_max
	.word	p24_saved_max
	.word	_x_p4_l1
	.word	p4_l1
	.word	_x_p9_l0
	.word	p9_l0
	.word	_x_p0_l1
	.word	p0_l1
	.word	_x_p11_saved_max
	.word	p11_saved_max
	.word	_x_p16_x
	.word	p16_x
	.word	_x_p24_x
	.word	p24_x
	.word	_x_p4_l0
	.word	p4_l0
	.word	_x_p0_l0
	.word	p0_l0
	.word	_x_p6_saved_max
	.word	p6_saved_max
	.word	_x_p11_x
	.word	p11_x
	.word	_x_p4_saved_max
	.word	p4_saved_max
	.word	_x_turn0
	.word	turn0
	.word	_x_p9_x
	.word	p9_x
	.word	_x_p23_saved_max
	.word	p23_saved_max
	.word	_x_p3_l1
	.word	p3_l1
	.word	_x_proposed4
	.word	proposed4
	.word	_x_p8_l0
	.word	p8_l0
	.word	_x_p0_saved_max
	.word	p0_saved_max
	.word	_x_p4_x
	.word	p4_x
	.word	_x_p23_x
	.word	p23_x
	.word	_x_p3_l0
	.word	p3_l0
	.word	_x_proposed3
	.word	proposed3
	.word	_x_p0_x
	.word	p0_x
	.word	_x_proposed25
	.word	proposed25
	.word	_x_proposed24
	.word	proposed24
	.word	_x_turn4
	.word	turn4
	.word	_x_delta
	.word	delta
	.word	_x_id4
	.word	id4
	.word	_x_proposed2
	.word	proposed2
	.word	_x_turn3
	.word	turn3
	.word	_x_p19_saved_max
	.word	p19_saved_max
	.word	_x_max_prop
	.word	max_prop
	.word	_x_id3
	.word	id3
	.word	_x_proposed1
	.word	proposed1
	.word	_x_turn2
	.word	turn2
	.word	_x_p14_saved_max
	.word	p14_saved_max
	.word	_x_p19_x
	.word	p19_x
	.word	_x_id2
	.word	id2
	.word	_x_proposed0
	.word	proposed0
	.word	_x_p3_saved_max
	.word	p3_saved_max
	.word	_x_p8_x
	.word	p8_x
	.word	_x_proposed12
	.word	proposed12
	.word	_x_p7_l0
	.word	p7_l0
	.word	_x_turn1
	.word	turn1
	.word	_x_p9_saved_max
	.word	p9_saved_max
	.word	_x_p14_x
	.word	p14_x
	.word	_x_id1
	.word	id1
	.word	_x_inc_max_prop
	.word	inc_max_prop
	.word	_x_p3_x
	.word	p3_x
	.word	_x_id0
	.word	id0
	.word	_x_proposed22
	.word	proposed22
	.word	_x_p2_x
	.word	p2_x
	.word	_x_proposed23
	.word	proposed23
	.word	_x_p2_saved_max
	.word	p2_saved_max
	.word	_x_proposed20
	.word	proposed20
	.word	_x_p7_x
	.word	p7_x
	.word	_x_p6_l0
	.word	p6_l0
	.word	_x_proposed5
	.word	proposed5
	.word	_x_p8_l1
	.word	p8_l1
	.word	_x_p13_l0
	.word	p13_l0
	.word	_x_p22_l0
	.word	p22_l0
	.word	_x_proposed6
	.word	proposed6
	.word	_x_p13_l1
	.word	p13_l1
	.word	_x_p18_l0
	.word	p18_l0
	.word	_x_p22_l1
	.word	p22_l1
	.word	_x_proposed7
	.word	proposed7
	.word	_x_p18_l1
	.word	p18_l1
	.word	_x_p1_x
	.word	p1_x
	.word	_x_p1_saved_max
	.word	p1_saved_max
	.word	_x_p6_x
	.word	p6_x
	.word	_x_p8_saved_max
	.word	p8_saved_max
	.word	_x_p13_x
	.word	p13_x
	.word	_x__diverge_delta
	.word	_diverge_delta
	.word	_x_p22_x
	.word	p22_x
	.word	_x_p2_l0
	.word	p2_l0
	.word	_x_proposed14
	.word	proposed14
	.word	_x_p13_saved_max
	.word	p13_saved_max
	.word	_x_p18_x
	.word	p18_x
	.word	_x_p22_saved_max
	.word	p22_saved_max
	.word	_x_p2_l1
	.word	p2_l1
	.word	_x_proposed15
	.word	proposed15
	.word	_x_p18_saved_max
	.word	p18_saved_max
	.word	_x_p5_x
	.word	p5_x
	.word	_x_p5_saved_max
	.word	p5_saved_max
	.word	_x_p10_x
	.word	p10_x
	.word	_x_p25_x
	.word	p25_x
	.word	_x_p5_l0
	.word	p5_l0
	.word	_x_p25_saved_max
	.word	p25_saved_max
	.word	_x_p5_l1
	.word	p5_l1
	.word	_x_p10_l0
	.word	p10_l0
	.word	_x_p6_l1
	.word	p6_l1
	.word	_x_p11_l0
	.word	p11_l0
	.word	_x_proposed21
	.word	proposed21
	.word	_x_p7_saved_max
	.word	p7_saved_max
	.word	_x_proposed18
	.word	proposed18
	.word	_x_p12_x
	.word	p12_x
	.word	_x_proposed13
	.word	proposed13
	.word	_x_p7_l1
	.word	p7_l1
	.word	_x_proposed10
	.word	proposed10
	.word	_x_p12_l0
	.word	p12_l0
	.word	_x_p9_l1
	.word	p9_l1
	.word	_x_p14_l0
	.word	p14_l0
	.word	_x_p10_saved_max
	.word	p10_saved_max
	.word	_x_p15_x
	.word	p15_x
	.word	_x_p10_l1
	.word	p10_l1
	.word	_x_p15_l0
	.word	p15_l0
	.word	_x_p11_l1
	.word	p11_l1
	.word	_x_p16_l0
	.word	p16_l0
	.word	_x_proposed19
	.word	proposed19
	.word	_x_p12_saved_max
	.word	p12_saved_max
	.word	_x_proposed16
	.word	proposed16
	.word	_x_p17_x
	.word	p17_x
	.word	_x_proposed11
	.word	proposed11
	.word	_x_p12_l1
	.word	p12_l1
	.word	_x_proposed8
	.word	proposed8
	.word	_x_p17_l0
	.word	p17_l0
	.word	_x_p14_l1
	.word	p14_l1
	.word	_x_p19_l0
	.word	p19_l0
	.word	_x_p15_saved_max
	.word	p15_saved_max
	.word	_x_p20_x
	.word	p20_x
	.word	_x_p15_l1
	.word	p15_l1
	.word	_x_p20_l0
	.word	p20_l0
	.word	_x_p16_saved_max
	.word	p16_saved_max
	.word	_x_p1_l0
	.word	p1_l0
	.word	_x_p21_x
	.word	p21_x
	.word	_x_p16_l1
	.word	p16_l1
	.word	_x_p21_l0
	.word	p21_l0
	.word	_x_proposed17
	.word	proposed17
	.word	_x_p17_saved_max
	.word	p17_saved_max
	.word	_x_proposed9
	.word	proposed9
	.word	_x_p17_l1
	.word	p17_l1
	.word	_x_p19_l1
	.word	p19_l1
	.word	_x_p20_saved_max
	.word	p20_saved_max
	.word	_x_p20_l1
	.word	p20_l1
	.word	_x_p1_l1
	.word	p1_l1
	.word	_x_p21_saved_max
	.word	p21_saved_max
	.word	_x_p21_l1
	.word	p21_l1
.L1677:
	bne	.L1238
	ldr	r3, .L1676+676
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+716
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+956
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+1092
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+828
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+940
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+508
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+812
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+476
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+492
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+268
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1238
	ldr	r3, .L1676+260
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
.L1238:
	ldr	r3, .L1676+452
	ldrb	r3, [r3]	@ zero_extendqisi2
	cmp	r3, #0
	moveq	r3, #1
	movne	r3, #0
	and	r4, r3, #255
	ldr	r3, .L1676+328
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+324
	ldr	r2, [r2]	@ float
	mov	r1, #1
	mov	r5, r1
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmple
	mov	r3, r0
	cmp	r3, #0
	bne	.L1240
	mov	r3, #0
	mov	r5, r3
.L1240:
	and	r3, r5, #255
	eor	r3, r3, r4
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
	ldr	r3, .L1676+288
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+652
	ldr	r2, [r2]	@ float
	mov	r1, r2
	mov	r0, r3
	bl	__aeabi_fcmpeq
	mov	r3, r0
	cmp	r3, #0
	bne	.L1241
	ldr	r3, .L1676+656
	ldr	r3, [r3]	@ float
	mov	r2, #1
	mov	r4, r2
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1242
	mov	r3, #0
	mov	r4, r3
.L1242:
	and	r3, r4, #255
	eor	r3, r3, #1
	and	r3, r3, #255
	cmp	r3, #0
	beq	.L302
.L1241:
	ldr	r3, .L1676+656
	ldr	r3, [r3]	@ float
	mov	r1, #1065353216
	mov	r0, r3
	bl	__aeabi_fcmpge
	mov	r3, r0
	cmp	r3, #0
	bne	.L1243
	ldr	r3, .L1676+288
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r4, r0
	mov	r5, r1
	ldr	r3, .L1676+656
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r6, r0
	mov	r7, r1
	ldr	r3, .L1676+652
	ldr	r3, [r3]	@ float
	mov	r0, r3
	bl	__aeabi_f2d
	mov	r2, r0
	mov	r3, r1
	mov	r0, r6
	mov	r1, r7
	bl	__aeabi_dsub
	mov	r2, r0
	mov	r3, r1
	mov	r0, r4
	mov	r1, r5
	bl	__aeabi_dadd
	mov	r2, r0
	mov	r3, r1
	mov	r0, r2
	mov	r1, r3
	mov	r2, #0
	mov	r3, #0
	bl	__aeabi_dcmpeq
	mov	r3, r0
	cmp	r3, #0
	beq	.L302
.L1243:
	mov	r3, #1
	b	.L1245
.L302:
	mov	r3, #0
.L1245:
	str	r3, [fp, #-24]
	ldr	r3, .L1676+20
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+24
	strb	r2, [r3]
	ldr	r3, .L1676+28
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+32
	strb	r2, [r3]
	ldr	r3, .L1676+36
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+40
	strb	r2, [r3]
	ldr	r3, .L1676+44
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+48
	strb	r2, [r3]
	ldr	r3, .L1676+52
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+56
	strb	r2, [r3]
	ldr	r3, .L1676+60
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+64
	strb	r2, [r3]
	ldr	r3, .L1676+68
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+72
	str	r3, [r2]	@ float
	ldr	r3, .L1676+76
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+80
	strb	r2, [r3]
	ldr	r3, .L1676+84
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+88
	strb	r2, [r3]
	ldr	r3, .L1676+92
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+96
	strb	r2, [r3]
	ldr	r3, .L1676+100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+104
	str	r3, [r2]	@ float
	ldr	r3, .L1676+108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+112
	str	r3, [r2]	@ float
	ldr	r3, .L1676+116
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+120
	str	r3, [r2]	@ float
	ldr	r3, .L1676+124
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+128
	strb	r2, [r3]
	ldr	r3, .L1676+132
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+136
	strb	r2, [r3]
	ldr	r3, .L1676+140
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+144
	str	r3, [r2]	@ float
	ldr	r3, .L1676+148
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+152
	str	r3, [r2]	@ float
	ldr	r3, .L1676+156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+160
	str	r3, [r2]	@ float
	ldr	r3, .L1676+164
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+168
	strb	r2, [r3]
	ldr	r3, .L1676+172
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+176
	str	r3, [r2]	@ float
	ldr	r3, .L1676+180
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+184
	str	r3, [r2]	@ float
	ldr	r3, .L1676+188
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+192
	strb	r2, [r3]
	ldr	r3, .L1676+196
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+200
	str	r3, [r2]	@ float
	ldr	r3, .L1676+204
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+208
	strb	r2, [r3]
	ldr	r3, .L1676+212
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+216
	str	r3, [r2]	@ float
	ldr	r3, .L1676+220
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+224
	str	r3, [r2]	@ float
	ldr	r3, .L1676+228
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+232
	str	r3, [r2]	@ float
	ldr	r3, .L1676+236
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+240
	strb	r2, [r3]
	ldr	r3, .L1676+244
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+248
	str	r3, [r2]	@ float
	ldr	r3, .L1676+252
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+256
	str	r3, [r2]	@ float
	ldr	r3, .L1676+260
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+264
	str	r3, [r2]	@ float
	ldr	r3, .L1676+268
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+272
	str	r3, [r2]	@ float
	ldr	r3, .L1676+276
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+280
	strb	r2, [r3]
	ldr	r3, .L1676+284
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+288
	str	r3, [r2]	@ float
	ldr	r3, .L1676+292
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+296
	strb	r2, [r3]
	ldr	r3, .L1676+300
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+304
	str	r3, [r2]	@ float
	ldr	r3, .L1676+308
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+312
	strb	r2, [r3]
	ldr	r3, .L1676+316
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+320
	str	r3, [r2]	@ float
	ldr	r3, .L1676+324
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+328
	str	r3, [r2]	@ float
	ldr	r3, .L1676+332
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+336
	strb	r2, [r3]
	ldr	r3, .L1676+340
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+344
	str	r3, [r2]	@ float
	ldr	r3, .L1676+348
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+352
	strb	r2, [r3]
	ldr	r3, .L1676+356
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+360
	str	r3, [r2]	@ float
	ldr	r3, .L1676+364
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+368
	str	r3, [r2]	@ float
	ldr	r3, .L1676+372
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+376
	strb	r2, [r3]
	ldr	r3, .L1676+380
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+384
	str	r3, [r2]	@ float
	ldr	r3, .L1676+388
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+392
	str	r3, [r2]	@ float
	ldr	r3, .L1676+396
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+400
	str	r3, [r2]	@ float
	ldr	r3, .L1676+404
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+408
	str	r3, [r2]	@ float
	ldr	r3, .L1676+412
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+416
	strb	r2, [r3]
	ldr	r3, .L1676+420
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+424
	strb	r2, [r3]
	ldr	r3, .L1676+428
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+432
	str	r3, [r2]	@ float
	ldr	r3, .L1676+436
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+440
	str	r3, [r2]	@ float
	ldr	r3, .L1676+444
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+448
	strb	r2, [r3]
	ldr	r3, .L1676+452
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+456
	strb	r2, [r3]
	ldr	r3, .L1676+460
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+464
	str	r3, [r2]	@ float
	ldr	r3, .L1676+468
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+472
	strb	r2, [r3]
	ldr	r3, .L1676+476
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+480
	str	r3, [r2]	@ float
	ldr	r3, .L1676+484
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+488
	str	r3, [r2]	@ float
	ldr	r3, .L1676+492
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+496
	str	r3, [r2]	@ float
	ldr	r3, .L1676+500
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+504
	str	r3, [r2]	@ float
	ldr	r3, .L1676+508
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+512
	str	r3, [r2]	@ float
	ldr	r3, .L1676+516
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+520
	str	r3, [r2]	@ float
	ldr	r3, .L1676+524
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+528
	strb	r2, [r3]
	ldr	r3, .L1676+532
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+536
	str	r3, [r2]	@ float
	ldr	r3, .L1676+540
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+544
	strb	r2, [r3]
	ldr	r3, .L1676+548
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+552
	strb	r2, [r3]
	ldr	r3, .L1676+556
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+560
	strb	r2, [r3]
	ldr	r3, .L1676+564
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+568
	str	r3, [r2]	@ float
	ldr	r3, .L1676+572
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+576
	strb	r2, [r3]
	ldr	r3, .L1676+580
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+584
	strb	r2, [r3]
	ldr	r3, .L1676+588
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+592
	strb	r2, [r3]
	ldr	r3, .L1676+596
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+600
	str	r3, [r2]	@ float
	ldr	r3, .L1676+604
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+608
	strb	r2, [r3]
	ldr	r3, .L1676+612
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+616
	str	r3, [r2]	@ float
	ldr	r3, .L1676+620
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+624
	str	r3, [r2]	@ float
	ldr	r3, .L1676+628
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+632
	str	r3, [r2]	@ float
	ldr	r3, .L1676+636
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+640
	str	r3, [r2]	@ float
	ldr	r3, .L1676+644
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+648
	str	r3, [r2]	@ float
	ldr	r3, .L1676+652
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+656
	str	r3, [r2]	@ float
	ldr	r3, .L1676+660
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+664
	str	r3, [r2]	@ float
	ldr	r3, .L1676+668
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+672
	strb	r2, [r3]
	ldr	r3, .L1676+676
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+680
	str	r3, [r2]	@ float
	ldr	r3, .L1676+684
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+688
	str	r3, [r2]	@ float
	ldr	r3, .L1676+692
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+696
	str	r3, [r2]	@ float
	ldr	r3, .L1676+700
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+704
	str	r3, [r2]	@ float
	ldr	r3, .L1676+708
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+712
	strb	r2, [r3]
	ldr	r3, .L1676+716
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+720
	str	r3, [r2]	@ float
	ldr	r3, .L1676+724
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+728
	str	r3, [r2]	@ float
	ldr	r3, .L1676+732
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+736
	str	r3, [r2]	@ float
	ldr	r3, .L1676+740
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+744
	str	r3, [r2]	@ float
	ldr	r3, .L1676+748
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+752
	str	r3, [r2]	@ float
	ldr	r3, .L1676+756
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+760
	str	r3, [r2]	@ float
	ldr	r3, .L1676+764
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+768
	strb	r2, [r3]
	ldr	r3, .L1676+772
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+776
	str	r3, [r2]	@ float
	ldr	r3, .L1676+780
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+784
	strb	r2, [r3]
	ldr	r3, .L1676+788
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+792
	strb	r2, [r3]
	ldr	r3, .L1676+796
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+800
	strb	r2, [r3]
	ldr	r3, .L1676+804
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+808
	strb	r2, [r3]
	ldr	r3, .L1676+812
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+816
	str	r3, [r2]	@ float
	ldr	r3, .L1676+820
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+824
	str	r3, [r2]	@ float
	ldr	r3, .L1676+828
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+832
	str	r3, [r2]	@ float
	ldr	r3, .L1676+836
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+840
	str	r3, [r2]	@ float
	ldr	r3, .L1676+844
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+848
	str	r3, [r2]	@ float
	ldr	r3, .L1676+852
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+856
	strb	r2, [r3]
	ldr	r3, .L1676+860
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+864
	str	r3, [r2]	@ float
	ldr	r3, .L1676+868
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+872
	strb	r2, [r3]
	ldr	r3, .L1676+876
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+880
	strb	r2, [r3]
	ldr	r3, .L1676+884
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+888
	strb	r2, [r3]
	ldr	r3, .L1676+892
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+896
	str	r3, [r2]	@ float
	ldr	r3, .L1676+900
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+904
	str	r3, [r2]	@ float
	ldr	r3, .L1676+908
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+912
	strb	r2, [r3]
	ldr	r3, .L1676+916
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+920
	strb	r2, [r3]
	ldr	r3, .L1676+924
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+928
	strb	r2, [r3]
	ldr	r3, .L1676+932
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+936
	strb	r2, [r3]
	ldr	r3, .L1676+940
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+944
	str	r3, [r2]	@ float
	ldr	r3, .L1676+948
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+952
	str	r3, [r2]	@ float
	ldr	r3, .L1676+956
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+960
	str	r3, [r2]	@ float
	ldr	r3, .L1676+964
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+968
	str	r3, [r2]	@ float
	ldr	r3, .L1676+972
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+976
	str	r3, [r2]	@ float
	ldr	r3, .L1676+980
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+984
	strb	r2, [r3]
	ldr	r3, .L1676+988
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+992
	str	r3, [r2]	@ float
	ldr	r3, .L1676+996
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1000
	strb	r2, [r3]
	ldr	r3, .L1676+1004
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1008
	strb	r2, [r3]
	ldr	r3, .L1676+1012
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1016
	strb	r2, [r3]
	ldr	r3, .L1676+1020
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1024
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1028
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1032
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1036
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1040
	strb	r2, [r3]
	ldr	r3, .L1676+1044
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1048
	strb	r2, [r3]
	ldr	r3, .L1676+1052
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1056
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1060
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1064
	strb	r2, [r3]
	ldr	r3, .L1676+1068
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1072
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1076
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1080
	strb	r2, [r3]
	ldr	r3, .L1676+1084
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1088
	strb	r2, [r3]
	ldr	r3, .L1676+1092
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1096
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1100
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1104
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1108
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1112
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1116
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1120
	strb	r2, [r3]
	ldr	r3, .L1676+1124
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1128
	strb	r2, [r3]
	ldr	r3, .L1676+1132
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1136
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1140
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1144
	strb	r2, [r3]
	ldr	r3, .L1676+1148
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1152
	strb	r2, [r3]
	ldr	r3, .L1676+1156
	ldr	r3, [r3]	@ float
	ldr	r2, .L1676+1160
	str	r3, [r2]	@ float
	ldr	r3, .L1676+1164
	ldrb	r2, [r3]	@ zero_extendqisi2
	ldr	r3, .L1676+1168
	strb	r2, [r3]
.L297:
	ldr	r3, [fp, #-24]
	cmp	r3, #0
	bne	.L1246
	mov	r3, #0
	mov	r0, r3
	sub	sp, fp, #20
	@ sp needed
	pop	{r4, r5, r6, r7, fp, pc}
	.size	main, .-main
	.ident	"GCC: (Ubuntu 9.4.0-1ubuntu1~20.04.2) 9.4.0"
	.section	.note.GNU-stack,"",%progbits
